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eamadio/fpgaMSP430 | fmsp430/misc/fmsp_sync_cell.vhd | 1 | 3,091 | ------------------------------------------------------------------------------
--! Copyright (C) 2009 , Olivier Girard
--
--! Redistribution and use in source and binary forms, with or without
--! modification, are permitted provided that the following conditions
--! are met:
--! * Redistributions of source code must retain the above copyright
--! notice, this list of conditions and the following disclaimer.
--! * Redistributions in binary form must reproduce the above copyright
--! notice, this list of conditions and the following disclaimer in the
--! documentation and/or other materials provided with the distribution.
--! * Neither the name of the authors nor the names of its contributors
--! may be used to endorse or promote products derived from this software
--! without specific prior written permission.
--
--! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
--! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
--! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
--! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
--! OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
--! THE POSSIBILITY OF SUCH DAMAGE
--
------------------------------------------------------------------------------
--
--! @file fmsp_sync_cell.vhd
--!
--! @brief fpgaMSP430 Generic synchronizer
--
--! @author Olivier Girard, [email protected]
--! @author Emmanuel Amadio, [email protected] (VHDL Rewrite)
--
------------------------------------------------------------------------------
--! @version 1
--! @date: 2017-04-21
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all; --! standard unresolved logic UX01ZWLH-
entity fmsp_sync_cell is
generic (
SYNC_EN : boolean := true --! Synchronize input
);
port (
--! INPUTs
clk : in std_logic; --! Receiving clock
rst : in std_logic; --! Receiving reset (active high)
data_in : in std_logic; --! Asynchronous data input
--! OUTPUTs
data_out : out std_logic --! Synchronized data output
);
end entity fmsp_sync_cell;
architecture RTL of fmsp_sync_cell is
signal data_sync : std_logic_vector(1 downto 0);
begin
DATA_SYNC_REG : process(clk,rst)
begin
if (rst = '1') then
data_sync <= "00";
elsif rising_edge(clk) then
data_sync <= data_sync(0) & data_in;
end if;
end process DATA_SYNC_REG;
DATA_MUX : process(data_sync(1),data_in)
begin
if (SYNC_EN = true) then
data_out <= data_sync(1);
else
data_out <= data_in;
end if;
end process DATA_MUX;
end RTL; --! fmsp_sync_cell
| bsd-3-clause | 8ece46ea10616fc84318ca6dc9e1a558 | 0.635717 | 4.009079 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-xilinx-ml510/config.vhd | 2 | 7,874 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := virtex5;
constant CFG_MEMTECH : integer := virtex5;
constant CFG_PADTECH : integer := virtex5;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := virtex5;
constant CFG_CLKMUL : integer := (8);
constant CFG_CLKDIV : integer := (10);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 1;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (2);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 4;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 4;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1 + 1 + 4*1;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2;
constant CFG_ATBSZ : integer := 2;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 1;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#C00#;
constant CFG_AHB_MON : integer := 1;
constant CFG_AHB_MONERR : integer := 1;
constant CFG_AHB_MONWAR : integer := 1;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0034#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000035#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDR2SP : integer := 1;
constant CFG_DDR2SP_INIT : integer := 1;
constant CFG_DDR2SP_FREQ : integer := 100;
constant CFG_DDR2SP_TRFC : integer := (130);
constant CFG_DDR2SP_DATAWIDTH : integer := (64);
constant CFG_DDR2SP_FTEN : integer := 0;
constant CFG_DDR2SP_FTWIDTH : integer := 0;
constant CFG_DDR2SP_COL : integer := (10);
constant CFG_DDR2SP_SIZE : integer := (512);
constant CFG_DDR2SP_DELAY0 : integer := (8);
constant CFG_DDR2SP_DELAY1 : integer := (8);
constant CFG_DDR2SP_DELAY2 : integer := (8);
constant CFG_DDR2SP_DELAY3 : integer := (8);
constant CFG_DDR2SP_DELAY4 : integer := (8);
constant CFG_DDR2SP_DELAY5 : integer := (8);
constant CFG_DDR2SP_DELAY6 : integer := (8);
constant CFG_DDR2SP_DELAY7 : integer := (8);
constant CFG_DDR2SP_NOSYNC : integer := 1;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 64;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0060#;
constant CFG_GRGPIO_WIDTH : integer := (12);
-- I2C master
constant CFG_I2C_ENABLE : integer := 1;
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 1;
constant CFG_SPICTRL_NUM : integer := (1);
constant CFG_SPICTRL_SLVS : integer := (1);
constant CFG_SPICTRL_FIFO : integer := (2);
constant CFG_SPICTRL_SLVREG : integer := 1;
constant CFG_SPICTRL_ODMODE : integer := 0;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 0;
constant CFG_SPICTRL_TWEN : integer := 0;
constant CFG_SPICTRL_MAXWLEN : integer := (0);
constant CFG_SPICTRL_SYNCRAM : integer := 0;
constant CFG_SPICTRL_FT : integer := 0;
-- PCI interface
constant CFG_PCI : integer := 3;
constant CFG_PCIVID : integer := 16#1AC8#;
constant CFG_PCIDID : integer := 16#0054#;
constant CFG_PCIDEPTH : integer := 128;
constant CFG_PCI_MTF : integer := 1;
-- PCI arbiter
constant CFG_PCI_ARB : integer := 1;
constant CFG_PCI_ARBAPB : integer := 1;
constant CFG_PCI_ARB_NGNT : integer := (8);
-- PCI trace buffer
constant CFG_PCITBUFEN: integer := 1;
constant CFG_PCITBUF : integer := 4096;
-- SVGA controller
constant CFG_SVGA_ENABLE : integer := 1;
-- AMBA System ACE Interface Controller
constant CFG_GRACECTRL : integer := 1;
-- AMBA Wrapper for Xilinx System Monitor
constant CFG_GRSYSMON : integer := 0;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-2.0 | c73f328c01ed984b00c590f7be988105 | 0.651003 | 3.561284 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/tech/stratixiii/simprims/stratixiii_atoms.vhd | 2 | 954,499 | -- Copyright (C) 1991-2009 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 9.0 Build 235 03/01/2009
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
package stratixiii_atom_pack is
function str_to_bin (lut_mask : string ) return std_logic_vector;
function product(list : std_logic_vector) return std_logic ;
function alt_conv_integer(arg : in std_logic_vector) return integer;
-- default generic values
CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns);
CONSTANT DefSetupHoldCnst : TIME := 0 ns;
CONSTANT DefPulseWdthCnst : TIME := 0 ns;
-- default control options
-- CONSTANT DefGlitchMode : VitalGlitchKindType := OnEvent;
-- change default delay type to Transport : for spr 68748
CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;
CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;
CONSTANT DefGlitchXOn : BOOLEAN := FALSE;
CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;
CONSTANT DefXOnChecks : BOOLEAN := TRUE;
-- output strength mapping
-- UX01ZWHL-
CONSTANT PullUp : VitalOutputMapType := "UX01HX01X";
CONSTANT NoPullUpZ : VitalOutputMapType := "UX01ZX01X";
CONSTANT PullDown : VitalOutputMapType := "UX01LX01X";
-- primitive result strength mapping
CONSTANT wiredOR : VitalResultMapType := ( 'U', 'X', 'L', '1' );
CONSTANT wiredAND : VitalResultMapType := ( 'U', 'X', '0', 'H' );
CONSTANT L : VitalTableSymbolType := '0';
CONSTANT H : VitalTableSymbolType := '1';
CONSTANT x : VitalTableSymbolType := '-';
CONSTANT S : VitalTableSymbolType := 'S';
CONSTANT R : VitalTableSymbolType := '/';
CONSTANT U : VitalTableSymbolType := 'X';
CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising)
-- Declare array types for CAM_SLICE
TYPE stratixiii_mem_data IS ARRAY (0 to 31) of STD_LOGIC_VECTOR (31 downto 0);
function int2str( value : integer ) return string;
function map_x_to_0 (value : std_logic) return std_logic;
function SelectDelay (CONSTANT Paths: IN VitalPathArray01Type) return TIME;
function int2bit (arg : boolean) return std_logic;
function int2bit (arg : integer) return std_logic;
function bin2int (s : std_logic_vector) return integer;
function bin2int (s : std_logic) return integer;
function int2bin (arg : integer; size : integer) return std_logic_vector;
function int2bin (arg : boolean; size : integer) return std_logic_vector;
function calc_sum_len( widtha : integer; widthb : integer) return integer;
end stratixiii_atom_pack;
library IEEE;
use IEEE.std_logic_1164.all;
package body stratixiii_atom_pack is
type masklength is array (4 downto 1) of std_logic_vector(3 downto 0);
function str_to_bin (lut_mask : string) return std_logic_vector is
variable slice : masklength := (OTHERS => "0000");
variable mask : std_logic_vector(15 downto 0);
begin
for i in 1 to lut_mask'length loop
case lut_mask(i) is
when '0' => slice(i) := "0000";
when '1' => slice(i) := "0001";
when '2' => slice(i) := "0010";
when '3' => slice(i) := "0011";
when '4' => slice(i) := "0100";
when '5' => slice(i) := "0101";
when '6' => slice(i) := "0110";
when '7' => slice(i) := "0111";
when '8' => slice(i) := "1000";
when '9' => slice(i) := "1001";
when 'a' => slice(i) := "1010";
when 'A' => slice(i) := "1010";
when 'b' => slice(i) := "1011";
when 'B' => slice(i) := "1011";
when 'c' => slice(i) := "1100";
when 'C' => slice(i) := "1100";
when 'd' => slice(i) := "1101";
when 'D' => slice(i) := "1101";
when 'e' => slice(i) := "1110";
when 'E' => slice(i) := "1110";
when others => slice(i) := "1111";
end case;
end loop;
mask := (slice(1) & slice(2) & slice(3) & slice(4));
return (mask);
end str_to_bin;
function product (list: std_logic_vector) return std_logic is
begin
for i in 0 to 31 loop
if list(i) = '0' then
return ('0');
end if;
end loop;
return ('1');
end product;
function alt_conv_integer(arg : in std_logic_vector) return integer is
variable result : integer;
begin
result := 0;
for i in arg'range loop
if arg(i) = '1' then
result := result + 2**i;
end if;
end loop;
return result;
end alt_conv_integer;
function int2str( value : integer ) return string is
variable ivalue,index : integer;
variable digit : integer;
variable line_no: string(8 downto 1) := " ";
begin
ivalue := value;
index := 1;
if (ivalue = 0) then
line_no := " 0";
end if;
while (ivalue > 0) loop
digit := ivalue MOD 10;
ivalue := ivalue/10;
case digit is
when 0 =>
line_no(index) := '0';
when 1 =>
line_no(index) := '1';
when 2 =>
line_no(index) := '2';
when 3 =>
line_no(index) := '3';
when 4 =>
line_no(index) := '4';
when 5 =>
line_no(index) := '5';
when 6 =>
line_no(index) := '6';
when 7 =>
line_no(index) := '7';
when 8 =>
line_no(index) := '8';
when 9 =>
line_no(index) := '9';
when others =>
ASSERT FALSE
REPORT "Illegal number!"
SEVERITY ERROR;
end case;
index := index + 1;
end loop;
return line_no;
end;
function map_x_to_0 (value : std_logic) return std_logic is
begin
if (Is_X (value) = TRUE) then
return '0';
else
return value;
end if;
end;
function SelectDelay (CONSTANT Paths : IN VitalPathArray01Type) return TIME IS
variable Temp : TIME;
variable TransitionTime : TIME := TIME'HIGH;
variable PathDelay : TIME := TIME'HIGH;
begin
for i IN Paths'RANGE loop
next when not Paths(i).PathCondition;
next when Paths(i).InputChangeTime > TransitionTime;
Temp := Paths(i).PathDelay(tr01);
if Paths(i).InputChangeTime < TransitionTime then
PathDelay := Temp;
else
if Temp < PathDelay then
PathDelay := Temp;
end if;
end if;
TransitionTime := Paths(i).InputChangeTime;
end loop;
return PathDelay;
end;
function int2bit (arg : integer) return std_logic is
variable int_val : integer := arg;
variable result : std_logic;
begin
if (int_val = 0) then
result := '0';
else
result := '1';
end if;
return result;
end int2bit;
function int2bit (arg : boolean) return std_logic is
variable int_val : boolean := arg;
variable result : std_logic;
begin
if (int_val ) then
result := '1';
else
result := '0';
end if;
return result;
end int2bit;
function bin2int (s : std_logic_vector) return integer is
constant temp : std_logic_vector(s'high-s'low DOWNTO 0) := s;
variable result : integer := 0;
begin
for i in temp'range loop
if (temp(i) = '1') then
result := result + (2**i);
end if;
end loop;
return(result);
end bin2int;
function bin2int (s : std_logic) return integer is
constant temp : std_logic := s;
variable result : integer := 0;
begin
if (temp = '1') then
result := 1;
else
result := 0;
end if;
return(result);
end bin2int;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function int2bin (arg : boolean; size : integer) return std_logic_vector is
variable result : std_logic_vector(size-1 downto 0);
begin
if(arg)then
result := (OTHERS => '1');
else
result := (OTHERS => '0');
end if;
return result;
end int2bin;
function calc_sum_len( widtha : integer; widthb : integer) return integer is
variable result: integer;
begin
if(widtha >= widthb) then
result := widtha + 1;
else
result := widthb + 1;
end if;
return result;
end calc_sum_len;
end stratixiii_atom_pack;
Library ieee;
use ieee.std_logic_1164.all;
Package stratixiii_pllpack is
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer);
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
clk0_used : in string; clk1_used : in string;
clk2_used : in string; clk3_used : in string;
clk4_used : in string; clk5_used : in string;
clk6_used : in string; clk7_used : in string;
clk8_used : in string; clk9_used : in string;
m : out integer;
n : out integer );
function gcd (X: integer; Y: integer) return integer;
function count_digit (X: integer) return integer;
function scale_num (X: integer; Y: integer) return integer;
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer) return integer;
function output_counter_value (clk_divide: integer; clk_mult : integer ;
M: integer; N: integer ) return integer;
function counter_mode (duty_cycle: integer; output_counter_value: integer) return string;
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer;
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer;
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function counter_time_delay ( clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer;
function get_phase_degree (phase_shift: integer; clk_period: integer) return integer;
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer;
function counter_ph (tap_phase: integer; m : integer; n: integer) return integer;
function ph_adjust (tap_phase: integer; ph_base : integer) return integer;
function translate_string (mode : string) return string;
function str2int (s : string) return integer;
function dqs_str2int (s : string) return integer;
end stratixiii_pllpack;
package body stratixiii_pllpack is
-- finds the closest integer fraction of a given pair of numerator and denominator.
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer) is
constant MAX_ITER : integer := 20;
type INT_ARRAY is array ((MAX_ITER-1) downto 0) of integer;
variable quotient_array : INT_ARRAY;
variable int_loop_iter : integer;
variable int_quot : integer;
variable m_value : integer;
variable d_value : integer;
variable old_m_value : integer;
variable swap : integer;
variable loop_iter : integer;
variable num : integer;
variable den : integer;
variable i_max_iter : integer;
begin
loop_iter := 0;
if (numerator = 0) then
num := 1;
else
num := numerator;
end if;
if (denominator = 0) then
den := 1;
else
den := denominator;
end if;
i_max_iter := max_iter;
while (loop_iter < i_max_iter) loop
int_quot := num / den;
quotient_array(loop_iter) := int_quot;
num := num - (den*int_quot);
loop_iter := loop_iter+1;
if ((num = 0) or (max_denom /= -1) or (loop_iter = i_max_iter)) then
-- calculate the numerator and denominator if there is a restriction on the
-- max denom value or if the loop is ending
m_value := 0;
d_value := 1;
-- get the rounded value at this stage for the remaining fraction
if (den /= 0) then
m_value := (2*num/den);
end if;
-- calculate the fraction numerator and denominator at this stage
for int_loop_iter in (loop_iter-1) downto 0 loop
if (m_value = 0) then
m_value := quotient_array(int_loop_iter);
d_value := 1;
else
old_m_value := m_value;
m_value := (quotient_array(int_loop_iter)*m_value) + d_value;
d_value := old_m_value;
end if;
end loop;
-- if the denominator is less than the maximum denom_value or if there is no restriction save it
if ((d_value <= max_denom) or (max_denom = -1)) then
if ((m_value = 0) or (d_value = 0)) then
fraction_num := numerator;
fraction_div := denominator;
else
fraction_num := m_value;
fraction_div := d_value;
end if;
end if;
-- end the loop if the denomitor has overflown or the numerator is zero (no remainder during this round)
if (((d_value > max_denom) and (max_denom /= -1)) or (num = 0)) then
i_max_iter := loop_iter;
end if;
end if;
-- swap the numerator and denominator for the next round
swap := den;
den := num;
num := swap;
end loop;
end find_simple_integer_fraction;
-- find the M and N values for Manual phase based on the following 5 criterias:
-- 1. The PFD frequency (i.e. Fin / N) must be in the range 5 MHz to 720 MHz
-- 2. The VCO frequency (i.e. Fin * M / N) must be in the range 300 MHz to 1300 MHz
-- 3. M is less than 512
-- 4. N is less than 512
-- 5. It's the smallest M/N which satisfies all the above constraints, and is within 2ps
-- of the desired vco-phase-shift-step
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
clk0_used : in string; clk1_used : in string;
clk2_used : in string; clk3_used : in string;
clk4_used : in string; clk5_used : in string;
clk6_used : in string; clk7_used : in string;
clk8_used : in string; clk9_used : in string;
m : out integer;
n : out integer ) is
constant MAX_M : integer := 511;
constant MAX_N : integer := 511;
constant MAX_PFD : integer := 720;
constant MIN_PFD : integer := 5;
constant MAX_VCO : integer := 1300;
constant MIN_VCO : integer := 300;
constant MAX_OFFSET : real := 0.004;
variable vco_period : integer;
variable pfd_freq : integer;
variable vco_freq : integer;
variable vco_ps_step_value : integer;
variable i_m : integer;
variable i_n : integer;
variable i_pre_m : integer;
variable i_pre_n : integer;
variable closest_vco_step_value : integer;
variable i_max_iter : integer;
variable loop_iter : integer;
variable clk0_div_factor_real : real;
variable clk1_div_factor_real : real;
variable clk2_div_factor_real : real;
variable clk3_div_factor_real : real;
variable clk4_div_factor_real : real;
variable clk5_div_factor_real : real;
variable clk6_div_factor_real : real;
variable clk7_div_factor_real : real;
variable clk8_div_factor_real : real;
variable clk9_div_factor_real : real;
variable clk0_div_factor_int : integer;
variable clk1_div_factor_int : integer;
variable clk2_div_factor_int : integer;
variable clk3_div_factor_int : integer;
variable clk4_div_factor_int : integer;
variable clk5_div_factor_int : integer;
variable clk6_div_factor_int : integer;
variable clk7_div_factor_int : integer;
variable clk8_div_factor_int : integer;
variable clk9_div_factor_int : integer;
begin
vco_period := vco_phase_shift_step * 8;
i_pre_m := 0;
i_pre_n := 0;
closest_vco_step_value := 0;
LOOP_1 : for i_n_out in 1 to MAX_N loop
for i_m_out in 1 to MAX_M loop
clk0_div_factor_real := real(clk0_div * i_m_out) / real(clk0_mult * i_n_out);
clk1_div_factor_real := real(clk1_div * i_m_out) / real(clk1_mult * i_n_out);
clk2_div_factor_real := real(clk2_div * i_m_out) / real(clk2_mult * i_n_out);
clk3_div_factor_real := real(clk3_div * i_m_out) / real(clk3_mult * i_n_out);
clk4_div_factor_real := real(clk4_div * i_m_out) / real(clk4_mult * i_n_out);
clk5_div_factor_real := real(clk5_div * i_m_out) / real(clk5_mult * i_n_out);
clk6_div_factor_real := real(clk6_div * i_m_out) / real(clk6_mult * i_n_out);
clk7_div_factor_real := real(clk7_div * i_m_out) / real(clk7_mult * i_n_out);
clk8_div_factor_real := real(clk8_div * i_m_out) / real(clk8_mult * i_n_out);
clk9_div_factor_real := real(clk9_div * i_m_out) / real(clk9_mult * i_n_out);
clk0_div_factor_int := integer(clk0_div_factor_real);
clk1_div_factor_int := integer(clk1_div_factor_real);
clk2_div_factor_int := integer(clk2_div_factor_real);
clk3_div_factor_int := integer(clk3_div_factor_real);
clk4_div_factor_int := integer(clk4_div_factor_real);
clk5_div_factor_int := integer(clk5_div_factor_real);
clk6_div_factor_int := integer(clk6_div_factor_real);
clk7_div_factor_int := integer(clk7_div_factor_real);
clk8_div_factor_int := integer(clk8_div_factor_real);
clk9_div_factor_int := integer(clk9_div_factor_real);
if (((abs(clk0_div_factor_real - real(clk0_div_factor_int)) < MAX_OFFSET) or (clk0_used = "unused")) and
((abs(clk1_div_factor_real - real(clk1_div_factor_int)) < MAX_OFFSET) or (clk1_used = "unused")) and
((abs(clk2_div_factor_real - real(clk2_div_factor_int)) < MAX_OFFSET) or (clk2_used = "unused")) and
((abs(clk3_div_factor_real - real(clk3_div_factor_int)) < MAX_OFFSET) or (clk3_used = "unused")) and
((abs(clk4_div_factor_real - real(clk4_div_factor_int)) < MAX_OFFSET) or (clk4_used = "unused")) and
((abs(clk5_div_factor_real - real(clk5_div_factor_int)) < MAX_OFFSET) or (clk5_used = "unused")) and
((abs(clk6_div_factor_real - real(clk6_div_factor_int)) < MAX_OFFSET) or (clk6_used = "unused")) and
((abs(clk7_div_factor_real - real(clk7_div_factor_int)) < MAX_OFFSET) or (clk7_used = "unused")) and
((abs(clk8_div_factor_real - real(clk8_div_factor_int)) < MAX_OFFSET) or (clk8_used = "unused")) and
((abs(clk9_div_factor_real - real(clk9_div_factor_int)) < MAX_OFFSET) or (clk9_used = "unused")) )
then
if ((i_m_out /= 0) and (i_n_out /= 0))
then
pfd_freq := 1000000 / (inclock_period * i_n_out);
vco_freq := (1000000 * i_m_out) / (inclock_period * i_n_out);
vco_ps_step_value := (inclock_period * i_n_out) / (8 * i_m_out);
if ( (i_m_out < max_m) and (i_n_out < max_n) and (pfd_freq >= min_pfd) and (pfd_freq <= max_pfd) and
(vco_freq >= min_vco) and (vco_freq <= max_vco) )
then
if (abs(vco_ps_step_value - vco_phase_shift_step) <= 2)
then
i_pre_m := i_m_out;
i_pre_n := i_n_out;
exit LOOP_1;
else
if (abs(vco_ps_step_value - vco_phase_shift_step) < abs(closest_vco_step_value - vco_phase_shift_step))
then
i_pre_m := i_m_out;
i_pre_n := i_n_out;
closest_vco_step_value := vco_ps_step_value;
end if;
end if;
end if;
end if;
end if;
end loop;
end loop;
if ((i_pre_m /= 0) and (i_pre_n /= 0))
then
find_simple_integer_fraction(i_pre_m, i_pre_n,
MAX_N, m, n);
else
n := 1;
m := lcm (clk0_mult, clk1_mult, clk2_mult, clk3_mult,
clk4_mult, clk5_mult, clk6_mult,
clk7_mult, clk8_mult, clk9_mult, inclock_period);
end if;
end find_m_and_n_4_manual_phase;
-- find the greatest common denominator of X and Y
function gcd (X: integer; Y: integer) return integer is
variable L, S, R, G : integer := 1;
begin
if (X < Y) then -- find which is smaller.
S := X;
L := Y;
else
S := Y;
L := X;
end if;
R := S;
while ( R > 1) loop
S := L;
L := R;
R := S rem L; -- divide bigger number by smaller.
-- remainder becomes smaller number.
end loop;
if (R = 0) then -- if evenly divisible then L is gcd else it is 1.
G := L;
else
G := R;
end if;
return G;
end gcd;
-- count the number of digits in the given integer
function count_digit (X: integer)
return integer is
variable count, result: integer := 0;
begin
result := X;
while (result /= 0) loop
result := (result / 10);
count := count + 1;
end loop;
return count;
end count_digit;
-- reduce the given huge number to Y significant digits
function scale_num (X: integer; Y: integer)
return integer is
variable count : integer := 0;
variable lc, fac_ten, result: integer := 1;
begin
count := count_digit(X);
for lc in 1 to (count-Y) loop
fac_ten := fac_ten * 10;
end loop;
result := (X / fac_ten);
return result;
end scale_num;
-- find the least common multiple of A1 to A10
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer)
return integer is
variable M1, M2, M3, M4, M5 , M6, M7, M8, M9, R: integer := 1;
begin
M1 := (A1 * A2)/gcd(A1, A2);
M2 := (M1 * A3)/gcd(M1, A3);
M3 := (M2 * A4)/gcd(M2, A4);
M4 := (M3 * A5)/gcd(M3, A5);
M5 := (M4 * A6)/gcd(M4, A6);
M6 := (M5 * A7)/gcd(M5, A7);
M7 := (M6 * A8)/gcd(M6, A8);
M8 := (M7 * A9)/gcd(M7, A9);
M9 := (M8 * A10)/gcd(M8, A10);
if (M9 < 3) then
R := 10;
elsif (M9 = 3) then
R := 9;
elsif ((M9 <= 10) and (M9 > 3)) then
R := 4 * M9;
elsif (M9 > 1000) then
R := scale_num(M9,3);
else
R := M9 ;
end if;
return R;
end lcm;
-- find the factor of division of the output clock frequency compared to the VCO
function output_counter_value (clk_divide: integer; clk_mult: integer ;
M: integer; N: integer ) return integer is
variable r_real : real := 1.0;
variable r: integer := 1;
begin
r_real := real(clk_divide * M)/ real(clk_mult * N);
r := integer(r_real);
return R;
end output_counter_value;
-- find the mode of each PLL counter - bypass, even or odd
function counter_mode (duty_cycle: integer; output_counter_value: integer)
return string is
variable R: string (1 to 6) := " ";
variable counter_value: integer := 1;
begin
counter_value := (2*duty_cycle*output_counter_value)/100;
if output_counter_value = 1 then
R := "bypass";
elsif (counter_value REM 2) = 0 then
R := " even";
else
R := " odd";
end if;
return R;
end counter_mode;
-- find the number of VCO clock cycles to hold the output clock high
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer is
variable R: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value *2)/100 ;
if (half_cycle_high REM 2 = 0) then
R := half_cycle_high/2 ;
else
R := (half_cycle_high/2) + 1;
end if;
return R;
end;
-- find the number of VCO clock cycles to hold the output clock low
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer is
variable R, R1: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value*2)/100 ;
if (half_cycle_high REM 2 = 0) then
R1 := half_cycle_high/2 ;
else
R1 := (half_cycle_high/2) + 1;
end if;
R := output_counter_value - R1;
if (R = 0) then
R := 1;
end if;
return R;
end;
-- find the smallest time delay amongst t1 to t10
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 > 0) then return m9; else return 0; end if;
end;
-- find the numerically largest negative number, and return its absolute value
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 < 0) then return (0 - m9); else return 0; end if;
end;
-- adjust the phase (tap_phase) with the largest negative number (ph_base)
function ph_adjust (tap_phase: integer; ph_base : integer) return integer is
begin
return (tap_phase + ph_base);
end;
-- find the time delay for each PLL counter
function counter_time_delay (clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer is
variable R: integer := 0;
begin
R := clk_time_delay + m_time_delay - n_time_delay;
return R;
end;
-- calculate the given phase shift (in ps) in terms of degrees
function get_phase_degree (phase_shift: integer; clk_period: integer)
return integer is
variable result: integer := 0;
begin
result := ( phase_shift * 360 ) / clk_period;
-- to round up the calculation result
if (result > 0) then
result := result + 1;
elsif (result < 0) then
result := result - 1;
else
result := 0;
end if;
return result;
end;
-- find the number of VCO clock cycles to wait initially before the first rising
-- edge of the output clock
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer is
variable R: integer;
variable R1: real;
begin
R1 := (real(abs(tap_phase)) * real(m))/(360.0 * real(n)) + 0.6;
-- Note NCSim VHDL had problem in rounding up for 0.5 - 0.99.
-- This checking will ensure that the rounding up is done.
if (R1 >= 0.5) and (R1 <= 1.0) then
R1 := 1.0;
end if;
R := integer(R1);
return R;
end;
-- find which VCO phase tap (0 to 7) to align the rising edge of the output clock to
function counter_ph (tap_phase: integer; m: integer; n: integer) return integer is
variable R: integer := 0;
begin
-- 0.5 is added for proper rounding of the tap_phase.
R := integer(real(integer(real(tap_phase * m / n)+ 0.5) REM 360)/45.0) rem 8;
return R;
end;
-- convert given string to length 6 by padding with spaces
function translate_string (mode : string) return string is
variable new_mode : string (1 to 6) := " ";
begin
if (mode = "bypass") then
new_mode := "bypass";
elsif (mode = "even") then
new_mode := " even";
elsif (mode = "odd") then
new_mode := " odd";
end if;
return new_mode;
end;
function str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "i n string parameter! "
SEVERITY ERROR;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
newdigit := newdigit * 10 + digit;
end loop;
return (sign*newdigit);
end;
function dqs_str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
variable err : boolean := false;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & " in string parameter! "
SEVERITY ERROR;
err := true;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
-- set error flag
err := true;
end case;
if (err) then
err := false;
else
newdigit := newdigit * 10 + digit;
end if;
end loop;
return (sign*newdigit);
end;
end stratixiii_pllpack;
--
--
-- DFFE Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
entity stratixiii_dffe is
generic(
TimingChecksOn: Boolean := True;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
port(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC;
CLRN : in STD_LOGIC;
PRN : in STD_LOGIC;
CLK : in STD_LOGIC;
ENA : in STD_LOGIC);
attribute VITAL_LEVEL0 of stratixiii_dffe : entity is TRUE;
end stratixiii_dffe;
-- architecture body --
architecture behave of stratixiii_dffe is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal D_ipd : STD_ULOGIC := 'U';
signal CLRN_ipd : STD_ULOGIC := 'U';
signal PRN_ipd : STD_ULOGIC := 'U';
signal CLK_ipd : STD_ULOGIC := 'U';
signal ENA_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (D_ipd, D, tipd_D);
VitalWireDelay (CLRN_ipd, CLRN, tipd_CLRN);
VitalWireDelay (PRN_ipd, PRN, tipd_PRN);
VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (D_ipd, CLRN_ipd, PRN_ipd, CLK_ipd, ENA_ipd)
-- timing check results
VARIABLE Tviol_D_CLK : STD_ULOGIC := '0';
VARIABLE Tviol_ENA_CLK : STD_ULOGIC := '0';
VARIABLE TimingData_D_CLK : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_ENA_CLK : VitalTimingDataType := VitalTimingDataInit;
-- functionality results
VARIABLE Violation : STD_ULOGIC := '0';
VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 7);
VARIABLE D_delayed : STD_ULOGIC := 'U';
VARIABLE CLK_delayed : STD_ULOGIC := 'U';
VARIABLE ENA_delayed : STD_ULOGIC := 'U';
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => '0');
-- output glitch detection variables
VARIABLE Q_VitalGlitchData : VitalGlitchDataType;
CONSTANT dffe_Q_tab : VitalStateTableType := (
( L, L, x, x, x, x, x, x, x, L ),
( L, H, L, H, H, x, x, H, x, H ),
( L, H, L, H, x, L, x, H, x, H ),
( L, H, L, x, H, H, x, H, x, H ),
( L, H, H, x, x, x, H, x, x, S ),
( L, H, x, x, x, x, L, x, x, H ),
( L, H, x, x, x, x, H, L, x, S ),
( L, x, L, L, L, x, H, H, x, L ),
( L, x, L, L, x, L, H, H, x, L ),
( L, x, L, x, L, H, H, H, x, L ),
( L, x, x, x, x, x, x, x, x, S ));
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_D_CLK,
TimingData => TimingData_D_CLK,
TestSignal => D_ipd,
TestSignalName => "D",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_D_CLK_noedge_posedge,
SetupLow => tsetup_D_CLK_noedge_posedge,
HoldHigh => thold_D_CLK_noedge_posedge,
HoldLow => thold_D_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) OR ( (NOT ENA_ipd) )) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ENA_CLK,
TimingData => TimingData_ENA_CLK,
TestSignal => ENA_ipd,
TestSignalName => "ENA",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ENA_CLK_noedge_posedge,
SetupLow => tsetup_ENA_CLK_noedge_posedge,
HoldHigh => thold_ENA_CLK_noedge_posedge,
HoldLow => thold_ENA_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
-------------------------
-- Functionality Section
-------------------------
Violation := Tviol_D_CLK or Tviol_ENA_CLK;
VitalStateTable(
StateTable => dffe_Q_tab,
DataIn => (
Violation, CLRN_ipd, CLK_delayed, Results(1), D_delayed, ENA_delayed, PRN_ipd, CLK_ipd),
Result => Results,
NumStates => 1,
PreviousDataIn => PrevData_Q);
D_delayed := D_ipd;
CLK_delayed := CLK_ipd;
ENA_delayed := ENA_ipd;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Q,
OutSignalName => "Q",
OutTemp => Results(1),
Paths => ( 0 => (PRN_ipd'last_event, tpd_PRN_Q_negedge, TRUE),
1 => (CLRN_ipd'last_event, tpd_CLRN_Q_negedge, TRUE),
2 => (CLK_ipd'last_event, tpd_CLK_Q_posedge, TRUE)),
GlitchData => Q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--
--
-- stratixiii_mux21 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.stratixiii_atom_pack.all;
entity stratixiii_mux21 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic);
attribute VITAL_LEVEL0 of stratixiii_mux21 : entity is TRUE;
end stratixiii_mux21;
architecture AltVITAL of stratixiii_mux21 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal A_ipd, B_ipd, S_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (A_ipd, A, tipd_A);
VitalWireDelay (B_ipd, B, tipd_B);
VitalWireDelay (S_ipd, S, tipd_S);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (A_ipd, B_ipd, S_ipd)
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if (S_ipd = '1') then
tmp_MO := B_ipd;
else
tmp_MO := A_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (A_ipd'last_event, tpd_A_MO, TRUE),
1 => (B_ipd'last_event, tpd_B_MO, TRUE),
2 => (S_ipd'last_event, tpd_S_MO, TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- stratixiii_mux41 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.stratixiii_atom_pack.all;
entity stratixiii_mux41 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN0_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN1_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN2_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN3_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_IN0 : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01;
tipd_IN2 : VitalDelayType01 := DefPropDelay01;
tipd_IN3 : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01)
);
port (
IN0 : in std_logic := '0';
IN1 : in std_logic := '0';
IN2 : in std_logic := '0';
IN3 : in std_logic := '0';
S : in std_logic_vector(1 downto 0) := (OTHERS => '0');
MO : out std_logic
);
attribute VITAL_LEVEL0 of stratixiii_mux41 : entity is TRUE;
end stratixiii_mux41;
architecture AltVITAL of stratixiii_mux41 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd : std_logic;
signal S_ipd : std_logic_vector(1 downto 0);
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN0_ipd, IN0, tipd_IN0);
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
VitalWireDelay (IN2_ipd, IN2, tipd_IN2);
VitalWireDelay (IN3_ipd, IN3, tipd_IN3);
VitalWireDelay (S_ipd(0), S(0), tipd_S(0));
VitalWireDelay (S_ipd(1), S(1), tipd_S(1));
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd, S_ipd(0), S_ipd(1))
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if ((S_ipd(1) = '1') AND (S_ipd(0) = '1')) then
tmp_MO := IN3_ipd;
elsif ((S_ipd(1) = '1') AND (S_ipd(0) = '0')) then
tmp_MO := IN2_ipd;
elsif ((S_ipd(1) = '0') AND (S_ipd(0) = '1')) then
tmp_MO := IN1_ipd;
else
tmp_MO := IN0_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (IN0_ipd'last_event, tpd_IN0_MO, TRUE),
1 => (IN1_ipd'last_event, tpd_IN1_MO, TRUE),
2 => (IN2_ipd'last_event, tpd_IN2_MO, TRUE),
3 => (IN3_ipd'last_event, tpd_IN3_MO, TRUE),
4 => (S_ipd(0)'last_event, tpd_S_MO(0), TRUE),
5 => (S_ipd(1)'last_event, tpd_S_MO(1), TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- stratixiii_and1 Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.stratixiii_atom_pack.all;
-- entity declaration --
entity stratixiii_and1 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01);
port(
Y : out STD_LOGIC;
IN1 : in STD_LOGIC);
attribute VITAL_LEVEL0 of stratixiii_and1 : entity is TRUE;
end stratixiii_and1;
-- architecture body --
architecture AltVITAL of stratixiii_and1 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
SIGNAL IN1_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN1_ipd)
-- functionality results
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
ALIAS Y_zd : STD_ULOGIC is Results(1);
-- output glitch detection variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
begin
-------------------------
-- Functionality Section
-------------------------
Y_zd := TO_X01(IN1_ipd);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => (0 => (IN1_ipd'last_event, tpd_IN1_Y, TRUE)),
GlitchData => Y_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
-------------------------------------------------------------------
--
-- Entity Name : stratixiii_jtag
--
-- Description : Stratix JTAG VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.stratixiii_atom_pack.all;
entity stratixiii_jtag is
generic (
lpm_type : string := "stratixiii_jtag"
);
port (
tms : in std_logic;
tck : in std_logic;
tdi : in std_logic;
ntrst : in std_logic;
tdoutap : in std_logic;
tdouser : in std_logic;
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
end stratixiii_jtag;
architecture architecture_jtag of stratixiii_jtag is
begin
end architecture_jtag;
-------------------------------------------------------------------
--
-- Entity Name : stratixiii_crcblock
--
-- Description : Stratix CRCBLOCK VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.stratixiii_atom_pack.all;
entity stratixiii_crcblock is
generic (
oscillator_divider : integer := 1;
crc_deld_disable : string := "off";
error_delay : integer := 0 ;
error_dra_dl_bypass : string := "off";
lpm_type : string := "stratixiii_crcblock"
);
port (
clk : in std_logic;
shiftnld : in std_logic;
crcerror : out std_logic;
regout : out std_logic
);
end stratixiii_crcblock;
architecture architecture_crcblock of stratixiii_crcblock is
begin
end architecture_crcblock;
---------------------------------------------------------------------
--
-- Entity Name : stratixiii_lcell_comb
--
-- Description : Stratix III LCELL_COMB VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
entity stratixiii_lcell_comb is
generic (
lut_mask : std_logic_vector(63 downto 0) := (OTHERS => '1');
shared_arith : string := "off";
extended_lut : string := "off";
dont_touch : string := "off";
lpm_type : string := "stratixiii_lcell_comb";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_datae_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_combout : VitalDelayType01 := DefPropDelay01;
tpd_datag_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datab_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datac_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datad_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_sumout : VitalDelayType01 := DefPropDelay01;
tpd_cin_sumout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datab_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datac_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datad_shareout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_datae : VitalDelayType01 := DefPropDelay01;
tipd_dataf : VitalDelayType01 := DefPropDelay01;
tipd_datag : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01;
tipd_sharein : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic := '0';
datab : in std_logic := '0';
datac : in std_logic := '0';
datad : in std_logic := '0';
datae : in std_logic := '0';
dataf : in std_logic := '0';
datag : in std_logic := '0';
cin : in std_logic := '0';
sharein : in std_logic := '0';
combout : out std_logic;
sumout : out std_logic;
cout : out std_logic;
shareout : out std_logic
);
attribute VITAL_LEVEL0 of stratixiii_lcell_comb : entity is TRUE;
end stratixiii_lcell_comb;
architecture vital_lcell_comb of stratixiii_lcell_comb is
attribute VITAL_LEVEL0 of vital_lcell_comb : architecture is TRUE;
signal dataa_ipd : std_logic;
signal datab_ipd : std_logic;
signal datac_ipd : std_logic;
signal datad_ipd : std_logic;
signal datae_ipd : std_logic;
signal dataf_ipd : std_logic;
signal datag_ipd : std_logic;
signal cin_ipd : std_logic;
signal sharein_ipd : std_logic;
signal f2_input3 : std_logic;
-- sub masks
signal f0_mask : std_logic_vector(15 downto 0);
signal f1_mask : std_logic_vector(15 downto 0);
signal f2_mask : std_logic_vector(15 downto 0);
signal f3_mask : std_logic_vector(15 downto 0);
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (dataa_ipd, dataa, tipd_dataa);
VitalWireDelay (datab_ipd, datab, tipd_datab);
VitalWireDelay (datac_ipd, datac, tipd_datac);
VitalWireDelay (datad_ipd, datad, tipd_datad);
VitalWireDelay (datae_ipd, datae, tipd_datae);
VitalWireDelay (dataf_ipd, dataf, tipd_dataf);
VitalWireDelay (datag_ipd, datag, tipd_datag);
VitalWireDelay (cin_ipd, cin, tipd_cin);
VitalWireDelay (sharein_ipd, sharein, tipd_sharein);
end block;
f0_mask <= lut_mask(15 downto 0);
f1_mask <= lut_mask(31 downto 16);
f2_mask <= lut_mask(47 downto 32);
f3_mask <= lut_mask(63 downto 48);
f2_input3 <= datag_ipd WHEN (extended_lut = "on") ELSE datac_ipd;
VITALtiming : process(dataa_ipd, datab_ipd, datac_ipd, datad_ipd,
datae_ipd, dataf_ipd, f2_input3, cin_ipd,
sharein_ipd)
variable combout_VitalGlitchData : VitalGlitchDataType;
variable sumout_VitalGlitchData : VitalGlitchDataType;
variable cout_VitalGlitchData : VitalGlitchDataType;
variable shareout_VitalGlitchData : VitalGlitchDataType;
-- sub lut outputs
variable f0_out : std_logic;
variable f1_out : std_logic;
variable f2_out : std_logic;
variable f3_out : std_logic;
-- muxed output
variable g0_out : std_logic;
variable g1_out : std_logic;
-- internal variables
variable f2_f : std_logic;
variable adder_input2 : std_logic;
-- output variables
variable combout_tmp : std_logic;
variable sumout_tmp : std_logic;
variable cout_tmp : std_logic;
-- temp variable for NCVHDL
variable lut_mask_var : std_logic_vector(63 downto 0) := (OTHERS => '1');
begin
lut_mask_var := lut_mask;
------------------------
-- Timing Check Section
------------------------
f0_out := VitalMUX(data => f0_mask,
dselect => (datad_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
f1_out := VitalMUX(data => f1_mask,
dselect => (datad_ipd,
f2_input3,
datab_ipd,
dataa_ipd));
f2_out := VitalMUX(data => f2_mask,
dselect => (datad_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
f3_out := VitalMUX(data => f3_mask,
dselect => (datad_ipd,
f2_input3,
datab_ipd,
dataa_ipd));
-- combout
if (extended_lut = "on") then
if (datae_ipd = '0') then
g0_out := f0_out;
g1_out := f2_out;
elsif (datae_ipd = '1') then
g0_out := f1_out;
g1_out := f3_out;
else
g0_out := 'X';
g1_out := 'X';
end if;
if (dataf_ipd = '0') then
combout_tmp := g0_out;
elsif ((dataf_ipd = '1') or (g0_out = g1_out))then
combout_tmp := g1_out;
else
combout_tmp := 'X';
end if;
else
combout_tmp := VitalMUX(data => lut_mask_var,
dselect => (dataf_ipd,
datae_ipd,
datad_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
end if;
-- sumout and cout
f2_f := VitalMUX(data => f2_mask,
dselect => (dataf_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
if (shared_arith = "on") then
adder_input2 := sharein_ipd;
else
adder_input2 := NOT f2_f;
end if;
sumout_tmp := cin_ipd XOR f0_out XOR adder_input2;
cout_tmp := (cin_ipd AND f0_out) OR (cin_ipd AND adder_input2) OR
(f0_out AND adder_input2);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => combout,
OutSignalName => "COMBOUT",
OutTemp => combout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_combout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_combout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_combout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_combout, TRUE),
4 => (datae_ipd'last_event, tpd_datae_combout, TRUE),
5 => (dataf_ipd'last_event, tpd_dataf_combout, TRUE),
6 => (datag_ipd'last_event, tpd_datag_combout, TRUE)),
GlitchData => combout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => sumout,
OutSignalName => "SUMOUT",
OutTemp => sumout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_sumout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_sumout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_sumout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_sumout, TRUE),
4 => (dataf_ipd'last_event, tpd_dataf_sumout, TRUE),
5 => (cin_ipd'last_event, tpd_cin_sumout, TRUE),
6 => (sharein_ipd'last_event, tpd_sharein_sumout, TRUE)),
GlitchData => sumout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => cout,
OutSignalName => "COUT",
OutTemp => cout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_cout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_cout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_cout, TRUE),
4 => (dataf_ipd'last_event, tpd_dataf_cout, TRUE),
5 => (cin_ipd'last_event, tpd_cin_cout, TRUE),
6 => (sharein_ipd'last_event, tpd_sharein_cout, TRUE)),
GlitchData => cout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => shareout,
OutSignalName => "SHAREOUT",
OutTemp => f2_out,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_shareout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_shareout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_shareout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_shareout, TRUE)),
GlitchData => shareout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_lcell_comb;
---------------------------------------------------------------------
--
-- Entity Name : stratixiii_routing_wire
--
-- Description : Stratix III Routing Wire VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_routing_wire is
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
attribute VITAL_LEVEL0 of stratixiii_routing_wire : entity is TRUE;
end stratixiii_routing_wire;
ARCHITECTURE behave of stratixiii_routing_wire is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal datain_ipd : std_logic;
signal datainglitch_inert : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process(datain_ipd, datainglitch_inert)
variable datain_inert_VitalGlitchData : VitalGlitchDataType;
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => datainglitch_inert,
OutSignalName => "datainglitch_inert",
OutTemp => datain_ipd,
Paths => (1 => (datain_ipd'last_event, tpd_datainglitch_dataout, TRUE)),
GlitchData => datain_inert_VitalGlitchData,
Mode => VitalInertial,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "dataout",
OutTemp => datainglitch_inert,
Paths => (1 => (datain_ipd'last_event, tpd_datain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : stratixiii_lvds_tx_reg
--
-- Description : Simulation model for a simple DFF.
-- This is used for registering the enable inputs.
-- No timing, powers upto 0.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiii_atom_pack.all;
ENTITY stratixiii_lvds_tx_reg is
GENERIC ( MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := True;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_d : VitalDelayType01 := DefpropDelay01;
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( q : OUT std_logic;
clk : IN std_logic;
ena : IN std_logic;
d : IN std_logic;
clrn : IN std_logic;
prn : IN std_logic
);
attribute VITAL_LEVEL0 of stratixiii_lvds_tx_reg : ENTITY is TRUE;
END stratixiii_lvds_tx_reg;
ARCHITECTURE vital_titan_lvds_tx_reg of stratixiii_lvds_tx_reg is
attribute VITAL_LEVEL0 of vital_titan_lvds_tx_reg : architecture is TRUE;
-- INTERNAL SIGNALS
signal clk_ipd : std_logic;
signal d_ipd : std_logic;
signal ena_ipd : std_logic;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (d_ipd, d, tipd_d);
end block;
process (clk_ipd, clrn, prn)
variable q_tmp : std_logic := '0';
variable q_VitalGlitchData : VitalGlitchDataType;
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d_ipd,
TestSignalName => "d",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT ena_ipd) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/stratixiii_lvds_tx_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (prn = '0') then
q_tmp := '1';
elsif (clrn = '0') then
q_tmp := '0';
elsif (clk_ipd'event and clk_ipd = '1') then
if (ena_ipd = '1') then
q_tmp := d_ipd;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_tmp,
Paths => (1 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_titan_lvds_tx_reg;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity name : stratixiii_lvds_tx_parallel_register
--
-- Description : Register for the 10 data input channels of the Stratix III
-- LVDS Tx
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiii_atom_pack.all;
USE std.textio.all;
ENTITY stratixiii_lvds_tx_parallel_register is
GENERIC ( channel_width : integer := 10;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_enable : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01)
);
PORT ( clk : in std_logic;
enable : in std_logic;
datain : in std_logic_vector(channel_width - 1 downto 0);
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector(channel_width - 1 downto 0)
);
END stratixiii_lvds_tx_parallel_register;
ARCHITECTURE vital_tx_reg of stratixiii_lvds_tx_parallel_register is
signal clk_ipd : std_logic;
signal enable_ipd : std_logic;
signal datain_ipd : std_logic_vector(channel_width - 1 downto 0);
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (enable_ipd, enable, tipd_enable);
loopbits : FOR i in datain'RANGE GENERATE
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
END GENERATE;
end block;
VITAL: process (clk_ipd, enable_ipd, datain_ipd, devpor, devclrn)
variable Tviol_datain_clk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(9 downto 0);
variable i : integer := 0;
variable dataout_tmp : std_logic_vector(channel_width - 1 downto 0);
variable CQDelay : TIME := 0 ns;
begin
if (now = 0 ns) then
dataout_tmp := (OTHERS => '0');
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_datain_clk,
TimingData => TimingData_datain_clk,
TestSignal => datain_ipd,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/stratixiii_lvds_tx_parallel_register",
XOn => XOn,
MsgOn => MsgOnChecks );
end if;
if ((devpor = '0') or (devclrn = '0')) then
dataout_tmp := (OTHERS => '0');
else
if (clk_ipd'event and clk_ipd = '1') then
if (enable_ipd = '1') then
dataout_tmp := datain_ipd;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
CQDelay := SelectDelay(
(1 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE))
);
dataout <= TRANSPORT dataout_tmp AFTER CQDelay;
end process;
end vital_tx_reg;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity name : stratixiii_lvds_tx_out_block
--
-- Description : Negative-edge triggered register on the Tx output.
-- Also, optionally generates an identical/inverted output clock
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiii_atom_pack.all;
USE std.textio.all;
ENTITY stratixiii_lvds_tx_out_block is
GENERIC ( bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_negedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01
);
PORT ( clk : in std_logic;
datain : in std_logic;
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic
);
END stratixiii_lvds_tx_out_block;
ARCHITECTURE vital_tx_out_block of stratixiii_lvds_tx_out_block is
signal clk_ipd : std_logic;
signal datain_ipd : std_logic;
signal inv_clk : integer;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process (clk_ipd, datain_ipd, devpor, devclrn)
variable dataout_VitalGlitchData : VitalGlitchDataType;
variable dataout_tmp : std_logic;
begin
if (now = 0 ns) then
dataout_tmp := '0';
else
if (bypass_serializer = "false") then
if (use_falling_clock_edge = "false") then
dataout_tmp := datain_ipd;
end if;
if (clk_ipd'event and clk_ipd = '0') then
if (use_falling_clock_edge = "true") then
dataout_tmp := datain_ipd;
end if;
end if;
else
if (invert_clock = "false") then
dataout_tmp := clk_ipd;
else
dataout_tmp := NOT (clk_ipd);
end if;
if (invert_clock = "false") then
inv_clk <= 0;
else
inv_clk <= 1;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
if (bypass_serializer = "false") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (0 => (datain_ipd'last_event, tpd_datain_dataout, TRUE),
1 => (clk_ipd'last_event, tpd_clk_dataout_negedge, use_falling_clock_edge = "true")),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end if;
if (bypass_serializer = "true") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (1 => (clk_ipd'last_event, tpd_clk_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end if;
end process;
end vital_tx_out_block;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity name : stratixiii_lvds_transmitter
--
-- Description : Timing simulation model for the Stratix III LVDS Tx WYSIWYG.
-- It instantiates the following sub-modules :
-- 1) primitive DFFE
-- 2) Stratix III_lvds_tx_parallel_register and
-- 3) Stratix III_lvds_tx_out_block
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiii_atom_pack.all;
USE std.textio.all;
USE work.stratixiii_lvds_tx_parallel_register;
USE work.stratixiii_lvds_tx_out_block;
USE work.stratixiii_lvds_tx_reg;
ENTITY stratixiii_lvds_transmitter is
GENERIC ( channel_width : integer := 10;
bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
use_serial_data_input : String := "false";
use_post_dpa_serial_data_input : String := "false";
is_used_as_outclk : String := "false";
tx_output_path_delay_engineering_bits : Integer := -1;
enable_dpaclk_to_lvdsout : string := "off";
preemphasis_setting : integer := 0;
vod_setting : integer := 0;
differential_drive : integer := 0;
lpm_type : string := "stratixiii_lvds_transmitter";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk0_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk0_dataout_negedge : VitalDelayType01 := DefPropDelay01;
tpd_serialdatain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_dpaclkin_dataout : VitalDelayType01 := DefPropDelay01;
tpd_postdpaserialdatain_dataout : VitalDelayType01 := DefPropDelay01;
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01);
tipd_serialdatain : VitalDelayType01 := DefpropDelay01;
tipd_dpaclkin : VitalDelayType01 := DefpropDelay01;
tipd_postdpaserialdatain : VitalDelayType01 := DefpropDelay01
);
PORT ( clk0 : in std_logic;
enable0 : in std_logic;
datain : in std_logic_vector(channel_width - 1 downto 0);
serialdatain : in std_logic := '0';
postdpaserialdatain : in std_logic := '0';
dpaclkin : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic;
serialfdbkout : out std_logic
);
end stratixiii_lvds_transmitter;
ARCHITECTURE vital_transmitter_atom of stratixiii_lvds_transmitter is
signal clk0_ipd : std_logic;
signal serialdatain_ipd : std_logic;
signal postdpaserialdatain_ipd : std_logic;
signal dpaclkin_ipd : std_logic;
signal input_data : std_logic_vector(channel_width - 1 downto 0);
signal txload0 : std_logic;
signal shift_out : std_logic;
signal clk0_dly0 : std_logic;
signal clk0_dly1 : std_logic;
signal clk0_dly2 : std_logic;
signal datain_dly : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly1 : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly2 : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly3 : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly4 : std_logic_vector(channel_width - 1 downto 0);
signal vcc : std_logic := '1';
signal tmp_dataout : std_logic;
COMPONENT stratixiii_lvds_tx_parallel_register
GENERIC ( channel_width : integer := 10;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_enable : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01)
);
PORT ( clk : in std_logic;
enable : in std_logic;
datain : in std_logic_vector(channel_width - 1 downto 0);
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector(channel_width - 1 downto 0)
);
END COMPONENT;
COMPONENT stratixiii_lvds_tx_out_block
GENERIC ( bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_negedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01
);
PORT ( clk : in std_logic;
datain : in std_logic;
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic
);
END COMPONENT;
COMPONENT stratixiii_lvds_tx_reg
GENERIC (TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01
);
PORT ( q : out STD_LOGIC := '0';
d : in STD_LOGIC := '1';
clrn : in STD_LOGIC := '1';
prn : in STD_LOGIC := '1';
clk : in STD_LOGIC := '0';
ena : in STD_LOGIC := '1'
);
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk0_ipd, clk0, tipd_clk0);
VitalWireDelay (serialdatain_ipd, serialdatain, tipd_serialdatain);
VitalWireDelay (dpaclkin_ipd, dpaclkin, tipd_dpaclkin);
VitalWireDelay (postdpaserialdatain_ipd, postdpaserialdatain, tipd_postdpaserialdatain);
end block;
txload0_reg: stratixiii_lvds_tx_reg
PORT MAP (d => enable0,
clrn => vcc,
prn => vcc,
ena => vcc,
clk => clk0_dly2,
q => txload0
);
input_reg: stratixiii_lvds_tx_parallel_register
GENERIC MAP ( channel_width => channel_width)
PORT MAP ( clk => txload0,
enable => vcc,
datain => datain_dly,
dataout => input_data,
devclrn => devclrn,
devpor => devpor
);
output_module: stratixiii_lvds_tx_out_block
GENERIC MAP ( bypass_serializer => bypass_serializer,
use_falling_clock_edge => use_falling_clock_edge,
invert_clock => invert_clock)
PORT MAP ( clk => clk0_dly2,
datain => shift_out,
dataout => tmp_dataout,
devclrn => devclrn,
devpor => devpor
);
clk_delay: process (clk0_ipd, datain)
begin
clk0_dly0 <= clk0_ipd;
datain_dly1 <= datain;
end process;
clk_delay1: process (clk0_dly0, datain_dly1)
begin
clk0_dly1 <= clk0_dly0;
datain_dly2 <= datain_dly1;
end process;
clk_delay2: process (clk0_dly1, datain_dly2)
begin
clk0_dly2 <= clk0_dly1;
datain_dly3 <= datain_dly2;
end process;
data_delay: process (datain_dly3)
begin
datain_dly4 <= datain_dly3;
end process;
data_delay1: process (datain_dly4)
begin
datain_dly <= datain_dly4;
end process;
VITAL: process (clk0_ipd, devclrn, devpor)
variable dataout_VitalGlitchData : VitalGlitchDataType;
variable i : integer := 0;
variable shift_data : std_logic_vector(channel_width-1 downto 0);
begin
if (now = 0 ns) then
shift_data := (OTHERS => '0');
end if;
if ((devpor = '0') or (devclrn = '0')) then
shift_data := (OTHERS => '0');
else
if (bypass_serializer = "false") then
if (clk0_ipd'event and clk0_ipd = '1') then
if (txload0 = '1') then
shift_data := input_data;
end if;
shift_out <= shift_data(channel_width - 1);
for i in channel_width-1 downto 1 loop
shift_data(i) := shift_data(i - 1);
end loop;
end if;
end if;
end if;
end process;
process (serialdatain_ipd,
postdpaserialdatain_ipd,
dpaclkin_ipd,
tmp_dataout
)
variable dataout_tmp : std_logic := '0';
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
if (serialdatain_ipd'event and use_serial_data_input = "true") then
dataout_tmp := serialdatain_ipd;
elsif (postdpaserialdatain_ipd'event and use_post_dpa_serial_data_input = "true") then
dataout_tmp := postdpaserialdatain_ipd;
elsif (dpaclkin_ipd'event and enable_dpaclk_to_lvdsout = "on") then
dataout_tmp := dpaclkin_ipd;
else
dataout_tmp := tmp_dataout;
end if;
----------------------
-- Path Delay Section
----------------------
if (use_serial_data_input = "true") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (0 => (serialdatain_ipd'last_event, tpd_serialdatain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
elsif (use_post_dpa_serial_data_input = "true") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (0 => (postdpaserialdatain_ipd'last_event, tpd_postdpaserialdatain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
elsif (enable_dpaclk_to_lvdsout = "on") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (0 => (dpaclkin_ipd'last_event, tpd_dpaclkin_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
else
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (0 => (tmp_dataout'last_event, DefPropDelay01, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end if;
end process;
end vital_transmitter_atom;
--
--
-- STRATIXIII_RUBLOCK Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.stratixiii_atom_pack.all;
entity stratixiii_rublock is
generic
(
sim_init_config : string := "factory";
sim_init_watchdog_value : integer := 0;
sim_init_status : integer := 0;
lpm_type : string := "stratixiii_rublock"
);
port
(
clk : in std_logic;
shiftnld : in std_logic;
captnupdt : in std_logic;
regin : in std_logic;
rsttimer : in std_logic;
rconfig : in std_logic;
regout : out std_logic
);
end stratixiii_rublock;
architecture architecture_rublock of stratixiii_rublock is
begin
end architecture_rublock;
----------------------------------------------------------------------------
-- Module Name : stratixiii_ram_register
-- Description : Register module for RAM inputs/outputs
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiii_atom_pack.all;
ENTITY stratixiii_ram_register IS
GENERIC (
width : INTEGER := 1;
preset : STD_LOGIC := '0';
tipd_d : VitalDelayArrayType01(143 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_stall : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpw_ena_posedge : VitalDelayType := DefPulseWdthCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_stall_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_stall_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
stall : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END stratixiii_ram_register;
ARCHITECTURE reg_arch OF stratixiii_ram_register IS
SIGNAL d_ipd : STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
SIGNAL clk_ipd : STD_LOGIC;
SIGNAL ena_ipd : STD_LOGIC;
SIGNAL aclr_ipd : STD_LOGIC;
SIGNAL stall_ipd : STD_LOGIC;
BEGIN
WireDelay : BLOCK
BEGIN
loopbits : FOR i in d'RANGE GENERATE
VitalWireDelay (d_ipd(i), d(i), tipd_d(i));
END GENERATE;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (stall_ipd, stall, tipd_stall);
END BLOCK;
-- REMTITAN PROCESS (d_ipd,ena_ipd,clk_ipd,aclr_ipd,devclrn,devpor)
PROCESS (d_ipd,ena_ipd,stall_ipd,clk_ipd,aclr_ipd,devclrn,devpor)
VARIABLE Tviol_clk_ena : STD_ULOGIC := '0';
VARIABLE Tviol_clk_aclr : STD_ULOGIC := '0';
VARIABLE Tviol_data_clk : STD_ULOGIC := '0';
VARIABLE TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_stall : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_aclr : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit;
VARIABLE Tviol_ena : STD_ULOGIC := '0';
VARIABLE PeriodData_ena : VitalPeriodDataType := VitalPeriodDataInit;
VARIABLE q_VitalGlitchDataArray : VitalGlitchDataArrayType(143 downto 0);
VARIABLE CQDelay : TIME := 0 ns;
VARIABLE q_reg : STD_LOGIC_VECTOR(width - 1 DOWNTO 0) := (OTHERS => preset);
BEGIN
IF (aclr_ipd = '1' OR devclrn = '0' OR devpor = '0') THEN
q_reg := (OTHERS => preset);
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1' AND stall_ipd = '0') THEN
q_reg := d_ipd;
END IF;
-- Timing checks
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_stall,
TestSignal => stall_ipd,
TestSignalName => "stall",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_stall_clk_noedge_posedge,
SetupLow => tsetup_stall_clk_noedge_posedge,
HoldHigh => thold_stall_clk_noedge_posedge,
HoldLow => thold_stall_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_aclr,
TimingData => TimingData_clk_aclr,
TestSignal => aclr_ipd,
TestSignalName => "aclr",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_aclr_clk_noedge_posedge,
SetupLow => tsetup_aclr_clk_noedge_posedge,
HoldHigh => thold_aclr_clk_noedge_posedge,
HoldLow => thold_aclr_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_data_clk,
TimingData => TimingData_data_clk,
TestSignal => d_ipd,
TestSignalName => "data",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalPeriodPulseCheck (
Violation => Tviol_ena,
PeriodData => PeriodData_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
PulseWidthHigh => tpw_ena_posedge,
HeaderMsg => "/RAM Register VitalPeriodPulseCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
-- Path Delay Selection
CQDelay := SelectDelay (
Paths => (
(0 => (clk_ipd'LAST_EVENT,tpd_clk_q_posedge,TRUE),
1 => (aclr_ipd'LAST_EVENT,tpd_aclr_q_posedge,TRUE))
)
);
q <= TRANSPORT q_reg AFTER CQDelay;
END PROCESS;
aclrout <= aclr_ipd;
END reg_arch;
----------------------------------------------------------------------------
-- Module Name : stratixiii_ram_pulse_generator
-- Description : Generate pulse to initiate memory read/write operations
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiii_atom_pack.all;
ENTITY stratixiii_ram_pulse_generator IS
GENERIC (
tipd_clk : VitalDelayType01 := (0.5 ns,0.5 ns);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tpd_clk_pulse_posedge : VitalDelayType01 := DefPropDelay01
);
PORT (
clk,ena : IN STD_LOGIC;
delaywrite : IN STD_LOGIC := '0';
pulse,cycle : OUT STD_LOGIC
);
ATTRIBUTE VITAL_Level0 OF stratixiii_ram_pulse_generator:ENTITY IS TRUE;
END stratixiii_ram_pulse_generator;
ARCHITECTURE pgen_arch OF stratixiii_ram_pulse_generator IS
SIGNAL clk_ipd,ena_ipd : STD_LOGIC;
SIGNAL state : STD_LOGIC;
ATTRIBUTE VITAL_Level0 OF pgen_arch:ARCHITECTURE IS TRUE;
BEGIN
WireDelay : BLOCK
BEGIN
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
END BLOCK;
PROCESS (clk_ipd,state)
BEGIN
IF (state = '1' AND state'EVENT) THEN
state <= '0';
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1') THEN
IF (delaywrite = '1') THEN
state <= '1' AFTER 1 NS; -- delayed write
ELSE
state <= '1';
END IF;
END IF;
END PROCESS;
PathDelay : PROCESS
VARIABLE pulse_VitalGlitchData : VitalGlitchDataType;
BEGIN
WAIT UNTIL state'EVENT;
VitalPathDelay01 (
OutSignal => pulse,
OutSignalName => "pulse",
OutTemp => state,
Paths => (0 => (clk_ipd'LAST_EVENT,tpd_clk_pulse_posedge,TRUE)),
GlitchData => pulse_VitalGlitchData,
Mode => DefGlitchMode,
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks
);
END PROCESS;
cycle <= clk_ipd;
END pgen_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiii_atom_pack.all;
USE work.stratixiii_ram_register;
USE work.stratixiii_ram_pulse_generator;
ENTITY stratixiii_ram_block IS
GENERIC (
-- -------- GLOBAL PARAMETERS ---------
operation_mode : STRING := "single_port";
mixed_port_feed_through_mode : STRING := "dont_care";
ram_block_type : STRING := "auto";
logical_ram_name : STRING := "ram_name";
init_file : STRING := "init_file.hex";
init_file_layout : STRING := "none";
enable_ecc : STRING := "false";
data_interleave_width_in_bits : INTEGER := 1;
data_interleave_offset_in_bits : INTEGER := 1;
port_a_logical_ram_depth : INTEGER := 0;
port_a_logical_ram_width : INTEGER := 0;
port_a_first_address : INTEGER := 0;
port_a_last_address : INTEGER := 0;
port_a_first_bit_number : INTEGER := 0;
port_a_address_clear : STRING := "none";
port_a_data_out_clear : STRING := "none";
port_a_data_in_clock : STRING := "clock0";
port_a_address_clock : STRING := "clock0";
port_a_write_enable_clock : STRING := "clock0";
port_a_read_enable_clock : STRING := "clock0";
port_a_byte_enable_clock : STRING := "clock0";
port_a_data_out_clock : STRING := "none";
port_a_data_width : INTEGER := 1;
port_a_address_width : INTEGER := 1;
port_a_byte_enable_mask_width : INTEGER := 1;
port_b_logical_ram_depth : INTEGER := 0;
port_b_logical_ram_width : INTEGER := 0;
port_b_first_address : INTEGER := 0;
port_b_last_address : INTEGER := 0;
port_b_first_bit_number : INTEGER := 0;
port_b_address_clear : STRING := "none";
port_b_data_out_clear : STRING := "none";
port_b_data_in_clock : STRING := "clock1";
port_b_address_clock : STRING := "clock1";
port_b_write_enable_clock: STRING := "clock1";
port_b_read_enable_clock: STRING := "clock1";
port_b_byte_enable_clock : STRING := "clock1";
port_b_data_out_clock : STRING := "none";
port_b_data_width : INTEGER := 1;
port_b_address_width : INTEGER := 1;
port_b_byte_enable_mask_width : INTEGER := 1;
port_a_read_during_write_mode : STRING := "new_data_no_nbe_read";
port_b_read_during_write_mode : STRING := "new_data_no_nbe_read";
power_up_uninitialized : STRING := "false";
port_b_byte_size : INTEGER := 0;
port_a_byte_size : INTEGER := 0;
lpm_type : string := "stratixiii_ram_block";
lpm_hint : string := "true";
clk0_input_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_core_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_output_clock_enable : STRING := "none"; -- ena0,none
clk1_input_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_core_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_output_clock_enable : STRING := "none"; -- ena1,none
clock_duty_cycle_dependence : STRING := "Auto";
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
mem_init2 : BIT_VECTOR := X"0";
mem_init3 : BIT_VECTOR := X"0";
mem_init4 : BIT_VECTOR := X"0";
mem_init5 : BIT_VECTOR := X"0";
mem_init6 : BIT_VECTOR := X"0";
mem_init7 : BIT_VECTOR := X"0";
mem_init8 : BIT_VECTOR := X"0";
mem_init9 : BIT_VECTOR := X"0";
mem_init10 : BIT_VECTOR := X"0";
mem_init11 : BIT_VECTOR := X"0";
mem_init12 : BIT_VECTOR := X"0";
mem_init13 : BIT_VECTOR := X"0";
mem_init14 : BIT_VECTOR := X"0";
mem_init15 : BIT_VECTOR := X"0";
mem_init16 : BIT_VECTOR := X"0";
mem_init17 : BIT_VECTOR := X"0";
mem_init18 : BIT_VECTOR := X"0";
mem_init19 : BIT_VECTOR := X"0";
mem_init20 : BIT_VECTOR := X"0";
mem_init21 : BIT_VECTOR := X"0";
mem_init22 : BIT_VECTOR := X"0";
mem_init23 : BIT_VECTOR := X"0";
mem_init24 : BIT_VECTOR := X"0";
mem_init25 : BIT_VECTOR := X"0";
mem_init26 : BIT_VECTOR := X"0";
mem_init27 : BIT_VECTOR := X"0";
mem_init28 : BIT_VECTOR := X"0";
mem_init29 : BIT_VECTOR := X"0";
mem_init30 : BIT_VECTOR := X"0";
mem_init31 : BIT_VECTOR := X"0";
mem_init32 : BIT_VECTOR := X"0";
mem_init33 : BIT_VECTOR := X"0";
mem_init34 : BIT_VECTOR := X"0";
mem_init35 : BIT_VECTOR := X"0";
mem_init36 : BIT_VECTOR := X"0";
mem_init37 : BIT_VECTOR := X"0";
mem_init38 : BIT_VECTOR := X"0";
mem_init39 : BIT_VECTOR := X"0";
mem_init40 : BIT_VECTOR := X"0";
mem_init41 : BIT_VECTOR := X"0";
mem_init42 : BIT_VECTOR := X"0";
mem_init43 : BIT_VECTOR := X"0";
mem_init44 : BIT_VECTOR := X"0";
mem_init45 : BIT_VECTOR := X"0";
mem_init46 : BIT_VECTOR := X"0";
mem_init47 : BIT_VECTOR := X"0";
mem_init48 : BIT_VECTOR := X"0";
mem_init49 : BIT_VECTOR := X"0";
mem_init50 : BIT_VECTOR := X"0";
mem_init51 : BIT_VECTOR := X"0";
mem_init52 : BIT_VECTOR := X"0";
mem_init53 : BIT_VECTOR := X"0";
mem_init54 : BIT_VECTOR := X"0";
mem_init55 : BIT_VECTOR := X"0";
mem_init56 : BIT_VECTOR := X"0";
mem_init57 : BIT_VECTOR := X"0";
mem_init58 : BIT_VECTOR := X"0";
mem_init59 : BIT_VECTOR := X"0";
mem_init60 : BIT_VECTOR := X"0";
mem_init61 : BIT_VECTOR := X"0";
mem_init62 : BIT_VECTOR := X"0";
mem_init63 : BIT_VECTOR := X"0";
mem_init64 : BIT_VECTOR := X"0";
mem_init65 : BIT_VECTOR := X"0";
mem_init66 : BIT_VECTOR := X"0";
mem_init67 : BIT_VECTOR := X"0";
mem_init68 : BIT_VECTOR := X"0";
mem_init69 : BIT_VECTOR := X"0";
mem_init70 : BIT_VECTOR := X"0";
mem_init71 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
-- -------- PORT DECLARATIONS ---------
PORT (
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portawe : IN STD_LOGIC := '0';
portare : IN STD_LOGIC := '1';
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portbwe : IN STD_LOGIC := '0';
portbre : IN STD_LOGIC := '1';
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
ena2 : IN STD_LOGIC := '1';
ena3 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portaaddrstall : IN STD_LOGIC := '0';
portbaddrstall : IN STD_LOGIC := '0';
eccstatus : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) := "000";
dftout : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := "000000000";
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
);
END stratixiii_ram_block;
ARCHITECTURE block_arch OF stratixiii_ram_block IS
COMPONENT stratixiii_ram_pulse_generator
PORT (
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
delaywrite : IN STD_LOGIC := '0';
pulse : OUT STD_LOGIC;
cycle : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT stratixiii_ram_register
GENERIC (
preset : STD_LOGIC := '0';
width : integer := 1
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
ena : IN STD_LOGIC;
stall : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END COMPONENT;
FUNCTION cond (condition : BOOLEAN;CONSTANT a,b : INTEGER) RETURN INTEGER IS
VARIABLE c: INTEGER;
BEGIN
IF (condition) THEN c := a; ELSE c := b; END IF;
RETURN c;
END;
SUBTYPE port_type IS BOOLEAN;
CONSTANT primary : port_type := TRUE;
CONSTANT secondary : port_type := FALSE;
CONSTANT primary_port_is_a : BOOLEAN := (port_b_data_width <= port_a_data_width);
CONSTANT primary_port_is_b : BOOLEAN := NOT primary_port_is_a;
CONSTANT mode_is_rom : BOOLEAN := (operation_mode = "rom");
CONSTANT mode_is_sp : BOOLEAN := (operation_mode = "single_port");
CONSTANT mode_is_dp : BOOLEAN := (operation_mode = "dual_port");
CONSTANT mode_is_bdp : BOOLEAN := (operation_mode = "bidir_dual_port");
CONSTANT wired_mode : BOOLEAN := (port_a_address_width = port_b_address_width) AND (port_a_address_width = 1)
AND (port_a_data_width /= port_b_data_width);
CONSTANT num_cols : INTEGER := cond(mode_is_rom OR mode_is_sp,1,
cond(wired_mode,2,2 ** (ABS(port_b_address_width - port_a_address_width))));
CONSTANT data_width : INTEGER := cond(primary_port_is_a,port_a_data_width,port_b_data_width);
CONSTANT data_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_data_width,port_b_data_width);
CONSTANT address_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_a,port_a_address_width,port_b_address_width);
CONSTANT address_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_address_width,port_b_address_width);
CONSTANT byte_size_a : INTEGER := port_a_data_width / port_a_byte_enable_mask_width;
CONSTANT byte_size_b : INTEGER := port_b_data_width / port_b_byte_enable_mask_width;
CONSTANT out_a_is_reg : BOOLEAN := (port_a_data_out_clock /= "none" AND port_a_data_out_clock /= "UNUSED");
CONSTANT out_b_is_reg : BOOLEAN := (port_b_data_out_clock /= "none" AND port_b_data_out_clock /= "UNUSED");
CONSTANT bytes_a_disabled : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
CONSTANT bytes_b_disabled : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
CONSTANT ram_type : BOOLEAN := FALSE;
TYPE bool_to_std_logic_map IS ARRAY(TRUE DOWNTO FALSE) OF STD_LOGIC;
CONSTANT bool_to_std_logic : bool_to_std_logic_map := ('1','0');
-- Hardware write modes
CONSTANT dual_clock : BOOLEAN := (operation_mode = "dual_port" OR
operation_mode = "bidir_dual_port") AND
(port_b_address_clock = "clock1");
CONSTANT both_new_data_same_port : BOOLEAN := (
((port_a_read_during_write_mode = "new_data_no_nbe_read") OR
(port_a_read_during_write_mode = "dont_care")) AND
((port_b_read_during_write_mode = "new_data_no_nbe_read") OR
(port_b_read_during_write_mode = "dont_care"))
);
SIGNAL hw_write_mode_a : STRING(3 DOWNTO 1);
SIGNAL hw_write_mode_b : STRING(3 DOWNTO 1);
SIGNAL delay_write_pulse_a : STD_LOGIC ;
SIGNAL delay_write_pulse_b : STD_LOGIC ;
CONSTANT be_mask_write_a : BOOLEAN := (port_a_read_during_write_mode = "new_data_with_nbe_read");
CONSTANT be_mask_write_b : BOOLEAN := (port_b_read_during_write_mode = "new_data_with_nbe_read");
CONSTANT old_data_write_a : BOOLEAN := (port_a_read_during_write_mode = "old_data");
CONSTANT old_data_write_b : BOOLEAN := (port_b_read_during_write_mode = "old_data");
SIGNAL read_before_write_a : BOOLEAN;
SIGNAL read_before_write_b : BOOLEAN;
-- -------- internal signals ---------
-- clock / clock enable
SIGNAL clk_a_in,clk_b_in : STD_LOGIC;
SIGNAL clk_a_byteena,clk_b_byteena : STD_LOGIC;
SIGNAL clk_a_out,clk_b_out : STD_LOGIC;
SIGNAL clkena_a_out,clkena_b_out : STD_LOGIC;
SIGNAL clkena_out_c0, clkena_out_c1 : STD_LOGIC;
SIGNAL write_cycle_a,write_cycle_b : STD_LOGIC;
SIGNAL clk_a_rena, clk_a_wena : STD_LOGIC;
SIGNAL clk_a_core : STD_LOGIC;
SIGNAL clk_b_rena, clk_b_wena : STD_LOGIC;
SIGNAL clk_b_core : STD_LOGIC;
SUBTYPE one_bit_bus_type IS STD_LOGIC_VECTOR(0 DOWNTO 0);
-- asynch clear
TYPE clear_mode_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
TYPE clear_vec_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
SIGNAL datain_a_clr,datain_b_clr : STD_LOGIC;
SIGNAL dataout_a_clr,dataout_b_clr : STD_LOGIC;
SIGNAL dataout_a_clr_reg, dataout_b_clr_reg : STD_LOGIC;
SIGNAL dataout_a_clr_reg_in, dataout_b_clr_reg_in : one_bit_bus_type;
SIGNAL dataout_a_clr_reg_out, dataout_b_clr_reg_out : one_bit_bus_type;
SIGNAL addr_a_clr,addr_b_clr : STD_LOGIC;
SIGNAL byteena_a_clr,byteena_b_clr : STD_LOGIC;
SIGNAL we_a_clr,re_a_clr,we_b_clr,re_b_clr : STD_LOGIC;
SIGNAL datain_a_clr_in,datain_b_clr_in : STD_LOGIC;
SIGNAL addr_a_clr_in,addr_b_clr_in : STD_LOGIC;
SIGNAL byteena_a_clr_in,byteena_b_clr_in : STD_LOGIC;
SIGNAL we_a_clr_in,re_a_clr_in,we_b_clr_in,re_b_clr_in : STD_LOGIC;
SIGNAL mem_invalidate,mem_invalidate_loc,read_latch_invalidate : clear_mode_type;
SIGNAL clear_asserted_during_write : clear_vec_type;
-- port A registers
SIGNAL we_a_reg : STD_LOGIC;
SIGNAL re_a_reg : STD_LOGIC;
SIGNAL we_a_reg_in,we_a_reg_out : one_bit_bus_type;
SIGNAL re_a_reg_in,re_a_reg_out : one_bit_bus_type;
SIGNAL addr_a_reg : STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0);
SIGNAL datain_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL dataout_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL dataout_a : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL byteena_a_reg : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width- 1 DOWNTO 0);
-- port B registers
SIGNAL we_b_reg, re_b_reg : STD_LOGIC;
SIGNAL re_b_reg_in,re_b_reg_out,we_b_reg_in,we_b_reg_out : one_bit_bus_type;
SIGNAL addr_b_reg : STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0);
SIGNAL datain_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL dataout_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL dataout_b : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL byteena_b_reg : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width- 1 DOWNTO 0);
-- pulses
TYPE pulse_vec IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
SIGNAL write_pulse,read_pulse,read_pulse_feedthru : pulse_vec;
SIGNAL rw_pulse : pulse_vec;
SIGNAL wpgen_a_clk,wpgen_a_clkena,wpgen_b_clk,wpgen_b_clkena : STD_LOGIC;
SIGNAL rpgen_a_clkena,rpgen_b_clkena : STD_LOGIC;
SIGNAL ftpgen_a_clkena,ftpgen_b_clkena : STD_LOGIC;
SIGNAL rwpgen_a_clkena,rwpgen_b_clkena : STD_LOGIC;
-- registered address
SIGNAL addr_prime_reg,addr_sec_reg : INTEGER;
-- input/output
SIGNAL datain_prime_reg,dataout_prime : STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
SIGNAL datain_sec_reg,dataout_sec : STD_LOGIC_VECTOR(data_unit_width - 1 DOWNTO 0);
-- overlapping location write
SIGNAL dual_write : BOOLEAN;
-- byte enable mask write
TYPE be_mask_write_vec IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
SIGNAL be_mask_write : be_mask_write_vec;
-- memory core
SUBTYPE mem_word_type IS STD_LOGIC_VECTOR (data_width - 1 DOWNTO 0);
SUBTYPE mem_col_type IS STD_LOGIC_VECTOR (data_unit_width - 1 DOWNTO 0);
TYPE mem_row_type IS ARRAY (num_cols - 1 DOWNTO 0) OF mem_col_type;
TYPE mem_type IS ARRAY ((2 ** address_unit_width) - 1 DOWNTO 0) OF mem_row_type;
SIGNAL mem : mem_type;
SIGNAL init_mem : BOOLEAN := FALSE;
CONSTANT mem_x : mem_type := (OTHERS => (OTHERS => (OTHERS => 'X')));
CONSTANT row_x : mem_row_type := (OTHERS => (OTHERS => 'X'));
CONSTANT col_x : mem_col_type := (OTHERS => 'X');
SIGNAL mem_data : mem_row_type;
SIGNAL old_mem_data : mem_row_type;
SIGNAL mem_unit_data : mem_col_type;
-- latches
TYPE read_latch_rec IS RECORD
prime : mem_row_type;
sec : mem_col_type;
END RECORD;
SIGNAL read_latch : read_latch_rec;
-- (row,column) coordinates
SIGNAL row_sec,col_sec : INTEGER;
-- byte enable
TYPE mask_type IS (normal,inverse);
TYPE mask_prime_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_word_type;
TYPE mask_sec_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_col_type;
TYPE mask_rec IS RECORD
prime : mask_prime_type;
sec : mask_sec_type;
END RECORD;
SIGNAL mask_vector : mask_rec;
SIGNAL mask_vector_common : mem_col_type;
FUNCTION get_mask(
b_ena : IN STD_LOGIC_VECTOR;
mode : port_type;
CONSTANT b_ena_width ,byte_size: INTEGER
) RETURN mask_rec IS
VARIABLE l : INTEGER;
VARIABLE mask : mask_rec := (
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X')),
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X'))
);
BEGIN
FOR l in 0 TO b_ena_width - 1 LOOP
IF (b_ena(l) = '0') THEN
IF (mode = primary) THEN
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask.prime(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
ELSE
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask.sec(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
END IF;
ELSIF (b_ena(l) = 'X' OR b_ena(l) = 'U') THEN
IF (mode = primary) THEN
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
ELSE
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
END IF;
END IF;
END LOOP;
RETURN mask;
END get_mask;
-- port active for read/write
SIGNAL active_a_core_in_vec,active_b_core_in_vec,active_a_core_out,active_b_core_out : one_bit_bus_type;
SIGNAL active_a_in,active_b_in : STD_LOGIC;
SIGNAL active_write_a : BOOLEAN;
SIGNAL active_write_b : BOOLEAN;
SIGNAL active_b_in_c0,active_b_core_in_c0,active_b_in_c1,active_b_core_in_c1 : STD_LOGIC;
SIGNAL active_a_core_in,active_b_core_in : STD_LOGIC;
SIGNAL active_a_core, active_b_core : BOOLEAN;
SIGNAL wire_vcc : STD_LOGIC := '1';
SIGNAL wire_gnd : STD_LOGIC := '0';
BEGIN
-- memory initialization
init_mem <= TRUE;
-- hardware write modes
hw_write_mode_a <= "R+W" WHEN ((port_a_read_during_write_mode = "old_data") OR
(port_a_read_during_write_mode = "new_data_with_nbe_read")) ELSE
" FW" WHEN (dual_clock OR (
mixed_port_feed_through_mode = "dont_care" AND
both_new_data_same_port
)) ELSE
" DW";
hw_write_mode_b <= "R+W" WHEN ((port_b_read_during_write_mode = "old_data") OR
(port_b_read_during_write_mode = "new_data_with_nbe_read")) ELSE
" FW" WHEN (dual_clock OR (
mixed_port_feed_through_mode = "dont_care" AND
both_new_data_same_port
)) ELSE
" DW";
delay_write_pulse_a <= '0' WHEN (mode_is_dp AND mixed_port_feed_through_mode = "dont_care") ELSE '1' WHEN (hw_write_mode_a /= " FW") ELSE '0';
delay_write_pulse_b <= '1' WHEN (hw_write_mode_b /= " FW") ELSE '0' ;
read_before_write_a <= (hw_write_mode_a = "R+W");
read_before_write_b <= (hw_write_mode_b = "R+W");
-- -------- core logic ---------------
clk_a_in <= clk0;
clk_a_wena <= '0' WHEN (port_a_write_enable_clock = "none") ELSE clk_a_in;
clk_a_rena <= '0' WHEN (port_a_read_enable_clock = "none") ELSE clk_a_in;
clk_a_byteena <= '0' WHEN (port_a_byte_enable_clock = "none" OR port_a_byte_enable_clock = "UNUSED") ELSE clk_a_in;
clk_a_out <= '0' WHEN (port_a_data_out_clock = "none" OR port_a_data_out_clock = "UNUSED") ELSE
clk0 WHEN (port_a_data_out_clock = "clock0") ELSE clk1;
clk_b_in <= clk0 WHEN (port_b_address_clock = "clock0") ELSE clk1;
clk_b_byteena <= '0' WHEN (port_b_byte_enable_clock = "none" OR port_b_byte_enable_clock = "UNUSED") ELSE
clk0 WHEN (port_b_byte_enable_clock = "clock0") ELSE clk1;
clk_b_wena <= '0' WHEN (port_b_write_enable_clock = "none") ELSE
clk0 WHEN (port_b_write_enable_clock = "clock0") ELSE
clk1;
clk_b_rena <= '0' WHEN (port_b_read_enable_clock = "none") ELSE
clk0 WHEN (port_b_read_enable_clock = "clock0") ELSE
clk1;
clk_b_out <= '0' WHEN (port_b_data_out_clock = "none" OR port_b_data_out_clock = "UNUSED") ELSE
clk0 WHEN (port_b_data_out_clock = "clock0") ELSE clk1;
addr_a_clr_in <= '0' WHEN (port_a_address_clear = "none" OR port_a_address_clear = "UNUSED") ELSE clr0;
addr_b_clr_in <= '0' WHEN (port_b_address_clear = "none" OR port_b_address_clear = "UNUSED") ELSE
clr0 WHEN (port_b_address_clear = "clear0") ELSE clr1;
datain_a_clr_in <= '0';
datain_b_clr_in <= '0';
dataout_a_clr <= '0' WHEN (port_a_data_out_clear = "none" OR port_a_data_out_clear = "UNUSED") ELSE
clr0 WHEN (port_a_data_out_clear = "clear0") ELSE clr1;
dataout_b_clr <= '0' WHEN (port_b_data_out_clear = "none" OR port_b_data_out_clear = "UNUSED") ELSE
clr0 WHEN (port_b_data_out_clear = "clear0") ELSE clr1;
byteena_a_clr_in <= '0';
byteena_b_clr_in <= '0';
we_a_clr_in <= '0';
re_a_clr_in <= '0';
we_b_clr_in <= '0';
re_b_clr_in <= '0';
active_a_in <= '1' WHEN (clk0_input_clock_enable = "none") ELSE
ena0 WHEN (clk0_input_clock_enable = "ena0") ELSE
ena2;
active_a_core_in <= '1' WHEN (clk0_core_clock_enable = "none") ELSE
ena0 WHEN (clk0_core_clock_enable = "ena0") ELSE
ena2;
be_mask_write(primary_port_is_a) <= be_mask_write_a;
be_mask_write(primary_port_is_b) <= be_mask_write_b;
active_b_in_c0 <= '1' WHEN (clk0_input_clock_enable = "none") ELSE
ena0 WHEN (clk0_input_clock_enable = "ena0") ELSE
ena2;
active_b_in_c1 <= '1' WHEN (clk1_input_clock_enable = "none") ELSE
ena1 WHEN (clk1_input_clock_enable = "ena1") ELSE
ena3;
active_b_in <= active_b_in_c0 WHEN (port_b_address_clock = "clock0") ELSE active_b_in_c1;
active_b_core_in_c0 <= '1' WHEN (clk0_core_clock_enable = "none") ELSE
ena0 WHEN (clk0_core_clock_enable = "ena0") ELSE
ena2;
active_b_core_in_c1 <= '1' WHEN (clk1_core_clock_enable = "none") ELSE
ena1 WHEN (clk1_core_clock_enable = "ena1") ELSE
ena3;
active_b_core_in <= active_b_core_in_c0 WHEN (port_b_address_clock = "clock0") ELSE active_b_core_in_c1;
active_write_a <= (byteena_a_reg /= bytes_a_disabled);
active_write_b <= (byteena_b_reg /= bytes_b_disabled);
-- Store core clock enable value for delayed write
-- port A core active
active_a_core_in_vec(0) <= active_a_core_in;
active_core_port_a : stratixiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => active_a_core_in_vec,
clk => clk_a_in,
aclr => wire_gnd,
devclrn => wire_vcc,devpor => wire_vcc,
ena => wire_vcc,
stall => wire_gnd,
q => active_a_core_out
);
active_a_core <= (active_a_core_out(0) = '1');
-- port B core active
active_b_core_in_vec(0) <= active_b_core_in;
active_core_port_b : stratixiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => active_b_core_in_vec,
clk => clk_b_in,
aclr => wire_gnd,
devclrn => wire_vcc,devpor => wire_vcc,
ena => wire_vcc,
stall => wire_gnd,
q => active_b_core_out
);
active_b_core <= (active_b_core_out(0) = '1');
-- ------ A input registers
-- write enable
we_a_reg_in(0) <= '0' WHEN mode_is_rom ELSE portawe;
we_a_register : stratixiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => we_a_reg_in,
clk => clk_a_wena,
aclr => we_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_core_in,
q => we_a_reg_out,
aclrout => we_a_clr
);
we_a_reg <= we_a_reg_out(0);
-- read enable
re_a_reg_in(0) <= portare;
re_a_register : stratixiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => re_a_reg_in,
clk => clk_a_rena,
aclr => re_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_core_in,
q => re_a_reg_out,
aclrout => re_a_clr
);
re_a_reg <= re_a_reg_out(0);
-- address
addr_a_register : stratixiii_ram_register
GENERIC MAP ( width => port_a_address_width )
PORT MAP (
d => portaaddr,
clk => clk_a_in,
aclr => addr_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => portaaddrstall,
ena => active_a_in,
q => addr_a_reg,
aclrout => addr_a_clr
);
-- data
datain_a_register : stratixiii_ram_register
GENERIC MAP ( width => port_a_data_width )
PORT MAP (
d => portadatain,
clk => clk_a_in,
aclr => datain_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => datain_a_reg,
aclrout => datain_a_clr
);
-- byte enable
byteena_a_register : stratixiii_ram_register
GENERIC MAP (
width => port_a_byte_enable_mask_width,
preset => '1'
)
PORT MAP (
d => portabyteenamasks,
clk => clk_a_byteena,
aclr => byteena_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => byteena_a_reg,
aclrout => byteena_a_clr
);
-- ------ B input registers
-- read enable
re_b_reg_in(0) <= portbre;
re_b_register : stratixiii_ram_register
GENERIC MAP (
width => 1
)
PORT MAP (
d => re_b_reg_in,
clk => clk_b_in,
aclr => re_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_core_in,
q => re_b_reg_out,
aclrout => re_b_clr
);
re_b_reg <= re_b_reg_out(0);
-- write enable
we_b_reg_in(0) <= portbwe;
we_b_register : stratixiii_ram_register
GENERIC MAP (
width => 1
)
PORT MAP (
d => we_b_reg_in,
clk => clk_b_in,
aclr => we_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_core_in,
q => we_b_reg_out,
aclrout => we_b_clr
);
we_b_reg <= we_b_reg_out(0);
-- address
addr_b_register : stratixiii_ram_register
GENERIC MAP ( width => port_b_address_width )
PORT MAP (
d => portbaddr,
clk => clk_b_in,
aclr => addr_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => portbaddrstall,
ena => active_b_in,
q => addr_b_reg,
aclrout => addr_b_clr
);
-- data
datain_b_register : stratixiii_ram_register
GENERIC MAP ( width => port_b_data_width )
PORT MAP (
d => portbdatain,
clk => clk_b_in,
aclr => datain_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => datain_b_reg,
aclrout => datain_b_clr
);
-- byte enable
byteena_b_register : stratixiii_ram_register
GENERIC MAP (
width => port_b_byte_enable_mask_width,
preset => '1'
)
PORT MAP (
d => portbbyteenamasks,
clk => clk_b_byteena,
aclr => byteena_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => byteena_b_reg,
aclrout => byteena_b_clr
);
datain_prime_reg <= datain_a_reg WHEN primary_port_is_a ELSE datain_b_reg;
addr_prime_reg <= alt_conv_integer(addr_a_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_b_reg);
datain_sec_reg <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
datain_b_reg WHEN primary_port_is_a ELSE datain_a_reg;
addr_sec_reg <= alt_conv_integer(addr_b_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_a_reg);
-- Write pulse generation
wpgen_a_clk <= clk_a_in;
wpgen_a_clkena <= '1' WHEN (active_a_core AND active_write_a AND (we_a_reg = '1')) ELSE '0';
wpgen_a : stratixiii_ram_pulse_generator
PORT MAP (
clk => wpgen_a_clk,
ena => wpgen_a_clkena,
delaywrite => delay_write_pulse_a,
pulse => write_pulse(primary_port_is_a),
cycle => write_cycle_a
);
wpgen_b_clk <= clk_b_in;
wpgen_b_clkena <= '1' WHEN (active_b_core AND active_write_b AND mode_is_bdp AND (we_b_reg = '1')) ELSE '0';
wpgen_b : stratixiii_ram_pulse_generator
PORT MAP (
clk => wpgen_b_clk,
ena => wpgen_b_clkena,
delaywrite => delay_write_pulse_b,
pulse => write_pulse(primary_port_is_b),
cycle => write_cycle_b
);
-- Read pulse generation
rpgen_a_clkena <= '1' WHEN (active_a_core AND (re_a_reg = '1') AND (we_a_reg = '0')) ELSE '0';
rpgen_a : stratixiii_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => rpgen_a_clkena,
cycle => clk_a_core,
pulse => read_pulse(primary_port_is_a)
);
rpgen_b_clkena <= '1' WHEN ((mode_is_dp OR mode_is_bdp) AND active_b_core AND (re_b_reg = '1') AND (we_b_reg = '0')) ELSE '0';
rpgen_b : stratixiii_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => rpgen_b_clkena,
cycle => clk_b_core,
pulse => read_pulse(primary_port_is_b)
);
-- Read-during-Write pulse generation
rwpgen_a_clkena <= '1' WHEN (active_a_core AND (re_a_reg = '1') AND (we_a_reg = '1') AND read_before_write_a) ELSE '0';
rwpgen_a : stratixiii_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => rwpgen_a_clkena,
pulse => rw_pulse(primary_port_is_a)
);
rwpgen_b_clkena <= '1' WHEN (active_b_core AND mode_is_bdp AND (re_b_reg = '1') AND (we_b_reg = '1') AND read_before_write_b) ELSE '0';
rwpgen_b : stratixiii_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => rwpgen_b_clkena,
pulse => rw_pulse(primary_port_is_b)
);
-- Create internal masks for byte enable processing
mask_create : PROCESS (byteena_a_reg,byteena_b_reg)
VARIABLE mask : mask_rec;
BEGIN
IF (byteena_a_reg'EVENT) THEN
mask := get_mask(byteena_a_reg,primary_port_is_a,port_a_byte_enable_mask_width,byte_size_a);
IF (primary_port_is_a) THEN
mask_vector.prime <= mask.prime;
ELSE
mask_vector.sec <= mask.sec;
END IF;
END IF;
IF (byteena_b_reg'EVENT) THEN
mask := get_mask(byteena_b_reg,primary_port_is_b,port_b_byte_enable_mask_width,byte_size_b);
IF (primary_port_is_b) THEN
mask_vector.prime <= mask.prime;
ELSE
mask_vector.sec <= mask.sec;
END IF;
END IF;
END PROCESS mask_create;
-- (row,col) coordinates
row_sec <= addr_sec_reg / num_cols;
col_sec <= addr_sec_reg mod num_cols;
mem_rw : PROCESS (init_mem,
write_pulse,read_pulse,read_pulse_feedthru,
rw_pulse,
mem_invalidate,mem_invalidate_loc,read_latch_invalidate)
-- mem init
TYPE rw_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
VARIABLE addr_range_init,row,col,index : INTEGER;
VARIABLE mem_init_std : STD_LOGIC_VECTOR((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
VARIABLE mem_init : bit_vector(mem_init71'length + mem_init70'length + mem_init69'length + mem_init68'length + mem_init67'length + mem_init66'length +
mem_init65'length + mem_init64'length + mem_init63'length + mem_init62'length + mem_init61'length +
mem_init60'length + mem_init59'length + mem_init58'length + mem_init57'length + mem_init56'length +
mem_init55'length + mem_init54'length + mem_init53'length + mem_init52'length + mem_init51'length +
mem_init50'length + mem_init49'length + mem_init48'length + mem_init47'length + mem_init46'length +
mem_init45'length + mem_init44'length + mem_init43'length + mem_init42'length + mem_init41'length +
mem_init40'length + mem_init39'length + mem_init38'length + mem_init37'length + mem_init36'length +
mem_init35'length + mem_init34'length + mem_init33'length + mem_init32'length + mem_init31'length +
mem_init30'length + mem_init29'length + mem_init28'length + mem_init27'length + mem_init26'length +
mem_init25'length + mem_init24'length + mem_init23'length + mem_init22'length + mem_init21'length +
mem_init20'length + mem_init19'length + mem_init18'length + mem_init17'length + mem_init16'length +
mem_init15'length + mem_init14'length + mem_init13'length + mem_init12'length + mem_init11'length +
mem_init10'length + mem_init9'length + mem_init8'length + mem_init7'length + mem_init6'length +
mem_init5'length + mem_init4'length + mem_init3'length + mem_init2'length + mem_init1'length +
mem_init0'length - 1 DOWNTO 0);
VARIABLE mem_val : mem_type;
-- read/write
VARIABLE mem_data_p : mem_row_type;
VARIABLE old_mem_data_p : mem_row_type;
VARIABLE row_prime,col_prime : INTEGER;
VARIABLE access_same_location : BOOLEAN;
VARIABLE read_during_write : rw_type;
BEGIN
read_during_write := (FALSE,FALSE);
-- Memory initialization
IF (init_mem'EVENT) THEN
-- Initialize output latches to 0
IF (primary_port_is_a) THEN
dataout_prime <= (OTHERS => '0');
IF (mode_is_dp OR mode_is_bdp) THEN dataout_sec <= (OTHERS => '0'); END IF;
ELSE
dataout_sec <= (OTHERS => '0');
IF (mode_is_dp OR mode_is_bdp) THEN dataout_prime <= (OTHERS => '0'); END IF;
END IF;
IF (power_up_uninitialized = "false" AND (NOT ram_type)) THEN
mem_val := (OTHERS => (OTHERS => (OTHERS => '0')));
END IF;
IF (primary_port_is_a) THEN
addr_range_init := port_a_last_address - port_a_first_address + 1;
ELSE
addr_range_init := port_b_last_address - port_b_first_address + 1;
END IF;
IF (init_file_layout = "port_a" OR init_file_layout = "port_b") THEN
mem_init := mem_init71 & mem_init70 & mem_init69 & mem_init68 & mem_init67 & mem_init66 &
mem_init65 & mem_init64 & mem_init63 & mem_init62 & mem_init61 &
mem_init60 & mem_init59 & mem_init58 & mem_init57 & mem_init56 &
mem_init55 & mem_init54 & mem_init53 & mem_init52 & mem_init51 &
mem_init50 & mem_init49 & mem_init48 & mem_init47 & mem_init46 &
mem_init45 & mem_init44 & mem_init43 & mem_init42 & mem_init41 &
mem_init40 & mem_init39 & mem_init38 & mem_init37 & mem_init36 &
mem_init35 & mem_init34 & mem_init33 & mem_init32 & mem_init31 &
mem_init30 & mem_init29 & mem_init28 & mem_init27 & mem_init26 &
mem_init25 & mem_init24 & mem_init23 & mem_init22 & mem_init21 &
mem_init20 & mem_init19 & mem_init18 & mem_init17 & mem_init16 &
mem_init15 & mem_init14 & mem_init13 & mem_init12 & mem_init11 &
mem_init10 & mem_init9 & mem_init8 & mem_init7 & mem_init6 &
mem_init5 & mem_init4 & mem_init3 & mem_init2 & mem_init1 &
mem_init0;
mem_init_std := to_stdlogicvector(mem_init) ((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
FOR row IN 0 TO addr_range_init - 1 LOOP
FOR col IN 0 to num_cols - 1 LOOP
index := row * data_width;
mem_val(row)(col) := mem_init_std(index + (col+1)*data_unit_width -1 DOWNTO
index + col*data_unit_width);
END LOOP;
END LOOP;
END IF;
mem <= mem_val;
END IF;
access_same_location := (mode_is_dp OR mode_is_bdp) AND (addr_prime_reg = row_sec);
-- Read before Write stage 1 : read data from memory
-- Read before Write stage 2 : send data to output
IF (rw_pulse(primary)'EVENT) THEN
IF (rw_pulse(primary) = '1') THEN
read_latch.prime <= mem(addr_prime_reg);
ELSE
IF (be_mask_write(primary)) THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = 'X') THEN
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END IF;
END LOOP;
ELSE
FOR i IN 0 TO data_width - 1 LOOP
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END LOOP;
END IF;
END IF;
END IF;
IF (rw_pulse(secondary)'EVENT) THEN
IF (rw_pulse(secondary) = '1') THEN
read_latch.sec <= mem(row_sec)(col_sec);
ELSE
IF (be_mask_write(secondary)) THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = 'X') THEN
dataout_sec(i) <= read_latch.sec(i);
END IF;
END LOOP;
ELSE
dataout_sec <= read_latch.sec;
END IF;
END IF;
END IF;
-- Write stage 1 : X to buffer
-- Write stage 2 : actual data to memory
IF (write_pulse(primary)'EVENT) THEN
IF (write_pulse(primary) = '1') THEN
old_mem_data_p := mem(addr_prime_reg);
mem_data_p := mem(addr_prime_reg);
FOR i IN 0 TO num_cols - 1 LOOP
mem_data_p(i) := mem_data_p(i) XOR
mask_vector.prime(inverse)((i + 1)*data_unit_width - 1 DOWNTO i*data_unit_width);
END LOOP;
read_during_write(secondary) := (access_same_location AND read_pulse(secondary)'EVENT AND read_pulse(secondary) = '1');
IF (read_during_write(secondary)) THEN
read_latch.sec <= old_mem_data_p(col_sec);
ELSE
mem_data <= mem_data_p;
END IF;
ELSIF (clear_asserted_during_write(primary) /= '1') THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = '0') THEN
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= datain_prime_reg(i);
ELSIF (mask_vector.prime(inverse)(i) = 'X') THEN
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= 'X';
END IF;
END LOOP;
END IF;
END IF;
IF (write_pulse(secondary)'EVENT) THEN
IF (write_pulse(secondary) = '1') THEN
read_during_write(primary) := (access_same_location AND read_pulse(primary)'EVENT AND read_pulse(primary) = '1');
IF (read_during_write(primary)) THEN
read_latch.prime <= mem(addr_prime_reg);
read_latch.prime(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
ELSE
mem_unit_data <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
END IF;
IF (access_same_location AND write_pulse(primary)'EVENT AND write_pulse(primary) = '1') THEN
mask_vector_common <=
mask_vector.prime(inverse)(((col_sec + 1)* data_unit_width - 1) DOWNTO col_sec*data_unit_width) AND
mask_vector.sec(inverse);
dual_write <= TRUE;
END IF;
ELSIF (clear_asserted_during_write(secondary) /= '1') THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = '0') THEN
mem(row_sec)(col_sec)(i) <= datain_sec_reg(i);
ELSIF (mask_vector.sec(inverse)(i) = 'X') THEN
mem(row_sec)(col_sec)(i) <= 'X';
END IF;
END LOOP;
END IF;
END IF;
-- Simultaneous write
IF (dual_write AND write_pulse = "00") THEN
mem(row_sec)(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector_common;
dual_write <= FALSE;
END IF;
-- Read stage 1 : read data
-- Read stage 2 : send data to output
IF ((NOT read_during_write(primary)) AND read_pulse(primary)'EVENT) THEN
IF (read_pulse(primary) = '1') THEN
read_latch.prime <= mem(addr_prime_reg);
IF (access_same_location AND write_pulse(secondary) = '1') THEN
read_latch.prime(col_sec) <= mem_unit_data;
END IF;
ELSE
FOR i IN 0 TO data_width - 1 LOOP
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END LOOP;
END IF;
END IF;
IF ((NOT read_during_write(secondary)) AND read_pulse(secondary)'EVENT) THEN
IF (read_pulse(secondary) = '1') THEN
IF (access_same_location AND write_pulse(primary) = '1') THEN
read_latch.sec <= mem_data(col_sec);
ELSE
read_latch.sec <= mem(row_sec)(col_sec);
END IF;
ELSE
dataout_sec <= read_latch.sec;
END IF;
END IF;
-- Same port feed thru
IF (read_pulse_feedthru(primary)'EVENT AND read_pulse_feedthru(primary) = '0') THEN
IF (be_mask_write(primary)) THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = '0') THEN
dataout_prime(i) <= datain_prime_reg(i);
END IF;
END LOOP;
ELSE
dataout_prime <= datain_prime_reg XOR mask_vector.prime(normal);
END IF;
END IF;
IF (read_pulse_feedthru(secondary)'EVENT AND read_pulse_feedthru(secondary) = '0') THEN
IF (be_mask_write(secondary)) THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = '0') THEN
dataout_sec(i) <= datain_sec_reg(i);
END IF;
END LOOP;
ELSE
dataout_sec <= datain_sec_reg XOR mask_vector.sec(normal);
END IF;
END IF;
-- Async clear
IF (mem_invalidate'EVENT) THEN
IF (mem_invalidate(primary) = TRUE OR mem_invalidate(secondary) = TRUE) THEN
mem <= mem_x;
END IF;
END IF;
IF (mem_invalidate_loc'EVENT) THEN
IF (mem_invalidate_loc(primary)) THEN mem(addr_prime_reg) <= row_x; END IF;
IF (mem_invalidate_loc(secondary)) THEN mem(row_sec)(col_sec) <= col_x; END IF;
END IF;
IF (read_latch_invalidate'EVENT) THEN
IF (read_latch_invalidate(primary)) THEN
read_latch.prime <= row_x;
END IF;
IF (read_latch_invalidate(secondary)) THEN
read_latch.sec <= col_x;
END IF;
END IF;
END PROCESS mem_rw;
-- Same port feed through
ftpgen_a_clkena <= '1' WHEN (active_a_core AND (NOT mode_is_dp) AND (NOT old_data_write_a) AND (we_a_reg = '1') AND (re_a_reg = '1')) ELSE '0';
ftpgen_a : stratixiii_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => ftpgen_a_clkena,
pulse => read_pulse_feedthru(primary_port_is_a)
);
ftpgen_b_clkena <= '1' WHEN (active_b_core AND mode_is_bdp AND (NOT old_data_write_b) AND (we_b_reg = '1') AND (re_b_reg = '1')) ELSE '0';
ftpgen_b : stratixiii_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => ftpgen_b_clkena,
pulse => read_pulse_feedthru(primary_port_is_b)
);
-- Asynch clear events
clear_a : PROCESS(addr_a_clr,we_a_clr,datain_a_clr)
BEGIN
IF (addr_a_clr'EVENT AND addr_a_clr = '1') THEN
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
mem_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
ELSIF (re_a_reg = '1') THEN
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
IF ((we_a_clr'EVENT AND we_a_clr = '1') OR (datain_a_clr'EVENT AND datain_a_clr = '1')) THEN
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
mem_invalidate_loc(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
END PROCESS clear_a;
clear_b : PROCESS(addr_b_clr,we_b_clr,datain_b_clr)
BEGIN
IF (addr_b_clr'EVENT AND addr_b_clr = '1') THEN
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (we_b_reg = '1')) THEN
mem_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
ELSIF ((mode_is_dp OR mode_is_bdp) AND re_b_reg = '1') THEN
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
IF ((we_b_clr'EVENT AND we_b_clr = '1') OR (datain_b_clr'EVENT AND datain_b_clr = '1')) THEN
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (we_b_reg = '1')) THEN
mem_invalidate_loc(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
END PROCESS clear_b;
-- Clear mux registers (Latch Clear)
-- Port A output register clear
dataout_a_clr_reg_in(0) <= dataout_a_clr;
aclr_a_mux_register : stratixiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => dataout_a_clr_reg_in,
clk => clk_a_core,
aclr => wire_gnd,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => wire_vcc,
q => dataout_a_clr_reg_out
);
dataout_a_clr_reg <= dataout_a_clr_reg_out(0);
-- Port B output register clear
dataout_b_clr_reg_in(0) <= dataout_b_clr;
aclr_b_mux_register : stratixiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => dataout_b_clr_reg_in,
clk => clk_b_core,
aclr => wire_gnd,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => wire_vcc,
q => dataout_b_clr_reg_out
);
dataout_b_clr_reg <= dataout_b_clr_reg_out(0);
-- ------ Output registers
clkena_out_c0 <= '1' WHEN (clk0_output_clock_enable = "none") ELSE ena0;
clkena_out_c1 <= '1' WHEN (clk1_output_clock_enable = "none") ELSE ena1;
clkena_a_out <= clkena_out_c0 WHEN (port_a_data_out_clock = "clock0") ELSE clkena_out_c1;
clkena_b_out <= clkena_out_c0 WHEN (port_b_data_out_clock = "clock0") ELSE clkena_out_c1;
dataout_a <= dataout_prime WHEN primary_port_is_a ELSE dataout_sec;
dataout_b <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
dataout_prime WHEN primary_port_is_b ELSE dataout_sec;
dataout_a_register : stratixiii_ram_register
GENERIC MAP ( width => port_a_data_width )
PORT MAP (
d => dataout_a,
clk => clk_a_out,
aclr => dataout_a_clr,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => clkena_a_out,
q => dataout_a_reg
);
dataout_b_register : stratixiii_ram_register
GENERIC MAP ( width => port_b_data_width )
PORT MAP (
d => dataout_b,
clk => clk_b_out,
aclr => dataout_b_clr,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => clkena_b_out,
q => dataout_b_reg
);
portadataout <= dataout_a_reg WHEN (out_a_is_reg) ELSE
(OTHERS => '0') WHEN ((dataout_a_clr = '1') OR (dataout_a_clr_reg = '1')) ELSE
dataout_a;
portbdataout <= dataout_b_reg WHEN (out_b_is_reg) ELSE
(OTHERS => '0') WHEN ((dataout_b_clr = '1') OR (dataout_b_clr_reg = '1')) ELSE
dataout_b;
eccstatus <= (OTHERS => '0');
dftout <= (OTHERS => '0');
END block_arch;
---------------------------------------------------------------------
--
-- Entity Name : stratixiii_ff
--
-- Description : Stratix III FF VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
use work.stratixiii_and1;
entity stratixiii_ff is
generic (
power_up : string := "low";
x_on_violation : string := "on";
lpm_type : string := "stratixiii_ff";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
clrn : in std_logic := '1';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
asdata : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of stratixiii_ff : entity is TRUE;
end stratixiii_ff;
architecture vital_lcell_ff of stratixiii_ff is
attribute VITAL_LEVEL0 of vital_lcell_ff : architecture is TRUE;
signal clk_ipd : std_logic;
signal d_ipd : std_logic;
signal d_dly : std_logic;
signal asdata_ipd : std_logic;
signal asdata_dly : std_logic;
signal asdata_dly1 : std_logic;
signal sclr_ipd : std_logic;
signal sload_ipd : std_logic;
signal clrn_ipd : std_logic;
signal aload_ipd : std_logic;
signal ena_ipd : std_logic;
component stratixiii_and1
generic (XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01
);
port (Y : out STD_LOGIC;
IN1 : in STD_LOGIC
);
end component;
begin
ddelaybuffer: stratixiii_and1
port map(IN1 => d_ipd,
Y => d_dly);
asdatadelaybuffer: stratixiii_and1
port map(IN1 => asdata_ipd,
Y => asdata_dly);
asdatadelaybuffer1: stratixiii_and1
port map(IN1 => asdata_dly,
Y => asdata_dly1);
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (asdata_ipd, asdata, tipd_asdata);
VitalWireDelay (sclr_ipd, sclr, tipd_sclr);
VitalWireDelay (sload_ipd, sload, tipd_sload);
VitalWireDelay (clrn_ipd, clrn, tipd_clrn);
VitalWireDelay (aload_ipd, aload, tipd_aload);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process (clk_ipd, d_dly, asdata_dly1,
sclr_ipd, sload_ipd, clrn_ipd, aload_ipd,
ena_ipd, devclrn, devpor)
variable Tviol_d_clk : std_ulogic := '0';
variable Tviol_asdata_clk : std_ulogic := '0';
variable Tviol_sclr_clk : std_ulogic := '0';
variable Tviol_sload_clk : std_ulogic := '0';
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_asdata_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sclr_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable iq : std_logic := '0';
variable idata: std_logic := '0';
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
if (now = 0 ns) then
if (power_up = "low") then
iq := '0';
elsif (power_up = "high") then
iq := '1';
end if;
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(sload_ipd) OR
(sclr_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_asdata_clk,
TimingData => TimingData_asdata_clk,
TestSignal => asdata_ipd,
TestSignalName => "ASDATA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_asdata_clk_noedge_posedge,
SetupLow => tsetup_asdata_clk_noedge_posedge,
HoldHigh => thold_asdata_clk_noedge_posedge,
HoldLow => thold_asdata_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT sload_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sclr_clk,
TimingData => TimingData_sclr_clk,
TestSignal => sclr_ipd,
TestSignalName => "SCLR",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sclr_clk_noedge_posedge,
SetupLow => tsetup_sclr_clk_noedge_posedge,
HoldHigh => thold_sclr_clk_noedge_posedge,
HoldLow => thold_sclr_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sload_clk,
TimingData => TimingData_sload_clk,
TestSignal => sload_ipd,
TestSignalName => "SLOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sload_clk_noedge_posedge,
SetupLow => tsetup_sload_clk_noedge_posedge,
HoldHigh => thold_sload_clk_noedge_posedge,
HoldLow => thold_sload_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
violation := Tviol_d_clk or Tviol_asdata_clk or
Tviol_sclr_clk or Tviol_sload_clk or Tviol_ena_clk;
if ((devpor = '0') or (devclrn = '0') or (clrn_ipd = '0')) then
iq := '0';
elsif (aload_ipd = '1') then
iq := asdata_dly1;
elsif (violation = 'X' and x_on_violation = "on") then
iq := 'X';
elsif clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' then
if (ena_ipd = '1') then
if (sclr_ipd = '1') then
iq := '0';
elsif (sload_ipd = '1') then
iq := asdata_dly1;
else
iq := d_dly;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => iq,
Paths => (0 => (clrn_ipd'last_event, tpd_clrn_q_posedge, TRUE),
1 => (aload_ipd'last_event, tpd_aload_q_posedge, TRUE),
2 => (asdata_ipd'last_event, tpd_asdata_q, TRUE),
3 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_lcell_ff;
--/////////////////////////////////////////////////////////////////////////////
--
-- VHDL Simulation Model for Stratix III CLKSELECT Atom
--
--/////////////////////////////////////////////////////////////////////////////
--
--
-- STRATIXIII_CLKSELECT Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
entity stratixiii_clkselect is
generic (
lpm_type : STRING := "stratixiii_clkselect";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tpd_inclk_outclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tpd_clkselect_outclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01)
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
outclk : out std_logic
);
attribute VITAL_LEVEL0 of stratixiii_clkselect : entity is TRUE;
end stratixiii_clkselect;
architecture vital_clkselect of stratixiii_clkselect is
attribute VITAL_LEVEL0 of vital_clkselect : architecture is TRUE;
signal inclk_ipd : std_logic_vector(3 downto 0);
signal clkselect_ipd : std_logic_vector(1 downto 0);
signal clkmux_out : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (inclk_ipd(0), inclk(0), tipd_inclk(0));
VitalWireDelay (inclk_ipd(1), inclk(1), tipd_inclk(1));
VitalWireDelay (inclk_ipd(2), inclk(2), tipd_inclk(2));
VitalWireDelay (inclk_ipd(3), inclk(3), tipd_inclk(3));
VitalWireDelay (clkselect_ipd(0), clkselect(0), tipd_clkselect(0));
VitalWireDelay (clkselect_ipd(1), clkselect(1), tipd_clkselect(1));
end block;
process(inclk_ipd, clkselect_ipd)
variable outclk_VitalGlitchData : VitalGlitchDataType;
variable tmp : std_logic;
begin
if (clkselect_ipd = "11") then
tmp := inclk_ipd(3);
elsif (clkselect_ipd = "10") then
tmp := inclk_ipd(2);
elsif (clkselect_ipd = "01") then
tmp := inclk_ipd(1);
else
tmp := inclk_ipd(0);
end if;
clkmux_out <= tmp;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01
(
OutSignal => outclk,
OutSignalName => "OUTCLOCK",
OutTemp => tmp,
Paths => (0 => (inclk_ipd(0)'last_event, tpd_inclk_outclk(0), TRUE),
1 => (inclk_ipd(1)'last_event, tpd_inclk_outclk(1), TRUE),
2 => (inclk_ipd(2)'last_event, tpd_inclk_outclk(2), TRUE),
3 => (inclk_ipd(3)'last_event, tpd_inclk_outclk(3), TRUE),
4 => (clkselect_ipd(0)'last_event, tpd_clkselect_outclk(0), TRUE),
5 => (clkselect_ipd(1)'last_event, tpd_clkselect_outclk(1), TRUE)),
GlitchData => outclk_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
end process;
end vital_clkselect;
--/////////////////////////////////////////////////////////////////////////////
--
-- stratixiii_and2 Model
-- Description : Simulation model for a simple two input AND gate.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.stratixiii_atom_pack.all;
-- entity declaration --
entity stratixiii_and2 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tpd_IN2_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01;
tipd_IN2 : VitalDelayType01 := DefPropDelay01);
port(
Y : out STD_LOGIC;
IN1 : in STD_LOGIC;
IN2 : in STD_LOGIC);
attribute VITAL_LEVEL0 of stratixiii_and2 : entity is TRUE;
end stratixiii_and2;
-- architecture body --
architecture AltVITAL of stratixiii_and2 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
SIGNAL IN1_ipd : STD_ULOGIC := 'U';
SIGNAL IN2_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
VitalWireDelay (IN2_ipd, IN2, tipd_IN2);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN1_ipd, IN2_ipd)
-- functionality results
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
ALIAS Y_zd : STD_ULOGIC is Results(1);
-- output glitch detection variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
begin
-------------------------
-- Functionality Section
-------------------------
Y_zd := TO_X01(IN1_ipd) AND TO_X01(IN2_ipd);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => ( 0 => (IN1_ipd'last_event, tpd_IN1_Y, TRUE),
1 => (IN2_ipd'last_event, tpd_IN2_Y, TRUE)),
GlitchData => Y_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixiii_ena_reg
--
-- Description : Simulation model for a simple DFF.
-- This is used for the gated clock generation
-- Powers upto 1.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_ena_reg is
generic (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of stratixiii_ena_reg : entity is TRUE;
end stratixiii_ena_reg;
ARCHITECTURE behave of stratixiii_ena_reg is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal d_ipd : std_logic;
signal clk_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (clk_ipd, clk, tipd_clk);
end block;
VITALtiming : process (clk_ipd, prn, clrn)
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable q_reg : std_logic := '1';
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "D",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((clrn) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/stratixiii_ena_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (prn = '0') then
q_reg := '1';
elsif (clrn = '0') then
q_reg := '0';
elsif (clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' and (ena = '1')) then
q_reg := d_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_reg,
Paths => (0 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- VHDL Simulation Model for Stratix III CLKCTRL Atom
--
--/////////////////////////////////////////////////////////////////////////////
--
--
-- Stratix III_CLKCTRL Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
use work.stratixiii_ena_reg;
use work.stratixiii_and2;
entity stratixiii_clkena is
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "stratixiii_clkena";
ena_register_mode : STRING := "Falling Edge";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01
);
port (
inclk : in std_logic := '0';
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
enaout : out std_logic;
outclk : out std_logic
);
attribute VITAL_LEVEL0 of stratixiii_clkena : entity is TRUE;
end stratixiii_clkena;
architecture vital_clkena of stratixiii_clkena is
attribute VITAL_LEVEL0 of vital_clkena : architecture is TRUE;
component stratixiii_and2
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tpd_IN2_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01;
tipd_IN2 : VitalDelayType01 := DefPropDelay01);
port(
Y : out STD_LOGIC;
IN1 : in STD_LOGIC;
IN2 : in STD_LOGIC);
end component;
component stratixiii_ena_reg
generic (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
end component;
signal inclk_ipd : std_logic;
signal inclk_inv : std_logic;
signal ena_ipd : std_logic;
signal cereg_clr : std_logic;
signal cereg1_out : std_logic;
signal cereg2_out : std_logic;
signal ena_out : std_logic;
signal vcc : std_logic := '1';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (inclk_ipd, inclk, tipd_inclk);
end block;
inclk_inv <= NOT inclk_ipd;
extena_reg1 : stratixiii_ena_reg
port map (
clk => inclk_inv,
ena => vcc,
d => ena_ipd,
clrn => vcc,
prn => devpor,
q => cereg1_out
);
extena_reg2 : stratixiii_ena_reg
port map (
clk => inclk_inv,
ena => vcc,
d => cereg1_out,
clrn => vcc,
prn => devpor,
q => cereg2_out
);
ena_out <= cereg1_out WHEN (ena_register_mode = "falling edge") ELSE
ena_ipd WHEN (ena_register_mode = "none") ELSE cereg2_out;
outclk_and : stratixiii_and2
port map (
IN1 => inclk_ipd,
IN2 => ena_out,
Y => outclk
);
enaout_and : stratixiii_and2
port map (
IN1 => vcc,
IN2 => ena_out,
Y => enaout
);
end vital_clkena;
----------------------------------------------------------------------------
-- Module Name : stratixiii_mlab_cell_pulse_generator
-- Description : Generate pulse to initiate memory read/write operations
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiii_atom_pack.all;
ENTITY stratixiii_mlab_cell_pulse_generator IS
GENERIC (
tipd_clk : VitalDelayType01 := (1 ps,1 ps);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tpd_clk_pulse_posedge : VitalDelayType01 := DefPropDelay01
);
PORT (
clk,ena : IN STD_LOGIC;
pulse,cycle : OUT STD_LOGIC
);
ATTRIBUTE VITAL_Level0 OF stratixiii_mlab_cell_pulse_generator:ENTITY IS TRUE;
END stratixiii_mlab_cell_pulse_generator;
ARCHITECTURE pgen_arch OF stratixiii_mlab_cell_pulse_generator IS
SIGNAL clk_ipd,ena_ipd : STD_LOGIC;
SIGNAL state : STD_LOGIC;
ATTRIBUTE VITAL_Level0 OF pgen_arch:ARCHITECTURE IS TRUE;
BEGIN
WireDelay : BLOCK
BEGIN
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
END BLOCK;
PROCESS (clk_ipd,state)
BEGIN
IF (state = '1' AND state'EVENT) THEN
state <= '0';
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1') THEN
state <= '1';
END IF;
END PROCESS;
PathDelay : PROCESS
VARIABLE pulse_VitalGlitchData : VitalGlitchDataType;
BEGIN
WAIT UNTIL state'EVENT;
VitalPathDelay01 (
OutSignal => pulse,
OutSignalName => "pulse",
OutTemp => state,
Paths => (0 => (clk_ipd'LAST_EVENT,tpd_clk_pulse_posedge,TRUE)),
GlitchData => pulse_VitalGlitchData,
Mode => DefGlitchMode,
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks
);
END PROCESS;
cycle <= clk_ipd;
END pgen_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiii_atom_pack.all;
USE work.stratixiii_mlab_cell_pulse_generator;
ENTITY stratixiii_mlab_cell IS
GENERIC (
-- -------- GLOBAL PARAMETERS ---------
logical_ram_name : STRING := "lutram";
init_file : STRING := "UNUSED";
data_interleave_offset_in_bits : INTEGER := 1;
logical_ram_depth : INTEGER := 0;
logical_ram_width : INTEGER := 0;
first_address : INTEGER := 0;
last_address : INTEGER := 0;
first_bit_number : INTEGER := 0;
data_width : INTEGER := 1;
address_width : INTEGER := 1;
byte_enable_mask_width : INTEGER := 1;
byte_size : INTEGER := 1;
lpm_type : string := "stratixiii_mlab_cell";
lpm_hint : string := "true";
mixed_port_feed_through_mode : string := "dont_care";
mem_init0 : BIT_VECTOR := X"0";
-- --------- VITAL PARAMETERS --------
tipd_clk0 : VitalDelayType01 := DefPropDelay01;
tipd_ena0 : VitalDelayType01 := DefPropDelay01;
tipd_portaaddr : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_portbaddr : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_portabyteenamasks : VitalDelayArrayType01(20 DOWNTO 0) := (OTHERS => DefPropDelay01);
tsetup_portaaddr_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_portabyteenamasks_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena0_clk0_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_portaaddr_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_portabyteenamasks_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ena0_clk0_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_portbaddr_portbdataout : VitalDelayType01 := DefPropDelay01
);
-- -------- PORT DECLARATIONS ---------
PORT (
portadatain : IN STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0) := (OTHERS => '0');
portabyteenamasks : IN STD_LOGIC_VECTOR(byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbaddr : IN STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0) := (OTHERS => '0');
clk0 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
portbdataout : OUT STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0)
);
END stratixiii_mlab_cell;
ARCHITECTURE block_arch OF stratixiii_mlab_cell IS
COMPONENT stratixiii_mlab_cell_pulse_generator
PORT (
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
pulse : OUT STD_LOGIC;
cycle : OUT STD_LOGIC
);
END COMPONENT;
CONSTANT port_byte_size : INTEGER := data_width / byte_enable_mask_width;
-- -------- internal signals ---------
-- Write address
SIGNAL write_address : INTEGER := 0;
SIGNAL read_address : INTEGER := 0;
-- pulses
SIGNAL write_pulse, write_cycle, write_clock : STD_LOGIC;
-- memory core
SUBTYPE mem_word_type IS STD_LOGIC_VECTOR (data_width - 1 DOWNTO 0);
TYPE mem_type IS ARRAY ((2 ** address_width) - 1 DOWNTO 0) OF mem_word_type;
SIGNAL mem : mem_type;
SIGNAL init_mem : BOOLEAN := FALSE;
-- byte enable
TYPE mask_type IS (normal,inverse);
TYPE mask_write IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_word_type;
SIGNAL mask_vector : mask_write := (
normal => (OTHERS => '0'),
inverse => (OTHERS => 'X')
);
-- output
FUNCTION get_mask(
b_ena : IN STD_LOGIC_VECTOR;
CONSTANT b_ena_width ,byte_size: INTEGER
) RETURN mask_write IS
VARIABLE l : INTEGER;
VARIABLE mask : mask_write := (normal => (OTHERS => '0'),inverse => (OTHERS => 'X'));
BEGIN
FOR l in 0 TO b_ena_width - 1 LOOP
IF (b_ena(l) = '0') THEN
mask(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
ELSIF (b_ena(l) = 'X' OR b_ena(l) = 'U') THEN
mask(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
END IF;
END LOOP;
RETURN mask;
END get_mask;
SIGNAL clk0_ipd : STD_LOGIC;
SIGNAL ena0_ipd : STD_LOGIC;
SIGNAL portaaddr_ipd : STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0);
SIGNAL portbaddr_ipd : STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0);
SIGNAL portabyteenamasks_ipd : STD_LOGIC_VECTOR(byte_enable_mask_width - 1 DOWNTO 0);
SIGNAL ena0_reg : STD_LOGIC := '0';
BEGIN
-- interconnect delays
WireDelay : BLOCK
BEGIN
loopbits_ad : FOR i in portaaddr'RANGE GENERATE
VitalWireDelay (portaaddr_ipd(i), portaaddr(i), tipd_portaaddr(i));
VitalWireDelay (portbaddr_ipd(i), portbaddr(i), tipd_portbaddr(i));
END GENERATE;
loopbits_be : FOR j in portabyteenamasks'RANGE GENERATE
VitalWireDelay (portabyteenamasks_ipd(j), portabyteenamasks(j), tipd_portabyteenamasks(j));
END GENERATE;
VitalWireDelay (clk0_ipd, clk0, tipd_clk0);
VitalWireDelay (ena0_ipd, ena0, tipd_ena0);
END BLOCK;
-- setup/hold checks
setup_hold_checks: PROCESS (ena0_reg,portaaddr_ipd,portabyteenamasks_ipd,clk0_ipd,ena0_ipd)
VARIABLE Tviol_clk_enable : STD_ULOGIC := '0';
VARIABLE Tviol_clk_address : STD_ULOGIC := '0';
VARIABLE Tviol_clk_bemasks : STD_ULOGIC := '0';
VARIABLE TimingData_clk_enable : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_address : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_bemasks : VitalTimingDataType := VitalTimingDataInit;
BEGIN
-- Timing checks
VitalSetupHoldCheck (
Violation => Tviol_clk_enable,
TimingData => TimingData_clk_enable,
TestSignal => ena0_ipd,
TestSignalName => "ena0",
RefSignal => clk0_ipd,
RefSignalName => "clk0",
SetupHigh => tsetup_ena0_clk0_noedge_posedge,
SetupLow => tsetup_ena0_clk0_noedge_posedge,
HoldHigh => thold_ena0_clk0_noedge_posedge,
HoldLow => thold_ena0_clk0_noedge_posedge,
CheckEnabled => TRUE,
RefTransition => '/',
HeaderMsg => "/LUTRAM VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_address,
TimingData => TimingData_clk_address,
TestSignal => portaaddr_ipd,
TestSignalName => "portaaddr",
RefSignal => clk0_ipd,
RefSignalName => "clk0",
SetupHigh => tsetup_portaaddr_clk0_noedge_negedge,
SetupLow => tsetup_portaaddr_clk0_noedge_negedge,
HoldHigh => thold_portaaddr_clk0_noedge_negedge,
HoldLow => thold_portaaddr_clk0_noedge_negedge,
CheckEnabled => (ena0_reg = '1'),
RefTransition => '\',
HeaderMsg => "/LUTRAM VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_bemasks,
TimingData => TimingData_clk_bemasks,
TestSignal => portabyteenamasks_ipd,
TestSignalName => "portabyteenamasks",
RefSignal => clk0_ipd,
RefSignalName => "clk0",
SetupHigh => tsetup_portabyteenamasks_clk0_noedge_negedge,
SetupLow => tsetup_portabyteenamasks_clk0_noedge_negedge,
HoldHigh => thold_portabyteenamasks_clk0_noedge_negedge,
HoldLow => thold_portabyteenamasks_clk0_noedge_negedge,
CheckEnabled => (ena0_reg = '1'),
RefTransition => '\',
HeaderMsg => "/LUTRAM VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
END PROCESS setup_hold_checks;
-- latch CE signal
PROCESS (clk0_ipd)
BEGIN
IF (clk0_ipd'EVENT AND clk0_ipd = '1') THEN
ena0_reg <= ena0_ipd;
END IF;
END PROCESS;
-- output path delay
PROCESS (portbaddr_ipd)
VARIABLE CQDelay : TIME := 0 ns;
BEGIN
CQDelay := SelectDelay(
( 1 => ( portbaddr_ipd'LAST_EVENT, tpd_portbaddr_portbdataout, TRUE ) )
);
read_address <= TRANSPORT alt_conv_integer(portbaddr_ipd) AFTER CQDelay;
END PROCESS;
-- memory initialization
init_mem <= TRUE;
write_clock <= NOT clk0_ipd;
write_address <= alt_conv_integer(portaaddr_ipd);
-- Write pulse generation (neg edge)
wpgen_a : stratixiii_mlab_cell_pulse_generator
PORT MAP (
clk => write_clock,
ena => ena0_reg,
pulse => write_pulse,
cycle => write_cycle
);
-- Create internal masks for byte enable processing
mask_create : PROCESS (portabyteenamasks_ipd)
VARIABLE mask : mask_write;
BEGIN
IF (portabyteenamasks_ipd'EVENT) THEN
mask := get_mask(portabyteenamasks_ipd,byte_enable_mask_width,port_byte_size);
mask_vector <= mask;
END IF;
END PROCESS mask_create;
mem_rw : PROCESS (init_mem, write_pulse)
-- mem init
VARIABLE addr_range_init,index : INTEGER;
VARIABLE mem_init_std : STD_LOGIC_VECTOR((last_address - first_address + 1)*data_width - 1 DOWNTO 0);
VARIABLE mem_init : bit_vector(mem_init0'length - 1 DOWNTO 0);
VARIABLE mem_val : mem_type;
-- read/write
VARIABLE mem_data_p : mem_word_type;
BEGIN
-- Memory initialization
IF (init_mem'EVENT) THEN
-- Initialize output to 0
mem_val := (OTHERS => (OTHERS => '0'));
IF (init_file /= "UNUSED" AND init_file /= "unused") THEN
addr_range_init := last_address - first_address + 1;
mem_init := mem_init0;
mem_init_std := to_stdlogicvector(mem_init)((last_address - first_address + 1)*data_width - 1 DOWNTO 0);
FOR row IN 0 TO addr_range_init - 1 LOOP
index := row * data_width;
mem_val(row) := mem_init_std(index + data_width -1 DOWNTO index );
END LOOP;
END IF;
mem <= mem_val;
END IF;
-- Write stage 1 : X to memory
-- Write stage 2 : actual data to memory
IF (write_pulse'EVENT) THEN
IF (write_pulse = '1') THEN
mem_data_p := mem(write_address);
FOR i IN 0 TO data_width - 1 LOOP
mem_data_p(i) := mem_data_p(i) XOR mask_vector(inverse)(i);
END LOOP;
mem(write_address) <= mem_data_p;
ELSIF (write_pulse = '0') THEN
mem_data_p := mem(write_address);
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector(normal)(i) = '0') THEN
mem(write_address)(i) <= portadatain(i);
mem_data_p(i) := portadatain(i);
ELSIF (mask_vector(inverse)(i) = 'X') THEN
mem(write_address)(i) <= 'X';
mem_data_p(i) := 'X';
END IF;
END LOOP;
END IF;
END IF;
END PROCESS mem_rw;
-- Continuous read
portbdataout <= mem(read_address);
END block_arch;
---------------------------------------------------------------------
--
-- Entity Name : stratixiii_io_ibuf
--
-- Description : Stratix III IO Ibuf VHDL simulation model
--
--
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_io_ibuf IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_ibar : VitalDelayType01 := DefPropDelay01;
tipd_dynamicterminationcontrol : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_ibar_o : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
differential_mode : string := "false";
bus_hold : string := "false";
simulate_z_as : string := "Z";
lpm_type : string := "stratixiii_io_ibuf"
);
PORT (
i : IN std_logic := '0';
ibar : IN std_logic := '0';
dynamicterminationcontrol : IN std_logic := '0';
o : OUT std_logic
);
END stratixiii_io_ibuf;
ARCHITECTURE arch OF stratixiii_io_ibuf IS
SIGNAL i_ipd : std_logic := '0';
SIGNAL ibar_ipd : std_logic := '0';
SIGNAL o_tmp : std_logic;
SIGNAL out_tmp : std_logic;
SIGNAL prev_value : std_logic := '0';
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
VitalWireDelay (ibar_ipd, ibar, tipd_ibar);
end block;
PROCESS(i_ipd, ibar_ipd)
BEGIN
IF (differential_mode = "false") THEN
IF (i_ipd = '1') THEN
o_tmp <= '1';
prev_value <= '1';
ELSIF (i_ipd = '0') THEN
o_tmp <= '0';
prev_value <= '0';
ELSE
o_tmp <= i_ipd;
END IF;
ELSE
IF (( i_ipd = '0' ) and (ibar_ipd = '1')) then
o_tmp <= '0';
ELSIF (( i_ipd = '1' ) and (ibar_ipd = '0')) then
o_tmp <= '1';
ELSIF((( i_ipd = '1' ) and (ibar_ipd = '1')) or (( i_ipd = '0' ) and (ibar_ipd = '0')))then
o_tmp <= 'X';
ELSE
o_tmp <= 'X';
END IF;
END IF;
END PROCESS;
out_tmp <= prev_value when (bus_hold = "true") else
'Z' when((o_tmp = 'Z') AND (simulate_z_as = "Z")) else
'X' when((o_tmp = 'Z') AND (simulate_z_as = "X")) else
'1' when((o_tmp = 'Z') AND (simulate_z_as = "vcc")) else
'0' when((o_tmp = 'Z') AND (simulate_z_as = "gnd")) else
o_tmp;
----------------------
-- Path Delay Section
----------------------
PROCESS( out_tmp)
variable output_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => out_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE),
1 => (ibar_ipd'last_event, tpd_ibar_o, TRUE)),
GlitchData => output_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : stratixiii_io_obuf
--
-- Description : Stratix III IO Obuf VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_io_obuf IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_dynamicterminationcontrol : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_oe_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
tpd_oe_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
open_drain_output : string := "false";
shift_series_termination_control : string := "false";
sim_dynamic_termination_control_is_connected : string := "false";
bus_hold : string := "false";
lpm_type : string := "stratixiii_io_obuf"
);
PORT (
i : IN std_logic := '0';
oe : IN std_logic := '1';
dynamicterminationcontrol : IN std_logic := '0';
seriesterminationcontrol : IN std_logic_vector(13 DOWNTO 0) := (others => '0');
parallelterminationcontrol : IN std_logic_vector(13 DOWNTO 0) := (others => '0');
devoe : IN std_logic := '1';
o : OUT std_logic;
obar : OUT std_logic
);
END stratixiii_io_obuf;
ARCHITECTURE arch OF stratixiii_io_obuf IS
--INTERNAL Signals
SIGNAL i_ipd : std_logic := '0';
SIGNAL oe_ipd : std_logic := '0';
SIGNAL dynamicterminationcontrol_ipd : std_logic := '0';
SIGNAL out_tmp : std_logic := 'Z';
SIGNAL out_tmp_bar : std_logic;
SIGNAL prev_value : std_logic := '0';
SIGNAL o_tmp : std_logic;
SIGNAL obar_tmp : std_logic;
SIGNAL o_tmp1 : std_logic;
SIGNAL obar_tmp1 : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
VitalWireDelay (oe_ipd, oe, tipd_oe);
VitalWireDelay (dynamicterminationcontrol_ipd, dynamicterminationcontrol, tipd_dynamicterminationcontrol);
end block;
PROCESS( i_ipd, oe_ipd)
BEGIN
IF (oe_ipd = '1') THEN
IF (open_drain_output = "true") THEN
IF (i_ipd = '0') THEN
out_tmp <= '0';
out_tmp_bar <= '1';
prev_value <= '0';
ELSE
out_tmp <= 'Z';
out_tmp_bar <= 'Z';
END IF;
ELSE
IF (i_ipd = '0') THEN
out_tmp <= '0';
out_tmp_bar <= '1';
prev_value <= '0';
ELSE
IF (i_ipd = '1') THEN
out_tmp <= '1';
out_tmp_bar <= '0';
prev_value <= '1';
ELSE
out_tmp <= i_ipd;
out_tmp_bar <= i_ipd;
END IF;
END IF;
END IF;
ELSE
IF (oe_ipd = '0') THEN
out_tmp <= 'Z';
out_tmp_bar <= 'Z';
ELSE
out_tmp <= 'X';
out_tmp_bar <= 'X';
END IF;
END IF;
END PROCESS;
o_tmp1 <= prev_value WHEN (bus_hold = "true") ELSE out_tmp;
obar_tmp1 <= NOT prev_value WHEN (bus_hold = "true") ELSE out_tmp_bar;
o_tmp <= 'X' when (( oe_ipd = '1') and (dynamicterminationcontrol = '1') and (sim_dynamic_termination_control_is_connected = "true")) else o_tmp1 WHEN (devoe = '1') ELSE 'Z';
obar_tmp <= 'X' when (( oe_ipd = '1') and (dynamicterminationcontrol = '1')and (sim_dynamic_termination_control_is_connected = "true")) else obar_tmp1 WHEN (devoe = '1') ELSE 'Z';
---------------------
-- Path Delay Section
----------------------
PROCESS( o_tmp,obar_tmp)
variable o_VitalGlitchData : VitalGlitchDataType;
variable obar_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => o_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE),
1 => (oe_ipd'last_event, tpd_oe_o, TRUE)),
GlitchData => o_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01 (
OutSignal => obar,
OutSignalName => "obar",
OutTemp => obar_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_obar, TRUE),
1 => (oe_ipd'last_event, tpd_oe_obar, TRUE)),
GlitchData => obar_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
-----------------------------------------------------------------------
--
-- Entity Name : stratixiii_ddio_in
--
-- Description : Stratix III DDIO_IN VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY altera;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use altera.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_ddio_in IS
generic(
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_clkn : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
use_clkn : string := "false";
lpm_type : string := "stratixiii_ddio_in"
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
clkn : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
regoutlo : OUT std_logic;
regouthi : OUT std_logic;
dfflo : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END stratixiii_ddio_in;
ARCHITECTURE arch OF stratixiii_ddio_in IS
component dffeas
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
--Internal Signals
SIGNAL datain_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL clkn_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '0';
SIGNAL areset_ipd : std_logic := '0';
SIGNAL sreset_ipd : std_logic := '0';
SIGNAL ddioreg_aclr : std_logic;
SIGNAL ddioreg_prn : std_logic;
SIGNAL ddioreg_adatasdata : std_logic;
SIGNAL ddioreg_sclr : std_logic;
SIGNAL ddioreg_sload : std_logic;
SIGNAL ddioreg_clk : std_logic;
SIGNAL dfflo_tmp : std_logic;
SIGNAL regout_tmp_hi : std_logic;
SIGNAL regout_tmp_lo : std_logic;
SIGNAL regouthi_tmp : std_logic;
SIGNAL regoutlo_tmp : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (clkn_ipd, clkn, tipd_clkn);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
end block;
ddioreg_clk <= NOT clk_ipd WHEN (use_clkn = "false") ELSE clkn_ipd;
--Decode the control values for the DDIO registers
PROCESS
BEGIN
WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT;
IF (async_mode = "clear") THEN
ddioreg_aclr <= NOT areset_ipd;
ddioreg_prn <= '1';
ELSIF (async_mode = "preset") THEN
ddioreg_aclr <= '1';
ddioreg_prn <= NOT areset_ipd;
ELSE
ddioreg_aclr <= '1';
ddioreg_prn <= '1';
END IF;
IF (sync_mode = "clear") THEN
ddioreg_adatasdata <= '0';
ddioreg_sclr <= sreset_ipd;
ddioreg_sload <= '0';
ELSIF (sync_mode = "preset") THEN
ddioreg_adatasdata <= '1';
ddioreg_sclr <= '0';
ddioreg_sload <= sreset_ipd;
ELSE
ddioreg_adatasdata <= '0';
ddioreg_sclr <= '0';
ddioreg_sload <= '0';
END IF;
END PROCESS;
--DDIO High Register
ddioreg_hi : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => datain_ipd,
clk => clk_ipd,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => regout_tmp_hi,
devpor => devpor,
devclrn => devclrn
);
--DDIO Low Register
ddioreg_lo : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => datain_ipd,
clk => ddioreg_clk,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dfflo_tmp,
devpor => devpor,
devclrn => devclrn
);
ddioreg_lo1 : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => dfflo_tmp,
clk => clk_ipd,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => regout_tmp_lo,
devpor => devpor,
devclrn => devclrn
);
regouthi <= regout_tmp_hi ;
regoutlo <= regout_tmp_lo ;
dfflo <= dfflo_tmp ;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : stratixiii_ddio_oe
--
-- Description : Stratix III DDIO_OE VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY altera;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use altera.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_ddio_oe IS
generic(
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "stratixiii_ddio_oe"
);
PORT (
oe : IN std_logic := '1';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END stratixiii_ddio_oe;
ARCHITECTURE arch OF stratixiii_ddio_oe IS
component stratixiii_mux21
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01
);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic
);
end component;
component dffeas
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
--Internal Signals
SIGNAL oe_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '0';
SIGNAL areset_ipd : std_logic := '0';
SIGNAL sreset_ipd : std_logic := '0';
SIGNAL ddioreg_aclr : std_logic;
SIGNAL ddioreg_prn : std_logic;
SIGNAL ddioreg_adatasdata : std_logic;
SIGNAL ddioreg_sclr : std_logic;
SIGNAL ddioreg_sload : std_logic;
SIGNAL dfflo_tmp : std_logic;
SIGNAL dffhi_tmp : std_logic;
signal nclk : std_logic;
signal dataout_tmp : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (oe_ipd, oe, tipd_oe);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
end block;
nclk <= NOT clk_ipd;
PROCESS
BEGIN
WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT;
IF (async_mode = "clear") THEN
ddioreg_aclr <= NOT areset_ipd;
ddioreg_prn <= '1';
ELSIF (async_mode = "preset") THEN
ddioreg_aclr <= '1';
ddioreg_prn <= NOT areset_ipd;
ELSE
ddioreg_aclr <= '1';
ddioreg_prn <= '1';
END IF;
IF (sync_mode = "clear") THEN
ddioreg_adatasdata <= '0';
ddioreg_sclr <= sreset_ipd;
ddioreg_sload <= '0';
ELSIF (sync_mode = "preset") THEN
ddioreg_adatasdata <= '1';
ddioreg_sclr <= '0';
ddioreg_sload <= sreset_ipd;
ELSE
ddioreg_adatasdata <= '0';
ddioreg_sclr <= '0';
ddioreg_sload <= '0';
END IF;
END PROCESS;
ddioreg_hi : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => oe_ipd,
clk => clk_ipd,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dffhi_tmp,
devpor => devpor,
devclrn => devclrn
);
--DDIO Low Register
ddioreg_lo : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => dffhi_tmp,
clk => nclk,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dfflo_tmp,
devpor => devpor,
devclrn => devclrn
);
--registered output
or_gate : stratixiii_mux21
port map (
A => dffhi_tmp,
B => dfflo_tmp,
S => dfflo_tmp,
MO => dataout
);
dfflo <= dfflo_tmp ;
dffhi <= dffhi_tmp ;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : stratixiii_ddio_out
--
-- Description : Stratix III DDIO_OUT VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY altera;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use altera.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_ddio_out IS
generic(
tipd_datainlo : VitalDelayType01 := DefPropDelay01;
tipd_datainhi : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_clkhi : VitalDelayType01 := DefPropDelay01;
tipd_clklo : VitalDelayType01 := DefPropDelay01;
tipd_muxsel : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
half_rate_mode : string := "false";
use_new_clocking_model : string := "false";
lpm_type : string := "stratixiii_ddio_out"
);
PORT (
datainlo : IN std_logic := '0';
datainhi : IN std_logic := '0';
clk : IN std_logic := '0';
clkhi : IN std_logic := '0';
clklo : IN std_logic := '0';
muxsel : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic_vector(1 downto 0) ;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END stratixiii_ddio_out;
ARCHITECTURE arch OF stratixiii_ddio_out IS
component stratixiii_mux21
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01
);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic
);
end component;
component dffeas
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
--Internal Signals
SIGNAL datainlo_ipd : std_logic := '0';
SIGNAL datainhi_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL clkhi_ipd : std_logic := '0';
SIGNAL clklo_ipd : std_logic := '0';
SIGNAL muxsel_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '0';
SIGNAL areset_ipd : std_logic := '0';
SIGNAL sreset_ipd : std_logic := '0';
SIGNAL ddioreg_aclr : std_logic;
SIGNAL ddioreg_prn : std_logic;
SIGNAL ddioreg_adatasdata : std_logic;
SIGNAL ddioreg_sclr : std_logic;
SIGNAL ddioreg_sload : std_logic;
SIGNAL dfflo_tmp : std_logic;
SIGNAL dffhi_tmp : std_logic;
SIGNAL dataout_tmp : std_logic;
Signal mux_sel : std_logic;
Signal mux_hi : std_logic;
Signal dffhi1_tmp : std_logic;
Signal sel_mux_hi_in : std_logic;
signal nclk : std_logic;
signal clk1 : std_logic;
signal clk_hi : std_logic;
signal clk_lo : std_logic;
signal clk_hr : std_logic;
signal muxsel1 : std_logic;
signal muxsel2: std_logic;
signal clk2 : std_logic;
signal muxsel_tmp: std_logic;
signal sel_mux_lo_in : std_logic;
signal datainlo_tmp : std_logic;
signal datainhi_tmp : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (datainlo_ipd, datainlo, tipd_datainlo);
VitalWireDelay (datainhi_ipd, datainhi, tipd_datainhi);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (clkhi_ipd, clkhi, tipd_clkhi);
VitalWireDelay (clklo_ipd, clklo, tipd_clklo);
VitalWireDelay (muxsel_ipd, muxsel, tipd_muxsel);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
end block;
nclk <= NOT clk_ipd;
PROCESS
BEGIN
WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT;
IF (async_mode = "clear") THEN
ddioreg_aclr <= NOT areset_ipd;
ddioreg_prn <= '1';
ELSIF (async_mode = "preset") THEN
ddioreg_aclr <= '1';
ddioreg_prn <= NOT areset_ipd;
ELSE
ddioreg_aclr <= '1';
ddioreg_prn <= '1';
END IF;
IF (sync_mode = "clear") THEN
ddioreg_adatasdata <= '0';
ddioreg_sclr <= sreset_ipd;
ddioreg_sload <= '0';
ELSIF (sync_mode = "preset") THEN
ddioreg_adatasdata <= '1';
ddioreg_sclr <= '0';
ddioreg_sload <= sreset_ipd;
ELSE
ddioreg_adatasdata <= '0';
ddioreg_sclr <= '0';
ddioreg_sload <= '0';
END IF;
END PROCESS;
process(clk_ipd)
begin
clk1 <= clk_ipd;
end process;
process(muxsel_ipd)
begin
muxsel1 <= muxsel_ipd;
end process;
--DDIO HIGH Register
clk_hi <= clkhi_ipd when(use_new_clocking_model = "true") else clk_ipd;
datainhi_tmp <= datainhi;
ddioreg_hi : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => datainhi_tmp,
clk => clk_hi,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dffhi_tmp,
devpor => devpor,
devclrn => devclrn
);
--DDIO Low Register
clk_lo <= clklo_ipd when(use_new_clocking_model = "true") else clk_ipd;
datainlo_tmp <= datainlo;
ddioreg_lo : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => datainlo_tmp,
clk => clk_lo,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dfflo_tmp,
devpor => devpor,
devclrn => devclrn
);
clk_hr <= NOT clkhi_ipd when(use_new_clocking_model = "true") else NOT clk_ipd;
ddioreg_hi1 : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => dffhi_tmp,
clk => clk_hr,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dffhi1_tmp,
devpor => devpor,
devclrn => devclrn
);
muxsel2 <= muxsel1;
clk2 <= clk1;
mux_sel <= muxsel2 when(use_new_clocking_model = "true") else clk2;
muxsel_tmp <= mux_sel;
sel_mux_lo_in <= dfflo_tmp;
sel_mux_hi_in <= dffhi1_tmp when(half_rate_mode = "true") else dffhi_tmp;
sel_mux : stratixiii_mux21
port map (
A => sel_mux_lo_in,
B => sel_mux_hi_in,
S => muxsel_tmp,
MO => dataout
);
dfflo <= dfflo_tmp;
dffhi(0) <= dffhi_tmp;
dffhi(1) <= dffhi1_tmp;
END arch;
-- --------------------------------------------------------------------
-- Module Name: stratixiii_rt_sm
-- Description: Parallel Termination State Machine
-- --------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
ENTITY stratixiii_rt_sm IS
PORT (
rup : IN std_logic;
rdn : IN std_logic;
clk : IN std_logic;
clken : IN std_logic;
clr : IN std_logic;
rtena : IN std_logic;
rscaldone : IN std_logic;
rtoffsetp : OUT std_logic_vector(3 DOWNTO 0);
rtoffsetn : OUT std_logic_vector(3 DOWNTO 0);
caldone : OUT std_logic;
sel_rup_vref : OUT std_logic_vector(2 DOWNTO 0);
sel_rdn_vref : OUT std_logic_vector(2 DOWNTO 0));
END stratixiii_rt_sm;
ARCHITECTURE stratixiii_rt_sm_rtl OF stratixiii_rt_sm IS
CONSTANT STRATIXIII_RTOCT_WAIT : std_logic_vector(4 DOWNTO 0) := "00000";
CONSTANT RUP_VREF_M_RDN_VER_M : std_logic_vector(4 DOWNTO 0) := "00001";
CONSTANT RUP_VREF_L_RDN_VER_L : std_logic_vector(4 DOWNTO 0) := "00010";
CONSTANT RUP_VREF_H_RDN_VER_H : std_logic_vector(4 DOWNTO 0) := "00011";
CONSTANT RUP_VREF_L_RDN_VER_H : std_logic_vector(4 DOWNTO 0) := "00100";
CONSTANT RUP_VREF_H_RDN_VER_L : std_logic_vector(4 DOWNTO 0) := "00101";
CONSTANT STRATIXIII_RTOCT_INC_PN : std_logic_vector(4 DOWNTO 0) := "01000";
CONSTANT STRATIXIII_RTOCT_DEC_PN : std_logic_vector(4 DOWNTO 0) := "01001";
CONSTANT STRATIXIII_RTOCT_INC_P : std_logic_vector(4 DOWNTO 0) := "01010";
CONSTANT STRATIXIII_RTOCT_DEC_P : std_logic_vector(4 DOWNTO 0) := "01011";
CONSTANT STRATIXIII_RTOCT_INC_N : std_logic_vector(4 DOWNTO 0) := "01100";
CONSTANT STRATIXIII_RTOCT_DEC_N : std_logic_vector(4 DOWNTO 0) := "01101";
CONSTANT STRATIXIII_RTOCT_SWITCH_REG: std_logic_vector(4 DOWNTO 0) := "10001";
CONSTANT STRATIXIII_RTOCT_DONE : std_logic_vector(4 DOWNTO 0) := "11111";
-- interface
SIGNAL nclr : std_logic := '1'; -- for synthesis
SIGNAL rtcalclk : std_logic;
SIGNAL caldone_sig : std_logic := '0';
-- sm
SIGNAL current_state : std_logic_vector(4 DOWNTO 0) := "00000";
SIGNAL next_state : std_logic_vector(4 DOWNTO 0) := "00000";
SIGNAL sel_rup_vref_h_d : std_logic := '0';
SIGNAL sel_rup_vref_h : std_logic := '0';
SIGNAL sel_rup_vref_m_d : std_logic := '1';
SIGNAL sel_rup_vref_m : std_logic := '1';
SIGNAL sel_rup_vref_l_d : std_logic := '0';
SIGNAL sel_rup_vref_l : std_logic := '0';
SIGNAL sel_rdn_vref_h_d : std_logic := '0';
SIGNAL sel_rdn_vref_h : std_logic := '0';
SIGNAL sel_rdn_vref_m_d : std_logic := '1';
SIGNAL sel_rdn_vref_m : std_logic := '1';
SIGNAL sel_rdn_vref_l_d : std_logic := '0';
SIGNAL sel_rdn_vref_l : std_logic := '0';
SIGNAL switch_region_d : std_logic := '0';
SIGNAL switch_region : std_logic := '0';
SIGNAL cmpup : std_logic := '0';
SIGNAL cmpdn : std_logic := '0';
SIGNAL rt_sm_done_d : std_logic := '0';
SIGNAL rt_sm_done : std_logic := '0';
-- cnt
SIGNAL p_cnt_d : std_logic_vector(2 DOWNTO 0) := "000";
SIGNAL p_cnt : std_logic_vector(2 DOWNTO 0) := "000";
SIGNAL n_cnt_d : std_logic_vector(2 DOWNTO 0) := "000";
SIGNAL n_cnt : std_logic_vector(2 DOWNTO 0) := "000";
SIGNAL p_cnt_sub_d : std_logic := '0';
SIGNAL p_cnt_sub : std_logic := '0';
SIGNAL n_cnt_sub_d : std_logic := '0';
SIGNAL n_cnt_sub : std_logic := '0';
BEGIN
-- primary output - MSB is sign bit
rtoffsetp <= p_cnt_sub & p_cnt ;
rtoffsetn <= n_cnt_sub & n_cnt ;
caldone <= caldone_sig;
caldone_sig <= rt_sm_done WHEN (rtena = '1') ELSE '1';
sel_rup_vref <= sel_rup_vref_h & sel_rup_vref_m & sel_rup_vref_l ;
sel_rdn_vref <= sel_rdn_vref_h & sel_rdn_vref_m & sel_rdn_vref_l ;
-- input interface
nclr <= NOT clr ;
rtcalclk <= ((rscaldone AND clken) AND (NOT caldone_sig)) AND clk ;
-- latch registers - rising on everything except cmpup and cmpdn
-- cmpup/dn
PROCESS
BEGIN
WAIT UNTIL (rtcalclk'EVENT AND rtcalclk = '0') OR (nclr'EVENT AND nclr = '0');
IF (nclr = '0') THEN
cmpup <= '0';
cmpdn <= '0';
ELSE
cmpup <= rup;
cmpdn <= rdn;
END IF;
END PROCESS;
-- other regisers
PROCESS
BEGIN
WAIT UNTIL (rtcalclk'EVENT AND rtcalclk = '1') OR (clr'EVENT AND clr = '1');
IF (clr = '1') THEN
current_state <= STRATIXIII_RTOCT_WAIT;
switch_region <= '0';
rt_sm_done <= '0';
p_cnt <= "000";
p_cnt_sub <= '0';
n_cnt <= "000";
n_cnt_sub <= '0';
sel_rup_vref_h <= '0';
sel_rup_vref_m <= '1';
sel_rup_vref_l <= '0';
sel_rdn_vref_h <= '0';
sel_rdn_vref_m <= '1';
sel_rdn_vref_l <= '0';
ELSE
current_state <= next_state;
switch_region <= switch_region_d;
rt_sm_done <= rt_sm_done_d;
p_cnt <= p_cnt_d;
p_cnt_sub <= p_cnt_sub_d;
n_cnt <= n_cnt_d;
n_cnt_sub <= n_cnt_sub_d;
sel_rup_vref_h <= sel_rup_vref_h_d;
sel_rup_vref_m <= sel_rup_vref_m_d;
sel_rup_vref_l <= sel_rup_vref_l_d;
sel_rdn_vref_h <= sel_rdn_vref_h_d;
sel_rdn_vref_m <= sel_rdn_vref_m_d;
sel_rdn_vref_l <= sel_rdn_vref_l_d;
END IF;
END PROCESS;
-- state machine
PROCESS(current_state, rtena, cmpup, cmpdn, p_cnt, n_cnt, switch_region)
variable p_cnt_d_var, n_cnt_d_var : std_logic_vector(2 DOWNTO 0);
variable p_cnt_sub_d_var, n_cnt_sub_d_var : std_logic;
BEGIN
p_cnt_d_var := p_cnt;
n_cnt_d_var := n_cnt;
p_cnt_sub_d_var := '0';
n_cnt_sub_d_var := '0';
CASE current_state IS
WHEN STRATIXIII_RTOCT_WAIT =>
IF (rtena = '0') THEN
next_state <= STRATIXIII_RTOCT_WAIT;
ELSE
next_state <= RUP_VREF_M_RDN_VER_M;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '1';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '1';
sel_rdn_vref_l_d <= '0';
END IF;
WHEN RUP_VREF_M_RDN_VER_M =>
IF (cmpup = '0' AND cmpdn = '0') THEN
next_state <= RUP_VREF_L_RDN_VER_L;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '0';
sel_rup_vref_l_d <= '1';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '0';
sel_rdn_vref_l_d <= '1';
ELSE
IF (cmpup = '1' AND cmpdn = '1') THEN
next_state <= RUP_VREF_H_RDN_VER_H;
sel_rup_vref_h_d <= '1';
sel_rup_vref_m_d <= '0';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '1';
sel_rdn_vref_m_d <= '0';
sel_rdn_vref_l_d <= '0';
ELSE
IF (cmpup = '1' AND cmpdn = '0') THEN
next_state <= STRATIXIII_RTOCT_INC_PN;
p_cnt_d_var := p_cnt_d_var + 1;
p_cnt_sub_d_var := '0';
n_cnt_d_var := n_cnt_d_var + 1;
n_cnt_sub_d_var := '0';
ELSE
IF (cmpup = '0' AND cmpdn = '1') THEN
next_state <= STRATIXIII_RTOCT_DEC_PN;
p_cnt_d_var := p_cnt_d_var + 1;
p_cnt_sub_d_var := '1';
n_cnt_d_var := n_cnt_d_var + 1;
n_cnt_sub_d_var := '1';
END IF;
END IF;
END IF;
END IF;
WHEN RUP_VREF_L_RDN_VER_L =>
IF (cmpup = '1' AND cmpdn = '1') THEN
next_state <= STRATIXIII_RTOCT_DONE;
ELSE
IF (cmpup = '0') THEN
next_state <= STRATIXIII_RTOCT_DEC_N;
n_cnt_d_var := n_cnt_d_var + 1;
n_cnt_sub_d_var := '1';
ELSE
IF (cmpup = '1' AND cmpdn = '0') THEN
next_state <= STRATIXIII_RTOCT_INC_P;
p_cnt_d_var := p_cnt_d_var + 1;
p_cnt_sub_d_var := '0';
END IF;
END IF;
END IF;
WHEN RUP_VREF_H_RDN_VER_H =>
IF (cmpup = '0' AND cmpdn = '0') THEN
next_state <= STRATIXIII_RTOCT_DONE;
ELSE
IF (cmpup = '1') THEN
next_state <= STRATIXIII_RTOCT_INC_N;
n_cnt_d_var := n_cnt_d_var + 1;
n_cnt_sub_d_var := '0';
ELSE
IF (cmpup = '0' AND cmpdn = '1') THEN
next_state <= STRATIXIII_RTOCT_DEC_P;
p_cnt_d_var := p_cnt_d_var + 1;
p_cnt_sub_d_var := '1';
END IF;
END IF;
END IF;
WHEN RUP_VREF_L_RDN_VER_H =>
IF (cmpup = '1' AND cmpdn = '0') THEN
next_state <= STRATIXIII_RTOCT_DONE;
ELSE
IF (cmpup = '1' AND switch_region = '1') THEN
next_state <= STRATIXIII_RTOCT_DEC_P;
p_cnt_d_var := p_cnt_d_var + 1;
p_cnt_sub_d_var := '1';
ELSE
IF (cmpup = '0' AND switch_region = '1') THEN
next_state <= STRATIXIII_RTOCT_DEC_N;
n_cnt_d_var := n_cnt_d_var + 1;
n_cnt_sub_d_var := '1';
ELSE
IF ((switch_region = '0') AND (cmpup = '0' OR cmpdn = '1')) THEN
next_state <= STRATIXIII_RTOCT_SWITCH_REG;
switch_region_d <= '1';
END IF;
END IF;
END IF;
END IF;
WHEN RUP_VREF_H_RDN_VER_L =>
IF (cmpup = '0' AND cmpdn = '1') THEN
next_state <= STRATIXIII_RTOCT_DONE;
ELSE
IF (cmpup = '1' AND switch_region = '1') THEN
next_state <= STRATIXIII_RTOCT_INC_N;
n_cnt_d_var := n_cnt_d_var + 1;
n_cnt_sub_d_var := '0';
ELSE
IF (cmpup = '0' AND switch_region = '1') THEN
next_state <= STRATIXIII_RTOCT_INC_P;
p_cnt_d_var := p_cnt_d_var + 1;
p_cnt_sub_d_var := '0';
ELSE
IF ((switch_region = '0') AND (cmpup = '1' OR cmpdn = '0')) THEN
next_state <= STRATIXIII_RTOCT_SWITCH_REG;
switch_region_d <= '1';
END IF;
END IF;
END IF;
END IF;
WHEN STRATIXIII_RTOCT_INC_PN =>
IF (cmpup = '1' AND cmpdn = '0') THEN
next_state <= STRATIXIII_RTOCT_INC_PN;
p_cnt_d_var := p_cnt_d_var + 1;
p_cnt_sub_d_var := '0';
n_cnt_d_var := n_cnt_d_var + 1;
n_cnt_sub_d_var := '0';
ELSE
IF (cmpup = '0' AND cmpdn = '0') THEN
next_state <= RUP_VREF_L_RDN_VER_L;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '0';
sel_rup_vref_l_d <= '1';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '0';
sel_rdn_vref_l_d <= '1';
ELSE
IF (cmpup = '1' AND cmpdn = '1') THEN
next_state <= RUP_VREF_H_RDN_VER_H;
sel_rup_vref_h_d <= '1';
sel_rup_vref_m_d <= '0';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '1';
sel_rdn_vref_m_d <= '0';
sel_rdn_vref_l_d <= '0';
ELSE
IF (cmpup = '0' AND cmpdn = '1') THEN
next_state <= RUP_VREF_L_RDN_VER_H;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '0';
sel_rup_vref_l_d <= '1';
sel_rdn_vref_h_d <= '1';
sel_rdn_vref_m_d <= '0';
sel_rdn_vref_l_d <= '0';
END IF;
END IF;
END IF;
END IF;
WHEN STRATIXIII_RTOCT_DEC_PN =>
IF (cmpup = '0' AND cmpdn = '1') THEN
next_state <= STRATIXIII_RTOCT_DEC_PN;
p_cnt_d_var := p_cnt_d_var + 1;
p_cnt_sub_d_var := '1';
n_cnt_d_var := n_cnt_d_var + 1;
n_cnt_sub_d_var := '1';
ELSE
IF (cmpup = '0' AND cmpdn = '0') THEN
next_state <= RUP_VREF_L_RDN_VER_L;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '0';
sel_rup_vref_l_d <= '1';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '0';
sel_rdn_vref_l_d <= '1';
ELSE
IF (cmpup = '1' AND cmpdn = '1') THEN
next_state <= RUP_VREF_H_RDN_VER_H;
sel_rup_vref_h_d <= '1';
sel_rup_vref_m_d <= '0';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '1';
sel_rdn_vref_m_d <= '0';
sel_rdn_vref_l_d <= '0';
ELSE
IF (cmpup = '1' AND cmpdn = '0') THEN
next_state <= RUP_VREF_H_RDN_VER_L;
sel_rup_vref_h_d <= '1';
sel_rup_vref_m_d <= '0';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '0';
sel_rdn_vref_l_d <= '1';
END IF;
END IF;
END IF;
END IF;
----------------- same action begin
WHEN STRATIXIII_RTOCT_INC_P =>
IF (switch_region = '1') THEN
next_state <= STRATIXIII_RTOCT_DONE;
ELSE
IF (switch_region = '0') THEN
next_state <= RUP_VREF_M_RDN_VER_M;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '1';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '1';
sel_rdn_vref_l_d <= '0';
END IF;
END IF;
WHEN STRATIXIII_RTOCT_DEC_P =>
IF (switch_region = '1') THEN
next_state <= STRATIXIII_RTOCT_DONE;
ELSE
IF (switch_region = '0') THEN
next_state <= RUP_VREF_M_RDN_VER_M;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '1';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '1';
sel_rdn_vref_l_d <= '0';
END IF;
END IF;
WHEN STRATIXIII_RTOCT_INC_N =>
IF (switch_region = '1') THEN
next_state <= STRATIXIII_RTOCT_DONE;
ELSE
IF (switch_region = '0') THEN
next_state <= RUP_VREF_M_RDN_VER_M;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '1';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '1';
sel_rdn_vref_l_d <= '0';
END IF;
END IF;
WHEN STRATIXIII_RTOCT_DEC_N =>
IF (switch_region = '1') THEN
next_state <= STRATIXIII_RTOCT_DONE;
ELSE
IF (switch_region = '0') THEN
next_state <= RUP_VREF_M_RDN_VER_M;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '1';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '1';
sel_rdn_vref_l_d <= '0';
END IF;
END IF;
----------------- same action end
WHEN STRATIXIII_RTOCT_SWITCH_REG =>
next_state <= RUP_VREF_M_RDN_VER_M;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '1';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '1';
sel_rdn_vref_l_d <= '0';
WHEN STRATIXIII_RTOCT_DONE =>
next_state <= STRATIXIII_RTOCT_DONE;
rt_sm_done_d <= '1';
WHEN OTHERS =>
next_state <= STRATIXIII_RTOCT_WAIT;
END CASE;
-- case(current_state)
-- schedule the outputs
p_cnt_d <= p_cnt_d_var;
n_cnt_d <= n_cnt_d_var;
p_cnt_sub_d <= p_cnt_sub_d_var;
n_cnt_sub_d <= n_cnt_sub_d_var;
END PROCESS;
END stratixiii_rt_sm_rtl;
-------------------------------------------------------------------------------
-- Module Name: stratixiii_termination_aux_clock_div
-- Description: auxilary clock divider module
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY stratixiii_termination_aux_clock_div IS
GENERIC (
clk_divide_by : INTEGER := 1;
extra_latency : INTEGER := 0
);
PORT (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC := '0';
clkout : OUT STD_LOGIC
);
END stratixiii_termination_aux_clock_div;
ARCHITECTURE oct_clock_div_arch OF stratixiii_termination_aux_clock_div IS
SIGNAL clk_edges : INTEGER := -1;
SIGNAL div_n_register : STD_LOGIC_VECTOR(2 * extra_latency DOWNTO 0)
:= (OTHERS => '0');
BEGIN
PROCESS(clk,reset)
VARIABLE div_n : STD_LOGIC_VECTOR(2 * extra_latency DOWNTO 0) := (OTHERS => '0');
VARIABLE m : INTEGER := 0;
VARIABLE running_clk_edge : INTEGER := -1;
BEGIN
running_clk_edge := clk_edges;
IF (reset = '1') THEN
clk_edges <= -1;
m := 0;
div_n := (OTHERS => '0');
ELSE
IF (clk'EVENT) THEN
IF (running_clk_edge = -1) THEN
m := 0;
div_n(0) := clk;
IF (clk = '1') THEN running_clk_edge := 0; END IF;
ELSIF (running_clk_edge mod clk_divide_by = 0) THEN
div_n(0) := NOT div_n(0);
END IF;
IF (running_clk_edge >= 0 OR clk = '1') THEN
clk_edges <= (running_clk_edge + 1) mod (2 * clk_divide_by);
END IF;
END IF;
END IF;
m := 0;
div_n_register(m) <= div_n(m);
WHILE (m < 2 * extra_latency) LOOP
div_n_register(m+1) <= div_n_register(m);
m := m + 1;
END LOOP;
END PROCESS;
clkout <= div_n_register(2 * extra_latency);
END oct_clock_div_arch;
-------------------------------------------------------------------------------
--
-- Module Name : stratixiii_termination
--
-- Description : Stratix III Termination Atom
-- Verilog simulation model
--
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.ALL;
USE IEEE.VITAL_Primitives.ALL;
use work.stratixiii_atom_pack.all;
USE WORK.stratixiii_termination_aux_clock_div;
USE WORK.stratixiii_rt_sm;
ENTITY stratixiii_termination IS
GENERIC (
runtime_control : STRING := "false";
allow_serial_data_from_core : STRING := "false";
power_down : STRING := "true";
enable_parallel_termination : STRING := "false";
test_mode : STRING := "false";
enable_calclk_divider : STRING := "false"; -- replaced by below
clock_divider_enable : STRING := "false";
enable_pwrupmode_enser_for_usrmode : STRING := "false";
bypass_enser_logic : STRING := "false";
bypass_rt_calclk : STRING := "false";
enable_rt_scan_mode : STRING := "false";
enable_loopback : STRING := "false";
force_rtcalen_for_pllbiasen : STRING := "false";
enable_rt_sm_loopback : STRING := "false";
select_vrefl_values : integer := 0;
select_vrefh_values : integer := 0;
divide_intosc_by : integer := 2;
use_usrmode_clear_for_configmode : STRING := "false";
tipd_rup : VitalDelayType01 := DefpropDelay01;
tipd_rdn : VitalDelayType01 := DefpropDelay01;
tipd_terminationclock : VitalDelayType01 := DefpropDelay01;
tipd_terminationclear : VitalDelayType01 := DefpropDelay01;
tipd_terminationenable : VitalDelayType01 := DefpropDelay01;
tipd_serializerenable : VitalDelayType01 := DefpropDelay01;
tipd_terminationcontrolin : VitalDelayType01 := DefpropDelay01;
tipd_otherserializerenable : VitalDelayArrayType01(8 downto 0) := (OTHERS => DefPropDelay01);
lpm_type : STRING := "stratixiii_termination");
PORT (
rup : IN std_logic := '0';
rdn : IN std_logic := '0';
terminationclock : IN std_logic := '0';
terminationclear : IN std_logic := '0';
terminationenable : IN std_logic := '1';
serializerenable : IN std_logic := '0';
terminationcontrolin : IN std_logic := '0';
scanin : IN std_logic := '0';
scanen : IN std_logic := '0';
otherserializerenable : IN std_logic_vector(8 DOWNTO 0) := (OTHERS => '0');
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
incrup : OUT std_logic;
incrdn : OUT std_logic;
serializerenableout : OUT std_logic;
terminationcontrol : OUT std_logic;
terminationcontrolprobe : OUT std_logic;
scanout : OUT std_logic;
shiftregisterprobe : OUT std_logic);
END stratixiii_termination;
ARCHITECTURE stratixiii_oct_arch OF stratixiii_termination IS
COMPONENT stratixiii_termination_aux_clock_div
GENERIC (
clk_divide_by : INTEGER := 1;
extra_latency : INTEGER := 0
);
PORT (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC := '0';
clkout : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT stratixiii_rt_sm
PORT (
rup : IN std_logic;
rdn : IN std_logic;
clk : IN std_logic;
clken : IN std_logic;
clr : IN std_logic;
rtena : IN std_logic;
rscaldone : IN std_logic;
rtoffsetp : OUT std_logic_vector(3 DOWNTO 0);
rtoffsetn : OUT std_logic_vector(3 DOWNTO 0);
caldone : OUT std_logic;
sel_rup_vref : OUT std_logic_vector(2 DOWNTO 0);
sel_rdn_vref : OUT std_logic_vector(2 DOWNTO 0)
);
END COMPONENT;
-- HW outputs
SIGNAL compout_rup_core : std_logic;
SIGNAL compout_rdn_core : std_logic;
SIGNAL ser_data_io : std_logic;
SIGNAL ser_data_core : std_logic;
-- HW inputs
SIGNAL usr_clk : std_logic;
SIGNAL cal_clk : std_logic;
SIGNAL rscal_clk : std_logic;
SIGNAL cal_clken : std_logic;
SIGNAL cal_nclr : std_logic;
-- legality check on enser
SIGNAL enser_checked : std_logic := '0';
-- Shift Register
SIGNAL sreg_bit_out : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
SIGNAL sreg_bit_out_tmp0 : std_logic := '0';
SIGNAL sreg_vshift_bit_tmp : std_logic := '0';
SIGNAL sreg_vshift_bit_out : std_logic := '0';
SIGNAL sreg_rscaldone_prev : std_logic := '0';
SIGNAL sreg_rscaldone_prev1 : std_logic := '0';
SIGNAL sregn_rscaldone_out : std_logic := '0';
SIGNAL sreg_bit6_prev : std_logic := '1';
-- nreg before SA-ADC
SIGNAL regn_rup_in : std_logic;
SIGNAL regn_rdn_in : std_logic;
SIGNAL regn_compout_rup : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
SIGNAL regn_compout_rdn : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
-- SA-ADC
SIGNAL sa_octcaln_out : std_logic_vector(6 DOWNTO 0); -- RUP - NMOS
SIGNAL sa_octcalp_out : std_logic_vector(6 DOWNTO 0); -- RDN - PMOS
SIGNAL sa_octcaln_in : std_logic_vector(6 DOWNTO 0);
SIGNAL sa_octcalp_in : std_logic_vector(6 DOWNTO 0);
-- ENSER
SIGNAL enser_out : std_logic;
SIGNAL enser_gen_out : std_logic;
SIGNAL enser_cnt : INTEGER := 0;
-- RT State Machine
SIGNAL rtsm_rup_in : std_logic;
SIGNAL rtsm_rdn_in : std_logic;
SIGNAL rtsm_rtena_in : std_logic;
SIGNAL rtsm_rscaldone_in : std_logic;
SIGNAL rtsm_caldone_out : std_logic;
SIGNAL rtsm_rtoffsetp_out : std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL rtsm_rtoffsetn_out : std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL rtsm_sel_rup_vref_out : std_logic_vector(2 DOWNTO 0) := (OTHERS => '0');
SIGNAL rtsm_sel_rdn_vref_out : std_logic_vector(2 DOWNTO 0) := (OTHERS => '0');
-- RT Adder/Sub
SIGNAL rtas_rs_rpcdp_in : std_logic_vector(6 DOWNTO 0);
SIGNAL rtas_rs_rpcdn_in : std_logic_vector(6 DOWNTO 0);
SIGNAL rtas_rtoffsetp_in : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
SIGNAL rtas_rtoffsetn_in : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
SIGNAL rtas_rs_rpcdp_out : std_logic_vector(6 DOWNTO 0);
SIGNAL rtas_rs_rpcdn_out : std_logic_vector(6 DOWNTO 0);
SIGNAL rtas_rt_rpcdp_out : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
SIGNAL rtas_rt_rpcdn_out : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
-- P2S
SIGNAL p2s_rs_rpcdp_in : std_logic_vector(6 DOWNTO 0);
SIGNAL p2s_rs_rpcdn_in : std_logic_vector(6 DOWNTO 0);
SIGNAL p2s_rt_rpcdp_in : std_logic_vector(6 DOWNTO 0);
SIGNAL p2s_rt_rpcdn_in : std_logic_vector(6 DOWNTO 0);
SIGNAL p2s_enser_in : std_logic;
SIGNAL p2s_clk_in : std_logic;
SIGNAL p2s_ser_data_out : std_logic;
SIGNAL p2s_parallel_reg : std_logic_vector(27 DOWNTO 0) := (OTHERS => '0');
SIGNAL p2s_serial_reg : std_logic := '0';
SIGNAL p2s_index : integer := 27;
-- used to set SA outputs
SIGNAL temp_xhdl10 : std_logic;
SIGNAL temp_xhdl12 : std_logic;
SIGNAL temp_xhdl14 : std_logic;
SIGNAL temp_xhdl16 : std_logic;
SIGNAL temp_xhdl18 : std_logic;
SIGNAL temp_xhdl20 : std_logic;
SIGNAL temp_xhdl22 : std_logic;
SIGNAL temp_xhdl24 : std_logic;
SIGNAL temp_xhdl26 : std_logic;
SIGNAL temp_xhdl28 : std_logic;
SIGNAL temp_xhdl30 : std_logic;
SIGNAL temp_xhdl32 : std_logic;
SIGNAL temp_xhdl34 : std_logic;
SIGNAL temp_xhdl36 : std_logic;
SIGNAL MY_GND : std_logic := '0';
-- timing
SIGNAL rup_ipd : std_logic;
SIGNAL rdn_ipd : std_logic;
SIGNAL terminationclock_ipd : std_logic;
SIGNAL terminationclear_ipd : std_logic;
SIGNAL terminationenable_ipd : std_logic;
SIGNAL serializerenable_ipd : std_logic;
SIGNAL terminationcontrolin_ipd : std_logic;
SIGNAL otherserializerenable_ipd : std_logic_vector(8 DOWNTO 0);
BEGIN
-- primary outputs
incrup <= terminationenable_ipd WHEN (enable_loopback = "true") ELSE compout_rup_core;
incrdn <= terminationclear_ipd WHEN (enable_loopback = "true") ELSE compout_rdn_core;
terminationcontrol <= ser_data_io;
terminationcontrolprobe <= serializerenable_ipd WHEN (enable_loopback = "true") ELSE ser_data_core;
shiftregisterprobe <= terminationclock_ipd WHEN (enable_loopback = "true") ELSE sreg_vshift_bit_out;
serializerenableout <= serializerenable;
compout_rup_core <= rup ;
compout_rdn_core <= rdn ;
ser_data_io <= terminationcontrolin WHEN (allow_serial_data_from_core = "true") ELSE p2s_ser_data_out;
ser_data_core <= p2s_ser_data_out ;
-- primary inputs
usr_clk <= terminationclock ;
cal_nclr <= '1' WHEN (terminationclear = '1') ELSE '0';
cal_clken <= '1' WHEN (terminationenable = '1' AND serializerenable = '1') ELSE '0';
-- divide by 100 clock
m_gen_calclk : stratixiii_termination_aux_clock_div
GENERIC MAP (
clk_divide_by => 100,
extra_latency => 0)
PORT MAP (
clk => usr_clk,
reset => MY_GND,
clkout => cal_clk);
rscal_clk <= cal_clk AND (NOT sregn_rscaldone_out) ;
-- legality check on enser
PROCESS
BEGIN
WAIT UNTIL (usr_clk'EVENT AND usr_clk = '1');
IF (serializerenable = '1' AND cal_clken = '0') THEN
IF (otherserializerenable(0) = '1' OR
otherserializerenable(1) = '1' OR
otherserializerenable(2) = '1' OR
otherserializerenable(3) = '1' OR
otherserializerenable(4) = '1' OR
otherserializerenable(5) = '1' OR
otherserializerenable(6) = '1' OR
otherserializerenable(7) = '1' OR
otherserializerenable(8) = '1') THEN
IF (enser_checked = '0') THEN
assert false
report "serializizerable and some bits of otherserializerenable are asserted at data transfer time"
severity warning;
enser_checked <= '1';
END IF;
ELSE
enser_checked <= '0'; -- for another check
END IF;
ELSE
enser_checked <= '0'; -- for another check
END IF;
END PROCESS;
-- SHIFT regiter
PROCESS
BEGIN
WAIT UNTIL (rscal_clk'EVENT AND rscal_clk = '1') OR (cal_nclr'EVENT AND cal_nclr = '1');
IF (cal_nclr = '1') THEN
sreg_bit6_prev <= '1';
sreg_bit_out <= "0000000";
sreg_vshift_bit_out <= '0';
sreg_vshift_bit_tmp <= '0';
sreg_bit_out_tmp0 <= '0';
sreg_rscaldone_prev <= '0';
sreg_rscaldone_prev1 <= '0';
ELSE
IF (cal_clken = '1') THEN
sreg_bit_out(6) <= sreg_bit6_prev;
sreg_bit_out(5) <= sreg_bit_out(6);
sreg_bit_out(4) <= sreg_bit_out(5);
sreg_bit_out(3) <= sreg_bit_out(4);
sreg_bit_out(2) <= sreg_bit_out(3);
sreg_bit_out(1) <= sreg_bit_out(2);
sreg_bit_out_tmp0 <= sreg_bit_out(1);
sreg_vshift_bit_tmp <= sreg_bit_out_tmp0;
sreg_bit_out(0) <= sreg_bit_out(1) OR sreg_vshift_bit_tmp;
sreg_vshift_bit_out <= sreg_bit_out_tmp0 OR sreg_vshift_bit_tmp;
sreg_bit6_prev <= '0';
END IF;
END IF;
-- might falling outside of 10 cycles
IF (sreg_vshift_bit_tmp = '1') THEN
sreg_rscaldone_prev <= '1';
END IF;
sreg_rscaldone_prev1 <= sreg_rscaldone_prev;
END PROCESS;
PROCESS
BEGIN
WAIT UNTIL (rscal_clk'EVENT AND rscal_clk = '0') OR (cal_nclr'EVENT AND cal_nclr = '1');
IF (cal_nclr = '1') THEN
sregn_rscaldone_out <= '0';
ELSE -- if (cal_clken == 1'b1) - outside of 10 cycles
IF (sreg_rscaldone_prev1 = '1' AND sregn_rscaldone_out = '0') THEN
sregn_rscaldone_out <= '1';
END IF;
END IF;
END PROCESS;
-- nreg and SA-ADC:
--
-- RDN_vol < ref_voltage < RUP_voltage
-- after reset, ref_voltage=VCCN/2; after ref_voltage_shift, ref_voltage=neighbor(VCCN/2)
-- at 0 code, RUP=VCCN so voltage_compare_out for RUP = 0
-- RDN=GND so voltage compare out for RDN = 0
regn_rup_in <= rup ;
regn_rdn_in <= rdn ;
PROCESS
BEGIN
WAIT UNTIL (cal_nclr'EVENT AND cal_nclr = '1') OR (rscal_clk'EVENT AND rscal_clk = '0');
IF (cal_nclr = '1') THEN
regn_compout_rup <= "0000000";
regn_compout_rdn <= "0000000";
ELSE
-- rup
IF (sreg_bit_out(0) = '1') THEN
regn_compout_rup(0) <= regn_rup_in;
END IF;
IF (sreg_bit_out(1) = '1') THEN
regn_compout_rup(1) <= regn_rup_in;
END IF;
IF (sreg_bit_out(2) = '1') THEN
regn_compout_rup(2) <= regn_rup_in;
END IF;
IF (sreg_bit_out(3) = '1') THEN
regn_compout_rup(3) <= regn_rup_in;
END IF;
IF (sreg_bit_out(4) = '1') THEN
regn_compout_rup(4) <= regn_rup_in;
END IF;
IF (sreg_bit_out(5) = '1') THEN
regn_compout_rup(5) <= regn_rup_in;
END IF;
IF (sreg_bit_out(6) = '1') THEN
regn_compout_rup(6) <= regn_rup_in;
END IF;
-- rdn
IF (sreg_bit_out(0) = '1') THEN
regn_compout_rdn(0) <= regn_rdn_in;
END IF;
IF (sreg_bit_out(1) = '1') THEN
regn_compout_rdn(1) <= regn_rdn_in;
END IF;
IF (sreg_bit_out(2) = '1') THEN
regn_compout_rdn(2) <= regn_rdn_in;
END IF;
IF (sreg_bit_out(3) = '1') THEN
regn_compout_rdn(3) <= regn_rdn_in;
END IF;
IF (sreg_bit_out(4) = '1') THEN
regn_compout_rdn(4) <= regn_rdn_in;
END IF;
IF (sreg_bit_out(5) = '1') THEN
regn_compout_rdn(5) <= regn_rdn_in;
END IF;
IF (sreg_bit_out(6) = '1') THEN
regn_compout_rdn(6) <= regn_rdn_in;
END IF;
END IF;
END PROCESS;
sa_octcaln_in <= sreg_bit_out ;
sa_octcalp_in <= sreg_bit_out ;
-- RUP - octcaln_in == 1 = (pin_voltage < ref_voltage): clear the bit setting
temp_xhdl10 <= '1' WHEN (sa_octcaln_in(0) = '1') ELSE sa_octcaln_out(0);
sa_octcaln_out(0) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(0) = '1') ELSE temp_xhdl10;
temp_xhdl12 <= '1' WHEN (sa_octcaln_in(1) = '1') ELSE sa_octcaln_out(1);
sa_octcaln_out(1) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(1) = '1') ELSE temp_xhdl12;
temp_xhdl14 <= '1' WHEN (sa_octcaln_in(2) = '1') ELSE sa_octcaln_out(2);
sa_octcaln_out(2) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(2) = '1') ELSE temp_xhdl14;
temp_xhdl16 <= '1' WHEN (sa_octcaln_in(3) = '1') ELSE sa_octcaln_out(3);
sa_octcaln_out(3) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(3) = '1') ELSE temp_xhdl16;
temp_xhdl18 <= '1' WHEN (sa_octcaln_in(4) = '1') ELSE sa_octcaln_out(4);
sa_octcaln_out(4) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(4) = '1') ELSE temp_xhdl18;
temp_xhdl20 <= '1' WHEN (sa_octcaln_in(5) = '1') ELSE sa_octcaln_out(5);
sa_octcaln_out(5) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(5) = '1') ELSE temp_xhdl20;
temp_xhdl22 <= '1' WHEN (sa_octcaln_in(6) = '1') ELSE sa_octcaln_out(6);
sa_octcaln_out(6) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(6) = '1') ELSE temp_xhdl22;
temp_xhdl24 <= '1' WHEN (sa_octcalp_in(0) = '1') ELSE sa_octcalp_out(0);
sa_octcalp_out(0) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(0) = '1') ELSE temp_xhdl24;
temp_xhdl26 <= '1' WHEN (sa_octcalp_in(1) = '1') ELSE sa_octcalp_out(1);
sa_octcalp_out(1) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(1) = '1') ELSE temp_xhdl26;
temp_xhdl28 <= '1' WHEN (sa_octcalp_in(2) = '1') ELSE sa_octcalp_out(2);
sa_octcalp_out(2) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(2) = '1') ELSE temp_xhdl28;
temp_xhdl30 <= '1' WHEN (sa_octcalp_in(3) = '1') ELSE sa_octcalp_out(3);
sa_octcalp_out(3) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(3) = '1') ELSE temp_xhdl30;
temp_xhdl32 <= '1' WHEN (sa_octcalp_in(4) = '1') ELSE sa_octcalp_out(4);
sa_octcalp_out(4) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(4) = '1') ELSE temp_xhdl32;
temp_xhdl34 <= '1' WHEN (sa_octcalp_in(5) = '1') ELSE sa_octcalp_out(5);
sa_octcalp_out(5) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(5) = '1') ELSE temp_xhdl34;
temp_xhdl36 <= '1' WHEN (sa_octcalp_in(6) = '1') ELSE sa_octcalp_out(6);
sa_octcalp_out(6) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(6) = '1') ELSE temp_xhdl36;
-- ENSER
enser_out <= serializerenable WHEN (runtime_control = "true" OR bypass_enser_logic = "true") ELSE enser_gen_out;
enser_gen_out <= '1' WHEN (enser_cnt > 0 AND enser_cnt < 31) ELSE '0';
PROCESS
BEGIN
WAIT UNTIL (usr_clk'EVENT AND usr_clk = '1') OR (sregn_rscaldone_out'EVENT AND sregn_rscaldone_out = '1');
IF (sregn_rscaldone_out = '0') THEN
enser_cnt <= 0;
ELSE
IF (enser_cnt < 63) THEN
enser_cnt <= enser_cnt + 1;
END IF;
END IF;
END PROCESS;
-- RT SM
rtsm_rup_in <= rup ;
rtsm_rdn_in <= rdn ;
rtsm_rtena_in <= '1' WHEN (enable_parallel_termination = "true") ELSE '0';
rtsm_rscaldone_in <= sregn_rscaldone_out ;
m_rt_sm : stratixiii_rt_sm
PORT MAP (
rup => rtsm_rup_in,
rdn => rtsm_rdn_in,
clk => cal_clk,
clken => cal_clken,
clr => cal_nclr,
rtena => rtsm_rtena_in,
rscaldone => rtsm_rscaldone_in,
rtoffsetp => rtsm_rtoffsetp_out,
rtoffsetn => rtsm_rtoffsetn_out,
caldone => rtsm_caldone_out,
sel_rup_vref => rtsm_sel_rup_vref_out,
sel_rdn_vref => rtsm_sel_rdn_vref_out
);
-- RT Adder/Sub
rtas_rs_rpcdp_in <= sa_octcalp_out ;
rtas_rs_rpcdn_in <= sa_octcaln_out ;
rtas_rtoffsetp_in <= "0000" & rtsm_rtoffsetp_out(2 DOWNTO 0);
rtas_rtoffsetn_in <="0000" & rtsm_rtoffsetn_out(2 DOWNTO 0);
rtas_rs_rpcdp_out <= rtas_rs_rpcdp_in ;
rtas_rs_rpcdn_out <= rtas_rs_rpcdn_in ;
rtas_rt_rpcdn_out <= (rtas_rs_rpcdn_in + rtas_rtoffsetn_in) WHEN (rtsm_rtoffsetn_out(3) = '0') ELSE
(rtas_rs_rpcdn_in - rtas_rtoffsetn_in);
rtas_rt_rpcdp_out <= (rtas_rs_rpcdp_in + rtas_rtoffsetp_in) WHEN (rtsm_rtoffsetp_out(3) = '0') ELSE
(rtas_rs_rpcdp_in - rtas_rtoffsetp_in);
-- P2S
p2s_rs_rpcdp_in <= rtas_rs_rpcdp_out ;
p2s_rs_rpcdn_in <= rtas_rs_rpcdn_out ;
p2s_rt_rpcdp_in <= rtas_rt_rpcdp_out;
p2s_rt_rpcdn_in <= rtas_rt_rpcdn_out;
p2s_enser_in <= enser_out ;
p2s_clk_in <= usr_clk ;
p2s_ser_data_out <= p2s_serial_reg ;
-- load - clken
PROCESS
BEGIN
WAIT UNTIL (p2s_clk_in'EVENT AND p2s_clk_in = '1') OR (cal_nclr'EVENT AND cal_nclr = '1');
IF (cal_nclr = '1') THEN
p2s_parallel_reg <= "0000000000000000000000000000";
ELSE
IF (cal_clken = '1') THEN
p2s_parallel_reg <= p2s_rs_rpcdp_in & p2s_rs_rpcdn_in & p2s_rt_rpcdp_in & p2s_rt_rpcdn_in;
END IF;
END IF;
END PROCESS;
-- shift - enser
PROCESS
BEGIN
WAIT UNTIL (p2s_clk_in'EVENT AND p2s_clk_in = '1') OR (cal_nclr'EVENT AND cal_nclr = '1');
IF (cal_nclr = '1') THEN
p2s_serial_reg <= '0';
p2s_index <= 27;
ELSE
IF (p2s_enser_in = '1' AND cal_clken = '0') THEN
p2s_serial_reg <= p2s_parallel_reg(p2s_index);
IF (p2s_index > 0) THEN
p2s_index <= p2s_index - 1;
END IF;
END IF;
END IF;
END PROCESS;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (rup_ipd, rup, tipd_rup);
VitalWireDelay (rdn_ipd, rdn, tipd_rdn);
VitalWireDelay (terminationclock_ipd, terminationclock, tipd_terminationclock);
VitalWireDelay (terminationclear_ipd, terminationclear, tipd_terminationclear);
VitalWireDelay (terminationenable_ipd, terminationenable, tipd_terminationenable);
VitalWireDelay (serializerenable_ipd, serializerenable, tipd_serializerenable);
VitalWireDelay (terminationcontrolin_ipd, terminationcontrolin, tipd_terminationcontrolin);
VitalWireDelay (otherserializerenable_ipd(0), otherserializerenable(0), tipd_otherserializerenable(0));
VitalWireDelay (otherserializerenable_ipd(1), otherserializerenable(1), tipd_otherserializerenable(1));
VitalWireDelay (otherserializerenable_ipd(2), otherserializerenable(2), tipd_otherserializerenable(2));
VitalWireDelay (otherserializerenable_ipd(3), otherserializerenable(3), tipd_otherserializerenable(3));
VitalWireDelay (otherserializerenable_ipd(4), otherserializerenable(4), tipd_otherserializerenable(4));
VitalWireDelay (otherserializerenable_ipd(5), otherserializerenable(5), tipd_otherserializerenable(5));
VitalWireDelay (otherserializerenable_ipd(6), otherserializerenable(6), tipd_otherserializerenable(6));
VitalWireDelay (otherserializerenable_ipd(7), otherserializerenable(7), tipd_otherserializerenable(7));
VitalWireDelay (otherserializerenable_ipd(8), otherserializerenable(8), tipd_otherserializerenable(8));
end block;
END stratixiii_oct_arch;
-------------------------------------------------------------------------------
--
-- Module Name : stratixiii_termination_logic
--
-- Description : Stratix III Termination Logic Atom
-- Verilog simulation model
--
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.VITAL_Timing.ALL;
USE IEEE.VITAL_Primitives.ALL;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_termination_logic IS
GENERIC (
tipd_serialloadenable : VitalDelayType01 := DefpropDelay01;
tipd_terminationclock : VitalDelayType01 := DefpropDelay01;
tipd_parallelloadenable : VitalDelayType01 := DefpropDelay01;
tipd_terminationdata : VitalDelayType01 := DefpropDelay01;
test_mode : string := "false";
lpm_type : string := "stratixiii_termination_logic");
PORT (
serialloadenable : IN std_logic := '0';
terminationclock : IN std_logic := '0';
parallelloadenable : IN std_logic := '0';
terminationdata : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
seriesterminationcontrol : OUT std_logic_vector(13 DOWNTO 0);
parallelterminationcontrol : OUT std_logic_vector(13 DOWNTO 0));
END stratixiii_termination_logic;
ARCHITECTURE stratixiii_oct_logic_arch OF stratixiii_termination_logic IS
CONSTANT xhdl_timescale : time := 1 ps;
SIGNAL usr_clk : std_logic;
SIGNAL rs_reg : std_logic_vector(13 DOWNTO 0) := (OTHERS => '0');
SIGNAL rt_reg : std_logic_vector(13 DOWNTO 0) := (OTHERS => '0');
SIGNAL hold_reg : std_logic_vector(27 DOWNTO 0) := (OTHERS => '0');
SIGNAL shift_index : integer := 27;
-- timing
SIGNAL serialloadenable_ipd : std_logic;
SIGNAL terminationclock_ipd : std_logic;
SIGNAL parallelloadenable_ipd : std_logic;
SIGNAL terminationdata_ipd : std_logic;
BEGIN
seriesterminationcontrol <= rs_reg;
parallelterminationcontrol <= rt_reg;
usr_clk <= terminationclock AFTER 11 * xhdl_timescale;
PROCESS
BEGIN
WAIT UNTIL (usr_clk'EVENT AND usr_clk = '1');
IF (serialloadenable = '0') THEN
shift_index <= 27;
ELSE
hold_reg(shift_index) <= terminationdata;
IF (shift_index > 0) THEN
shift_index <= shift_index - 1;
END IF;
END IF;
END PROCESS;
PROCESS
BEGIN
WAIT UNTIL (parallelloadenable'EVENT AND parallelloadenable = '1');
IF (parallelloadenable = '1') THEN
rs_reg <= hold_reg(27 DOWNTO 14);
rt_reg <= hold_reg(13 DOWNTO 0);
END IF;
END PROCESS;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (serialloadenable_ipd, serialloadenable, tipd_serialloadenable);
VitalWireDelay (terminationclock_ipd, terminationclock, tipd_terminationclock);
VitalWireDelay (parallelloadenable_ipd, parallelloadenable, tipd_parallelloadenable);
VitalWireDelay (terminationdata_ipd, terminationdata, tipd_terminationdata);
end block;
END stratixiii_oct_logic_arch;
-------------------------------------------------------------------------------
-- utilities common for ddr
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package stratixiii_atom_ddr_pack is
function dll_unsigned2bin (in_int : integer) return std_logic_vector;
end stratixiii_atom_ddr_pack;
library IEEE;
use IEEE.std_logic_1164.all;
package body stratixiii_atom_ddr_pack is
-- truncate input integer to get 6 LSB bits
function dll_unsigned2bin (in_int : integer) return std_logic_vector is
variable tmp_int, i : integer;
variable tmp_bit : integer;
variable result : std_logic_vector(5 downto 0) := "000000";
begin
tmp_int := in_int;
for i in 0 to 5 loop
tmp_bit := tmp_int MOD 2;
if (tmp_bit = 1) then
result(i) := '1';
else
result(i) := '0';
end if;
tmp_int := tmp_int/2;
end loop;
return result;
end dll_unsigned2bin;
end stratixiii_atom_ddr_pack;
-------------------------------------------------------------------------------
-- auxilary module for ddr
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
ENTITY stratixiii_dll_gray_encoder IS
GENERIC ( width : integer := 6 );
PORT ( mbin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
gout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END stratixiii_dll_gray_encoder;
ARCHITECTURE stratixiii_dll_gray_encoder_arch OF stratixiii_dll_gray_encoder IS
SIGNAL greg : STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
gout <= greg;
PROCESS(mbin)
VARIABLE i : INTEGER := 0;
BEGIN
greg(width-1) <= mbin(width-1);
IF (width > 1) THEN
i := width - 2;
WHILE (i >= 0) LOOP
greg(i) <= mbin(i+1) XOR mbin(i);
i := i - 1;
END LOOP;
END IF;
END PROCESS;
END stratixiii_dll_gray_encoder_arch;
-------------------------------------------------------------------------------
-- auxilary module for ddr
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
ENTITY stratixiii_dll_gray_decoder IS
GENERIC ( width : integer := 6 );
PORT ( gin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
bout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END stratixiii_dll_gray_decoder;
ARCHITECTURE stratixiii_dll_gray_decoder_arch OF stratixiii_dll_gray_decoder IS
SIGNAL breg : STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
bout <= breg;
PROCESS(gin)
VARIABLE i : INTEGER := 0;
VARIABLE bvar : STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
bvar(width-1) := gin(width-1);
IF (width > 1) THEN
i := width - 2;
WHILE (i >= 0) LOOP
bvar(i) := bvar(i+1) XOR gin(i);
i := i - 1;
END LOOP;
END IF;
breg <= bvar;
END PROCESS;
END stratixiii_dll_gray_decoder_arch;
-------------------------------------------------------------------------------
-- Module Name: stratixiii_ddr_delay_chain_s
-- Description: auxilary module - delay chain-setting
-------------------------------------------------------------------------------
Library ieee;
use ieee.std_logic_1164.all;
use work.stratixiii_atom_pack.all;
use work.stratixiii_dll_gray_decoder;
ENTITY stratixiii_ddr_delay_chain_s IS
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
phasectrlin_limit : integer := 7
);
PORT (
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 DOWNTO 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
delayed_clkout : OUT std_logic
);
END stratixiii_ddr_delay_chain_s;
ARCHITECTURE stratixiii_ddr_delay_chain_s_arch OF stratixiii_ddr_delay_chain_s IS
COMPONENT stratixiii_dll_gray_decoder
GENERIC ( width : integer := 6 );
PORT ( gin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
bout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END COMPONENT;
SIGNAL clk_delay : INTEGER := 0;
SIGNAL delayed_clk : STD_LOGIC := '0';
SIGNAL delayctrl_bin : STD_LOGIC_VECTOR (5 DOWNTO 0) := (OTHERS => '0');
SIGNAL delayctrlin_in : STD_LOGIC_VECTOR (5 DOWNTO 0) := (OTHERS => '0');
SIGNAL phasectrlin_in : STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0');
BEGIN
delayctrlin_in(0) <= '1' WHEN (delayctrlin(0) = '1') ELSE '0';
delayctrlin_in(1) <= '1' WHEN (delayctrlin(1) = '1') ELSE '0';
delayctrlin_in(2) <= '1' WHEN (delayctrlin(2) = '1') ELSE '0';
delayctrlin_in(3) <= '1' WHEN (delayctrlin(3) = '1') ELSE '0';
delayctrlin_in(4) <= '1' WHEN (delayctrlin(4) = '1') ELSE '0';
delayctrlin_in(5) <= '1' WHEN (delayctrlin(5) = '1') ELSE '0';
phasectrlin_in(0) <= '1' WHEN (phasectrlin(0) = '1') ELSE '0';
phasectrlin_in(1) <= '1' WHEN (phasectrlin(1) = '1') ELSE '0';
phasectrlin_in(2) <= '1' WHEN (phasectrlin(2) = '1') ELSE '0';
phasectrlin_in(3) <= '1' WHEN (phasectrlin(3) = '1') ELSE '0';
-- decoder
mdr_delayctrl_in_dec : stratixiii_dll_gray_decoder
GENERIC MAP (width => 6)
PORT MAP (gin => delayctrlin_in, bout => delayctrl_bin);
PROCESS(delayctrl_bin, phasectrlin_in)
variable sim_intrinsic_delay : INTEGER := 0;
variable acell_delay : INTEGER := 0;
variable delay_chain_len : INTEGER := 0;
BEGIN
IF (delay_buffer_mode = "low") THEN
sim_intrinsic_delay := sim_low_buffer_intrinsic_delay;
ELSE
sim_intrinsic_delay := sim_high_buffer_intrinsic_delay;
END IF;
-- cell
acell_delay := sim_intrinsic_delay + alt_conv_integer(delayctrl_bin) * sim_buffer_delay_increment;
-- no of cells
IF (use_phasectrlin = "false") THEN
delay_chain_len := phase_setting;
ELSIF (alt_conv_integer(phasectrlin_in) > phasectrlin_limit) THEN
delay_chain_len := 0;
ELSE
delay_chain_len := alt_conv_integer(phasectrlin_in);
END IF;
-- total delay - added extra 1 ps for resolving racing
clk_delay <= delay_chain_len * acell_delay + 1;
IF ((use_phasectrlin = "true") AND (alt_conv_integer(phasectrlin_in) > phasectrlin_limit)) THEN
assert false report "Warning: DDR phasesetting has invalid phasectrlin setting" severity warning;
END IF;
END PROCESS; -- generating delays
delayed_clk <= transport clk after (clk_delay * 1 ps);
delayed_clkout <= delayed_clk;
END stratixiii_ddr_delay_chain_s_arch;
-------------------------------------------------------------------------------
-- based on dffeas
-------------------------------------------------------------------------------
Library ieee;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
entity stratixiii_ddr_io_reg is
generic(
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port(
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of stratixiii_ddr_io_reg : entity is TRUE;
end stratixiii_ddr_io_reg;
architecture vital_titan_ddr_io_reg of stratixiii_ddr_io_reg is
attribute VITAL_LEVEL0 of vital_titan_ddr_io_reg : architecture is TRUE;
signal clk_ipd : std_logic;
signal d_ipd : std_logic;
signal d_dly : std_logic;
signal asdata_ipd : std_logic;
signal asdata_dly : std_logic;
signal asdata_dly1 : std_logic;
signal sclr_ipd : std_logic;
signal sload_ipd : std_logic;
signal clrn_ipd : std_logic;
signal prn_ipd : std_logic;
signal aload_ipd : std_logic;
signal ena_ipd : std_logic;
begin
d_dly <= d_ipd;
asdata_dly <= asdata_ipd;
asdata_dly1 <= asdata_dly;
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (asdata_ipd, asdata, tipd_asdata);
VitalWireDelay (sclr_ipd, sclr, tipd_sclr);
VitalWireDelay (sload_ipd, sload, tipd_sload);
VitalWireDelay (clrn_ipd, clrn, tipd_clrn);
VitalWireDelay (prn_ipd, prn, tipd_prn);
VitalWireDelay (aload_ipd, aload, tipd_aload);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process ( clk_ipd, d_dly, asdata_dly1,
sclr_ipd, sload_ipd, clrn_ipd, prn_ipd, aload_ipd,
ena_ipd, devclrn, devpor)
variable Tviol_d_clk : std_ulogic := '0';
variable Tviol_asdata_clk : std_ulogic := '0';
variable Tviol_sclr_clk : std_ulogic := '0';
variable Tviol_sload_clk : std_ulogic := '0';
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_asdata_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sclr_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable iq : std_logic := '0';
variable idata: std_logic := '0';
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
if (now = 0 ns) then
if ((power_up = "low") or (power_up = "DONT_CARE")) then
iq := '0';
elsif (power_up = "high") then
iq := '1';
else
iq := '0';
end if;
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT clrn_ipd) OR
(NOT prn_ipd) OR
(sload_ipd) OR
(sclr_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/stratixiii_ddr_io_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_asdata_clk,
TimingData => TimingData_asdata_clk,
TestSignal => asdata_ipd,
TestSignalName => "ASDATA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_asdata_clk_noedge_posedge,
SetupLow => tsetup_asdata_clk_noedge_posedge,
HoldHigh => thold_asdata_clk_noedge_posedge,
HoldLow => thold_asdata_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT clrn_ipd) OR
(NOT prn_ipd) OR
(NOT sload_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/stratixiii_ddr_io_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sclr_clk,
TimingData => TimingData_sclr_clk,
TestSignal => sclr_ipd,
TestSignalName => "SCLR",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sclr_clk_noedge_posedge,
SetupLow => tsetup_sclr_clk_noedge_posedge,
HoldHigh => thold_sclr_clk_noedge_posedge,
HoldLow => thold_sclr_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT clrn_ipd) OR
(NOT prn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/stratixiii_ddr_io_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sload_clk,
TimingData => TimingData_sload_clk,
TestSignal => sload_ipd,
TestSignalName => "SLOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sload_clk_noedge_posedge,
SetupLow => tsetup_sload_clk_noedge_posedge,
HoldHigh => thold_sload_clk_noedge_posedge,
HoldLow => thold_sload_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT clrn_ipd) OR
(NOT prn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/stratixiii_ddr_io_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT clrn_ipd) OR
(NOT prn_ipd) OR
(NOT devpor) OR
(NOT devclrn) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/stratixiii_ddr_io_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
violation := Tviol_d_clk or Tviol_asdata_clk or
Tviol_sclr_clk or Tviol_sload_clk or Tviol_ena_clk;
if ((devpor = '0') or (devclrn = '0') or (clrn_ipd = '0')) then
iq := '0';
elsif (prn_ipd = '0') then
iq := '1';
elsif (aload_ipd = '1') then
iq := asdata_dly1;
elsif (violation = 'X' and x_on_violation = "on") then
iq := 'X';
elsif clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' then
if (ena_ipd = '1') then
if (sclr_ipd = '1') then
iq := '0';
elsif (sload_ipd = '1') then
iq := asdata_dly1;
else
iq := d_dly;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => iq,
Paths => (0 => (clrn_ipd'last_event, tpd_clrn_q_negedge, TRUE),
1 => (prn_ipd'last_event, tpd_prn_q_negedge, TRUE),
2 => (aload_ipd'last_event, tpd_aload_q_posedge, TRUE),
3 => (asdata_ipd'last_event, tpd_asdata_q, TRUE),
4 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_titan_ddr_io_reg;
-------------------------------------------------------------------------------
--
-- Entity Name : Stratix III_dll
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
use work.stratixiii_pllpack.all;
use work.stratixiii_atom_ddr_pack.all;
use work.stratixiii_dll_gray_encoder;
ENTITY stratixiii_dll is
GENERIC (
input_frequency : string := "0 ps";
delay_buffer_mode : string := "low";
delay_chain_length : integer := 12;
delayctrlout_mode : string := "normal";
jitter_reduction : string := "false";
use_upndnin : string := "false";
use_upndninclkena : string := "false";
dual_phase_comparators : string := "true";
sim_valid_lock : integer := 16;
sim_valid_lockcount : integer := 0; -- 10000 = 1000 + 100*dllcounter
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
static_delay_ctrl : integer := 0;
lpm_type : string := "stratixiii_dll";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_aload : VitalDelayType01 := DefpropDelay01;
tipd_upndnin : VitalDelayType01 := DefpropDelay01;
tipd_upndninclkena : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tsetup_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_upndnout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_delayctrlout_posedge : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01)
);
PORT ( clk : IN std_logic := '0';
aload : IN std_logic := '0';
upndnin : IN std_logic := '1';
upndninclkena : IN std_logic := '1';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '0';
delayctrlout : OUT std_logic_vector(5 DOWNTO 0);
dqsupdate : OUT std_logic;
offsetdelayctrlout : OUT std_logic_vector(5 DOWNTO 0);
offsetdelayctrlclkout : OUT std_logic;
upndnout : OUT std_logic
);
END stratixiii_dll;
ARCHITECTURE vital_titandll of stratixiii_dll is
COMPONENT stratixiii_dll_gray_encoder
GENERIC ( width : integer := 6 );
PORT ( mbin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
gout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END COMPONENT;
signal clk_in : std_logic := '0';
signal aload_in_buf : std_logic := '0';
signal upndn_in : std_logic := '0';
signal upndninclkena_in : std_logic := '1';
signal delayctrl_out : std_logic_vector(5 DOWNTO 0) := "000000";
signal offsetdelayctrl_out : std_logic_vector(5 DOWNTO 0) := "000000";
signal upndn_out : std_logic := '0';
signal dqsupdate_out : std_logic := '0';
signal para_delay_buffer_mode : std_logic_vector (1 DOWNTO 0) := "01";
signal para_delayctrlout_mode : std_logic_vector (1 DOWNTO 0) := "00";
signal para_static_delay_ctrl : integer := 0;
signal para_jitter_reduction : std_logic := '0';
signal para_use_upndnin : std_logic := '0';
signal para_use_upndninclkena : std_logic := '1';
-- INTERNAL NETS AND VARIABLES
-- for functionality - by modules
signal sim_buffer_intrinsic_delay : INTEGER := 0;
-- two reg on the de-assertion of dll
SIGNAL aload_in : std_logic := '0';
SIGNAL aload_reg1 : std_logic := '1';
SIGNAL aload_reg2 : std_logic := '1';
-- delay and offset control out resolver
signal dr_delayctrl_out : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_delayctrl_int : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_offsetctrl_out : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_dllcount_in : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_clk8_in : std_logic := '0';
signal dr_aload_in : std_logic := '0';
signal dr_reg_dllcount : std_logic_vector (5 DOWNTO 0) := "000000";
signal para_static_delay_ctrl_gray : std_logic_vector (5 DOWNTO 0) := "000000";
-- delay chain setting counter
signal dc_dllcount_out_gray : std_logic_vector (5 DOWNTO 0) := "000000";
signal dc_dllcount_out_vec : std_logic_vector (5 DOWNTO 0) := "000000";
signal dc_dllcount_out : integer := 0;
signal dc_dqsupdate_out : std_logic := '0';
signal dc_upndn_in : std_logic := '1';
signal dc_aload_in : std_logic := '0';
signal dc_upndnclkena_in : std_logic := '1';
signal dc_clk8_in : std_logic := '0';
signal dc_clk1_in : std_logic := '0';
signal dc_dlltolock_in : std_logic := '0';
signal dc_reg_dllcount : integer := 0;
signal dc_reg_dlltolock_pulse : std_logic := '0';
-- jitter reduction counter
signal jc_upndn_out : std_logic := '0';
signal jc_upndnclkena_out : std_logic := '1';
signal jc_clk8_in : std_logic := '0';
signal jc_upndn_in : std_logic := '1';
signal jc_aload_in : std_logic := '0';
signal jc_clkena_in : std_logic := '1'; -- new in stratixiii
signal jc_count : integer := 8;
signal jc_reg_upndn : std_logic := '0';
signal jc_reg_upndnclkena : std_logic := '0';
-- phase comparator
signal pc_lock : std_logic := '0'; -- new in stratixiii
signal pc_upndn_out : std_logic := '1';
signal pc_dllcount_in : integer := 0;
signal pc_clk1_in : std_logic := '0';
signal pc_clk8_in : std_logic := '0';
signal pc_aload_in : std_logic := '0';
signal pc_reg_upndn : std_logic := '1';
signal pc_delay : integer := 0;
signal pc_lock_reg : std_logic := '0'; -- new in stratixiii
signal pc_comp_range : integer := 0; -- new in stratixiii
-- clock generator
signal cg_clk_in : std_logic := '0';
signal cg_aload_in : std_logic := '0';
signal cg_clk1_out : std_logic := '0';
signal cg_clk8a_out : std_logic := '0';
signal cg_clk8b_out : std_logic := '0';
-- por: 000
signal cg_reg_1 : std_logic := '0';
signal cg_rega_2 : std_logic := '0';
signal cg_rega_3 : std_logic := '0';
-- por: 010
signal cg_regb_2 : std_logic := '1';
signal cg_regb_3 : std_logic := '0';
-- for violation checks
signal dll_to_lock : std_logic := '0';
signal input_period : integer := 10000;
signal clk_in_last_value : std_logic := 'X';
begin
-- paramters
input_period <= dqs_str2int(input_frequency);
para_static_delay_ctrl <= static_delay_ctrl;
para_use_upndnin <= '1' WHEN use_upndnin = "true" ELSE '0';
para_jitter_reduction <= '1' WHEN jitter_reduction = "true" ELSE '0';
para_use_upndninclkena <= '1' WHEN use_upndninclkena = "true" ELSE '0';
para_delay_buffer_mode <= "00" WHEN delay_buffer_mode = "auto" ELSE "01" WHEN delay_buffer_mode = "low" ELSE "10";
para_delayctrlout_mode <= "01" WHEN delayctrlout_mode = "test" ELSE "10" WHEN delayctrlout_mode="normal" ELSE "11" WHEN delayctrlout_mode="static" ELSE "00";
sim_buffer_intrinsic_delay <= sim_low_buffer_intrinsic_delay WHEN (delay_buffer_mode = "low") ELSE
sim_high_buffer_intrinsic_delay;
-- violation check block
process (clk_in)
variable got_first_rising_edge : std_logic := '0';
variable got_first_falling_edge : std_logic := '0';
variable per_violation : std_logic := '0';
variable duty_violation : std_logic := '0';
variable sent_per_violation : std_logic := '0';
variable sent_duty_violation : std_logic := '0';
variable clk_in_last_rising_edge : time := 0 ps;
variable clk_in_last_falling_edge : time := 0 ps;
variable input_period_ps : time := 10000 ps;
variable duty_cycle : time := 5000 ps;
variable clk_in_period : time := 10000 ps;
variable clk_in_duty_cycle : time := 5000 ps;
variable clk_per_tolerance : time := 2 ps;
variable half_cycles_to_lock : integer := 1;
variable init : boolean := true;
begin
if (init) then
input_period_ps := dqs_str2int(input_frequency) * 1 ps;
if (input_period_ps = 0 ps) then
assert false report "Need to specify ps scale in simulation command" severity error;
end if;
duty_cycle := input_period_ps/2;
clk_per_tolerance := 2 ps;
half_cycles_to_lock := 0;
init := false;
end if;
if (clk_in'event and clk_in = '1') then -- rising edge
if (got_first_rising_edge = '0') then
got_first_rising_edge := '1';
else -- subsequent rising
-- check for clock period and duty cycle violation
clk_in_period := now - clk_in_last_rising_edge;
clk_in_duty_cycle := now - clk_in_last_falling_edge;
if ((clk_in_period < (input_period_ps - clk_per_tolerance)) or (clk_in_period > (input_period_ps + clk_per_tolerance))) then
per_violation := '1';
if (sent_per_violation /= '1') then
sent_per_violation := '1';
assert false report "Input clock frequency violation." severity warning;
end if;
elsif ((clk_in_duty_cycle < (duty_cycle - clk_per_tolerance/2 - 1 ps)) or (clk_in_duty_cycle > (duty_cycle + clk_per_tolerance/2 + 1 ps))) then
duty_violation := '1';
if (sent_duty_violation /= '1') then
sent_duty_violation := '1';
assert false report "Input clock duty cycle violation." severity warning;
end if;
else
if (per_violation = '1') then
sent_per_violation := '0';
assert false report "Input clock frequency now matches specified clock frequency." severity warning;
end if;
per_violation := '0';
duty_violation := '0';
end if;
end if;
if (per_violation = '0' and duty_violation = '0' and dll_to_lock = '0') then
half_cycles_to_lock := half_cycles_to_lock + 1;
if (half_cycles_to_lock >= sim_valid_lock) then
dll_to_lock <= '1';
assert false report "DLL to lock to incoming clock" severity note;
end if;
end if;
clk_in_last_rising_edge := now;
elsif (clk_in'event and clk_in = '0') then -- falling edge
got_first_falling_edge := '1';
if (got_first_rising_edge = '1') then
-- duty cycle check
clk_in_duty_cycle := now - clk_in_last_rising_edge;
if ((clk_in_duty_cycle < (duty_cycle - clk_per_tolerance/2 - 1 ps)) or (clk_in_duty_cycle > (duty_cycle + clk_per_tolerance/2 + 1 ps))) then
duty_violation := '1';
if (sent_duty_violation /= '1') then
sent_duty_violation := '1';
assert false report "Input clock duty cycle violation." severity warning;
end if;
else
duty_violation := '0';
end if;
if (dll_to_lock = '0' and duty_violation = '0') then
half_cycles_to_lock := half_cycles_to_lock + 1;
end if;
end if;
clk_in_last_falling_edge := now;
elsif (got_first_falling_edge = '1' or got_first_rising_edge = '1') then
-- switches from 1, 0 to X
half_cycles_to_lock := 0;
got_first_rising_edge := '0';
got_first_falling_edge := '0';
if (dll_to_lock = '1') then
dll_to_lock <= '0';
assert false report "Illegal value detected on input clock. DLL will lose lock." severity warning;
else
assert false report "Illegal value detected on input clock." severity warning;
end if;
end if;
clk_in_last_value <= clk_in;
end process ; -- violation check
-- outputs
delayctrl_out <= dr_delayctrl_out;
offsetdelayctrl_out <= dr_offsetctrl_out;
offsetdelayctrlclkout <= dr_clk8_in;
dqsupdate_out <= cg_clk8a_out;
upndn_out <= pc_upndn_out;
-- two registers on aload path --------------------------------------------
aload_in <= (aload_in_buf OR aload_reg2);
process(clk_in)
begin
if (clk_in = '0' and clk_in'event) then
aload_reg2 <= aload_reg1;
aload_reg1 <= aload_in_buf;
end if;
end process;
-- Delay and offset ctrl out resolver -------------------------------------
-------- convert calculations into integer
-- inputs
dr_clk8_in <= not cg_clk8b_out;
dr_dllcount_in <= dc_dllcount_out_gray;
dr_aload_in <= aload_in;
mdll_count_enc : stratixiii_dll_gray_encoder
GENERIC MAP (width => 6)
PORT MAP (mbin => dc_dllcount_out_vec, gout => dc_dllcount_out_gray);
dc_dllcount_out_vec <= dll_unsigned2bin(dc_dllcount_out);
-- outputs
dr_delayctrl_out <= dr_reg_dllcount;
dr_offsetctrl_out <= dr_delayctrl_int;
-- assumed para_static_delay_ctrl is gray-coded
para_static_delay_ctrl_gray <= dll_unsigned2bin(para_static_delay_ctrl);
dr_delayctrl_int <= para_static_delay_ctrl_gray WHEN (delayctrlout_mode = "static") ELSE
dr_dllcount_in;
-- model
process(dr_clk8_in, dr_aload_in)
begin
if (dr_aload_in = '1' and dr_aload_in'event) then
dr_reg_dllcount <= "000000";
elsif (dr_clk8_in = '1' and dr_clk8_in'event and dr_aload_in /= '1') then
dr_reg_dllcount <= dr_delayctrl_int;
end if;
end process;
-- Delay Setting Control Counter ------------------------------------------
--inputs
dc_dlltolock_in <= dll_to_lock;
dc_aload_in <= aload_in;
dc_clk1_in <= cg_clk1_out;
dc_clk8_in <= not cg_clk8b_out;
dc_upndnclkena_in <= upndninclkena WHEN (para_use_upndninclkena = '1') ELSE
jc_upndnclkena_out WHEN (para_jitter_reduction = '1') ELSE
(not pc_lock) WHEN (dual_phase_comparators = "true") ELSE
'1';
dc_upndn_in <= upndnin WHEN (para_use_upndnin = '1') ELSE
jc_upndn_out WHEN (para_jitter_reduction = '1') ELSE
pc_upndn_out;
-- outputs
dc_dllcount_out <= dc_reg_dllcount; -- needs to turn into gray counter
-- dll counter logic
process(dc_clk8_in, dc_aload_in, dc_dlltolock_in)
variable dc_var_dllcount : integer := 64;
variable init : boolean := true;
begin
if (init) then
if (delay_buffer_mode = "low") then
dc_var_dllcount := 32;
else
dc_var_dllcount := 16;
end if;
init := false;
end if;
if (dc_aload_in = '1' and dc_aload_in'event) then
if (delay_buffer_mode = "low") then
dc_var_dllcount := 32;
else
dc_var_dllcount := 16;
end if;
elsif (dc_aload_in /= '1' and dc_dlltolock_in = '1' and dc_reg_dlltolock_pulse /= '1' and
dc_upndnclkena_in = '1' and para_use_upndnin = '0') then
dc_var_dllcount := sim_valid_lockcount;
dc_reg_dlltolock_pulse <= '1';
elsif (dc_aload_in /= '1' and
dc_upndnclkena_in = '1' and dc_clk8_in'event and dc_clk8_in = '1') then -- posedge clk
if (dc_upndn_in = '1') then
if ((para_delay_buffer_mode = "01" and dc_var_dllcount < 63) or
(para_delay_buffer_mode /= "01" and dc_var_dllcount < 31)) then
dc_var_dllcount := dc_var_dllcount + 1;
end if;
elsif (dc_upndn_in = '0') then
if (dc_var_dllcount > 0) then
dc_var_dllcount := dc_var_dllcount - 1;
end if;
end if;
end if; -- rising clock
-- schedule signal dc_reg_dllcount
dc_reg_dllcount <= dc_var_dllcount;
end process;
-- Jitter reduction counter -----------------------------------------------
-- inputs
jc_clk8_in <= not cg_clk8b_out;
jc_upndn_in <= pc_upndn_out;
jc_aload_in <= aload_in;
-- new in stratixiii
jc_clkena_in <= '1' WHEN (dual_phase_comparators = "false") ELSE (not pc_lock);
-- outputs
jc_upndn_out <= jc_reg_upndn;
jc_upndnclkena_out <= jc_reg_upndnclkena;
-- Model
process (jc_clk8_in, jc_aload_in)
begin
if (jc_aload_in = '1' and jc_aload_in'event) then
jc_count <= 8;
elsif (jc_aload_in /= '1' and jc_clk8_in'event and jc_clk8_in = '1') then
if (jc_clkena_in = '1') then
if (jc_count = 12) then
jc_reg_upndn <= '1';
jc_reg_upndnclkena <= '1';
jc_count <= 8;
elsif (jc_count = 4) then
jc_reg_upndn <= '0';
jc_reg_upndnclkena <= '1';
jc_count <= 8;
else -- increment/decrement counter
jc_reg_upndnclkena <= '0';
if (jc_upndn_in = '1') then
jc_count <= jc_count + 1;
elsif (jc_upndn_in = '0') then
jc_count <= jc_count - 1;
end if;
end if;
else -- not clkena
jc_reg_upndnclkena <= '0';
end if;
end if;
end process;
-- Phase comparator -------------------------------------------------------
-- inputs
pc_clk1_in <= cg_clk1_out;
pc_clk8_in <= cg_clk8b_out; -- positive
pc_dllcount_in <= dc_dllcount_out; -- for phase loop calculation
pc_aload_in <= aload_in;
-- outputs
pc_upndn_out <= pc_reg_upndn;
pc_lock <= pc_lock_reg;
-- parameter used
-- sim_loop_intrinsic_delay, sim_loop_delay_increment
pc_comp_range <= (3*delay_chain_length*sim_buffer_delay_increment)/2;
-- Model
process (pc_clk8_in, pc_aload_in)
variable pc_var_delay : integer := 0;
begin
if (pc_aload_in = '1' and pc_aload_in'event) then
pc_var_delay := 0;
elsif (pc_aload_in /= '1' and pc_clk8_in'event and pc_clk8_in = '1' ) then
pc_var_delay := delay_chain_length * (sim_buffer_intrinsic_delay + sim_buffer_delay_increment * pc_dllcount_in);
pc_delay <= pc_var_delay;
if (dual_phase_comparators = "false") then
if (pc_var_delay > input_period) then
pc_reg_upndn <= '0';
else
pc_reg_upndn <= '1';
end if;
else -- use dual phase
if (pc_var_delay < (input_period - pc_comp_range/2)) then
pc_reg_upndn <= '1';
pc_lock_reg <= '0';
elsif (pc_var_delay <= (input_period + pc_comp_range/2)) then
pc_reg_upndn <= '0';
pc_lock_reg <= '1';
else
pc_reg_upndn <= '0';
pc_lock_reg <= '0';
end if;
end if;
end if;
end process;
-- Clock Generator -------------------------------------------------------
-- inputs
cg_clk_in <= clk_in;
cg_aload_in <= aload_in;
-- outputs
cg_clk8a_out <= cg_rega_3;
cg_clk8b_out <= cg_regb_3;
cg_clk1_out <= '0' WHEN cg_aload_in = '1' ELSE cg_clk_in;
-- Model
process(cg_clk1_out, cg_aload_in)
begin
if (cg_aload_in = '1' and cg_aload_in'event) then
cg_reg_1 <= '0';
elsif (cg_aload_in /= '1' and cg_clk1_out = '1' and cg_clk1_out'event) then
cg_reg_1 <= not cg_reg_1;
end if;
end process;
process(cg_reg_1, cg_aload_in)
begin
if (cg_aload_in = '1' and cg_aload_in'event) then
cg_rega_2 <= '0';
cg_regb_2 <= '1';
elsif (cg_aload_in /= '1' and cg_reg_1 = '1' and cg_reg_1'event) then
cg_rega_2 <= not cg_rega_2;
cg_regb_2 <= not cg_regb_2;
end if;
end process;
process (cg_rega_2, cg_aload_in)
begin
if (cg_aload_in = '1' and cg_aload_in'event) then
cg_rega_3 <= '0';
elsif (cg_aload_in /= '1' and cg_rega_2 = '1' and cg_rega_2'event) then
cg_rega_3 <= not cg_rega_3;
end if;
end process;
process (cg_regb_2, cg_aload_in)
begin
if (cg_aload_in = '1' and cg_aload_in'event) then
cg_regb_3 <= '0';
elsif (cg_aload_in /= '1' and cg_regb_2 = '1' and cg_regb_2'event) then
cg_regb_3 <= not cg_regb_3;
end if;
end process;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (clk_in, clk, tipd_clk);
VitalWireDelay (aload_in_buf, aload, tipd_aload);
VitalWireDelay (upndn_in, upndnin, tipd_upndnin);
VitalWireDelay (upndninclkena_in, upndninclkena, tipd_upndninclkena);
end block;
------------------------
-- Timing Check Section
------------------------
VITALtiming : process (clk_in, upndn_in, upndninclkena_in,
delayctrl_out, offsetdelayctrl_out, dqsupdate_out, upndn_out)
variable Tviol_upndnin_clk : std_ulogic := '0';
variable Tviol_upndninclkena_clk : std_ulogic := '0';
variable TimingData_upndnin_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_upndninclkena_clk : VitalTimingDataType := VitalTimingDataInit;
variable delayctrlout_VitalGlitchDataArray : VitalGlitchDataArrayType(5 downto 0);
variable upndnout_VitalGlitchData : VitalGlitchDataType;
begin
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_upndnin_clk,
TimingData => TimingData_upndnin_clk,
TestSignal => upndn_in,
TestSignalName => "UPNDNIN",
RefSignal => clk_in,
RefSignalName => "CLK",
SetupHigh => tsetup_upndnin_clk_noedge_posedge,
SetupLow => tsetup_upndnin_clk_noedge_posedge,
HoldHigh => thold_upndnin_clk_noedge_posedge,
HoldLow => thold_upndnin_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXIII_DLL",
XOn => XOn,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_upndninclkena_clk,
TimingData => TimingData_upndninclkena_clk,
TestSignal => upndninclkena_in,
TestSignalName => "UPNDNINCLKENA",
RefSignal => clk_in,
RefSignalName => "CLK",
SetupHigh => tsetup_upndninclkena_clk_noedge_posedge,
SetupLow => tsetup_upndninclkena_clk_noedge_posedge,
HoldHigh => thold_upndninclkena_clk_noedge_posedge,
HoldLow => thold_upndninclkena_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXIII_DLL",
XOn => XOn,
MsgOn => MsgOnChecks );
end if;
----------------------
-- Path Delay Section
----------------------
offsetdelayctrlout <= offsetdelayctrl_out;
dqsupdate <= dqsupdate_out;
VitalPathDelay01 (
OutSignal => upndnout,
OutSignalName => "UPNDNOUT",
OutTemp => upndn_out,
Paths => (0 => (clk_in'last_event, tpd_clk_upndnout_posedge, TRUE)),
GlitchData => upndnout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(0),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(0),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(0), TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(0),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(1),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(1),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(1), TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(1),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(2),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(2),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(2), TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(2),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(3),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(3),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(3), TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(3),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(4),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(4),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(4), TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(4),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(5),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(5),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(5), TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(5),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process; -- vital timing
end vital_titandll;
-------------------------------------------------------------------------------
--
-- Entity Name : Stratix III_dll_offset_ctrl
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
USE work.stratixiii_pllpack.all;
use work.stratixiii_atom_ddr_pack.all;
use work.stratixiii_dll_gray_encoder;
use work.stratixiii_dll_gray_decoder;
ENTITY stratixiii_dll_offset_ctrl is
GENERIC (
use_offset : string := "false";
static_offset : string := "0";
delay_buffer_mode : string := "low";
lpm_type : string := "stratixiii_dll_offset_ctrl";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_aload : VitalDelayType01 := DefpropDelay01;
tipd_offset : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_offsetdelayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_addnsub : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tsetup_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_offsetctrlout_posedge : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01)
);
PORT ( clk : IN std_logic := '0';
aload : IN std_logic := '0';
offsetdelayctrlin : IN std_logic_vector(5 DOWNTO 0) := "000000";
offset : IN std_logic_vector(5 DOWNTO 0) := "000000";
addnsub : IN std_logic := '1';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '0';
offsettestout : OUT std_logic_vector(5 DOWNTO 0);
offsetctrlout : OUT std_logic_vector(5 DOWNTO 0)
);
END stratixiii_dll_offset_ctrl;
ARCHITECTURE vital_titanoffset of stratixiii_dll_offset_ctrl is
COMPONENT stratixiii_dll_gray_encoder
GENERIC ( width : integer := 6 );
PORT ( mbin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
gout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT stratixiii_dll_gray_decoder
GENERIC ( width : integer := 6 );
PORT ( gin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
bout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END COMPONENT;
signal clk_in : std_logic := '0';
signal aload_in : std_logic := '0';
signal offset_in : std_logic_vector(5 DOWNTO 0) := "000000";
signal offsetdelayctrlin_in : std_logic_vector(5 DOWNTO 0) := "000000";
signal addnsub_in : std_logic := '0';
signal offsetctrl_out : std_logic_vector(5 DOWNTO 0) := "000000";
signal para_delay_buffer_mode : std_logic_vector (1 DOWNTO 0) := "01";
signal para_use_offset : std_logic := '0';
signal para_static_offset : integer := 0;
signal para_static_offset_pos : integer := 0;
-- INTERNAL NETS AND VARIABLES
-- for functionality - by modules
-- two reg on the de-assertion of aload
SIGNAL aload_reg1 : std_logic := '1';
SIGNAL aload_reg2 : std_logic := '1';
-- delay and offset control out resolver
signal dr_offsetctrl_out : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_offsettest_out : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_offsetctrl_out_gray : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_addnsub_in : std_logic := '1';
signal dr_clk8_in : std_logic := '0';
signal dr_aload_in : std_logic := '0';
signal dr_offset_in_gray : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_delayctrl_in_gray : std_logic_vector (5 DOWNTO 0) := "000000";
signal para_static_offset_vec_pos : std_logic_vector (5 DOWNTO 0) := "000000";
signal para_static_offset_gray : std_logic_vector (5 DOWNTO 0) := "000000"; -- signed in 2's complement
-- docoder
signal dr_delayctrl_in_bin : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_offset_in_bin : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_offset_in_bin_pos : std_logic_vector (5 DOWNTO 0) := "000000"; -- for over/underflow check
signal para_static_offset_bin : std_logic_vector (5 DOWNTO 0) := "000000";
signal para_static_offset_bin_pos : std_logic_vector (5 DOWNTO 0) := "000000"; -- for over/underflow check
signal dr_reg_offset : std_logic_vector (5 DOWNTO 0) := "000000";
begin
-- paramters
para_delay_buffer_mode <= "01" WHEN delay_buffer_mode = "low" ELSE "00";
para_use_offset <= '1' WHEN use_offset = "true" ELSE '0';
para_static_offset <= dqs_str2int(static_offset); -- signed int
para_static_offset_pos <= para_static_offset WHEN (para_static_offset > 0) ELSE (-1)*para_static_offset;
-- outputs
offsetctrl_out <= dr_offsetctrl_out_gray;
offsettestout <= dr_offsettest_out;
-- two registers on aload path --------------------------------------------
-- it should be user clock to DLL, not the /8 clock of offsetctrl
process(clk_in)
begin
if (clk_in = '0' and clk_in'event) then
aload_reg2 <= aload_reg1;
aload_reg1 <= aload_in;
end if;
end process;
-- Delay and offset ctrl out resolver -------------------------------------
-- inputs
dr_clk8_in <= clk_in;
dr_addnsub_in <= addnsub_in;
dr_aload_in <= aload_in; -- aload_in | aload_reg2;
dr_delayctrl_in_gray <= offsetdelayctrlin_in;
dr_offset_in_gray <= offset_in;
para_static_offset_vec_pos <= dll_unsigned2bin(para_static_offset_pos);
para_static_offset_gray <= ("111111" - para_static_offset_vec_pos + "000001") WHEN (para_static_offset < 0) ELSE para_static_offset_vec_pos;
-- outputs
dr_offsetctrl_out <= dr_reg_offset;
moffsetctrl_out_enc : stratixiii_dll_gray_encoder
GENERIC MAP (width => 6)
PORT MAP (mbin => dr_reg_offset, gout => dr_offsetctrl_out_gray);
dr_offsettest_out <= para_static_offset_gray WHEN (use_offset = "false") ELSE offset_in;
-- model
-- decoders
mdr_delayctrl_in_dec : stratixiii_dll_gray_decoder
GENERIC MAP (width => 6)
PORT MAP (gin => dr_delayctrl_in_gray, bout => dr_delayctrl_in_bin);
mdr_offset_in_dec : stratixiii_dll_gray_decoder
GENERIC MAP (width => 6)
PORT MAP (gin => dr_offset_in_gray, bout => dr_offset_in_bin);
mpara_static_offset_dec : stratixiii_dll_gray_decoder
GENERIC MAP (width => 6)
PORT MAP (gin => para_static_offset_gray, bout => para_static_offset_bin);
-- get postive value of decoded offset for over/underflow check
para_static_offset_bin_pos <= ("111111" - para_static_offset_bin + "000001") WHEN (para_static_offset < 0) ELSE para_static_offset_bin;
dr_offset_in_bin_pos <= ("111111" - dr_offset_in_bin + "000001") WHEN ((use_offset = "true") AND (addnsub_in = '0')) ELSE dr_offset_in_bin;
-- generating dr_reg_offset
process(dr_clk8_in, dr_aload_in)
begin
if (dr_aload_in = '1' and dr_aload_in'event) then
dr_reg_offset <= "000000";
elsif (dr_aload_in /= '1' and dr_clk8_in = '1' and dr_clk8_in'event) then
if (use_offset = "true") then
if (dr_addnsub_in = '1') then
if (dr_delayctrl_in_bin < "111111" - dr_offset_in_bin) then
dr_reg_offset <= dr_delayctrl_in_bin + dr_offset_in_bin;
else
dr_reg_offset <= "111111";
end if;
elsif (dr_addnsub_in = '0') then
if (dr_delayctrl_in_bin > dr_offset_in_bin_pos) then
dr_reg_offset <= dr_delayctrl_in_bin + dr_offset_in_bin; -- same as - *_pos
else
dr_reg_offset <= "000000";
end if;
end if;
else
if (para_static_offset >= 0) then -- do not use a + b < "11111" as it does not check overflow
if ((para_static_offset_bin < "111111") AND (dr_delayctrl_in_bin < "111111" - para_static_offset_bin )) then
dr_reg_offset <= dr_delayctrl_in_bin + para_static_offset_bin;
else
dr_reg_offset <= "111111";
end if;
else
if ((para_static_offset_bin_pos < "111111") AND (dr_delayctrl_in_bin > para_static_offset_bin_pos)) then
dr_reg_offset <= dr_delayctrl_in_bin + para_static_offset_bin; -- same as - *_pos
else
dr_reg_offset <= "000000";
end if;
end if;
end if;
end if; -- rising clock
end process ; -- generating dr_reg_offset
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (clk_in, clk, tipd_clk);
VitalWireDelay (aload_in, aload, tipd_aload);
VitalWireDelay (addnsub_in, addnsub, tipd_addnsub);
VitalWireDelay (offset_in(0), offset(0), tipd_offset(0));
VitalWireDelay (offset_in(1), offset(1), tipd_offset(1));
VitalWireDelay (offset_in(2), offset(2), tipd_offset(2));
VitalWireDelay (offset_in(3), offset(3), tipd_offset(3));
VitalWireDelay (offset_in(4), offset(4), tipd_offset(4));
VitalWireDelay (offset_in(5), offset(5), tipd_offset(5));
VitalWireDelay (offsetdelayctrlin_in(0), offsetdelayctrlin(0), tipd_offsetdelayctrlin(0));
VitalWireDelay (offsetdelayctrlin_in(1), offsetdelayctrlin(1), tipd_offsetdelayctrlin(1));
VitalWireDelay (offsetdelayctrlin_in(2), offsetdelayctrlin(2), tipd_offsetdelayctrlin(2));
VitalWireDelay (offsetdelayctrlin_in(3), offsetdelayctrlin(3), tipd_offsetdelayctrlin(3));
VitalWireDelay (offsetdelayctrlin_in(4), offsetdelayctrlin(4), tipd_offsetdelayctrlin(4));
VitalWireDelay (offsetdelayctrlin_in(5), offsetdelayctrlin(5), tipd_offsetdelayctrlin(5));
end block;
------------------------
-- Timing Check Section
------------------------
VITALtiming : process (clk_in, offset_in, addnsub_in,
offsetctrl_out)
variable Tviol_offset_clk : std_ulogic := '0';
variable Tviol_addnsub_clk : std_ulogic := '0';
variable TimingData_offset_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_addnsub_clk : VitalTimingDataType := VitalTimingDataInit;
variable offsetctrlout_VitalGlitchDataArray : VitalGlitchDataArrayType(5 downto 0);
begin
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_offset_clk,
TimingData => TimingData_offset_clk,
TestSignal => offset_in,
TestSignalName => "OFFSET",
RefSignal => clk_in,
RefSignalName => "CLK",
SetupHigh => tsetup_offset_clk_noedge_posedge(0),
SetupLow => tsetup_offset_clk_noedge_posedge(0),
HoldHigh => thold_offset_clk_noedge_posedge(0),
HoldLow => thold_offset_clk_noedge_posedge(0),
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXIII_OFFSETCTRL",
XOn => XOn,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_addnsub_clk,
TimingData => TimingData_addnsub_clk,
TestSignal => addnsub_in,
TestSignalName => "ADDNSUB",
RefSignal => clk_in,
RefSignalName => "CLK",
SetupHigh => tsetup_addnsub_clk_noedge_posedge,
SetupLow => tsetup_addnsub_clk_noedge_posedge,
HoldHigh => thold_addnsub_clk_noedge_posedge,
HoldLow => thold_addnsub_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXIII_OFFSETCTRL",
XOn => XOn,
MsgOn => MsgOnChecks );
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => offsetctrlout(0),
OutSignalName => "offsetctrlOUT",
OutTemp => offsetctrl_out(0),
Paths => (0 => (clk_in'last_event, tpd_clk_offsetctrlout_posedge(0), TRUE)),
GlitchData => offsetctrlout_VitalGlitchDataArray(0),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => offsetctrlout(1),
OutSignalName => "offsetctrlOUT",
OutTemp => offsetctrl_out(1),
Paths => (0 => (clk_in'last_event, tpd_clk_offsetctrlout_posedge(1), TRUE)),
GlitchData => offsetctrlout_VitalGlitchDataArray(1),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => offsetctrlout(2),
OutSignalName => "offsetctrlOUT",
OutTemp => offsetctrl_out(2),
Paths => (0 => (clk_in'last_event, tpd_clk_offsetctrlout_posedge(2), TRUE)),
GlitchData => offsetctrlout_VitalGlitchDataArray(2),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => offsetctrlout(3),
OutSignalName => "offsetctrlOUT",
OutTemp => offsetctrl_out(3),
Paths => (0 => (clk_in'last_event, tpd_clk_offsetctrlout_posedge(3), TRUE)),
GlitchData => offsetctrlout_VitalGlitchDataArray(3),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => offsetctrlout(4),
OutSignalName => "offsetctrlOUT",
OutTemp => offsetctrl_out(4),
Paths => (0 => (clk_in'last_event, tpd_clk_offsetctrlout_posedge(4), TRUE)),
GlitchData => offsetctrlout_VitalGlitchDataArray(4),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => offsetctrlout(5),
OutSignalName => "offsetctrlOUT",
OutTemp => offsetctrl_out(5),
Paths => (0 => (clk_in'last_event, tpd_clk_offsetctrlout_posedge(5), TRUE)),
GlitchData => offsetctrlout_VitalGlitchDataArray(5),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process; -- vital timing
end vital_titanoffset;
-------------------------------------------------------------------------------
--
-- Entity Name : stratixiii_dqs_delay_chain
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
use work.stratixiii_dll_gray_decoder;
ENTITY stratixiii_dqs_delay_chain IS
GENERIC (
dqs_input_frequency : string := "unused" ;
use_phasectrlin : string := "false";
phase_setting : integer := 0;
delay_buffer_mode : string := "low";
dqs_phase_shift : integer := 0;
dqs_offsetctrl_enable : string := "false";
dqs_ctrl_latches_enable : string := "false";
-- DFT added in WYS 1.33
test_enable : string := "false";
test_select : integer := 0;
-- SIM only
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
lpm_type : string := "stratixiii_dqs_delay_chain";
tipd_dqsin : VitalDelayType01 := DefpropDelay01;
tipd_aload : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_offsetctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_dqsupdateen : VitalDelayType01 := DefpropDelay01;
tipd_phasectrlin : VitalDelayArrayType01(2 downto 0) := (OTHERS => DefPropDelay01);
tpd_dqsin_dqsbusout : VitalDelayType01 := DefPropDelay01;
tsetup_delayctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_delayctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_offsetctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_offsetctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
dqsin : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
offsetctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
dqsupdateen : IN std_logic := '1';
phasectrlin : IN std_logic_vector(2 downto 0) := (OTHERS => '0');
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsbusout : OUT std_logic;
dffin : OUT std_logic
);
END;
ARCHITECTURE stratixiii_dqs_delay_chain_arch OF stratixiii_dqs_delay_chain IS
-- component section
COMPONENT stratixiii_dll_gray_decoder
GENERIC ( width : integer := 6 );
PORT ( gin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
bout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END COMPONENT;
-- signal section
SIGNAL delayctrl_bin : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL offsetctrl_bin : std_logic_vector(5 downto 0) := (OTHERS => '0');
-- offsetctrl after "dqs_offsetctrl_enable" mux
SIGNAL offsetctrl_mux : std_logic_vector(5 downto 0) := (OTHERS => '0');
-- reged outputs of delay count
SIGNAL delayctrl_reg : std_logic_vector(5 downto 0) := (OTHERS => '1');
SIGNAL offsetctrl_reg : std_logic_vector(5 downto 0) := (OTHERS => '1');
-- delay count after latch enable mux
SIGNAL delayctrl_reg_mux : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL offsetctrl_reg_mux : std_logic_vector(5 downto 0) := (OTHERS => '0');
-- timing outputs
SIGNAL tmp_dqsbusout : STD_LOGIC := '0';
SIGNAL dqs_delay : INTEGER := 0;
-- timing inputs
SIGNAL dqsin_in : std_logic := '0';
SIGNAL delayctrlin_in : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL offsetctrlin_in : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL dqsupdateen_in : std_logic := '1';
SIGNAL phasectrlin_in : std_logic_vector(2 downto 0) := (OTHERS => '0');
SIGNAL test_bus : std_logic_vector(12 downto 0);
SIGNAL test_lpbk : std_logic;
SIGNAL tmp_dqsin : std_logic;
BEGIN
PROCESS(dqsupdateen_in)
BEGIN
IF (dqsupdateen_in = '1') THEN
delayctrl_reg <= delayctrlin_in;
offsetctrl_reg <= offsetctrl_mux;
END IF;
END PROCESS;
offsetctrl_mux <= offsetctrlin_in WHEN (dqs_offsetctrl_enable = "true") ELSE delayctrlin_in;
-- mux after reg
delayctrl_reg_mux <= delayctrl_reg WHEN (dqs_ctrl_latches_enable = "true") ELSE delayctrlin_in;
offsetctrl_reg_mux <= offsetctrl_reg WHEN (dqs_ctrl_latches_enable = "true") ELSE offsetctrl_mux;
mdelayctrlin_dec : stratixiii_dll_gray_decoder
GENERIC MAP (width => 6)
PORT MAP (gin => delayctrl_reg_mux, bout => delayctrl_bin);
moffsetctrlin_dec : stratixiii_dll_gray_decoder
GENERIC MAP (width => 6)
PORT MAP (gin => offsetctrl_reg_mux, bout => offsetctrl_bin);
PROCESS (delayctrl_bin, offsetctrl_bin, phasectrlin_in)
variable sim_intrinsic_delay : INTEGER := 0;
variable tmp_delayctrl : std_logic_vector(5 downto 0) := (OTHERS => '0');
variable tmp_offsetctrl : std_logic_vector(5 downto 0) := (OTHERS => '0');
variable acell_delay : INTEGER := 0;
variable aoffsetcell_delay : INTEGER := 0;
variable delay_chain_len : INTEGER := 0;
BEGIN
IF (delay_buffer_mode = "low") THEN
sim_intrinsic_delay := sim_low_buffer_intrinsic_delay;
ELSE
sim_intrinsic_delay := sim_high_buffer_intrinsic_delay;
END IF;
IF (delay_buffer_mode = "high" AND delayctrl_bin(5) = '1') THEN
tmp_delayctrl := "011111";
ELSE
tmp_delayctrl := delayctrl_bin;
END IF;
IF (delay_buffer_mode = "high" AND offsetctrl_bin(5) = '1') THEN
tmp_offsetctrl := "011111";
ELSE
tmp_offsetctrl := offsetctrl_bin;
END IF;
-- cell
acell_delay := sim_intrinsic_delay + alt_conv_integer(tmp_delayctrl) * sim_buffer_delay_increment;
IF (dqs_offsetctrl_enable = "true") THEN
aoffsetcell_delay := sim_intrinsic_delay + alt_conv_integer(tmp_offsetctrl)*sim_buffer_delay_increment;
ELSE
aoffsetcell_delay := acell_delay;
END IF;
-- no of cells
IF (use_phasectrlin = "false") THEN
delay_chain_len := phase_setting;
ELSIF (phasectrlin_in(2) = '1') THEN
delay_chain_len := 0;
ELSE
delay_chain_len := alt_conv_integer(phasectrlin_in) + 1;
END IF;
-- total delay
IF (delay_chain_len = 0) THEN
dqs_delay <= 0;
ELSE
dqs_delay <= (delay_chain_len - 1)*acell_delay + aoffsetcell_delay;
END IF;
END PROCESS; -- generating delays
-- test bus loopback
test_bus <= (not dqsupdateen_in) & offsetctrl_reg_mux & delayctrl_reg_mux;
test_lpbk <= test_bus(test_select) WHEN ((0 <= test_select) AND (test_select <= 12)) ELSE 'Z';
tmp_dqsin <= (test_lpbk AND dqsin) WHEN (test_enable = "true") ELSE dqsin_in;
tmp_dqsbusout <= transport tmp_dqsin after (dqs_delay * 1 ps);
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (dqsin_in, dqsin, tipd_dqsin);
loopbits_delayctrlin : FOR i in delayctrlin'RANGE GENERATE
VitalWireDelay (delayctrlin_in(i), delayctrlin(i), tipd_delayctrlin(i));
END GENERATE;
loopbits_offsetctrlin : FOR i in offsetctrlin'RANGE GENERATE
VitalWireDelay (offsetctrlin_in(i), offsetctrlin(i), tipd_offsetctrlin(i));
END GENERATE;
VitalWireDelay (dqsupdateen_in, dqsupdateen, tipd_dqsupdateen);
loopbits_phasectrlin : FOR i in phasectrlin'RANGE GENERATE
VitalWireDelay (phasectrlin_in(i), phasectrlin(i), tipd_phasectrlin(i));
END GENERATE;
end block;
-----------------------------------
-- Timing Check Section
-----------------------------------
VITAL_timing_check: PROCESS (dqsupdateen_in,offsetctrlin_in,delayctrlin_in)
variable Tviol_dqsupdateen_offsetctrlin : std_ulogic := '0';
variable TimingData_dqsupdateen_offsetctrlin : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_dqsupdateen_delayctrlin : std_ulogic := '0';
variable TimingData_dqsupdateen_delayctrlin : VitalTimingDataType := VitalTimingDataInit;
BEGIN
IF (TimingChecksOn) THEN
VitalSetupHoldCheck (
Violation => Tviol_dqsupdateen_offsetctrlin,
TimingData => TimingData_dqsupdateen_offsetctrlin,
TestSignal => offsetctrlin_in,
TestSignalName => "offsetctrlin",
RefSignal => dqsupdateen_in,
RefSignalName => "dqsupdateen",
SetupHigh => tsetup_offsetctrlin_dqsupdateen_noedge_posedge(0),
SetupLow => tsetup_offsetctrlin_dqsupdateen_noedge_posedge(0),
HoldHigh => thold_offsetctrlin_dqsupdateen_noedge_posedge(0),
HoldLow => thold_offsetctrlin_dqsupdateen_noedge_posedge(0),
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXIII_DQS_DELAY_CHAIN",
XOn => XOnChecks,
MsgOn => MsgOnChecks
);
VitalSetupHoldCheck (
Violation => Tviol_dqsupdateen_delayctrlin,
TimingData => TimingData_dqsupdateen_delayctrlin,
TestSignal => delayctrlin_in,
TestSignalName => "delayctrlin",
RefSignal => dqsupdateen_in,
RefSignalName => "dqsupdateen",
SetupHigh => tsetup_delayctrlin_dqsupdateen_noedge_posedge(0),
SetupLow => tsetup_delayctrlin_dqsupdateen_noedge_posedge(0),
HoldHigh => thold_delayctrlin_dqsupdateen_noedge_posedge(0),
HoldLow => thold_delayctrlin_dqsupdateen_noedge_posedge(0),
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXIII_DQS_DELAY_CHAIN",
XOn => XOnChecks,
MsgOn => MsgOnChecks
);
END IF;
END PROCESS; -- timing check
--------------------------------------
-- Path Delay Section
--------------------------------------
VITAL_path_delays: PROCESS (tmp_dqsbusout)
variable dqsbusout_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => dqsbusout,
OutSignalName => "dqsbusout",
OutTemp => tmp_dqsbusout,
Paths => (0 => (dqsin_in'last_event, tpd_dqsin_dqsbusout, TRUE)),
GlitchData => dqsbusout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
END PROCESS; -- Path Delays
END stratixiii_dqs_delay_chain_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : stratixiii_dqs_enable
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_dqs_enable IS
GENERIC (
lpm_type : string := "stratixiii_dqs_enable";
tipd_dqsin : VitalDelayType01 := DefpropDelay01;
tipd_dqsenable : VitalDelayType01 := DefpropDelay01;
tpd_dqsin_dqsbusout : VitalDelayType01 := DefPropDelay01;
tpd_dqsenable_dqsbusout : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
dqsin : IN std_logic := '0';
dqsenable : IN std_logic := '1';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsbusout : OUT std_logic
);
END;
ARCHITECTURE stratixiii_dqs_enable_arch OF stratixiii_dqs_enable IS
-- component section
-- signal section
SIGNAL ena_reg : STD_LOGIC := '1';
-- timing output
SIGNAL tmp_dqsbusout : std_logic := '0';
-- timing input
SIGNAL dqsin_in : std_logic := '0';
SIGNAL dqsenable_in : std_logic := '1';
BEGIN
tmp_dqsbusout <= ena_reg AND dqsin_in;
PROCESS(tmp_dqsbusout, dqsenable_in)
BEGIN
IF (dqsenable_in = '1') THEN
ena_reg <= '1';
ELSIF (tmp_dqsbusout'event AND tmp_dqsbusout = '0') THEN
ena_reg <= '0';
END IF;
END PROCESS;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (dqsin_in, dqsin, tipd_dqsin);
VitalWireDelay (dqsenable_in, dqsenable, tipd_dqsenable);
end block;
--------------------------------------
-- Path Delay Section
--------------------------------------
VITAL_path_delays: PROCESS (tmp_dqsbusout)
variable dqsbusout_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => dqsbusout,
OutSignalName => "dqsbusout",
OutTemp => tmp_dqsbusout,
Paths => (0 => (dqsin_in'last_event, tpd_dqsin_dqsbusout, TRUE),
1 => (dqsenable_in'last_event, tpd_dqsenable_dqsbusout, TRUE)),
GlitchData => dqsbusout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
END PROCESS; -- Path Delays
END stratixiii_dqs_enable_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : stratixiii_dqs_enable_ctrl
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
use work.stratixiii_ddr_io_reg;
use work.stratixiii_ddr_delay_chain_s;
ENTITY stratixiii_dqs_enable_ctrl IS
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
level_dqs_enable : string := "false";
delay_dqs_enable_by_half_cycle : string := "false";
add_phase_transfer_reg : string := "false";
invert_phase : string := "false";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
lpm_type : string := "stratixiii_dqs_enable_ctrl";
tipd_dqsenablein : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_enaphasetransferreg : VitalDelayType01 := DefpropDelay01;
tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
dqsenablein : IN std_logic := '1';
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
enaphasetransferreg : IN std_logic := '0';
phaseinvertctrl : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsenableout : OUT std_logic;
dffin : OUT std_logic;
dffextenddqsenable : OUT std_logic
);
END;
ARCHITECTURE stratixiii_dqs_enable_ctrl_arch OF stratixiii_dqs_enable_ctrl IS
-- component section
COMPONENT stratixiii_ddr_delay_chain_s
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
phasectrlin_limit : integer := 7
);
PORT (
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 DOWNTO 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
delayed_clkout : OUT std_logic
);
END COMPONENT;
component stratixiii_ddr_io_reg
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
-- int signals
SIGNAL phasectrl_clkout : std_logic := '0';
SIGNAL delayed_clk : std_logic := '0';
SIGNAL dqsenablein_reg_q : std_logic := '0';
SIGNAL dqsenablein_level_ena : std_logic := '0';
-- transfer delay
SIGNAL dqsenablein_reg_dly : std_logic := '0';
SIGNAL phasetransferdelay_mux_out : std_logic := '0';
SIGNAL dqsenable_delayed_regp : std_logic := '0';
SIGNAL dqsenable_delayed_regn : std_logic := '0';
SIGNAL m_vcc : std_logic := '1';
SIGNAL m_gnd : std_logic := '0';
SIGNAL not_clk_in : std_logic := '1';
SIGNAL not_delayed_clk : std_logic := '1';
-- timing output
SIGNAL tmp_dqsenableout : std_logic := '1';
-- timing input
SIGNAL dqsenablein_in : std_logic := '1';
SIGNAL clk_in : std_logic := '0';
SIGNAL delayctrlin_in : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL phasectrlin_in : std_logic_vector(3 downto 0) := (OTHERS => '0');
SIGNAL enaphasetransferreg_in : std_logic := '0';
SIGNAL phaseinvertctrl_in : std_logic := '0';
BEGIN
-- delay chain
m_delay_chain : stratixiii_ddr_delay_chain_s
GENERIC MAP (
phase_setting => phase_setting,
use_phasectrlin => use_phasectrlin,
delay_buffer_mode => delay_buffer_mode,
sim_low_buffer_intrinsic_delay => sim_low_buffer_intrinsic_delay,
sim_high_buffer_intrinsic_delay => sim_high_buffer_intrinsic_delay,
sim_buffer_delay_increment => sim_buffer_delay_increment
)
PORT MAP(
clk => clk_in,
delayctrlin => delayctrlin_in,
phasectrlin => phasectrlin_in,
delayed_clkout => phasectrl_clkout
);
delayed_clk <= (not phasectrl_clkout) WHEN (invert_phase = "true") ELSE
phasectrl_clkout WHEN (invert_phase = "false") ELSE
(not phasectrl_clkout) WHEN (phaseinvertctrl_in = '1') ELSE
phasectrl_clkout;
not_clk_in <= not clk_in;
not_delayed_clk <= not delayed_clk;
dqsenablein_reg : stratixiii_ddr_io_reg
PORT MAP(
d => dqsenablein_in,
clk => clk_in,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => m_gnd,
asdata => m_gnd,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => dqsenablein_reg_q
);
dqsenable_transfer_reg : stratixiii_ddr_io_reg
PORT MAP (
d => dqsenablein_reg_q,
clk => not_delayed_clk,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => m_gnd,
asdata => m_gnd,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => dqsenablein_reg_dly
);
-- add phase transfer mux
phasetransferdelay_mux_out <= dqsenablein_reg_dly WHEN (add_phase_transfer_reg = "true") ELSE
dqsenablein_reg_q WHEN (add_phase_transfer_reg = "false") ELSE
dqsenablein_reg_dly WHEN (enaphasetransferreg_in = '1') ELSE
dqsenablein_reg_q;
dqsenablein_level_ena <= phasetransferdelay_mux_out WHEN (level_dqs_enable = "true") ELSE dqsenablein_in;
dqsenableout_reg : stratixiii_ddr_io_reg
PORT MAP(
d => dqsenablein_level_ena,
clk => delayed_clk,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => m_gnd,
asdata => m_gnd,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => dqsenable_delayed_regp
);
dqsenableout_extend_reg : stratixiii_ddr_io_reg
PORT MAP(
d => dqsenable_delayed_regp,
clk => not_delayed_clk,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => m_gnd,
asdata => m_gnd,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => dqsenable_delayed_regn
);
tmp_dqsenableout <= dqsenable_delayed_regp WHEN (delay_dqs_enable_by_half_cycle = "false") ELSE
(dqsenable_delayed_regp AND dqsenable_delayed_regn);
dqsenableout <= tmp_dqsenableout;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (dqsenablein_in, dqsenablein, tipd_dqsenablein);
VitalWireDelay (clk_in, clk, tipd_clk);
loopbits_delayctrlin : FOR i in delayctrlin'RANGE GENERATE
VitalWireDelay (delayctrlin_in(i), delayctrlin(i), tipd_delayctrlin(i));
END GENERATE;
loopbits_phasectrlin : FOR i in phasectrlin'RANGE GENERATE
VitalWireDelay (phasectrlin_in(i), phasectrlin(i), tipd_phasectrlin(i));
END GENERATE;
VitalWireDelay (enaphasetransferreg_in, enaphasetransferreg, tipd_enaphasetransferreg);
VitalWireDelay (phaseinvertctrl_in, phaseinvertctrl, tipd_phaseinvertctrl);
end block;
END stratixiii_dqs_enable_ctrl_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : stratixiii_delay_chain
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_delay_chain IS
GENERIC (
sim_delayctrlin_rising_delay_0 : integer := 0;
sim_delayctrlin_rising_delay_1 : integer := 50;
sim_delayctrlin_rising_delay_2 : integer := 100;
sim_delayctrlin_rising_delay_3 : integer := 150;
sim_delayctrlin_rising_delay_4 : integer := 200;
sim_delayctrlin_rising_delay_5 : integer := 250;
sim_delayctrlin_rising_delay_6 : integer := 300;
sim_delayctrlin_rising_delay_7 : integer := 350;
sim_delayctrlin_rising_delay_8 : integer := 400;
sim_delayctrlin_rising_delay_9 : integer := 450;
sim_delayctrlin_rising_delay_10 : integer := 500;
sim_delayctrlin_rising_delay_11 : integer := 550;
sim_delayctrlin_rising_delay_12 : integer := 600;
sim_delayctrlin_rising_delay_13 : integer := 650;
sim_delayctrlin_rising_delay_14 : integer := 700;
sim_delayctrlin_rising_delay_15 : integer := 750;
sim_delayctrlin_falling_delay_0 : integer := 0;
sim_delayctrlin_falling_delay_1 : integer := 50;
sim_delayctrlin_falling_delay_2 : integer := 100;
sim_delayctrlin_falling_delay_3 : integer := 150;
sim_delayctrlin_falling_delay_4 : integer := 200;
sim_delayctrlin_falling_delay_5 : integer := 250;
sim_delayctrlin_falling_delay_6 : integer := 300;
sim_delayctrlin_falling_delay_7 : integer := 350;
sim_delayctrlin_falling_delay_8 : integer := 400;
sim_delayctrlin_falling_delay_9 : integer := 450;
sim_delayctrlin_falling_delay_10 : integer := 500;
sim_delayctrlin_falling_delay_11 : integer := 550;
sim_delayctrlin_falling_delay_12 : integer := 600;
sim_delayctrlin_falling_delay_13 : integer := 650;
sim_delayctrlin_falling_delay_14 : integer := 700;
sim_delayctrlin_falling_delay_15 : integer := 750;
use_delayctrlin : string := "true";
delay_setting : integer := 0;
-- new in STRATIXIV ww30.2008
sim_finedelayctrlin_falling_delay_0 : integer := 0;
sim_finedelayctrlin_falling_delay_1 : integer := 25;
sim_finedelayctrlin_rising_delay_0 : integer := 0;
sim_finedelayctrlin_rising_delay_1 : integer := 25;
use_finedelayctrlin : string := "false";
lpm_type : string := "stratixiii_delay_chain";
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic := '0';
delayctrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
finedelayctrlin : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dataout : OUT std_logic
);
END;
ARCHITECTURE stratixiii_delay_chain_arch OF stratixiii_delay_chain IS
-- type def
type delay_chain_int_vec is array (natural range <>) of integer;
-- component section
-- signal section
SIGNAL rising_dly : INTEGER := 0;
SIGNAL falling_dly : INTEGER := 0;
SIGNAL delayctrlin_in : STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0');
SIGNAL finedelayctrlin_in : STD_LOGIC := '0';
-- timing inputs
SIGNAL tmp_dataout : std_logic := '0';
-- timing inputs
SIGNAL datain_in : std_logic := '0';
BEGIN
-- filtering X/U etc.
delayctrlin_in(0) <= '1' WHEN (delayctrlin(0) = '1') ELSE '0';
delayctrlin_in(1) <= '1' WHEN (delayctrlin(1) = '1') ELSE '0';
delayctrlin_in(2) <= '1' WHEN (delayctrlin(2) = '1') ELSE '0';
delayctrlin_in(3) <= '1' WHEN (delayctrlin(3) = '1') ELSE '0';
finedelayctrlin_in <= '1' WHEN (finedelayctrlin = '1') ELSE '0';
-- generate dynamic delay table and dynamic delay
process(delayctrlin_in, finedelayctrlin_in)
variable init : boolean := true;
variable dly_table_rising : delay_chain_int_vec(15 downto 0) := (OTHERS => 0);
variable dly_table_falling : delay_chain_int_vec(15 downto 0) := (OTHERS => 0);
variable finedly_table_rising : delay_chain_int_vec(1 downto 0) := (OTHERS => 0);
variable finedly_table_falling : delay_chain_int_vec(1 downto 0) := (OTHERS => 0);
variable dly_setting : integer := 0;
variable finedly_setting : integer := 0;
begin
if (init) then
dly_table_rising(0) := sim_delayctrlin_rising_delay_0;
dly_table_rising(1) := sim_delayctrlin_rising_delay_1;
dly_table_rising(2) := sim_delayctrlin_rising_delay_2;
dly_table_rising(3) := sim_delayctrlin_rising_delay_3;
dly_table_rising(4) := sim_delayctrlin_rising_delay_4;
dly_table_rising(5) := sim_delayctrlin_rising_delay_5;
dly_table_rising(6) := sim_delayctrlin_rising_delay_6;
dly_table_rising(7) := sim_delayctrlin_rising_delay_7;
dly_table_rising(8) := sim_delayctrlin_rising_delay_8;
dly_table_rising(9) := sim_delayctrlin_rising_delay_9;
dly_table_rising(10) := sim_delayctrlin_rising_delay_10;
dly_table_rising(11) := sim_delayctrlin_rising_delay_11;
dly_table_rising(12) := sim_delayctrlin_rising_delay_12;
dly_table_rising(13) := sim_delayctrlin_rising_delay_13;
dly_table_rising(14) := sim_delayctrlin_rising_delay_14;
dly_table_rising(15) := sim_delayctrlin_rising_delay_15;
dly_table_falling(0) := sim_delayctrlin_falling_delay_0;
dly_table_falling(1) := sim_delayctrlin_falling_delay_1;
dly_table_falling(2) := sim_delayctrlin_falling_delay_2;
dly_table_falling(3) := sim_delayctrlin_falling_delay_3;
dly_table_falling(4) := sim_delayctrlin_falling_delay_4;
dly_table_falling(5) := sim_delayctrlin_falling_delay_5;
dly_table_falling(6) := sim_delayctrlin_falling_delay_6;
dly_table_falling(7) := sim_delayctrlin_falling_delay_7;
dly_table_falling(8) := sim_delayctrlin_falling_delay_8;
dly_table_falling(9) := sim_delayctrlin_falling_delay_9;
dly_table_falling(10) := sim_delayctrlin_falling_delay_10;
dly_table_falling(11) := sim_delayctrlin_falling_delay_11;
dly_table_falling(12) := sim_delayctrlin_falling_delay_12;
dly_table_falling(13) := sim_delayctrlin_falling_delay_13;
dly_table_falling(14) := sim_delayctrlin_falling_delay_14;
dly_table_falling(15) := sim_delayctrlin_falling_delay_15;
finedly_table_rising(0) := sim_finedelayctrlin_rising_delay_0;
finedly_table_rising(1) := sim_finedelayctrlin_rising_delay_1;
finedly_table_falling(0) := sim_finedelayctrlin_falling_delay_0;
finedly_table_falling(1) := sim_finedelayctrlin_falling_delay_1;
init := false;
end if;
IF (use_delayctrlin = "false") THEN
dly_setting := delay_setting;
ELSE
dly_setting := alt_conv_integer(delayctrlin_in);
END IF;
IF (finedelayctrlin_in = '1') THEN
finedly_setting := 1;
ELSE
finedly_setting := 0;
END IF;
IF (use_finedelayctrlin = "true") THEN
rising_dly <= dly_table_rising(dly_setting) + finedly_table_rising(finedly_setting);
falling_dly <= dly_table_falling(dly_setting) + finedly_table_falling(finedly_setting);
ELSE
rising_dly <= dly_table_rising(dly_setting);
falling_dly <= dly_table_falling(dly_setting);
END IF;
end process; -- generating dynamic delays
PROCESS(datain_in)
BEGIN
if (datain_in = '0') then
tmp_dataout <= transport datain_in after (falling_dly * 1 ps);
else
tmp_dataout <= transport datain_in after (rising_dly * 1 ps);
end if;
END PROCESS;
----------------------------------
-- Path Delay Section
----------------------------------
VITAL: process(tmp_dataout)
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "dataout",
OutTemp => tmp_dataout,
Paths => (0 => (datain_in'last_event, tpd_datain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (datain_in, datain, tipd_datain);
end block;
END stratixiii_delay_chain_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : stratixiii_io_clock_divider
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
use work.stratixiii_ddr_delay_chain_s;
ENTITY stratixiii_io_clock_divider IS
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
use_masterin : string := "false";
invert_phase : string := "false";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
lpm_type : string := "stratixiii_io_clock_divider";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_phaseselect : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01;
tipd_masterin : VitalDelayType01 := DefpropDelay01;
tpd_clk_clkout : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
clk : IN std_logic := '0';
phaseselect : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
phaseinvertctrl : IN std_logic := '0';
masterin : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
clkout : OUT std_logic;
slaveout : OUT std_logic
);
END;
ARCHITECTURE stratixiii_io_clock_divider_arch OF stratixiii_io_clock_divider IS
-- component section
COMPONENT stratixiii_ddr_delay_chain_s
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
phasectrlin_limit : integer := 7
);
PORT (
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 DOWNTO 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
delayed_clkout : OUT std_logic
);
END COMPONENT;
-- int signals
SIGNAL phasectrl_clkout : STD_LOGIC := '0';
SIGNAL delayed_clk : STD_LOGIC := '0';
SIGNAL divided_clk_in : STD_LOGIC := '0';
SIGNAL divided_clk : STD_LOGIC := '0';
-- timing outputs
SIGNAL tmp_clkout : STD_LOGIC := '0';
-- timing inputs
SIGNAL clk_in : std_logic := '0';
SIGNAL phaseselect_in : std_logic := '0';
SIGNAL delayctrlin_in : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL phasectrlin_in : std_logic_vector(3 downto 0) := (OTHERS => '0');
SIGNAL phaseinvertctrl_in : std_logic := '0';
SIGNAL masterin_in : std_logic := '0';
BEGIN
-- delay chain
m_delay_chain : stratixiii_ddr_delay_chain_s
GENERIC MAP (
phase_setting => phase_setting,
use_phasectrlin => use_phasectrlin,
delay_buffer_mode => delay_buffer_mode,
sim_low_buffer_intrinsic_delay => sim_low_buffer_intrinsic_delay,
sim_high_buffer_intrinsic_delay => sim_high_buffer_intrinsic_delay,
sim_buffer_delay_increment => sim_buffer_delay_increment
)
PORT MAP(
clk => clk_in,
delayctrlin => delayctrlin_in,
phasectrlin => phasectrlin_in,
delayed_clkout => phasectrl_clkout
);
delayed_clk <= (not phasectrl_clkout) WHEN (invert_phase = "true") ELSE
phasectrl_clkout WHEN (invert_phase = "false") ELSE
(not phasectrl_clkout) WHEN (phaseinvertctrl_in = '1') ELSE
phasectrl_clkout;
divided_clk_in <= masterin_in WHEN (use_masterin = "true") ELSE divided_clk;
PROCESS (delayed_clk)
BEGIN
if (delayed_clk = '1') then
divided_clk <= not divided_clk_in;
end if;
END PROCESS;
tmp_clkout <= (not divided_clk) WHEN (phaseselect_in = '1') ELSE divided_clk;
slaveout <= divided_clk;
----------------------------------
-- Path Delay Section
----------------------------------
VITAL: process(tmp_clkout)
variable clkout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => clkout,
OutSignalName => "clkout",
OutTemp => tmp_clkout,
Paths => (0 => (clk_in'last_event, tpd_clk_clkout, TRUE)),
GlitchData => clkout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (clk_in, clk, tipd_clk);
VitalWireDelay (phaseselect_in, phaseselect, tipd_phaseselect);
loopbits_delayctrlin : FOR i in delayctrlin'RANGE GENERATE
VitalWireDelay (delayctrlin_in(i), delayctrlin(i), tipd_delayctrlin(i));
END GENERATE;
loopbits_phasectrlin : FOR i in phasectrlin'RANGE GENERATE
VitalWireDelay (phasectrlin_in(i), phasectrlin(i), tipd_phasectrlin(i));
END GENERATE;
VitalWireDelay (phaseinvertctrl_in, phaseinvertctrl, tipd_phaseinvertctrl);
VitalWireDelay (masterin_in, masterin, tipd_masterin);
end block;
END stratixiii_io_clock_divider_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : stratixiii_output_phase_alignment
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
use work.stratixiii_ddr_io_reg;
use work.stratixiii_ddr_delay_chain_s;
ENTITY stratixiii_output_phase_alignment IS
GENERIC (
operation_mode : string := "ddio_out";
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
add_output_cycle_delay : string := "false";
use_delayed_clock : string := "false";
add_phase_transfer_reg : string := "false";
use_phasectrl_clock : string := "true";
use_primary_clock : string := "true";
invert_phase : string := "false";
bypass_input_register : string := "false";
phase_setting_for_delayed_clock : integer := 2;
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
-- new in STRATIXIV: ww30.2008
duty_cycle_delay_mode : string := "none";
sim_dutycycledelayctrlin_falling_delay_0 : integer := 0 ;
sim_dutycycledelayctrlin_falling_delay_1 : integer := 25 ;
sim_dutycycledelayctrlin_falling_delay_10 : integer := 250 ;
sim_dutycycledelayctrlin_falling_delay_11 : integer := 275 ;
sim_dutycycledelayctrlin_falling_delay_12 : integer := 300 ;
sim_dutycycledelayctrlin_falling_delay_13 : integer := 325 ;
sim_dutycycledelayctrlin_falling_delay_14 : integer := 350 ;
sim_dutycycledelayctrlin_falling_delay_15 : integer := 375 ;
sim_dutycycledelayctrlin_falling_delay_2 : integer := 50 ;
sim_dutycycledelayctrlin_falling_delay_3 : integer := 75 ;
sim_dutycycledelayctrlin_falling_delay_4 : integer := 100 ;
sim_dutycycledelayctrlin_falling_delay_5 : integer := 125 ;
sim_dutycycledelayctrlin_falling_delay_6 : integer := 150 ;
sim_dutycycledelayctrlin_falling_delay_7 : integer := 175 ;
sim_dutycycledelayctrlin_falling_delay_8 : integer := 200 ;
sim_dutycycledelayctrlin_falling_delay_9 : integer := 225 ;
sim_dutycycledelayctrlin_rising_delay_0 : integer := 0 ;
sim_dutycycledelayctrlin_rising_delay_1 : integer := 25 ;
sim_dutycycledelayctrlin_rising_delay_10 : integer := 250 ;
sim_dutycycledelayctrlin_rising_delay_11 : integer := 275 ;
sim_dutycycledelayctrlin_rising_delay_12 : integer := 300 ;
sim_dutycycledelayctrlin_rising_delay_13 : integer := 325 ;
sim_dutycycledelayctrlin_rising_delay_14 : integer := 350 ;
sim_dutycycledelayctrlin_rising_delay_15 : integer := 375 ;
sim_dutycycledelayctrlin_rising_delay_2 : integer := 50 ;
sim_dutycycledelayctrlin_rising_delay_3 : integer := 75 ;
sim_dutycycledelayctrlin_rising_delay_4 : integer := 100 ;
sim_dutycycledelayctrlin_rising_delay_5 : integer := 125 ;
sim_dutycycledelayctrlin_rising_delay_6 : integer := 150 ;
sim_dutycycledelayctrlin_rising_delay_7 : integer := 175 ;
sim_dutycycledelayctrlin_rising_delay_8 : integer := 200 ;
sim_dutycycledelayctrlin_rising_delay_9 : integer := 225 ;
lpm_type : string := "stratixiii_output_phase_alignment";
tipd_datain : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_areset : VitalDelayType01 := DefpropDelay01;
tipd_sreset : VitalDelayType01 := DefpropDelay01;
tipd_clkena : VitalDelayType01 := DefpropDelay01;
tipd_enaoutputcycledelay : VitalDelayType01 := DefpropDelay01;
tipd_enaphasetransferreg : VitalDelayType01 := DefpropDelay01;
tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic_vector(1 downto 0) := (OTHERS => '0');
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
clkena : IN std_logic := '1';
enaoutputcycledelay : IN std_logic := '0';
enaphasetransferreg : IN std_logic := '0';
phaseinvertctrl : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
delaymode : IN std_logic := '0'; -- new in STRATIXIV: ww30.2008
dutycycledelayctrlin: IN std_logic_vector(3 downto 0) := (OTHERS => '0');
dataout : OUT std_logic;
dffin : OUT std_logic_vector(1 downto 0);
dff1t : OUT std_logic_vector(1 downto 0);
dffddiodataout : OUT std_logic
);
END;
ARCHITECTURE stratixiii_output_phase_alignment_arch OF stratixiii_output_phase_alignment IS
-- type def
type delay_chain_int_vec is array (natural range <>) of integer;
-- component section
COMPONENT stratixiii_ddr_delay_chain_s
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
phasectrlin_limit : integer := 7
);
PORT (
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 DOWNTO 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
delayed_clkout : OUT std_logic
);
END COMPONENT;
component stratixiii_ddr_io_reg
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
-- int signals on clock paths
SIGNAL clk_in_delayed: STD_LOGIC := '0';
SIGNAL clk_in_mux: STD_LOGIC := '0';
SIGNAL phasectrl_clkout: STD_LOGIC := '0';
SIGNAL phaseinvertctrl_out: STD_LOGIC := '0';
SIGNAL m_vcc: STD_LOGIC := '1';
SIGNAL m_gnd: STD_LOGIC := '0';
-- IO registers
-- common
SIGNAL adatasdata_in_r : STD_LOGIC := '0'; -- sync reset - common for transfer and output reg
SIGNAL sclr_in_r : STD_LOGIC := '0';
SIGNAL sload_in_r : STD_LOGIC := '0';
SIGNAL sclr_in : STD_LOGIC := '0';
SIGNAL sload_in : STD_LOGIC := '0';
SIGNAL adatasdata_in : STD_LOGIC := '0';
SIGNAL clrn_in_r : STD_LOGIC := '1'; -- async reset - common for all registers
SIGNAL prn_in_r : STD_LOGIC := '1';
SIGNAL datain_q: STD_LOGIC := '0';
SIGNAL ddio_datain_q: STD_LOGIC := '0';
SIGNAL cycledelay_q: STD_LOGIC := '0';
SIGNAL ddio_cycledelay_q: STD_LOGIC := '0';
SIGNAL cycledelay_mux_out: STD_LOGIC := '0';
SIGNAL ddio_cycledelay_mux_out: STD_LOGIC := '0';
SIGNAL bypass_input_reg_mux_out : STD_LOGIC := '0';
SIGNAL ddio_bypass_input_reg_mux_out : STD_LOGIC := '0';
SIGNAL not_clk_in_mux: STD_LOGIC := '0';
SIGNAL ddio_out_clk_mux: STD_LOGIC := '0';
SIGNAL ddio_out_lo_q: STD_LOGIC := '0';
SIGNAL ddio_out_hi_q: STD_LOGIC := '0';
-- transfer delay now by negative clk
SIGNAL transfer_q: STD_LOGIC := '0';
SIGNAL ddio_transfer_q: STD_LOGIC := '0';
-- Duty Cycle Delay
SIGNAL dcd_in : STD_LOGIC := '0';
SIGNAL dcd_out : STD_LOGIC := '0';
SIGNAL dcd_both : STD_LOGIC := '0';
SIGNAL dcd_both_gnd : STD_LOGIC := '0';
SIGNAL dcd_both_vcc : STD_LOGIC := '0';
SIGNAL dcd_fallnrise : STD_LOGIC := '0';
SIGNAL dcd_fallnrise_gnd : STD_LOGIC := '0';
SIGNAL dcd_fallnrise_vcc : STD_LOGIC := '0';
SIGNAL dcd_rising_dly : INTEGER := 0;
SIGNAL dcd_falling_dly : INTEGER := 0;
SIGNAL dlyclk_clk: STD_LOGIC := '0';
SIGNAL dlyclk_d: STD_LOGIC := '0';
SIGNAL dlyclk_q: STD_LOGIC := '0';
SIGNAL ddio_dlyclk_d: STD_LOGIC := '0';
SIGNAL ddio_dlyclk_q: STD_LOGIC := '0';
SIGNAL dlyclk_clkena_in: STD_LOGIC := '0'; -- shared
SIGNAL dlyclk_extended_q: STD_LOGIC := '0';
SIGNAL dlyclk_extended_clk: STD_LOGIC := '0';
SIGNAL normal_dataout: STD_LOGIC := '0';
SIGNAL extended_dataout: STD_LOGIC := '0';
SIGNAL ddio_dataout: STD_LOGIC := '0';
SIGNAL tmp_dataout: STD_LOGIC := '0';
-- timing inputs
SIGNAL datain_in : std_logic_vector(1 downto 0) := (OTHERS => '0');
SIGNAL clk_in : std_logic := '0';
SIGNAL delayctrlin_in : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL phasectrlin_in : std_logic_vector(3 downto 0) := (OTHERS => '0');
SIGNAL areset_in : std_logic := '0';
SIGNAL sreset_in : std_logic := '0';
SIGNAL clkena_in : std_logic := '1';
SIGNAL enaoutputcycledelay_in : std_logic := '0';
SIGNAL enaphasetransferreg_in : std_logic := '0';
SIGNAL phaseinvertctrl_in : std_logic := '0';
SIGNAL delaymode_in: std_logic := '0';
SIGNAL dutycycledelayctrlin_in : std_logic_vector(3 downto 0) := (OTHERS => '0');
BEGIN
-- filtering X/U etc.
delaymode_in <= '1' WHEN (delaymode = '1') ELSE '0';
dutycycledelayctrlin_in(0) <= '1' WHEN (dutycycledelayctrlin(0) = '1') ELSE '0';
dutycycledelayctrlin_in(1) <= '1' WHEN (dutycycledelayctrlin(1) = '1') ELSE '0';
dutycycledelayctrlin_in(2) <= '1' WHEN (dutycycledelayctrlin(2) = '1') ELSE '0';
dutycycledelayctrlin_in(3) <= '1' WHEN (dutycycledelayctrlin(3) = '1') ELSE '0';
-- delay chain for clk_in delay
m_clk_in_delay_chain : stratixiii_ddr_delay_chain_s
GENERIC MAP (
phase_setting => phase_setting_for_delayed_clock,
use_phasectrlin => "false",
delay_buffer_mode => delay_buffer_mode,
sim_low_buffer_intrinsic_delay => sim_low_buffer_intrinsic_delay,
sim_high_buffer_intrinsic_delay => sim_high_buffer_intrinsic_delay,
sim_buffer_delay_increment => sim_buffer_delay_increment
)
PORT MAP(
clk => clk_in,
delayctrlin => delayctrlin_in,
phasectrlin => phasectrlin_in,
delayed_clkout => clk_in_delayed
);
-- clock source for datain and cycle delay registers
clk_in_mux <= clk_in_delayed WHEN (use_delayed_clock = "true") ELSE clk_in;
-- delay chain for phase control
m_delay_chain : stratixiii_ddr_delay_chain_s
GENERIC MAP (
phase_setting => phase_setting,
use_phasectrlin => use_phasectrlin,
delay_buffer_mode => delay_buffer_mode,
sim_low_buffer_intrinsic_delay => sim_low_buffer_intrinsic_delay,
sim_high_buffer_intrinsic_delay => sim_high_buffer_intrinsic_delay,
phasectrlin_limit => 10,
sim_buffer_delay_increment => sim_buffer_delay_increment
)
PORT MAP(
clk => clk_in,
delayctrlin => delayctrlin_in,
phasectrlin => phasectrlin_in,
delayed_clkout => phasectrl_clkout
);
-- primary outputs
normal_dataout <= dlyclk_q;
extended_dataout <= dlyclk_q OR dlyclk_extended_q; -- oe port is active low
ddio_dataout <= ddio_out_hi_q WHEN (ddio_out_clk_mux = '1') ELSE ddio_out_lo_q;
tmp_dataout <= ddio_dataout WHEN (operation_mode = "ddio_out") ELSE
extended_dataout WHEN (operation_mode = "extended_oe" OR operation_mode = "extended_rtena") ELSE
normal_dataout WHEN (operation_mode = "output" OR operation_mode = "oe" OR operation_mode = "rtena") ELSE
'Z';
dataout <= tmp_dataout;
ddio_out_clk_mux <= dlyclk_clk after 1 ps; -- symbolic T4 to remove glitch on data_h
ddio_out_lo_q <= dlyclk_q after 2 ps; -- symbolic 2 T4 to remove glitch on data_l
ddio_out_hi_q <= ddio_dlyclk_q;
-- resolve reset modes
PROCESS(areset_in)
BEGIN
IF (async_mode = "clear") THEN
clrn_in_r <= not areset_in;
prn_in_r <= '1';
ELSIF (async_mode = "preset") THEN
prn_in_r <= not areset_in;
clrn_in_r <= '1';
END IF;
END PROCESS;
PROCESS(sreset_in)
BEGIN
IF (sync_mode = "clear") THEN
sclr_in_r <= sreset_in;
adatasdata_in_r <= '0';
sload_in_r <= '0';
ELSIF (sync_mode = "preset") THEN
sload_in_r <= sreset_in;
adatasdata_in_r <= '1';
sclr_in_r <= '0';
END IF;
END PROCESS;
sclr_in <= '0' WHEN (operation_mode = "rtena" OR operation_mode = "extended_rtena") ELSE sclr_in_r;
sload_in <= '0' WHEN (operation_mode = "rtena" OR operation_mode = "extended_rtena") ELSE sload_in_r;
adatasdata_in <= adatasdata_in_r;
dlyclk_clkena_in <= '1' WHEN (operation_mode = "rtena" OR operation_mode = "extended_rtena") ELSE clkena_in;
-- Datain Register
datain_reg : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_in(0),
clk => clk_in_mux,
ena => m_vcc,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => datain_q
);
-- DDIO Datain Register
ddio_datain_reg : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_in(1),
clk => clk_in_mux,
ena => m_vcc,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => ddio_datain_q
);
-- Cycle Delay Register
cycledelay_reg : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_q,
clk => clk_in_mux,
ena => m_vcc,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => cycledelay_q
);
-- DDIO Cycle Delay Register
ddio_cycledelay_reg : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => ddio_datain_q,
clk => clk_in_mux,
ena => m_vcc,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => ddio_cycledelay_q
);
-- enaoutputcycledelay data path mux
cycledelay_mux_out <= cycledelay_q WHEN (add_output_cycle_delay = "true") ELSE
datain_q WHEN (add_output_cycle_delay = "false") ELSE
cycledelay_q WHEN (enaoutputcycledelay_in = m_vcc) ELSE
datain_q;
-- input register bypass mux
bypass_input_reg_mux_out <= datain_in(0) WHEN (bypass_input_register = "true") ELSE cycledelay_mux_out;
--assign #300 transfer_q = cycledelay_mux_out;
-- transfer delay is implemented with negative register in rev1.26
transferdelay_reg : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => bypass_input_reg_mux_out,
clk => not_clk_in_mux,
ena => m_vcc,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => sclr_in,
sload => sload_in,
devclrn => devclrn,
devpor => devpor,
q => transfer_q
);
-- add phase transfer data path mux
dlyclk_d <= transfer_q WHEN (add_phase_transfer_reg = "true") ELSE
bypass_input_reg_mux_out WHEN (add_phase_transfer_reg = "false") ELSE
transfer_q WHEN (enaphasetransferreg_in = m_vcc) ELSE
bypass_input_reg_mux_out;
-- clock mux for the output register
phaseinvertctrl_out <= (not phasectrl_clkout) WHEN (invert_phase = "true") ELSE
phasectrl_clkout WHEN (invert_phase = "false") ELSE
(not phasectrl_clkout) WHEN (phaseinvertctrl_in = m_vcc) ELSE
phasectrl_clkout;
-- Duty Cycle Delay
dcd_in <= phaseinvertctrl_out WHEN (use_phasectrl_clock = "true") ELSE clk_in_mux;
PROCESS(dutycycledelayctrlin_in)
variable init : boolean := true;
variable dcd_table_rising : delay_chain_int_vec(15 downto 0) := (OTHERS => 0);
variable dcd_table_falling : delay_chain_int_vec(15 downto 0) := (OTHERS => 0);
variable dcd_dly_setting : integer := 0;
begin
if (init) then
dcd_table_rising(0) := sim_dutycycledelayctrlin_rising_delay_0;
dcd_table_rising(1) := sim_dutycycledelayctrlin_rising_delay_1;
dcd_table_rising(2) := sim_dutycycledelayctrlin_rising_delay_2;
dcd_table_rising(3) := sim_dutycycledelayctrlin_rising_delay_3;
dcd_table_rising(4) := sim_dutycycledelayctrlin_rising_delay_4;
dcd_table_rising(5) := sim_dutycycledelayctrlin_rising_delay_5;
dcd_table_rising(6) := sim_dutycycledelayctrlin_rising_delay_6;
dcd_table_rising(7) := sim_dutycycledelayctrlin_rising_delay_7;
dcd_table_rising(8) := sim_dutycycledelayctrlin_rising_delay_8;
dcd_table_rising(9) := sim_dutycycledelayctrlin_rising_delay_9;
dcd_table_rising(10) := sim_dutycycledelayctrlin_rising_delay_10;
dcd_table_rising(11) := sim_dutycycledelayctrlin_rising_delay_11;
dcd_table_rising(12) := sim_dutycycledelayctrlin_rising_delay_12;
dcd_table_rising(13) := sim_dutycycledelayctrlin_rising_delay_13;
dcd_table_rising(14) := sim_dutycycledelayctrlin_rising_delay_14;
dcd_table_rising(15) := sim_dutycycledelayctrlin_rising_delay_15;
dcd_table_falling(0) := sim_dutycycledelayctrlin_falling_delay_0;
dcd_table_falling(1) := sim_dutycycledelayctrlin_falling_delay_1;
dcd_table_falling(2) := sim_dutycycledelayctrlin_falling_delay_2;
dcd_table_falling(3) := sim_dutycycledelayctrlin_falling_delay_3;
dcd_table_falling(4) := sim_dutycycledelayctrlin_falling_delay_4;
dcd_table_falling(5) := sim_dutycycledelayctrlin_falling_delay_5;
dcd_table_falling(6) := sim_dutycycledelayctrlin_falling_delay_6;
dcd_table_falling(7) := sim_dutycycledelayctrlin_falling_delay_7;
dcd_table_falling(8) := sim_dutycycledelayctrlin_falling_delay_8;
dcd_table_falling(9) := sim_dutycycledelayctrlin_falling_delay_9;
dcd_table_falling(10) := sim_dutycycledelayctrlin_falling_delay_10;
dcd_table_falling(11) := sim_dutycycledelayctrlin_falling_delay_11;
dcd_table_falling(12) := sim_dutycycledelayctrlin_falling_delay_12;
dcd_table_falling(13) := sim_dutycycledelayctrlin_falling_delay_13;
dcd_table_falling(14) := sim_dutycycledelayctrlin_falling_delay_14;
dcd_table_falling(15) := sim_dutycycledelayctrlin_falling_delay_15;
init := false;
end if;
dcd_dly_setting := alt_conv_integer(dutycycledelayctrlin_in);
dcd_rising_dly <= dcd_table_rising(dcd_dly_setting);
dcd_falling_dly <= dcd_table_falling(dcd_dly_setting);
end process; -- generating dynamic delays
PROCESS(dcd_in)
BEGIN
dcd_both_gnd <= dcd_in;
if (dcd_in = '0') then
dcd_both_vcc <= transport dcd_in after (dcd_falling_dly * 1 ps);
else
dcd_both_vcc <= transport dcd_in after (dcd_rising_dly * 1 ps);
end if;
END PROCESS;
PROCESS(dcd_in)
BEGIN
if (dcd_in = '0') then
dcd_fallnrise_gnd <= transport dcd_in after (dcd_falling_dly * 1 ps);
else
dcd_fallnrise_vcc <= transport dcd_in after (dcd_rising_dly * 1 ps);
end if;
END PROCESS;
dcd_both <= dcd_both_vcc WHEN (delaymode_in = '1') ELSE dcd_both_gnd;
dcd_fallnrise <= dcd_fallnrise_vcc WHEN (delaymode_in = '1') ELSE dcd_fallnrise_gnd;
dlyclk_clk <= dcd_both WHEN (duty_cycle_delay_mode = "both") ELSE
dcd_fallnrise WHEN (duty_cycle_delay_mode = "fallnrise") ELSE dcd_in;
-- Output Register clocked by phasectrl_clk
dlyclk_reg : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => dlyclk_d,
clk => dlyclk_clk,
ena => dlyclk_clkena_in,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => sclr_in,
sload => sload_in,
devclrn => devclrn,
devpor => devpor,
q => dlyclk_q
);
-- enaoutputcycledelay data path mux
ddio_cycledelay_mux_out <= ddio_cycledelay_q WHEN (add_output_cycle_delay = "true") ELSE
ddio_datain_q WHEN (add_output_cycle_delay = "false") ELSE
ddio_cycledelay_q WHEN (enaoutputcycledelay_in = m_vcc) ELSE
ddio_datain_q;
-- input register bypass mux
ddio_bypass_input_reg_mux_out <= datain_in(1) WHEN (bypass_input_register = "true") ELSE ddio_cycledelay_mux_out;
--assign #300 ddio_transfer_q = ddio_cycledelay_mux_out;
-- transfer delay is implemented with negative register in rev1.26
not_clk_in_mux <= not clk_in_mux;
ddio_transferdelay_reg : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => ddio_bypass_input_reg_mux_out,
clk => not_clk_in_mux,
ena => m_vcc,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => sclr_in,
sload => sload_in,
devclrn => devclrn,
devpor => devpor,
q => ddio_transfer_q
);
-- add phase transfer data path mux
ddio_dlyclk_d <= ddio_transfer_q WHEN (add_phase_transfer_reg = "true") ELSE
ddio_bypass_input_reg_mux_out WHEN (add_phase_transfer_reg = "false") ELSE
ddio_transfer_q WHEN (enaphasetransferreg_in = m_vcc) ELSE
ddio_bypass_input_reg_mux_out;
-- Output Register clocked by phasectrl_clk
ddio_dlyclk_reg : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => ddio_dlyclk_d,
clk => dlyclk_clk,
ena => dlyclk_clkena_in,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => sclr_in,
sload => sload_in,
devclrn => devclrn,
devpor => devpor,
q => ddio_dlyclk_q
);
-- Extension Register
dlyclk_extended_clk <= not dlyclk_clk;
dlyclk_extended_reg : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => dlyclk_q,
clk => dlyclk_extended_clk,
ena => dlyclk_clkena_in,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => sclr_in,
sload => sload_in,
devclrn => devclrn,
devpor => devpor,
q => dlyclk_extended_q
);
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
loopbits_datain : FOR i in datain'RANGE GENERATE
VitalWireDelay (datain_in(i), datain(i), tipd_datain(i));
END GENERATE;
VitalWireDelay (clk_in, clk, tipd_clk);
loopbits_delayctrlin : FOR i in delayctrlin'RANGE GENERATE
VitalWireDelay (delayctrlin_in(i), delayctrlin(i), tipd_delayctrlin(i));
END GENERATE;
loopbits_phasectrlin : FOR i in phasectrlin'RANGE GENERATE
VitalWireDelay (phasectrlin_in(i), phasectrlin(i), tipd_phasectrlin(i));
END GENERATE;
VitalWireDelay (areset_in, areset, tipd_areset);
VitalWireDelay (sreset_in, sreset, tipd_sreset);
VitalWireDelay (clkena_in, clkena, tipd_clkena);
VitalWireDelay (enaoutputcycledelay_in, enaoutputcycledelay, tipd_enaoutputcycledelay);
VitalWireDelay (enaphasetransferreg_in, enaphasetransferreg, tipd_enaphasetransferreg);
VitalWireDelay (phaseinvertctrl_in, phaseinvertctrl, tipd_phaseinvertctrl);
end block;
END stratixiii_output_phase_alignment_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : stratixiii_input_phase_alignment
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
use work.stratixiii_ddr_io_reg;
use work.stratixiii_ddr_delay_chain_s;
ENTITY stratixiii_input_phase_alignment IS
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
power_up : string := "low";
async_mode : string := "none";
add_input_cycle_delay : string := "false";
bypass_output_register : string := "false";
add_phase_transfer_reg : string := "false";
invert_phase : string := "false";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
lpm_type : string := "stratixiii_input_phase_alignment";
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_areset : VitalDelayType01 := DefpropDelay01;
tipd_enainputcycledelay : VitalDelayType01 := DefpropDelay01;
tipd_enaphasetransferreg : VitalDelayType01 := DefpropDelay01;
tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
areset : IN std_logic := '0';
enainputcycledelay : IN std_logic := '0';
enaphasetransferreg : IN std_logic := '0';
phaseinvertctrl : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dataout : OUT std_logic;
dffin : OUT std_logic;
dff1t : OUT std_logic
);
END;
ARCHITECTURE stratixiii_input_phase_alignment_arch OF stratixiii_input_phase_alignment IS
-- component section
COMPONENT stratixiii_ddr_delay_chain_s
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
phasectrlin_limit : integer := 7
);
PORT (
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 DOWNTO 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
delayed_clkout : OUT std_logic
);
END COMPONENT;
component stratixiii_ddr_io_reg
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
-- int signals
SIGNAL phasectrl_clkout : STD_LOGIC := '0';
SIGNAL delayed_clk : STD_LOGIC := '0';
SIGNAL not_delayed_clk : STD_LOGIC := '1';
SIGNAL m_vcc: STD_LOGIC := '1';
SIGNAL m_gnd: STD_LOGIC := '0';
-- IO registers
-- common
SIGNAL adatasdata_in_r : STD_LOGIC := '0';
SIGNAL aload_in_r : STD_LOGIC := '0';
SIGNAL datain_q : STD_LOGIC := '0';
SIGNAL cycledelay_q : STD_LOGIC := '0';
SIGNAL cycledelay_mux_out : STD_LOGIC := '0';
SIGNAL cycledelay_mux_out_dly : STD_LOGIC := '0';
SIGNAL dlyclk_d : STD_LOGIC := '0';
SIGNAL dlyclk_q : STD_LOGIC := '0';
SIGNAL tmp_dataout : STD_LOGIC := '0';
-- timing inputs
SIGNAL datain_in : std_logic := '0';
SIGNAL clk_in : std_logic := '0';
SIGNAL delayctrlin_in : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL phasectrlin_in : std_logic_vector(3 downto 0) := (OTHERS => '0');
SIGNAL areset_in : std_logic := '0';
SIGNAL enainputcycledelay_in : std_logic := '0';
SIGNAL enaphasetransferreg_in : std_logic := '0';
SIGNAL phaseinvertctrl_in : std_logic := '0';
BEGIN
m_clk_in_delay_chain : stratixiii_ddr_delay_chain_s
GENERIC MAP (
phase_setting => phase_setting,
use_phasectrlin => use_phasectrlin,
delay_buffer_mode => delay_buffer_mode,
sim_low_buffer_intrinsic_delay => sim_low_buffer_intrinsic_delay,
sim_high_buffer_intrinsic_delay => sim_high_buffer_intrinsic_delay,
sim_buffer_delay_increment => sim_buffer_delay_increment
)
PORT MAP(
clk => clk_in,
delayctrlin => delayctrlin_in,
phasectrlin => phasectrlin_in,
delayed_clkout => phasectrl_clkout
);
delayed_clk <= (not phasectrl_clkout) WHEN (invert_phase = "true") ELSE
phasectrl_clkout WHEN (invert_phase = "false") ELSE
(not phasectrl_clkout) WHEN (phaseinvertctrl_in = '1') ELSE
phasectrl_clkout;
-- primary output
dataout <= tmp_dataout;
tmp_dataout <= dlyclk_d WHEN (bypass_output_register = "true") ELSE dlyclk_q;
-- add phase transfer data path mux
dlyclk_d <= cycledelay_mux_out_dly WHEN (add_phase_transfer_reg = "true") ELSE
cycledelay_mux_out WHEN (add_phase_transfer_reg = "false") ELSE
cycledelay_mux_out_dly WHEN (enaphasetransferreg_in = '1') ELSE
cycledelay_mux_out;
-- enaoutputcycledelay data path mux
cycledelay_mux_out <= cycledelay_q WHEN (add_input_cycle_delay = "true") ELSE
datain_q WHEN (add_input_cycle_delay = "false") ELSE
cycledelay_q WHEN (enainputcycledelay_in = '1') ELSE
datain_q;
-- resolve reset modes
PROCESS (areset_in)
BEGIN
if (async_mode = "clear") then
aload_in_r <= areset_in;
adatasdata_in_r <= '0';
elsif (async_mode = "preset") then
aload_in_r <= areset_in;
adatasdata_in_r <= '1';
else -- async_mode = "none"
adatasdata_in_r <= 'Z';
end if;
END PROCESS;
-- Datain Register
datain_reg : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_in,
clk => delayed_clk,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => datain_q
);
-- Cycle Delay Register
cycledelay_reg : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_q,
clk => delayed_clk,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => cycledelay_q
);
-- assign #300 cycledelay_mux_out_dly = cycledelay_mux_out; replaced by neg reg
-- Transfer Register - clocked by negative edge
not_delayed_clk <= not delayed_clk;
transfer_reg : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => cycledelay_mux_out,
clk => not_delayed_clk, -- ~delayed_clk
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => cycledelay_mux_out_dly
);
-- Register clocked by actually by clk_in
dlyclk_reg : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => dlyclk_d,
clk => clk_in,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => dlyclk_q
);
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (datain_in, datain, tipd_datain);
VitalWireDelay (clk_in, clk, tipd_clk);
loopbits_delayctrlin : FOR i in delayctrlin'RANGE GENERATE
VitalWireDelay (delayctrlin_in(i), delayctrlin(i), tipd_delayctrlin(i));
END GENERATE;
loopbits_phasectrlin : FOR i in phasectrlin'RANGE GENERATE
VitalWireDelay (phasectrlin_in(i), phasectrlin(i), tipd_phasectrlin(i));
END GENERATE;
VitalWireDelay (areset_in, areset, tipd_areset);
VitalWireDelay (enainputcycledelay_in, enainputcycledelay, tipd_enainputcycledelay);
VitalWireDelay (enaphasetransferreg_in, enaphasetransferreg, tipd_enaphasetransferreg);
VitalWireDelay (phaseinvertctrl_in, phaseinvertctrl, tipd_phaseinvertctrl);
end block;
END stratixiii_input_phase_alignment_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : stratixiii_half_rate_input
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
use work.stratixiii_ddr_io_reg;
ENTITY stratixiii_half_rate_input IS
GENERIC (
power_up : string := "low";
async_mode : string := "none";
use_dataoutbypass : string := "false";
lpm_type : string := "stratixiii_half_rate_input";
tipd_datain : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_directin : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_areset : VitalDelayType01 := DefpropDelay01;
tipd_dataoutbypass : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic_vector(1 downto 0) := (OTHERS => '0');
directin : IN std_logic := '0';
clk : IN std_logic := '0';
areset : IN std_logic := '0';
dataoutbypass: IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dataout : OUT std_logic_vector(3 downto 0);
dffin : OUT std_logic
);
END;
ARCHITECTURE stratixiii_half_rate_input_arch OF stratixiii_half_rate_input IS
-- component section
component stratixiii_ddr_io_reg
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
SIGNAL m_vcc: STD_LOGIC := '1';
SIGNAL m_gnd: STD_LOGIC := '0';
-- IO SIGNAListers
-- common
SIGNAL neg_clk_in : STD_LOGIC := '0';
SIGNAL adatasdata_in_r : STD_LOGIC := '0';
SIGNAL aload_in_r : STD_LOGIC := '0';
-- low_bank = {1, 0} - capturing datain at falling edge then sending at falling rise
-- high_bank = {3, 2} - output of SIGNALister datain at rising
SIGNAL high_bank : STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0');
SIGNAL low_bank : STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0');
SIGNAL low_bank_low : STD_LOGIC := '0';
SIGNAL low_bank_high : STD_LOGIC := '0';
SIGNAL high_bank_low : STD_LOGIC := '0';
SIGNAL high_bank_high: STD_LOGIC := '0';
SIGNAL dataout_reg_n : STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0');
SIGNAL tmp_dataout : STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0');
-- delayed version to ensure 1 latency as expected in functional sim
SIGNAL datain_in : std_logic_vector(1 downto 0) := (OTHERS => '0');
-- timing inputs
SIGNAL datain_ipd : std_logic_vector(1 downto 0) := (OTHERS => '0');
SIGNAL directin_in : std_logic := '0';
SIGNAL clk_in : std_logic := '0';
SIGNAL areset_in : std_logic := '0';
SIGNAL dataoutbypass_in: std_logic := '0';
BEGIN
-- primary input
datain_in <= transport datain_ipd after 2 ps;
-- primary output
dataout <= tmp_dataout;
tmp_dataout(3) <= directin_in WHEN (dataoutbypass_in = '0' AND use_dataoutbypass = "true") ELSE high_bank_high;
tmp_dataout(2) <= directin_in WHEN (dataoutbypass_in = '0' AND use_dataoutbypass = "true") ELSE high_bank_low;
tmp_dataout(1) <= low_bank(1);
tmp_dataout(0) <= low_bank(0);
low_bank <= low_bank_high & low_bank_low;
high_bank <= high_bank_high & high_bank_low;
-- resolve reset modes
PROCESS(areset_in)
BEGIN
if (async_mode = "clear") then
aload_in_r <= areset_in;
adatasdata_in_r <= '0';
elsif (async_mode = "preset") then
aload_in_r <= areset_in;
adatasdata_in_r <= '1';
else -- async_mode = "none"
adatasdata_in_r <= 'Z';
end if;
END PROCESS;
neg_clk_in <= not clk_in;
-- datain_1 - H
reg1_h : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_in(1),
clk => clk_in,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => high_bank_high
);
-- datain_0 - H
reg0_h : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_in(0),
clk => clk_in,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => high_bank_low
);
-- datain_1 - L (n)
reg1_l_n : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_in(1),
clk => neg_clk_in,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => dataout_reg_n(1)
);
-- datain_1 - L
reg1_l : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => dataout_reg_n(1),
clk => clk_in,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => low_bank_high
);
-- datain_0 - L (n)
reg0_l_n : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_in(0),
clk => neg_clk_in,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => dataout_reg_n(0)
);
-- datain_0 - L
reg0_l : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => dataout_reg_n(0),
clk => clk_in,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => low_bank_low
);
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
loopbits_datain : FOR i in datain'RANGE GENERATE
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
END GENERATE;
VitalWireDelay (directin_in, directin, tipd_directin);
VitalWireDelay (clk_in, clk, tipd_clk);
VitalWireDelay (areset_in, areset, tipd_areset);
VitalWireDelay (dataoutbypass_in, dataoutbypass, tipd_dataoutbypass);
end block;
END stratixiii_half_rate_input_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : stratixiii_io_config
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_io_config IS
GENERIC (
enhanced_mode : string := "false";
lpm_type : string := "stratixiii_io_config";
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_update : VitalDelayType01 := DefpropDelay01;
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
update : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
-- new STRATIXIV: ww30.2008
dutycycledelaymode : OUT std_logic;
dutycycledelaysettings : OUT std_logic_vector(3 downto 0);
outputfinedelaysetting1 : OUT std_logic;
outputfinedelaysetting2 : OUT std_logic;
outputonlydelaysetting2 : OUT std_logic_vector(2 downto 0);
outputonlyfinedelaysetting2 : OUT std_logic;
padtoinputregisterfinedelaysetting : OUT std_logic;
padtoinputregisterdelaysetting : OUT std_logic_vector(3 downto 0);
outputdelaysetting1 : OUT std_logic_vector(3 downto 0);
outputdelaysetting2 : OUT std_logic_vector(2 downto 0);
dataout : OUT std_logic
);
END;
ARCHITECTURE stratixiii_io_config_arch OF stratixiii_io_config IS
-- component section
SIGNAL shift_reg : std_logic_vector(10 downto 0) := (OTHERS => '0');
SIGNAL output_reg : std_logic_vector(10 downto 0) := (OTHERS => '0');
SIGNAL tmp_output : std_logic_vector(10 downto 0) := (OTHERS => '0');
SIGNAL enhance_shift_reg : std_logic_vector(22 downto 0) := (OTHERS => '0');
SIGNAL enhance_output_reg : std_logic_vector(22 downto 0) := (OTHERS => '0');
SIGNAL enhance_tmp_output : std_logic_vector(22 downto 0) := (OTHERS => '0');
-- timing outputs
SIGNAL tmp_dataout : std_logic := '0';
-- timing inputs
SIGNAL datain_in : std_logic := '0';
SIGNAL clk_in : std_logic := '0';
SIGNAL ena_in : std_logic := '0';
SIGNAL update_in : std_logic := '0';
BEGIN
-- primary outputs
tmp_dataout <= enhance_shift_reg(22) WHEN (enhanced_mode = "true") ELSE shift_reg(10);
-- bit order changed in wys revision 1.32
outputdelaysetting1 <= tmp_output(3 DOWNTO 0);
outputdelaysetting2 <= tmp_output(6 DOWNTO 4);
padtoinputregisterdelaysetting <= tmp_output(10 DOWNTO 7);
-- padtoinputregisterdelaysetting <= tmp_output(3 DOWNTO 0);
-- outputdelaysetting1 <= tmp_output(7 DOWNTO 4);
-- outputdelaysetting2 <= tmp_output(10 DOWNTO 8);
tmp_output <= output_reg;
outputdelaysetting1 <= enhance_tmp_output(3 DOWNTO 0) WHEN (enhanced_mode = "true") ELSE tmp_output(3 DOWNTO 0);
outputdelaysetting2 <= enhance_tmp_output(6 DOWNTO 4) WHEN (enhanced_mode = "true") ELSE tmp_output(6 DOWNTO 4);
padtoinputregisterdelaysetting <= enhance_tmp_output(10 DOWNTO 7) WHEN (enhanced_mode = "true") ELSE tmp_output(10 DOWNTO 7);
outputfinedelaysetting1 <= enhance_tmp_output(11) WHEN (enhanced_mode = "true") ELSE '0';
outputfinedelaysetting2 <= enhance_tmp_output(12) WHEN (enhanced_mode = "true") ELSE '0';
padtoinputregisterfinedelaysetting <= enhance_tmp_output(13) WHEN (enhanced_mode = "true") ELSE '0';
outputonlyfinedelaysetting2 <= enhance_tmp_output(14) WHEN (enhanced_mode = "true") ELSE '0';
outputonlydelaysetting2 <= enhance_tmp_output(17 DOWNTO 15) WHEN (enhanced_mode = "true") ELSE "000";
dutycycledelaymode <= enhance_tmp_output(18) WHEN (enhanced_mode = "true") ELSE '0';
dutycycledelaysettings <= enhance_tmp_output(22 DOWNTO 19) WHEN (enhanced_mode = "true") ELSE "0000";
tmp_output <= output_reg;
enhance_tmp_output <= enhance_output_reg;
PROCESS(clk_in)
BEGIN
if (clk_in = '1' AND ena_in = '1') then
shift_reg(0) <= datain_in;
shift_reg(10 DOWNTO 1) <= shift_reg(9 DOWNTO 0);
enhance_shift_reg(0) <= datain_in;
enhance_shift_reg(22 DOWNTO 1) <= enhance_shift_reg(21 DOWNTO 0);
end if;
END PROCESS;
PROCESS(clk_in)
BEGIN
if (clk_in = '1' AND update_in = '1') then
output_reg <= shift_reg;
enhance_output_reg <= enhance_shift_reg;
end if;
END PROCESS;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (datain_in, datain, tipd_datain);
VitalWireDelay (clk_in, clk, tipd_clk);
VitalWireDelay (ena_in, ena, tipd_ena);
VitalWireDelay (update_in, update, tipd_update);
end block;
-----------------------------------
-- Timing Check Section
-----------------------------------
VITAL_timing_check: PROCESS (clk_in,datain_in,ena_in,update_in)
variable Tviol_clk_datain : std_ulogic := '0';
variable TimingData_clk_datain : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_clk_ena : std_ulogic := '0';
variable TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_clk_update : std_ulogic := '0';
variable TimingData_clk_update : VitalTimingDataType := VitalTimingDataInit;
BEGIN
IF (TimingChecksOn) THEN
VitalSetupHoldCheck (
Violation => Tviol_clk_datain,
TimingData => TimingData_clk_datain,
TestSignal => datain_in,
TestSignalName => "Datain",
RefSignal => clk_in,
RefSignalName => "clk",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXIII_IO_CONFIG",
XOn => XOnChecks,
MsgOn => MsgOnChecks
);
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_ena,
TestSignal => ena_in,
TestSignalName => "Ena",
RefSignal => clk_in,
RefSignalName => "clk",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXIII_IO_CONFIG",
XOn => XOnChecks,
MsgOn => MsgOnChecks
);
VitalSetupHoldCheck (
Violation => Tviol_clk_update,
TimingData => TimingData_clk_update,
TestSignal => update_in,
TestSignalName => "Update",
RefSignal => clk_in,
RefSignalName => "clk",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXIII_IO_CONFIG",
XOn => XOnChecks,
MsgOn => MsgOnChecks
);
END IF;
END PROCESS; -- timing check
--------------------------------------
-- Path Delay Section
--------------------------------------
VITAL_path_delays: PROCESS (tmp_dataout)
variable dataout_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "Dataout",
OutTemp => tmp_dataout,
Paths => (0 => (clk_in'last_event, tpd_clk_dataout_posedge, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
END PROCESS; -- Path Delays
END stratixiii_io_config_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : stratixiii_dqs_config
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_dqs_config IS
GENERIC (
enhanced_mode : string := "false";
lpm_type : string := "stratixiii_dqs_config";
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_update : VitalDelayType01 := DefpropDelay01;
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
ena : IN std_logic := '0';
update : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsbusoutfinedelaysetting : OUT std_logic; -- new in STRATIXIV
dqsenablefinedelaysetting : OUT std_logic; -- new in STRATIXIV
dqsbusoutdelaysetting : OUT std_logic_vector(3 downto 0);
dqsinputphasesetting : OUT std_logic_vector(2 downto 0);
dqsenablectrlphasesetting : OUT std_logic_vector(3 downto 0);
dqsoutputphasesetting : OUT std_logic_vector(3 downto 0);
dqoutputphasesetting : OUT std_logic_vector(3 downto 0);
resyncinputphasesetting : OUT std_logic_vector(3 downto 0);
dividerphasesetting : OUT std_logic;
enaoctcycledelaysetting : OUT std_logic;
enainputcycledelaysetting : OUT std_logic;
enaoutputcycledelaysetting: OUT std_logic;
dqsenabledelaysetting : OUT std_logic_vector(2 downto 0);
octdelaysetting1 : OUT std_logic_vector(3 downto 0);
octdelaysetting2 : OUT std_logic_vector(2 downto 0);
enadataoutbypass : OUT std_logic;
enadqsenablephasetransferreg : OUT std_logic;
enaoctphasetransferreg : OUT std_logic;
enaoutputphasetransferreg : OUT std_logic;
enainputphasetransferreg : OUT std_logic;
resyncinputphaseinvert : OUT std_logic;
dqsenablectrlphaseinvert : OUT std_logic;
dqoutputphaseinvert : OUT std_logic;
dqsoutputphaseinvert : OUT std_logic;
dataout : OUT std_logic
);
END;
ARCHITECTURE stratixiii_dqs_config_arch OF stratixiii_dqs_config IS
-- component section
SIGNAL shift_reg : STD_LOGIC_VECTOR (47 DOWNTO 0) := (OTHERS => '0');
SIGNAL output_reg : STD_LOGIC_VECTOR (47 DOWNTO 0) := (OTHERS => '0');
SIGNAL tmp_output : STD_LOGIC_VECTOR (47 DOWNTO 0) := (OTHERS => '0');
-- timing outputs
SIGNAL tmp_dataout : std_logic := '0';
-- timing inputs
SIGNAL datain_in : std_logic := '0';
SIGNAL clk_in : std_logic := '0';
SIGNAL ena_in : std_logic := '0';
SIGNAL update_in : std_logic := '0';
BEGIN
-- primary outputs
tmp_dataout <= shift_reg(47) WHEN (enhanced_mode = "true")ELSE shift_reg(45);
dqsbusoutdelaysetting <= tmp_output(3 DOWNTO 0);
dqsinputphasesetting <= tmp_output(6 DOWNTO 4);
dqsenablectrlphasesetting <= tmp_output(10 DOWNTO 7);
dqsoutputphasesetting <= tmp_output(14 DOWNTO 11);
dqoutputphasesetting <= tmp_output(18 DOWNTO 15);
resyncinputphasesetting <= tmp_output(22 DOWNTO 19);
dividerphasesetting <= tmp_output(23);
enaoctcycledelaysetting <= tmp_output(24);
enainputcycledelaysetting <= tmp_output(25);
enaoutputcycledelaysetting<= tmp_output(26);
dqsenabledelaysetting <= tmp_output(29 DOWNTO 27);
octdelaysetting1 <= tmp_output(33 DOWNTO 30);
octdelaysetting2 <= tmp_output(36 DOWNTO 34);
enadataoutbypass <= tmp_output(37);
enadqsenablephasetransferreg <= tmp_output(38); -- new in 1.23
enaoctphasetransferreg <= tmp_output(39); -- new in 1.23
enaoutputphasetransferreg <= tmp_output(40); -- new in 1.23
enainputphasetransferreg <= tmp_output(41); -- new in 1.23
resyncinputphaseinvert <= tmp_output(42); -- new in 1.26
dqsenablectrlphaseinvert <= tmp_output(43); -- new in 1.26
dqoutputphaseinvert <= tmp_output(44); -- new in 1.26
dqsoutputphaseinvert <= tmp_output(45); -- new in 1.26
-- new in STRATIXIV: ww30.2008
dqsbusoutfinedelaysetting <= tmp_output(46) WHEN (enhanced_mode = "true") ELSE '0';
dqsenablefinedelaysetting <= tmp_output(47) WHEN (enhanced_mode = "true") ELSE '0';
tmp_output <= output_reg;
PROCESS(clk_in)
begin
if (clk_in = '1' AND ena_in = '1') then
shift_reg(0) <= datain_in;
shift_reg(47 DOWNTO 1) <= shift_reg(46 DOWNTO 0);
end if;
end process;
PROCESS(clk_in)
begin
if (clk_in = '1' AND update_in = '1') then
output_reg <= shift_reg;
end if;
end process;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (datain_in, datain, tipd_datain);
VitalWireDelay (clk_in, clk, tipd_clk);
VitalWireDelay (ena_in, ena, tipd_ena);
VitalWireDelay (update_in, update, tipd_update);
end block;
-----------------------------------
-- Timing Check Section
-----------------------------------
VITAL_timing_check: PROCESS (clk_in,datain_in,ena_in,update_in)
variable Tviol_clk_datain : std_ulogic := '0';
variable TimingData_clk_datain : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_clk_ena : std_ulogic := '0';
variable TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_clk_update : std_ulogic := '0';
variable TimingData_clk_update : VitalTimingDataType := VitalTimingDataInit;
BEGIN
IF (TimingChecksOn) THEN
VitalSetupHoldCheck (
Violation => Tviol_clk_datain,
TimingData => TimingData_clk_datain,
TestSignal => datain_in,
TestSignalName => "Datain",
RefSignal => clk_in,
RefSignalName => "clk",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXIII_IO_CONFIG",
XOn => XOnChecks,
MsgOn => MsgOnChecks
);
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_ena,
TestSignal => ena_in,
TestSignalName => "Ena",
RefSignal => clk_in,
RefSignalName => "clk",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXIII_IO_CONFIG",
XOn => XOnChecks,
MsgOn => MsgOnChecks
);
VitalSetupHoldCheck (
Violation => Tviol_clk_update,
TimingData => TimingData_clk_update,
TestSignal => update_in,
TestSignalName => "Update",
RefSignal => clk_in,
RefSignalName => "clk",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXIII_IO_CONFIG",
XOn => XOnChecks,
MsgOn => MsgOnChecks
);
END IF;
END PROCESS; -- timing check
--------------------------------------
-- Path Delay Section
--------------------------------------
VITAL_path_delays: PROCESS (tmp_dataout)
variable dataout_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "Dataout",
OutTemp => tmp_dataout,
Paths => (0 => (clk_in'last_event, tpd_clk_dataout_posedge, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
END PROCESS; -- Path Delays
END stratixiii_dqs_config_arch;
-------------------------------------------------------------------------------
-- Module Name: stratixiii_mac_bit_register --
-- Description: Stratix III MAC single bit register --
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_mac_bit_register IS
GENERIC (
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_aclr_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
sload : IN std_logic := '0';
bypass_register : IN std_logic := '0';
dataout : OUT std_logic
);
END stratixiii_mac_bit_register;
ARCHITECTURE arch OF stratixiii_mac_bit_register IS
SIGNAL datain_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL aclr_ipd : std_logic := '0';
SIGNAL sload_ipd : std_logic := '1';
SIGNAL dataout_tmp : std_logic := '0';
SIGNAL dataout_reg : std_logic := '0';
BEGIN
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (sload_ipd, sload, tipd_sload);
end block;
PROCESS(clk_ipd, datain_ipd, sload_ipd, aclr_ipd)
variable Tviol_datain_clk : std_ulogic := '0';
variable Tviol_sload_clk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
VARIABLE CQDelay : TIME := 0 ns;
BEGIN
IF (aclr_ipd = '1') THEN
dataout_reg <= '0';
ELSIF (clk_ipd'EVENT AND clk_ipd = '1') THEN
IF (sload_ipd = '1') THEN
dataout_reg <= datain_ipd;
ELSE
dataout_reg <= dataout_reg;
END IF;
END IF;
VitalSetupHoldCheck (
Violation => Tviol_datain_clk,
TimingData => TimingData_datain_clk,
TestSignal => datain,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT aclr_ipd) OR
(sload_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/MAC Register VitalSetupHoldCheck",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sload_clk,
TimingData => TimingData_sload_clk,
TestSignal => sload_ipd,
TestSignalName => "SLOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sload_clk_noedge_posedge,
SetupLow => tsetup_sload_clk_noedge_posedge,
HoldHigh => thold_sload_clk_noedge_posedge,
HoldLow => thold_sload_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT aclr_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/MAC Register VitalSetupHoldCheck",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
END PROCESS;
dataout_tmp <= datain_ipd WHEN bypass_register = '1' ELSE dataout_reg;
PROCESS(dataout_tmp)
variable dataout_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "dataout",
OutTemp => dataout_tmp,
Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE),
1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
END PROCESS;
END arch;
-------------------------------------------------------------------------------
-- Module Name: stratixiii_mac_register --
-- Description: Stratix III MAC variable width register --
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_mac_register IS
GENERIC (
data_width : integer := 18;
tipd_datain : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_aclr_dataout_posedge : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tpd_clk_dataout_posedge : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tsetup_datain_clk_noedge_posedge : VitalDelayArrayType(71 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_datain_clk_noedge_posedge : VitalDelayArrayType(71 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
datain : IN std_logic_vector(data_width - 1 DOWNTO 0) := (others => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
sload : IN std_logic := '0';
bypass_register : IN std_logic := '0';
dataout : OUT std_logic_vector(data_width - 1 DOWNTO 0)
);
END stratixiii_mac_register;
ARCHITECTURE arch OF stratixiii_mac_register IS
SIGNAL datain_ipd : std_logic_vector(data_width -1 downto 0) := (others => '0');
SIGNAL clk_ipd : std_logic := '0';
SIGNAL aclr_ipd : std_logic := '0';
SIGNAL sload_ipd : std_logic := '1';
SIGNAL dataout_tmp : std_logic_vector(data_width - 1 DOWNTO 0) := (others => '0');
SIGNAL dataout_reg : std_logic_vector(data_width - 1 DOWNTO 0) := (others => '0');
BEGIN
WireDelay : block
begin
g1 :for i in datain'range generate
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
end generate;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (sload_ipd, sload, tipd_sload);
end block;
PROCESS(clk_ipd, datain_ipd, sload_ipd, aclr_ipd)
BEGIN
IF (aclr_ipd = '1') THEN
dataout_reg <= (OTHERS => '0');
ELSIF (clk_ipd'EVENT AND clk_ipd = '1') THEN
IF (sload_ipd = '1') THEN
dataout_reg <= datain_ipd;
ELSE
dataout_reg <= dataout_reg;
END IF;
END IF;
END process;
sh: block
begin
g0 : for i in datain'range generate
process(datain_ipd(i),clk_ipd,sload_ipd)
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(71 downto 0);
variable Tviol_sload_clk : std_ulogic := '0';
variable Tviol_datain_clk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
begin
VitalSetupHoldCheck (
Violation => Tviol_datain_clk,
TimingData => TimingData_datain_clk,
TestSignal => datain_ipd(i),
TestSignalName => "DATAIN(i)",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datain_clk_noedge_posedge(i),
SetupLow => tsetup_datain_clk_noedge_posedge(i),
HoldHigh => thold_datain_clk_noedge_posedge(i),
HoldLow => thold_datain_clk_noedge_posedge(i),
CheckEnabled => TO_X01((NOT aclr_ipd) OR
(sload_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/MAC_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sload_clk,
TimingData => TimingData_sload_clk,
TestSignal => sload_ipd,
TestSignalName => "SLOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sload_clk_noedge_posedge,
SetupLow => tsetup_sload_clk_noedge_posedge,
HoldHigh => thold_sload_clk_noedge_posedge,
HoldLow => thold_sload_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT aclr_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/MAC_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
END PROCESS;
end generate g0;
end block;
dataout_tmp <= datain_ipd WHEN bypass_register = '1' ELSE dataout_reg;
PathDelay : block
begin
g1 : for i in dataout'range generate
PROCESS (dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge(i), TRUE),
1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
end process;
end generate;
end block;
END arch;
-------------------------------------------------------------------------------
-- Module Name: stratixiii_mac_multiplier --
-- Description: Stratix III MAC signed multiplier --
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_mac_multiplier IS
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18;
tipd_dataa : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tipd_signa : VitalDelayType01 := DefPropDelay01;
tipd_signb : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout : VitalDelayArrayType01(18*36-1 downto 0) := (others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(18*36-1 downto 0) := (others => DefPropDelay01);
tpd_signa_dataout : VitalDelayArrayType01(35 downto 0) := (others => DefPropDelay01);
tpd_signb_dataout : VitalDelayArrayType01(35 downto 0) := (others => DefPropDelay01);
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '0');
signa : IN std_logic := '0';
signb : IN std_logic := '0';
dataout : OUT std_logic_vector(dataa_width + datab_width - 1 DOWNTO 0)
);
END stratixiii_mac_multiplier;
ARCHITECTURE arch OF stratixiii_mac_multiplier IS
constant dataout_width : integer := dataa_width + datab_width;
SIGNAL product : std_logic_vector(dataout_width - 1 DOWNTO 0):= (others => '0');
SIGNAL abs_product : std_logic_vector(dataout_width - 1 DOWNTO 0):= (others => '0');
SIGNAL abs_a : std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '0');
SIGNAL abs_b : std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '0');
SIGNAL dataout_tmp : std_logic_vector(dataout_width - 1 DOWNTO 0):= (others => '0');
SIGNAL product_sign : std_logic := '0';
SIGNAL dataa_sign : std_logic := '0';
SIGNAL datab_sign : std_logic := '0';
SIGNAL dataa_ipd : std_logic_vector(dataa_width -1 DOWNTO 0) := (others => '0');
SIGNAL datab_ipd : std_logic_vector(datab_width -1 DOWNTO 0) := (others => '0');
SIGNAL signa_ipd : std_logic := '0';
SIGNAL signb_ipd : std_logic := '0';
BEGIN
WireDelay : block
begin
g1 :for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
end generate;
g2 :for i in datab'range generate
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
end generate;
VitalWireDelay (signa_ipd, signa, tipd_signa);
VitalWireDelay (signb_ipd, signb, tipd_signb);
end block;
dataa_sign <= dataa_ipd(dataa_width - 1) AND signa_ipd ;
datab_sign <= datab_ipd(datab_width - 1) AND signb_ipd ;
product_sign <= dataa_sign XOR datab_sign ;
abs_a <= (NOT dataa_ipd + '1') WHEN dataa_sign = '1' ELSE dataa_ipd;
abs_b <= (NOT datab_ipd + '1') WHEN datab_sign = '1' ELSE datab_ipd;
abs_product <= abs_a * abs_b ;
dataout_tmp <= (NOT abs_product + 1) WHEN product_sign = '1' ELSE abs_product;
PathDelay : block
begin
do : for i in dataout'range generate
process(dataout_tmp(i))
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout(i), TRUE),
1 => (datab_ipd'last_event, tpd_datab_dataout(i), TRUE),
2 => (signa'last_event, tpd_signa_dataout(i), TRUE),
3 => (signb'last_event, tpd_signb_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE
);
end process;
end generate do;
end block;
END arch;
----------------------------------------------------------------------------------
-- Module Name: stratixiii_mac_mult_atom --
-- Description: Simulation model for stratixiii mac mult atom. --
-- This model instantiates the following components. --
-- 1.stratixiii_mac_bit_register. --
-- 2.stratixiii_mac_register. --
-- 3.stratixiii_mac_multiplier. --
----------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_mac_mult IS
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
scanouta_clock : string := "none";
dataa_clear : string := "none";
datab_clear : string := "none";
signa_clear : string := "none";
signb_clear : string := "none";
scanouta_clear : string := "none";
signa_internally_grounded : string := "false";
signb_internally_grounded : string := "false";
lpm_type : string := "stratixiii_mac_mult"
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '1');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '1');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
ena : IN std_logic_vector(3 DOWNTO 0) := (others => '1');
dataout : OUT std_logic_vector(dataa_width + datab_width - 1 DOWNTO 0);
scanouta : OUT std_logic_vector(dataa_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END stratixiii_mac_mult;
ARCHITECTURE arch OF stratixiii_mac_mult IS
constant dataout_width : integer := dataa_width + datab_width;
COMPONENT stratixiii_mac_bit_register
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
sload : IN std_logic := '0';
bypass_register : IN std_logic := '0';
dataout : OUT std_logic
);
END COMPONENT;
COMPONENT stratixiii_mac_register
GENERIC (
data_width : integer := 18
);
PORT (
datain : IN std_logic_vector(data_width - 1 DOWNTO 0) := (others => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
sload : IN std_logic := '0';
bypass_register : IN std_logic := '0';
dataout : OUT std_logic_vector(data_width - 1 DOWNTO 0)
);
END COMPONENT;
COMPONENT stratixiii_mac_multiplier
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '0');
signa : IN std_logic := '0';
signb : IN std_logic := '0';
dataout : OUT std_logic_vector(dataa_width + datab_width - 1 DOWNTO 0)
);
END COMPONENT;
--Internal signals to instantiate the dataa input register unit
SIGNAL dataa_clk_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL dataa_aclr_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL dataa_clk : std_logic := '0';
SIGNAL dataa_aclr : std_logic := '0';
SIGNAL dataa_sload : std_logic := '0';
SIGNAL dataa_bypass_register : std_logic := '0';
SIGNAL dataa_in_reg : std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '0');
SIGNAL dataa_in : std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '0');
--Internal signals to instantiate the datab input register unit
SIGNAL datab_clk_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL datab_aclr_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL datab_clk : std_logic := '0';
SIGNAL datab_aclr : std_logic := '0';
SIGNAL datab_sload : std_logic := '0';
SIGNAL datab_bypass_register : std_logic := '0';
SIGNAL datab_in_reg : std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '0');
SIGNAL datab_in : std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '0');
--Internal signals to instantiate the signa input register unit
SIGNAL signa_clk_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_aclr_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_clk : std_logic := '0';
SIGNAL signa_aclr : std_logic := '0';
SIGNAL signa_sload : std_logic := '0';
SIGNAL signa_bypass_register : std_logic := '0';
SIGNAL signa_in_reg : std_logic := '0';
SIGNAL signa_in : std_logic := '0';
--Internal signbls to instantiate the signb input register unit
SIGNAL signb_clk_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_aclr_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_clk : std_logic := '0';
SIGNAL signb_aclr : std_logic := '0';
SIGNAL signb_sload : std_logic := '0';
SIGNAL signb_bypass_register : std_logic := '0';
SIGNAL signb_in_reg : std_logic := '0';
SIGNAL signb_in : std_logic := '0';
--Internal scanoutals to instantiate the scanouta input register unit
SIGNAL scanouta_clk_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL scanouta_aclr_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL scanouta_clk : std_logic := '0';
SIGNAL scanouta_aclr : std_logic := '0';
SIGNAL scanouta_sload : std_logic := '0';
SIGNAL scanouta_bypass_register : std_logic := '0';
SIGNAL scanouta_tmp : std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '0');
--Internal Signals to instantiate the mac multiplier
SIGNAL signa_mult : std_logic := '0';
SIGNAL signb_mult : std_logic := '0';
SIGNAL dataout_tmp : std_logic_vector(dataout_width - 1 DOWNTO 0):= (others => '0');
BEGIN
--Instantiate the dataa input Register
dataa_clk_value <= "0000" WHEN ((dataa_clock = "0") or (dataa_clock = "none"))
ELSE "0001" WHEN (dataa_clock = "1")
ELSE "0010" WHEN (dataa_clock = "2")
ELSE "0011" WHEN (dataa_clock = "3")
ELSE "0000" ;
dataa_aclr_value <= "0000" WHEN ((dataa_clear = "0") or (dataa_clear = "none"))
ELSE "0001" WHEN (dataa_clear = "1")
ELSE "0010" WHEN (dataa_clear = "2")
ELSE "0011" WHEN (dataa_clear = "3")
ELSE "0000" ;
dataa_clk <= '1' WHEN clk(conv_integer(dataa_clk_value)) = '1' ELSE '0';
dataa_aclr <= '1' WHEN (aclr(conv_integer(dataa_aclr_value)) OR (NOT devclrn) OR (NOT devpor)) = '1' ELSE '0';
dataa_sload <= '1' WHEN ena(conv_integer(dataa_clk_value)) = '1' ELSE '0';
dataa_bypass_register <= '1' WHEN (dataa_clock = "none") ELSE '0';
dataa_in <= dataa;
dataa_input_register : stratixiii_mac_register
GENERIC MAP (
data_width => dataa_width
)
PORT MAP (
datain => dataa_in,
clk => dataa_clk,
aclr => dataa_aclr,
sload => dataa_sload,
bypass_register => dataa_bypass_register,
dataout => dataa_in_reg
);
--Instantiate the datab input Register
datab_clk_value <= "0000" WHEN ((datab_clock = "0") or (datab_clock = "none"))
ELSE "0001" WHEN (datab_clock = "1")
ELSE "0010" WHEN (datab_clock = "2")
ELSE "0011" WHEN (datab_clock = "3")
ELSE "0000" ;
datab_aclr_value <= "0000" WHEN ((datab_clear = "0") or (datab_clear = "none"))
ELSE "0001" WHEN (datab_clear = "1")
ELSE "0010" WHEN (datab_clear = "2")
ELSE "0011" WHEN (datab_clear = "3")
ELSE "0000" ;
datab_clk <= '1' WHEN clk(conv_integer(datab_clk_value)) = '1' ELSE '0';
datab_aclr <= '1' WHEN (aclr(conv_integer(datab_aclr_value)) OR (NOT devclrn) OR (NOT devpor)) = '1' ELSE '0';
datab_sload <= '1' WHEN ena(conv_integer(datab_clk_value)) = '1' ELSE '0';
datab_bypass_register <= '1' WHEN (datab_clock = "none") ELSE '0';
datab_in <= datab;
datab_input_register : stratixiii_mac_register
GENERIC MAP (
data_width => datab_width
)
PORT MAP (
datain => datab_in,
clk => datab_clk,
aclr => datab_aclr,
sload => datab_sload,
bypass_register => datab_bypass_register,
dataout => datab_in_reg
);
--Instantiate the signa input Register
signa_clk_value <= "0000" WHEN ((signa_clock = "0") or (signa_clock = "none"))
ELSE "0001" WHEN (signa_clock = "1")
ELSE "0010" WHEN (signa_clock = "2")
ELSE "0011" WHEN (signa_clock = "3")
ELSE "0000" ;
signa_aclr_value <= "0000" WHEN ((signa_clear = "0") or (signa_clear = "none"))
ELSE "0001" WHEN (signa_clear = "1")
ELSE "0010" WHEN (signa_clear = "2")
ELSE "0011" WHEN (signa_clear = "3")
ELSE "0000" ;
signa_clk <= '1' WHEN clk(conv_integer(signa_clk_value)) = '1' ELSE '0';
signa_aclr <= '1' WHEN (aclr(conv_integer(signa_aclr_value)) OR (NOT devclrn) OR (NOT devpor)) = '1' ELSE '0';
signa_sload <= '1' WHEN ena(conv_integer(signa_clk_value)) = '1' ELSE '0';
signa_bypass_register <= '1' WHEN (signa_clock = "none") ELSE '0';
signa_in <= signa;
signa_input_register : stratixiii_mac_bit_register
PORT MAP (
datain => signa_in,
clk => signa_clk,
aclr => signa_aclr,
sload => signa_sload,
bypass_register => signa_bypass_register,
dataout => signa_in_reg
);
--Instantiate the signb input Register
signb_clk_value <= "0000" WHEN ((signb_clock = "0") or (signb_clock = "none"))
ELSE "0001" WHEN (signb_clock = "1")
ELSE "0010" WHEN (signb_clock = "2")
ELSE "0011" WHEN (signb_clock = "3")
ELSE "0000" ;
signb_aclr_value <= "0000" WHEN ((signb_clear = "0") or (signb_clear = "none"))
ELSE "0001" WHEN (signb_clear = "1")
ELSE "0010" WHEN (signb_clear = "2")
ELSE "0011" WHEN (signb_clear = "3")
ELSE "0000" ;
signb_clk <= '1' WHEN clk(conv_integer(signb_clk_value)) = '1' ELSE '0';
signb_aclr <= '1' WHEN (aclr(conv_integer(signb_aclr_value)) OR (NOT devclrn) OR (NOT devpor)) = '1' ELSE '0';
signb_sload <= '1' WHEN ena(conv_integer(signb_clk_value)) = '1' ELSE '0';
signb_bypass_register <= '1' WHEN (signb_clock = "none") ELSE '0';
signb_in <= signb;
signb_input_register : stratixiii_mac_bit_register
PORT MAP (
datain => signb_in,
clk => signb_clk,
aclr => signb_aclr,
sload => signb_sload,
bypass_register => signb_bypass_register,
dataout => signb_in_reg
);
--Instantiate the scanouta input Register
scanouta_clk_value <= "0000" WHEN ((scanouta_clock = "0") or (scanouta_clock = "none"))
ELSE "0001" WHEN (scanouta_clock = "1")
ELSE "0010" WHEN (scanouta_clock = "2")
ELSE "0011" WHEN (scanouta_clock = "3")
ELSE "0000" ;
scanouta_aclr_value <= "0000" WHEN ((scanouta_clear = "0") or (scanouta_clear = "none"))
ELSE "0001" WHEN (scanouta_clear = "1")
ELSE "0010" WHEN (scanouta_clear = "2")
ELSE "0011" WHEN (scanouta_clear = "3")
ELSE "0000" ;
scanouta_clk <= '1' WHEN clk(conv_integer(scanouta_clk_value)) = '1' ELSE '0';
scanouta_aclr <= '1' WHEN (aclr(conv_integer(scanouta_aclr_value)) OR (NOT devclrn) OR (NOT devpor)) = '1' ELSE '0';
scanouta_sload <= '1' WHEN ena(conv_integer(scanouta_clk_value)) = '1' ELSE '0';
scanouta_bypass_register <= '1' WHEN (scanouta_clock = "none") ELSE '0';
scanouta_input_register : stratixiii_mac_register
GENERIC MAP (
data_width => dataa_width
)
PORT MAP (
datain => dataa_in_reg,
clk => scanouta_clk,
aclr => scanouta_aclr,
sload => scanouta_sload,
bypass_register => scanouta_bypass_register,
dataout => scanouta
);
--Instantiate mac_multiplier block
signa_mult <= '0' WHEN (signa_internally_grounded = "true") ELSE signa_in_reg;
signb_mult <= '0' WHEN (signb_internally_grounded = "true") ELSE signb_in_reg;
mac_multiplier : stratixiii_mac_multiplier
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width
)
PORT MAP (
dataa => dataa_in_reg,
datab => datab_in_reg,
signa => signa_mult,
signb => signb_mult,
dataout => dataout
);
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: stratixiii_fsa_isse --
-- Description: Stratix III first stage adder input selection and sign extension block. --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_fsa_isse IS
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
datac_width : integer := 36;
datad_width : integer := 36;
chainin_width : integer := 44;
multa_signa_internally_grounded : string := "false";
multa_signb_internally_grounded : string := "false";
multb_signa_internally_grounded : string := "false";
multb_signb_internally_grounded : string := "false";
multc_signa_internally_grounded : string := "false";
multc_signb_internally_grounded : string := "false";
multd_signa_internally_grounded : string := "false";
multd_signb_internally_grounded : string := "false";
operation_mode : string := "output_only"
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0);
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0);
datac : IN std_logic_vector(datac_width - 1 DOWNTO 0);
datad : IN std_logic_vector(datad_width - 1 DOWNTO 0);
chainin : IN std_logic_vector(chainin_width - 1 DOWNTO 0);
signa : IN std_logic := '0';
signb : IN std_logic := '0';
dataa_out : OUT std_logic_vector(71 DOWNTO 0);
datab_out : OUT std_logic_vector(71 DOWNTO 0);
datac_out : OUT std_logic_vector(71 DOWNTO 0);
datad_out : OUT std_logic_vector(71 DOWNTO 0);
chainin_out : OUT std_logic_vector(71 DOWNTO 0);
operation : OUT std_logic_vector(3 DOWNTO 0)
);
END stratixiii_fsa_isse;
ARCHITECTURE arch OF stratixiii_fsa_isse IS
signal dataa_out_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
signal datab_out_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
signal datac_out_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
signal datad_out_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
signal chainin_out_tmp: std_logic_vector(71 DOWNTO 0) := (others => '0');
signal sign :std_logic := '0';
BEGIN
operation <= "0000" WHEN (operation_mode = "output_only") ELSE
"0001" WHEN (operation_mode = "one_level_adder") ELSE
"0010" WHEN (operation_mode = "loopback") ELSE
"0011" WHEN (operation_mode = "accumulator") ELSE
"0100" WHEN (operation_mode = "accumulator_chain_out") ELSE
"0101" WHEN (operation_mode = "two_level_adder") ELSE
"0110" WHEN (operation_mode = "two_level_adder_chain_out") ELSE
"0111" WHEN (operation_mode = "36_bit_multiply") ELSE
"1000" WHEN (operation_mode = "shift") ELSE
"1001" WHEN (operation_mode = "double") ELSE "0000";
sign <= signa or signb;
PROCESS( dataa,datab,datac,datad,chainin,signa,signb)
variable active_signb : std_logic := '0';
variable active_signc : std_logic := '0';
variable active_signd : std_logic := '0';
variable read_new_param : std_logic := '0';
variable datab_out_tim_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
variable datac_out_tim_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
variable datad_out_tim_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
variable datab_out_fun_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
variable datac_out_fun_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
variable datad_out_fun_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
BEGIN
IF ( multa_signa_internally_grounded = "false" AND multa_signb_internally_grounded = "false"
AND multb_signa_internally_grounded = "false" AND multb_signb_internally_grounded = "false"
AND multc_signa_internally_grounded = "false" AND multc_signb_internally_grounded = "false"
AND multd_signa_internally_grounded = "false" AND multd_signb_internally_grounded = "false") THEN
read_new_param := '0' ;
ELSE
read_new_param := '1' ;
END IF;
IF ((operation_mode = "36_bit_multiply") or (operation_mode = "shift") or (operation_mode = "double")) THEN
if (multb_signb_internally_grounded = "false" AND multb_signa_internally_grounded = "true") then
active_signb := signb;
elsif(multb_signb_internally_grounded = "true" AND multb_signa_internally_grounded = "false" ) then
active_signb := signa;
elsif(multb_signb_internally_grounded = "false" AND multb_signa_internally_grounded = "false") then
active_signb := sign;
else
active_signb := '0';
end if;
ELSE
active_signb := sign;
END IF;
IF ((operation_mode = "36_bit_multiply") or (operation_mode = "shift") or (operation_mode = "double")) THEN
if (multc_signb_internally_grounded = "false" AND multc_signa_internally_grounded = "true") then
active_signc := signb;
elsif(multc_signb_internally_grounded = "true" AND multc_signa_internally_grounded = "false" ) then
active_signc := signa;
elsif(multc_signb_internally_grounded = "false" AND multc_signa_internally_grounded = "false") then
active_signc := sign;
else
active_signc := '0';
end if;
ELSE
active_signc := sign;
END IF;
IF ((operation_mode = "36_bit_multiply") or (operation_mode = "shift") or (operation_mode = "double")) THEN
if (multd_signb_internally_grounded = "false" AND multd_signa_internally_grounded = "true") then
active_signd := signb;
elsif(multd_signb_internally_grounded = "true" AND multd_signa_internally_grounded = "false" ) then
active_signd := signa;
elsif(multd_signb_internally_grounded = "false" AND multd_signa_internally_grounded = "false") then
active_signd := sign;
else
active_signd := '0';
end if;
ELSE
active_signd := sign;
END IF;
IF (dataa(dataa_width - 1) = '1' AND sign = '1') THEN
dataa_out_tmp <= sxt(dataa(dataa_width - 1 DOWNTO 0), 72);
ELSE
dataa_out_tmp <= ext(dataa(dataa_width - 1 DOWNTO 0), 72);
END IF;
IF (datab(datab_width - 1) = '1' AND active_signb = '1') THEN
datab_out_tim_tmp := sxt(datab(datab_width - 1 DOWNTO 0), 72);
ELSE
datab_out_tim_tmp := ext(datab(datab_width - 1 DOWNTO 0), 72);
END IF;
IF (datac(datac_width - 1) = '1' AND active_signc = '1') THEN
datac_out_tim_tmp := sxt(datac(datac_width - 1 DOWNTO 0), 72);
ELSE
datac_out_tim_tmp := ext(datac(datac_width - 1 DOWNTO 0), 72);
END IF;
IF (datad(datad_width - 1) = '1' AND active_signd = '1') THEN
datad_out_tim_tmp := sxt(datad(datad_width - 1 DOWNTO 0), 72);
ELSE
datad_out_tim_tmp := ext(datad(datad_width - 1 DOWNTO 0), 72);
END IF;
IF ((operation_mode = "36_bit_multiply") or (operation_mode = "shift")) THEN
IF(datab(datab_width - 1) = '1' AND signb = '1') THEN
datab_out_fun_tmp := sxt(datab(datab_width - 1 DOWNTO 0), 72);
ELSE
datab_out_fun_tmp := ext(datab(datab_width - 1 DOWNTO 0), 72);
END IF;
ELSIF(operation_mode = "double") THEN
IF(datab(datab_width - 1) = '1' AND signa = '1') THEN
datab_out_fun_tmp := sxt(datab(datab_width - 1 DOWNTO 0), 72);
ELSE
datab_out_fun_tmp := ext(datab(datab_width - 1 DOWNTO 0), 72);
END IF;
ELSE
IF (datab(datab_width - 1) = '1' AND sign = '1') THEN
datab_out_fun_tmp := sxt(datab(datab_width - 1 DOWNTO 0), 72);
ELSE
datab_out_fun_tmp := ext(datab(datab_width - 1 DOWNTO 0), 72);
END IF;
END IF;
IF ((operation_mode = "36_bit_multiply") or (operation_mode = "shift")) THEN
IF (datac(datac_width - 1) = '1' AND signa = '1') THEN
datac_out_fun_tmp := sxt(datac(datac_width - 1 DOWNTO 0), 72);
ELSE
datac_out_fun_tmp := ext(datac(datac_width - 1 DOWNTO 0), 72);
END IF;
ELSE
IF (datac(datac_width - 1) = '1' AND sign = '1') THEN
datac_out_fun_tmp := sxt(datac(datac_width - 1 DOWNTO 0), 72);
ELSE
datac_out_fun_tmp := ext(datac(datac_width - 1 DOWNTO 0), 72);
END IF;
END IF;
IF ((operation_mode = "36_bit_multiply") or (operation_mode = "shift")) THEN
datad_out_fun_tmp := ext(datad(datad_width - 1 DOWNTO 0), 72);
ELSIF(operation_mode = "double")THEN
IF (datad(datad_width - 1) = '1' AND signa = '1') THEN
datad_out_fun_tmp := sxt(datad(datad_width - 1 DOWNTO 0), 72);
ELSE
datad_out_fun_tmp := ext(datad(datad_width - 1 DOWNTO 0), 72);
END IF;
ELSE
IF (datad(datad_width - 1) = '1' AND sign = '1') THEN
datad_out_fun_tmp := sxt(datad(datad_width - 1 DOWNTO 0), 72);
ELSE
datad_out_fun_tmp := ext(datad(datad_width - 1 DOWNTO 0), 72);
END IF;
END IF;
IF (chainin(chainin_width - 1) = '1') THEN
chainin_out_tmp <= sxt(chainin(chainin_width - 1 DOWNTO 0), 72);
ELSE
chainin_out_tmp <= ext(chainin(chainin_width - 1 DOWNTO 0), 72);
END IF;
IF(read_new_param = '1') THEN
datab_out_tmp <= datab_out_tim_tmp;
datac_out_tmp <= datac_out_tim_tmp;
datad_out_tmp <= datad_out_tim_tmp;
ELSE
datab_out_tmp <= datab_out_fun_tmp;
datac_out_tmp <= datac_out_fun_tmp;
datad_out_tmp <= datad_out_fun_tmp;
END IF;
END process;
dataa_out <= dataa_out_tmp;
datab_out <= datab_out_tmp;
datac_out <= datac_out_tmp;
datad_out <= datad_out_tmp;
chainin_out <= chainin_out_tmp;
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: stratixiii_first_stage_add_sub --
-- Description: Stratix III First Stage Adder Subtractor Unit --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_first_stage_add_sub IS
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
fsa_mode : string := "add";
tipd_dataa : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_sign : VitalDelayType01 :=DefPropDelay01;
tpd_dataa_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_sign_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT (
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
sign : IN std_logic := '0';
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0)
);
END stratixiii_first_stage_add_sub;
ARCHITECTURE arch OF stratixiii_first_stage_add_sub IS
SIGNAL dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL abs_b : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL abs_a : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL sign_a : std_logic := '0';
SIGNAL sign_b : std_logic := '0';
SIGNAL dataa_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datab_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL sign_ipd : std_logic := '0';
BEGIN
WireDelay : block
begin
g1 :for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
end generate;
g2 :for i in datab'range generate
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
end generate;
VitalWireDelay (sign_ipd, sign, tipd_sign);
end block;
PROCESS
BEGIN
WAIT UNTIL dataa_ipd'EVENT OR datab_ipd'EVENT OR sign_ipd'EVENT OR operation'EVENT;
IF ((operation = "0111") OR (operation = "1000")or (operation = "1001")) THEN --36 std_logic multiply, shift and add
dataout_tmp <= dataa_ipd(53 DOWNTO 36) & dataa_ipd(35 DOWNTO 0) & "000000000000000000" + datab_ipd;
ELSE
IF(fsa_mode = "add")THEN
IF (sign_ipd = '1') THEN
dataout_tmp <= signed(dataa_ipd) + signed(datab_ipd);
ELSE
dataout_tmp <= unsigned(dataa_ipd) + unsigned(datab_ipd);
END IF;
ELSE
IF (sign_ipd = '1') THEN
dataout_tmp <= signed(dataa_ipd) - signed(datab_ipd);
ELSE
dataout_tmp <= unsigned(dataa_ipd) - unsigned(datab_ipd);
END IF;
END IF;
END IF;
END process ;
PathDelay : block
begin
do1 : for i in dataout'range generate
process(dataout_tmp(i))
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout(i), TRUE),
1 => (datab_ipd'last_event, tpd_datab_dataout(i), TRUE),
2 => (sign'last_event, tpd_sign_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE
);
end process;
end generate do1;
end block;
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: stratixiii_second_stage_add_accum --
-- Description: Stratix III Second stage Adder and Accumulator/Decimator Unit --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_second_stage_add_accum IS
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
ssa_mode : string := "add";
tipd_dataa : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_accumin : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_sign : VitalDelayType01 :=DefPropDelay01;
tpd_dataa_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_accumin_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_sign_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_dataa_overflow : VitalDelayType01 := DefPropDelay01;
tpd_datab_overflow : VitalDelayType01 := DefPropDelay01;
tpd_accumin_overflow : VitalDelayType01 := DefPropDelay01;
tpd_sign_overflow : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT (
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
accumin : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
sign : IN std_logic := '0';
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
overflow : OUT std_logic
);
END stratixiii_second_stage_add_accum;
ARCHITECTURE arch OF stratixiii_second_stage_add_accum IS
constant accum_width : integer := dataa_width + 7;
SIGNAL dataout_temp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataa_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datab_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL accum_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL overflow_tmp : std_logic := '0';
SIGNAL dataa_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datab_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL accumin_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL sign_ipd : std_logic := '0';
SIGNAL signb_ipd : std_logic := '0';
BEGIN
WireDelay : block
begin
g1 :for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
end generate;
g2 :for i in datab'range generate
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
end generate;
g3 :for i in accumin'range generate
VitalWireDelay (accumin_ipd(i), accumin(i), tipd_accumin(i));
end generate;
VitalWireDelay (sign_ipd, sign, tipd_sign);
end block;
PROCESS
Variable dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
BEGIN
WAIT UNTIL dataa_ipd'EVENT OR datab_ipd'EVENT OR sign_ipd'EVENT OR accumin_ipd'EVENT OR operation'EVENT;
IF (operation = "0011" OR operation = "0100") THEN --Accumultor or Accumulator chainout
IF(ssa_mode = "add")THEN
IF (sign_ipd = '1') THEN
dataout_tmp := signed(sxt(accumin_ipd(accum_width-1 downto 0),72)) + signed(sxt(dataa_ipd(accum_width-1 downto 0),72)) + signed(sxt(datab_ipd(accum_width-1 downto 0),72));
ELSE
dataout_tmp := unsigned(ext(accumin_ipd(accum_width-1 downto 0),72)) + unsigned(ext(dataa_ipd(accum_width-1 downto 0),72)) + unsigned(ext(datab_ipd(accum_width-1 downto 0),72));
END IF;
ELSE
IF (sign_ipd = '1') THEN
dataout_tmp := signed(accumin_ipd) - signed(dataa_ipd)- signed(datab_ipd);
ELSE
dataout_tmp := unsigned(accumin_ipd) - unsigned(dataa_ipd)- unsigned(datab_ipd);
END IF;
END IF;
IF(sign_ipd = '1')THEN
overflow_tmp <= dataout_tmp(accum_width) xor dataout_tmp(accum_width -1);
ELSE
IF(ssa_mode = "add")THEN
overflow_tmp <= dataout_tmp(accum_width);
ELSE
overflow_tmp <= 'X';
END IF;
END IF;
ELSIF (operation = "0101" OR operation = "0110") THEN -- two level adder or two level with chainout
overflow_tmp <= '0';
IF (sign_ipd = '1') THEN
dataout_tmp := signed(dataa_ipd) + signed(datab_ipd);
ELSE
dataout_tmp := unsigned(dataa_ipd) + unsigned(datab_ipd);
END IF;
ELSIF ((operation = "0111") OR (operation = "1000")) THEN --36 std_logic multiply; shift and add
dataout_tmp(71 DOWNTO 0) := dataa_ipd(53 DOWNTO 0) & "000000000000000000" + datab_ipd;
overflow_tmp <= '0';
ELSIF ((operation = "1001")) THEN --double mode
dataout_tmp(71 DOWNTO 0) := dataa_ipd + datab_ipd;
overflow_tmp <= '0';
END IF;
dataout_temp <= dataout_tmp;
END PROCESS;
PathDelay : block
begin
do1 : for i in dataout'range generate
process(dataout_temp(i))
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_temp(i),
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout(i), TRUE),
1 => (datab_ipd'last_event, tpd_datab_dataout(i), TRUE),
2 => (accumin_ipd'last_event, tpd_accumin_dataout(i), TRUE),
3 => (sign'last_event, tpd_sign_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE
);
end process;
end generate do1;
process(overflow_tmp)
VARIABLE overflow_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => overflow,
OutSignalName => "overflow",
OutTemp => overflow_tmp,
paths => (0 => (dataa_ipd'last_event, tpd_dataa_overflow, TRUE),
1 => (datab_ipd'last_event, tpd_datab_overflow, TRUE),
2 => (accumin_ipd'last_event, tpd_accumin_overflow, TRUE),
3 => (sign'last_event, tpd_sign_overflow, TRUE)),
GlitchData => overflow_VitalGlitchData,
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE
);
end process;
end block;
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: stratixiii_round_block --
-- Description: Stratix III round block --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_round_block IS
GENERIC (
round_mode : string := "nearest_integer";
round_width : integer := 15;
operation_mode : string := "output_only"
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
round : IN std_logic := '0';
datain_width : IN std_logic_vector(7 DOWNTO 0):= (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0)
);
END stratixiii_round_block;
ARCHITECTURE arch OF stratixiii_round_block IS
signal out_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
BEGIN
dataout <= out_tmp ;
PROCESS(datain,round,datain_width)
variable i : integer ;
variable j : integer ;
variable sign : std_logic ;
variable result_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
variable dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
variable dataout_value : std_logic_vector(71 DOWNTO 0) := (others => '0');
BEGIN
if(round = '0')then
dataout_value := datain;
else
dataout_value := datain;
j := 0;
sign := '0';
IF( conv_integer(datain_width) > round_width) THEN
for i in ((conv_integer(datain_width)) - round_width) to (conv_integer(datain_width) -1) loop
result_tmp(j) := datain(i);
j := j + 1;
END LOOP;
for i in 0 to (conv_integer(datain_width) - round_width -2) loop
sign := sign or datain(i);
dataout_value(i) := 'X';
END LOOP;
dataout_value((conv_integer(datain_width)) - round_width -1) := 'X';
IF (datain(conv_integer(datain_width) - round_width -1) = '0') THEN -- fractional < 0.5
dataout_tmp := result_tmp;
ELSE
IF ((datain(conv_integer(datain_width) - round_width -1) = '1') AND (sign = '1')) THEN --fractional > 0.5
dataout_tmp := result_tmp + '1';
ELSE
IF (round_mode = "nearest_even") THEN --unbiased rounding
IF(result_tmp(0) = '1') THEN --check for odd integer
dataout_tmp := result_tmp + '1' ;
ELSE
dataout_tmp := result_tmp;
END IF;
ELSE --biased rounding
dataout_tmp := result_tmp + '1';
END IF;
END IF;
END IF;
j := conv_integer(datain_width) - round_width;
FOR i IN 0 to (round_width -1)LOOP
dataout_value(j) := dataout_tmp(i);
j := j + 1;
END LOOP;
ELSE
dataout_value := datain;
END IF;
end if;
out_tmp <= dataout_value;
END PROCESS;
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: stratixiii_saturate_block --
-- Description: Stratix III saturation block --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_saturate_block IS
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
saturate_width : integer := 15;
round_width : integer := 15;
saturate_mode : string := " asymmetric";
operation_mode : string := "output_only"
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
saturate : IN std_logic := '0';
round : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
datain_width : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0):= (others => '0');
saturation_overflow : OUT std_logic
);
END stratixiii_saturate_block;
ARCHITECTURE arch OF stratixiii_saturate_block IS
constant accum_width : integer := dataa_width + 8;
SIGNAL saturation_overflow_tmp : std_logic := '0';
signal msb : std_logic := '0';
signal sign : std_logic := '0';
signal min : std_logic_vector(71 downto 0):=(others => '1');
signal max : std_logic_vector(71 downto 0):=(others => '0');
signal dataout_tmp : std_logic_vector(71 DOWNTO 0):= (others => '0');
SIGNAL i : integer;
BEGIN
sign <= signa OR signb ;
msb <= datain(accum_width) when ((operation_mode = "accumulator") or (operation_mode = "accumulator_chain_out") or(operation_mode = "two_level_adder_chain_out"))
ELSE datain(dataa_width +1) when(operation_mode = "two_level_adder")
ELSE datain(dataa_width) when((operation_mode = "one_level_adder")or (operation_mode = "loopback"))
ELSE datain(dataa_width -1);
dataout <= dataout_tmp ;
saturation_overflow <= saturation_overflow_tmp ;
PROCESS(datain,datain_width,round,saturate,sign,msb)
variable saturation_temp : std_logic := '0';
variable sign_tmp : std_logic := '1';
variable data_tmp : std_logic := '0';
BEGIN
IF (saturate = '0') THEN
dataout_tmp <= datain;
saturation_overflow_tmp <= '0';
ELSE
saturation_temp := '0';
data_tmp := '0';
sign_tmp := '1';
IF (round = '1') THEN
for i in 0 to (conv_integer(datain_width) - round_width -1) LOOP
min(i) <= 'X';
max(i) <= 'X';
END LOOP;
END IF;
IF (saturate_mode = "symmetric") THEN
for i in 0 to (conv_integer(datain_width) - round_width -1) LOOP
min(i) <= 'X';
IF (round = '1') THEN
max(i) <= 'X';
ELSE
max(i) <= '1';
END IF;
END LOOP;
for i in (conv_integer(datain_width) - round_width) to (conv_integer(datain_width) - saturate_width -1) LOOP
data_tmp := data_tmp or datain(i);
max(i) <= '1';
min(i) <= '0';
END LOOP;
min(conv_integer(datain_width) - round_width) <= '1';
END IF;
IF (saturate_mode = "asymmetric") THEN
for i in 0 to (conv_integer(datain_width) - saturate_width -1) LOOP
max(i) <= '1';
min(i) <= '0';
END LOOP;
END IF;
if((saturate_width = 1))then
IF (msb /= datain(conv_integer(datain_width)-1)) THEN
saturation_temp := '1';
ELSE
sign_tmp := sign_tmp and datain(conv_integer(datain_width)-1);
END IF;
else
for i in (conv_integer(datain_width) - saturate_width) to (conv_integer(datain_width)-1) LOOP
sign_tmp := sign_tmp and datain(i);
IF (datain(conv_integer(datain_width)-1) /= datain(i)) THEN
saturation_temp := '1';
end if;
END LOOP;
end if;
-- Trigger the saturation overflow for data=-2^n in case of symmetric saturation.
if((sign_tmp ='1') and (data_tmp = '0') and (saturate_mode = "symmetric")) then
saturation_temp := '1';
end if;
saturation_overflow_tmp <= saturation_temp;
IF (saturation_temp = '1') THEN
IF ((operation_mode = "output_only")or (operation_mode = "accumulator_chain_out") or(operation_mode = "two_level_adder_chain_out")) THEN
IF (msb = '1') THEN
dataout_tmp <= min;
ELSE
dataout_tmp <= max;
END IF;
ELSE
IF (sign = '1') THEN
IF (msb = '1') THEN
dataout_tmp <= min;
ELSE
dataout_tmp <= max;
END IF;
ELSE
dataout_tmp <= (others => 'X');
END IF;
END IF;
ELSE
dataout_tmp <= datain;
END IF;
END IF;
END PROCESS;
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: stratixiii_round_saturate_block --
-- Description: Stratix III round and saturation Unit. --
-- This unit instantiated the following components. --
-- 1.stratixiii_round_block. --
-- 2.stratixiii_saturate_block. --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_round_saturate_block IS
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
saturate_width : integer := 15;
round_width : integer := 15;
saturate_mode : string := " asymmetric";
round_mode : string := "nearest_integer";
operation_mode : string := "output_only" ;
tipd_datain : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_round : VitalDelayType01 :=DefPropDelay01;
tipd_saturate : VitalDelayType01 :=DefPropDelay01;
tipd_signa : VitalDelayType01 :=DefPropDelay01;
tipd_signb : VitalDelayType01 :=DefPropDelay01;
tpd_datain_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_round_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_saturate_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_signa_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_signb_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_datain_saturationoverflow : VitalDelayType01 := DefPropDelay01;
tpd_round_saturationoverflow : VitalDelayType01 := DefPropDelay01;
tpd_saturate_saturationoverflow : VitalDelayType01 := DefPropDelay01;
tpd_signa_saturationoverflow : VitalDelayType01 := DefPropDelay01;
tpd_signb_saturationoverflow : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
round : IN std_logic := '0';
saturate : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
datain_width : IN std_logic_vector(7 DOWNTO 0);
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
saturationoverflow : OUT std_logic
);
END stratixiii_round_saturate_block;
ARCHITECTURE arch OF stratixiii_round_saturate_block IS
COMPONENT stratixiii_round_block
GENERIC (
round_mode : string := "nearest_integer";
round_width : integer := 15;
operation_mode : string := "output_only"
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
round : IN std_logic := '0';
datain_width : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0)
);
END COMPONENT;
COMPONENT stratixiii_saturate_block
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
saturate_mode : string := " asymmetric";
saturate_width : integer := 15;
round_width : integer := 15;
operation_mode : string := "output_only"
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
saturate : IN std_logic := '0';
round : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
datain_width : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
saturation_overflow : OUT std_logic
);
END COMPONENT;
SIGNAL dataout_round : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL saturate_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_saturate : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datain_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL signa_ipd : std_logic := '0';
SIGNAL signb_ipd : std_logic := '0';
SIGNAL round_ipd : std_logic := '0';
SIGNAL saturate_ipd : std_logic := '0';
SIGNAL saturationoverflow_tmp : std_logic := '0';
BEGIN
WireDelay : block
begin
g1 :for i in datain'range generate
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
end generate;
VitalWireDelay (signa_ipd, signa, tipd_signa);
VitalWireDelay (signb_ipd, signb, tipd_signb);
VitalWireDelay (round_ipd, round, tipd_round);
VitalWireDelay (saturate_ipd, saturate, tipd_saturate);
end block;
round_unit : stratixiii_round_block
GENERIC MAP (
operation_mode => operation_mode,
round_width => round_width,
round_mode => round_mode
)
PORT MAP (
datain => datain_ipd,
round => round_ipd,
datain_width => datain_width,
dataout => dataout_round
);
saturate_unit : stratixiii_saturate_block
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width,
operation_mode => operation_mode,
saturate_mode => saturate_mode,
saturate_width =>saturate_width,
round_width =>round_width
)
PORT MAP (
datain => dataout_round,
saturate => saturate_ipd,
round => round_ipd,
signa => signa_ipd,
signb => signb_ipd,
datain_width => datain_width,
dataout => dataout_saturate,
saturation_overflow => saturationoverflow_tmp
);
PathDelay : block
begin
do1 : for i in dataout'range generate
process(dataout_saturate(i))
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_saturate(i),
Paths => (0 => (datain_ipd'last_event, tpd_datain_dataout(i), TRUE),
1 => (round_ipd'last_event, tpd_round_dataout(i), TRUE),
2 => (saturate_ipd'last_event, tpd_saturate_dataout(i), TRUE),
3 => (signa'last_event, tpd_signa_dataout(i), TRUE),
4 => (signb'last_event, tpd_signb_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE
);
end process;
end generate do1;
process(saturationoverflow_tmp)
VARIABLE saturationoverflow_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => saturationoverflow,
OutSignalName => "saturationoverflow",
OutTemp => saturationoverflow_tmp,
Paths => (0 => (datain_ipd'last_event, tpd_datain_saturationoverflow, TRUE),
1 => (round_ipd'last_event, tpd_round_saturationoverflow, TRUE),
2 => (saturate_ipd'last_event, tpd_saturate_saturationoverflow, TRUE),
3 => (signa'last_event, tpd_signa_saturationoverflow, TRUE),
4 => (signb'last_event, tpd_signb_saturationoverflow, TRUE)),
GlitchData => saturationoverflow_VitalGlitchData,
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE
);
end process;
end block;
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: stratixiii_rotate_shift_block --
-- Description: Stratix III roate and shift Unit. --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_rotate_shift_block IS
GENERIC (
dataa_width : integer := 32;
datab_width : integer := 32;
tipd_datain : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_rotate : VitalDelayType01 :=DefPropDelay01;
tipd_shiftright : VitalDelayType01 :=DefPropDelay01;
tipd_signa : VitalDelayType01 :=DefPropDelay01;
tipd_signb : VitalDelayType01 :=DefPropDelay01;
tpd_datain_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_rotate_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_shiftright_dataout: VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_signa_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
rotate : IN std_logic := '0';
shiftright : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
dataout : OUT std_logic_vector(71 DOWNTO 0)
);
END stratixiii_rotate_shift_block;
ARCHITECTURE arch OF stratixiii_rotate_shift_block IS
signal dataout_tmp : std_logic_vector(71 downto 0) := (others => '0');
SIGNAL datain_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL signa_ipd : std_logic := '0';
SIGNAL signb_ipd : std_logic := '0';
SIGNAL rotate_ipd : std_logic := '0';
SIGNAL shiftright_ipd : std_logic := '0';
SIGNAL sign : std_logic;
BEGIN
WireDelay : block
begin
g1 :for i in datain'range generate
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
end generate;
VitalWireDelay (signa_ipd, signa, tipd_signa);
VitalWireDelay (signb_ipd, signa, tipd_signa);
VitalWireDelay (rotate_ipd, rotate, tipd_rotate);
VitalWireDelay (shiftright_ipd, shiftright, tipd_shiftright);
end block;
PROCESS
BEGIN
WAIT UNTIL datain_ipd'EVENT OR rotate_ipd'EVENT OR shiftright_ipd'EVENT;
sign <= signa_ipd xor signb_ipd;
dataout_tmp <= datain;
IF ((rotate_ipd = '0') AND (shiftright_ipd = '0')) THEN
dataout_tmp(39 downto 8) <= datain_ipd(39 downto 8);
ELSIF ((rotate_ipd = '0') AND (shiftright_ipd = '1')) THEN --shift right
dataout_tmp(39 downto 8) <= datain_ipd(71 downto 40);
ELSIF((rotate_ipd = '1') AND (shiftright_ipd = '0')) THEN
dataout_tmp(39 downto 8) <= datain_ipd(39 downto 8) OR datain_ipd(71 downto 40);
ELSE
dataout_tmp <= datain_ipd;
END IF;
END PROCESS;
PathDelay : block
begin
do1 : for i in dataout'range generate
process(dataout_tmp(i))
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (datain_ipd'last_event, tpd_datain_dataout(i), TRUE),
1 => (rotate_ipd'last_event, tpd_rotate_dataout(i), TRUE),
2 => (shiftright_ipd'last_event, tpd_shiftright_dataout(i), TRUE),
3 => (signa'last_event, tpd_signa_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE
);
end process;
end generate do1;
end block;
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: stratixiii_carry_chain_adder --
-- Description: Stratix III carry Chain Adder --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_carry_chain_adder IS
GENERIC(
tipd_dataa : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tpd_dataa_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT (
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
dataout : OUT STD_LOGIC_vector(71 DOWNTO 0)
);
END stratixiii_carry_chain_adder;
ARCHITECTURE arch OF stratixiii_carry_chain_adder IS
SIGNAL dataa_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datab_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
BEGIN
WireDelay : block
begin
g1 :for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
end generate;
g2 :for i in datab'range generate
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
end generate;
end block;
dataout_tmp <= (dataa_ipd(71 downto 45) & dataa_ipd(43) & dataa_ipd(43 downto 0)) + (datab_ipd(71 downto 45) & datab_ipd(43) & datab_ipd(43 downto 0)) ;
PathDelay : block
begin
do1 : for i in dataout'range generate
process(dataout_tmp(i))
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout(i), TRUE),
1 => (datab_ipd'last_event, tpd_datab_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE
);
end process;
end generate do1;
end block;
END arch;
----------------------------------------------------------------------------------
-- Module Name: stratixiii_mac_out_atom --
-- Description: Simulation model for stratixiii mac out atom --
-- This model instantiates the following components --
-- 1.stratixiii_mac_bit_register --
-- 2.stratixiii_mac_register --
-- 3.stratixiii_fsa_isse --
-- 4.stratixiii_first_stage_add_sub --
-- 5.stratixiii_second_stage_add_accum --
-- 6.stratixiii_round_saturate_block --
-- 7.stratixiii_rotate_shift_block --
-- 8.stratixiii_carry_chain_adder --
----------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
ENTITY stratixiii_mac_out IS
GENERIC (
operation_mode : string := "output_only";
dataa_width : integer := 1;
datab_width : integer := 1;
datac_width : integer := 1;
datad_width : integer := 1;
chainin_width : integer := 1;
round_width : integer := 15;
round_chain_out_width : integer := 15;
saturate_width : integer := 15;
saturate_chain_out_width : integer := 15;
first_adder0_clock : string := "none";
first_adder0_clear : string := "none";
first_adder1_clock : string := "none";
first_adder1_clear : string := "none";
second_adder_clock : string := "none";
second_adder_clear : string := "none";
output_clock : string := "none";
output_clear : string := "none";
signa_clock : string := "none";
signa_clear : string := "none";
signb_clock : string := "none";
signb_clear : string := "none";
round_clock : string := "none";
round_clear : string := "none";
roundchainout_clock : string := "none";
roundchainout_clear : string := "none";
saturate_clock : string := "none";
saturate_clear : string := "none";
saturatechainout_clock : string := "none";
saturatechainout_clear : string := "none";
zeroacc_clock : string := "none";
zeroacc_clear : string := "none";
zeroloopback_clock : string := "none";
zeroloopback_clear : string := "none";
rotate_clock : string := "none";
rotate_clear : string := "none";
shiftright_clock : string := "none";
shiftright_clear : string := "none";
signa_pipeline_clock : string := "none";
signa_pipeline_clear : string := "none";
signb_pipeline_clock : string := "none";
signb_pipeline_clear : string := "none";
round_pipeline_clock : string := "none";
round_pipeline_clear : string := "none";
roundchainout_pipeline_clock : string := "none";
roundchainout_pipeline_clear : string := "none";
saturate_pipeline_clock : string := "none";
saturate_pipeline_clear : string := "none";
saturatechainout_pipeline_clock: string := "none";
saturatechainout_pipeline_clear: string := "none";
zeroacc_pipeline_clock : string := "none";
zeroacc_pipeline_clear : string := "none";
zeroloopback_pipeline_clock : string := "none";
zeroloopback_pipeline_clear : string := "none";
rotate_pipeline_clock : string := "none";
rotate_pipeline_clear : string := "none";
shiftright_pipeline_clock : string := "none";
shiftright_pipeline_clear : string := "none";
roundchainout_output_clock : string := "none";
roundchainout_output_clear : string := "none";
saturatechainout_output_clock : string := "none";
saturatechainout_output_clear : string := "none";
zerochainout_output_clock : string := "none";
zerochainout_output_clear : string := "none";
zeroloopback_output_clock : string := "none";
zeroloopback_output_clear : string := "none";
rotate_output_clock : string := "none";
rotate_output_clear : string := "none";
shiftright_output_clock : string := "none";
shiftright_output_clear : string := "none";
first_adder0_mode : string := "add";
first_adder1_mode : string := "add";
acc_adder_operation : string := "add";
round_mode : string := "nearest_integer";
round_chain_out_mode : string := "nearest_integer";
saturate_mode : string := "asymmetric";
saturate_chain_out_mode : string := "asymmetric";
multa_signa_internally_grounded : string := "false";
multa_signb_internally_grounded : string := "false";
multb_signa_internally_grounded : string := "false";
multb_signb_internally_grounded : string := "false";
multc_signa_internally_grounded : string := "false";
multc_signb_internally_grounded : string := "false";
multd_signa_internally_grounded : string := "false";
multd_signb_internally_grounded : string := "false";
lpm_type : string := "stratixiii_mac_out";
dataout_width : integer:=72
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '1');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '1');
datac : IN std_logic_vector(datac_width - 1 DOWNTO 0):= (others => '1');
datad : IN std_logic_vector(datad_width - 1 DOWNTO 0):= (others => '1');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
chainin : IN std_logic_vector(chainin_width - 1 DOWNTO 0):= (others => '0');
round : IN std_logic := '0';
saturate : IN std_logic := '0';
zeroacc : IN std_logic := '0';
roundchainout : IN std_logic := '0';
saturatechainout : IN std_logic := '0';
zerochainout : IN std_logic := '0';
zeroloopback : IN std_logic := '0';
rotate : IN std_logic := '0';
shiftright : IN std_logic := '0';
clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
ena : IN std_logic_vector(3 DOWNTO 0) := (others => '1');
aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
loopbackout : OUT std_logic_vector(17 DOWNTO 0):= (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
overflow : OUT std_logic := '0';
saturatechainoutoverflow: OUT std_logic := '0';
dftout : OUT std_logic := '0';
devpor : IN std_logic := '1';
devclrn : IN std_logic := '1'
);
END stratixiii_mac_out;
ARCHITECTURE arch OF stratixiii_mac_out IS
COMPONENT stratixiii_mac_bit_register
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
sload : IN std_logic := '0';
bypass_register : IN std_logic := '0';
dataout : OUT std_logic
);
END COMPONENT;
COMPONENT stratixiii_mac_register
GENERIC (
data_width : integer := 18
);
PORT (
datain : IN std_logic_vector(data_width - 1 DOWNTO 0) := (others => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
sload : IN std_logic := '0';
bypass_register : IN std_logic := '0';
dataout : OUT std_logic_vector(data_width - 1 DOWNTO 0)
);
END COMPONENT;
COMPONENT stratixiii_fsa_isse
GENERIC (
datab_width : integer := 36;
dataa_width : integer := 36;
chainin_width : integer := 44;
operation_mode : string := "output_only";
datad_width : integer := 36;
multa_signa_internally_grounded : string := "false";
multa_signb_internally_grounded : string := "false";
multb_signa_internally_grounded : string := "false";
multb_signb_internally_grounded : string := "false";
multc_signa_internally_grounded : string := "false";
multc_signb_internally_grounded : string := "false";
multd_signa_internally_grounded : string := "false";
multd_signb_internally_grounded : string := "false";
datac_width : integer := 36
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '0');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '0');
datac : IN std_logic_vector(datac_width - 1 DOWNTO 0):= (others => '0');
datad : IN std_logic_vector(datad_width - 1 DOWNTO 0):= (others => '0');
chainin : IN std_logic_vector(chainin_width - 1 DOWNTO 0):= (others => '0');
signa : IN std_logic := '0';
signb : IN std_logic := '0';
dataa_out : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
datab_out : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
datac_out : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
datad_out : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
chainin_out : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
operation : OUT std_logic_vector(3 DOWNTO 0)
);
END COMPONENT;
COMPONENT stratixiii_first_stage_add_sub
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
fsa_mode : string := "add"
);
PORT (
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
sign : IN std_logic := '0';
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0)
);
END COMPONENT;
COMPONENT stratixiii_second_stage_add_accum
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
ssa_mode : string := "add"
);
PORT (
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
accumin : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
sign : IN std_logic := '0';
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
overflow : OUT std_logic
);
END COMPONENT;
COMPONENT stratixiii_round_saturate_block
GENERIC (
datab_width : integer := 36;
dataa_width : integer := 36;
saturate_mode : string := " asymmetric";
saturate_width : integer := 15;
round_width : integer := 15;
operation_mode : string := "output_only";
round_mode : string := "nearest_integer"
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
round : IN std_logic := '0';
saturate : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
datain_width : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
saturationoverflow : OUT std_logic
);
END COMPONENT;
COMPONENT stratixiii_rotate_shift_block
GENERIC (
datab_width : integer := 32;
dataa_width : integer := 32
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
rotate : IN std_logic := '0';
shiftright : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
dataout : OUT std_logic_vector(71 DOWNTO 0)
);
END COMPONENT;
COMPONENT stratixiii_carry_chain_adder
PORT (
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0)
);
END COMPONENT;
--signals for zeroloopback input register
SIGNAL zeroloopback_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroloopback_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroloopback_clk_ir : std_logic := '0';
SIGNAL zeroloopback_aclr_ir : std_logic := '0';
SIGNAL zeroloopback_sload_ir : std_logic := '0';
SIGNAL zeroloopback_bypass_register_ir : std_logic := '0';
SIGNAL zeroloopback_in_reg : std_logic := '0';
SIGNAL zeroloopback_in : std_logic := '0';
--signals for zeroacc input register
SIGNAL zeroacc_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc_clk_ir : std_logic := '0';
SIGNAL zeroacc_aclr_ir : std_logic := '0';
SIGNAL zeroacc_sload_ir : std_logic := '0';
SIGNAL zeroacc_bypass_register_ir : std_logic := '0';
SIGNAL zeroacc_in_reg : std_logic := '0';
SIGNAL zeroacc_in : std_logic := '0';
--Signals for signa input register
SIGNAL signa_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_clk_ir : std_logic := '0';
SIGNAL signa_aclr_ir : std_logic := '0';
SIGNAL signa_sload_ir : std_logic := '0';
SIGNAL signa_bypass_register_ir : std_logic := '0';
SIGNAL signa_in_reg : std_logic := '0';
SIGNAL signa_in : std_logic := '0';
--signals for signb input register
SIGNAL signb_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_clk_ir : std_logic := '0';
SIGNAL signb_aclr_ir : std_logic := '0';
SIGNAL signb_sload_ir : std_logic := '0';
SIGNAL signb_bypass_register_ir : std_logic := '0';
SIGNAL signb_in_reg : std_logic := '0';
SIGNAL signb_in : std_logic := '0';
--signals for rotate input register
SIGNAL rotate_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rotate_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rotate_clk_ir : std_logic := '0';
SIGNAL rotate_aclr_ir : std_logic := '0';
SIGNAL rotate_sload_ir : std_logic := '0';
SIGNAL rotate_bypass_register_ir: std_logic := '0';
SIGNAL rotate_in_reg : std_logic := '0';
SIGNAL rotate_in : std_logic := '0';
--signals for shiftright input register
SIGNAL shiftright_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL shiftright_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL shiftright_clk_ir : std_logic := '0';
SIGNAL shiftright_aclr_ir : std_logic := '0';
SIGNAL shiftright_sload_ir : std_logic := '0';
SIGNAL shiftright_bypass_register_ir : std_logic := '0';
SIGNAL shiftright_in_reg : std_logic := '0';
SIGNAL shiftright_in : std_logic := '0';
--signals for round input register
SIGNAL round_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round_clk_ir : std_logic := '0';
SIGNAL round_aclr_ir : std_logic := '0';
SIGNAL round_sload_ir : std_logic := '0';
SIGNAL round_bypass_register_ir : std_logic := '0';
SIGNAL round_in_reg : std_logic := '0';
SIGNAL round_in : std_logic := '0';
--signals for saturate input register
SIGNAL saturate_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate_clk_ir : std_logic := '0';
SIGNAL saturate_aclr_ir : std_logic := '0';
SIGNAL saturate_sload_ir : std_logic := '0';
SIGNAL saturate_bypass_register_ir : std_logic := '0';
SIGNAL saturate_in_reg : std_logic := '0';
SIGNAL saturate_in : std_logic := '0';
--signals for roundchainout input register
SIGNAL roundchainout_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL roundchainout_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL roundchainout_clk_ir : std_logic := '0';
SIGNAL roundchainout_aclr_ir : std_logic := '0';
SIGNAL roundchainout_sload_ir : std_logic := '0';
SIGNAL roundchainout_bypass_register_ir: std_logic := '0';
SIGNAL roundchainout_in_reg : std_logic := '0';
SIGNAL roundchainout_in : std_logic := '0';
--signals for saturatechainout input register
SIGNAL saturatechainout_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturatechainout_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturatechainout_clk_ir : std_logic := '0';
SIGNAL saturatechainout_aclr_ir : std_logic := '0';
SIGNAL saturatechainout_sload_ir: std_logic := '0';
SIGNAL saturatechainout_bypass_register_ir: std_logic := '0';
SIGNAL saturatechainout_in_reg : std_logic := '0';
SIGNAL saturatechainout_in : std_logic := '0';
--signals for fsa_input_interface
SIGNAL dataa_fsa_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datab_fsa_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datac_fsa_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datad_fsa_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL chainin_coa_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL operation : std_logic_vector(3 DOWNTO 0) := (others => '0');
--Signals for First Stage Adder units
SIGNAL dataout_fsa0 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL fsa_pip_datain1 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_fsa1 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL overflow_fsa0 : std_logic := '0';
SIGNAL overflow_fsa1 : std_logic := '0';
--signals for zeroloopback pipeline register
SIGNAL zeroloopback_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroloopback_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroloopback_clk_pip : std_logic := '0';
SIGNAL zeroloopback_aclr_pip : std_logic := '0';
SIGNAL zeroloopback_sload_pip : std_logic := '0';
SIGNAL zeroloopback_bypass_register_pip: std_logic := '0';
SIGNAL zeroloopback_pip_reg : std_logic := '0';
--signals for zeroacc pipeline register
SIGNAL zeroacc_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc_clk_pip : std_logic := '0';
SIGNAL zeroacc_aclr_pip : std_logic := '0';
SIGNAL zeroacc_sload_pip : std_logic := '0';
SIGNAL zeroacc_bypass_register_pip : std_logic := '0';
SIGNAL zeroacc_pip_reg : std_logic := '0';
--Signals for signa pipeline register
SIGNAL signa_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_clk_pip : std_logic := '0';
SIGNAL signa_aclr_pip : std_logic := '0';
SIGNAL signa_sload_pip : std_logic := '0';
SIGNAL signa_bypass_register_pip: std_logic := '0';
SIGNAL signa_pip_reg : std_logic := '0';
--signals for signb pipeline register
SIGNAL signb_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_clk_pip : std_logic := '0';
SIGNAL signb_aclr_pip : std_logic := '0';
SIGNAL signb_sload_pip : std_logic := '0';
SIGNAL signb_bypass_register_pip: std_logic := '0';
SIGNAL signb_pip_reg : std_logic := '0';
--signals for rotate pipeline register
SIGNAL rotate_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rotate_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rotate_clk_pip : std_logic := '0';
SIGNAL rotate_aclr_pip : std_logic := '0';
SIGNAL rotate_sload_pip : std_logic := '0';
SIGNAL rotate_bypass_register_pip : std_logic := '0';
SIGNAL rotate_pip_reg : std_logic := '0';
--signals for shiftright pipeline register
SIGNAL shiftright_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL shiftright_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL shiftright_clk_pip : std_logic := '0';
SIGNAL shiftright_aclr_pip : std_logic := '0';
SIGNAL shiftright_sload_pip : std_logic := '0';
SIGNAL shiftright_bypass_register_pip : std_logic := '0';
SIGNAL shiftright_pip_reg : std_logic := '0';
--signals for round pipeline register
SIGNAL round_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round_clk_pip : std_logic := '0';
SIGNAL round_aclr_pip : std_logic := '0';
SIGNAL round_sload_pip : std_logic := '0';
SIGNAL round_bypass_register_pip: std_logic := '0';
SIGNAL round_pip_reg : std_logic := '0';
--signals for saturate pipeline register
SIGNAL saturate_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate_clk_pip : std_logic := '0';
SIGNAL saturate_aclr_pip : std_logic := '0';
SIGNAL saturate_sload_pip : std_logic := '0';
SIGNAL saturate_bypass_register_pip : std_logic := '0';
SIGNAL saturate_pip_reg : std_logic := '0';
--signals for roundchainout pipeline register
SIGNAL roundchainout_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL roundchainout_aclrval_pip: std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL roundchainout_clk_pip : std_logic := '0';
SIGNAL roundchainout_aclr_pip : std_logic := '0';
SIGNAL roundchainout_sload_pip : std_logic := '0';
SIGNAL roundchainout_bypass_register_pip: std_logic := '0';
SIGNAL roundchainout_pip_reg : std_logic := '0';
--signals for saturatechainout pipeline register
SIGNAL saturatechainout_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturatechainout_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturatechainout_clk_pip : std_logic := '0';
SIGNAL saturatechainout_aclr_pip: std_logic := '0';
SIGNAL saturatechainout_sload_pip : std_logic := '0';
SIGNAL saturatechainout_bypass_register_pip: std_logic := '0';
SIGNAL saturatechainout_pip_reg : std_logic := '0';
--signals for fsa0 pipeline register
SIGNAL fsa0_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL fsa0_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL fsa0_clk_pip : std_logic := '0';
SIGNAL fsa0_aclr_pip : std_logic := '0';
SIGNAL fsa0_sload_pip : std_logic := '0';
SIGNAL fsa0_bypass_register_pip : std_logic := '0';
SIGNAL fsa0_pip_reg : std_logic_vector(71 DOWNTO 0) := (others => '0');
--signals for fsa1 pipeline register
SIGNAL fsa1_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL fsa1_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL fsa1_clk_pip : std_logic := '0';
SIGNAL fsa1_aclr_pip : std_logic := '0';
SIGNAL fsa1_sload_pip : std_logic := '0';
SIGNAL fsa1_bypass_register_pip : std_logic := '0';
SIGNAL fsa1_pip_reg : std_logic_vector(71 DOWNTO 0) := (others => '0');
--Signals for second stage adder
SIGNAL ssa_accum_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL ssa_sign : std_logic := '0';
SIGNAL ssa_dataout : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL ssa_overflow : std_logic := '0';
--Signals for RS block
SIGNAL rs_datain : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_of : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_saturation_overflow : std_logic := '0';
SIGNAL ssa_datain_width : std_logic_vector(7 DOWNTO 0);
SIGNAL ssa_round_width : std_logic_vector(3 DOWNTO 0) := (others => '0');
--signals for zeroloopback output register
SIGNAL zeroloopback_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroloopback_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroloopback_clk_or : std_logic := '0';
SIGNAL zeroloopback_aclr_or : std_logic := '0';
SIGNAL zeroloopback_sload_or : std_logic := '0';
SIGNAL zeroloopback_bypass_register_or : std_logic := '0';
SIGNAL zeroloopback_out_reg : std_logic := '0';
--signals for zerochainout output register
SIGNAL zerochainout_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zerochainout_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zerochainout_clk_or : std_logic := '0';
SIGNAL zerochainout_aclr_or : std_logic := '0';
SIGNAL zerochainout_sload_or : std_logic := '0';
SIGNAL zerochainout_bypass_register_or : std_logic := '0';
SIGNAL zerochainout_out_reg : std_logic := '0';
--Signals for saturation_overflow output register
SIGNAL rs_saturation_overflow_in : std_logic := '0';
SIGNAL saturation_overflow_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturation_overflow_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturation_overflow_clk_or : std_logic := '0';
SIGNAL saturation_overflow_aclr_or : std_logic := '0';
SIGNAL saturation_overflow_sload_or : std_logic := '0';
SIGNAL saturation_overflow_bypass_register_or: std_logic := '0';
SIGNAL saturation_overflow_out_reg : std_logic := '0';
--signals for rs_dataout output register
SIGNAL rs_dataout_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_clkval_or_co : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_aclrval_or_co : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_clkval_or_o : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_aclrval_or_o : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_clk_or : std_logic := '0';
SIGNAL rs_dataout_aclr_or : std_logic := '0';
SIGNAL rs_dataout_sload_or : std_logic := '0';
SIGNAL rs_dataout_bypass_register_or_co : std_logic := '0';
SIGNAL rs_dataout_bypass_register_or_o : std_logic := '0';
SIGNAL rs_dataout_bypass_register_or : std_logic := '0';
SIGNAL rs_dataout_out_reg : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_saturation_overflow_out_reg : std_logic := '0';
--signals for rotate output register
SIGNAL rotate_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rotate_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rotate_clk_or : std_logic := '0';
SIGNAL rotate_aclr_or : std_logic := '0';
SIGNAL rotate_sload_or : std_logic := '0';
SIGNAL rotate_bypass_register_or: std_logic := '0';
SIGNAL rotate_out_reg : std_logic := '0';
--signals for shiftright output register
SIGNAL shiftright_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL shiftright_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL shiftright_clk_or : std_logic := '0';
SIGNAL shiftright_aclr_or : std_logic := '0';
SIGNAL shiftright_sload_or : std_logic := '0';
SIGNAL shiftright_bypass_register_or : std_logic := '0';
SIGNAL shiftright_out_reg : std_logic := '0';
--signals for roundchainout output register
SIGNAL roundchainout_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL roundchainout_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL roundchainout_clk_or : std_logic := '0';
SIGNAL roundchainout_aclr_or : std_logic := '0';
SIGNAL roundchainout_sload_or : std_logic := '0';
SIGNAL roundchainout_bypass_register_or: std_logic := '0';
SIGNAL roundchainout_out_reg : std_logic := '0';
--signals for saturatechainout output register
SIGNAL saturatechainout_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturatechainout_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturatechainout_clk_or : std_logic := '0';
SIGNAL saturatechainout_aclr_or : std_logic := '0';
SIGNAL saturatechainout_sload_or: std_logic := '0';
SIGNAL saturatechainout_bypass_register_or: std_logic := '0';
SIGNAL saturatechainout_out_reg : std_logic := '0';
--Signals for chainout Adder RS Block
SIGNAL coa_dataout : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL coa_round_width : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL coa_rs_dataout : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL coa_rs_saturation_overflow : std_logic := '0';
--signals for control signals for COA output register
SIGNAL coa_reg_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL coa_reg_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL coa_reg_clk_or : std_logic := '0';
SIGNAL coa_reg_aclr_or : std_logic := '0';
SIGNAL coa_reg_sload_or : std_logic := '0';
SIGNAL coa_reg_bypass_register_or : std_logic := '0';
SIGNAL coa_reg_out_reg : std_logic := '0';
SIGNAL coa_rs_saturation_overflow_out_reg: std_logic := '0';
SIGNAL coa_rs_saturationchainout_overflow_out_reg: std_logic := '0';
SIGNAL coa_rs_dataout_out_reg : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_shift_rot : std_logic_vector(71 DOWNTO 0):= (others => '0');
SIGNAL dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL loopbackout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL saturation_overflow_tmp : std_logic := '0';
SIGNAL saturationchainout_overflow_tmp : std_logic := '0';
SIGNAL rs_dataout_tmp1 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL sign : std_logic := '0';
BEGIN
process(rs_dataout, rs_saturation_overflow, saturate_pip_reg)
variable rs_tmp : std_logic_vector(71 downto 0):= (others => '0');
begin
rs_tmp := rs_dataout;
if (((operation_mode = "output_only")or (operation_mode = "one_level_adder") or(operation_mode = "loopback")) and (dataa_width > 1) and (saturate_pip_reg = '1'))then
rs_tmp(dataa_width -1) := rs_saturation_overflow ;
end if;
rs_dataout_of <= rs_tmp;
end process;
--Instantiate the zeroloopback input Register
zeroloopback_clkval_ir <= "0000" WHEN ((zeroloopback_clock = "0") or (zeroloopback_clock = "none"))
ELSE "0001" WHEN (zeroloopback_clock = "1")
ELSE "0010" WHEN (zeroloopback_clock = "2")
ELSE "0011" WHEN (zeroloopback_clock = "3")
ELSE "0000" ;
zeroloopback_aclrval_ir <= "0000" WHEN ((zeroloopback_clear = "0") or (zeroloopback_clear = "none"))
ELSE "0001" WHEN (zeroloopback_clear = "1")
ELSE "0010" WHEN (zeroloopback_clear = "2")
ELSE "0011" WHEN (zeroloopback_clear = "3")
ELSE "0000" ;
zeroloopback_clk_ir <= '1' WHEN clk(conv_integer(zeroloopback_clkval_ir)) = '1' ELSE '0';
zeroloopback_aclr_ir <= '1' WHEN (aclr(conv_integer(zeroloopback_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
zeroloopback_sload_ir <= '1' WHEN ena(conv_integer(zeroloopback_clkval_ir)) = '1' ELSE '0';
zeroloopback_bypass_register_ir <= '1' WHEN (zeroloopback_clock = "none") ELSE '0';
zeroloopback_in <= zeroloopback;
zeroloopback_input_register : stratixiii_mac_bit_register
PORT MAP (
datain => zeroloopback_in,
clk => zeroloopback_clk_ir,
aclr => zeroloopback_aclr_ir,
sload => zeroloopback_sload_ir,
bypass_register => zeroloopback_bypass_register_ir,
dataout => zeroloopback_in_reg
);
--Instantiate the zeroacc input Register
zeroacc_clkval_ir <= "0000" WHEN ((zeroacc_clock = "0") or (zeroacc_clock = "none"))
ELSE "0001" WHEN (zeroacc_clock = "1")
ELSE "0010" WHEN (zeroacc_clock = "2")
ELSE "0011" WHEN (zeroacc_clock = "3")
ELSE "0000" ;
zeroacc_aclrval_ir <= "0000" WHEN ((zeroacc_clear = "0") or (zeroacc_clear = "none"))
ELSE "0001" WHEN (zeroacc_clear = "1")
ELSE "0010" WHEN (zeroacc_clear = "2")
ELSE "0011" WHEN (zeroacc_clear = "3")
ELSE "0000" ;
zeroacc_clk_ir <= '1' WHEN clk(conv_integer(zeroacc_clkval_ir)) = '1' ELSE '0';
zeroacc_aclr_ir <= '1' WHEN (aclr(conv_integer(zeroacc_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
zeroacc_sload_ir <= '1' WHEN ena(conv_integer(zeroacc_clkval_ir)) = '1' ELSE '0';
zeroacc_bypass_register_ir <= '1' WHEN (zeroacc_clock = "none") ELSE '0';
zeroacc_in <= zeroacc;
zeroacc_input_register : stratixiii_mac_bit_register
PORT MAP (
datain => zeroacc_in,
clk => zeroacc_clk_ir,
aclr => zeroacc_aclr_ir,
sload => zeroacc_sload_ir,
bypass_register => zeroacc_bypass_register_ir,
dataout => zeroacc_in_reg
);
--Instantiate the signa input Register
signa_clkval_ir <= "0000" WHEN ((signa_clock = "0") or (signa_clock = "none"))
ELSE "0001" WHEN (signa_clock = "1")
ELSE "0010" WHEN (signa_clock = "2")
ELSE "0011" WHEN (signa_clock = "3")
ELSE "0000" ;
signa_aclrval_ir <= "0000" WHEN ((signa_clear = "0") or (signa_clear = "none"))
ELSE "0001" WHEN (signa_clear = "1")
ELSE "0010" WHEN (signa_clear = "2")
ELSE "0011" WHEN (signa_clear = "3")
ELSE "0000" ;
signa_clk_ir <= '1' WHEN clk(conv_integer(signa_clkval_ir)) = '1' ELSE '0';
signa_aclr_ir <= '1' WHEN (aclr(conv_integer(signa_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
signa_sload_ir <= '1' WHEN ena(conv_integer(signa_clkval_ir)) = '1' ELSE '0';
signa_bypass_register_ir <= '1' WHEN (signa_clock = "none") ELSE '0';
signa_in <= signa;
signa_input_register : stratixiii_mac_bit_register
PORT MAP (
datain => signa_in,
clk => signa_clk_ir,
aclr => signa_aclr_ir,
sload => signa_sload_ir,
bypass_register => signa_bypass_register_ir,
dataout => signa_in_reg
);
--Instantiate the signb input Register
signb_clkval_ir <= "0000" WHEN ((signb_clock = "0") or (signb_clock = "none"))
ELSE "0001" WHEN (signb_clock = "1")
ELSE "0010" WHEN (signb_clock = "2")
ELSE "0011" WHEN (signb_clock = "3")
ELSE "0000" ;
signb_aclrval_ir <= "0000" WHEN ((signb_clear = "0") or (signb_clear = "none"))
ELSE "0001" WHEN (signb_clear = "1")
ELSE "0010" WHEN (signb_clear = "2")
ELSE "0011" WHEN (signb_clear = "3")
ELSE "0000" ;
signb_clk_ir <= '1' WHEN clk(conv_integer(signb_clkval_ir)) = '1' ELSE '0';
signb_aclr_ir <= '1' WHEN (aclr(conv_integer(signb_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
signb_sload_ir <= '1' WHEN ena(conv_integer(signb_clkval_ir)) = '1' ELSE '0';
signb_bypass_register_ir <= '1' WHEN (signb_clock = "none") ELSE '0';
signb_in <= signb;
signb_input_register : stratixiii_mac_bit_register
PORT MAP (
datain => signb_in,
clk => signb_clk_ir,
aclr => signb_aclr_ir,
sload => signb_sload_ir,
bypass_register => signb_bypass_register_ir,
dataout => signb_in_reg
);
--Instantiate the rotate input Register
rotate_clkval_ir <= "0000" WHEN ((rotate_clock = "0") or (rotate_clock = "none"))
ELSE "0001" WHEN (rotate_clock = "1")
ELSE "0010" WHEN (rotate_clock = "2")
ELSE "0011" WHEN (rotate_clock = "3")
ELSE "0000" ;
rotate_aclrval_ir <= "0000" WHEN ((rotate_clear = "0") or (rotate_clear = "none"))
ELSE "0001" WHEN (rotate_clear = "1")
ELSE "0010" WHEN (rotate_clear = "2")
ELSE "0011" WHEN (rotate_clear = "3")
ELSE "0000" ;
rotate_clk_ir <= '1' WHEN clk(conv_integer(rotate_clkval_ir)) = '1' ELSE '0';
rotate_aclr_ir <= '1' WHEN (aclr(conv_integer(rotate_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
rotate_sload_ir <= '1' WHEN ena(conv_integer(rotate_clkval_ir)) = '1' ELSE '0';
rotate_bypass_register_ir <= '1' WHEN (rotate_clock = "none") ELSE '0';
rotate_in <= rotate;
rotate_input_register : stratixiii_mac_bit_register
PORT MAP (
datain => rotate_in,
clk => rotate_clk_ir,
aclr => rotate_aclr_ir,
sload => rotate_sload_ir,
bypass_register => rotate_bypass_register_ir,
dataout => rotate_in_reg
);
--Instantiate the shiftright input Register
shiftright_clkval_ir <= "0000" WHEN ((shiftright_clock = "0") or (shiftright_clock = "none"))
ELSE "0001" WHEN (shiftright_clock = "1")
ELSE "0010" WHEN (shiftright_clock = "2")
ELSE "0011" WHEN (shiftright_clock = "3")
ELSE "0000" ;
shiftright_aclrval_ir <= "0000" WHEN ((shiftright_clear = "0") or (shiftright_clear = "none"))
ELSE "0001" WHEN (shiftright_clear = "1")
ELSE "0010" WHEN (shiftright_clear = "2")
ELSE "0011" WHEN (shiftright_clear = "3")
ELSE "0000" ;
shiftright_clk_ir <= '1' WHEN clk(conv_integer(shiftright_clkval_ir)) = '1' ELSE '0';
shiftright_aclr_ir <= '1' WHEN (aclr(conv_integer(shiftright_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
shiftright_sload_ir <= '1' WHEN ena(conv_integer(shiftright_clkval_ir)) = '1' ELSE '0';
shiftright_bypass_register_ir <= '1' WHEN (shiftright_clock = "none") ELSE '0';
shiftright_in <= shiftright;
shiftright_input_register : stratixiii_mac_bit_register
PORT MAP (
datain => shiftright_in,
clk => shiftright_clk_ir,
aclr => shiftright_aclr_ir,
sload => shiftright_sload_ir,
bypass_register => shiftright_bypass_register_ir,
dataout => shiftright_in_reg
);
--Instantiate the round input Register
round_clkval_ir <= "0000" WHEN ((round_clock = "0") or (round_clock = "none"))
ELSE "0001" WHEN (round_clock = "1")
ELSE "0010" WHEN (round_clock = "2")
ELSE "0011" WHEN (round_clock = "3")
ELSE "0000" ;
round_aclrval_ir <= "0000" WHEN ((round_clear = "0") or (round_clear = "none"))
ELSE "0001" WHEN (round_clear = "1")
ELSE "0010" WHEN (round_clear = "2")
ELSE "0011" WHEN (round_clear = "3")
ELSE "0000" ;
round_clk_ir <= '1' WHEN clk(conv_integer(round_clkval_ir)) = '1' ELSE '0';
round_aclr_ir <= '1' WHEN (aclr(conv_integer(round_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
round_sload_ir <= '1' WHEN ena(conv_integer(round_clkval_ir)) = '1' ELSE '0';
round_bypass_register_ir <= '1' WHEN (round_clock = "none") ELSE '0';
round_in <= round;
round_input_register : stratixiii_mac_bit_register
PORT MAP (
datain => round_in,
clk => round_clk_ir,
aclr => round_aclr_ir,
sload => round_sload_ir,
bypass_register => round_bypass_register_ir,
dataout => round_in_reg
);
--Instantiate the saturate input Register
saturate_clkval_ir <= "0000" WHEN ((saturate_clock = "0") or (saturate_clock = "none"))
ELSE "0001" WHEN (saturate_clock = "1")
ELSE "0010" WHEN (saturate_clock = "2")
ELSE "0011" WHEN (saturate_clock = "3")
ELSE "0000" ;
saturate_aclrval_ir <= "0000" WHEN ((saturate_clear = "0") or (saturate_clear = "none"))
ELSE "0001" WHEN (saturate_clear = "1")
ELSE "0010" WHEN (saturate_clear = "2")
ELSE "0011" WHEN (saturate_clear = "3")
ELSE "0000" ;
saturate_clk_ir <= '1' WHEN clk(conv_integer(saturate_clkval_ir)) = '1' ELSE '0';
saturate_aclr_ir <= '1' WHEN (aclr(conv_integer(saturate_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
saturate_sload_ir <= '1' WHEN ena(conv_integer(saturate_clkval_ir)) = '1' ELSE '0';
saturate_bypass_register_ir <= '1' WHEN (saturate_clock = "none") ELSE '0';
saturate_in <= saturate;
saturate_input_register : stratixiii_mac_bit_register
PORT MAP (
datain => saturate_in,
clk => saturate_clk_ir,
aclr => saturate_aclr_ir,
sload => saturate_sload_ir,
bypass_register => saturate_bypass_register_ir,
dataout => saturate_in_reg
);
--Instantiate the roundchainout input Register
roundchainout_clkval_ir <= "0000" WHEN ((roundchainout_clock = "0") or (roundchainout_clock = "none"))
ELSE "0001" WHEN (roundchainout_clock = "1")
ELSE "0010" WHEN (roundchainout_clock = "2")
ELSE "0011" WHEN (roundchainout_clock = "3")
ELSE "0000" ;
roundchainout_aclrval_ir <= "0000" WHEN ((roundchainout_clear = "0") or (roundchainout_clear = "none"))
ELSE "0001" WHEN (roundchainout_clear = "1")
ELSE "0010" WHEN (roundchainout_clear = "2")
ELSE "0011" WHEN (roundchainout_clear = "3")
ELSE "0000" ;
roundchainout_clk_ir <= '1' WHEN clk(conv_integer(roundchainout_clkval_ir)) = '1' ELSE '0';
roundchainout_aclr_ir <= '1' WHEN (aclr(conv_integer(roundchainout_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
roundchainout_sload_ir <= '1' WHEN ena(conv_integer(roundchainout_clkval_ir)) = '1' ELSE '0';
roundchainout_bypass_register_ir <= '1' WHEN (roundchainout_clock = "none") ELSE '0';
roundchainout_in <= roundchainout;
roundchainout_input_register : stratixiii_mac_bit_register
PORT MAP (
datain => roundchainout_in,
clk => roundchainout_clk_ir,
aclr => roundchainout_aclr_ir,
sload => roundchainout_sload_ir,
bypass_register => roundchainout_bypass_register_ir,
dataout => roundchainout_in_reg
);
--Instantiate the saturatechainout input Register
saturatechainout_clkval_ir <= "0000" WHEN ((saturatechainout_clock = "0") or (saturatechainout_clock = "none"))
ELSE "0001" WHEN (saturatechainout_clock = "1")
ELSE "0010" WHEN (saturatechainout_clock = "2")
ELSE "0011" WHEN (saturatechainout_clock = "3")
ELSE "0000" ;
saturatechainout_aclrval_ir <= "0000" WHEN ((saturatechainout_clear = "0") or (saturatechainout_clear = "none"))
ELSE "0001" WHEN (saturatechainout_clear = "1")
ELSE "0010" WHEN (saturatechainout_clear = "2")
ELSE "0011" WHEN (saturatechainout_clear = "3")
ELSE "0000" ;
saturatechainout_clk_ir <= '1' WHEN clk(conv_integer(saturatechainout_clkval_ir)) = '1' ELSE '0';
saturatechainout_aclr_ir <= '1' WHEN (aclr(conv_integer(saturatechainout_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
saturatechainout_sload_ir <= '1' WHEN ena(conv_integer(saturatechainout_clkval_ir)) = '1' ELSE '0';
saturatechainout_bypass_register_ir <= '1' WHEN (saturatechainout_clock = "none") ELSE '0';
saturatechainout_in <= saturatechainout;
saturatechainout_input_register : stratixiii_mac_bit_register
PORT MAP (
datain => saturatechainout_in,
clk => saturatechainout_clk_ir,
aclr => saturatechainout_aclr_ir,
sload => saturatechainout_sload_ir,
bypass_register => saturatechainout_bypass_register_ir,
dataout => saturatechainout_in_reg
);
--Instantiate the First level adder interface and sign extension block
sign <= signa_in_reg OR signb_in_reg ;
fsa_interface : stratixiii_fsa_isse
GENERIC MAP (
chainin_width => chainin_width,
dataa_width => dataa_width,
datab_width => datab_width,
datac_width => datac_width,
datad_width => datad_width,
operation_mode => operation_mode,
multa_signa_internally_grounded => multa_signa_internally_grounded,
multa_signb_internally_grounded => multa_signb_internally_grounded,
multb_signa_internally_grounded => multb_signa_internally_grounded,
multb_signb_internally_grounded => multb_signb_internally_grounded,
multc_signa_internally_grounded => multc_signa_internally_grounded,
multc_signb_internally_grounded => multc_signb_internally_grounded,
multd_signa_internally_grounded => multd_signa_internally_grounded,
multd_signb_internally_grounded => multd_signb_internally_grounded
)
PORT MAP (
dataa => dataa,
datab => datab,
datac => datac,
datad => datad,
chainin => chainin,
signa => signa_in_reg,
signb => signb_in_reg,
dataa_out => dataa_fsa_in,
datab_out => datab_fsa_in,
datac_out => datac_fsa_in,
datad_out => datad_fsa_in,
chainin_out => chainin_coa_in,
operation => operation
);
--Instantiate First Stage Adder/Subtractor Unit0
fsaunit0 : stratixiii_first_stage_add_sub
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width,
fsa_mode => first_adder0_mode
)
PORT MAP (
dataa => dataa_fsa_in,
datab => datab_fsa_in,
sign => sign,
operation => operation,
dataout => dataout_fsa0
);
--Instantiate First Stage Adder/Subtractor Unit1
fsaunit1 : stratixiii_first_stage_add_sub
GENERIC MAP (
dataa_width => datac_width,
datab_width => datad_width,
fsa_mode => first_adder1_mode
)
PORT MAP (
dataa => datac_fsa_in,
datab => datad_fsa_in,
sign => sign,
operation => operation,
dataout => dataout_fsa1
);
--Instantiate the zeroloopback pipeline Register
zeroloopback_clkval_pip <= "0000" WHEN ((zeroloopback_pipeline_clock = "0") or (zeroloopback_pipeline_clock = "none"))
ELSE "0001" WHEN (zeroloopback_pipeline_clock = "1")
ELSE "0010" WHEN (zeroloopback_pipeline_clock = "2")
ELSE "0011" WHEN (zeroloopback_pipeline_clock = "3")
ELSE "0000" ;
zeroloopback_aclrval_pip <= "0000" WHEN ((zeroloopback_pipeline_clear = "0") or (zeroloopback_pipeline_clear = "none"))
ELSE "0001" WHEN (zeroloopback_pipeline_clear = "1")
ELSE "0010" WHEN (zeroloopback_pipeline_clear = "2")
ELSE "0011" WHEN (zeroloopback_pipeline_clear = "3")
ELSE "0000" ;
zeroloopback_clk_pip <= '1' WHEN clk(conv_integer(zeroloopback_clkval_pip)) = '1' ELSE '0';
zeroloopback_aclr_pip <= '1' WHEN (aclr(conv_integer(zeroloopback_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
zeroloopback_sload_pip <= '1' WHEN ena(conv_integer(zeroloopback_clkval_pip)) = '1' ELSE '0';
zeroloopback_bypass_register_pip <= '1' WHEN (zeroloopback_pipeline_clock = "none") ELSE '0';
zeroloopback_pipeline_register : stratixiii_mac_bit_register
PORT MAP (
datain => zeroloopback_in_reg,
clk => zeroloopback_clk_pip,
aclr => zeroloopback_aclr_pip,
sload => zeroloopback_sload_pip,
bypass_register => zeroloopback_bypass_register_pip,
dataout => zeroloopback_pip_reg
);
--Instantiate the zeroacc pipeline Register
zeroacc_clkval_pip <= "0000" WHEN ((zeroacc_pipeline_clock = "0") or (zeroacc_pipeline_clock = "none"))
ELSE "0001" WHEN (zeroacc_pipeline_clock = "1")
ELSE "0010" WHEN (zeroacc_pipeline_clock = "2")
ELSE "0011" WHEN (zeroacc_pipeline_clock = "3")
ELSE "0000" ;
zeroacc_aclrval_pip <= "0000" WHEN ((zeroacc_pipeline_clear = "0") or (zeroacc_pipeline_clear = "none"))
ELSE "0001" WHEN (zeroacc_pipeline_clear = "1")
ELSE "0010" WHEN (zeroacc_pipeline_clear = "2")
ELSE "0011" WHEN (zeroacc_pipeline_clear = "3")
ELSE "0000" ;
zeroacc_clk_pip <= '1' WHEN clk(conv_integer(zeroacc_clkval_pip)) = '1' ELSE '0';
zeroacc_aclr_pip <= '1' WHEN (aclr(conv_integer(zeroacc_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
zeroacc_sload_pip <= '1' WHEN ena(conv_integer(zeroacc_clkval_pip)) = '1' ELSE '0';
zeroacc_bypass_register_pip <= '1' WHEN (zeroacc_pipeline_clock = "none") ELSE '0';
zeroacc_pipeline_register : stratixiii_mac_bit_register
PORT MAP (
datain => zeroacc_in_reg,
clk => zeroacc_clk_pip,
aclr => zeroacc_aclr_pip,
sload => zeroacc_sload_pip,
bypass_register => zeroacc_bypass_register_pip,
dataout => zeroacc_pip_reg
);
--Instantiate the signa pipeline Register
signa_clkval_pip <= "0000" WHEN ((signa_pipeline_clock = "0") or (signa_pipeline_clock = "none"))
ELSE "0001" WHEN (signa_pipeline_clock = "1")
ELSE "0010" WHEN (signa_pipeline_clock = "2")
ELSE "0011" WHEN (signa_pipeline_clock = "3")
ELSE "0000" ;
signa_aclrval_pip <= "0000" WHEN ((signa_pipeline_clear = "0") or (signa_pipeline_clear = "none"))
ELSE "0001" WHEN (signa_pipeline_clear = "1")
ELSE "0010" WHEN (signa_pipeline_clear = "2")
ELSE "0011" WHEN (signa_pipeline_clear = "3")
ELSE "0000" ;
signa_clk_pip <= '1' WHEN clk(conv_integer(signa_clkval_pip)) = '1' ELSE '0';
signa_aclr_pip <= '1' WHEN (aclr(conv_integer(signa_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
signa_sload_pip <= '1' WHEN ena(conv_integer(signa_clkval_pip)) = '1' ELSE '0';
signa_bypass_register_pip <= '1' WHEN (signa_pipeline_clock = "none") ELSE '0';
signa_pipeline_register : stratixiii_mac_bit_register
PORT MAP (
datain => signa_in_reg,
clk => signa_clk_pip,
aclr => signa_aclr_pip,
sload => signa_sload_pip,
bypass_register => signa_bypass_register_pip,
dataout => signa_pip_reg
);
--Instantiate the signb pipeline Register
signb_clkval_pip <= "0000" WHEN ((signb_pipeline_clock = "0") or (signb_pipeline_clock = "none"))
ELSE "0001" WHEN (signb_pipeline_clock = "1")
ELSE "0010" WHEN (signb_pipeline_clock = "2")
ELSE "0011" WHEN (signb_pipeline_clock = "3")
ELSE "0000" ;
signb_aclrval_pip <= "0000" WHEN ((signb_pipeline_clear = "0") or (signb_pipeline_clear = "none"))
ELSE "0001" WHEN (signb_pipeline_clear = "1")
ELSE "0010" WHEN (signb_pipeline_clear = "2")
ELSE "0011" WHEN (signb_pipeline_clear = "3")
ELSE "0000" ;
signb_clk_pip <= '1' WHEN clk(conv_integer(signb_clkval_pip)) = '1' ELSE '0';
signb_aclr_pip <= '1' WHEN (aclr(conv_integer(signb_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
signb_sload_pip <= '1' WHEN ena(conv_integer(signb_clkval_pip)) = '1' ELSE '0';
signb_bypass_register_pip <= '1' WHEN (signb_pipeline_clock = "none") ELSE '0';
signb_pipeline_register : stratixiii_mac_bit_register
PORT MAP (
datain => signb_in_reg,
clk => signb_clk_pip,
aclr => signb_aclr_pip,
sload => signb_sload_pip,
bypass_register => signb_bypass_register_pip,
dataout => signb_pip_reg
);
--Instantiate the rotate pipeline Register
rotate_clkval_pip <= "0000" WHEN ((rotate_pipeline_clock = "0") or (rotate_pipeline_clock = "none"))
ELSE "0001" WHEN (rotate_pipeline_clock = "1")
ELSE "0010" WHEN (rotate_pipeline_clock = "2")
ELSE "0011" WHEN (rotate_pipeline_clock = "3")
ELSE "0000" ;
rotate_aclrval_pip <= "0000" WHEN ((rotate_pipeline_clear = "0") or (rotate_pipeline_clear = "none"))
ELSE "0001" WHEN (rotate_pipeline_clear = "1")
ELSE "0010" WHEN (rotate_pipeline_clear = "2")
ELSE "0011" WHEN (rotate_pipeline_clear = "3")
ELSE "0000" ;
rotate_clk_pip <= '1' WHEN clk(conv_integer(rotate_clkval_pip)) = '1' ELSE '0';
rotate_aclr_pip <= '1' WHEN (aclr(conv_integer(rotate_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
rotate_sload_pip <= '1' WHEN ena(conv_integer(rotate_clkval_pip)) = '1' ELSE '0';
rotate_bypass_register_pip <= '1' WHEN (rotate_pipeline_clock = "none") ELSE '0';
rotate_pipeline_register : stratixiii_mac_bit_register
PORT MAP (
datain => rotate_in_reg,
clk => rotate_clk_pip,
aclr => rotate_aclr_pip,
sload => rotate_sload_pip,
bypass_register => rotate_bypass_register_pip,
dataout => rotate_pip_reg
);
--Instantiate the shiftright pipeline Register
shiftright_clkval_pip <= "0000" WHEN ((shiftright_pipeline_clock = "0") or (shiftright_pipeline_clock = "none"))
ELSE "0001" WHEN (shiftright_pipeline_clock = "1")
ELSE "0010" WHEN (shiftright_pipeline_clock = "2")
ELSE "0011" WHEN (shiftright_pipeline_clock = "3")
ELSE "0000" ;
shiftright_aclrval_pip <= "0000" WHEN ((shiftright_pipeline_clear = "0") or (shiftright_pipeline_clear = "none"))
ELSE "0001" WHEN (shiftright_pipeline_clear = "1")
ELSE "0010" WHEN (shiftright_pipeline_clear = "2")
ELSE "0011" WHEN (shiftright_pipeline_clear = "3")
ELSE "0000" ;
shiftright_clk_pip <= '1' WHEN clk(conv_integer(shiftright_clkval_pip)) = '1' ELSE '0';
shiftright_aclr_pip <= '1' WHEN (aclr(conv_integer(shiftright_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
shiftright_sload_pip <= '1' WHEN ena(conv_integer(shiftright_clkval_pip)) = '1' ELSE '0';
shiftright_bypass_register_pip <= '1' WHEN (shiftright_pipeline_clock = "none") ELSE '0';
shiftright_pipeline_register : stratixiii_mac_bit_register
PORT MAP (
datain => shiftright_in_reg,
clk => shiftright_clk_pip,
aclr => shiftright_aclr_pip,
sload => shiftright_sload_pip,
bypass_register => shiftright_bypass_register_pip,
dataout => shiftright_pip_reg
);
--Instantiate the round pipeline Register
round_clkval_pip <= "0000" WHEN ((round_pipeline_clock = "0") or (round_pipeline_clock = "none"))
ELSE "0001" WHEN (round_pipeline_clock = "1")
ELSE "0010" WHEN (round_pipeline_clock = "2")
ELSE "0011" WHEN (round_pipeline_clock = "3")
ELSE "0000" ;
round_aclrval_pip <= "0000" WHEN ((round_pipeline_clear = "0") or (round_pipeline_clear = "none"))
ELSE "0001" WHEN (round_pipeline_clear = "1")
ELSE "0010" WHEN (round_pipeline_clear = "2")
ELSE "0011" WHEN (round_pipeline_clear = "3")
ELSE "0000" ;
round_clk_pip <= '1' WHEN clk(conv_integer(round_clkval_pip)) = '1' ELSE '0';
round_aclr_pip <= '1' WHEN (aclr(conv_integer(round_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
round_sload_pip <= '1' WHEN ena(conv_integer(round_clkval_pip)) = '1' ELSE '0';
round_bypass_register_pip <= '1' WHEN (round_pipeline_clock = "none") ELSE '0';
round_pipeline_register : stratixiii_mac_bit_register
PORT MAP (
datain => round_in_reg,
clk => round_clk_pip,
aclr => round_aclr_pip,
sload => round_sload_pip,
bypass_register => round_bypass_register_pip,
dataout => round_pip_reg
);
--Instantiate the saturate pipeline Register
saturate_clkval_pip <= "0000" WHEN ((saturate_pipeline_clock = "0") or (saturate_pipeline_clock = "none"))
ELSE "0001" WHEN (saturate_pipeline_clock = "1")
ELSE "0010" WHEN (saturate_pipeline_clock = "2")
ELSE "0011" WHEN (saturate_pipeline_clock = "3")
ELSE "0000" ;
saturate_aclrval_pip <= "0000" WHEN ((saturate_pipeline_clear = "0") or (saturate_pipeline_clear = "none"))
ELSE "0001" WHEN (saturate_pipeline_clear = "1")
ELSE "0010" WHEN (saturate_pipeline_clear = "2")
ELSE "0011" WHEN (saturate_pipeline_clear = "3")
ELSE "0000" ;
saturate_clk_pip <= '1' WHEN clk(conv_integer(saturate_clkval_pip)) = '1' ELSE '0';
saturate_aclr_pip <= '1' WHEN (aclr(conv_integer(saturate_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
saturate_sload_pip <= '1' WHEN ena(conv_integer(saturate_clkval_pip)) = '1' ELSE '0';
saturate_bypass_register_pip <= '1' WHEN (saturate_pipeline_clock = "none") ELSE '0';
saturate_pipeline_register : stratixiii_mac_bit_register
PORT MAP (
datain => saturate_in_reg,
clk => saturate_clk_pip,
aclr => saturate_aclr_pip,
sload => saturate_sload_pip,
bypass_register => saturate_bypass_register_pip,
dataout => saturate_pip_reg
);
--Instantiate the roundchainout pipeline Register
roundchainout_clkval_pip <= "0000" WHEN ((roundchainout_pipeline_clock = "0") or (roundchainout_pipeline_clock = "none"))
ELSE "0001" WHEN (roundchainout_pipeline_clock = "1")
ELSE "0010" WHEN (roundchainout_pipeline_clock = "2")
ELSE "0011" WHEN (roundchainout_pipeline_clock = "3")
ELSE "0000" ;
roundchainout_aclrval_pip <= "0000" WHEN ((roundchainout_pipeline_clear = "0") or (roundchainout_pipeline_clear = "none"))
ELSE "0001" WHEN (roundchainout_pipeline_clear = "1")
ELSE "0010" WHEN (roundchainout_pipeline_clear = "2")
ELSE "0011" WHEN (roundchainout_pipeline_clear = "3")
ELSE "0000" ;
roundchainout_clk_pip <= '1' WHEN clk(conv_integer(roundchainout_clkval_pip)) = '1' ELSE '0';
roundchainout_aclr_pip <= '1' WHEN (aclr(conv_integer(roundchainout_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
roundchainout_sload_pip <= '1' WHEN ena(conv_integer(roundchainout_clkval_pip)) = '1' ELSE '0';
roundchainout_bypass_register_pip <= '1' WHEN (roundchainout_pipeline_clock = "none") ELSE '0';
roundchainout_pipeline_register : stratixiii_mac_bit_register
PORT MAP (
datain => roundchainout_in_reg,
clk => roundchainout_clk_pip,
aclr => roundchainout_aclr_pip,
sload => roundchainout_sload_pip,
bypass_register => roundchainout_bypass_register_pip,
dataout => roundchainout_pip_reg
);
--Instantiate the saturatechainout pipeline Register
saturatechainout_clkval_pip <= "0000" WHEN ((saturatechainout_pipeline_clock = "0") or (saturatechainout_pipeline_clock = "none"))
ELSE "0001" WHEN (saturatechainout_pipeline_clock = "1")
ELSE "0010" WHEN (saturatechainout_pipeline_clock = "2")
ELSE "0011" WHEN (saturatechainout_pipeline_clock = "3")
ELSE "0000" ;
saturatechainout_aclrval_pip <= "0000" WHEN ((saturatechainout_pipeline_clear = "0") or (saturatechainout_pipeline_clear = "none"))
ELSE "0001" WHEN (saturatechainout_pipeline_clear = "1")
ELSE "0010" WHEN (saturatechainout_pipeline_clear = "2")
ELSE "0011" WHEN (saturatechainout_pipeline_clear = "3")
ELSE "0000" ;
saturatechainout_clk_pip <= '1' WHEN clk(conv_integer(saturatechainout_clkval_pip)) = '1' ELSE '0';
saturatechainout_aclr_pip <= '1' WHEN (aclr(conv_integer(saturatechainout_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
saturatechainout_sload_pip <= '1' WHEN ena(conv_integer(saturatechainout_clkval_pip)) = '1' ELSE '0';
saturatechainout_bypass_register_pip <= '1' WHEN (saturatechainout_pipeline_clock = "none") ELSE '0';
saturatechainout_pipeline_register : stratixiii_mac_bit_register
PORT MAP (
datain => saturatechainout_in_reg,
clk => saturatechainout_clk_pip,
aclr => saturatechainout_aclr_pip,
sload => saturatechainout_sload_pip,
bypass_register => saturatechainout_bypass_register_pip,
dataout => saturatechainout_pip_reg
);
-- Instantiate fsa0 dataout pipline register
fsa_pip_datain1 <= dataa_fsa_in WHEN (operation_mode = "output_only") ELSE dataout_fsa0;
fsa0_clkval_pip <= "0000" WHEN ((first_adder0_clock = "0") or (first_adder0_clock = "none"))
ELSE "0001" WHEN (first_adder0_clock = "1")
ELSE "0010" WHEN (first_adder0_clock = "2")
ELSE "0011" WHEN (first_adder0_clock = "3")
ELSE "0000" ;
fsa0_aclrval_pip <= "0000" WHEN ((first_adder0_clear = "0") or (first_adder0_clear = "none"))
ELSE "0001" WHEN (first_adder0_clear = "1")
ELSE "0010" WHEN (first_adder0_clear = "2")
ELSE "0011" WHEN (first_adder0_clear = "3")
ELSE "0000" ;
fsa0_clk_pip <= '1' WHEN clk(conv_integer(fsa0_clkval_pip)) = '1' ELSE '0';
fsa0_aclr_pip <= '1' WHEN (aclr(conv_integer(fsa0_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
fsa0_sload_pip <= '1' WHEN ena(conv_integer(fsa0_clkval_pip)) = '1' ELSE '0';
fsa0_bypass_register_pip <= '1' WHEN (first_adder0_clock = "none") ELSE '0';
fsa0_pipeline_register : stratixiii_mac_register
GENERIC MAP (
data_width => 72
)
PORT MAP (
datain => fsa_pip_datain1,
clk => fsa0_clk_pip,
aclr => fsa0_aclr_pip,
sload => fsa0_sload_pip,
bypass_register => fsa0_bypass_register_pip,
dataout => fsa0_pip_reg
);
-- Instantiate fsa1 dataout pipline register
fsa1_clkval_pip <= "0000" WHEN ((first_adder1_clock = "0") or (first_adder1_clock = "none"))
ELSE "0001" WHEN (first_adder1_clock = "1")
ELSE "0010" WHEN (first_adder1_clock = "2")
ELSE "0011" WHEN (first_adder1_clock = "3")
ELSE "0000" ;
fsa1_aclrval_pip <= "0000" WHEN ((first_adder1_clear = "0") or (first_adder1_clear = "none"))
ELSE "0001" WHEN (first_adder1_clear = "1")
ELSE "0010" WHEN (first_adder1_clear = "2")
ELSE "0011" WHEN (first_adder1_clear = "3")
ELSE "0000" ;
fsa1_clk_pip <= '1' WHEN clk(conv_integer(fsa1_clkval_pip)) = '1' ELSE '0';
fsa1_aclr_pip <= '1' WHEN (aclr(conv_integer(fsa1_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
fsa1_sload_pip <= '1' WHEN ena(conv_integer(fsa1_clkval_pip)) = '1' ELSE '0';
fsa1_bypass_register_pip <= '1' WHEN (first_adder1_clock = "none") ELSE '0';
fsa1_pipeline_register : stratixiii_mac_register
GENERIC MAP (
data_width => 72
)
PORT MAP (
datain => dataout_fsa1,
clk => fsa1_clk_pip,
aclr => fsa1_aclr_pip,
sload => fsa1_sload_pip,
bypass_register => fsa1_bypass_register_pip,
dataout => fsa1_pip_reg
);
--Instantiate the second level adder/accumulator block
ssa_accum_in <= rs_dataout_out_reg WHEN (NOT zeroacc_pip_reg) = '1' ELSE (others => '0');
ssa_sign <= signa_pip_reg OR signb_pip_reg ;
ssa_unit : stratixiii_second_stage_add_accum
GENERIC MAP (
dataa_width => dataa_width + 1,
datab_width => datac_width + 1,
ssa_mode => acc_adder_operation
)
PORT MAP (
dataa => fsa0_pip_reg,
datab => fsa1_pip_reg,
accumin => ssa_accum_in,
sign => ssa_sign,
operation => operation,
dataout => ssa_dataout,
overflow => ssa_overflow
);
-- Instantiate round and saturation block
rs_datain <= fsa0_pip_reg when ((operation_mode = "output_only") or (operation_mode = "one_level_adder")or(operation_mode = "loopback"))
ELSE ssa_dataout ;
ssa_datain_width <= CONV_STD_LOGIC_VECTOR(dataa_width + 8,8) when ((operation_mode = "accumulator") or(operation_mode = "accumulator_chain_out") or(operation_mode = "two_level_adder_chain_out"))
ELSE CONV_STD_LOGIC_VECTOR(dataa_width +2,8) when(operation_mode = "two_level_adder")
ELSE CONV_STD_LOGIC_VECTOR(dataa_width + datab_width,8) when ((operation_mode = "shift" ) or (operation_mode = "36_bit_multiply" ))
ELSE CONV_STD_LOGIC_VECTOR(dataa_width + 8,8) when ((operation_mode = "double" ))
ELSE CONV_STD_LOGIC_VECTOR(dataa_width,8);
rs_block : stratixiii_round_saturate_block
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width,
operation_mode => operation_mode,
round_mode => round_mode,
saturate_mode => saturate_mode,
saturate_width => saturate_width,
round_width => round_width
)
PORT MAP (
datain => rs_datain,
round => round_pip_reg,
saturate => saturate_pip_reg,
signa => signa_pip_reg,
signb => signb_pip_reg,
datain_width => ssa_datain_width,
dataout => rs_dataout,
saturationoverflow => rs_saturation_overflow
);
--Instantiate the zeroloopback output Register
zeroloopback_clkval_or <= "0000" WHEN ((zeroloopback_output_clock = "0") or (zeroloopback_output_clock = "none"))
ELSE "0001" WHEN (zeroloopback_output_clock = "1")
ELSE "0010" WHEN (zeroloopback_output_clock = "2")
ELSE "0011" WHEN (zeroloopback_output_clock = "3")
ELSE "0000" ;
zeroloopback_aclrval_or <= "0000" WHEN ((zeroloopback_output_clear = "0") or (zeroloopback_output_clear = "none"))
ELSE "0001" WHEN (zeroloopback_output_clear = "1")
ELSE "0010" WHEN (zeroloopback_output_clear = "2")
ELSE "0011" WHEN (zeroloopback_output_clear = "3")
ELSE "0000" ;
zeroloopback_clk_or <= '1' WHEN clk(conv_integer(zeroloopback_clkval_or)) = '1' ELSE '0';
zeroloopback_aclr_or <= '1' WHEN (aclr(conv_integer(zeroloopback_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
zeroloopback_sload_or <= '1' WHEN ena(conv_integer(zeroloopback_clkval_or)) = '1' ELSE '0';
zeroloopback_bypass_register_or <= '1' WHEN (zeroloopback_output_clock = "none") ELSE '0';
zeroloopback_output_register : stratixiii_mac_bit_register
PORT MAP (
datain => zeroloopback_pip_reg,
clk => zeroloopback_clk_or,
aclr => zeroloopback_aclr_or,
sload => zeroloopback_sload_or,
bypass_register => zeroloopback_bypass_register_or,
dataout => zeroloopback_out_reg
);
--Instantiate the zerochainout output Register
zerochainout_clkval_or <= "0000" WHEN ((zerochainout_output_clock = "0") or (zerochainout_output_clock = "none"))
ELSE "0001" WHEN (zerochainout_output_clock = "1")
ELSE "0010" WHEN (zerochainout_output_clock = "2")
ELSE "0011" WHEN (zerochainout_output_clock = "3")
ELSE "0000" ;
zerochainout_aclrval_or <= "0000" WHEN ((zerochainout_output_clear = "0") or (zerochainout_output_clear = "none"))
ELSE "0001" WHEN (zerochainout_output_clear = "1")
ELSE "0010" WHEN (zerochainout_output_clear = "2")
ELSE "0011" WHEN (zerochainout_output_clear = "3")
ELSE "0000" ;
zerochainout_clk_or <= '1' WHEN clk(conv_integer(zerochainout_clkval_or)) = '1' ELSE '0';
zerochainout_aclr_or <= '1' WHEN (aclr(conv_integer(zerochainout_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
zerochainout_sload_or <= '1' WHEN ena(conv_integer(zerochainout_clkval_or)) = '1' ELSE '0';
zerochainout_bypass_register_or <= '1' WHEN (zerochainout_output_clock = "none") ELSE '0';
zerochainout_output_register : stratixiii_mac_bit_register
PORT MAP (
datain => zerochainout,
clk => zerochainout_clk_or,
aclr => zerochainout_aclr_or,
sload => zerochainout_sload_or,
bypass_register => zerochainout_bypass_register_or,
dataout => zerochainout_out_reg
);
-- Instantiate Round_Saturate dataout output register
rs_dataout_clkval_or_co <= "0000" WHEN ((second_adder_clock = "0") or (second_adder_clock = "none"))
ELSE "0001" WHEN (second_adder_clock = "1")
ELSE "0010" WHEN (second_adder_clock = "2")
ELSE "0011" WHEN (second_adder_clock = "3")
ELSE "0000" ;
rs_dataout_aclrval_or_co <= "0000" WHEN ((second_adder_clear = "0") or (second_adder_clear = "none"))
ELSE "0001" WHEN (second_adder_clear = "1")
ELSE "0010" WHEN (second_adder_clear = "2")
ELSE "0011" WHEN (second_adder_clear = "3")
ELSE "0000" ;
rs_dataout_clkval_or_o <= "0000" WHEN ((output_clock = "0") or (output_clock = "none"))
ELSE "0001" WHEN (output_clock = "1")
ELSE "0010" WHEN (output_clock = "2")
ELSE "0011" WHEN (output_clock = "3")
ELSE "0000" ;
rs_dataout_aclrval_or_o <= "0000" WHEN ((output_clear = "0") or (output_clear = "none"))
ELSE "0001" WHEN (output_clear = "1")
ELSE "0010" WHEN (output_clear = "2")
ELSE "0011" WHEN (output_clear = "3")
ELSE "0000" ;
rs_dataout_aclrval_or <= rs_dataout_aclrval_or_co WHEN ((operation_mode = "two_level_adder_chain_out") or (operation_mode = "accumulator_chain_out" ))
ELSE rs_dataout_aclrval_or_o;
rs_dataout_clkval_or <= rs_dataout_clkval_or_co WHEN ((operation_mode = "two_level_adder_chain_out") or (operation_mode = "accumulator_chain_out" ))
ELSE rs_dataout_clkval_or_o;
rs_dataout_bypass_register_or_co <= '1' WHEN (second_adder_clock = "none") ELSE '0';
rs_dataout_bypass_register_or_o <= '1' WHEN (output_clock = "none") ELSE '0';
rs_dataout_clk_or <= '1' WHEN clk(conv_integer(rs_dataout_clkval_or)) = '1' ELSE '0';
rs_dataout_aclr_or <= '1' WHEN (aclr(conv_integer(rs_dataout_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
rs_dataout_sload_or <= '1' WHEN ena(conv_integer(rs_dataout_clkval_or)) = '1' ELSE '0';
rs_dataout_bypass_register_or <= rs_dataout_bypass_register_or_co WHEN ((operation_mode = "two_level_adder_chain_out") or (operation_mode = "accumulator_chain_out" ))
ELSE rs_dataout_bypass_register_or_o;
rs_dataout_in <= ssa_dataout WHEN ((operation_mode = "36_bit_multiply") OR (operation_mode = "shift")) ELSE rs_dataout_of;
rs_dataout_output_register : stratixiii_mac_register
GENERIC MAP (
data_width => 72
)
PORT MAP (
datain => rs_dataout_in,
clk => rs_dataout_clk_or,
aclr => rs_dataout_aclr_or,
sload => rs_dataout_sload_or,
bypass_register => rs_dataout_bypass_register_or,
dataout => rs_dataout_out_reg
);
-- Instantiate Round_Saturate saturation_overflow output register
rs_saturation_overflow_in <= rs_saturation_overflow WHEN (saturate_pip_reg = '1') ELSE ssa_overflow;
rs_saturation_overflow_output_register : stratixiii_mac_bit_register
PORT MAP (
datain => rs_saturation_overflow_in,
clk => rs_dataout_clk_or,
aclr => rs_dataout_aclr_or,
sload => rs_dataout_sload_or,
bypass_register => rs_dataout_bypass_register_or,
dataout => rs_saturation_overflow_out_reg
);
--Instantiate the rotate output Register
rotate_clkval_or <= "0000" WHEN ((rotate_output_clock = "0") or (rotate_output_clock = "none"))
ELSE "0001" WHEN (rotate_output_clock = "1")
ELSE "0010" WHEN (rotate_output_clock = "2")
ELSE "0011" WHEN (rotate_output_clock = "3")
ELSE "0000" ;
rotate_aclrval_or <= "0000" WHEN ((rotate_output_clear = "0") or (rotate_output_clear = "none"))
ELSE "0001" WHEN (rotate_output_clear = "1")
ELSE "0010" WHEN (rotate_output_clear = "2")
ELSE "0011" WHEN (rotate_output_clear = "3")
ELSE "0000" ;
rotate_clk_or <= '1' WHEN clk(conv_integer(rotate_clkval_or)) = '1' ELSE '0';
rotate_aclr_or <= '1' WHEN (aclr(conv_integer(rotate_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
rotate_sload_or <= '1' WHEN ena(conv_integer(rotate_clkval_or)) = '1' ELSE '0';
rotate_bypass_register_or <= '1' WHEN (rotate_output_clock = "none") ELSE '0';
rotate_output_register : stratixiii_mac_bit_register
PORT MAP (
datain => rotate_pip_reg,
clk => rotate_clk_or,
aclr => rotate_aclr_or,
sload => rotate_sload_or,
bypass_register => rotate_bypass_register_or,
dataout => rotate_out_reg
);
--Instantiate the shiftright output Register
shiftright_output_register : stratixiii_mac_bit_register
PORT MAP (
datain => shiftright_pip_reg,
clk => shiftright_clk_or,
aclr => shiftright_aclr_or,
sload => shiftright_sload_or,
bypass_register => shiftright_bypass_register_or,
dataout => shiftright_out_reg
);
shiftright_clkval_or <= "0000" WHEN ((shiftright_output_clock = "0") or (shiftright_output_clock = "none"))
ELSE "0001" WHEN (shiftright_output_clock = "1")
ELSE "0010" WHEN (shiftright_output_clock = "2")
ELSE "0011" WHEN (shiftright_output_clock = "3")
ELSE "0000" ;
shiftright_aclrval_or <= "0000" WHEN ((shiftright_output_clear = "0") or (shiftright_output_clear = "none"))
ELSE "0001" WHEN (shiftright_output_clear = "1")
ELSE "0010" WHEN (shiftright_output_clear = "2")
ELSE "0011" WHEN (shiftright_output_clear = "3")
ELSE "0000" ;
shiftright_clk_or <= '1' WHEN clk(conv_integer(shiftright_clkval_or)) = '1' ELSE '0';
shiftright_aclr_or <= '1' WHEN (aclr(conv_integer(shiftright_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
shiftright_sload_or <= '1' WHEN ena(conv_integer(shiftright_clkval_or)) = '1' ELSE '0';
shiftright_bypass_register_or <= '1' WHEN (shiftright_output_clock = "none") ELSE '0';
--Instantiate the roundchainout output Register
roundchainout_clkval_or <= "0000" WHEN ((roundchainout_output_clock = "0") or (roundchainout_output_clock = "none"))
ELSE "0001" WHEN (roundchainout_output_clock = "1")
ELSE "0010" WHEN (roundchainout_output_clock = "2")
ELSE "0011" WHEN (roundchainout_output_clock = "3")
ELSE "0000" ;
roundchainout_aclrval_or <= "0000" WHEN ((roundchainout_output_clear = "0") or (roundchainout_output_clear = "none"))
ELSE "0001" WHEN (roundchainout_output_clear = "1")
ELSE "0010" WHEN (roundchainout_output_clear = "2")
ELSE "0011" WHEN (roundchainout_output_clear = "3")
ELSE "0000" ;
roundchainout_clk_or <= '1' WHEN clk(conv_integer(roundchainout_clkval_or)) = '1' ELSE '0';
roundchainout_aclr_or <= '1' WHEN (aclr(conv_integer(roundchainout_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
roundchainout_sload_or <= '1' WHEN ena(conv_integer(roundchainout_clkval_or)) = '1' ELSE '0';
roundchainout_bypass_register_or <= '1' WHEN (roundchainout_output_clock = "none") ELSE '0';
roundchainout_output_register : stratixiii_mac_bit_register
PORT MAP (
datain => roundchainout_pip_reg,
clk => roundchainout_clk_or,
aclr => roundchainout_aclr_or,
sload => roundchainout_sload_or,
bypass_register => roundchainout_bypass_register_or,
dataout => roundchainout_out_reg
);
--Instantiate the saturatechainout output Register
saturatechainout_clkval_or <= "0000" WHEN ((saturatechainout_output_clock = "0") or (saturatechainout_output_clock = "none"))
ELSE "0001" WHEN (saturatechainout_output_clock = "1")
ELSE "0010" WHEN (saturatechainout_output_clock = "2")
ELSE "0011" WHEN (saturatechainout_output_clock = "3")
ELSE "0000" ;
saturatechainout_aclrval_or <= "0000" WHEN ((saturatechainout_output_clear = "0") or (saturatechainout_output_clear = "none"))
ELSE "0001" WHEN (saturatechainout_output_clear = "1")
ELSE "0010" WHEN (saturatechainout_output_clear = "2")
ELSE "0011" WHEN (saturatechainout_output_clear = "3")
ELSE "0000" ;
saturatechainout_clk_or <= '1' WHEN clk(conv_integer(saturatechainout_clkval_or)) = '1' ELSE '0';
saturatechainout_aclr_or <= '1' WHEN (aclr(conv_integer(saturatechainout_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
saturatechainout_sload_or <= '1' WHEN ena(conv_integer(saturatechainout_clkval_or)) = '1' ELSE '0';
saturatechainout_bypass_register_or <= '1' WHEN (saturatechainout_output_clock = "none") ELSE '0';
saturatechainout_output_register : stratixiii_mac_bit_register
PORT MAP (
datain => saturatechainout_pip_reg,
clk => saturatechainout_clk_or,
aclr => saturatechainout_aclr_or,
sload => saturatechainout_sload_or,
bypass_register => saturatechainout_bypass_register_or,
dataout => saturatechainout_out_reg
);
--Instantiate the Carry chainout Adder
chainout_adder : stratixiii_carry_chain_adder
PORT MAP (
dataa => rs_dataout_out_reg,
datab => chainin_coa_in,
dataout => coa_dataout
);
--Instantiate the carry chainout adder RS Block
coa_rs_block : stratixiii_round_saturate_block
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width,
operation_mode => operation_mode,
round_mode => round_chain_out_mode,
saturate_mode => saturate_chain_out_mode,
saturate_width => saturate_chain_out_width,
round_width => round_chain_out_width
)
PORT MAP (
datain => coa_dataout,
round => roundchainout_out_reg,
saturate => saturatechainout_out_reg,
signa => signa_pip_reg,
signb => signb_pip_reg,
datain_width => ssa_datain_width,
dataout => coa_rs_dataout,
saturationoverflow => coa_rs_saturation_overflow
);
--Instantiate the rs_saturation_overflow output register (after COA)
coa_reg_clkval_or <= "0000" WHEN ((output_clock = "0") or (output_clock = "none"))
ELSE "0001" WHEN (output_clock = "1")
ELSE "0010" WHEN (output_clock = "2")
ELSE "0011" WHEN (output_clock = "3")
ELSE "0000" ;
coa_reg_aclrval_or <= "0000" WHEN ((output_clear = "0") or (output_clear = "none"))
ELSE "0001" WHEN (output_clear = "1")
ELSE "0010" WHEN (output_clear = "2")
ELSE "0011" WHEN (output_clear = "3")
ELSE "0000" ;
coa_reg_clk_or <= '1' WHEN clk(conv_integer(coa_reg_clkval_or)) = '1' ELSE '0';
coa_reg_aclr_or <= '1' WHEN (aclr(conv_integer(coa_reg_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
coa_reg_sload_or <= '1' WHEN ena(conv_integer(coa_reg_clkval_or)) = '1' ELSE '0';
coa_reg_bypass_register_or <= '1' WHEN (output_clock = "none") ELSE '0';
coa_rs_saturation_overflow_register : stratixiii_mac_bit_register
PORT MAP (
datain => rs_saturation_overflow_out_reg,
clk => coa_reg_clk_or,
aclr => coa_reg_aclr_or,
sload => coa_reg_sload_or,
bypass_register => '1',
dataout => coa_rs_saturation_overflow_out_reg
);
--Instantiate the rs_saturationchainout_overflow output register
coa_rs_saturationchainout_overflow_register : stratixiii_mac_bit_register
PORT MAP (
datain => coa_rs_saturation_overflow,
clk => coa_reg_clk_or,
aclr => coa_reg_aclr_or,
sload => coa_reg_sload_or,
bypass_register => coa_reg_bypass_register_or,
dataout => coa_rs_saturationchainout_overflow_out_reg
);
-- Instantiate the coa_rs_dataout output register
coa_rs_dataout_register : stratixiii_mac_register
GENERIC MAP (
data_width => 72
)
PORT MAP (
datain => coa_rs_dataout,
clk => coa_reg_clk_or,
aclr => coa_reg_aclr_or,
sload => coa_reg_sload_or,
bypass_register => coa_reg_bypass_register_or,
dataout => coa_rs_dataout_out_reg
);
--Instantiate the shift/Rotate Unit
shift_rot_unit : stratixiii_rotate_shift_block
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width
)
PORT MAP (
datain => rs_dataout_out_reg,
rotate => rotate_out_reg,
shiftright => shiftright_out_reg,
signa => signa_pip_reg,
signb => signb_pip_reg,
dataout => dataout_shift_rot
);
--Assign the dataout depENDing on the mode of operation
dataout_tmp <= coa_rs_dataout_out_reg when((operation_mode = "accumulator_chain_out")or(operation_mode = "two_level_adder_chain_out"))
ELSE dataout_shift_rot when (operation_mode = "shift")
ELSE rs_dataout_out_reg;
--Assign the loopbackout for loopback mode
loopbackout_tmp <= rs_dataout_out_reg when((operation_mode = "loopback") and (zeroloopback_out_reg = '0'))
ELSE (others => '0');
--Assign the saturation overflow output
saturation_overflow_tmp <= rs_saturation_overflow_out_reg when((operation_mode = "accumulator") or(operation_mode = "two_level_adder"))
ELSE coa_rs_saturation_overflow_out_reg when((operation_mode = "accumulator_chain_out")or(operation_mode = "two_level_adder_chain_out"))
ELSE '0';
--Assign the saturationchainout overflow output
saturationchainout_overflow_tmp <= coa_rs_saturationchainout_overflow_out_reg when((operation_mode = "accumulator_chain_out") or(operation_mode = "two_level_adder_chain_out"))
ELSE '0';
dataout <= (others => '0') WHEN (((operation_mode = "accumulator_chain_out")or(operation_mode = "two_level_adder_chain_out")) and (zerochainout_out_reg = '1'))
ELSE dataout_tmp;
loopbackout <= loopbackout_tmp(35 downto 18);
overflow <= saturation_overflow_tmp;
saturatechainoutoverflow <= saturationchainout_overflow_tmp;
END arch;
----------------------------------------------------------------------------
-- Module Name : stratixiii_io_pad
-- Description : Simulation model for stratixiii IO pad
----------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
ENTITY stratixiii_io_pad IS
GENERIC (
lpm_type : string := "stratixiii_io_pad");
PORT (
--INPUT PORTS
padin : IN std_logic := '0'; -- Input Pad
--OUTPUT PORTS
padout : OUT std_logic); -- Output Pad
END stratixiii_io_pad;
ARCHITECTURE arch OF stratixiii_io_pad IS
BEGIN
padout <= padin;
END arch;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixiii_mn_cntr
--
-- Description : Timing simulation model for the M and N counter. This is a
-- common model for the input counter and the loop feedback
-- counter of the StratixII PLL.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY stratixiii_mn_cntr is
PORT( clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END stratixiii_mn_cntr;
ARCHITECTURE behave of stratixiii_mn_cntr is
begin
process (clk, reset)
variable count : integer := 1;
variable first_rising_edge : boolean := true;
variable tmp_cout : std_logic;
begin
if (reset = '1') then
count := 1;
tmp_cout := '0';
first_rising_edge := true;
elsif (clk'event) then
if (clk = '1' and first_rising_edge) then
first_rising_edge := false;
tmp_cout := clk;
elsif (not first_rising_edge) then
if (count < modulus) then
count := count + 1;
else
count := 1;
tmp_cout := not tmp_cout;
end if;
end if;
end if;
cout <= transport tmp_cout after time_delay * 1 ps;
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixiii_scale_cntr
--
-- Description : Timing simulation model for the output scale-down counters.
-- This is a common model for the C0, C1, C2, C3, C4 and C5
-- output counters of the StratixII PLL.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY stratixiii_scale_cntr is
PORT( clk : IN std_logic;
reset : IN std_logic := '0';
initial : IN integer := 1;
high : IN integer := 1;
low : IN integer := 1;
mode : IN string := "bypass";
ph_tap : IN integer := 0;
cout : OUT std_logic
);
END stratixiii_scale_cntr;
ARCHITECTURE behave of stratixiii_scale_cntr is
begin
process (clk, reset)
variable tmp_cout : std_logic := '0';
variable count : integer := 1;
variable output_shift_count : integer := 1;
variable first_rising_edge : boolean := false;
begin
if (reset = '1') then
count := 1;
output_shift_count := 1;
tmp_cout := '0';
first_rising_edge := false;
elsif (clk'event) then
if (mode = " off") then
tmp_cout := '0';
elsif (mode = "bypass") then
tmp_cout := clk;
first_rising_edge := true;
elsif (not first_rising_edge) then
if (clk = '1') then
if (output_shift_count = initial) then
tmp_cout := clk;
first_rising_edge := true;
else
output_shift_count := output_shift_count + 1;
end if;
end if;
elsif (output_shift_count < initial) then
if (clk = '1') then
output_shift_count := output_shift_count + 1;
end if;
else
count := count + 1;
if (mode = " even" and (count = (high*2) + 1)) then
tmp_cout := '0';
elsif (mode = " odd" and (count = high*2)) then
tmp_cout := '0';
elsif (count = (high + low)*2 + 1) then
tmp_cout := '1';
count := 1; -- reset count
end if;
end if;
end if;
cout <= transport tmp_cout;
end process;
end behave;
--BEGIN MF PORTING DELETE
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixiii_pll_reg
--
-- Description : Simulation model for a simple DFF.
-- This is required for the generation of the bit slip-signals.
-- No timing, powers upto 0.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY stratixiii_pll_reg is
PORT( clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
end stratixiii_pll_reg;
ARCHITECTURE behave of stratixiii_pll_reg is
begin
process (clk, prn, clrn)
variable q_reg : std_logic := '0';
begin
if (prn = '0') then
q_reg := '1';
elsif (clrn = '0') then
q_reg := '0';
elsif (clk'event and clk = '1' and (ena = '1')) then
q_reg := D;
end if;
Q <= q_reg;
end process;
end behave;
--END MF PORTING DELETE
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixiii_pll
--
-- Description : Timing simulation model for the StratixII PLL.
-- In the functional mode, it is also the model for the altpll
-- megafunction.
--
-- Limitations : Does not support Spread Spectrum and Bandwidth.
--
-- Outputs : Up to 10 output clocks, each defined by its own set of
-- parameters. Locked output (active high) indicates when the
-- PLL locks. clkbad and activeclock are used for
-- clock switchover to indicate which input clock has gone
-- bad, when the clock switchover initiates and which input
-- clock is being used as the reference, respectively.
-- scandataout is the data output of the serial scan chain.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE STD.TEXTIO.all;
USE work.stratixiii_atom_pack.all;
USE work.stratixiii_pllpack.all;
USE work.stratixiii_mn_cntr;
USE work.stratixiii_scale_cntr;
USE work.stratixiii_dffe;
USE work.stratixiii_pll_reg;
-- New Features : The list below outlines key new features in STRATIXIII:
-- 1. Dynamic Phase Reconfiguration
-- 2. Dynamic PLL Reconfiguration (different protocol)
-- 3. More output counters
ENTITY stratixiii_pll is
GENERIC (
operation_mode : string := "normal";
pll_type : string := "auto"; -- AUTO/FAST/ENHANCED/LEFT_RIGHT/TOP_BOTTOM
compensate_clock : string := "clock0";
inclk0_input_frequency : integer := 0;
inclk1_input_frequency : integer := 0;
self_reset_on_loss_lock : string := "off";
switch_over_type : string := "auto";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "off";
dpa_multiply_by : integer := 0;
dpa_divide_by : integer := 0;
dpa_divider : integer := 0;
bandwidth : integer := 0;
bandwidth_type : string := "auto";
use_dc_coupling : string := "false";
lock_c : integer := 4;
sim_gate_lock_device_behavior : string := "off";
lock_high : integer := 0;
lock_low : integer := 0;
lock_window_ui : string := "0.05";
lock_window : time := 5 ps;
test_bypass_lock_detect : string := "off";
clk0_output_frequency : integer := 0;
clk0_multiply_by : integer := 0;
clk0_divide_by : integer := 0;
clk0_phase_shift : string := "0";
clk0_duty_cycle : integer := 50;
clk1_output_frequency : integer := 0;
clk1_multiply_by : integer := 0;
clk1_divide_by : integer := 0;
clk1_phase_shift : string := "0";
clk1_duty_cycle : integer := 50;
clk2_output_frequency : integer := 0;
clk2_multiply_by : integer := 0;
clk2_divide_by : integer := 0;
clk2_phase_shift : string := "0";
clk2_duty_cycle : integer := 50;
clk3_output_frequency : integer := 0;
clk3_multiply_by : integer := 0;
clk3_divide_by : integer := 0;
clk3_phase_shift : string := "0";
clk3_duty_cycle : integer := 50;
clk4_output_frequency : integer := 0;
clk4_multiply_by : integer := 0;
clk4_divide_by : integer := 0;
clk4_phase_shift : string := "0";
clk4_duty_cycle : integer := 50;
clk5_output_frequency : integer := 0;
clk5_multiply_by : integer := 0;
clk5_divide_by : integer := 0;
clk5_phase_shift : string := "0";
clk5_duty_cycle : integer := 50;
clk6_output_frequency : integer := 0;
clk6_multiply_by : integer := 0;
clk6_divide_by : integer := 0;
clk6_phase_shift : string := "0";
clk6_duty_cycle : integer := 50;
clk7_output_frequency : integer := 0;
clk7_multiply_by : integer := 0;
clk7_divide_by : integer := 0;
clk7_phase_shift : string := "0";
clk7_duty_cycle : integer := 50;
clk8_output_frequency : integer := 0;
clk8_multiply_by : integer := 0;
clk8_divide_by : integer := 0;
clk8_phase_shift : string := "0";
clk8_duty_cycle : integer := 50;
clk9_output_frequency : integer := 0;
clk9_multiply_by : integer := 0;
clk9_divide_by : integer := 0;
clk9_phase_shift : string := "0";
clk9_duty_cycle : integer := 50;
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
-- ADVANCED USER PARAMETERS
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
c0_high : integer := 1;
c0_low : integer := 1;
c0_initial : integer := 1;
c0_mode : string := "bypass";
c0_ph : integer := 0;
c1_high : integer := 1;
c1_low : integer := 1;
c1_initial : integer := 1;
c1_mode : string := "bypass";
c1_ph : integer := 0;
c2_high : integer := 1;
c2_low : integer := 1;
c2_initial : integer := 1;
c2_mode : string := "bypass";
c2_ph : integer := 0;
c3_high : integer := 1;
c3_low : integer := 1;
c3_initial : integer := 1;
c3_mode : string := "bypass";
c3_ph : integer := 0;
c4_high : integer := 1;
c4_low : integer := 1;
c4_initial : integer := 1;
c4_mode : string := "bypass";
c4_ph : integer := 0;
c5_high : integer := 1;
c5_low : integer := 1;
c5_initial : integer := 1;
c5_mode : string := "bypass";
c5_ph : integer := 0;
c6_high : integer := 1;
c6_low : integer := 1;
c6_initial : integer := 1;
c6_mode : string := "bypass";
c6_ph : integer := 0;
c7_high : integer := 1;
c7_low : integer := 1;
c7_initial : integer := 1;
c7_mode : string := "bypass";
c7_ph : integer := 0;
c8_high : integer := 1;
c8_low : integer := 1;
c8_initial : integer := 1;
c8_mode : string := "bypass";
c8_ph : integer := 0;
c9_high : integer := 1;
c9_low : integer := 1;
c9_initial : integer := 1;
c9_mode : string := "bypass";
c9_ph : integer := 0;
m_ph : integer := 0;
clk0_counter : string := "unused";
clk1_counter : string := "unused";
clk2_counter : string := "unused";
clk3_counter : string := "unused";
clk4_counter : string := "unused";
clk5_counter : string := "unused";
clk6_counter : string := "unused";
clk7_counter : string := "unused";
clk8_counter : string := "unused";
clk9_counter : string := "unused";
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
c5_use_casc_in : string := "off";
c6_use_casc_in : string := "off";
c7_use_casc_in : string := "off";
c8_use_casc_in : string := "off";
c9_use_casc_in : string := "off";
m_test_source : integer := -1;
c0_test_source : integer := -1;
c1_test_source : integer := -1;
c2_test_source : integer := -1;
c3_test_source : integer := -1;
c4_test_source : integer := -1;
c5_test_source : integer := -1;
c6_test_source : integer := -1;
c7_test_source : integer := -1;
c8_test_source : integer := -1;
c9_test_source : integer := -1;
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
vco_post_scale : integer := 1;
vco_frequency_control : string := "auto";
vco_phase_shift_step : integer := 0;
charge_pump_current : integer := 10;
loop_filter_r : string := " 1.0";
loop_filter_c : integer := 0;
pll_compensation_delay : integer := 0;
simulation_type : string := "functional";
lpm_type : string := "stratixiii_pll";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk5_use_even_counter_mode : string := "off";
clk6_use_even_counter_mode : string := "off";
clk7_use_even_counter_mode : string := "off";
clk8_use_even_counter_mode : string := "off";
clk9_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
clk5_use_even_counter_value : string := "off";
clk6_use_even_counter_value : string := "off";
clk7_use_even_counter_value : string := "off";
clk8_use_even_counter_value : string := "off";
clk9_use_even_counter_value : string := "off";
-- Test only
init_block_reset_a_count : integer := 1;
init_block_reset_b_count : integer := 1;
charge_pump_current_bits : integer := 0;
lock_window_ui_bits : integer := 0;
loop_filter_c_bits : integer := 0;
loop_filter_r_bits : integer := 0;
test_counter_c0_delay_chain_bits : integer := 0;
test_counter_c1_delay_chain_bits : integer := 0;
test_counter_c2_delay_chain_bits : integer := 0;
test_counter_c3_delay_chain_bits : integer := 0;
test_counter_c4_delay_chain_bits : integer := 0;
test_counter_c5_delay_chain_bits : integer := 0;
test_counter_c6_delay_chain_bits : integer := 0;
test_counter_c7_delay_chain_bits : integer := 0;
test_counter_c8_delay_chain_bits : integer := 0;
test_counter_c9_delay_chain_bits : integer := 0;
test_counter_m_delay_chain_bits : integer := 0;
test_counter_n_delay_chain_bits : integer := 0;
test_feedback_comp_delay_chain_bits : integer := 0;
test_input_comp_delay_chain_bits : integer := 0;
test_volt_reg_output_mode_bits : integer := 0;
test_volt_reg_output_voltage_bits : integer := 0;
test_volt_reg_test_mode : string := "false";
vco_range_detector_high_bits : integer := -1;
vco_range_detector_low_bits : integer := -1;
scan_chain_mif_file : string := "";
dpa_output_clock_phase_shift : integer := 0;
test_counter_c3_sclk_delay_chain_bits : integer := -1;
test_counter_c4_sclk_delay_chain_bits : integer := -1;
test_counter_c5_lden_delay_chain_bits : integer := -1;
test_counter_c6_lden_delay_chain_bits : integer := -1;
auto_settings : string := "true";
-- Simulation only generics
family_name : string := "StratixIII";
-- VITAL generics
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_fbin : VitalDelayType01 := DefPropDelay01;
tipd_scanclk : VitalDelayType01 := DefPropDelay01;
tipd_scanclkena : VitalDelayType01 := DefPropDelay01;
tipd_scandata : VitalDelayType01 := DefPropDelay01;
tipd_configupdate : VitalDelayType01 := DefPropDelay01;
tipd_clkswitch : VitalDelayType01 := DefPropDelay01;
tipd_phaseupdown : VitalDelayType01 := DefPropDelay01;
tipd_phasecounterselect : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phasestep : VitalDelayType01 := DefPropDelay01;
tsetup_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
use_vco_bypass : string := "false"
);
PORT
(
inclk : in std_logic_vector(1 downto 0);
fbin : in std_logic := '0';
fbout : out std_logic;
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
scandata : in std_logic := '0';
scanclk : in std_logic := '0';
scanclkena : in std_logic := '1';
configupdate : in std_logic := '0';
clk : out std_logic_vector(9 downto 0);
phasecounterselect : in std_logic_vector(3 downto 0) := "0000";
phaseupdown : in std_logic := '0';
phasestep : in std_logic := '0';
clkbad : out std_logic_vector(1 downto 0);
activeclock : out std_logic;
locked : out std_logic;
scandataout : out std_logic;
scandone : out std_logic;
phasedone : out std_logic;
vcooverrange : out std_logic;
vcounderrange : out std_logic
);
END stratixiii_pll;
ARCHITECTURE vital_pll of stratixiii_pll is
TYPE int_array is ARRAY(NATURAL RANGE <>) of integer;
TYPE str_array is ARRAY(NATURAL RANGE <>) of string(1 to 6);
TYPE str_array1 is ARRAY(NATURAL RANGE <>) of string(1 to 9);
TYPE std_logic_array is ARRAY(NATURAL RANGE <>) of std_logic;
-- internal advanced parameter signals
signal i_vco_min : integer := vco_min * (vco_post_scale/2);
signal i_vco_max : integer := vco_max * (vco_post_scale/2);
signal i_vco_center : integer;
signal i_pfd_min : integer;
signal i_pfd_max : integer;
signal c_ph_val : int_array(0 to 9) := (OTHERS => 0);
signal c_ph_val_tmp : int_array(0 to 9) := (OTHERS => 0);
signal c_high_val : int_array(0 to 9) := (OTHERS => 1);
signal c_low_val : int_array(0 to 9) := (OTHERS => 1);
signal c_initial_val : int_array(0 to 9) := (OTHERS => 1);
signal c_mode_val : str_array(0 to 9);
signal clk_num : str_array(0 to 9);
-- old values
signal c_high_val_old : int_array(0 to 9) := (OTHERS => 1);
signal c_low_val_old : int_array(0 to 9) := (OTHERS => 1);
signal c_ph_val_old : int_array(0 to 9) := (OTHERS => 0);
signal c_mode_val_old : str_array(0 to 9);
-- hold registers
signal c_high_val_hold : int_array(0 to 9) := (OTHERS => 1);
signal c_low_val_hold : int_array(0 to 9) := (OTHERS => 1);
signal c_ph_val_hold : int_array(0 to 9) := (OTHERS => 0);
signal c_mode_val_hold : str_array(0 to 9);
-- temp registers
signal sig_c_ph_val_tmp : int_array(0 to 9) := (OTHERS => 0);
signal c_ph_val_orig : int_array(0 to 9) := (OTHERS => 0);
signal i_clk9_counter : integer := 9;
signal i_clk8_counter : integer := 8;
signal i_clk7_counter : integer := 7;
signal i_clk6_counter : integer := 6;
signal i_clk5_counter : integer := 5;
signal real_lock_high : integer := 0;
signal i_clk4_counter : integer := 4;
signal i_clk3_counter : integer := 3;
signal i_clk2_counter : integer := 2;
signal i_clk1_counter : integer := 1;
signal i_clk0_counter : integer := 0;
signal i_charge_pump_current : integer;
signal i_loop_filter_r : integer;
-- end internal advanced parameter signals
-- CONSTANTS
CONSTANT SCAN_CHAIN : integer := 144;
CONSTANT GPP_SCAN_CHAIN : integer := 234;
CONSTANT FAST_SCAN_CHAIN : integer := 180;
CONSTANT cntrs : str_array(9 downto 0) := (" C9", " C8", " C7", " C6", " C5", " C4", " C3", " C2", " C1", " C0");
CONSTANT ss_cntrs : str_array(0 to 3) := (" M", " M2", " N", " N2");
CONSTANT loop_filter_c_arr : int_array(0 to 3) := (0,0,0,0);
CONSTANT fpll_loop_filter_c_arr : int_array(0 to 3) := (0,0,0,0);
CONSTANT charge_pump_curr_arr : int_array(0 to 15) := (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0);
CONSTANT num_phase_taps : integer := 8;
-- signals
signal vcc : std_logic := '1';
signal fbclk : std_logic;
signal refclk : std_logic;
signal vco_over : std_logic := '0';
signal vco_under : std_logic := '1';
signal pll_locked : boolean := false;
signal c_clk : std_logic_array(0 to 9);
signal vco_out : std_logic_vector(7 downto 0) := (OTHERS => '0');
-- signals to assign values to counter params
signal m_val : integer := 1;
signal n_val : integer := 1;
signal m_ph_val : integer := 0;
signal m_ph_initial : integer := 0;
signal m_ph_val_tmp : integer := 0;
signal m_initial_val : integer := m_initial;
signal m_mode_val : string(1 to 6) := " ";
signal n_mode_val : string(1 to 6) := " ";
signal lfc_val : integer := 0;
signal vco_cur : integer := vco_post_scale;
signal cp_curr_val : integer := 0;
signal lfr_val : string(1 to 2) := " ";
signal cp_curr_old_bit_setting : integer := charge_pump_current_bits;
signal cp_curr_val_bit_setting : std_logic_vector(2 downto 0) := (OTHERS => '0');
signal lfr_old_bit_setting : integer := loop_filter_r_bits;
signal lfr_val_bit_setting : std_logic_vector(4 downto 0) := (OTHERS => '0');
signal lfc_old_bit_setting : integer := loop_filter_c_bits;
signal lfc_val_bit_setting : std_logic_vector(1 downto 0) := (OTHERS => '0');
signal pll_reconfig_display_full_setting : boolean := FALSE; -- display full setting, change to true
-- old values
signal m_val_old : integer := 1;
signal n_val_old : integer := 1;
signal m_mode_val_old : string(1 to 6) := " ";
signal n_mode_val_old : string(1 to 6) := " ";
signal m_ph_val_old : integer := 0;
signal lfc_old : integer := 0;
signal vco_old : integer := 0;
signal cp_curr_old : integer := 0;
signal lfr_old : string(1 to 2) := " ";
signal num_output_cntrs : integer := 10;
signal scanclk_period : time := 1 ps;
signal scan_data : std_logic_vector(0 to 233) := (OTHERS => '0');
signal clk_pfd : std_logic_vector(0 to 9);
signal clk0_tmp : std_logic;
signal clk1_tmp : std_logic;
signal clk2_tmp : std_logic;
signal clk3_tmp : std_logic;
signal clk4_tmp : std_logic;
signal clk5_tmp : std_logic;
signal clk6_tmp : std_logic;
signal clk7_tmp : std_logic;
signal clk8_tmp : std_logic;
signal clk9_tmp : std_logic;
signal update_conf_latches : std_logic := '0';
signal update_conf_latches_reg : std_logic := '0';
signal clkin : std_logic := '0';
signal gate_locked : std_logic := '0';
signal pfd_locked : std_logic := '0';
signal lock : std_logic := '0';
signal about_to_lock : boolean := false;
signal reconfig_err : boolean := false;
signal inclk_c0 : std_logic;
signal inclk_c1 : std_logic;
signal inclk_c2 : std_logic;
signal inclk_c3 : std_logic;
signal inclk_c4 : std_logic;
signal inclk_c5 : std_logic;
signal inclk_c6 : std_logic;
signal inclk_c7 : std_logic;
signal inclk_c8 : std_logic;
signal inclk_c9 : std_logic;
signal inclk_m : std_logic;
signal devpor : std_logic;
signal devclrn : std_logic;
signal inclk0_ipd : std_logic;
signal inclk1_ipd : std_logic;
signal pfdena_ipd : std_logic;
signal areset_ipd : std_logic;
signal fbin_ipd : std_logic;
signal scanclk_ipd : std_logic;
signal scanclkena_ipd, scanclkena_reg : std_logic;
signal scandata_ipd : std_logic;
signal clkswitch_ipd : std_logic;
signal phasecounterselect_ipd : std_logic_vector(3 downto 0);
signal phaseupdown_ipd : std_logic;
signal phasestep_ipd : std_logic;
signal configupdate_ipd : std_logic;
-- registered signals
signal sig_offset : time := 0 ps;
signal sig_refclk_time : time := 0 ps;
signal sig_fbclk_period : time := 0 ps;
signal sig_vco_period_was_phase_adjusted : boolean := false;
signal sig_phase_adjust_was_scheduled : boolean := false;
signal sig_stop_vco : std_logic := '0';
signal sig_m_times_vco_period : time := 0 ps;
signal sig_new_m_times_vco_period : time := 0 ps;
signal sig_got_refclk_posedge : boolean := false;
signal sig_got_fbclk_posedge : boolean := false;
signal sig_got_second_refclk : boolean := false;
signal m_delay : integer := 0;
signal n_delay : integer := 0;
signal inclk1_tmp : std_logic := '0';
signal reset_low : std_logic := '0';
-- Phase Reconfig
SIGNAL phasecounterselect_reg : std_logic_vector(3 DOWNTO 0);
SIGNAL phaseupdown_reg : std_logic := '0';
SIGNAL phasestep_reg : std_logic := '0';
SIGNAL phasestep_high_count : integer := 0;
SIGNAL update_phase : std_logic := '0';
signal scandataout_tmp : std_logic := '0';
signal scandata_in : std_logic := '0';
signal scandata_out : std_logic := '0';
signal scandone_tmp : std_logic := '1';
signal initiate_reconfig : std_logic := '0';
signal sig_refclk_period : time := (inclk0_input_frequency * 1 ps) * n;
signal schedule_vco : std_logic := '0';
signal areset_ena_sig : std_logic := '0';
signal pll_in_test_mode : boolean := false;
signal pll_has_just_been_reconfigured : boolean := false;
signal inclk_c_from_vco : std_logic_array(0 to 9);
signal inclk_m_from_vco : std_logic;
SIGNAL inclk0_period : time := 0 ps;
SIGNAL last_inclk0_period : time := 0 ps;
SIGNAL last_inclk0_edge : time := 0 ps;
SIGNAL first_inclk0_edge_detect : STD_LOGIC := '0';
SIGNAL inclk1_period : time := 0 ps;
SIGNAL last_inclk1_period : time := 0 ps;
SIGNAL last_inclk1_edge : time := 0 ps;
SIGNAL first_inclk1_edge_detect : STD_LOGIC := '0';
COMPONENT stratixiii_mn_cntr
PORT (
clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END COMPONENT;
COMPONENT stratixiii_scale_cntr
PORT (
clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial : IN integer := 1;
high : IN integer := 1;
low : IN integer := 1;
mode : IN string := "bypass";
ph_tap : IN integer := 0
);
END COMPONENT;
COMPONENT stratixiii_dffe
GENERIC(
TimingChecksOn: Boolean := true;
InstancePath: STRING := "*";
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
PORT(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
END COMPONENT;
COMPONENT stratixiii_pll_reg
PORT(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (inclk0_ipd, inclk(0), tipd_inclk(0));
VitalWireDelay (inclk1_ipd, inclk(1), tipd_inclk(1));
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (fbin_ipd, fbin, tipd_fbin);
VitalWireDelay (pfdena_ipd, pfdena, tipd_pfdena);
VitalWireDelay (scanclk_ipd, scanclk, tipd_scanclk);
VitalWireDelay (scanclkena_ipd, scanclkena, tipd_scanclkena);
VitalWireDelay (scandata_ipd, scandata, tipd_scandata);
VitalWireDelay (configupdate_ipd, configupdate, tipd_configupdate);
VitalWireDelay (clkswitch_ipd, clkswitch, tipd_clkswitch);
VitalWireDelay (phaseupdown_ipd, phaseupdown, tipd_phaseupdown);
VitalWireDelay (phasestep_ipd, phasestep, tipd_phasestep);
VitalWireDelay (phasecounterselect_ipd(0), phasecounterselect(0), tipd_phasecounterselect(0));
VitalWireDelay (phasecounterselect_ipd(1), phasecounterselect(1), tipd_phasecounterselect(1));
VitalWireDelay (phasecounterselect_ipd(2), phasecounterselect(2), tipd_phasecounterselect(2));
VitalWireDelay (phasecounterselect_ipd(3), phasecounterselect(3), tipd_phasecounterselect(3));
end block;
inclk_m <= fbclk when m_test_source = 0 else
refclk when m_test_source = 1 else
inclk_m_from_vco;
areset_ena_sig <= areset_ipd or sig_stop_vco;
pll_in_test_mode <= true when (m_test_source /= -1 or c0_test_source /= -1 or
c1_test_source /= -1 or c2_test_source /= -1 or
c3_test_source /= -1 or c4_test_source /= -1 or
c5_test_source /= -1 or c6_test_source /= -1 or
c7_test_source /= -1 or c8_test_source /= -1 or
c9_test_source /= -1)
else
false;
real_lock_high <= lock_high WHEN (sim_gate_lock_device_behavior = "on") ELSE 0;
m1 : stratixiii_mn_cntr
port map ( clk => inclk_m,
reset => areset_ena_sig,
cout => fbclk,
initial_value => m_initial_val,
modulus => m_val,
time_delay => m_delay
);
-- add delta delay to inclk1 to ensure inclk0 and inclk1 are processed
-- in different simulation deltas.
inclk1_tmp <= inclk1_ipd;
-- Calculate the inclk0 period
PROCESS
VARIABLE inclk0_period_tmp : time := 0 ps;
BEGIN
WAIT UNTIL (inclk0_ipd'EVENT AND inclk0_ipd = '1');
IF (first_inclk0_edge_detect = '0') THEN
first_inclk0_edge_detect <= '1';
ELSE
last_inclk0_period <= inclk0_period;
inclk0_period_tmp := NOW - last_inclk0_edge;
END IF;
last_inclk0_edge <= NOW;
inclk0_period <= inclk0_period_tmp;
END PROCESS;
-- Calculate the inclk1 period
PROCESS
VARIABLE inclk1_period_tmp : time := 0 ps;
BEGIN
WAIT UNTIL (inclk1_ipd'EVENT AND inclk1_ipd = '1');
IF (first_inclk1_edge_detect = '0') THEN
first_inclk1_edge_detect <= '1';
ELSE
last_inclk1_period <= inclk1_period;
inclk1_period_tmp := NOW - last_inclk1_edge;
END IF;
last_inclk1_edge <= NOW;
inclk1_period <= inclk1_period_tmp;
END PROCESS;
process (inclk0_ipd, inclk1_tmp, clkswitch_ipd)
variable input_value : std_logic := '0';
variable current_clock : integer := 0;
variable clk0_count, clk1_count : integer := 0;
variable clk0_is_bad, clk1_is_bad : std_logic := '0';
variable primary_clk_is_bad : boolean := false;
variable current_clk_is_bad : boolean := false;
variable got_curr_clk_falling_edge_after_clkswitch : boolean := false;
variable switch_over_count : integer := 0;
variable active_clock : std_logic := '0';
variable external_switch : boolean := false;
variable diff_percent_period : integer := 0;
variable buf : line;
variable switch_clock : boolean := false;
begin
if (now = 0 ps) then
if (switch_over_type = "manual" and clkswitch_ipd = '1') then
current_clock := 1;
active_clock := '1';
end if;
end if;
if (clkswitch_ipd'event and clkswitch_ipd = '1' and switch_over_type = "auto") then
external_switch := true;
elsif (switch_over_type = "manual") then
if (clkswitch_ipd'event and clkswitch_ipd = '1') then
switch_clock := true;
elsif (clkswitch_ipd'event and clkswitch_ipd = '0') then
switch_clock := false;
end if;
end if;
if (switch_clock = true) then
if (inclk0_ipd'event or inclk1_tmp'event) then
if (current_clock = 0) then
current_clock := 1;
active_clock := '1';
clkin <= transport inclk1_tmp;
elsif (current_clock = 1) then
current_clock := 0;
active_clock := '0';
clkin <= transport inclk0_ipd;
end if;
switch_clock := false;
end if;
end if;
-- save the current inclk event value
if (inclk0_ipd'event) then
input_value := inclk0_ipd;
elsif (inclk1_tmp'event) then
input_value := inclk1_tmp;
end if;
-- check if either input clk is bad
if (inclk0_ipd'event and inclk0_ipd = '1') then
clk0_count := clk0_count + 1;
clk0_is_bad := '0';
clk1_count := 0;
if (clk0_count > 2) then
-- no event on other clk for 2 cycles
clk1_is_bad := '1';
if (current_clock = 1) then
current_clk_is_bad := true;
end if;
end if;
end if;
if (inclk1_tmp'event and inclk1_tmp = '1') then
clk1_count := clk1_count + 1;
clk1_is_bad := '0';
clk0_count := 0;
if (clk1_count > 2) then
-- no event on other clk for 2 cycles
clk0_is_bad := '1';
if (current_clock = 0) then
current_clk_is_bad := true;
end if;
end if;
end if;
-- check if the bad clk is the primary clock
if (clk0_is_bad = '1') then
primary_clk_is_bad := true;
else
primary_clk_is_bad := false;
end if;
-- actual switching
if (inclk0_ipd'event and current_clock = 0) then
if (external_switch) then
if (not got_curr_clk_falling_edge_after_clkswitch) then
if (inclk0_ipd = '0') then
got_curr_clk_falling_edge_after_clkswitch := true;
end if;
clkin <= transport inclk0_ipd;
end if;
else
clkin <= transport inclk0_ipd;
end if;
elsif (inclk1_tmp'event and current_clock = 1) then
if (external_switch) then
if (not got_curr_clk_falling_edge_after_clkswitch) then
if (inclk1_tmp = '0') then
got_curr_clk_falling_edge_after_clkswitch := true;
end if;
clkin <= transport inclk1_tmp;
end if;
else
clkin <= transport inclk1_tmp;
end if;
else
if (input_value = '1' and enable_switch_over_counter = "on" and primary_clk_is_bad) then
switch_over_count := switch_over_count + 1;
end if;
if ((input_value = '0')) then
if (external_switch and (got_curr_clk_falling_edge_after_clkswitch or current_clk_is_bad)) or (primary_clk_is_bad and clkswitch_ipd /= '1' and (enable_switch_over_counter = "off" or switch_over_count = switch_over_counter)) then
got_curr_clk_falling_edge_after_clkswitch := false;
if(inclk0_period > inclk1_period) then
diff_percent_period := (( inclk0_period - inclk1_period ) * 100) / inclk1_period;
else
diff_percent_period := (( inclk1_period - inclk0_period ) * 100) / inclk0_period;
end if;
if((diff_percent_period > 20)and ( switch_over_type = "auto")) then
WRITE(buf,string'("Warning : The input clock frequencies specified for the specified PLL are too far apart for auto-switch-over feature to work properly. Please make sure that the clock frequencies are 20 percent apart for correct functionality."));
writeline(output, buf);
end if;
if (current_clock = 0) then
current_clock := 1;
else
current_clock := 0;
end if;
active_clock := not active_clock;
switch_over_count := 0;
external_switch := false;
current_clk_is_bad := false;
else
if(switch_over_type = "auto") then
if(current_clock = 0 and clk0_is_bad = '1' and clk1_is_bad = '0' ) then
current_clock := 1;
active_clock := not active_clock;
end if;
if(current_clock = 1 and clk0_is_bad = '0' and clk1_is_bad = '1' ) then
current_clock := 0;
active_clock := not active_clock;
end if;
end if;
end if;
end if;
end if;
-- schedule outputs
clkbad(0) <= clk0_is_bad;
clkbad(1) <= clk1_is_bad;
activeclock <= active_clock;
end process;
n1 : stratixiii_mn_cntr
port map (
clk => clkin,
reset => areset_ipd,
cout => refclk,
initial_value => n_val,
modulus => n_val);
inclk_c0 <= refclk when c0_test_source = 1 else
fbclk when c0_test_source = 0 else
inclk_c_from_vco(0);
c0 : stratixiii_scale_cntr
port map (
clk => inclk_c0,
reset => areset_ena_sig,
cout => c_clk(0),
initial => c_initial_val(0),
high => c_high_val(0),
low => c_low_val(0),
mode => c_mode_val(0),
ph_tap => c_ph_val(0));
inclk_c1 <= refclk when c1_test_source = 1 else
fbclk when c1_test_source = 0 else
c_clk(0) when c1_use_casc_in = "on" else
inclk_c_from_vco(1);
c1 : stratixiii_scale_cntr
port map (
clk => inclk_c1,
reset => areset_ena_sig,
cout => c_clk(1),
initial => c_initial_val(1),
high => c_high_val(1),
low => c_low_val(1),
mode => c_mode_val(1),
ph_tap => c_ph_val(1));
inclk_c2 <= refclk when c2_test_source = 1 else
fbclk when c2_test_source = 0 else
c_clk(1) when c2_use_casc_in = "on" else
inclk_c_from_vco(2);
c2 : stratixiii_scale_cntr
port map (
clk => inclk_c2,
reset => areset_ena_sig,
cout => c_clk(2),
initial => c_initial_val(2),
high => c_high_val(2),
low => c_low_val(2),
mode => c_mode_val(2),
ph_tap => c_ph_val(2));
inclk_c3 <= refclk when c3_test_source = 1 else
fbclk when c3_test_source = 0 else
c_clk(2) when c3_use_casc_in = "on" else
inclk_c_from_vco(3);
c3 : stratixiii_scale_cntr
port map (
clk => inclk_c3,
reset => areset_ena_sig,
cout => c_clk(3),
initial => c_initial_val(3),
high => c_high_val(3),
low => c_low_val(3),
mode => c_mode_val(3),
ph_tap => c_ph_val(3));
inclk_c4 <= refclk when c4_test_source = 1 else
fbclk when c4_test_source = 0 else
c_clk(3) when (c4_use_casc_in = "on") else
inclk_c_from_vco(4);
c4 : stratixiii_scale_cntr
port map (
clk => inclk_c4,
reset => areset_ena_sig,
cout => c_clk(4),
initial => c_initial_val(4),
high => c_high_val(4),
low => c_low_val(4),
mode => c_mode_val(4),
ph_tap => c_ph_val(4));
inclk_c5 <= refclk when c5_test_source = 1 else
fbclk when c5_test_source = 0 else
c_clk(4) when c5_use_casc_in = "on" else
inclk_c_from_vco(5);
c5 : stratixiii_scale_cntr
port map (
clk => inclk_c5,
reset => areset_ena_sig,
cout => c_clk(5),
initial => c_initial_val(5),
high => c_high_val(5),
low => c_low_val(5),
mode => c_mode_val(5),
ph_tap => c_ph_val(5));
inclk_c6 <= refclk when c6_test_source = 1 else
fbclk when c6_test_source = 0 else
c_clk(5) when c6_use_casc_in = "on" else
inclk_c_from_vco(6);
c6 : stratixiii_scale_cntr
port map (
clk => inclk_c6,
reset => areset_ena_sig,
cout => c_clk(6),
initial => c_initial_val(6),
high => c_high_val(6),
low => c_low_val(6),
mode => c_mode_val(6),
ph_tap => c_ph_val(6));
inclk_c7 <= refclk when c7_test_source = 1 else
fbclk when c7_test_source = 0 else
c_clk(6) when c7_use_casc_in = "on" else
inclk_c_from_vco(7);
c7 : stratixiii_scale_cntr
port map (
clk => inclk_c7,
reset => areset_ena_sig,
cout => c_clk(7),
initial => c_initial_val(7),
high => c_high_val(7),
low => c_low_val(7),
mode => c_mode_val(7),
ph_tap => c_ph_val(7));
inclk_c8 <= refclk when c8_test_source = 1 else
fbclk when c8_test_source = 0 else
c_clk(7) when c8_use_casc_in = "on" else
inclk_c_from_vco(8);
c8 : stratixiii_scale_cntr
port map (
clk => inclk_c8,
reset => areset_ena_sig,
cout => c_clk(8),
initial => c_initial_val(8),
high => c_high_val(8),
low => c_low_val(8),
mode => c_mode_val(8),
ph_tap => c_ph_val(8));
inclk_c9 <= refclk when c9_test_source = 1 else
fbclk when c9_test_source = 0 else
c_clk(8) when c9_use_casc_in = "on" else
inclk_c_from_vco(9);
c9 : stratixiii_scale_cntr
port map (
clk => inclk_c9,
reset => areset_ena_sig,
cout => c_clk(9),
initial => c_initial_val(9),
high => c_high_val(9),
low => c_low_val(9),
mode => c_mode_val(9),
ph_tap => c_ph_val(9));
process(scandone_tmp, lock)
begin
if (scandone_tmp'event and (scandone_tmp = '1')) then
pll_has_just_been_reconfigured <= true;
elsif (lock'event and (lock = '1')) then
pll_has_just_been_reconfigured <= false;
end if;
end process;
process(inclk_c0, inclk_c1, areset_ipd, sig_stop_vco)
variable c0_got_first_rising_edge : boolean := false;
variable c0_count : integer := 2;
variable c0_initial_count : integer := 1;
variable c0_tmp, c1_tmp : std_logic := '0';
variable c1_got_first_rising_edge : boolean := false;
variable c1_count : integer := 2;
variable c1_initial_count : integer := 1;
begin
if (areset_ipd = '1' or sig_stop_vco = '1') then
c0_count := 2;
c1_count := 2;
c0_initial_count := 1;
c1_initial_count := 1;
c0_got_first_rising_edge := false;
c1_got_first_rising_edge := false;
else
if (not c0_got_first_rising_edge) then
if (inclk_c0'event and inclk_c0 = '1') then
if (c0_initial_count = c_initial_val(0)) then
c0_got_first_rising_edge := true;
else
c0_initial_count := c0_initial_count + 1;
end if;
end if;
elsif (inclk_c0'event) then
c0_count := c0_count + 1;
if (c0_count = (c_high_val(0) + c_low_val(0)) * 2) then
c0_count := 1;
end if;
end if;
if (inclk_c0'event and inclk_c0 = '0') then
if (c0_count = 1) then
c0_tmp := '1';
c0_got_first_rising_edge := false;
else
c0_tmp := '0';
end if;
end if;
if (not c1_got_first_rising_edge) then
if (inclk_c1'event and inclk_c1 = '1') then
if (c1_initial_count = c_initial_val(1)) then
c1_got_first_rising_edge := true;
else
c1_initial_count := c1_initial_count + 1;
end if;
end if;
elsif (inclk_c1'event) then
c1_count := c1_count + 1;
if (c1_count = (c_high_val(1) + c_low_val(1)) * 2) then
c1_count := 1;
end if;
end if;
if (inclk_c1'event and inclk_c1 = '0') then
if (c1_count = 1) then
c1_tmp := '1';
c1_got_first_rising_edge := false;
else
c1_tmp := '0';
end if;
end if;
end if;
end process;
locked <= pfd_locked WHEN (test_bypass_lock_detect = "on") ELSE
lock;
process (scandone_tmp)
variable buf : line;
begin
if (scandone_tmp'event and scandone_tmp = '1') then
if (reconfig_err = false) then
ASSERT false REPORT "PLL Reprogramming completed with the following values (Values in parantheses indicate values before reprogramming) :" severity note;
write (buf, string'(" N modulus = "));
write (buf, n_val);
write (buf, string'(" ( "));
write (buf, n_val_old);
write (buf, string'(" )"));
writeline (output, buf);
write (buf, string'(" M modulus = "));
write (buf, m_val);
write (buf, string'(" ( "));
write (buf, m_val_old);
write (buf, string'(" )"));
writeline (output, buf);
write (buf, string'(" M ph_tap = "));
write (buf, m_ph_val);
write (buf, string'(" ( "));
write (buf, m_ph_val_old);
write (buf, string'(" )"));
writeline (output, buf);
for i in 0 to (num_output_cntrs-1) loop
write (buf, clk_num(i));
write (buf, string'(" : "));
write (buf, cntrs(i));
write (buf, string'(" : high = "));
write (buf, c_high_val(i));
write (buf, string'(" ("));
write (buf, c_high_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , low = "));
write (buf, c_low_val(i));
write (buf, string'(" ("));
write (buf, c_low_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , mode = "));
write (buf, c_mode_val(i));
write (buf, string'(" ("));
write (buf, c_mode_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , phase tap = "));
write (buf, c_ph_val(i));
write (buf, string'(" ("));
write (buf, c_ph_val_old(i));
write (buf, string'(") "));
writeline(output, buf);
end loop;
IF (pll_reconfig_display_full_setting) THEN
write (buf, string'(" Charge Pump Current (uA) = "));
write (buf, cp_curr_val);
write (buf, string'(" ( "));
write (buf, cp_curr_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Capacitor (pF) = "));
write (buf, lfc_val);
write (buf, string'(" ( "));
write (buf, lfc_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Resistor (Kohm) = "));
write (buf, lfr_val);
write (buf, string'(" ( "));
write (buf, lfr_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" VCO_Post_Scale = "));
write (buf, vco_cur);
write (buf, string'(" ( "));
write (buf, vco_old);
write (buf, string'(" ) "));
writeline (output, buf);
ELSE
write (buf, string'(" Charge Pump Current (bit setting) = "));
write (buf, alt_conv_integer(cp_curr_val_bit_setting));
write (buf, string'(" ( "));
write (buf, cp_curr_old_bit_setting);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Capacitor (bit setting) = "));
write (buf, alt_conv_integer(lfc_val_bit_setting));
write (buf, string'(" ( "));
write (buf, lfc_old_bit_setting);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Resistor (bit setting) = "));
write (buf, alt_conv_integer(lfr_val_bit_setting));
write (buf, string'(" ( "));
write (buf, lfr_old_bit_setting);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" VCO_Post_Scale = "));
write (buf, vco_cur);
write (buf, string'(" ( "));
write (buf, vco_old);
write (buf, string'(" ) "));
writeline (output, buf);
END IF;
cp_curr_old_bit_setting <= alt_conv_integer(cp_curr_val_bit_setting);
lfc_old_bit_setting <= alt_conv_integer(lfc_val_bit_setting);
lfr_old_bit_setting <= alt_conv_integer(lfr_val_bit_setting);
else ASSERT false REPORT "Errors were encountered during PLL reprogramming. Please refer to error/warning messages above." severity warning;
end if;
end if;
end process;
update_conf_latches <= configupdate_ipd;
process (scandone_tmp,areset_ipd,update_conf_latches, c_clk(0), c_clk(1), c_clk(2), c_clk(3), c_clk(4), c_clk(5), c_clk(6), c_clk(7), c_clk(8), c_clk(9), vco_out, fbclk, scanclk_ipd)
variable init : boolean := true;
variable low, high : std_logic_vector(7 downto 0);
variable low_fast, high_fast : std_logic_vector(3 downto 0);
variable mode : string(1 to 6) := "bypass";
variable is_error : boolean := false;
variable m_tmp, n_tmp : std_logic_vector(8 downto 0);
variable lfr_val_tmp : string(1 to 2) := " ";
variable c_high_val_tmp,c_hval : int_array(0 to 9) := (OTHERS => 1);
variable c_low_val_tmp,c_lval : int_array(0 to 9) := (OTHERS => 1);
variable c_mode_val_tmp : str_array(0 to 9);
variable m_val_tmp : integer := 0;
variable c0_rising_edge_transfer_done : boolean := false;
variable c1_rising_edge_transfer_done : boolean := false;
variable c2_rising_edge_transfer_done : boolean := false;
variable c3_rising_edge_transfer_done : boolean := false;
variable c4_rising_edge_transfer_done : boolean := false;
variable c5_rising_edge_transfer_done : boolean := false;
variable c6_rising_edge_transfer_done : boolean := false;
variable c7_rising_edge_transfer_done : boolean := false;
variable c8_rising_edge_transfer_done : boolean := false;
variable c9_rising_edge_transfer_done : boolean := false;
-- variables for scaling of multiply_by and divide_by values
variable i_clk0_mult_by : integer := 1;
variable i_clk0_div_by : integer := 1;
variable i_clk1_mult_by : integer := 1;
variable i_clk1_div_by : integer := 1;
variable i_clk2_mult_by : integer := 1;
variable i_clk2_div_by : integer := 1;
variable i_clk3_mult_by : integer := 1;
variable i_clk3_div_by : integer := 1;
variable i_clk4_mult_by : integer := 1;
variable i_clk4_div_by : integer := 1;
variable i_clk5_mult_by : integer := 1;
variable i_clk5_div_by : integer := 1;
variable i_clk6_mult_by : integer := 1;
variable i_clk6_div_by : integer := 1;
variable i_clk7_mult_by : integer := 1;
variable i_clk7_div_by : integer := 1;
variable i_clk8_mult_by : integer := 1;
variable i_clk8_div_by : integer := 1;
variable i_clk9_mult_by : integer := 1;
variable i_clk9_div_by : integer := 1;
variable max_d_value : integer := 1;
variable new_multiplier : integer := 1;
-- internal variables for storing the phase shift number.(used in lvds mode only)
variable i_clk0_phase_shift : integer := 1;
variable i_clk1_phase_shift : integer := 1;
variable i_clk2_phase_shift : integer := 1;
-- user to advanced variables
variable max_neg_abs : integer := 0;
variable i_m_initial : integer;
variable i_m : integer := 1;
variable i_n : integer := 1;
variable i_c_high : int_array(0 to 9);
variable i_c_low : int_array(0 to 9);
variable i_c_initial : int_array(0 to 9);
variable i_c_ph : int_array(0 to 9);
variable i_c_mode : str_array(0 to 9);
variable i_m_ph : integer;
variable output_count : integer;
variable new_divisor : integer;
variable clk0_cntr : string(1 to 6) := " c0";
variable clk1_cntr : string(1 to 6) := " c1";
variable clk2_cntr : string(1 to 6) := " c2";
variable clk3_cntr : string(1 to 6) := " c3";
variable clk4_cntr : string(1 to 6) := " c4";
variable clk5_cntr : string(1 to 6) := " c5";
variable clk6_cntr : string(1 to 6) := " c6";
variable clk7_cntr : string(1 to 6) := " c7";
variable clk8_cntr : string(1 to 6) := " c8";
variable clk9_cntr : string(1 to 6) := " c9";
variable fbk_cntr : string(1 to 2);
variable fbk_cntr_index : integer;
variable start_bit : integer;
variable quiet_time : time := 0 ps;
variable slowest_clk_old : time := 0 ps;
variable slowest_clk_new : time := 0 ps;
variable i : integer := 0;
variable j : integer := 0;
variable scanread_active_edge : time := 0 ps;
variable got_first_scanclk : boolean := false;
variable scanclk_last_rising_edge : time := 0 ps;
variable current_scan_data : std_logic_vector(0 to 233) := (OTHERS => '0');
variable index : integer := 0;
variable Tviol_scandata_scanclk : std_ulogic := '0';
variable TimingData_scandata_scanclk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_scanclkena_scanclk : std_ulogic := '0';
variable TimingData_scanclkena_scanclk : VitalTimingDataType := VitalTimingDataInit;
variable scan_chain_length : integer := GPP_SCAN_CHAIN;
variable tmp_rem : integer := 0;
variable scanclk_cycles : integer := 0;
variable lfc_tmp : std_logic_vector(1 downto 0);
variable lfr_tmp : std_logic_vector(5 downto 0);
variable lfr_int : integer := 0;
variable n_hi,n_lo,m_hi,m_lo : std_logic_vector(7 downto 0);
variable buf : line;
variable buf_scan_data : STD_LOGIC_VECTOR(0 TO 1) := (OTHERS => '0');
variable buf_scan_data_2 : STD_LOGIC_VECTOR(0 TO 2) := (OTHERS => '0');
function slowest_clk (
C0 : integer; C0_mode : string(1 to 6);
C1 : integer; C1_mode : string(1 to 6);
C2 : integer; C2_mode : string(1 to 6);
C3 : integer; C3_mode : string(1 to 6);
C4 : integer; C4_mode : string(1 to 6);
C5 : integer; C5_mode : string(1 to 6);
C6 : integer; C6_mode : string(1 to 6);
C7 : integer; C7_mode : string(1 to 6);
C8 : integer; C8_mode : string(1 to 6);
C9 : integer; C9_mode : string(1 to 6);
refclk : time; m_mod : integer) return time is
variable max_modulus : integer := 1;
variable q_period : time := 0 ps;
variable refclk_int : integer := 0;
begin
if (C0_mode /= "bypass" and C0_mode /= " off") then
max_modulus := C0;
end if;
if (C1 > max_modulus and C1_mode /= "bypass" and C1_mode /= " off") then
max_modulus := C1;
end if;
if (C2 > max_modulus and C2_mode /= "bypass" and C2_mode /= " off") then
max_modulus := C2;
end if;
if (C3 > max_modulus and C3_mode /= "bypass" and C3_mode /= " off") then
max_modulus := C3;
end if;
if (C4 > max_modulus and C4_mode /= "bypass" and C4_mode /= " off") then
max_modulus := C4;
end if;
if (C5 > max_modulus and C5_mode /= "bypass" and C5_mode /= " off") then
max_modulus := C5;
end if;
if (C6 > max_modulus and C6_mode /= "bypass" and C6_mode /= " off") then
max_modulus := C6;
end if;
if (C7 > max_modulus and C7_mode /= "bypass" and C7_mode /= " off") then
max_modulus := C7;
end if;
if (C8 > max_modulus and C8_mode /= "bypass" and C8_mode /= " off") then
max_modulus := C8;
end if;
if (C9 > max_modulus and C9_mode /= "bypass" and C9_mode /= " off") then
max_modulus := C9;
end if;
refclk_int := refclk / 1 ps;
if (m_mod /= 0) then
q_period := (refclk_int * max_modulus / m_mod) * 1 ps;
end if;
return (2*q_period);
end slowest_clk;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function extract_cntr_string (arg:string) return string is
variable str : string(1 to 6) := " c0";
begin
if (arg = "c0") then
str := " c0";
elsif (arg = "c1") then
str := " c1";
elsif (arg = "c2") then
str := " c2";
elsif (arg = "c3") then
str := " c3";
elsif (arg = "c4") then
str := " c4";
elsif (arg = "c5") then
str := " c5";
elsif (arg = "c6") then
str := " c6";
elsif (arg = "c7") then
str := " c7";
elsif (arg = "c8") then
str := " c8";
elsif (arg = "c9") then
str := " c9";
else str := " c0";
end if;
return str;
end extract_cntr_string;
function extract_cntr_index (arg:string) return integer is
variable index : integer := 0;
begin
if (arg(6) = '0') then
index := 0;
elsif (arg(6) = '1') then
index := 1;
elsif (arg(6) = '2') then
index := 2;
elsif (arg(6) = '3') then
index := 3;
elsif (arg(6) = '4') then
index := 4;
elsif (arg(6) = '5') then
index := 5;
elsif (arg(6) = '6') then
index := 6;
elsif (arg(6) = '7') then
index := 7;
elsif (arg(6) = '8') then
index := 8;
else index := 9;
end if;
return index;
end extract_cntr_index;
function output_cntr_num (arg:string) return string is
variable str : string(1 to 6) := "unused";
begin
if (arg = "c0") then
str := " clk0";
elsif (arg = "c1") then
str := " clk1";
elsif (arg = "c2") then
str := " clk2";
elsif (arg = "c3") then
str := " clk3";
elsif (arg = "c4") then
str := " clk4";
elsif (arg = "c5") then
str := " clk5";
elsif (arg = "c6") then
str := " clk6";
elsif (arg = "c7") then
str := " clk7";
elsif (arg = "c8") then
str := " clk8";
elsif (arg = "c9") then
str := " clk9";
else str := "unused";
end if;
return str;
end output_cntr_num;
begin
IF (areset_ipd'EVENT AND areset_ipd = '1') then
c_ph_val <= i_c_ph;
END IF;
if (init) then
if (m = 0) then
clk9_cntr := " c9";
clk8_cntr := " c8";
clk7_cntr := " c7";
clk6_cntr := " c6";
clk5_cntr := " c5";
clk4_cntr := " c4";
clk3_cntr := " c3";
clk2_cntr := " c2";
clk1_cntr := " c1";
clk0_cntr := " c0";
else
clk9_cntr := extract_cntr_string(clk9_counter);
clk8_cntr := extract_cntr_string(clk8_counter);
clk7_cntr := extract_cntr_string(clk7_counter);
clk6_cntr := extract_cntr_string(clk6_counter);
clk5_cntr := extract_cntr_string(clk5_counter);
clk4_cntr := extract_cntr_string(clk4_counter);
clk3_cntr := extract_cntr_string(clk3_counter);
clk2_cntr := extract_cntr_string(clk2_counter);
clk1_cntr := extract_cntr_string(clk1_counter);
clk0_cntr := extract_cntr_string(clk0_counter);
end if;
clk_num(9) <= output_cntr_num(clk9_counter);
clk_num(8) <= output_cntr_num(clk8_counter);
clk_num(7) <= output_cntr_num(clk7_counter);
clk_num(6) <= output_cntr_num(clk6_counter);
clk_num(5) <= output_cntr_num(clk5_counter);
clk_num(4) <= output_cntr_num(clk4_counter);
clk_num(3) <= output_cntr_num(clk3_counter);
clk_num(2) <= output_cntr_num(clk2_counter);
clk_num(1) <= output_cntr_num(clk1_counter);
clk_num(0) <= output_cntr_num(clk0_counter);
i_clk0_counter <= extract_cntr_index(clk0_cntr);
i_clk1_counter <= extract_cntr_index(clk1_cntr);
i_clk2_counter <= extract_cntr_index(clk2_cntr);
i_clk3_counter <= extract_cntr_index(clk3_cntr);
i_clk4_counter <= extract_cntr_index(clk4_cntr);
i_clk5_counter <= extract_cntr_index(clk5_cntr);
i_clk6_counter <= extract_cntr_index(clk6_cntr);
i_clk7_counter <= extract_cntr_index(clk7_cntr);
i_clk8_counter <= extract_cntr_index(clk8_cntr);
i_clk9_counter <= extract_cntr_index(clk9_cntr);
if (m = 0) then -- convert user parameters to advanced
-- set the limit of the divide_by value that can be returned by
-- the following function.
max_d_value := 500;
-- scale down the multiply_by and divide_by values provided by the design
-- before attempting to use them in the calculations below
find_simple_integer_fraction(clk0_multiply_by, clk0_divide_by,
max_d_value, i_clk0_mult_by, i_clk0_div_by);
find_simple_integer_fraction(clk1_multiply_by, clk1_divide_by,
max_d_value, i_clk1_mult_by, i_clk1_div_by);
find_simple_integer_fraction(clk2_multiply_by, clk2_divide_by,
max_d_value, i_clk2_mult_by, i_clk2_div_by);
find_simple_integer_fraction(clk3_multiply_by, clk3_divide_by,
max_d_value, i_clk3_mult_by, i_clk3_div_by);
find_simple_integer_fraction(clk4_multiply_by, clk4_divide_by,
max_d_value, i_clk4_mult_by, i_clk4_div_by);
find_simple_integer_fraction(clk5_multiply_by, clk5_divide_by,
max_d_value, i_clk5_mult_by, i_clk5_div_by);
find_simple_integer_fraction(clk6_multiply_by, clk6_divide_by,
max_d_value, i_clk6_mult_by, i_clk6_div_by);
find_simple_integer_fraction(clk7_multiply_by, clk7_divide_by,
max_d_value, i_clk7_mult_by, i_clk7_div_by);
find_simple_integer_fraction(clk8_multiply_by, clk8_divide_by,
max_d_value, i_clk8_mult_by, i_clk8_div_by);
find_simple_integer_fraction(clk9_multiply_by, clk9_divide_by,
max_d_value, i_clk9_mult_by, i_clk9_div_by);
if (vco_frequency_control = "manual_phase") then
find_m_and_n_4_manual_phase(inclk0_input_frequency, vco_phase_shift_step,
i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,
i_clk4_mult_by,
i_clk5_mult_by,i_clk6_mult_by,
i_clk7_mult_by,i_clk8_mult_by,i_clk9_mult_by,
i_clk0_div_by, i_clk1_div_by,
i_clk2_div_by, i_clk3_div_by,
i_clk4_div_by,
i_clk5_div_by,i_clk6_div_by,
i_clk7_div_by,i_clk8_div_by,i_clk9_div_by,
clk0_counter, clk1_counter,
clk2_counter, clk3_counter,
clk4_counter,
clk5_counter,clk6_counter,
clk7_counter,clk8_counter,clk9_counter,
i_m, i_n);
elsif (((pll_type = "fast") or (pll_type = "lvds") OR (pll_type = "left_right")) and ((vco_multiply_by /= 0) and (vco_divide_by /= 0))) then
i_n := vco_divide_by;
i_m := vco_multiply_by;
else
i_n := 1;
if (((pll_type = "fast") or (pll_type = "left_right")) and (compensate_clock = "lvdsclk")) then
i_m := i_clk0_mult_by;
else
i_m := lcm (i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,
i_clk4_mult_by,
i_clk5_mult_by,i_clk6_mult_by,
i_clk7_mult_by,i_clk8_mult_by,i_clk9_mult_by,
inclk0_input_frequency);
end if;
end if;
if (pll_type = "flvds") then
-- Need to readjust phase shift values when the clock multiply value has been readjusted.
new_multiplier := clk0_multiply_by / i_clk0_mult_by;
i_clk0_phase_shift := str2int(clk0_phase_shift) * new_multiplier;
i_clk1_phase_shift := str2int(clk1_phase_shift) * new_multiplier;
i_clk2_phase_shift := str2int(clk2_phase_shift) * new_multiplier;
else
i_clk0_phase_shift := str2int(clk0_phase_shift);
i_clk1_phase_shift := str2int(clk1_phase_shift);
i_clk2_phase_shift := str2int(clk2_phase_shift);
end if;
max_neg_abs := maxnegabs(i_clk0_phase_shift,
i_clk1_phase_shift,
i_clk2_phase_shift,
str2int(clk3_phase_shift),
str2int(clk4_phase_shift),
str2int(clk5_phase_shift),
str2int(clk6_phase_shift),
str2int(clk7_phase_shift),
str2int(clk8_phase_shift),
str2int(clk9_phase_shift)
);
i_m_ph := counter_ph(get_phase_degree(max_neg_abs,inclk0_input_frequency), i_m, i_n);
i_c_ph(0) := counter_ph(get_phase_degree(ph_adjust(i_clk0_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(1) := counter_ph(get_phase_degree(ph_adjust(i_clk1_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(2) := counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(3) := counter_ph(get_phase_degree(ph_adjust(str2int(clk3_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(4) := counter_ph(get_phase_degree(ph_adjust(str2int(clk4_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(5) := counter_ph(get_phase_degree(ph_adjust(str2int(clk5_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(6) := counter_ph(get_phase_degree(ph_adjust(str2int(clk6_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(7) := counter_ph(get_phase_degree(ph_adjust(str2int(clk7_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(8) := counter_ph(get_phase_degree(ph_adjust(str2int(clk8_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(9) := counter_ph(get_phase_degree(ph_adjust(str2int(clk9_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_high(0) := counter_high(output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_high(1) := counter_high(output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_high(2) := counter_high(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_high(3) := counter_high(output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_high(4) := counter_high(output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_c_high(5) := counter_high(output_counter_value(i_clk5_div_by,
i_clk5_mult_by, i_m, i_n), clk5_duty_cycle);
i_c_high(6) := counter_high(output_counter_value(i_clk6_div_by,
i_clk6_mult_by, i_m, i_n), clk6_duty_cycle);
i_c_high(7) := counter_high(output_counter_value(i_clk7_div_by,
i_clk7_mult_by, i_m, i_n), clk7_duty_cycle);
i_c_high(8) := counter_high(output_counter_value(i_clk8_div_by,
i_clk8_mult_by, i_m, i_n), clk8_duty_cycle);
i_c_high(9) := counter_high(output_counter_value(i_clk9_div_by,
i_clk9_mult_by, i_m, i_n), clk9_duty_cycle);
i_c_low(0) := counter_low(output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_low(1) := counter_low(output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_low(2) := counter_low(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_low(3) := counter_low(output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_low(4) := counter_low(output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_c_low(5) := counter_low(output_counter_value(i_clk5_div_by,
i_clk5_mult_by, i_m, i_n), clk5_duty_cycle);
i_c_low(6) := counter_low(output_counter_value(i_clk6_div_by,
i_clk6_mult_by, i_m, i_n), clk6_duty_cycle);
i_c_low(7) := counter_low(output_counter_value(i_clk7_div_by,
i_clk7_mult_by, i_m, i_n), clk7_duty_cycle);
i_c_low(8) := counter_low(output_counter_value(i_clk8_div_by,
i_clk8_mult_by, i_m, i_n), clk8_duty_cycle);
i_c_low(9) := counter_low(output_counter_value(i_clk9_div_by,
i_clk9_mult_by, i_m, i_n), clk9_duty_cycle);
i_m_initial := counter_initial(get_phase_degree(max_neg_abs, inclk0_input_frequency), i_m,i_n);
i_c_initial(0) := counter_initial(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(1) := counter_initial(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(2) := counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(3) := counter_initial(get_phase_degree(ph_adjust(str2int(clk3_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(4) := counter_initial(get_phase_degree(ph_adjust(str2int(clk4_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(5) := counter_initial(get_phase_degree(ph_adjust(str2int(clk5_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(6) := counter_initial(get_phase_degree(ph_adjust(str2int(clk6_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(7) := counter_initial(get_phase_degree(ph_adjust(str2int(clk7_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(8) := counter_initial(get_phase_degree(ph_adjust(str2int(clk8_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(9) := counter_initial(get_phase_degree(ph_adjust(str2int(clk9_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_mode(0) := counter_mode(clk0_duty_cycle, output_counter_value(i_clk0_div_by, i_clk0_mult_by, i_m, i_n));
i_c_mode(1) := counter_mode(clk1_duty_cycle, output_counter_value(i_clk1_div_by, i_clk1_mult_by, i_m, i_n));
i_c_mode(2) := counter_mode(clk2_duty_cycle, output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n));
i_c_mode(3) := counter_mode(clk3_duty_cycle, output_counter_value(i_clk3_div_by, i_clk3_mult_by, i_m, i_n));
i_c_mode(4) := counter_mode(clk4_duty_cycle, output_counter_value(i_clk4_div_by, i_clk4_mult_by, i_m, i_n));
i_c_mode(5) := counter_mode(clk5_duty_cycle, output_counter_value(i_clk5_div_by, i_clk5_mult_by, i_m, i_n));
i_c_mode(6) := counter_mode(clk6_duty_cycle, output_counter_value(i_clk6_div_by, i_clk6_mult_by, i_m, i_n));
i_c_mode(7) := counter_mode(clk7_duty_cycle, output_counter_value(i_clk7_div_by, i_clk7_mult_by, i_m, i_n));
i_c_mode(8) := counter_mode(clk8_duty_cycle, output_counter_value(i_clk8_div_by, i_clk8_mult_by, i_m, i_n));
i_c_mode(9) := counter_mode(clk9_duty_cycle, output_counter_value(i_clk9_div_by, i_clk9_mult_by, i_m, i_n));
else -- m /= 0
i_n := n;
i_m := m;
i_m_initial := m_initial;
i_m_ph := m_ph;
i_c_ph(0) := c0_ph;
i_c_ph(1) := c1_ph;
i_c_ph(2) := c2_ph;
i_c_ph(3) := c3_ph;
i_c_ph(4) := c4_ph;
i_c_ph(5) := c5_ph;
i_c_ph(6) := c6_ph;
i_c_ph(7) := c7_ph;
i_c_ph(8) := c8_ph;
i_c_ph(9) := c9_ph;
i_c_high(0) := c0_high;
i_c_high(1) := c1_high;
i_c_high(2) := c2_high;
i_c_high(3) := c3_high;
i_c_high(4) := c4_high;
i_c_high(5) := c5_high;
i_c_high(6) := c6_high;
i_c_high(7) := c7_high;
i_c_high(8) := c8_high;
i_c_high(9) := c9_high;
i_c_low(0) := c0_low;
i_c_low(1) := c1_low;
i_c_low(2) := c2_low;
i_c_low(3) := c3_low;
i_c_low(4) := c4_low;
i_c_low(5) := c5_low;
i_c_low(6) := c6_low;
i_c_low(7) := c7_low;
i_c_low(8) := c8_low;
i_c_low(9) := c9_low;
i_c_initial(0) := c0_initial;
i_c_initial(1) := c1_initial;
i_c_initial(2) := c2_initial;
i_c_initial(3) := c3_initial;
i_c_initial(4) := c4_initial;
i_c_initial(5) := c5_initial;
i_c_initial(6) := c6_initial;
i_c_initial(7) := c7_initial;
i_c_initial(8) := c8_initial;
i_c_initial(9) := c9_initial;
i_c_mode(0) := translate_string(c0_mode);
i_c_mode(1) := translate_string(c1_mode);
i_c_mode(2) := translate_string(c2_mode);
i_c_mode(3) := translate_string(c3_mode);
i_c_mode(4) := translate_string(c4_mode);
i_c_mode(5) := translate_string(c5_mode);
i_c_mode(6) := translate_string(c6_mode);
i_c_mode(7) := translate_string(c7_mode);
i_c_mode(8) := translate_string(c8_mode);
i_c_mode(9) := translate_string(c9_mode);
end if; -- user to advanced conversion.
m_initial_val <= i_m_initial;
n_val <= i_n;
m_val <= i_m;
if (i_m = 1) then
m_mode_val <= "bypass";
else
m_mode_val <= " ";
end if;
if (i_n = 1) then
n_mode_val <= "bypass";
else
n_mode_val <= " ";
end if;
m_ph_val <= i_m_ph;
m_ph_initial <= i_m_ph;
m_val_tmp := i_m;
for i in 0 to 9 loop
if (i_c_mode(i) = "bypass") then
if (pll_type = "fast" or pll_type = "lvds" OR (pll_type = "left_right")) then
i_c_high(i) := 16;
i_c_low(i) := 16;
else
i_c_high(i) := 256;
i_c_low(i) := 256;
end if;
end if;
c_ph_val(i) <= i_c_ph(i);
c_initial_val(i) <= i_c_initial(i);
c_high_val(i) <= i_c_high(i);
c_low_val(i) <= i_c_low(i);
c_mode_val(i) <= i_c_mode(i);
c_high_val_tmp(i) := i_c_high(i);
c_hval(i) := i_c_high(i);
c_low_val_tmp(i) := i_c_low(i);
c_lval(i) := i_c_low(i);
c_mode_val_tmp(i) := i_c_mode(i);
c_ph_val_orig(i) <= i_c_ph(i);
c_high_val_hold(i) <= i_c_high(i);
c_low_val_hold(i) <= i_c_low(i);
c_mode_val_hold(i) <= i_c_mode(i);
end loop;
if (pll_type = "fast" OR (pll_type = "left_right")) then
scan_chain_length := FAST_SCAN_CHAIN;
else
scan_chain_length := GPP_SCAN_CHAIN;
end if;
if (pll_type = "fast" or pll_type = "lvds" OR (pll_type = "left_right")) then
num_output_cntrs <= 7;
else
num_output_cntrs <= 10;
end if;
init := false;
elsif (scandone_tmp'EVENT AND scandone_tmp = '1') then
c0_rising_edge_transfer_done := false;
c1_rising_edge_transfer_done := false;
c2_rising_edge_transfer_done := false;
c3_rising_edge_transfer_done := false;
c4_rising_edge_transfer_done := false;
c5_rising_edge_transfer_done := false;
c6_rising_edge_transfer_done := false;
c7_rising_edge_transfer_done := false;
c8_rising_edge_transfer_done := false;
c9_rising_edge_transfer_done := false;
update_conf_latches_reg <= '0';
elsif (update_conf_latches'event and update_conf_latches = '1') then
initiate_reconfig <= '1';
elsif (areset_ipd'event AND areset_ipd = '1') then
if (scandone_tmp = '0') then scandone_tmp <= '1' AFTER scanclk_period; end if;
elsif (scanclk_ipd'event and scanclk_ipd = '1') then
IF (initiate_reconfig = '1') THEN
initiate_reconfig <= '0';
ASSERT false REPORT "PLL Reprogramming Initiated" severity note;
update_conf_latches_reg <= update_conf_latches;
reconfig_err <= false;
scandone_tmp <= '0';
cp_curr_old <= cp_curr_val;
lfc_old <= lfc_val;
lfr_old <= lfr_val;
vco_old <= vco_cur;
-- LF unused : bit 0,1
-- LF Capacitance : bits 2,3 : all values are legal
buf_scan_data := scan_data(2 TO 3);
IF ((pll_type = "fast") OR (pll_type = "lvds") OR (pll_type = "left_right")) THEN
lfc_val <= fpll_loop_filter_c_arr(alt_conv_integer(buf_scan_data));
ELSE
lfc_val <= loop_filter_c_arr(alt_conv_integer(buf_scan_data));
END IF;
-- LF Resistance : bits 4-8
-- valid values - 00000,00100,10000,10100,11000,11011,11100,11110
IF (scan_data(4 TO 8) = "00000") THEN
lfr_val <= "20";
ELSIF (scan_data(4 TO 8) = "00100") THEN
lfr_val <= "16";
ELSIF (scan_data(4 TO 8) = "10000") THEN
lfr_val <= "12";
ELSIF (scan_data(4 TO 8) = "10100") THEN
lfr_val <= "08";
ELSIF (scan_data(4 TO 8) = "11000") THEN
lfr_val <= "06";
ELSIF (scan_data(4 TO 8) = "11011") THEN
lfr_val <= "04";
ELSIF (scan_data(4 TO 8) = "11100") THEN
lfr_val <= "02";
ELSE
lfr_val <= "01";
END IF;
-- VCO post scale assignment
if (scan_data(9) = '1') then -- vco_post_scale = 1
i_vco_max <= vco_max/2;
i_vco_min <= vco_min/2;
vco_cur <= 1;
else
i_vco_max <= vco_max;
i_vco_min <= vco_min;
vco_cur <= 2;
end if;
-- CP
-- Bit 9 : CRBYPASS
-- Bit 10-14 : unused
-- Bits 15-17 : all values are legal
buf_scan_data_2 := scan_data(15 TO 17);
cp_curr_val <= charge_pump_curr_arr(alt_conv_integer(buf_scan_data_2));
-- save old values for display info.
cp_curr_val_bit_setting <= scan_data(15 TO 17);
lfc_val_bit_setting <= scan_data(2 TO 3);
lfr_val_bit_setting <= scan_data(4 TO 8);
m_val_old <= m_val;
n_val_old <= n_val;
m_mode_val_old <= m_mode_val;
n_mode_val_old <= n_mode_val;
WHILE (i < num_output_cntrs) LOOP
c_high_val_old(i) <= c_high_val(i);
c_low_val_old(i) <= c_low_val(i);
c_mode_val_old(i) <= c_mode_val(i);
i := i + 1;
END LOOP;
-- M counter
-- 1. Mode - bypass (bit 18)
IF (scan_data(18) = '1') THEN
m_mode_val <= "bypass";
-- 3. Mode - odd/even (bit 27)
ELSIF (scan_data(27) = '1') THEN
m_mode_val <= " odd";
ELSE
m_mode_val <= " even";
END IF;
-- 2. High (bit 19-26)
m_hi := scan_data(19 TO 26);
-- 4. Low (bit 28-35)
m_lo := scan_data(28 TO 35);
-- N counter
-- 1. Mode - bypass (bit 36)
IF (scan_data(36) = '1') THEN
n_mode_val <= "bypass";
-- 3. Mode - odd/even (bit 45)
ELSIF (scan_data(45) = '1') THEN
n_mode_val <= " odd";
ELSE
n_mode_val <= " even";
END IF;
-- 2. High (bit 37-44)
n_hi := scan_data(37 TO 44);
-- 4. Low (bit 46-53)
n_lo := scan_data(46 TO 53);
-- C counters (start bit 54) bit 1:mode(bypass),bit 2-9:high,bit 10:mode(odd/even),bit 11-18:low
i := 0;
WHILE (i < num_output_cntrs) LOOP
-- 1. Mode - bypass
IF (scan_data(54 + i * 18 + 0) = '1') THEN
c_mode_val_tmp(i) := "bypass";
-- 3. Mode - odd/even
ELSIF (scan_data(54 + i * 18 + 9) = '1') THEN
c_mode_val_tmp(i) := " odd";
ELSE
c_mode_val_tmp(i) := " even";
END IF;
-- 2. Hi
high := scan_data(54 + i * 18 + 1 TO 54 + i * 18 + 8);
c_hval(i) := alt_conv_integer(high);
IF (c_hval(i) /= 0) THEN
c_high_val_tmp(i) := c_hval(i);
ELSE
c_high_val_tmp(i) := alt_conv_integer("000000001");
END IF;
-- 4. Low
low := scan_data(54 + i * 18 + 10 TO 54 + i * 18 + 17);
c_lval(i) := alt_conv_integer(low);
IF (c_lval(i) /= 0) THEN
c_low_val_tmp(i) := c_lval(i);
ELSE
c_low_val_tmp(i) := alt_conv_integer("000000001");
END IF;
i := i + 1;
END LOOP;
-- Legality Checks
-- M counter value
IF(scan_data(18) /= '1') THEN
IF ((m_hi /= m_lo) and (scan_data(27) /= '1')) THEN
reconfig_err <= TRUE;
WRITE(buf,string'("Warning : The M counter of the " & family_name & " Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work"));
writeline(output, buf);
ELSIF (m_hi /= "00000000") THEN
m_val_tmp := alt_conv_integer(m_hi) + alt_conv_integer(m_lo);
ELSE
m_val_tmp := alt_conv_integer("000000001");
END IF;
ELSE
m_val_tmp := alt_conv_integer("10000000");
END IF;
-- N counter value
IF(scan_data(36) /= '1') THEN
IF ((n_hi /= n_lo)and (scan_data(45) /= '1')) THEN
reconfig_err <= TRUE;
WRITE(buf,string'("Warning : The N counter of the " & family_name & " Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work"));
writeline(output, buf);
ELSIF (n_hi /= "00000000") THEN
n_val <= alt_conv_integer(n_hi) + alt_conv_integer(n_lo);
ELSE
n_val <= alt_conv_integer("000000001");
END IF;
ELSE
n_val <= alt_conv_integer("10000000");
END IF;
-- TODO : Give warnings/errors in the following cases?
-- 1. Illegal counter values (error)
-- 2. Change of mode (warning)
-- 3. Only 50% duty cycle allowed for M counter (odd mode - hi-lo=1,even - hi-lo=0)
END IF;
end if;
if (fbclk'event and fbclk = '1') then
m_val <= m_val_tmp;
end if;
if (update_conf_latches_reg = '1') then
if (scanclk_ipd'event and scanclk_ipd = '1') then
c0_rising_edge_transfer_done := true;
c_high_val(0) <= c_high_val_tmp(0);
c_mode_val(0) <= c_mode_val_tmp(0);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c1_rising_edge_transfer_done := true;
c_high_val(1) <= c_high_val_tmp(1);
c_mode_val(1) <= c_mode_val_tmp(1);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c2_rising_edge_transfer_done := true;
c_high_val(2) <= c_high_val_tmp(2);
c_mode_val(2) <= c_mode_val_tmp(2);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(3) <= c_high_val_tmp(3);
c_mode_val(3) <= c_mode_val_tmp(3);
c3_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(4) <= c_high_val_tmp(4);
c_mode_val(4) <= c_mode_val_tmp(4);
c4_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(5) <= c_high_val_tmp(5);
c_mode_val(5) <= c_mode_val_tmp(5);
c5_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(6) <= c_high_val_tmp(6);
c_mode_val(6) <= c_mode_val_tmp(6);
c6_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(7) <= c_high_val_tmp(7);
c_mode_val(7) <= c_mode_val_tmp(7);
c7_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(8) <= c_high_val_tmp(8);
c_mode_val(8) <= c_mode_val_tmp(8);
c8_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(9) <= c_high_val_tmp(9);
c_mode_val(9) <= c_mode_val_tmp(9);
c9_rising_edge_transfer_done := true;
end if;
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c0_rising_edge_transfer_done) then
c_low_val(0) <= c_low_val_tmp(0);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c1_rising_edge_transfer_done) then
c_low_val(1) <= c_low_val_tmp(1);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c2_rising_edge_transfer_done) then
c_low_val(2) <= c_low_val_tmp(2);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c3_rising_edge_transfer_done) then
c_low_val(3) <= c_low_val_tmp(3);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c4_rising_edge_transfer_done) then
c_low_val(4) <= c_low_val_tmp(4);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c5_rising_edge_transfer_done) then
c_low_val(5) <= c_low_val_tmp(5);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c6_rising_edge_transfer_done) then
c_low_val(6) <= c_low_val_tmp(6);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c7_rising_edge_transfer_done) then
c_low_val(7) <= c_low_val_tmp(7);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c8_rising_edge_transfer_done) then
c_low_val(8) <= c_low_val_tmp(8);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c9_rising_edge_transfer_done) then
c_low_val(9) <= c_low_val_tmp(9);
end if;
if (update_phase = '1') then
if (vco_out(0)'event and vco_out(0) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 0) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 0) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(1)'event and vco_out(1) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 1) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 1) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(2)'event and vco_out(2) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 2) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 2) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(3)'event and vco_out(3) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 3) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 3) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(4)'event and vco_out(4) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 4) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 4) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(5)'event and vco_out(5) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 5) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 5) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(6)'event and vco_out(6) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 6) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 6) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(7)'event and vco_out(7) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 7) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 7) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
end if;
if (vco_out(0)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 0) then
inclk_c_from_vco(i) <= vco_out(0);
end if;
end loop;
if (m_ph_val = 0) then
inclk_m_from_vco <= vco_out(0);
end if;
end if;
if (vco_out(1)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 1) then
inclk_c_from_vco(i) <= vco_out(1);
end if;
end loop;
if (m_ph_val = 1) then
inclk_m_from_vco <= vco_out(1);
end if;
end if;
if (vco_out(2)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 2) then
inclk_c_from_vco(i) <= vco_out(2);
end if;
end loop;
if (m_ph_val = 2) then
inclk_m_from_vco <= vco_out(2);
end if;
end if;
if (vco_out(3)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 3) then
inclk_c_from_vco(i) <= vco_out(3);
end if;
end loop;
if (m_ph_val = 3) then
inclk_m_from_vco <= vco_out(3);
end if;
end if;
if (vco_out(4)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 4) then
inclk_c_from_vco(i) <= vco_out(4);
end if;
end loop;
if (m_ph_val = 4) then
inclk_m_from_vco <= vco_out(4);
end if;
end if;
if (vco_out(5)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 5) then
inclk_c_from_vco(i) <= vco_out(5);
end if;
end loop;
if (m_ph_val = 5) then
inclk_m_from_vco <= vco_out(5);
end if;
end if;
if (vco_out(6)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 6) then
inclk_c_from_vco(i) <= vco_out(6);
end if;
end loop;
if (m_ph_val = 6) then
inclk_m_from_vco <= vco_out(6);
end if;
end if;
if (vco_out(7)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 7) then
inclk_c_from_vco(i) <= vco_out(7);
end if;
end loop;
if (m_ph_val = 7) then
inclk_m_from_vco <= vco_out(7);
end if;
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_scandata_scanclk,
TimingData => TimingData_scandata_scanclk,
TestSignal => scandata_ipd,
TestSignalName => "scandata",
RefSignal => scanclk_ipd,
RefSignalName => "scanclk",
SetupHigh => tsetup_scandata_scanclk_noedge_negedge,
SetupLow => tsetup_scandata_scanclk_noedge_negedge,
HoldHigh => thold_scandata_scanclk_noedge_negedge,
HoldLow => thold_scandata_scanclk_noedge_negedge,
CheckEnabled => TRUE,
RefTransition => '\',
HeaderMsg => InstancePath & "/stratixiii_pll",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_scanclkena_scanclk,
TimingData => TimingData_scanclkena_scanclk,
TestSignal => scanclkena_ipd,
TestSignalName => "scanclkena",
RefSignal => scanclk_ipd,
RefSignalName => "scanclk",
SetupHigh => tsetup_scanclkena_scanclk_noedge_negedge,
SetupLow => tsetup_scanclkena_scanclk_noedge_negedge,
HoldHigh => thold_scanclkena_scanclk_noedge_negedge,
HoldLow => thold_scanclkena_scanclk_noedge_negedge,
CheckEnabled => TRUE,
RefTransition => '\',
HeaderMsg => InstancePath & "/stratixiii_pll",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (scanclk_ipd'event AND scanclk_ipd = '0' AND now > 0 ps) then
scanclkena_reg <= scanclkena_ipd;
if (scanclkena_reg = '1') then
scandata_in <= scandata_ipd;
scandata_out <= scandataout_tmp;
end if;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1' and now > 0 ps) then
if (got_first_scanclk) then
scanclk_period <= now - scanclk_last_rising_edge;
else
got_first_scanclk := true;
end if;
if (scanclkena_reg = '1') then
for j in scan_chain_length - 1 downto 1 loop
scan_data(j) <= scan_data(j-1);
end loop;
scan_data(0) <= scandata_in;
end if;
scanclk_last_rising_edge := now;
end if;
end process;
-- PLL Phase Reconfiguration
PROCESS(scanclk_ipd, areset_ipd,phasestep_ipd)
VARIABLE i : INTEGER := 0;
VARIABLE c_ph : INTEGER := 0;
VARIABLE m_ph : INTEGER := 0;
VARIABLE select_counter : INTEGER := 0;
BEGIN
IF (NOW = 0 ps) THEN
m_ph_val_tmp <= m_ph_initial;
END IF;
-- Latch phase enable (same as phasestep) on neg edge of scan clock
IF (scanclk_ipd'EVENT AND scanclk_ipd = '0') THEN
phasestep_reg <= phasestep_ipd;
END IF;
IF (phasestep_ipd'EVENT and phasestep_ipd = '1') THEN
IF (update_phase = '0') THEN
phasestep_high_count <= 0; -- phase adjustments must be 1 cycle apart
-- if not, next phasestep cycle is skipped
END IF;
END IF;
-- revert counter phase tap values to POF programmed values
-- if PLL is reset
IF (areset_ipd'EVENT AND areset_ipd = '1') then
c_ph_val_tmp <= c_ph_val_orig;
m_ph_val_tmp <= m_ph_initial;
END IF;
IF (scanclk_ipd'EVENT AND scanclk_ipd = '1') THEN
IF (phasestep_reg = '1') THEN
IF (phasestep_high_count = 1) THEN
phasecounterselect_reg <= phasecounterselect_ipd;
phaseupdown_reg <= phaseupdown_ipd;
-- start reconfiguration
IF (phasecounterselect_ipd < "1100") THEN -- no counters selected
IF (phasecounterselect_ipd = "0000") THEN
i := 0;
WHILE (i < num_output_cntrs) LOOP
c_ph := c_ph_val(i);
IF (phaseupdown_ipd = '1') THEN
c_ph := (c_ph + 1) mod num_phase_taps;
ELSIF (c_ph = 0) THEN
c_ph := num_phase_taps - 1;
ELSE
c_ph := (c_ph - 1) mod num_phase_taps;
END IF;
c_ph_val_tmp(i) <= c_ph;
i := i + 1;
END LOOP;
ELSIF (phasecounterselect_ipd = "0001") THEN
m_ph := m_ph_val;
IF (phaseupdown_ipd = '1') THEN
m_ph := (m_ph + 1) mod num_phase_taps;
ELSIF (m_ph = 0) THEN
m_ph := num_phase_taps - 1;
ELSE
m_ph := (m_ph - 1) mod num_phase_taps;
END IF;
m_ph_val_tmp <= m_ph;
ELSE
select_counter := alt_conv_integer(phasecounterselect_ipd) - 2;
c_ph := c_ph_val(select_counter);
IF (phaseupdown_ipd = '1') THEN
c_ph := (c_ph + 1) mod num_phase_taps;
ELSIF (c_ph = 0) THEN
c_ph := num_phase_taps - 1;
ELSE
c_ph := (c_ph - 1) mod num_phase_taps;
END IF;
c_ph_val_tmp(select_counter) <= c_ph;
END IF;
update_phase <= '1','0' AFTER (0.5 * scanclk_period);
END IF;
END IF;
phasestep_high_count <= phasestep_high_count + 1;
END IF;
END IF;
END PROCESS;
scandataout_tmp <= scan_data(FAST_SCAN_CHAIN-2) when (pll_type = "fast" or pll_type = "lvds" or pll_type = "left_right") else scan_data(GPP_SCAN_CHAIN-2);
process (schedule_vco, areset_ipd, pfdena_ipd, refclk, fbclk)
variable sched_time : time := 0 ps;
TYPE time_array is ARRAY (0 to 7) of time;
variable init : boolean := true;
variable refclk_period : time;
variable m_times_vco_period : time;
variable new_m_times_vco_period : time;
variable phase_shift : time_array := (OTHERS => 0 ps);
variable last_phase_shift : time_array := (OTHERS => 0 ps);
variable l_index : integer := 1;
variable cycle_to_adjust : integer := 0;
variable stop_vco : boolean := false;
variable locked_tmp : std_logic := '0';
variable pll_is_locked : boolean := false;
variable cycles_pfd_low : integer := 0;
variable cycles_pfd_high : integer := 0;
variable cycles_to_lock : integer := 0;
variable cycles_to_unlock : integer := 0;
variable got_first_refclk : boolean := false;
variable got_second_refclk : boolean := false;
variable got_first_fbclk : boolean := false;
variable refclk_time : time := 0 ps;
variable fbclk_time : time := 0 ps;
variable first_fbclk_time : time := 0 ps;
variable fbclk_period : time := 0 ps;
variable first_schedule : boolean := true;
variable vco_val : std_logic := '0';
variable vco_period_was_phase_adjusted : boolean := false;
variable phase_adjust_was_scheduled : boolean := false;
variable loop_xplier : integer;
variable loop_initial : integer := 0;
variable loop_ph : integer := 0;
variable loop_time_delay : integer := 0;
variable initial_delay : time := 0 ps;
variable vco_per : time;
variable tmp_rem : integer;
variable my_rem : integer;
variable fbk_phase : integer := 0;
variable pull_back_M : integer := 0;
variable total_pull_back : integer := 0;
variable fbk_delay : integer := 0;
variable offset : time := 0 ps;
variable tmp_vco_per : integer := 0;
variable high_time : time;
variable low_time : time;
variable got_refclk_posedge : boolean := false;
variable got_fbclk_posedge : boolean := false;
variable inclk_out_of_range : boolean := false;
variable no_warn : boolean := false;
variable ext_fbk_cntr_modulus : integer := 1;
variable init_clks : boolean := true;
variable pll_is_in_reset : boolean := false;
variable buf : line;
begin
if (init) then
-- jump-start the VCO
-- add 1 ps delay to ensure all signals are updated to initial
-- values
schedule_vco <= transport not schedule_vco after 1 ps;
init := false;
end if;
if (schedule_vco'event) then
if (init_clks) then
refclk_period := inclk0_input_frequency * n_val * 1 ps;
m_times_vco_period := refclk_period;
new_m_times_vco_period := refclk_period;
init_clks := false;
end if;
sched_time := 0 ps;
for i in 0 to 7 loop
last_phase_shift(i) := phase_shift(i);
end loop;
cycle_to_adjust := 0;
l_index := 1;
m_times_vco_period := new_m_times_vco_period;
end if;
-- areset was asserted
if (areset_ipd'event and areset_ipd = '1') then
assert false report family_name & " PLL was reset" severity note;
-- reset lock parameters
pll_is_locked := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
end if;
if (schedule_vco'event and (areset_ipd = '1' or stop_vco)) then
if (areset_ipd = '1') then
pll_is_in_reset := true;
got_first_refclk := false;
got_second_refclk := false;
end if;
-- drop VCO taps to 0
for i in 0 to 7 loop
vco_out(i) <= transport '0' after last_phase_shift(i);
phase_shift(i) := 0 ps;
last_phase_shift(i) := 0 ps;
end loop;
-- reset lock parameters
pll_is_locked := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
got_first_refclk := false;
got_second_refclk := false;
refclk_time := 0 ps;
got_first_fbclk := false;
fbclk_time := 0 ps;
first_fbclk_time := 0 ps;
fbclk_period := 0 ps;
first_schedule := true;
vco_val := '0';
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
elsif ((schedule_vco'event or areset_ipd'event) and areset_ipd = '0' and (not stop_vco) and now > 0 ps) then
-- note areset deassert time
-- note it as refclk_time to prevent false triggering
-- of stop_vco after areset
if (areset_ipd'event and areset_ipd = '0' and pll_is_in_reset) then
refclk_time := now;
pll_is_in_reset := false;
locked_tmp := '0';
end if;
-- calculate loop_xplier : this will be different from m_val
-- in external_feedback_mode
loop_xplier := m_val;
loop_initial := m_initial_val - 1;
loop_ph := m_ph_val;
-- convert initial value to delay
initial_delay := (loop_initial * m_times_vco_period)/loop_xplier;
-- convert loop ph_tap to delay
my_rem := (m_times_vco_period/1 ps) rem loop_xplier;
tmp_vco_per := (m_times_vco_period/1 ps) / loop_xplier;
if (my_rem /= 0) then
tmp_vco_per := tmp_vco_per + 1;
end if;
fbk_phase := (loop_ph * tmp_vco_per)/8;
pull_back_M := initial_delay/1 ps + fbk_phase;
total_pull_back := pull_back_M;
if (simulation_type = "timing") then
total_pull_back := total_pull_back + pll_compensation_delay;
end if;
while (total_pull_back > refclk_period/1 ps) loop
total_pull_back := total_pull_back - refclk_period/1 ps;
end loop;
if (total_pull_back > 0) then
offset := refclk_period - (total_pull_back * 1 ps);
end if;
fbk_delay := total_pull_back - fbk_phase;
if (fbk_delay < 0) then
offset := offset - (fbk_phase * 1 ps);
fbk_delay := total_pull_back;
end if;
-- assign m_delay
m_delay <= transport fbk_delay after 1 ps;
my_rem := (m_times_vco_period/1 ps) rem loop_xplier;
for i in 1 to loop_xplier loop
-- adjust cycles
tmp_vco_per := (m_times_vco_period/1 ps)/loop_xplier;
if (my_rem /= 0 and l_index <= my_rem) then
tmp_rem := (loop_xplier * l_index) rem my_rem;
cycle_to_adjust := (loop_xplier * l_index) / my_rem;
if (tmp_rem /= 0) then
cycle_to_adjust := cycle_to_adjust + 1;
end if;
end if;
if (cycle_to_adjust = i) then
tmp_vco_per := tmp_vco_per + 1;
l_index := l_index + 1;
end if;
-- calculate high and low periods
vco_per := tmp_vco_per * 1 ps;
high_time := (tmp_vco_per/2) * 1 ps;
if (tmp_vco_per rem 2 /= 0) then
high_time := high_time + 1 ps;
end if;
low_time := vco_per - high_time;
-- schedule the rising and falling edges
for j in 1 to 2 loop
vco_val := not vco_val;
if (vco_val = '0') then
sched_time := sched_time + high_time;
elsif (vco_val = '1') then
sched_time := sched_time + low_time;
end if;
-- schedule the phase taps
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
if (first_schedule) then
vco_out(k) <= transport vco_val after (sched_time + phase_shift(k));
else
vco_out(k) <= transport vco_val after (sched_time + last_phase_shift(k));
end if;
end loop;
end loop;
end loop;
-- schedule once more
if (first_schedule) then
vco_val := not vco_val;
if (vco_val = '0') then
sched_time := sched_time + high_time;
elsif (vco_val = '1') then
sched_time := sched_time + low_time;
end if;
-- schedule the phase taps
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
vco_out(k) <= transport vco_val after (sched_time + phase_shift(k));
end loop;
first_schedule := false;
end if;
schedule_vco <= transport not schedule_vco after sched_time;
if (vco_period_was_phase_adjusted) then
m_times_vco_period := refclk_period;
new_m_times_vco_period := refclk_period;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := true;
vco_per := m_times_vco_period/loop_xplier;
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
end loop;
end if;
end if;
-- Bypass lock detect
if (refclk'event and refclk = '1' and areset_ipd = '0') then
if (test_bypass_lock_detect = "on") then
if (pfdena_ipd = '1') then
cycles_pfd_low := 0;
if (pfd_locked = '0') then
if (cycles_pfd_high = lock_high) then
assert false report family_name & " PLL locked in test mode on PFD enable assertion." severity warning;
pfd_locked <= '1';
end if;
cycles_pfd_high := cycles_pfd_high + 1;
end if;
end if;
if (pfdena_ipd = '0') then
cycles_pfd_high := 0;
if (pfd_locked = '1') then
if (cycles_pfd_low = lock_low) then
assert false report family_name & " PLL lost lock in test mode on PFD enable de-assertion." severity warning;
pfd_locked <= '0';
end if;
cycles_pfd_low := cycles_pfd_low + 1;
end if;
end if;
end if;
if (refclk'event and refclk = '1' and areset_ipd = '0') then
got_refclk_posedge := true;
if (not got_first_refclk) then
got_first_refclk := true;
else
got_second_refclk := true;
refclk_period := now - refclk_time;
-- check if incoming freq. will cause VCO range to be
-- exceeded
if ( (i_vco_max /= 0 and i_vco_min /= 0 and pfdena_ipd = '1') and
(((refclk_period/1 ps)/loop_xplier > i_vco_max) or
((refclk_period/1 ps)/loop_xplier < i_vco_min)) ) then
if (pll_is_locked) then
if ((refclk_period/1 ps)/loop_xplier > i_vco_max) then
assert false report "Input clock freq. is over VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_over <= '1';
end if;
if ((refclk_period/1 ps)/loop_xplier < i_vco_min) then
assert false report "Input clock freq. is under VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_under <= '1';
end if;
if (inclk_out_of_range) then
pll_is_locked := false;
locked_tmp := '0';
cycles_to_lock := 0;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
assert false report family_name & " PLL lost lock." severity note;
end if;
elsif (not no_warn) then
if ((refclk_period/1 ps)/loop_xplier > i_vco_max) then
assert false report "Input clock freq. is over VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_over <= '1';
end if;
if ((refclk_period/1 ps)/loop_xplier < i_vco_min) then
assert false report "Input clock freq. is under VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_under <= '1';
end if;
assert false report " Input clock freq. is not within VCO range : " & family_name & " PLL may not lock. Please use the correct frequency." severity warning;
no_warn := true;
end if;
inclk_out_of_range := true;
else
vco_over <= '0';
vco_under <= '0';
inclk_out_of_range := false;
no_warn := false;
end if;
end if;
end if;
if (stop_vco) then
stop_vco := false;
schedule_vco <= not schedule_vco;
end if;
refclk_time := now;
else
got_refclk_posedge := false;
end if;
-- Update M counter value on feedback clock edge
if (fbclk'event and fbclk = '1') then
got_fbclk_posedge := true;
if (not got_first_fbclk) then
got_first_fbclk := true;
else
fbclk_period := now - fbclk_time;
end if;
-- need refclk_period here, so initialized to proper value above
if ( ( (now - refclk_time > 1.5 * refclk_period) and pfdena_ipd = '1' and pll_is_locked) or
( (now - refclk_time > 5 * refclk_period) and pfdena_ipd = '1' and pll_has_just_been_reconfigured = false) or
( (now - refclk_time > 50 * refclk_period) and pfdena_ipd = '1' and pll_has_just_been_reconfigured = true) ) then
stop_vco := true;
-- reset
got_first_refclk := false;
got_first_fbclk := false;
got_second_refclk := false;
if (pll_is_locked) then
pll_is_locked := false;
locked_tmp := '0';
assert false report family_name & " PLL lost lock due to loss of input clock or the input clock is not detected within the allowed time frame." severity note;
if ((i_vco_max = 0) and (i_vco_min = 0)) then
assert false report "Please run timing simulation to check whether the input clock is operating within the supported VCO range or not." severity note;
end if;
end if;
cycles_to_lock := 0;
cycles_to_unlock := 0;
first_schedule := true;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
end if;
fbclk_time := now;
else
got_fbclk_posedge := false;
end if;
if ((got_refclk_posedge or got_fbclk_posedge) and got_second_refclk and pfdena_ipd = '1' and (not inclk_out_of_range)) then
-- now we know actual incoming period
if ( abs(fbclk_time - refclk_time) <= 5 ps or
(got_first_fbclk and abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5 ps)) then
-- considered in phase
if (cycles_to_lock = real_lock_high) then
if (not pll_is_locked) then
assert false report family_name & " PLL locked to incoming clock" severity note;
end if;
pll_is_locked := true;
locked_tmp := '1';
cycles_to_unlock := 0;
end if;
-- increment lock counter only if second part of above
-- time check is NOT true
if (not(abs(refclk_period - abs(fbclk_time - refclk_time)) <= lock_window)) then
cycles_to_lock := cycles_to_lock + 1;
end if;
-- adjust m_times_vco_period
new_m_times_vco_period := refclk_period;
else
-- if locked, begin unlock
if (pll_is_locked) then
cycles_to_unlock := cycles_to_unlock + 1;
if (cycles_to_unlock = lock_low) then
pll_is_locked := false;
locked_tmp := '0';
cycles_to_lock := 0;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
assert false report family_name & " PLL lost lock." severity note;
got_first_refclk := false;
got_first_fbclk := false;
got_second_refclk := false;
end if;
end if;
if ( abs(refclk_period - fbclk_period) <= 2 ps ) then
-- frequency is still good
if (now = fbclk_time and (not phase_adjust_was_scheduled)) then
if ( abs(fbclk_time - refclk_time) > refclk_period/2) then
new_m_times_vco_period := m_times_vco_period + (refclk_period - abs(fbclk_time - refclk_time));
vco_period_was_phase_adjusted := true;
else
new_m_times_vco_period := m_times_vco_period - abs(fbclk_time - refclk_time);
vco_period_was_phase_adjusted := true;
end if;
end if;
else
phase_adjust_was_scheduled := false;
new_m_times_vco_period := refclk_period;
end if;
end if;
end if;
if (pfdena_ipd = '0') then
if (pll_is_locked) then
locked_tmp := 'X';
end if;
pll_is_locked := false;
cycles_to_lock := 0;
end if;
-- give message only at time of deassertion
if (pfdena_ipd'event and pfdena_ipd = '0') then
assert false report "PFDENA deasserted." severity note;
elsif (pfdena_ipd'event and pfdena_ipd = '1') then
got_first_refclk := false;
got_second_refclk := false;
refclk_time := now;
end if;
if (reconfig_err) then
lock <= '0';
else
lock <= locked_tmp;
end if;
-- signal to calculate quiet_time
sig_refclk_period <= refclk_period;
if (stop_vco = true) then
sig_stop_vco <= '1';
else
sig_stop_vco <= '0';
end if;
pll_locked <= pll_is_locked;
end process;
clk0_tmp <= c_clk(i_clk0_counter);
clk_pfd(0) <= clk0_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(0) <= clk_pfd(0) WHEN (test_bypass_lock_detect = "on") ELSE
clk0_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else
'X';
clk1_tmp <= c_clk(i_clk1_counter);
clk_pfd(1) <= clk1_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(1) <= clk_pfd(1) WHEN (test_bypass_lock_detect = "on") ELSE
clk1_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk2_tmp <= c_clk(i_clk2_counter);
clk_pfd(2) <= clk2_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(2) <= clk_pfd(2) WHEN (test_bypass_lock_detect = "on") ELSE
clk2_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk3_tmp <= c_clk(i_clk3_counter);
clk_pfd(3) <= clk3_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(3) <= clk_pfd(3) WHEN (test_bypass_lock_detect = "on") ELSE
clk3_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk4_tmp <= c_clk(i_clk4_counter);
clk_pfd(4) <= clk4_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(4) <= clk_pfd(4) WHEN (test_bypass_lock_detect = "on") ELSE
clk4_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk5_tmp <= c_clk(i_clk5_counter);
clk_pfd(5) <= clk5_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(5) <= clk_pfd(5) WHEN (test_bypass_lock_detect = "on") ELSE
clk5_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk6_tmp <= c_clk(i_clk6_counter);
clk_pfd(6) <= clk6_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(6) <= clk_pfd(6) WHEN (test_bypass_lock_detect = "on") ELSE
clk6_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk7_tmp <= c_clk(i_clk7_counter);
clk_pfd(7) <= clk7_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(7) <= clk_pfd(7) WHEN (test_bypass_lock_detect = "on") ELSE
clk7_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk8_tmp <= c_clk(i_clk8_counter);
clk_pfd(8) <= clk8_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(8) <= clk_pfd(8) WHEN (test_bypass_lock_detect = "on") ELSE
clk8_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk9_tmp <= c_clk(i_clk9_counter);
clk_pfd(9) <= clk9_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(9) <= clk_pfd(9) WHEN (test_bypass_lock_detect = "on") ELSE
clk9_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
scandataout <= scandata_out;
scandone <= NOT scandone_tmp;
phasedone <= NOT update_phase;
vcooverrange <= 'Z' WHEN (vco_range_detector_high_bits = -1) ELSE vco_over;
vcounderrange <= 'Z' WHEN (vco_range_detector_low_bits = -1) ELSE vco_under;
fbout <= fbclk;
end vital_pll;
-- END ARCHITECTURE VITAL_PLL
-------------------------------------------------------------------
--
-- Entity Name : stratixiii_asmiblock
--
-- Description : Stratix III ASMIBLOCK VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.stratixiii_atom_pack.all;
entity stratixiii_asmiblock is
generic (
lpm_type : string := "stratixiii_asmiblock"
);
port (
dclkin : in std_logic := '0';
scein : in std_logic := '0';
sdoin : in std_logic := '0';
data0in : in std_logic := '0';
oe : in std_logic := '0';
dclkout : out std_logic;
sceout : out std_logic;
sdoout : out std_logic;
data0out: out std_logic
);
end stratixiii_asmiblock;
architecture architecture_asmiblock of stratixiii_asmiblock is
begin
end architecture_asmiblock; -- end of stratixiii_asmiblock
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : stratixiii_lvds_reg
--
-- Description : Simulation model for a simple DFF.
-- This is used for registering the enable inputs.
-- No timing, powers upto 0.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiii_atom_pack.all;
ENTITY stratixiii_lvds_reg is
GENERIC ( MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := True;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_d : VitalDelayType01 := DefpropDelay01;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01
);
PORT ( q : OUT std_logic;
clk : IN std_logic;
ena : IN std_logic := '1';
d : IN std_logic;
clrn : IN std_logic := '1';
prn : IN std_logic := '1'
);
END stratixiii_lvds_reg;
ARCHITECTURE vital_titan_lvds_reg of stratixiii_lvds_reg is
-- INTERNAL SIGNALS
signal clk_ipd : std_logic;
signal d_ipd : std_logic;
signal ena_ipd : std_logic;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (d_ipd, d, tipd_d);
end block;
process (clk_ipd, d_ipd, clrn, prn)
variable q_tmp : std_logic := '0';
variable q_VitalGlitchData : VitalGlitchDataType;
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
begin
------------------------
-- Timing Check Section
------------------------
if (prn = '0') then
q_tmp := '1';
elsif (clrn = '0') then
q_tmp := '0';
elsif (clk_ipd'event and clk_ipd = '1') then
if (ena_ipd = '1') then
q_tmp := d_ipd;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_tmp,
Paths => (1 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_titan_lvds_reg;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : stratixiii_lvds_rx_fifo_sync_ram
--
-- Description :
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiii_atom_pack.all;
ENTITY stratixiii_lvds_rx_fifo_sync_ram is
PORT ( clk : IN std_logic;
datain : IN std_logic := '0';
writereset : IN std_logic := '0';
waddr : IN std_logic_vector(2 DOWNTO 0) := "000";
raddr : IN std_logic_vector(2 DOWNTO 0) := "000";
we : IN std_logic := '0';
dataout : OUT std_logic
);
END stratixiii_lvds_rx_fifo_sync_ram;
ARCHITECTURE vital_arm_lvds_rx_fifo_sync_ram OF stratixiii_lvds_rx_fifo_sync_ram IS
-- INTERNAL SIGNALS
signal dataout_tmp : std_logic;
signal ram_d : std_logic_vector(0 TO 5);
signal ram_q : std_logic_vector(0 TO 5);
signal data_reg : std_logic_vector(0 TO 5);
begin
dataout <= dataout_tmp;
process (clk, writereset)
variable initial : boolean := true;
begin
if (initial) then
for i in 0 to 5 loop
ram_q(i) <= '0';
end loop;
initial := false;
end if;
if (writereset = '1') then
for i in 0 to 5 loop
ram_q(i) <= '0';
end loop;
elsif (clk'event and clk = '1') then
for i in 0 to 5 loop
ram_q(i) <= ram_d(i);
end loop;
end if;
end process;
process (we, data_reg, ram_q)
begin
if (we = '1') then
ram_d <= data_reg;
else
ram_d <= ram_q;
end if;
end process;
data_reg(0) <= datain when (waddr = "000") else ram_q(0) ;
data_reg(1) <= datain when (waddr = "001") else ram_q(1) ;
data_reg(2) <= datain when (waddr = "010") else ram_q(2) ;
data_reg(3) <= datain when (waddr = "011") else ram_q(3) ;
data_reg(4) <= datain when (waddr = "100") else ram_q(4) ;
data_reg(5) <= datain when (waddr = "101") else ram_q(5) ;
process (ram_q, we, waddr, raddr)
variable initial : boolean := true;
begin
if (initial) then
dataout_tmp <= '0';
initial := false;
end if;
case raddr is
when "000" =>
dataout_tmp <= ram_q(0);
when "001" =>
dataout_tmp <= ram_q(1);
when "010" =>
dataout_tmp <= ram_q(2);
when "011" =>
dataout_tmp <= ram_q(3);
when "100" =>
dataout_tmp <= ram_q(4);
when "101" =>
dataout_tmp <= ram_q(5);
when others =>
dataout_tmp <= '0';
end case;
end process;
END vital_arm_lvds_rx_fifo_sync_ram;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : stratixiii_lvds_rx_fifo
--
-- Description :
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiii_atom_pack.all;
USE work.stratixiii_lvds_rx_fifo_sync_ram;
ENTITY stratixiii_lvds_rx_fifo is
GENERIC ( channel_width : integer := 10;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_wclk : VitalDelayType01 := DefpropDelay01;
tipd_rclk : VitalDelayType01 := DefpropDelay01;
tipd_dparst : VitalDelayType01 := DefpropDelay01;
tipd_fiforst : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tpd_rclk_dataout_posedge: VitalDelayType01 := DefPropDelay01;
tpd_dparst_dataout_posedge: VitalDelayType01 := DefPropDelay01
);
PORT ( wclk : IN std_logic:= '0';
rclk : IN std_logic:= '0';
dparst : IN std_logic := '0';
fiforst : IN std_logic := '0';
datain : IN std_logic := '0';
dataout : OUT std_logic
);
END stratixiii_lvds_rx_fifo;
ARCHITECTURE vital_arm_lvds_rx_fifo of stratixiii_lvds_rx_fifo is
-- INTERNAL SIGNALS
signal datain_in : std_logic;
signal rclk_in : std_logic;
signal dparst_in : std_logic;
signal fiforst_in : std_logic;
signal wclk_in : std_logic;
signal ram_datain : std_logic;
signal ram_dataout : std_logic;
signal wrPtr : std_logic_vector(2 DOWNTO 0);
signal rdPtr : std_logic_vector(2 DOWNTO 0);
signal rdAddr : std_logic_vector(2 DOWNTO 0);
signal ram_we : std_logic;
signal write_side_sync_reset : std_logic;
signal read_side_sync_reset : std_logic;
COMPONENT stratixiii_lvds_rx_fifo_sync_ram
PORT ( clk : IN std_logic;
datain : IN std_logic := '0';
writereset : IN std_logic := '0';
waddr : IN std_logic_vector(2 DOWNTO 0) := "000";
raddr : IN std_logic_vector(2 DOWNTO 0) := "000";
we : IN std_logic := '0';
dataout : OUT std_logic
);
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (wclk_in, wclk, tipd_wclk);
VitalWireDelay (rclk_in, rclk, tipd_rclk);
VitalWireDelay (dparst_in, dparst, tipd_dparst);
VitalWireDelay (fiforst_in, fiforst, tipd_fiforst);
VitalWireDelay (datain_in, datain, tipd_datain);
end block;
rdAddr <= rdPtr ;
s_fifo_ram : stratixiii_lvds_rx_fifo_sync_ram
PORT MAP ( clk => wclk_in,
datain => ram_datain,
writereset => write_side_sync_reset,
waddr => wrPtr,
raddr => rdAddr,
we => ram_we,
dataout => ram_dataout
);
process (wclk_in, dparst_in)
variable initial : boolean := true;
begin
if (initial) then
wrPtr <= "000";
write_side_sync_reset <= '0';
ram_we <= '0';
ram_datain <= '0';
initial := false;
end if;
if (dparst_in = '1' or (fiforst_in = '1' and wclk_in'event and wclk_in = '1')) then
write_side_sync_reset <= '1';
ram_datain <= '0';
wrPtr <= "000";
ram_we <= '0';
elsif (dparst_in = '0' and (fiforst_in = '0' and wclk_in'event and wclk_in = '1')) then
write_side_sync_reset <= '0';
end if;
if (wclk_in'event and wclk_in = '1' and write_side_sync_reset = '0' and fiforst_in = '0' and dparst_in = '0') then
ram_datain <= datain_in;
ram_we <= '1';
case wrPtr is
when "000" => wrPtr <= "001";
when "001" => wrPtr <= "010";
when "010" => wrPtr <= "011";
when "011" => wrPtr <= "100";
when "100" => wrPtr <= "101";
when "101" => wrPtr <= "000";
when others => wrPtr <= "000";
end case;
end if;
end process;
process (rclk_in, dparst_in)
variable initial : boolean := true;
variable dataout_tmp : std_logic := '0';
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
if (initial) then
rdPtr <= "011";
read_side_sync_reset <= '0';
dataout_tmp := '0';
initial := false;
end if;
if (dparst_in = '1' or (fiforst_in = '1' and rclk_in'event and rclk_in = '1')) then
read_side_sync_reset <= '1';
rdPtr <= "011";
dataout_tmp := '0';
elsif (dparst_in = '0' and (fiforst_in = '0' and rclk_in'event and rclk_in = '1')) then
read_side_sync_reset <= '0';
end if;
if (rclk_in'event and rclk_in = '1' and read_side_sync_reset = '0' and fiforst_in = '0' and dparst_in = '0') then
case rdPtr is
when "000" => rdPtr <= "001";
when "001" => rdPtr <= "010";
when "010" => rdPtr <= "011";
when "011" => rdPtr <= "100";
when "100" => rdPtr <= "101";
when "101" => rdPtr <= "000";
when others => rdPtr <= "000";
end case;
dataout_tmp := ram_dataout;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
Outsignal => dataout,
OutsignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (1 => (rclk_in'last_event, tpd_rclk_dataout_posedge, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
END vital_arm_lvds_rx_fifo;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : stratixiii_lvds_rx_bitslip
--
-- Description :
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiii_atom_pack.all;
USE work.stratixiii_lvds_reg;
ENTITY stratixiii_lvds_rx_bitslip is
GENERIC ( channel_width : integer := 10;
bitslip_rollover : integer := 12;
x_on_bitslip : string := "on";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_bslipcntl : VitalDelayType01 := DefpropDelay01;
tipd_bsliprst : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tpd_bsliprst_bslipmax_posedge: VitalDelayType01 := DefPropDelay01;
tpd_clk0_bslipmax_posedge: VitalDelayType01 := DefPropDelay01
);
PORT ( clk0 : IN std_logic := '0';
bslipcntl : IN std_logic := '0';
bsliprst : IN std_logic := '0';
datain : IN std_logic := '0';
bslipmax : OUT std_logic;
dataout : OUT std_logic
);
END stratixiii_lvds_rx_bitslip;
ARCHITECTURE vital_arm_lvds_rx_bitslip OF stratixiii_lvds_rx_bitslip IS
-- INTERNAL SIGNALS
signal clk0_in : std_logic;
signal bslipcntl_in : std_logic;
signal bsliprst_in : std_logic;
signal datain_in : std_logic;
signal slip_count : integer := 0;
signal dataout_tmp : std_logic;
signal bitslip_arr : std_logic_vector(11 DOWNTO 0) := "000000000000";
signal bslipcntl_reg : std_logic;
signal vcc : std_logic := '1';
signal slip_data : std_logic := '0';
signal start_corrupt_bits : std_logic := '0';
signal num_corrupt_bits : integer := 0;
COMPONENT stratixiii_lvds_reg
GENERIC ( MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_d : VitalDelayType01 := DefpropDelay01;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( q : OUT std_logic;
clk : IN std_logic;
ena : IN std_logic := '1';
d : IN std_logic;
clrn : IN std_logic := '1';
prn : IN std_logic := '1'
);
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk0_in, clk0, tipd_clk0);
VitalWireDelay (bslipcntl_in, bslipcntl, tipd_bslipcntl);
VitalWireDelay (bsliprst_in, bsliprst, tipd_bsliprst);
VitalWireDelay (datain_in, datain, tipd_datain);
end block;
bslipcntlreg : stratixiii_lvds_reg
PORT MAP ( d => bslipcntl_in,
clk => clk0_in,
ena => vcc,
clrn => vcc,
prn => vcc,
q => bslipcntl_reg
);
-- 4-bit slip counter and 12-bit shift register
process (bslipcntl_reg, bsliprst_in, clk0_in)
variable initial : boolean := true;
variable bslipmax_tmp : std_logic := '0';
variable bslipmax_VitalGlitchData : VitalGlitchDataType;
begin
if (bsliprst_in = '1') then
slip_count <= 0;
bslipmax_tmp := '0';
-- bitslip_arr <= (OTHERS => '0');
if (bsliprst_in'event and bsliprst_in = '1' and bsliprst_in'last_value = '0') then
ASSERT false report "Bit Slip Circuit was reset. Serial Data stream will have 0 latency" severity note;
end if;
else
if (bslipcntl_reg'event and bslipcntl_reg = '1' and bslipcntl_reg'last_value = '0') then
if (x_on_bitslip = "on") then
start_corrupt_bits <= '1';
end if;
num_corrupt_bits <= 0;
if (slip_count = bitslip_rollover) then
ASSERT false report "Rollover occurred on Bit Slip circuit. Serial data stream will have 0 latency." severity note;
slip_count <= 0;
bslipmax_tmp := '0';
else
slip_count <= slip_count + 1;
if ((slip_count + 1) = bitslip_rollover) then
ASSERT false report "The Bit Slip circuit has reached the maximum Bit Slip limit. Rollover will occur on the next slip." severity note;
bslipmax_tmp := '1';
end if;
end if;
elsif (bslipcntl_reg'event and bslipcntl_reg = '0' and bslipcntl_reg'last_value = '1') then
start_corrupt_bits <= '0';
num_corrupt_bits <= 0;
end if;
end if;
if (clk0_in'event and clk0_in = '1' and clk0_in'last_value = '0') then
bitslip_arr(0) <= datain_in;
for i in 0 to (bitslip_rollover - 1) loop
bitslip_arr(i + 1) <= bitslip_arr(i);
end loop;
if (start_corrupt_bits = '1') then
num_corrupt_bits <= num_corrupt_bits + 1;
end if;
if (num_corrupt_bits+1 = 3) then
start_corrupt_bits <= '0';
end if;
end if;
-- end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
Outsignal => bslipmax,
OutsignalName => "BSLIPMAX",
OutTemp => bslipmax_tmp,
Paths => (1 => (clk0_in'last_event, tpd_clk0_bslipmax_posedge, TRUE),
2 => (bsliprst_in'last_event, tpd_bsliprst_bslipmax_posedge, TRUE)),
GlitchData => bslipmax_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
slip_data <= bitslip_arr(slip_count);
dataoutreg : stratixiii_lvds_reg
PORT MAP ( d => slip_data,
clk => clk0_in,
ena => vcc,
clrn => vcc,
prn => vcc,
q => dataout_tmp
);
dataout <= dataout_tmp when start_corrupt_bits = '0' else
'X' when start_corrupt_bits = '1' and num_corrupt_bits < 3 else
dataout_tmp;
END vital_arm_lvds_rx_bitslip;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : stratixiii_lvds_rx_deser
--
-- Description : Timing simulation model for the stratixiii LVDS RECEIVER
-- DESERIALIZER. This module receives serial data and outputs
-- parallel data word of width = channel width
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiii_atom_pack.all;
ENTITY stratixiii_lvds_rx_deser IS
GENERIC ( channel_width : integer := 4;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( clk : IN std_logic := '0';
datain : IN std_logic := '0';
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END stratixiii_lvds_rx_deser;
ARCHITECTURE vital_arm_lvds_rx_deser OF stratixiii_lvds_rx_deser IS
-- INTERNAL SIGNALS
signal clk_ipd : std_logic;
signal datain_ipd : std_logic;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process (clk_ipd, devpor, devclrn)
variable dataout_tmp : std_logic_vector(channel_width - 1 downto 0) := (OTHERS => '0');
variable i : integer := 0;
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(9 downto 0);
variable CQDelay : TIME := 0 ns;
begin
if (devclrn = '0' or devpor = '0') then
dataout_tmp := (OTHERS => '0');
else
if (clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0') then
for i in channel_width - 1 DOWNTO 1 loop
dataout_tmp(i) := dataout_tmp(i - 1);
end loop;
dataout_tmp(0) := datain_ipd;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
CQDelay := SelectDelay (
(1 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE))
);
dataout <= TRANSPORT dataout_tmp AFTER CQDelay;
end process;
END vital_arm_lvds_rx_deser;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : stratixiii_lvds_rx_parallel_reg
--
-- Description : Timing simulation model for the stratixiii LVDS RECEIVER
-- PARALLEL REGISTER. The data width equals max. channel width,
-- which is 10.
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiii_atom_pack.all;
ENTITY stratixiii_lvds_rx_parallel_reg IS
GENERIC ( channel_width : integer := 4;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_enable : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01);
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( clk : IN std_logic;
enable : IN std_logic := '1';
datain : IN std_logic_vector(channel_width - 1 DOWNTO 0);
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END stratixiii_lvds_rx_parallel_reg;
ARCHITECTURE vital_arm_lvds_rx_parallel_reg OF stratixiii_lvds_rx_parallel_reg IS
-- INTERNAL SIGNALS
signal clk_ipd : std_logic;
signal datain_ipd : std_logic_vector(channel_width - 1 downto 0);
signal enable_ipd : std_logic;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (enable_ipd, enable, tipd_enable);
loopbits : FOR i in datain'RANGE GENERATE
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
END GENERATE;
end block;
VITAL: process (clk_ipd, devpor, devclrn)
variable dataout_tmp : std_logic_vector(channel_width - 1 downto 0) := (OTHERS => '0');
variable i : integer := 0;
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(9 downto 0);
variable CQDelay : TIME := 0 ns;
begin
if ((devpor = '0') or (devclrn = '0')) then
dataout_tmp := (OTHERS => '0');
else
if (clk_ipd'event and clk_ipd = '1') then
if (enable_ipd = '1') then
dataout_tmp := datain_ipd;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
CQDelay := SelectDelay (
(1 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE))
);
dataout <= dataout_tmp AFTER CQDelay;
end process;
END vital_arm_lvds_rx_parallel_reg;
-------------------------------------------------------------------------------
--
-- Module Name : stratixiii_pclk_divider
--
-- Description : Simulation model for a clock divider
-- output clock is divided by value specified
-- in the parameter clk_divide_by
--
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY stratixiii_pclk_divider IS
GENERIC (
clk_divide_by : integer := 1);
PORT (
clkin : IN std_logic;
lloaden : OUT std_logic;
clkout : OUT std_logic);
END stratixiii_pclk_divider;
ARCHITECTURE arch OF stratixiii_pclk_divider IS
SIGNAL lloaden_tmp : std_logic := '0';
SIGNAL clkout_tmp : std_logic := '0';
SIGNAL cnt : std_logic_vector(4 DOWNTO 0):= (others => '0');
BEGIN
clkout <= clkin WHEN (clk_divide_by = 1) ELSE clkout_tmp;
lloaden <= lloaden_tmp;
PROCESS(clkin)
variable count : std_logic := '0';
variable start : std_logic := '0';
variable prev_load : std_logic := '0';
BEGIN
IF(clkin = '1') THEN
count := '1';
END IF;
if( count = '1') then
IF (cnt < clk_divide_by) THEN
clkout_tmp <= '0';
cnt <= cnt + "00001";
ELSE
IF (cnt = (2 * clk_divide_by - 1)) THEN
cnt <= "00000";
ELSE
clkout_tmp <= '1';
cnt <= cnt + "00001";
END IF;
END IF;
end if;
END PROCESS;
process( clkin, cnt )
begin
if( cnt =( 2*clk_divide_by -2) )then
lloaden_tmp <= '1';
else
if(cnt = 0)then
lloaden_tmp <= '0';
end if;
end if;
end process;
END arch;
-------------------------------------------------------------------------------
--
-- Module Name : stratixiii_select_ini_phase_dpaclk
--
-- Description : Simulation model for selecting the initial phase of the dpa clock
--
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.ALL;
ENTITY stratixiii_select_ini_phase_dpaclk IS
GENERIC(
initial_phase_select : integer := 0
);
PORT (
clkin : IN STD_LOGIC;
loaden : IN STD_LOGIC;
enable : IN STD_LOGIC;
clkout : OUT STD_LOGIC;
loadenout : OUT STD_LOGIC
);
END stratixiii_select_ini_phase_dpaclk;
ARCHITECTURE trans OF stratixiii_select_ini_phase_dpaclk IS
SIGNAL clk_period : time := 0 ps;
SIGNAL last_clk_period : time := 0 ps;
SIGNAL last_clkin_edge : time := 0 ps;
SIGNAL first_clkin_edge_detect : STD_LOGIC := '0';
SIGNAL clk0_tmp : STD_LOGIC;
SIGNAL clk1_tmp : STD_LOGIC;
SIGNAL clk2_tmp : STD_LOGIC;
SIGNAL clk3_tmp : STD_LOGIC;
SIGNAL clk4_tmp : STD_LOGIC;
SIGNAL clk5_tmp : STD_LOGIC;
SIGNAL clk6_tmp : STD_LOGIC;
SIGNAL clk7_tmp : STD_LOGIC;
SIGNAL loaden0_tmp : STD_LOGIC;
SIGNAL loaden1_tmp : STD_LOGIC;
SIGNAL loaden2_tmp : STD_LOGIC;
SIGNAL loaden3_tmp : STD_LOGIC;
SIGNAL loaden4_tmp : STD_LOGIC;
SIGNAL loaden5_tmp : STD_LOGIC;
SIGNAL loaden6_tmp : STD_LOGIC;
SIGNAL loaden7_tmp : STD_LOGIC;
SIGNAL clkout_tmp : STD_LOGIC;
SIGNAL loadenout_tmp : STD_LOGIC;
BEGIN
clkout_tmp <= clk1_tmp when (initial_phase_select = 1) else
clk2_tmp when (initial_phase_select = 2) else
clk3_tmp when (initial_phase_select = 3) else
clk4_tmp when (initial_phase_select = 4) else
clk5_tmp when (initial_phase_select = 5) else
clk6_tmp when (initial_phase_select = 6) else
clk7_tmp when (initial_phase_select = 7) else
clk0_tmp;
clkout <= clkout_tmp when enable = '1' else clkin;
loadenout_tmp <= loaden1_tmp when (initial_phase_select = 1) else
loaden2_tmp when (initial_phase_select = 2) else
loaden3_tmp when (initial_phase_select = 3) else
loaden4_tmp when (initial_phase_select = 4) else
loaden5_tmp when (initial_phase_select = 5) else
loaden6_tmp when (initial_phase_select = 6) else
loaden7_tmp when (initial_phase_select = 7) else
loaden0_tmp;
loadenout <= loadenout_tmp when enable = '1' else loaden;
-- Calculate the clock period
PROCESS
VARIABLE clk_period_tmp : time := 0 ps;
BEGIN
WAIT UNTIL (clkin'EVENT AND clkin = '1');
IF (first_clkin_edge_detect = '0') THEN
first_clkin_edge_detect <= '1';
ELSE
last_clk_period <= clk_period;
clk_period_tmp := NOW - last_clkin_edge;
END IF;
last_clkin_edge <= NOW;
clk_period <= clk_period_tmp;
END PROCESS;
-- Generate the phase shifted signals
PROCESS (clkin)
BEGIN
clk0_tmp <= clkin;
clk1_tmp <= TRANSPORT clkin after (clk_period * 0.125) ;
clk2_tmp <= TRANSPORT clkin after (clk_period * 0.25) ;
clk3_tmp <= TRANSPORT clkin after (clk_period * 0.375) ;
clk4_tmp <= TRANSPORT clkin after (clk_period * 0.5) ;
clk5_tmp <= TRANSPORT clkin after (clk_period * 0.625) ;
clk6_tmp <= TRANSPORT clkin after (clk_period * 0.75) ;
clk7_tmp <= TRANSPORT clkin after (clk_period * 0.875) ;
END PROCESS;
PROCESS (loaden)
BEGIN
loaden0_tmp <= clkin;
loaden1_tmp <= TRANSPORT loaden after (clk_period * 0.125) ;
loaden2_tmp <= TRANSPORT loaden after (clk_period * 0.25) ;
loaden3_tmp <= TRANSPORT loaden after (clk_period * 0.375) ;
loaden4_tmp <= TRANSPORT loaden after (clk_period * 0.5) ;
loaden5_tmp <= TRANSPORT loaden after (clk_period * 0.625) ;
loaden6_tmp <= TRANSPORT loaden after (clk_period * 0.75) ;
loaden7_tmp <= TRANSPORT loaden after (clk_period * 0.875) ;
END PROCESS;
END trans;
-------------------------------------------------------------------------------
--
-- Module Name : stratixiii_dpa_retime_block
--
-- Description : Simulation model for generating the retimed clock,data and loaden.
-- Each of the signals has 8 different phase shifted versions.
--
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.ALL;
ENTITY stratixiii_dpa_retime_block IS
PORT (
clkin : IN STD_LOGIC;
datain : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk0 : OUT STD_LOGIC;
clk1 : OUT STD_LOGIC;
clk2 : OUT STD_LOGIC;
clk3 : OUT STD_LOGIC;
clk4 : OUT STD_LOGIC;
clk5 : OUT STD_LOGIC;
clk6 : OUT STD_LOGIC;
clk7 : OUT STD_LOGIC;
data0 : OUT STD_LOGIC;
data1 : OUT STD_LOGIC;
data2 : OUT STD_LOGIC;
data3 : OUT STD_LOGIC;
data4 : OUT STD_LOGIC;
data5 : OUT STD_LOGIC;
data6 : OUT STD_LOGIC;
data7 : OUT STD_LOGIC;
lock : OUT STD_LOGIC
);
END stratixiii_dpa_retime_block;
ARCHITECTURE trans OF stratixiii_dpa_retime_block IS
SIGNAL clk_period : time := 0 ps;
SIGNAL last_clk_period : time := 0 ps;
SIGNAL last_clkin_edge : time := 0 ps;
SIGNAL first_clkin_edge_detect : STD_LOGIC := '0';
SIGNAL clk0_tmp : STD_LOGIC;
SIGNAL clk1_tmp : STD_LOGIC;
SIGNAL clk2_tmp : STD_LOGIC;
SIGNAL clk3_tmp : STD_LOGIC;
SIGNAL clk4_tmp : STD_LOGIC;
SIGNAL clk5_tmp : STD_LOGIC;
SIGNAL clk6_tmp : STD_LOGIC;
SIGNAL clk7_tmp : STD_LOGIC;
SIGNAL data0_tmp : STD_LOGIC;
SIGNAL data1_tmp : STD_LOGIC;
SIGNAL data2_tmp : STD_LOGIC;
SIGNAL data3_tmp : STD_LOGIC;
SIGNAL data4_tmp : STD_LOGIC;
SIGNAL data5_tmp : STD_LOGIC;
SIGNAL data6_tmp : STD_LOGIC;
SIGNAL data7_tmp : STD_LOGIC;
SIGNAL lock_tmp : STD_LOGIC := '0';
BEGIN
clk0 <= '0' WHEN reset = '1' ELSE clk0_tmp;
clk1 <= '0' WHEN reset = '1' ELSE clk1_tmp;
clk2 <= '0' WHEN reset = '1' ELSE clk2_tmp;
clk3 <= '0' WHEN reset = '1' ELSE clk3_tmp;
clk4 <= '0' WHEN reset = '1' ELSE clk4_tmp;
clk5 <= '0' WHEN reset = '1' ELSE clk5_tmp;
clk6 <= '0' WHEN reset = '1' ELSE clk6_tmp;
clk7 <= '0' WHEN reset = '1' ELSE clk7_tmp;
data0 <= '0' WHEN reset = '1' ELSE data0_tmp;
data1 <= '0' WHEN reset = '1' ELSE data1_tmp;
data2 <= '0' WHEN reset = '1' ELSE data2_tmp;
data3 <= '0' WHEN reset = '1' ELSE data3_tmp;
data4 <= '0' WHEN reset = '1' ELSE data4_tmp;
data5 <= '0' WHEN reset = '1' ELSE data5_tmp;
data6 <= '0' WHEN reset = '1' ELSE data6_tmp;
data7 <= '0' WHEN reset = '1' ELSE data7_tmp;
lock <= '0' WHEN reset = '1' ELSE lock_tmp;
-- Calculate the clock period
PROCESS
VARIABLE clk_period_tmp : time := 0 ps;
BEGIN
WAIT UNTIL (clkin'EVENT AND clkin = '1');
IF (first_clkin_edge_detect = '0') THEN
first_clkin_edge_detect <= '1';
ELSE
last_clk_period <= clk_period;
clk_period_tmp := NOW - last_clkin_edge;
END IF;
IF (((clk_period_tmp = last_clk_period) OR (clk_period_tmp = last_clk_period + 1 ps) OR (clk_period_tmp = last_clk_period - 1 ps)) AND (clk_period_tmp /= 0 ps ) AND (last_clk_period /= 0 ps)) THEN
lock_tmp <= '1';
ELSE
lock_tmp <= '0';
END IF;
last_clkin_edge <= NOW;
clk_period <= clk_period_tmp;
END PROCESS;
-- Generate the phase shifted signals
PROCESS (clkin)
BEGIN
clk0_tmp <= clkin;
clk1_tmp <= TRANSPORT clkin after (clk_period * 0.125) ;
clk2_tmp <= TRANSPORT clkin after (clk_period * 0.25) ;
clk3_tmp <= TRANSPORT clkin after (clk_period * 0.375) ;
clk4_tmp <= TRANSPORT clkin after (clk_period * 0.5) ;
clk5_tmp <= TRANSPORT clkin after (clk_period * 0.625) ;
clk6_tmp <= TRANSPORT clkin after (clk_period * 0.75) ;
clk7_tmp <= TRANSPORT clkin after (clk_period * 0.875) ;
END PROCESS;
PROCESS (datain)
BEGIN
data0_tmp <= datain;
data1_tmp <= TRANSPORT datain after (clk_period * 0.125) ;
data2_tmp <= TRANSPORT datain after (clk_period * 0.25) ;
data3_tmp <= TRANSPORT datain after (clk_period * 0.375) ;
data4_tmp <= TRANSPORT datain after (clk_period * 0.5) ;
data5_tmp <= TRANSPORT datain after (clk_period * 0.625) ;
data6_tmp <= TRANSPORT datain after (clk_period * 0.75) ;
data7_tmp <= TRANSPORT datain after (clk_period * 0.875) ;
END PROCESS;
END trans;
-------------------------------------------------------------------------------
--
-- Module Name : stratixiii_dpa_block
--
-- Description : Simulation model for selecting the retimed data, clock and loaden
-- depending on the PPM varaiation and direction of shift.
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE work.stratixiii_dpa_retime_block;
ENTITY stratixiii_dpa_block IS
GENERIC (
net_ppm_variation : INTEGER := 0;
is_negative_ppm_drift : STRING := "off";
enable_soft_cdr_mode: STRING := "on"
);
PORT (
clkin : IN STD_LOGIC;
dpareset : IN STD_LOGIC;
dpahold : IN STD_LOGIC;
datain : IN STD_LOGIC;
clkout : OUT STD_LOGIC;
dataout : OUT STD_LOGIC;
dpalock : OUT STD_LOGIC
);
END stratixiii_dpa_block;
ARCHITECTURE trans OF stratixiii_dpa_block IS
COMPONENT stratixiii_dpa_retime_block
PORT (
clkin : IN STD_LOGIC;
datain : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk0 : OUT STD_LOGIC;
clk1 : OUT STD_LOGIC;
clk2 : OUT STD_LOGIC;
clk3 : OUT STD_LOGIC;
clk4 : OUT STD_LOGIC;
clk5 : OUT STD_LOGIC;
clk6 : OUT STD_LOGIC;
clk7 : OUT STD_LOGIC;
data0 : OUT STD_LOGIC;
data1 : OUT STD_LOGIC;
data2 : OUT STD_LOGIC;
data3 : OUT STD_LOGIC;
data4 : OUT STD_LOGIC;
data5 : OUT STD_LOGIC;
data6 : OUT STD_LOGIC;
data7 : OUT STD_LOGIC;
lock : OUT STD_LOGIC
);
END COMPONENT;
SIGNAL clk0_tmp : STD_LOGIC;
SIGNAL clk1_tmp : STD_LOGIC;
SIGNAL clk2_tmp : STD_LOGIC;
SIGNAL clk3_tmp : STD_LOGIC;
SIGNAL clk4_tmp : STD_LOGIC;
SIGNAL clk5_tmp : STD_LOGIC;
SIGNAL clk6_tmp : STD_LOGIC;
SIGNAL clk7_tmp : STD_LOGIC;
SIGNAL data0_tmp : STD_LOGIC;
SIGNAL data1_tmp : STD_LOGIC;
SIGNAL data2_tmp : STD_LOGIC;
SIGNAL data3_tmp : STD_LOGIC;
SIGNAL data4_tmp : STD_LOGIC;
SIGNAL data5_tmp : STD_LOGIC;
SIGNAL data6_tmp : STD_LOGIC;
SIGNAL data7_tmp : STD_LOGIC;
SIGNAL select_xhdl1 : STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
SIGNAL clkout_tmp : STD_LOGIC;
SIGNAL dataout_tmp : STD_LOGIC;
SIGNAL counter_reset_value : INTEGER ;
SIGNAL count_value : INTEGER ;
SIGNAL i : INTEGER := 0;
SIGNAL dpalock_xhdl0 : STD_LOGIC;
BEGIN
-- Drive referenced outputs
dpalock <= dpalock_xhdl0;
dataout <= dataout_tmp when (enable_soft_cdr_mode = "on") else datain;
clkout <= clkout_tmp when (enable_soft_cdr_mode = "on") else clkin;
data_clock_retime : stratixiii_dpa_retime_block
PORT MAP (
clkin => clkin,
datain => datain,
reset => dpareset,
clk0 => clk0_tmp,
clk1 => clk1_tmp,
clk2 => clk2_tmp,
clk3 => clk3_tmp,
clk4 => clk4_tmp,
clk5 => clk5_tmp,
clk6 => clk6_tmp,
clk7 => clk7_tmp,
data0 => data0_tmp,
data1 => data1_tmp,
data2 => data2_tmp,
data3 => data3_tmp,
data4 => data4_tmp,
data5 => data5_tmp,
data6 => data6_tmp,
data7 => data7_tmp,
lock => dpalock_xhdl0
);
PROCESS (clkin, dpareset, dpahold)
variable initial : boolean := true;
variable ppm_tmp : integer;
BEGIN
if(initial) then
if(net_ppm_variation = 0) then
ppm_tmp := 1;
else
ppm_tmp := net_ppm_variation;
end if;
if(net_ppm_variation = 0) then
counter_reset_value <= 1;
count_value <= 1;
initial := false;
else
counter_reset_value <= 1000000 / (ppm_tmp * 8);
count_value <= 1000000 / (ppm_tmp * 8);
initial := false;
end if;
end if;
IF (clkin'EVENT AND clkin = '1') THEN
IF(net_ppm_variation = 0) THEN
select_xhdl1 <= "000";
ELSE
IF (dpareset = '1') THEN
i <= 0;
select_xhdl1 <= "000";
ELSE
IF (dpahold = '0') THEN
IF (i < count_value) THEN
i <= i + 1;
ELSE
select_xhdl1 <= select_xhdl1 + "001";
i <= 0;
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (select_xhdl1, clk0_tmp, clk1_tmp, clk2_tmp, clk3_tmp, clk4_tmp, clk5_tmp, clk6_tmp, clk7_tmp,
data0_tmp, data1_tmp, data2_tmp, data3_tmp, data4_tmp, data5_tmp, data6_tmp, data7_tmp)
BEGIN
if (select_xhdl1 = "000") then
clkout_tmp <= clk0_tmp;
dataout_tmp <= data0_tmp;
elsif (select_xhdl1 = "001") then
if( is_negative_ppm_drift = "off")then
clkout_tmp <= clk1_tmp;
dataout_tmp <= data1_tmp;
else
clkout_tmp <= clk7_tmp;
dataout_tmp <= data7_tmp;
end if;
elsif (select_xhdl1 = "010") then
if( is_negative_ppm_drift = "off")then
clkout_tmp <= clk2_tmp;
dataout_tmp <= data2_tmp;
else
clkout_tmp <= clk6_tmp;
dataout_tmp <= data6_tmp;
end if;
elsif (select_xhdl1 = "011")then
if( is_negative_ppm_drift = "off")then
clkout_tmp <= clk3_tmp;
dataout_tmp <= data3_tmp;
else
clkout_tmp <= clk5_tmp;
dataout_tmp <= data5_tmp;
end if;
elsif (select_xhdl1 = "100")then
clkout_tmp <= clk4_tmp;
dataout_tmp <= data4_tmp;
elsif (select_xhdl1 = "101")then
if( is_negative_ppm_drift = "off")then
clkout_tmp <= clk5_tmp;
dataout_tmp <= data5_tmp;
else
clkout_tmp <= clk3_tmp;
dataout_tmp <= data3_tmp;
end if;
elsif (select_xhdl1 = "110") then
if( is_negative_ppm_drift = "off")then
clkout_tmp <= clk6_tmp;
dataout_tmp <= data6_tmp;
else
clkout_tmp <= clk2_tmp;
dataout_tmp <= data2_tmp;
end if;
elsif (select_xhdl1 = "111")then
if( is_negative_ppm_drift = "off")then
clkout_tmp <= clk7_tmp;
dataout_tmp <= data7_tmp;
else
clkout_tmp <= clk1_tmp;
dataout_tmp <= data1_tmp;
end if;
else
clkout_tmp <= clk0_tmp;
dataout_tmp <= data0_tmp;
end if;
END PROCESS;
END trans;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : stratixiii_LVDS_RECEIVER
--
-- Description : Timing simulation model for the stratixiii LVDS RECEIVER
-- atom. This module instantiates the following sub-modules :
-- 1) stratixiii_lvds_rx_fifo
-- 2) stratixiii_lvds_rx_bitslip
-- 3) DFFEs for the LOADEN signals
-- 4) stratixiii_lvds_rx_parallel_reg
-- 5) stratixiii_pclk_divider
-- 6) stratixiii_select_ini_phase_dpaclk
-- 7) stratixiii_dpa_block
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiii_atom_pack.all;
USE work.stratixiii_lvds_rx_bitslip;
USE work.stratixiii_lvds_rx_fifo;
USE work.stratixiii_lvds_rx_deser;
USE work.stratixiii_lvds_rx_parallel_reg;
USE work.stratixiii_lvds_reg;
USE work.stratixiii_pclk_divider;
USE work.stratixiii_select_ini_phase_dpaclk;
USE work.stratixiii_dpa_block;
ENTITY stratixiii_lvds_receiver IS
GENERIC ( channel_width : integer := 10;
data_align_rollover : integer := 2;
enable_dpa : string := "off";
lose_lock_on_one_change : string := "off";
reset_fifo_at_first_lock : string := "on";
align_to_rising_edge_only : string := "on";
use_serial_feedback_input : string := "off";
dpa_debug : string := "off";
enable_soft_cdr : string := "off";
dpa_output_clock_phase_shift : INTEGER := 0 ;
enable_dpa_initial_phase_selection : string := "off";
dpa_initial_phase_value : INTEGER := 0;
enable_dpa_align_to_rising_edge_only : string := "off";
net_ppm_variation : INTEGER := 0;
is_negative_ppm_drift : string := "off";
rx_input_path_delay_engineering_bits : INTEGER := -1;
x_on_bitslip : string := "on";
lpm_type : string := "stratixiii_lvds_receiver";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_dpareset : VitalDelayType01 := DefpropDelay01;
tipd_dpahold : VitalDelayType01 := DefpropDelay01;
tipd_dpaswitch : VitalDelayType01 := DefpropDelay01;
tipd_fiforeset : VitalDelayType01 := DefpropDelay01;
tipd_bitslip : VitalDelayType01 := DefpropDelay01;
tipd_bitslipreset : VitalDelayType01 := DefpropDelay01;
tipd_serialfbk : VitalDelayType01 := DefpropDelay01;
tpd_clk0_dpalock_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( clk0 : IN std_logic;
datain : IN std_logic := '0';
enable0 : IN std_logic := '0';
dpareset : IN std_logic := '0';
dpahold : IN std_logic := '0';
dpaswitch : IN std_logic := '0';
fiforeset : IN std_logic := '0';
bitslip : IN std_logic := '0';
bitslipreset : IN std_logic := '0';
serialfbk : IN std_logic := '0';
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
dpalock : OUT std_logic:= '0';
bitslipmax : OUT std_logic;
serialdataout : OUT std_logic;
postdpaserialdataout : OUT std_logic;
divfwdclk : OUT std_logic;
dpaclkout : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END stratixiii_lvds_receiver;
ARCHITECTURE vital_arm_lvds_receiver OF stratixiii_lvds_receiver IS
COMPONENT stratixiii_lvds_rx_bitslip
GENERIC ( channel_width : integer := 10;
bitslip_rollover : integer := 12;
x_on_bitslip : string := "on";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_bslipcntl : VitalDelayType01 := DefpropDelay01;
tipd_bsliprst : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tpd_bsliprst_bslipmax_posedge: VitalDelayType01 := DefPropDelay01;
tpd_clk0_bslipmax_posedge: VitalDelayType01 := DefPropDelay01
);
PORT ( clk0 : IN std_logic := '0';
bslipcntl : IN std_logic := '0';
bsliprst : IN std_logic := '0';
datain : IN std_logic := '0';
bslipmax : OUT std_logic;
dataout : OUT std_logic
);
END COMPONENT;
COMPONENT stratixiii_lvds_rx_fifo
GENERIC ( channel_width : integer := 10
);
PORT ( wclk : IN std_logic := '0';
rclk : IN std_logic := '0';
fiforst : IN std_logic := '0';
dparst : IN std_logic := '0';
datain : IN std_logic := '0';
dataout : OUT std_logic
);
END COMPONENT;
COMPONENT stratixiii_lvds_rx_deser
GENERIC ( channel_width : integer := 4
);
PORT ( clk : IN std_logic;
datain : IN std_logic;
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
COMPONENT stratixiii_lvds_rx_parallel_reg
GENERIC ( channel_width : integer := 4
);
PORT ( clk : IN std_logic;
enable : IN std_logic := '1';
datain : IN std_logic_vector(channel_width - 1 DOWNTO 0);
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
COMPONENT stratixiii_lvds_reg
GENERIC ( MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_d : VitalDelayType01 := DefpropDelay01;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( q : OUT std_logic;
clk : IN std_logic;
ena : IN std_logic := '1';
d : IN std_logic;
clrn : IN std_logic := '1';
prn : IN std_logic := '1'
);
END COMPONENT;
COMPONENT stratixiii_pclk_divider
GENERIC (
clk_divide_by : integer := 1);
PORT (
clkin : IN std_logic;
lloaden : OUT std_logic;
clkout : OUT std_logic);
END COMPONENT;
COMPONENT stratixiii_select_ini_phase_dpaclk
GENERIC(
initial_phase_select : integer := 0
);
PORT (
clkin : IN STD_LOGIC;
loaden : IN STD_LOGIC;
enable : IN STD_LOGIC;
loadenout : OUT STD_LOGIC;
clkout : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT stratixiii_dpa_block
GENERIC (
net_ppm_variation : INTEGER := 0;
is_negative_ppm_drift : STRING := "off";
enable_soft_cdr_mode: STRING := "on"
);
PORT (
clkin : IN STD_LOGIC;
dpareset : IN STD_LOGIC;
dpahold : IN STD_LOGIC;
datain : IN STD_LOGIC;
clkout : OUT STD_LOGIC;
dataout : OUT STD_LOGIC;
dpalock : OUT STD_LOGIC
);
END COMPONENT;
-- INTERNAL SIGNALS
signal bitslip_ipd : std_logic;
signal bitslipreset_ipd : std_logic;
signal clk0_ipd : std_logic;
signal datain_ipd : std_logic;
signal dpahold_ipd : std_logic;
signal dpareset_ipd : std_logic;
signal dpaswitch_ipd : std_logic;
signal enable0_ipd : std_logic;
signal fiforeset_ipd : std_logic;
signal serialfbk_ipd : std_logic;
signal fifo_wclk : std_logic;
signal fifo_rclk : std_logic;
signal fifo_datain : std_logic;
signal fifo_dataout : std_logic;
signal fifo_reset : std_logic;
signal slip_datain : std_logic;
signal slip_dataout : std_logic;
signal bitslip_reset : std_logic;
-- wire deser_dataout;
signal dpa_clk : std_logic;
signal dpa_rst : std_logic;
signal datain_reg : std_logic;
signal datain_reg_neg : std_logic;
signal datain_reg_tmp : std_logic;
signal deser_dataout : std_logic_vector(channel_width - 1 DOWNTO 0);
signal reset_fifo : std_logic;
signal gnd : std_logic := '0';
signal vcc : std_logic := '1';
signal in_reg_data : std_logic;
signal slip_datain_tmp : std_logic;
signal s_bitslip_clk : std_logic;
signal loaden : std_logic;
signal ini_dpa_clk : std_logic;
signal ini_dpa_load : std_logic;
signal ini_phase_select_enable : std_logic;
signal dpa_clk_shift : std_logic;
signal dpa_data_shift : std_logic;
signal lloaden : std_logic;
signal lock_tmp : std_logic;
signal divfwdclk_tmp : std_logic;
signal dpa_is_locked : std_logic;
signal dpareg0_out : std_logic;
signal dpareg1_out : std_logic;
signal xhdl_12 : std_logic;
signal rxload : std_logic;
signal clk0_tmp : std_logic;
signal clk0_tmp_neg : std_logic;
begin
WireDelay : block
begin
VitalWireDelay (clk0_ipd, clk0, tipd_clk0);
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (enable0_ipd, enable0, tipd_enable0);
VitalWireDelay (dpareset_ipd, dpareset, tipd_dpareset);
VitalWireDelay (dpahold_ipd, dpahold, tipd_dpahold);
VitalWireDelay (dpaswitch_ipd, dpaswitch, tipd_dpaswitch);
VitalWireDelay (fiforeset_ipd, fiforeset, tipd_fiforeset);
VitalWireDelay (bitslip_ipd, bitslip, tipd_bitslip);
VitalWireDelay (bitslipreset_ipd, bitslipreset, tipd_bitslipreset);
VitalWireDelay (serialfbk_ipd, serialfbk, tipd_serialfbk);
end block;
process (clk0_ipd, dpareset_ipd,lock_tmp )
variable dpalock_VitalGlitchData : VitalGlitchDataType;
variable initial : boolean := true;
begin
if (initial) then
if (reset_fifo_at_first_lock = "on") then
reset_fifo <= '1';
else
reset_fifo <= '0';
end if;
initial := false;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => dpalock,
OutSignalName => "DPALOCK",
OutTemp => dpa_is_locked,
Paths => (1 => (clk0_ipd'last_event, tpd_clk0_dpalock_posedge, enable_dpa = "on")),
GlitchData => dpalock_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
if(lock_tmp = '1') then
reset_fifo <= '0';
else
reset_fifo <= '1';
end if;
end process;
xhdl_12 <= devclrn OR devpor;
-- input register in non-DPA mode for sampling incoming data
in_reg : stratixiii_lvds_reg
PORT MAP (
d => in_reg_data,
clk => clk0_tmp,
ena => vcc,
clrn => xhdl_12,
prn => vcc,
q => datain_reg
);
in_reg_data <= serialfbk_ipd WHEN (use_serial_feedback_input = "on") ELSE datain_ipd;
clk0_tmp <= clk0_ipd;
clk0_tmp_neg <= not clk0_ipd;
neg_reg : stratixiii_lvds_reg
PORT MAP (
d => in_reg_data,
clk => clk0_tmp_neg,
ena => vcc,
clrn => xhdl_12,
prn => vcc,
q => datain_reg_neg
);
datain_reg_tmp <= datain_reg WHEN (align_to_rising_edge_only = "on") ELSE datain_reg_neg;
-- dpa initial phase select
ini_clk_phase_select: stratixiii_select_ini_phase_dpaclk
GENERIC MAP(
initial_phase_select => dpa_initial_phase_value
)
PORT MAP(
clkin => clk0_ipd,
loaden => enable0_ipd,
enable => ini_phase_select_enable,
loadenout=>ini_dpa_load,
clkout => ini_dpa_clk
);
ini_phase_select_enable <= '1' when (enable_dpa_initial_phase_selection = "on") else '0';
-- DPA circuitary
dpareg0 : stratixiii_lvds_reg
PORT MAP (
d => in_reg_data,
clk => ini_dpa_clk,
clrn => vcc,
prn => vcc,
ena => vcc,
q => dpareg0_out
);
dpareg1 : stratixiii_lvds_reg
PORT MAP ( d => dpareg0_out,
clk => ini_dpa_clk,
clrn => vcc,
prn => vcc,
ena => vcc,
q => dpareg1_out
);
dpa_circuit: stratixiii_dpa_block
GENERIC MAP(
net_ppm_variation => net_ppm_variation,
is_negative_ppm_drift => is_negative_ppm_drift,
enable_soft_cdr_mode => enable_soft_cdr
)
PORT MAP(
clkin => ini_dpa_clk,
dpareset => dpareset_ipd,
dpahold => dpahold_ipd,
datain => dpareg1_out,
clkout => dpa_clk_shift,
dataout => dpa_data_shift,
dpalock => lock_tmp
);
dpa_clk <= dpa_clk_shift when ((enable_soft_cdr = "on") or (enable_dpa = "on")) else '0' ;
dpa_rst <= dpareset_ipd when ((enable_soft_cdr = "on") or (enable_dpa = "on")) else '0' ;
-- PCLK and lloaden generation
clk_forward: stratixiii_pclk_divider
GENERIC MAP (
clk_divide_by => channel_width )
PORT MAP(
clkin => dpa_clk,
lloaden => lloaden,
clkout => divfwdclk_tmp
);
-- FIFO
s_fifo : stratixiii_lvds_rx_fifo
GENERIC MAP ( channel_width => channel_width
)
PORT MAP ( wclk => dpa_clk,
rclk => fifo_rclk,
fiforst => fifo_reset,
dparst => dpa_rst,
datain => fifo_datain,
dataout => fifo_dataout
);
fifo_rclk <= clk0_ipd WHEN (enable_dpa = "on") ELSE gnd ;
fifo_wclk <= dpa_clk ;
fifo_datain <= dpa_data_shift WHEN (enable_dpa = "on") ELSE gnd ;
fifo_reset <= (NOT devpor) OR (NOT devclrn) OR fiforeset_ipd OR dpa_rst OR reset_fifo ;
-- Bit Slip
s_bslip : stratixiii_lvds_rx_bitslip
GENERIC MAP ( bitslip_rollover => data_align_rollover,
channel_width => channel_width,
x_on_bitslip => x_on_bitslip
)
PORT MAP ( clk0 => s_bitslip_clk,
bslipcntl => bitslip_ipd,
bsliprst => bitslip_reset,
datain => slip_datain,
bslipmax => bitslipmax,
dataout => slip_dataout
);
bitslip_reset <= (NOT devpor) OR (NOT devclrn) OR bitslipreset_ipd ;
slip_datain_tmp <= fifo_dataout when (enable_dpa = "on" and dpaswitch_ipd = '1') else datain_reg_tmp ;
slip_datain <= dpa_data_shift when(enable_soft_cdr = "on") else slip_datain_tmp;
s_bitslip_clk <= dpa_clk when (enable_soft_cdr = "on") else clk0_ipd;
-- DESERIALISER
rxload_reg : stratixiii_lvds_reg
PORT MAP ( d => loaden,
clk => s_bitslip_clk,
ena => vcc,
clrn => vcc,
prn => vcc,
q => rxload
);
loaden <= lloaden when (enable_soft_cdr = "on") else ini_dpa_load;
s_deser : stratixiii_lvds_rx_deser
GENERIC MAP (channel_width => channel_width
)
PORT MAP (clk => s_bitslip_clk,
datain => slip_dataout,
devclrn => devclrn,
devpor => devpor,
dataout => deser_dataout
);
output_reg : stratixiii_lvds_rx_parallel_reg
GENERIC MAP ( channel_width => channel_width
)
PORT MAP ( clk => s_bitslip_clk,
enable => rxload,
datain => deser_dataout,
devpor => devpor,
devclrn => devclrn,
dataout => dataout
);
dpa_is_locked <= gnd;
dpaclkout <= dpa_clk_shift;
postdpaserialdataout <= dpa_data_shift ;
serialdataout <= datain_ipd;
divfwdclk <= divfwdclk_tmp ;
END vital_arm_lvds_receiver;
----------------------------------------------------------------------------------
--Module Name: stratixiii_pseudo_diff_out --
--Description: Simulation model for Stratix III Pseudo Differential --
-- Output Buffer --
----------------------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_pseudo_diff_out IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
lpm_type : string := "stratixiii_pseudo_diff_out"
);
PORT (
i : IN std_logic := '0';
o : OUT std_logic;
obar : OUT std_logic
);
END stratixiii_pseudo_diff_out;
ARCHITECTURE arch OF stratixiii_pseudo_diff_out IS
SIGNAL i_ipd : std_logic ;
SIGNAL o_tmp : std_logic ;
SIGNAL obar_tmp : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
end block;
PROCESS( i_ipd)
BEGIN
IF (i_ipd = '0') THEN
o_tmp <= '0';
obar_tmp <= '1';
ELSE
IF (i_ipd = '1') THEN
o_tmp <= '1';
obar_tmp <= '0';
ELSE
o_tmp <= i_ipd;
obar_tmp <= i_ipd;
END IF;
END IF;
END PROCESS;
---------------------
-- Path Delay Section
----------------------
PROCESS( o_tmp,obar_tmp)
variable o_VitalGlitchData : VitalGlitchDataType;
variable obar_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => o_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE)),
GlitchData => o_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01 (
OutSignal => obar,
OutSignalName => "obar",
OutTemp => obar_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_obar, TRUE)),
GlitchData => obar_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
--------------------------------------------------------------
--
-- Entity Name : stratixiii_bias_logic
--
-- Description : STRATIXIII Bias Block's Logic Block
-- VHDL simulation model
--
--------------------------------------------------------------
LIBRARY IEEE;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use IEEE.std_logic_1164.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_bias_logic IS
GENERIC (
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_shiftnld : VitalDelayType01 := DefPropDelay01;
tipd_captnupdt : VitalDelayType01 := DefPropDelay01;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
captnupdt : in std_logic := '0';
mainclk : out std_logic := '0';
updateclk : out std_logic := '0';
capture : out std_logic := '0';
update : out std_logic := '0'
);
attribute VITAL_LEVEL0 of stratixiii_bias_logic : ENTITY IS TRUE;
end stratixiii_bias_logic;
ARCHITECTURE vital_bias_logic of stratixiii_bias_logic IS
attribute VITAL_LEVEL0 of vital_bias_logic : ARCHITECTURE IS TRUE;
signal clk_ipd : std_logic := '0';
signal shiftnld_ipd : std_logic := '0';
signal captnupdt_ipd : std_logic := '0';
begin
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (shiftnld_ipd, shiftnld, tipd_shiftnld);
VitalWireDelay (captnupdt_ipd, captnupdt, tipd_captnupdt);
end block;
process (clk_ipd, shiftnld_ipd, captnupdt_ipd)
variable select_tmp : std_logic_vector(1 DOWNTO 0) := (others => '0');
begin
select_tmp := captnupdt_ipd & shiftnld_ipd;
case select_tmp IS
when "10"|"11" =>
mainclk <= '0';
updateclk <= clk_ipd;
capture <= '1';
update <= '0';
when "01" =>
mainclk <= '0';
updateclk <= clk_ipd;
capture <= '0';
update <= '0';
when "00" =>
mainclk <= clk_ipd;
updateclk <= '0';
capture <= '0';
update <= '1';
when others =>
mainclk <= '0';
updateclk <= '0';
capture <= '0';
update <= '0';
end case;
end process;
end vital_bias_logic;
--------------------------------------------------------------
--
-- Entity Name : stratixiii_bias_generator
--
-- Description : STRATIXIII Bias Generator VHDL simulation model
--
--------------------------------------------------------------
LIBRARY IEEE;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use IEEE.std_logic_1164.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_bias_generator IS
GENERIC (
tipd_din : VitalDelayType01 := DefPropDelay01;
tipd_mainclk : VitalDelayType01 := DefPropDelay01;
tipd_updateclk : VitalDelayType01 := DefPropDelay01;
tipd_update : VitalDelayType01 := DefPropDelay01;
tipd_capture : VitalDelayType01 := DefPropDelay01;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
din : in std_logic := '0';
mainclk : in std_logic := '0';
updateclk : in std_logic := '0';
capture : in std_logic := '0';
update : in std_logic := '0';
dout : out std_logic := '0'
);
attribute VITAL_LEVEL0 of stratixiii_bias_generator : ENTITY IS TRUE;
end stratixiii_bias_generator;
ARCHITECTURE vital_bias_generator of stratixiii_bias_generator IS
attribute VITAL_LEVEL0 of vital_bias_generator : ARCHITECTURE IS TRUE;
CONSTANT TOTAL_REG : integer := 252;
signal din_ipd : std_logic := '0';
signal mainclk_ipd : std_logic := '0';
signal updateclk_ipd : std_logic := '0';
signal update_ipd : std_logic := '0';
signal capture_ipd : std_logic := '0';
signal generator_reg : std_logic_vector((TOTAL_REG - 1) DOWNTO 0) := (others => '0');
signal update_reg : std_logic_vector((TOTAL_REG - 1) DOWNTO 0) := (others => '0');
signal dout_tmp : std_logic := '0';
signal i : integer := 0;
begin
WireDelay : block
begin
VitalWireDelay (din_ipd, din, tipd_din);
VitalWireDelay (mainclk_ipd, mainclk, tipd_mainclk);
VitalWireDelay (updateclk_ipd, updateclk, tipd_updateclk);
VitalWireDelay (update_ipd, update, tipd_update);
VitalWireDelay (capture_ipd, capture, tipd_capture);
end block;
process (mainclk_ipd)
begin
if (mainclk_ipd'event AND (mainclk_ipd = '1') AND (mainclk_ipd'last_value = '0')) then
if ((capture_ipd = '0') AND (update_ipd = '1')) then
for i in 0 to (TOTAL_REG - 1)
loop
generator_reg(i) <= update_reg(i);
end loop;
end if;
end if;
end process;
process (updateclk_ipd)
begin
if (updateclk_ipd'event AND (updateclk_ipd = '1') AND (updateclk_ipd'last_value = '0')) then
dout_tmp <= update_reg(TOTAL_REG - 1);
if ((capture_ipd = '0') AND (update_ipd = '0')) then
for i in 1 to (TOTAL_REG - 1)
loop
update_reg(i) <= update_reg(i - 1);
end loop;
update_reg(0) <= din_ipd;
elsif ((capture_ipd = '1') AND (update_ipd = '0')) then
for i in 1 to (TOTAL_REG - 1)
loop
update_reg(i) <= generator_reg(i);
end loop;
end if;
end if;
end process;
dout <= dout_tmp;
end vital_bias_generator;
--------------------------------------------------------------
--
-- Entity Name : stratixiii_bias_block
--
-- Description : STRATIXIII Bias Block VHDL simulation model
--
--------------------------------------------------------------
LIBRARY IEEE;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use IEEE.std_logic_1164.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_bias_block IS
GENERIC (
lpm_type : string := "stratixiii_bias_block";
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_shiftnld : VitalDelayType01 := DefPropDelay01;
tipd_captnupdt : VitalDelayType01 := DefPropDelay01;
tipd_din : VitalDelayType01 := DefPropDelay01;
tsetup_din_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_shiftnld_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_captnupdt_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_din_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_shiftnld_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_captnupdt_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_dout_posedge : VitalDelayType01 := DefPropDelay01;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
captnupdt : in std_logic := '0';
din : in std_logic := '0';
dout : out std_logic := '0'
);
attribute VITAL_LEVEL0 of stratixiii_bias_block : ENTITY IS TRUE;
end stratixiii_bias_block;
ARCHITECTURE vital_bias_block of stratixiii_bias_block IS
COMPONENT stratixiii_bias_logic
GENERIC (
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_shiftnld : VitalDelayType01 := DefPropDelay01;
tipd_captnupdt : VitalDelayType01 := DefPropDelay01;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
captnupdt : in std_logic := '0';
mainclk : out std_logic := '0';
updateclk : out std_logic := '0';
capture : out std_logic := '0';
update : out std_logic := '0'
);
end COMPONENT;
COMPONENT stratixiii_bias_generator
GENERIC (
tipd_din : VitalDelayType01 := DefPropDelay01;
tipd_mainclk : VitalDelayType01 := DefPropDelay01;
tipd_updateclk : VitalDelayType01 := DefPropDelay01;
tipd_update : VitalDelayType01 := DefPropDelay01;
tipd_capture : VitalDelayType01 := DefPropDelay01;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
din : in std_logic := '0';
mainclk : in std_logic := '0';
updateclk : in std_logic := '0';
capture : in std_logic := '0';
update : in std_logic := '0';
dout : out std_logic := '0'
);
end COMPONENT;
signal mainclk_wire : std_logic := '0';
signal updateclk_wire : std_logic := '0';
signal capture_wire : std_logic := '0';
signal update_wire : std_logic := '0';
begin
logic_block : stratixiii_bias_logic
PORT MAP (
clk => clk,
shiftnld => shiftnld,
captnupdt => captnupdt,
mainclk => mainclk_wire,
updateclk => updateclk_wire,
capture => capture_wire,
update => update_wire
);
bias_generator : stratixiii_bias_generator
PORT MAP (
din => din,
mainclk => mainclk_wire,
updateclk => updateclk_wire,
capture => capture_wire,
update => update_wire,
dout => dout
);
end vital_bias_block;
-------------------------------------------------------------------
--
-- Entity Name : stratixiii_tsdblock
--
-- Description : Stratix III TSDBLOCK VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.stratixiii_atom_pack.all;
entity stratixiii_tsdblock is
generic (
poi_cal_temperature : integer := 85;
clock_divider_enable : string := "on";
clock_divider_value : integer := 40;
sim_tsdcalo : integer := 0;
user_offset_enable : string := "off";
lpm_type : string := "stratixiii_tsdblock"
);
port (
offset : in std_logic_vector(5 downto 0) := (OTHERS => '0');
clk : in std_logic := '0';
ce : in std_logic := '0';
clr : in std_logic := '0';
testin : in std_logic_vector(7 downto 0) := (OTHERS => '0');
tsdcalo : out std_logic_vector(7 downto 0);
tsdcaldone : out std_logic;
fdbkctrlfromcore : in std_logic := '0';
compouttest : in std_logic := '0';
tsdcompout : out std_logic;
offsetout : out std_logic_vector(5 downto 0)
);
end stratixiii_tsdblock;
architecture architecture_tsdblock of stratixiii_tsdblock is
begin
end architecture_tsdblock; -- end of stratixiii_tsdblock
| gpl-2.0 | 6de7724a96c82ab889d2aa8934581f2b | 0.459353 | 4.245558 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/lab3_project.xpr/project_1/project_1.ipdefs/ip_0/RecComp_cnn_lab_convolve_kernel_1_0/hdl/ip/convolve_kernel_ap_fmul_6_max_dsp_32.vhd | 1 | 14,037 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_5;
USE floating_point_v7_1_5.floating_point_v7_1_5;
ENTITY convolve_kernel_ap_fmul_6_max_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END convolve_kernel_ap_fmul_6_max_dsp_32;
ARCHITECTURE convolve_kernel_ap_fmul_6_max_dsp_32_arch OF convolve_kernel_ap_fmul_6_max_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF convolve_kernel_ap_fmul_6_max_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_5 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_5;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF convolve_kernel_ap_fmul_6_max_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_5,Vivado 2017.3";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF convolve_kernel_ap_fmul_6_max_dsp_32_arch : ARCHITECTURE IS "convolve_kernel_ap_fmul_6_max_dsp_32,floating_point_v7_1_5,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF convolve_kernel_ap_fmul_6_max_dsp_32_arch: ARCHITECTURE IS "convolve_kernel_ap_fmul_6_max_dsp_32,floating_point_v7_1_5,{x_ipProduct=Vivado 2017.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=5,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=1,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HA" &
"S_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=6,C_OPTIMIZATION=1,C_MULT_USAGE=3,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESET" &
"N=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED" &
"=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_result_tvalid: SIGNAL IS "XIL_INTERFACENAME M_AXIS_RESULT, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_b_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_B, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_a_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_A, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_PARAMETER OF aclken: SIGNAL IS "XIL_INTERFACENAME aclken_intf, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_PARAMETER OF aclk: SIGNAL IS "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF S_AXIS_OPERATION:M_AXIS_RESULT:S_AXIS_C:S_AXIS_B:S_AXIS_A, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 10000000, PHASE 0.000";
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
BEGIN
U0 : floating_point_v7_1_5
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 1,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 6,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 3,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END convolve_kernel_ap_fmul_6_max_dsp_32_arch;
| mit | a99a3756c3d3d21b3ce7de6d691f2833 | 0.660967 | 3.027173 | false | false | false | false |
dawsonjon/FPGA-TX | synthesis/nexys_4/tx/interpolate.vhd | 3 | 3,917 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity interpolate is
generic(
interpolation_factor : integer := 8192;
output_width : integer := 24;
width : integer := 8
);
port(
clk : in std_logic;
rst : in std_logic;
input : in std_logic_vector(width - 1 downto 0);
input_stb : in std_logic;
input_ack : out std_logic;
output_0 : out std_logic_vector(output_width - 1 downto 0);
output_1 : out std_logic_vector(output_width - 1 downto 0);
output_2 : out std_logic_vector(output_width - 1 downto 0);
output_3 : out std_logic_vector(output_width - 1 downto 0);
output_4 : out std_logic_vector(output_width - 1 downto 0);
output_5 : out std_logic_vector(output_width - 1 downto 0);
output_6 : out std_logic_vector(output_width - 1 downto 0);
output_7 : out std_logic_vector(output_width - 1 downto 0)
);
end entity interpolate;
architecture rtl of interpolate is
signal count : integer range 0 to interpolation_factor - 1 := 0;
signal last_input : signed(output_width - 1 downto 0) := (others => '0');
signal delta : signed(output_width - 1 downto 0) := (others => '0');
signal delta_d1 : signed(output_width - 1 downto 0) := (others => '0');
signal delta_d2 : signed(output_width - 1 downto 0) := (others => '0');
signal delta_d3 : signed(output_width - 1 downto 0) := (others => '0');
signal accum : signed(output_width - 1 downto 0) := (others => '0');
signal tree_0 : signed(output_width - 1 downto 0) := (others => '0');
signal tree_1 : signed(output_width - 1 downto 0) := (others => '0');
signal tree_00 : signed(output_width - 1 downto 0) := (others => '0');
signal tree_01 : signed(output_width - 1 downto 0) := (others => '0');
signal tree_10 : signed(output_width - 1 downto 0) := (others => '0');
signal tree_11 : signed(output_width - 1 downto 0) := (others => '0');
signal tree_000 : signed(output_width - 1 downto 0) := (others => '0');
signal tree_001 : signed(output_width - 1 downto 0) := (others => '0');
signal tree_010 : signed(output_width - 1 downto 0) := (others => '0');
signal tree_011 : signed(output_width - 1 downto 0) := (others => '0');
signal tree_100 : signed(output_width - 1 downto 0) := (others => '0');
signal tree_101 : signed(output_width - 1 downto 0) := (others => '0');
signal tree_110 : signed(output_width - 1 downto 0) := (others => '0');
signal tree_111 : signed(output_width - 1 downto 0) := (others => '0');
begin
process
begin
wait until rising_edge(clk);
if count = 0 then
count <= interpolation_factor-1;
last_input <= resize(signed(input), output_width);
delta <= resize(signed(input), output_width) - last_input;
input_ack <= '1';
else
count <= count - 1;
input_ack <= '0';
end if;
delta_d1 <= delta;
delta_d2 <= delta_d1;
delta_d3 <= delta_d2;
accum <= accum + (delta(output_width-4 downto 0) & "000");
tree_0 <= accum;
tree_1 <= accum + (delta_d1(output_width-3 downto 0) & "00");
tree_00 <= tree_0;
tree_01 <= tree_0 + (delta_d2(output_width-2 downto 0) & '0');
tree_10 <= tree_1;
tree_11 <= tree_1 + (delta_d2(output_width-2 downto 0) & '0');
tree_000 <= tree_00;
tree_001 <= tree_00 + delta_d3;
tree_010 <= tree_01;
tree_011 <= tree_01 + delta_d3;
tree_100 <= tree_10;
tree_101 <= tree_10 + delta_d3;
tree_110 <= tree_11;
tree_111 <= tree_11 + delta_d3;
output_0 <= std_logic_vector(tree_000);
output_1 <= std_logic_vector(tree_001);
output_2 <= std_logic_vector(tree_010);
output_3 <= std_logic_vector(tree_011);
output_4 <= std_logic_vector(tree_100);
output_5 <= std_logic_vector(tree_101);
output_6 <= std_logic_vector(tree_110);
output_7 <= std_logic_vector(tree_111);
end process;
end rtl;
| mit | 7a8e9d44699288134bebbab126efc07a | 0.603013 | 3.17423 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-gr-xc3s-1500/config.vhd | 1 | 8,831 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := spartan3;
constant CFG_MEMTECH : integer := spartan3;
constant CFG_PADTECH : integer := spartan3;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := spartan3;
constant CFG_CLKMUL : integer := (4);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (4);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 4;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2;
constant CFG_ATBSZ : integer := 2;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- USB DSU
constant CFG_GRUSB_DCL : integer := 0;
constant CFG_GRUSB_DCL_UIFACE : integer := 1;
constant CFG_GRUSB_DCL_DW : integer := 8;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000008#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 1;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 1 + 0;
-- AHB status register
constant CFG_AHBSTAT : integer := 0;
constant CFG_AHBSTATN : integer := 1;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 16;
-- CAN 2.0 interface
constant CFG_CAN : integer := 0;
constant CFG_CAN_NUM : integer := 1;
constant CFG_CANIO : integer := 16#0#;
constant CFG_CANIRQ : integer := 0;
constant CFG_CANSEPIRQ: integer := 0;
constant CFG_CAN_SYNCRST : integer := 0;
constant CFG_CANFT : integer := 0;
-- GR USB 2.0 Device Controller
constant CFG_GRUSBDC : integer := 0;
constant CFG_GRUSBDC_AIFACE : integer := 0;
constant CFG_GRUSBDC_UIFACE : integer := 1;
constant CFG_GRUSBDC_DW : integer := 8;
constant CFG_GRUSBDC_NEPI : integer := 1;
constant CFG_GRUSBDC_NEPO : integer := 1;
constant CFG_GRUSBDC_I0 : integer := 1024;
constant CFG_GRUSBDC_I1 : integer := 1024;
constant CFG_GRUSBDC_I2 : integer := 1024;
constant CFG_GRUSBDC_I3 : integer := 1024;
constant CFG_GRUSBDC_I4 : integer := 1024;
constant CFG_GRUSBDC_I5 : integer := 1024;
constant CFG_GRUSBDC_I6 : integer := 1024;
constant CFG_GRUSBDC_I7 : integer := 1024;
constant CFG_GRUSBDC_I8 : integer := 1024;
constant CFG_GRUSBDC_I9 : integer := 1024;
constant CFG_GRUSBDC_I10 : integer := 1024;
constant CFG_GRUSBDC_I11 : integer := 1024;
constant CFG_GRUSBDC_I12 : integer := 1024;
constant CFG_GRUSBDC_I13 : integer := 1024;
constant CFG_GRUSBDC_I14 : integer := 1024;
constant CFG_GRUSBDC_I15 : integer := 1024;
constant CFG_GRUSBDC_O0 : integer := 1024;
constant CFG_GRUSBDC_O1 : integer := 1024;
constant CFG_GRUSBDC_O2 : integer := 1024;
constant CFG_GRUSBDC_O3 : integer := 1024;
constant CFG_GRUSBDC_O4 : integer := 1024;
constant CFG_GRUSBDC_O5 : integer := 1024;
constant CFG_GRUSBDC_O6 : integer := 1024;
constant CFG_GRUSBDC_O7 : integer := 1024;
constant CFG_GRUSBDC_O8 : integer := 1024;
constant CFG_GRUSBDC_O9 : integer := 1024;
constant CFG_GRUSBDC_O10 : integer := 1024;
constant CFG_GRUSBDC_O11 : integer := 1024;
constant CFG_GRUSBDC_O12 : integer := 1024;
constant CFG_GRUSBDC_O13 : integer := 1024;
constant CFG_GRUSBDC_O14 : integer := 1024;
constant CFG_GRUSBDC_O15 : integer := 1024;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- UART 2
constant CFG_UART2_ENABLE : integer := 0;
constant CFG_UART2_FIFO : integer := 1;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- Spacewire interface
constant CFG_SPW_EN : integer := 0;
constant CFG_SPW_NUM : integer := 1;
constant CFG_SPW_AHBFIFO : integer := 4;
constant CFG_SPW_RXFIFO : integer := 16;
constant CFG_SPW_RMAP : integer := 0;
constant CFG_SPW_RMAPBUF : integer := 4;
constant CFG_SPW_RMAPCRC : integer := 0;
constant CFG_SPW_NETLIST : integer := 0;
constant CFG_SPW_FT : integer := 0;
constant CFG_SPW_GRSPW : integer := 2;
constant CFG_SPW_RXUNAL : integer := 0;
constant CFG_SPW_DMACHAN : integer := 1;
constant CFG_SPW_PORTS : integer := 1;
constant CFG_SPW_INPUT : integer := 2;
constant CFG_SPW_OUTPUT : integer := 0;
constant CFG_SPW_RTSAME : integer := 0;
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 1;
constant CFG_VGA_ENABLE : integer := 0;
constant CFG_SVGA_ENABLE : integer := 1;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-2.0 | 3b97456345c6e9a6bb92f521486f7cf7 | 0.655418 | 3.581103 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/grlib/stdlib/testlib.vhd | 1 | 31,840 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- package: testlib
-- file: testlib.vhd
-- author: Marko Isomaki - Aeroflex Gaisler
-- description: package for common vhdl functions for testbenches
------------------------------------------------------------------------------
-- pragma translate_off
library std;
use std.standard.all;
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library grlib;
use grlib.stdio.all;
use grlib.stdlib.tost;
-- pragma translate_on
package testlib is
-- pragma translate_off
type octet_vector is array (natural range <>) of std_logic_vector(7 downto 0);
subtype data_vector8 is octet_vector;
type data_vector16 is array (natural range <>) of std_logic_vector(15 downto 0);
type data_vector32 is array (natural range <>) of std_logic_vector(31 downto 0);
type data_vector64 is array (natural range <>) of std_logic_vector(63 downto 0);
type data_vector128 is array (natural range <>) of std_logic_vector(127 downto 0);
type data_vector256 is array (natural range <>) of std_logic_vector(255 downto 0);
type nibble_vector is array (natural range <>) of std_logic_vector(3 downto 0);
subtype data_vector is data_vector32;
-----------------------------------------------------------------------------
-- compare function handling '-'. c is the expected data parameter. If it is
--'-' or 'U' then this bit is not compared. Returns true if the vectors match
-----------------------------------------------------------------------------
function compare(o, c: in std_logic_vector) return boolean;
-----------------------------------------------------------------------------
-- compare function handling '-'
-----------------------------------------------------------------------------
function compare(o, c: in std_ulogic_vector) return boolean;
-----------------------------------------------------------------------------
-- this procedure prints a message to standard output. Also includes the time
-- at which it occurs.
-----------------------------------------------------------------------------
procedure print(
constant comment: in string := "-";
constant severe: in severity_level := note;
constant screen: in boolean := true);
-----------------------------------------------------------------------------
-- synchronisation with respect to clock and with output offset
-----------------------------------------------------------------------------
procedure synchronise(
signal clock: in std_ulogic;
constant offset: in time := 5 ns;
constant enable: in boolean := true);
-----------------------------------------------------------------------------
-- this procedure initialises the test error counters. Used in testbenches
-- with a test variable to check if a subtest has failed and at the end how
-- many subtests have failed. This procedure is called before the first
-- subtest
-----------------------------------------------------------------------------
procedure tinitialise(
variable test: inout boolean;
variable testcount: inout integer);
-----------------------------------------------------------------------------
-- this procedure completes the sub-test. Called at the end of each subtest
-----------------------------------------------------------------------------
procedure tintermediate(
variable test: inout boolean;
variable testcount: inout integer);
-----------------------------------------------------------------------------
-- this procedure completes the test. Called at the end of the complete test
-----------------------------------------------------------------------------
procedure tterminate(
variable test: inout boolean;
variable testcount: inout integer);
-----------------------------------------------------------------------------
-- check std_logic_vector array
-----------------------------------------------------------------------------
procedure check(
variable tp: inout boolean;
constant received: in std_logic_vector;
constant expected: in std_logic_vector;
constant message: in string := "");
-----------------------------------------------------------------------------
-- check std_logic
-----------------------------------------------------------------------------
procedure check(
variable tp: inout boolean;
constant received: in std_logic;
constant expected: in std_logic;
constant message: in string := "");
-----------------------------------------------------------------------------
-- check std_ulogic_vector array
-----------------------------------------------------------------------------
procedure check(
variable tp: inout boolean;
constant received: in std_ulogic_vector;
constant expected: in std_ulogic_vector;
constant message: in string := "");
-----------------------------------------------------------------------------
-- check natural
-----------------------------------------------------------------------------
procedure check(
variable tp: inout boolean;
constant received: in natural;
constant expected: in natural;
constant message: in string := "");
-----------------------------------------------------------------------------
-- check time
-----------------------------------------------------------------------------
procedure check(
variable tp: inout boolean;
constant received: in time;
constant expected: in time;
constant spread: in time;
constant message: in string := "");
-----------------------------------------------------------------------------
-- check boolean
-----------------------------------------------------------------------------
procedure check(
variable tp: inout boolean;
constant received: in boolean;
constant expected: in boolean;
constant message: in string := "");
-----------------------------------------------------------------------------
-- Convert Data_Vector to Octet_Vector
-----------------------------------------------------------------------------
function conv_octet_vector(
constant d: in data_vector)
return octet_vector;
-----------------------------------------------------------------------------
-- Convert Octet_Vector to Data_Vector, with padding
-----------------------------------------------------------------------------
function conv_data_vector(
constant o: in octet_vector)
return data_vector;
procedure compare(
constant data: in octet_vector;
constant cxdata: in octet_vector;
variable tP: inout boolean);
----------------------------------------------------------------------------
-- Read file contents to octet vector
----------------------------------------------------------------------------
--Expects data only in hex with four bytes on each line.
procedure readfile(
constant filename: in string := "";
constant filetype: in integer := 0;
constant size: in integer := 0;
variable dataout: out octet_vector);
--Reads bytes from a file with the format packets are output from ethereal
procedure readfile(
constant filename: in string := "";
constant size: in integer := 0;
variable dataout: out octet_vector);
----------------------------------------------------------------------------
-- Read file contents to data_vector
----------------------------------------------------------------------------
--Expects data only in hex with four bytes on each line.
procedure readfile(
constant filename: in string := "";
constant size: in integer := 0;
variable dataout: out data_vector);
--generates an random integer from 0 to the maximum value specified with max
procedure gen_rand_int(
constant max : in real;
variable seed1 : inout positive;
variable seed2 : inout positive;
variable rand : out integer);
--reverses std_logic_vector
function reverse(din : std_logic_vector) return std_logic_vector;
-- Returns offset to start of valid data for an access of size 'size' in
-- AMBA data vector
function ahb_doff (
constant dw : integer;
constant size : integer; -- access size
constant addr : std_logic_vector(4 downto 0))
return integer;
-- pragma translate_on
end package testlib;
-- pragma translate_off
--============================================================================--
package body testlib is
-----------------------------------------------------------------------------
-- compare function handling '-'
-----------------------------------------------------------------------------
function compare(o, c: in std_logic_vector) return boolean is
variable t: std_logic_vector(o'range) := c;
variable result: boolean;
begin
result := true;
for i in o'range loop
if not (o(i)=t(i) or t(i)='-' or t(i)='U') then
result := false;
end if;
end loop;
return result;
end function compare;
-----------------------------------------------------------------------------
-- compare function handling '-'
-----------------------------------------------------------------------------
function compare(o, c: in std_ulogic_vector) return boolean is
variable t: std_ulogic_vector(o'range) := c;
variable result: boolean;
begin
result := true;
for i in o'range loop
if not (o(i)=t(i) or t(i)='-' or t(i)='U') then
result := false;
end if;
end loop;
return result;
end function compare;
-----------------------------------------------------------------------------
-- this procedure prints a message to standard output
-----------------------------------------------------------------------------
procedure print(
constant comment: in string := "-";
constant severe: in severity_level := note;
constant screen: in boolean := true) is
variable l: line;
begin
if screen then
write(l, now, right, 15);
write(l, " : " & comment);
if severe = warning then
write(l, string'(" # warning, "));
elsif severe = error then
write(l, string'(" # error, "));
elsif severe = failure then
write(l, string'(" # failure, "));
end if;
writeline(output, l);
end if;
end procedure print;
-----------------------------------------------------------------------------
-- synchronisation with respect to clock and with output offset
-----------------------------------------------------------------------------
procedure synchronise(
signal clock: in std_ulogic;
constant offset: in time := 5 ns;
constant enable: in boolean := true) is
begin
if enable then
wait until clock = '1'; -- synchronise
wait for offset; -- output offset delay
end if;
end procedure synchronise;
-----------------------------------------------------------------------------
-- this procedure initialises the test error counters
-----------------------------------------------------------------------------
procedure tinitialise(
variable test: inout boolean;
variable testcount: inout integer) is
begin
--------------------------------------------------------------------------
-- initialise test status
--------------------------------------------------------------------------
test := true; -- reset any errors
testcount := 0;
print("--=========================================================--");
print("*** test initialised ¨ ***");
print("--=========================================================--");
end procedure tinitialise;
-----------------------------------------------------------------------------
-- this procedure completes the sub-test
-----------------------------------------------------------------------------
procedure tintermediate(
variable test: inout boolean;
variable testcount: inout integer) is
variable l: line;
begin
--------------------------------------------------------------------------
-- report test status
--------------------------------------------------------------------------
wait for 10 us;
print("--=========================================================--");
if test then
print("*** sub-test completed successfully ***");
if testcount > 0 then
write(l, now, right, 15);
write(l, string'(" : "));
write(l, testcount);
write(l, string'(" sub-test(s) ended with one or more errors."));
writeline(output, l);
end if;
else
print("*** sub-test completed with errors -- # error # -- ***");
testcount := testcount + 1;
test := true;
if testcount > 0 then
write(l, now, right, 15);
write(l, string'(" : "));
write(l, testcount);
write(l, string'(" sub-test(s) ended with one or more errors."));
writeline(output, l);
end if;
end if;
print("--=========================================================--");
end procedure tintermediate;
-----------------------------------------------------------------------------
-- this procedure completes the test
-----------------------------------------------------------------------------
procedure tterminate(
variable test: inout boolean;
variable testcount: inout integer) is
variable l: line;
begin
--------------------------------------------------------------------------
-- end of test
--------------------------------------------------------------------------
wait for 1 ms;
print("--=========================================================--");
if testcount = 0 then
print("*** test completed successfully ***");
else
print("*** test completed with errors -- # error # -- ***");
write(l, now, right, 15);
write(l, string'(" : "));
write(l, testcount);
write(l, string'(" sub-test(s) ended with one or more errors."));
writeline(output, l);
end if;
print("--=========================================================--");
report "---- end of test ----"
severity failure;
wait;
end procedure tterminate;
-----------------------------------------------------------------------------
-- check std_logic_vector array
-----------------------------------------------------------------------------
procedure check(
variable tp: inout boolean;
constant received: in std_logic_vector;
constant expected: in std_logic_vector;
constant message: in string := "") is
variable l: line;
constant padding: std_logic_vector(1 to
(4-(received'length mod 4))) :=
(others => '0');
begin
if not compare(received, expected) then
write(l, now, right, 15);
write(l, string'(" : ") & message & string'(" :"));
write(l, string'(" received: "));
if padding'length > 0 and padding'length < 4 then
hwrite(l, padding & std_logic_vector(received));
else
hwrite(l, std_logic_vector(received));
end if;
write(l, string'(" expected: "));
if padding'length > 0 and padding'length < 4 then
hwrite(l, padding & std_logic_vector(expected));
else
hwrite(l, std_logic_vector(expected));
end if;
write(l, string'(" # error"));
writeline(output, l);
tp := false;
end if;
end procedure check;
-----------------------------------------------------------------------------
-- check std_logic
-----------------------------------------------------------------------------
procedure check(
variable tp: inout boolean;
constant received: in std_logic;
constant expected: in std_logic;
constant message: in string := "") is
variable l: line;
begin
if not (to_x01z(received)=to_x01z(expected)) then
write(l, now, right, 15);
write(l, string'(" : ") & message & string'(" :"));
write(l, string'(" received: "));
write(l, received);
write(l, string'(" expected: "));
write(l, expected);
write(l, string'(" # error"));
writeline(output, l);
tp := false;
end if;
end procedure check;
-----------------------------------------------------------------------------
-- check std_ulogic_vector array
-----------------------------------------------------------------------------
procedure check(
variable tp: inout boolean;
constant received: in std_ulogic_vector;
constant expected: in std_ulogic_vector;
constant message: in string := "") is
variable l: line;
constant padding: std_ulogic_vector(1 to
(4-(received'length mod 4))) :=
(others => '0');
begin
if not compare(received, expected) then
write(l, now, right, 15);
write(l, string'(" : ") & message & string'(" :"));
write(l, string'(" received: "));
if padding'length > 0 and padding'length < 4 then
hwrite(l, std_logic_vector(padding) & std_logic_vector(received));
else
hwrite(l, std_logic_vector(received));
end if;
write(l, string'(" expected: "));
if padding'length > 0 and padding'length < 4 then
hwrite(l, std_logic_vector(padding) & std_logic_vector(expected));
else
hwrite(l, std_logic_vector(expected));
end if;
write(l, string'(" # error"));
writeline(output, l);
tp := false;
end if;
end procedure check;
-----------------------------------------------------------------------------
-- check natural
-----------------------------------------------------------------------------
procedure check(
variable tp: inout boolean;
constant received: in natural;
constant expected: in natural;
constant message: in string := "") is
variable l: line;
begin
if received /= expected then
write(l, now, right, 15);
write(l, string'(" : ") & message & string'(" :"));
write(l, string'(" received: "));
write(l, received);
write(l, string'(" expected: "));
write(l, expected);
write(l, string'(" # error"));
writeline(output, l);
tp := false;
end if;
end procedure check;
-----------------------------------------------------------------------------
-- check time
-----------------------------------------------------------------------------
procedure check(
variable tp: inout boolean;
constant received: in time;
constant expected: in time;
constant spread: in time;
constant message: in string := "") is
variable l: line;
begin
if (received > expected+spread) or
(received < expected-spread) then
write(l, now, right, 15);
write(l, string'(" : ") & message & string'(" :"));
write(l, string'(" received: "));
write(l, received);
write(l, string'(" expected: "));
write(l, expected);
write(l, string'(" # error"));
writeline(output, l);
tp := false;
end if;
end procedure check;
-----------------------------------------------------------------------------
-- check boolean
-----------------------------------------------------------------------------
procedure check(
variable tp: inout boolean;
constant received: in boolean;
constant expected: in boolean;
constant message: in string := "") is
variable l: line;
begin
if received /= expected then
write(l, now, right, 15);
write(l, string'(" : ") & message & string'(" :"));
write(l, string'(" received: "));
write(l, received);
write(l, string'(" expected: "));
write(l, expected);
write(l, string'(" # error"));
writeline(output, l);
tp := false;
end if;
end procedure check;
-----------------------------------------------------------------------------
-- Convert Data_Vector to Octet_Vector
-----------------------------------------------------------------------------
function conv_octet_vector(
constant d: in data_vector)
return octet_vector is
variable o: octet_vector(0 to d'Length*4-1);
begin
for i in o'range loop
o(i) := d(i/4)((3-(i mod 4))*8+7 downto (3-(i mod 4))*8);
end loop;
return o;
end function conv_octet_vector;
-----------------------------------------------------------------------------
-- Convert Octet_Vector to Data_Vector, with padding
-----------------------------------------------------------------------------
function conv_data_vector(
constant o: in octet_vector)
return data_vector is
variable d: data_vector(0 to (1+(o'Length-1)/4)-1);
begin
for i in o'Range loop
d(i/4)((3-(i mod 4))*8+7 downto (3-(i mod 4))*8) := o(i);
end loop;
return d;
end function conv_data_vector;
procedure compare(
constant data: in octet_vector;
constant cxdata: in octet_vector;
variable tp: inout boolean) is
begin
if (data'length /= cxdata'length) then
tp := false;
print("compare error: lengths do not match");
else
for i in data'low to data'low+data'length-1 loop
if not compare(data(i), cxdata(i)) then
tp := false;
print("compare error. index: " & tost(i) & " data: " & tost(data(i)) & " expected: " & tost(cxdata(i)));
end if;
end loop;
end if;
end compare;
function FromChar(C: Character) return Std_Logic_Vector is
variable R: Std_Logic_Vector(0 to 3);
begin
case C is
when '0' => R := "0000";
when '1' => R := "0001";
when '2' => R := "0010";
when '3' => R := "0011";
when '4' => R := "0100";
when '5' => R := "0101";
when '6' => R := "0110";
when '7' => R := "0111";
when '8' => R := "1000";
when '9' => R := "1001";
when 'A' => R := "1010";
when 'B' => R := "1011";
when 'C' => R := "1100";
when 'D' => R := "1101";
when 'E' => R := "1110";
when 'F' => R := "1111";
when 'a' => R := "1010";
when 'b' => R := "1011";
when 'c' => R := "1100";
when 'd' => R := "1101";
when 'e' => R := "1110";
when 'f' => R := "1111";
when others => R := "XXXX";
end case;
return R;
end FromChar;
procedure readfile(
constant filename: in string := "";
constant filetype: in integer := 0;
constant size: in integer := 0;
variable dataout: out octet_vector) is
file readfile: text;
variable l: line;
variable test: boolean := true;
variable count: integer := 0;
variable dtmp: std_logic_vector(31 downto 0);
variable data: octet_vector(0 to size-1);
variable i: integer := 0;
variable good: boolean := true;
variable c: character;
begin
if size /= 0 then
if filename = "" then
print("no file given");
else
if filetype = 0 then
file_open(readfile, filename, read_mode);
while not endfile(readfile) loop
readline(readfile, l);
hread(l, dtmp, test);
if (not test) then
print("illegal data in file");
exit;
end if;
for i in 0 to 3 loop
data(count) := dtmp(31-i*8 downto 24-i*8);
count := count + 1;
if count >= size then
exit;
end if;
end loop;
if count >= size then
exit;
end if;
end loop;
if count < size then
print("not enough data in file");
else
for i in 0 to size-1 loop
dataout(dataout'low+i) := data(i);
end loop;
end if;
else
file_open(readfile, filename, read_mode);
while not endfile(readfile) loop
readline(readfile, L);
while (i < 4) loop
Read(L, C, good);
if not good then
Print("Error in read data");
exit;
end if;
if (C = character'val(32)) or (C = character'val(160)) or (C = HT) then
next;
else
i := i + 1;
end if;
end loop;
i := 0;
while (i < 32) loop
Read(L, C, good);
if not good then
Print("Error in read data");
exit;
end if;
if (C = character'val(32)) or (C = character'val(160)) or (C = HT) then
next;
else
if (i mod 2) = 0 then
data(count)(7 downto 4) := fromchar(C);
else
data(count)(3 downto 0) := fromchar(C);
-- Print(tost(data(count)));
count := count + 1;
if count >= size then
exit;
end if;
end if;
i := i + 1;
end if;
end loop;
i := 0;
end loop;
if count < size then
Print("Not enough data in file");
else
dataout := data;
end if;
end if;
end if;
else
print("size is zero. no data read");
end if;
end procedure;
procedure readfile(
constant filename: in string := "";
constant size: in integer := 0;
variable dataout: out octet_vector) is
begin
readfile(filename, 0, size, dataout);
end procedure;
procedure readfile(
constant filename: in string := "";
constant size: in integer := 0;
variable dataout: out data_vector) is
file readfile: text;
variable l: line;
variable test: boolean := true;
variable count: integer := 0;
variable data: data_vector(0 to size/4);
begin
if size /= 0 then
if filename = "" then
print("no file given");
else
file_open(readfile, filename, read_mode);
while not endfile(readfile) loop
readline(readfile, l);
hread(l, data(count/4), test);
if (not test) then
print("illegal data in file");
exit;
end if;
count := count + 4;
if count >= size then
exit;
end if;
end loop;
if count < size then
print("not enough data in file");
else
if (size mod 4) = 0 then
dataout(dataout'low to dataout'low+data'high-1) :=
data(0 to data'high-1);
else
dataout(dataout'low to dataout'low+data'high) := data(0 to data'high);
end if;
end if;
end if;
else
print("size is zero. no data read");
end if;
end procedure;
procedure gen_rand_int(
constant max : in real;
variable seed1 : inout positive;
variable seed2 : inout positive;
variable rand : out integer) is
variable rand_tmp : real;
begin
uniform(seed1, seed2, rand_tmp);
rand := integer(floor(rand_tmp*max));
end procedure;
function reverse(din : std_logic_vector)
return std_logic_vector is
variable dout: std_logic_vector(din'REVERSE_RANGE);
begin
for i in din'RANGE loop dout(i) := din(i); end loop;
return dout;
end function reverse;
function ahb_doff (
constant dw : integer;
constant size : integer;
constant addr : std_logic_vector(4 downto 0))
return integer is
variable off : integer;
begin -- ahb_doff
if size < 256 and dw = 256 and addr(4) = '0' then off := 128; else off := 0; end if;
if size < 128 and dw >= 128 and addr(3) = '0' then off := off + 64; end if;
if size < 64 and dw >= 64 and addr(2) = '0' then off := off + 32; end if;
if size < 32 and addr(1) = '0' then off := off + 16; end if;
if size < 16 and addr(0) = '0' then off := off + 8; end if;
return off;
end ahb_doff;
end package body ; --=======================================--
-- pragma translate_on
| gpl-2.0 | 7d8bfb43de69a76e5e5aae02e02ed553 | 0.423587 | 5.166315 | false | true | false | false |
VerkhovtsovPavel/BSUIR_Labs | Master/POCP/My_Designs/Accum/src/OneHot.vhd | 1 | 3,063 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library accum;
use accum.OneHotAccum.all;
entity OneHot is
port (
CLK, RST, Start: in std_logic;
Stop: out std_logic
);
end OneHot;
architecture Beh of OneHot is
component MROM is
port (
RE: in std_logic;
ADDR: in mem_addr;
DOUT: out command
);
end component;
component MRAM is
port (
CLK: in std_logic;
RW: in std_logic;
ADDR: in mem_addr;
DIN: in operand;
DOUT: out operand
);
end component;
component DPATH is
port(
EN: in std_logic;
-- operation type
OT: in operation;
-- operand
OP1 : in operand;
RES: out operand;
-- zero flag
ZF: out std_logic
);
end component;
component CTRL1 is
port(
CLK, RST, Start: in std_logic;
Stop: out std_logic;
-- ROM
ROM_re: out std_logic;
ROM_addr: out mem_addr;
ROM_dout: in command;
-- RAM
RAM_rw: out std_logic;
RAM_addr: out mem_addr;
RAM_din: out operand;
RAM_dout: in operand;
-- datapath
DP_op1: out operand;
DP_ot: out operation;
DP_en: out std_logic;
DP_res: in operand;
DP_zf: in std_logic
);
end component;
signal rom_re: std_logic;
signal rom_addr: mem_addr;
signal rom_dout: command;
signal ram_rw: std_logic;
signal ram_addr: mem_addr;
signal ram_din: operand;
signal ram_dout: operand;
signal dp_op1: operand;
signal dp_ot: operation;
signal dp_en: std_logic;
signal dp_res: operand;
signal dp_zf: std_logic;
begin
UMRAM: MRAM
port map(
CLK => CLK,
RW => ram_rw,
ADDR => ram_addr,
DIN => ram_din,
DOUT => ram_dout
);
UMROM: MROM
port map (
RE => rom_re,
ADDR => rom_addr,
DOUT => rom_dout
);
UDPATH: DPATH
port map(
EN => dp_en,
OT => dp_ot,
OP1 => dp_op1,
RES => dp_res,
ZF => dp_zf
);
UCTRL1: CTRL1
port map(
CLK => CLK,
RST => RST,
START => Start,
STOP => STOP,
ROM_RE => rom_re,
ROM_ADDR => rom_addr,
ROM_DOUT => rom_dout,
RAM_RW => ram_rw,
RAM_ADDR => ram_addr,
RAM_DIN => ram_din,
RAM_DOUT => ram_dout,
DP_EN => dp_en,
DP_OT => dp_ot,
DP_OP1 => dp_op1,
DP_RES => dp_res,
DP_ZF => dp_zf
);
end Beh;
| mit | 2ce03c441f9725b3b23127c4e211bf2c | 0.429318 | 3.983095 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/pci/ptf/pt_pci_target.vhd | 1 | 31,894 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pt_pci_target
-- File: pt_pci_target.vhd
-- Author: Nils-Johan Wessman, Aeroflex Gaisler
-- Description: PCI Target emulator.
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library gaisler;
use gaisler.pt_pkg.all;
--use gaisler.pcilib.all;
--use gaisler.ambatest.all;
library std;
use std.textio.all;
entity pt_pci_target is
generic (
slot : integer := 0;
abits : integer := 10;
bars : integer := 1;
resptime : integer := 2;
latency : integer := 0;
rbuf : integer := 8;
stopwd : boolean := true;
tval : time := 7 ns;
conf : config_header_type := config_init;
dbglevel : integer := 1);
port (
-- PCI signals
pciin : in pci_type;
pciout : out pci_type;
-- TB signals
dbgi : in pt_pci_target_in_type;
dbgo : out pt_pci_target_out_type
);
end pt_pci_target;
architecture tb of pt_pci_target is
constant T_O : integer := 9;
constant word : std_logic_vector(2 downto 0) := "100";
type response_element_type;
type response_element_ptr is access response_element_type;
type response_element_type is record
id : integer;
resp : pt_pci_response_type;
nxt : response_element_ptr;
end record;
signal resp : pt_pci_response_type;
constant non_resp : pt_pci_response_type := ((others => '0'), 0, 0, 0, 0, 0, 0, 0, true);
type resp_print_type is array (0 to 8) of string(1 to 5);
constant resp_print : resp_print_type := ("-----", "retry", "-----", "disw ", "diswo", "abort", "parer", "debug", "-----");
signal pci_core : pt_pci_target_in_type;
signal core_pci : pt_pci_target_out_type;
type mem_type is array(0 to ((2**abits)-1)) of std_logic_vector(31 downto 0);
type state_type is(idle,b_busy,respwait,tabort,write,read,latw,retry,dis);
type reg_type is record
state : state_type;
pci : pci_type;
pcien : std_logic;
aden : std_logic;
paren : std_logic;
erren : std_logic;
write : std_logic;
waitcycles : integer;
latcnt : integer;
curword : integer;
first : boolean;
di : std_logic_vector(31 downto 0);
ad : std_logic_vector(31 downto 0);
comm : std_logic_vector(3 downto 0);
config : config_header_type;
cbe : std_logic_vector(3 downto 0); -- *** sub-word write
retrycnt : std_logic_vector(7 downto 0);
resp : pt_pci_response_type;
resp_addr : std_logic_vector(31 downto 0);
parerr : std_logic;
firstacc : std_logic;
perren : std_logic_vector(1 downto 0);
pcirad : std_logic_vector(31 downto 0);
pcircbe : std_logic_vector(3 downto 0);
sigperr : std_logic_vector(2 downto 0);
end record;
signal r,rin : reg_type;
signal do : std_logic_vector(31 downto 0);
procedure readconf(ad : in std_logic_vector(5 downto 0); data : out std_logic_vector(31 downto 0)) is
begin
case conv_integer(ad) is
when 0 => data(31 downto 16) := (conv_std_logic_vector(slot,4) & r.config.devid(11 downto 0));
data(15 downto 0) := r.config.vendid;
when 1 => data(31 downto 16) := r.config.status; data(15 downto 0) := r.config.command;
when 2 => data(31 downto 8) := r.config.class_code; data(7 downto 0) := r.config.revid;
when 3 => data(31 downto 24) := r.config.bist; data(23 downto 16) := r.config.header_type;
data(15 downto 8) := r.config.lat_timer; data(7 downto 0) := r.config.cache_lsize;
when 4 => data := r.config.bar(0)(31 downto abits) & zero32(abits-1 downto 0);
when 5 => if bars > 1 then data := r.config.bar(1)(31 downto 9) & zero32(8 downto 1) & '1';
else data := (others => '0'); end if;
when 6 => if bars > 2 then data := r.config.bar(2)(31 downto abits) & zero32(abits-1 downto 0);
else data := (others => '0'); end if;
when 7 => if bars > 3 then data := r.config.bar(3)(31 downto abits) & zero32(abits-1 downto 0);
else data := (others => '0'); end if;
when 8 => if bars > 4 then data := r.config.bar(4)(31 downto abits) & zero32(abits-1 downto 0);
else data := (others => '0'); end if;
when 9 => if bars > 5 then data := r.config.bar(5)(31 downto abits) & zero32(abits-1 downto 0);
else data := (others => '0'); end if;
when 10 => data := r.config.cis_p;
when 11 => data(31 downto 16) := r.config.subid; data(15 downto 0) := r.config.subvendid;
when 12 => data := r.config.exp_rom_ba;
when 13 => data(31 downto 24) := r.config.max_lat; data(23 downto 16) := r.config.min_gnt;
data(15 downto 8) := r.config.int_pin; data(7 downto 0) := r.config.int_line;
when others =>
end case;
end procedure;
procedure writeconf(ad : in std_logic_vector(5 downto 0);
data : in std_logic_vector(31 downto 0);
cbe : in std_logic_vector(3 downto 0);
vconfig : out config_header_type) is
variable new_data : std_logic_vector(31 downto 0);
begin
readconf(ad,new_data);
if cbe(3) = '0' then new_data(31 downto 24) := data(31 downto 24); end if;
if cbe(2) = '0' then new_data(23 downto 16) := data(23 downto 16); end if;
if cbe(1) = '0' then new_data(15 downto 8) := data(15 downto 8); end if;
if cbe(0) = '0' then new_data( 7 downto 0) := data( 7 downto 0); end if;
case conv_integer(ad) is
-- when 0 => vconfig.devid := new_data(31 downto 16); vconfig.vendid <= new_data(15 downto 0);
when 1 => vconfig.status := new_data(31 downto 16); vconfig.command := new_data(15 downto 0);
when 2 => vconfig.class_code := new_data(31 downto 8); vconfig.revid := new_data(7 downto 0);
when 3 => vconfig.bist := new_data(31 downto 24); vconfig.header_type := new_data(23 downto 16);
vconfig.lat_timer := new_data(15 downto 8); vconfig.cache_lsize := new_data(7 downto 0);
when 4 => vconfig.bar(0) := new_data;
when 5 => vconfig.bar(1) := new_data;
when 6 => vconfig.bar(2) := new_data;
when 7 => vconfig.bar(3) := new_data;
when 8 => vconfig.bar(4) := new_data;
when 9 => vconfig.bar(5) := new_data;
when 10 => vconfig.cis_p := new_data;
when 11 => vconfig.subid := new_data(31 downto 16); vconfig.subvendid := new_data(15 downto 0);
when 12 => vconfig.exp_rom_ba := new_data;
when 13 => vconfig.max_lat := new_data(31 downto 24); vconfig.min_gnt := new_data(23 downto 16);
vconfig.int_pin := new_data(15 downto 8); vconfig.int_line := new_data(7 downto 0);
when others =>
end case;
end procedure;
function pci_hit(ad : std_logic_vector(31 downto 0);
c : std_logic_vector(3 downto 0);
idsel : std_logic;
con : config_header_type) return boolean is
variable hit : boolean;
begin
hit := false;
if ((c = CONF_READ or c = CONF_WRITE)
and idsel = '1' and ad(1 downto 0) = "00")
then hit := true;
else
for i in 0 to bars-1 loop
if i = 1 then
if ((c = IO_READ or c = IO_WRITE)
and ad(31 downto abits) = con.bar(i)(31 downto abits))
then hit := true; end if;
else
if ((c = MEM_READ or c = MEM_WRITE or c = MEM_R_MULT or c = MEM_R_LINE or c = MEM_W_INV)
and ad(31 downto abits) = con.bar(i)(31 downto abits))
then hit := true; end if;
end if;
end loop;
end if;
return(hit);
end function;
-- Description: Insert a response into the linked list of responses
procedure insert_resp (
constant id : in integer;
variable resp_root : inout response_element_ptr;
signal resp : in pt_pci_response_type) is
variable elem : response_element_ptr;
begin -- insert_resp
elem := resp_root;
if elem /= NULL then
while elem.nxt /= NULL loop elem := elem.nxt; end loop;
elem.nxt := new response_element_type'(id, resp, NULL);
else
resp_root := new response_element_type'(id, resp, NULL);
end if;
end insert_resp;
-- Description: Searches the list for a response to a particular address.
-- If a response is found the response is returned via 'resp' and 'found'
-- is set to true, otherwise 'found' is set to false.
procedure get_resp (
variable resp_root : inout response_element_ptr;
signal addr : in std_logic_vector(31 downto 0);
signal resp : out pt_pci_response_type;
variable found : out boolean) is
variable elem, prev : response_element_ptr;
variable lfound : boolean := false;
begin -- get_resp
prev := resp_root;
elem := resp_root;
--print(tost(NOW/1 ns) & "ns get_resp: addr[" & tost(addr) & "]");
while elem /= NULL and not lfound loop
-- Check if response is a match for address
if addr(abits-1 downto 0) = elem.resp.addr(abits-1 downto 0) then
resp <= elem.resp;
lfound := true;
resp.valid <= true;
--if prev = resp_root then
-- resp_root := elem.nxt;
--else
-- prev.nxt := elem.nxt;
--end if;
--deallocate(elem);
end if;
if not lfound then
prev := elem;
elem := elem.nxt;
end if;
end loop;
--print(tost(NOW/1 ns) & "ns get_resp: found[" & tost(lfound) & "]");
if lfound then found := true;
else
found := false;
resp.retry <= 0;
resp.ws <= 0;
resp.diswithout <= 0;
resp.diswith <= 0;
resp.parerr <= 0;
resp.abort <= 0;
resp.debug <= 0;
resp.valid <= false;
end if;
end get_resp;
-- Description: Searches the list for a response with a particular addr.
-- If a response is found the response is removed and the id
-- will match the input id.
procedure rm_resp (
variable resp_root : inout response_element_ptr;
constant addr : in std_logic_vector(31 downto 0) )is
variable elem, prev : response_element_ptr;
variable lfound : boolean := false;
begin -- rm_resp
prev := resp_root;
elem := resp_root;
while elem /= NULL and not lfound loop
if addr(abits-1 downto 0) = elem.resp.addr(abits-1 downto 0) then
if prev = resp_root then
resp_root := elem.nxt;
else
prev.nxt := elem.nxt;
end if;
deallocate(elem);
lfound := true;
else
prev := elem;
elem := elem.nxt;
end if;
end loop;
end rm_resp;
-- Description: Removes all responses in list
procedure rm_all_resp (
variable resp_root : inout response_element_ptr) is
variable elem, curr : response_element_ptr;
variable lfound : boolean := false;
begin -- rm_all_resp
curr := resp_root;
elem := resp_root;
while elem /= NULL loop
curr := elem;
elem := elem.nxt;
deallocate(curr);
end loop;
resp_root := NULL;
end rm_all_resp;
begin
cont : process
variable first : boolean := true;
variable mem : mem_type;
begin
if first then
for i in 0 to ((2**abits)-1) loop
mem(i) := (others => '0');
end loop;
first := false;
elsif r.ad(0) /= 'U' then
do <= mem(conv_integer(to_x01(r.ad)));
--if r.write = '1' then mem(conv_integer(to_x01(r.ad))) := r.di; end if; -- *** sub-word write
if r.write = '1' then
case r.cbe is
when "1110" =>
mem(conv_integer(to_x01(r.ad)))(7 downto 0) := r.di(7 downto 0);
when "1101" =>
mem(conv_integer(to_x01(r.ad)))(15 downto 8) := r.di(15 downto 8);
when "1011" =>
mem(conv_integer(to_x01(r.ad)))(23 downto 16) := r.di(23 downto 16);
when "0111" =>
mem(conv_integer(to_x01(r.ad)))(31 downto 24) := r.di(31 downto 24);
when "1100" =>
mem(conv_integer(to_x01(r.ad)))(15 downto 0) := r.di(15 downto 0);
when "0011" =>
mem(conv_integer(to_x01(r.ad)))(31 downto 16) := r.di(31 downto 16);
when others =>
mem(conv_integer(to_x01(r.ad))) := r.di;
end case;
end if;
end if;
wait for 1 ns;
end process;
core_resp : process
variable resp_root : response_element_ptr := NULL;
variable found : boolean;
begin
if pci_core.req /= '1' and dbgi.req /= '1' then
wait until pci_core.req = '1' or dbgi.req = '1';
end if;
if dbgi.req = '1' then
if dbgi.insert = '1' then
insert_resp(0, resp_root, dbgi.resp);
elsif dbgi.remove = '1' then
if dbgi.rmall = '1' then
rm_all_resp(resp_root);
else
rm_resp(resp_root, dbgi.addr);
end if;
else
dbgo.valid <= '0';
get_resp(resp_root, pci_core.addr, dbgo.resp, found);
if found = true then dbgo.valid <= '1'; end if;
end if;
dbgo.ack <= '1';
wait until dbgi.req = '0';
dbgo.ack <= '0';
end if;
if pci_core.req = '1' then
if pci_core.insert = '1' then
insert_resp(0, resp_root, pci_core.resp);
else
core_pci.valid <= '0';
get_resp(resp_root, pci_core.addr, core_pci.resp, found);
if found = true then core_pci.valid <= '1'; end if;
end if;
core_pci.ack <= '1';
wait until pci_core.req = '0';
core_pci.ack <= '0';
end if;
end process;
--comb : process(pciin, do)
comb : process
variable v : reg_type;
procedure sync_with_core is
begin
pci_core.req <= '1';
wait until core_pci.ack = '1';
pci_core.req <= '0';
wait until core_pci.ack = '0';
end sync_with_core;
begin
if pciin.syst.rst = '0' then
v.state := idle;
v.config := conf;
v.waitcycles := 1;
v.latcnt := latency;
v.ad := (others => '0');
v.di := (others => '0');
v.retrycnt := (others => '0');
v.resp.valid := false;
v.perren := (others => '0');
v.sigperr := (others => '0');
elsif rising_edge(pciin.syst.clk) then
v := r; v.write := '0';
v.pci.ad.par := xorv(r.pci.ad.ad & pciin.ad.cbe);
v.pci.ad.par := v.pci.ad.par xor r.parerr; -- Add par error
v.paren := r.aden; v.erren := not (r.perren(1) or r.perren(0)); --v.erren := r.paren;
v.perren(1) := v.perren(0);
v.pcirad := pciin.ad.ad; v.pcircbe := pciin.ad.cbe;
v.pci.err.perr := not r.perren(0) or not (xorv(r.pcirad & r.pcircbe & pciin.ad.par) or r.sigperr(1));-- or '1'; -- FIXME: ... disable perr
v.sigperr(1) := r.sigperr(0); v.sigperr(2) := r.sigperr(1); v.sigperr(0) := '0';
case r.state is
when idle =>
v.perren(0) := '0';
v.firstacc := '1';
if (r.pci.ifc.trdy and r.pci.ifc.stop and r.pci.ifc.devsel) = '1' then v.pcien := '1'; end if;
v.aden := '1'; v.waitcycles := 1; v.latcnt := latency; v.first := true;
v.pci.ifc.trdy := '1'; v.pci.ifc.stop := '1'; v.curword := 0;
v.pci.ifc.devsel := '1'; --v.pci.err.perr := '1';
if pciin.ifc.frame = '0' then
v.comm := pciin.ad.cbe;
if pci_hit(pciin.ad.ad,pciin.ad.cbe,pciin.ifc.idsel(slot),v.config) then
pci_core.addr <= zero32(31 downto abits) & pciin.ad.ad(abits-1 downto 0); pci_core.insert <= '0';
pci_core.resp.retry <= 0; pci_core.resp.ws <= 0; pci_core.resp.diswithout <= 0; pci_core.resp.diswith <= 0;
sync_with_core;
if core_pci.valid = '1' and r.resp.valid = false then
if core_pci.resp.debug > 0 then print(tost(NOW/1 ns) & "ns Resp1: " & tost(core_pci.resp.addr) & ", "
& resp_print(core_pci.resp.retry*1) & ", " & "ws:" & tost(core_pci.resp.ws) & ", " & resp_print(core_pci.resp.diswith*3+core_pci.resp.diswithout*4)
& ", " & resp_print(core_pci.resp.abort*5) & ", " & resp_print(core_pci.resp.parerr*6) & ", " & tost(core_pci.resp.valid));
end if;
v.resp := core_pci.resp;
v.resp.valid := true;
--if resptime > core_pci.resp.ws then v.resp.ws := resptime; end if; -- use resptime if grater, else use access waitstates
--v.resp.ws := resptime; -- Always use resptime
elsif r.resp.valid = false then
v.resp := non_resp;
end if;
--if r.retrycnt /= x"00" then -- retry response
-- if r.retrycnt = x"ff" then v.retrycnt := x"02";
-- else v.retrycnt := v.retrycnt - 1; end if;
-- v.state := respwait;
--else
-- v.retrycnt := x"ff";
v.ad := zero32(31 downto abits) & pciin.ad.ad(abits-1 downto 0);
--if r.waitcycles = resptime then
if r.waitcycles = resptime and v.resp.retry = 0 then
--if v.resp.ws = 0 and v.resp.retry = 0 then
v.pci.ifc.devsel := '0'; v.pcien := '0';
if pciin.ad.cbe(0) = '1' then v.state := write; v.pci.ifc.trdy := '0';
--if v.resp.abort = 1 then v.pci.ifc.trdy := '1'; v.pci.ifc.stop := '0'; v.pci.ifc.devsel := '1'; end if;
--if v.resp.abort = 1 then v.pci.ifc.trdy := '1'; end if;
if v.resp.abort = 1 then
v.state := tabort;
v.pci.ifc.trdy := '1'; v.pci.ifc.stop := '1'; v.pci.ifc.devsel := '0';
end if;
if v.resp.parerr = 1 then v.sigperr(0) := '1'; end if;
v.resp_addr := v.ad + "100"; pci_core.addr <= v.resp_addr; pci_core.insert <= '0'; sync_with_core;
if core_pci.valid = '1' then v.resp := core_pci.resp; v.resp.valid := true;
if core_pci.resp.debug > 0 then print(tost(NOW/1 ns) & "ns Resp2: " & tost(core_pci.resp.addr) & ", "
& resp_print(core_pci.resp.retry*1) & ", " & "ws:" & tost(core_pci.resp.ws) & ", " & resp_print(core_pci.resp.diswith*3+core_pci.resp.diswithout*4)
& ", " & resp_print(core_pci.resp.abort*5) & ", " & resp_print(core_pci.resp.parerr*6) & ", " & tost(core_pci.resp.valid));
end if;
else v.resp := non_resp; end if;
else v.state := read; v.aden := '0'; end if;
else v.state := respwait; v.waitcycles := r.waitcycles+1; end if;
--else v.state := respwait; if v.resp.ws /= 0 then v.resp.ws := v.resp.ws - 1; end if; end if;
--end if;
else
v.state := b_busy;
end if;
end if;
when b_busy =>
if (pciin.ifc.frame and pciin.ifc.irdy) = '1' then
v.state := idle;
end if;
when retry => -- retry response
v.resp.ws := 0;
if pciin.ifc.frame = '1' then
v.pci.ifc.devsel := '1'; v.pci.ifc.stop := '1'; v.pcien := '1';
v.state := idle;
if r.resp.retry /= 0 then v.resp.retry := r.resp.retry - 1; end if;
end if;
when respwait => -- Initial response time
--if r.retrycnt /= x"ff" then
if r.resp.valid = true and r.resp.retry /= 0 then
v.pci.ifc.devsel := '0'; v.pci.ifc.stop := '0'; v.pcien := '0';
v.state := retry;
elsif r.waitcycles = resptime then
--elsif r.resp.ws <= 1 then
v.pci.ifc.devsel := '0'; v.pcien := '0';
if r.comm(0) = '1' then v.state := write; v.pci.ifc.trdy := '0';
--if r.resp.diswith = 1 or r.resp.diswithout = 1 then v.pci.ifc.stop := '0'; end if;
--if r.resp.diswithout = 1 then v.pci.ifc.trdy := '1'; end if;
if r.resp.parerr = 1 then v.sigperr(0) := '1'; end if;
v.resp_addr := r.ad + "100"; pci_core.addr <= v.resp_addr; pci_core.insert <= '0'; sync_with_core;
if core_pci.valid = '1' then v.resp := core_pci.resp; v.resp.valid := true;
if core_pci.resp.debug > 0 then print(tost(NOW/1 ns) & "ns Resp: " & tost(core_pci.resp.addr) & ", "
& resp_print(core_pci.resp.retry*1) & ", " & "ws:" & tost(core_pci.resp.ws) & ", " & resp_print(core_pci.resp.diswith*3+core_pci.resp.diswithout*4)
& ", " & resp_print(core_pci.resp.abort*5) & ", " & resp_print(core_pci.resp.parerr*6) & ", " & tost(core_pci.resp.valid));
end if;
else v.resp := non_resp; end if;
else v.state := read; v.aden := '0'; v.resp.ws := 0; end if;
if r.resp.abort = 1 then
v.state := tabort;
v.pci.ifc.trdy := '1'; v.pci.ifc.stop := '1'; v.pci.ifc.devsel := '0';
end if;
else v.waitcycles := r.waitcycles+1; end if;
--v.resp.ws := 0;
--else v.resp.ws := r.resp.ws - 1; end if;
when tabort => -- Target abort on first data phase
v.pci.ifc.trdy := '1'; v.pci.ifc.stop := '0'; v.pci.ifc.devsel := '1';
if pciin.ifc.frame = '1' and pciin.ifc.irdy = '0' and (r.pci.ifc.trdy and r.pci.ifc.stop) = '0' then
v.state := idle;
v.pci.ifc.trdy := '1'; v.pci.ifc.devsel := '1'; v.pci.ifc.stop := '1';
v.resp.valid := false;
end if;
when write => -- Write access
v.perren(0) := '1';
--if pciin.ifc.irdy = '0' then
if pciin.ifc.irdy = '0' and r.pci.ifc.trdy = '0' then
v.curword := r.curword+1;
if r.comm = CONF_WRITE then writeconf(r.ad(7 downto 2),pciin.ad.ad,pciin.ad.cbe,v.config);
--else v.di := pciin.ad.ad; v.write := '1'; end if; -- *** sub-word write
else v.di := pciin.ad.ad; v.write := '1'; v.cbe := pciin.ad.cbe; end if;
if r.resp.ws = 0 then
v.firstacc := '0';
if r.resp.diswith = 1 or r.resp.diswithout = 1 then v.pci.ifc.stop := '0'; v.state := dis; end if;
if r.resp.diswithout = 1 then v.pci.ifc.trdy := '1'; end if;
if r.resp.abort = 1 then v.pci.ifc.trdy := '1'; v.pci.ifc.stop := '0'; v.pci.ifc.devsel := '1'; end if;
if r.resp.parerr = 1 then v.sigperr(0) := '1'; end if;
v.resp_addr := r.resp_addr + "100"; pci_core.addr <= v.resp_addr; pci_core.insert <= '0'; sync_with_core;
if core_pci.valid = '1' then v.resp := core_pci.resp; v.resp.valid := true;
if core_pci.resp.debug > 0 then print(tost(NOW/1 ns) & "ns Resp: " & tost(core_pci.resp.addr) & ", "
& resp_print(core_pci.resp.retry*1) & ", " & "ws:" & tost(core_pci.resp.ws) & ", " & resp_print(core_pci.resp.diswith*3+core_pci.resp.diswithout*4)
& ", " & resp_print(core_pci.resp.abort*5) & ", " & resp_print(core_pci.resp.parerr*6) & ", " & tost(core_pci.resp.valid));
end if;
else v.resp := non_resp; end if;
end if;
--elsif r.resp.abort = 1 then -- Target abort on first data phase
-- v.pci.ifc.trdy := '1'; v.pci.ifc.stop := '0'; v.pci.ifc.devsel := '1';
end if;
if r.write = '1' then v.ad := r.ad + "100"; end if;
if pciin.ifc.frame = '1' and pciin.ifc.irdy = '0' and (r.pci.ifc.trdy and r.pci.ifc.stop) = '0' then
v.state := idle;
v.pci.ifc.trdy := '1'; v.pci.ifc.devsel := '1'; v.pci.ifc.stop := '1';
v.resp.valid := false;
--elsif (r.latcnt > 0 and pciin.ifc.irdy = '0') then v.state := latw; v.pci.ifc.trdy := '1'; v.latcnt := r.latcnt-1;
elsif (r.resp.ws > 0 and pciin.ifc.irdy = '0') then v.state := latw; v.pci.ifc.trdy := '1'; v.resp.ws := r.resp.ws-1;
end if;
when read => -- Read access
v.perren(0) := '0';
v.pci.ifc.trdy := '0';
if (pciin.ifc.irdy = '0' or r.first = true) then
v.ad := r.ad + "100"; v.first := false;
if r.comm = CONF_READ then readconf(r.ad(7 downto 2),v.pci.ad.ad);
else v.pci.ad.ad := do; end if;
if r.resp.parerr = 1 then v.parerr := '1'; else v.parerr := '0'; end if; -- Add par error
if r.resp.ws = 0 then
v.firstacc := '0';
if r.firstacc = '0' and (r.resp.diswith = 1 or r.resp.diswithout = 1) then v.pci.ifc.stop := '0'; v.state := dis; end if;
if r.firstacc = '0' and r.resp.diswithout = 1 then v.pci.ifc.trdy := '1'; end if;
if r.resp.abort = 1 then v.pci.ifc.trdy := '1'; v.pci.ifc.stop := '0'; v.pci.ifc.devsel := '1'; v.state := dis; end if;
pci_core.addr <= v.ad; pci_core.insert <= '0'; sync_with_core;
if core_pci.valid = '1' then v.resp := core_pci.resp; v.resp.valid := true;
if core_pci.resp.debug > 0 then print(tost(NOW/1 ns) & "ns Resp: " & tost(core_pci.resp.addr) & ", "
& resp_print(core_pci.resp.retry*1) & ", " & "ws:" & tost(core_pci.resp.ws) & ", " & resp_print(core_pci.resp.diswith*3+core_pci.resp.diswithout*4)
& ", " & resp_print(core_pci.resp.abort*5) & ", " & resp_print(core_pci.resp.parerr*6) & ", " & tost(core_pci.resp.valid));
end if;
else v.resp := non_resp; end if;
end if;
end if;
if (pciin.ifc.trdy or pciin.ifc.irdy) = '0' then v.curword := r.curword+1; end if;
if (pciin.ifc.frame and not (pciin.ifc.trdy and pciin.ifc.stop)) = '1' then
v.state := idle; v.aden := '1';
v.pci.ifc.trdy := '1'; v.pci.ifc.devsel := '1';
v.resp.valid := false;
--elsif (r.latcnt > 0 and (pciin.ifc.trdy or pciin.ifc.irdy) = '0' and pciin.ifc.stop = '1') then
elsif (r.resp.ws > 0 and (pciin.ifc.trdy or pciin.ifc.irdy) = '0' and pciin.ifc.stop = '1') then
--v.state := latw; v.latcnt := r.latcnt-1; v.pci.ifc.trdy := '1';
v.state := latw; v.resp.ws := r.resp.ws-1; v.pci.ifc.trdy := '1';
end if;
when latw => -- Latency between data phases
v.pci.ifc.trdy := '1';
if r.write = '1' then v.ad := r.ad + "100"; end if;
--if (r.latcnt <= 1 and r.comm(0) = '0') then
if (r.resp.ws <= 1 and r.comm(0) = '0') then
--v.latcnt := latency;
v.resp.ws := 0;
v.state := read; v.aden := '0'; v.pci.ifc.trdy := '0';
--elsif r.latcnt = 0 then
if r.resp.diswith = 1 or r.resp.diswithout = 1 then v.pci.ifc.stop := '0'; v.state := dis; end if;
if r.resp.diswithout = 1 then v.pci.ifc.trdy := '1'; end if;
if r.resp.abort = 1 then v.pci.ifc.trdy := '1'; v.pci.ifc.stop := '0'; v.pci.ifc.devsel := '1'; end if;
pci_core.addr <= r.ad; pci_core.insert <= '0'; sync_with_core;
if core_pci.valid = '1' then v.resp := core_pci.resp; v.resp.valid := true;
if core_pci.resp.debug > 0 then print(tost(NOW/1 ns) & "ns Resp: " & tost(core_pci.resp.addr) & ", "
& resp_print(core_pci.resp.retry*1) & ", " & "ws:" & tost(core_pci.resp.ws) & ", " & resp_print(core_pci.resp.diswith*3+core_pci.resp.diswithout*4)
& ", " & resp_print(core_pci.resp.abort*5) & ", " & resp_print(core_pci.resp.parerr*6) & ", " & tost(core_pci.resp.valid));
end if;
else v.resp := non_resp; end if;
elsif r.resp.ws = 0 then
--v.latcnt := latency;
v.resp.ws := 0;
v.state := write; v.pci.ifc.trdy := '0';
if r.resp.diswith = 1 or r.resp.diswithout = 1 then v.pci.ifc.stop := '0'; v.state := dis; end if;
if r.resp.diswithout = 1 then v.pci.ifc.trdy := '1'; end if;
if r.resp.abort = 1 then v.pci.ifc.trdy := '1'; v.pci.ifc.stop := '0'; v.pci.ifc.devsel := '1'; end if;
v.resp_addr := r.resp_addr + "100"; pci_core.addr <= v.resp_addr; pci_core.insert <= '0'; sync_with_core;
if core_pci.valid = '1' then v.resp := core_pci.resp; v.resp.valid := true;
if core_pci.resp.debug > 0 then print(tost(NOW/1 ns) & "ns Resp: " & tost(core_pci.resp.addr) & ", "
& resp_print(core_pci.resp.retry*1) & ", " & "ws:" & tost(core_pci.resp.ws) & ", " & resp_print(core_pci.resp.diswith*3+core_pci.resp.diswithout*4)
& ", " & resp_print(core_pci.resp.abort*5) & ", " & resp_print(core_pci.resp.parerr*6) & ", " & tost(core_pci.resp.valid));
end if;
else v.resp := non_resp; end if;
--else v.latcnt := r.latcnt-1; end if;
else v.resp.ws := r.resp.ws-1; end if;
if (pciin.ifc.frame and not r.pci.ifc.stop) = '1' then -- done if disconnect ???
v.state := idle;
v.pci.ifc.trdy := '1'; v.pci.ifc.devsel := '1';
v.resp.valid := false;
end if;
when dis =>
v.perren(0) := '0';
v.pci.ifc.stop := '0';
if r.write = '1' then v.ad := r.ad + "100"; end if;
if pciin.ifc.irdy = '0' then
v.pci.ifc.trdy := '1';
if r.pci.ifc.trdy = '0' then
if r.comm = CONF_WRITE then writeconf(r.ad(7 downto 2),pciin.ad.ad,pciin.ad.cbe,v.config);
elsif r.comm(0) = '1' then v.di := pciin.ad.ad; v.write := '1'; v.cbe := pciin.ad.cbe; end if;
end if;
end if;
if pciin.ifc.frame = '1' then
v.state := idle;
v.pci.ifc.trdy := '1'; v.pci.ifc.devsel := '1'; v.pci.ifc.stop := '1';
v.resp.valid := false;
end if;
when others =>
end case;
-- Disconnect type
--if ((v.curword+1) >= rbuf) then
-- if pciin.ifc.frame = '1' then
-- v.pci.ifc.stop := '1';
-- elsif stopwd then
-- if r.pci.ifc.stop = '1' then
-- v.pci.ifc.stop := v.pci.ifc.trdy;
-- else
-- if pciin.ifc.irdy = '0' then v.pci.ifc.trdy := '1'; end if;
-- v.pci.ifc.stop := '0';
-- end if;
-- else
-- v.pci.ifc.stop := '0';
-- v.pci.ifc.trdy := '1';
-- end if;
--end if;
end if;
r <= v;
--rin <= v;
wait on pciin.syst.clk, pciin.syst.rst;
end process;
--clockreg : process(pciin.syst)
--begin
-- if rising_edge(pciin.syst.clk) then
-- r <= rin;
-- end if;
--end process;
pciout.ad.ad <= r.pci.ad.ad after tval when r.aden = '0' else (others => 'Z') after tval;
pciout.ad.par <= r.pci.ad.par after tval when (r.paren = '0' and (r.pci.ad.par = '1' or r.pci.ad.par = '0')) else 'Z' after tval;
pciout.ifc.trdy <= r.pci.ifc.trdy after tval when r.pcien = '0' else 'Z' after tval;
pciout.ifc.stop <= r.pci.ifc.stop after tval when r.pcien = '0' else 'Z' after tval;
pciout.ifc.devsel <= r.pci.ifc.devsel after tval when r.pcien = '0' else 'Z' after tval;
pciout.err.perr <= r.pci.err.perr after tval when r.erren = '0' else 'Z' after tval;
-- Unused signals
pciout.ad.cbe <= (others => 'Z');
pciout.ifc.frame <= 'Z';
pciout.ifc.irdy <= 'Z';
pciout.ifc.lock <= 'Z';
pciout.ifc.idsel <= (others => 'Z');
pciout.err.serr <= 'Z';
pciout.arb <= arb_const;
pciout.syst <= syst_const;
pciout.ext64 <= ext64_const;
pciout.cache <= cache_const;
pciout.int <= (others => 'Z');
end;
-- pragma translate_on
| gpl-2.0 | 0553f5fbdf6831f0f6fc618e85d67bb3 | 0.544742 | 3.083631 | false | true | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/lab3_project_default.xpr/project_1/project_1.ipdefs/ip_0/tmp.srcs/sources_1/ip/convolve_kernel_ap_fmul_2_max_dsp_32/hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd | 16 | 80,739 | `protect begin_protected
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`protect end_protected
| mit | 66cead47b4a69256bbc67f7c9993fc03 | 0.951709 | 1.820209 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/lab3_project_default.xpr/project_1/project_1.ipdefs/ip_0/hdl/vhdl/convolve_kernel_control_s_axi.vhd | 1 | 12,110 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity convolve_kernel_control_s_axi is
generic (
C_S_AXI_ADDR_WIDTH : INTEGER := 4;
C_S_AXI_DATA_WIDTH : INTEGER := 32);
port (
-- axi4 lite slave signals
ACLK :in STD_LOGIC;
ARESET :in STD_LOGIC;
ACLK_EN :in STD_LOGIC;
AWADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
AWVALID :in STD_LOGIC;
AWREADY :out STD_LOGIC;
WDATA :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0);
WVALID :in STD_LOGIC;
WREADY :out STD_LOGIC;
BRESP :out STD_LOGIC_VECTOR(1 downto 0);
BVALID :out STD_LOGIC;
BREADY :in STD_LOGIC;
ARADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
ARVALID :in STD_LOGIC;
ARREADY :out STD_LOGIC;
RDATA :out STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP :out STD_LOGIC_VECTOR(1 downto 0);
RVALID :out STD_LOGIC;
RREADY :in STD_LOGIC;
interrupt :out STD_LOGIC;
-- user signals
ap_start :out STD_LOGIC;
ap_done :in STD_LOGIC;
ap_ready :in STD_LOGIC;
ap_idle :in STD_LOGIC
);
end entity convolve_kernel_control_s_axi;
-- ------------------------Address Info-------------------
-- 0x0 : Control signals
-- bit 0 - ap_start (Read/Write/COH)
-- bit 1 - ap_done (Read/COR)
-- bit 2 - ap_idle (Read)
-- bit 3 - ap_ready (Read)
-- bit 7 - auto_restart (Read/Write)
-- others - reserved
-- 0x4 : Global Interrupt Enable Register
-- bit 0 - Global Interrupt Enable (Read/Write)
-- others - reserved
-- 0x8 : IP Interrupt Enable Register (Read/Write)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0xc : IP Interrupt Status Register (Read/TOW)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
architecture behave of convolve_kernel_control_s_axi is
type states is (wridle, wrdata, wrresp, wrreset, rdidle, rddata, rdreset); -- read and write fsm states
signal wstate : states := wrreset;
signal rstate : states := rdreset;
signal wnext, rnext: states;
constant ADDR_AP_CTRL : INTEGER := 16#0#;
constant ADDR_GIE : INTEGER := 16#4#;
constant ADDR_IER : INTEGER := 16#8#;
constant ADDR_ISR : INTEGER := 16#c#;
constant ADDR_BITS : INTEGER := 4;
signal waddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal wmask : UNSIGNED(31 downto 0);
signal aw_hs : STD_LOGIC;
signal w_hs : STD_LOGIC;
signal rdata_data : UNSIGNED(31 downto 0);
signal ar_hs : STD_LOGIC;
signal raddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal AWREADY_t : STD_LOGIC;
signal WREADY_t : STD_LOGIC;
signal ARREADY_t : STD_LOGIC;
signal RVALID_t : STD_LOGIC;
-- internal registers
signal int_ap_idle : STD_LOGIC;
signal int_ap_ready : STD_LOGIC;
signal int_ap_done : STD_LOGIC := '0';
signal int_ap_start : STD_LOGIC := '0';
signal int_auto_restart : STD_LOGIC := '0';
signal int_gie : STD_LOGIC := '0';
signal int_ier : UNSIGNED(1 downto 0) := (others => '0');
signal int_isr : UNSIGNED(1 downto 0) := (others => '0');
begin
-- ----------------------- Instantiation------------------
-- ----------------------- AXI WRITE ---------------------
AWREADY_t <= '1' when wstate = wridle else '0';
AWREADY <= AWREADY_t;
WREADY_t <= '1' when wstate = wrdata else '0';
WREADY <= WREADY_t;
BRESP <= "00"; -- OKAY
BVALID <= '1' when wstate = wrresp else '0';
wmask <= (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0));
aw_hs <= AWVALID and AWREADY_t;
w_hs <= WVALID and WREADY_t;
-- write FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wstate <= wrreset;
elsif (ACLK_EN = '1') then
wstate <= wnext;
end if;
end if;
end process;
process (wstate, AWVALID, WVALID, BREADY)
begin
case (wstate) is
when wridle =>
if (AWVALID = '1') then
wnext <= wrdata;
else
wnext <= wridle;
end if;
when wrdata =>
if (WVALID = '1') then
wnext <= wrresp;
else
wnext <= wrdata;
end if;
when wrresp =>
if (BREADY = '1') then
wnext <= wridle;
else
wnext <= wrresp;
end if;
when others =>
wnext <= wridle;
end case;
end process;
waddr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (aw_hs = '1') then
waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0));
end if;
end if;
end if;
end process;
-- ----------------------- AXI READ ----------------------
ARREADY_t <= '1' when (rstate = rdidle) else '0';
ARREADY <= ARREADY_t;
RDATA <= STD_LOGIC_VECTOR(rdata_data);
RRESP <= "00"; -- OKAY
RVALID_t <= '1' when (rstate = rddata) else '0';
RVALID <= RVALID_t;
ar_hs <= ARVALID and ARREADY_t;
raddr <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0));
-- read FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rstate <= rdreset;
elsif (ACLK_EN = '1') then
rstate <= rnext;
end if;
end if;
end process;
process (rstate, ARVALID, RREADY, RVALID_t)
begin
case (rstate) is
when rdidle =>
if (ARVALID = '1') then
rnext <= rddata;
else
rnext <= rdidle;
end if;
when rddata =>
if (RREADY = '1' and RVALID_t = '1') then
rnext <= rdidle;
else
rnext <= rddata;
end if;
when others =>
rnext <= rdidle;
end case;
end process;
rdata_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (ar_hs = '1') then
case (TO_INTEGER(raddr)) is
when ADDR_AP_CTRL =>
rdata_data <= (7 => int_auto_restart, 3 => int_ap_ready, 2 => int_ap_idle, 1 => int_ap_done, 0 => int_ap_start, others => '0');
when ADDR_GIE =>
rdata_data <= (0 => int_gie, others => '0');
when ADDR_IER =>
rdata_data <= (1 => int_ier(1), 0 => int_ier(0), others => '0');
when ADDR_ISR =>
rdata_data <= (1 => int_isr(1), 0 => int_isr(0), others => '0');
when others =>
rdata_data <= (others => '0');
end case;
end if;
end if;
end if;
end process;
-- ----------------------- Register logic ----------------
interrupt <= int_gie and (int_isr(0) or int_isr(1));
ap_start <= int_ap_start;
int_ap_idle <= ap_idle;
int_ap_ready <= ap_ready;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_start <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then
int_ap_start <= '1';
elsif (int_ap_ready = '1') then
int_ap_start <= int_auto_restart; -- clear on handshake/auto restart
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_done <= '0';
elsif (ACLK_EN = '1') then
if (ap_done = '1') then
int_ap_done <= '1';
elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then
int_ap_done <= '0'; -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_auto_restart <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1') then
int_auto_restart <= WDATA(7);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_gie <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_GIE and WSTRB(0) = '1') then
int_gie <= WDATA(0);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ier <= "00";
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_IER and WSTRB(0) = '1') then
int_ier <= UNSIGNED(WDATA(1 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(0) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(0) = '1' and ap_done = '1') then
int_isr(0) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(0) <= int_isr(0) xor WDATA(0); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(1) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(1) = '1' and ap_ready = '1') then
int_isr(1) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(1) <= int_isr(1) xor WDATA(1); -- toggle on write
end if;
end if;
end if;
end process;
-- ----------------------- Memory logic ------------------
end architecture behave;
| mit | d55a68d1ed70be8a9e77d376d30c39e1 | 0.433113 | 3.929267 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/leon3v3/dsu3x.vhd | 1 | 30,001 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: dsu
-- File: dsu.vhd
-- Author: Jiri Gaisler, Edvin Catovic - Gaisler Research
-- Description: Combined LEON3 debug support and AHB trace unit
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.config_types.all;
use grlib.config.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.leon3.all;
library techmap;
use techmap.gencomp.all;
entity dsu3x is
generic (
hindex : integer := 0;
haddr : integer := 16#900#;
hmask : integer := 16#f00#;
ncpu : integer := 1;
tbits : integer := 30; -- timer bits (instruction trace time tag)
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 0;
clk2x : integer range 0 to 1 := 0;
testen : integer := 0
);
port (
rst : in std_ulogic;
hclk : in std_ulogic;
cpuclk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
tahbsi : in ahb_slv_in_type;
dbgi : in l3_debug_out_vector(0 to NCPU-1);
dbgo : out l3_debug_in_vector(0 to NCPU-1);
dsui : in dsu_in_type;
dsuo : out dsu_out_type;
hclken : in std_ulogic
);
attribute sync_set_reset of rst : signal is "true";
end;
architecture rtl of dsu3x is
constant TBUFABITS : integer := log2(kbytes) + 6;
constant NBITS : integer := log2x(ncpu);
constant PROC_H : integer := 24+NBITS-1;
constant PROC_L : integer := 24;
constant AREA_H : integer := 23;
constant AREA_L : integer := 20;
constant HBITS : integer := 28;
constant DSU3_VERSION : integer := 1;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_LEON3DSU, 0, DSU3_VERSION, 0),
4 => ahb_membar(haddr, '0', '0', hmask),
others => zero32);
type slv_reg_type is record
hsel : std_ulogic;
haddr : std_logic_vector(PROC_H downto 0);
hwrite : std_ulogic;
hwdata : std_logic_vector(31 downto 0);
hrdata : std_logic_vector(31 downto 0);
hready : std_ulogic;
hready2 : std_ulogic;
end record;
constant slv_reg_none : slv_reg_type := (
hsel => '0',
haddr => (others => '0'),
hwrite => '0',
hwdata => (others => '0'),
hrdata => (others => '0'),
hready => '1',
hready2 => '1'
);
type reg_type is record
slv : slv_reg_type;
en : std_logic_vector(0 to NCPU-1);
te : std_logic_vector(0 to NCPU-1);
be : std_logic_vector(0 to NCPU-1);
bw : std_logic_vector(0 to NCPU-1);
bs : std_logic_vector(0 to NCPU-1);
bx : std_logic_vector(0 to NCPU-1);
bz : std_logic_vector(0 to NCPU-1);
halt : std_logic_vector(0 to NCPU-1);
reset : std_logic_vector(0 to NCPU-1);
bn : std_logic_vector(NCPU-1 downto 0);
ss : std_logic_vector(NCPU-1 downto 0);
bmsk : std_logic_vector(NCPU-1 downto 0);
dmsk : std_logic_vector(NCPU-1 downto 0);
cnt : std_logic_vector(2 downto 0);
dsubre : std_logic_vector(2 downto 0);
dsuen : std_logic_vector(2 downto 0);
act : std_ulogic;
timer : std_logic_vector(tbits-1 downto 0);
pwd : std_logic_vector(NCPU-1 downto 0);
tstop : std_ulogic;
end record;
constant RRES : reg_type := (
slv => slv_reg_none,
en => (others => '0'),
te => (others => '0'),
be => (others => '0'),
bw => (others => '0'),
bs => (others => '0'),
bx => (others => '0'),
bz => (others => '0'),
halt => (others => '0'),
reset => (others => '0'),
bn => (others => '0'),
ss => (others => '0'),
bmsk => (others => '0'),
dmsk => (others => '0'),
cnt => (others => '0'),
dsubre => (others => '0'),
dsuen => (others => '0'),
act => '0',
timer => (others => '0'),
pwd => (others => '0'),
tstop => '0'
);
type trace_break_reg is record
addr : std_logic_vector(31 downto 2);
mask : std_logic_vector(31 downto 2);
read : std_logic;
write : std_logic;
end record;
constant trace_break_none : trace_break_reg := (
addr => (others => '0'),
mask => (others => '0'),
read => '0',
write => '0'
);
type t_reg_type is record
haddr : std_logic_vector(31 downto 0);
hwrite : std_logic;
htrans : std_logic_vector(1 downto 0);
hsize : std_logic_vector(2 downto 0);
hburst : std_logic_vector(2 downto 0);
hwdata : std_logic_vector(31 downto 0);
hmaster : std_logic_vector(3 downto 0);
hmastlock : std_logic;
hsel : std_logic;
ahbactive : std_logic;
aindex : std_logic_vector(TBUFABITS - 1 downto 0); -- buffer index
enable : std_logic; -- trace enable
bphit : std_logic; -- AHB breakpoint hit
bphit2 : std_logic; -- delayed bphit
dcnten : std_logic; -- delay counter enable
delaycnt : std_logic_vector(TBUFABITS - 1 downto 0); -- delay counter
tbreg1 : trace_break_reg;
tbreg2 : trace_break_reg;
tbwr : std_logic; -- trace buffer write enable
break : std_logic; -- break CPU when AHB tracing stops
end record;
constant TRES : t_reg_type := (
haddr => (others => '0'),
hwrite => '0',
htrans => (others => '0'),
hsize => (others => '0'),
hburst => (others => '0'),
hwdata => (others => '0'),
hmaster => (others => '0'),
hmastlock => '0',
hsel => '0',
ahbactive => '0',
aindex => (others => '0'),
enable => '0',
bphit => '0',
bphit2 => '0',
dcnten => '0',
delaycnt => (others => '0'),
tbreg1 => trace_break_none,
tbreg2 => trace_break_none,
tbwr => '0',
break => '0'
);
type hclk_reg_type is record
irq : std_ulogic;
oen : std_ulogic;
end record;
constant hclk_reg_none : hclk_reg_type := (
irq => '0', oen => '0'
);
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant TRACEN : boolean := (kbytes /= 0);
signal tbi : tracebuf_in_type;
signal tbo : tracebuf_out_type;
signal tr, trin : t_reg_type;
signal r, rin : reg_type;
signal rh, rhin : hclk_reg_type;
signal ahbsi2, tahbsi2 : ahb_slv_in_type;
signal hrdata2x : std_logic_vector(31 downto 0);
begin
comb: process(rst, r, ahbsi, ahbsi2, tahbsi2, dbgi, dsui, ahbmi, tr, tbo, hclken, rh, hrdata2x)
variable v : reg_type;
variable iuacc : std_ulogic;
variable dbgmode, tstop : std_ulogic;
variable rawindex : integer range 0 to (2**NBITS)-1;
variable index : natural range 0 to NCPU-1;
variable hasel1 : std_logic_vector(AREA_H-1 downto AREA_L);
variable hasel2 : std_logic_vector(6 downto 2);
variable tv : t_reg_type;
variable vabufi : tracebuf_in_type;
variable aindex : std_logic_vector(TBUFABITS - 1 downto 0); -- buffer index
variable hirq : std_logic_vector(NAHBIRQ-1 downto 0);
variable cpwd : std_logic_vector(15 downto 0);
variable hrdata : std_logic_vector(31 downto 0);
variable bphit1, bphit2 : std_ulogic;
variable vh : hclk_reg_type;
begin
v := r;
iuacc := '0'; --v.slv.hready := '0';
dbgmode := '0'; tstop := '1';
v.dsubre := r.dsubre(1 downto 0) & dsui.break;
v.dsuen := r.dsuen(1 downto 0) & dsui.enable;
hrdata := r.slv.hrdata;
tv := tr; vabufi.enable := '0'; tv.bphit := '0'; tv.tbwr := '0';
if (clk2x /= 0) then tv.bphit2 := tr.bphit; else tv.bphit2 := '0'; end if;
vabufi.data := (others => '0'); vabufi.addr := (others => '0');
vabufi.write := (others => '0'); aindex := (others => '0');
hirq := (others => '0'); v.reset := (others => '0');
if TRACEN then
aindex := tr.aindex + 1;
if (clk2x /= 0) then vh.irq := tr.bphit or tr.bphit2; hirq(irq) := rh.irq;
else hirq(irq) := tr.bphit; end if;
end if;
if hclken = '1' then
v.slv.hready := '0'; v.act := '0';
end if;
-- check for AHB watchpoints
bphit1 := '0'; bphit2 := '0';
if TRACEN and ((tahbsi2.hready and tr.ahbactive) = '1') then
if ((((tr.tbreg1.addr xor tr.haddr(31 downto 2)) and tr.tbreg1.mask) = zero32(29 downto 0)) and
(((tr.tbreg1.read and not tr.hwrite) or (tr.tbreg1.write and tr.hwrite)) = '1'))
then bphit1 := '1'; end if;
if ((((tr.tbreg2.addr xor tr.haddr(31 downto 2)) and tr.tbreg2.mask) = zero32(29 downto 0)) and
(((tr.tbreg2.read and not tr.hwrite) or (tr.tbreg2.write and tr.hwrite)) = '1'))
then bphit2 := '1'; end if;
if (bphit1 or bphit2) = '1' then
if ((tr.enable and not r.act) = '1') and (tr.dcnten = '0') and
(tr.delaycnt /= zero32(TBUFABITS-1 downto 0))
then tv.dcnten := '1';
else tv.enable := '0'; tv.bphit := tr.break; end if;
end if;
end if;
-- generate AHB buffer inputs
vabufi.write := "0000";
if TRACEN then
if (tr.enable = '1') and (r.act = '0') then
vabufi.addr(TBUFABITS-1 downto 0) := tr.aindex;
vabufi.data(127) := bphit1 or bphit2;
vabufi.data(96+tbits-1 downto 96) := r.timer;
vabufi.data(94 downto 80) := ahbmi.hirq(15 downto 1);
vabufi.data(79) := tr.hwrite;
vabufi.data(78 downto 77) := tr.htrans;
vabufi.data(76 downto 74) := tr.hsize;
vabufi.data(73 downto 71) := tr.hburst;
vabufi.data(70 downto 67) := tr.hmaster;
vabufi.data(66) := tr.hmastlock;
vabufi.data(65 downto 64) := ahbmi.hresp;
if tr.hwrite = '1' then
vabufi.data(63 downto 32) := ahbsi2.hwdata(31 downto 0);
else
vabufi.data(63 downto 32) := ahbmi.hrdata(31 downto 0);
end if;
vabufi.data(31 downto 0) := tr.haddr;
else
vabufi.addr(TBUFABITS-1 downto 0) := tr.haddr(TBUFABITS+3 downto 4);
vabufi.data := ahbsi2.hwdata(31 downto 0) & ahbsi2.hwdata(31 downto 0) & ahbsi2.hwdata(31 downto 0) & ahbsi2.hwdata(31 downto 0);
end if;
-- write trace buffer
if (tr.enable and not r.act) = '1' then
if (tr.ahbactive and ahbsi2.hready) = '1' then
tv.aindex := aindex; tv.tbwr := '1';
vabufi.enable := '1'; vabufi.write := "1111";
end if;
end if;
-- trace buffer delay counter handling
if (tr.dcnten = '1') then
if (tr.delaycnt = zero32(TBUFABITS-1 downto 0)) then
tv.enable := '0'; tv.dcnten := '0'; tv.bphit := tr.break;
end if;
if tr.tbwr = '1' then tv.delaycnt := tr.delaycnt - 1; end if;
end if;
-- save AHB transfer parameters
if (tahbsi2.hready = '1' ) then
tv.haddr := tahbsi2.haddr; tv.hwrite := tahbsi2.hwrite; tv.htrans := tahbsi2.htrans;
tv.hsize := tahbsi2.hsize; tv.hburst := tahbsi2.hburst;
tv.hmaster := tahbsi2.hmaster; tv.hmastlock := tahbsi2.hmastlock;
end if;
if tr.hsel = '1' then tv.hwdata := tahbsi2.hwdata(31 downto 0); end if;
if tahbsi2.hready = '1' then
tv.hsel := tahbsi2.hsel(hindex);
tv.ahbactive := tahbsi2.htrans(1);
end if;
end if;
if r.slv.hsel = '1' then
if (clk2x = 0) then
v.cnt := r.cnt - 1;
else
if (r.cnt /= "111") or (hclken = '1') then v.cnt := r.cnt - 1; end if;
end if;
end if;
if (r.slv.hready and hclken) = '1' then
v.slv.hsel := '0'; --v.slv.act := '0';
end if;
for i in 0 to NCPU-1 loop
if dbgi(i).dsumode = '1' then
if r.dmsk(i) = '0' then
dbgmode := '1';
if hclken = '1' then v.act := '1'; end if;
end if;
v.bn(i) := '1';
else
tstop := '0';
end if;
end loop;
if tstop = '0' then v.timer := r.timer + 1; end if;
if (clk2x /= 0) then
if hclken = '1' then v.tstop := tstop; end if;
tstop := r.tstop;
end if;
cpwd := (others => '0');
for i in 0 to NCPU-1 loop
v.bn(i) := v.bn(i) or (dbgmode and r.bmsk(i)) or (r.dsubre(1) and not r.dsubre(2));
if TRACEN then v.bn(i) := v.bn(i) or (tr.bphit and not r.ss(i) and not r.act); end if;
v.pwd(i) := dbgi(i).idle and (not dbgi(i).ipend) and not v.bn(i);
end loop;
cpwd(NCPU-1 downto 0) := r.pwd;
if (ahbsi2.hready and ahbsi2.hsel(hindex)) = '1' then
if (ahbsi2.htrans(1) = '1') then
v.slv.hsel := '1';
v.slv.haddr := ahbsi2.haddr(PROC_H downto 0);
v.slv.hwrite := ahbsi2.hwrite;
v.cnt := "111";
end if;
end if;
for i in 0 to NCPU-1 loop
v.en(i) := r.dsuen(2) and dbgi(i).dsu;
end loop;
rawindex := conv_integer(r.slv.haddr(PROC_H downto PROC_L));
if ncpu = 1 then index := 0; else
if rawindex > ncpu then index := ncpu-1; else index := rawindex; end if;
end if;
hasel1 := r.slv.haddr(AREA_H-1 downto AREA_L);
hasel2 := r.slv.haddr(6 downto 2);
if r.slv.hsel = '1' then
case hasel1 is
when "000" => -- DSU registers
if r.cnt(2 downto 0) = "110" then
if hclken = '1' then v.slv.hready := '1'; else v.slv.hready2 := '1'; end if;
end if;
hrdata := (others => '0');
case hasel2 is
when "00000" =>
if r.slv.hwrite = '1' then
if hclken = '1' then
v.te(index) := ahbsi2.hwdata(0);
v.be(index) := ahbsi2.hwdata(1);
v.bw(index) := ahbsi2.hwdata(2);
v.bs(index) := ahbsi2.hwdata(3);
v.bx(index) := ahbsi2.hwdata(4);
v.bz(index) := ahbsi2.hwdata(5);
v.reset(index) := ahbsi2.hwdata(9);
v.halt(index) := ahbsi2.hwdata(10);
else v.reset := r.reset; end if;
end if;
hrdata(0) := r.te(index);
hrdata(1) := r.be(index);
hrdata(2) := r.bw(index);
hrdata(3) := r.bs(index);
hrdata(4) := r.bx(index);
hrdata(5) := r.bz(index);
hrdata(6) := dbgi(index).dsumode;
hrdata(7) := r.dsuen(2);
hrdata(8) := r.dsubre(2);
hrdata(9) := not dbgi(index).error;
hrdata(10) := dbgi(index).halt;
hrdata(11) := dbgi(index).pwd;
when "00010" => -- timer
if r.slv.hwrite = '1' then
if hclken = '1' then
v.timer := ahbsi2.hwdata(tbits-1 downto 0);
else v.timer := r.timer; end if;
end if;
hrdata(tbits-1 downto 0) := r.timer;
when "01000" =>
if r.slv.hwrite = '1' then
if hclken = '1' then
v.bn := ahbsi2.hwdata(NCPU-1 downto 0);
v.ss := ahbsi2.hwdata(16+NCPU-1 downto 16);
else v.bn := r.bn; v.ss := r.ss; end if;
end if;
hrdata(NCPU-1 downto 0) := r.bn;
hrdata(16+NCPU-1 downto 16) := r.ss;
when "01001" =>
if (r.slv.hwrite and hclken) = '1' then
v.bmsk(NCPU-1 downto 0) := ahbsi2.hwdata(NCPU-1 downto 0);
v.dmsk(NCPU-1 downto 0) := ahbsi2.hwdata(NCPU-1+16 downto 16);
end if;
hrdata(NCPU-1 downto 0) := r.bmsk;
hrdata(NCPU-1+16 downto 16) := r.dmsk;
when "10000" =>
if TRACEN then
hrdata((TBUFABITS + 15) downto 16) := tr.delaycnt;
hrdata(2 downto 0) := tr.break & tr.dcnten & tr.enable;
if r.slv.hwrite = '1' then
if hclken = '1' then
tv.delaycnt := ahbsi2.hwdata((TBUFABITS+ 15) downto 16);
tv.break := ahbsi2.hwdata(2);
tv.dcnten := ahbsi2.hwdata(1);
tv.enable := ahbsi2.hwdata(0);
else
tv.delaycnt := tr.delaycnt; tv.break := tr.break;
tv.dcnten := tr.dcnten; tv.enable := tr.enable;
end if;
end if;
end if;
when "10001" =>
if TRACEN then
hrdata((TBUFABITS - 1 + 4) downto 4) := tr.aindex;
if r.slv.hwrite = '1' then
if hclken = '1' then
tv.aindex := ahbsi2.hwdata((TBUFABITS - 1 + 4) downto 4);
else tv.aindex := tr.aindex; end if;
end if;
end if;
when "10100" =>
if TRACEN then
hrdata(31 downto 2) := tr.tbreg1.addr;
if (r.slv.hwrite and hclken) = '1' then
tv.tbreg1.addr := ahbsi2.hwdata(31 downto 2);
end if;
end if;
when "10101" =>
if TRACEN then
hrdata := tr.tbreg1.mask & tr.tbreg1.read & tr.tbreg1.write;
if (r.slv.hwrite and hclken) = '1' then
tv.tbreg1.mask := ahbsi2.hwdata(31 downto 2);
tv.tbreg1.read := ahbsi2.hwdata(1);
tv.tbreg1.write := ahbsi2.hwdata(0);
end if;
end if;
when "10110" =>
if TRACEN then
hrdata(31 downto 2) := tr.tbreg2.addr;
if (r.slv.hwrite and hclken) = '1' then
tv.tbreg2.addr := ahbsi2.hwdata(31 downto 2);
end if;
end if;
when "10111" =>
if TRACEN then
hrdata := tr.tbreg2.mask & tr.tbreg2.read & tr.tbreg2.write;
if (r.slv.hwrite and hclken) = '1' then
tv.tbreg2.mask := ahbsi2.hwdata(31 downto 2);
tv.tbreg2.read := ahbsi2.hwdata(1);
tv.tbreg2.write := ahbsi2.hwdata(0);
end if;
end if;
when others =>
end case;
when "010" => -- AHB tbuf
if TRACEN then
if r.cnt(2 downto 0) = "101" then
if hclken = '1' then v.slv.hready := '1'; else v.slv.hready2 := '1'; end if;
end if;
vabufi.enable := not (tr.enable and not r.act);
case tr.haddr(3 downto 2) is
when "00" =>
hrdata := tbo.data(127 downto 96);
if (r.slv.hwrite and hclken) = '1' then
vabufi.write(3) := vabufi.enable and v.slv.hready;
end if;
when "01" =>
hrdata := tbo.data(95 downto 64);
if (r.slv.hwrite and hclken) = '1' then
vabufi.write(2) := vabufi.enable and v.slv.hready;
end if;
when "10" =>
hrdata := tbo.data(63 downto 32);
if (r.slv.hwrite and hclken) = '1' then
vabufi.write(1) := vabufi.enable and v.slv.hready;
end if;
when others =>
hrdata := tbo.data(31 downto 0);
if (r.slv.hwrite and hclken) = '1' then
vabufi.write(0) := vabufi.enable and v.slv.hready;
end if;
end case;
else
if hclken = '1' then v.slv.hready := '1'; else v.slv.hready2 := '1'; end if;
end if;
when "011" | "001" => -- IU reg file, IU tbuf
iuacc := '1';
hrdata := dbgi(index).data;
if r.cnt(2 downto 0) = "101" then
if hclken = '1' then v.slv.hready := '1'; else v.slv.hready2 := '1'; end if;
end if;
when "100" => -- IU reg access
iuacc := '1';
hrdata := dbgi(index).data;
if r.cnt(1 downto 0) = "11" then
if hclken = '1' then v.slv.hready := '1'; else v.slv.hready2 := '1'; end if;
end if;
when "111" => -- DSU ASI
if r.cnt(2 downto 1) = "11" then iuacc := '1'; else iuacc := '0'; end if;
if (dbgi(index).crdy = '1') or (r.cnt = "000") then
if hclken = '1' then v.slv.hready := '1'; else v.slv.hready2 := '1'; end if;
end if;
hrdata := dbgi(index).data;
when others =>
if hclken = '1' then v.slv.hready := '1'; else v.slv.hready2 := '1'; end if;
end case;
if (r.slv.hready and hclken and not v.slv.hsel) = '1' then v.slv.hready := '0'; end if;
if (clk2x /= 0) and (r.slv.hready2 and hclken) = '1' then v.slv.hready := '1'; end if;
end if;
if r.slv.hsel = '1' then
if (r.slv.hwrite and hclken) = '1' then v.slv.hwdata := ahbsi2.hwdata(31 downto 0); end if;
if (clk2x = 0) or ((r.slv.hready or r.slv.hready2) = '0') then
v.slv.hrdata := hrdata;
end if;
end if;
if ((ahbsi2.hready and ahbsi2.hsel(hindex)) = '1') and (ahbsi2.htrans(1) = '0') then
if (clk2x = 0) or (r.slv.hsel = '0') then
v.slv.hready := '1';
end if;
end if;
if (clk2x /= 0) and (r.slv.hready = '1') then v.slv.hready2 := '0'; end if;
if v.slv.hsel = '0' then v.slv.hready := '1'; end if;
vh.oen := '0';
if (clk2x /= 0) then
if (hclken and r.slv.hsel and (r.slv.hready2 or v.slv.hready)) = '1'
then vh.oen := '1'; end if;
if (r.slv.hsel = '1') and (r.cnt = "111") and (hclken = '0') then iuacc := '0'; end if;
end if;
if (not RESET_ALL) and (rst = '0') then
v.bn := (others => r.dsubre(2)); v.bmsk := (others => '0');
v.dmsk := (others => '0');
v.ss := (others => '0'); v.timer := (others => '0'); v.slv.hsel := '0';
for i in 0 to NCPU-1 loop
v.bw(i) := r.dsubre(2); v.be(i) := r.dsubre(2);
v.bx(i) := r.dsubre(2); v.bz(i) := r.dsubre(2);
v.bs(i) := '0'; v.te(i) := '0';
end loop;
tv.ahbactive := '0'; tv.enable := '0';
tv.hsel := '0'; tv.dcnten := '0';
tv.tbreg1.read := '0'; tv.tbreg1.write := '0';
tv.tbreg2.read := '0'; tv.tbreg2.write := '0';
v.slv.hready := '1'; v.halt := (others => '0');
v.act := '0'; v.tstop := '0';
end if;
vabufi.enable := vabufi.enable and not ahbsi.scanen;
vabufi.diag := ahbsi.testen & "000";
rin <= v; trin <= tv; tbi <= vabufi;
for i in 0 to NCPU-1 loop
dbgo(i).tenable <= r.te(i);
dbgo(i).dsuen <= r.en(i);
dbgo(i).dbreak <= r.bn(i); -- or (dbgmode and r.bmsk(i));
if conv_integer(r.slv.haddr(PROC_H downto PROC_L)) = i then
dbgo(i).denable <= iuacc;
else
dbgo(i).denable <= '0';
end if;
dbgo(i).step <= r.ss(i);
dbgo(i).berror <= r.be(i);
dbgo(i).bsoft <= r.bs(i);
dbgo(i).bwatch <= r.bw(i);
dbgo(i).btrapa <= r.bx(i);
dbgo(i).btrape <= r.bz(i);
dbgo(i).daddr <= r.slv.haddr(PROC_L-1 downto 2);
dbgo(i).ddata <= r.slv.hwdata(31 downto 0);
dbgo(i).dwrite <= r.slv.hwrite;
dbgo(i).halt <= r.halt(i);
dbgo(i).reset <= r.reset(i);
dbgo(i).timer(tbits-1 downto 0) <= r.timer;
dbgo(i).timer(30 downto tbits) <= (others => '0');
end loop;
ahbso.hconfig <= hconfig;
ahbso.hresp <= HRESP_OKAY;
ahbso.hready <= r.slv.hready;
if (clk2x = 0) then
ahbso.hrdata <= ahbdrivedata(r.slv.hrdata);
else
ahbso.hrdata <= ahbdrivedata(hrdata2x);
end if;
ahbso.hsplit <= (others => '0');
ahbso.hirq <= hirq;
ahbso.hindex <= hindex;
dsuo.active <= r.act;
dsuo.tstop <= tstop;
dsuo.pwd <= cpwd;
rhin <= vh;
end process;
comb2gen0 : if (clk2x /= 0) generate
-- register i/f
gen0 : for i in ahbsi.hsel'range generate
ag0 : clkand generic map (tech => 0, ren => 0) port map (ahbsi.hsel(i), hclken, ahbsi2.hsel(i));
end generate;
gen1 : for i in ahbsi.haddr'range generate
ag1 : clkand generic map (tech => 0, ren => 0) port map (ahbsi.haddr(i), hclken, ahbsi2.haddr(i));
end generate;
ag2 : clkand generic map (tech => 0, ren => 0) port map (ahbsi.hwrite, hclken, ahbsi2.hwrite);
gen3 : for i in ahbsi.htrans'range generate
ag3 : clkand generic map (tech => 0, ren => 0) port map (ahbsi.htrans(i), hclken, ahbsi2.htrans(i));
end generate;
gen4 : for i in ahbsi.hwdata'range generate
ag4 : clkand generic map (tech => 0, ren => 0) port map (ahbsi.hwdata(i), hclken, ahbsi2.hwdata(i));
end generate;
ag5 : clkand generic map (tech => 0, ren => 0) port map (ahbsi.hready, hclken, ahbsi2.hready);
-- not used by register i/f:
ahbsi2.hsize <= (others => '0');
ahbsi2.hburst <= (others => '0');
ahbsi2.hprot <= (others => '0');
ahbsi2.hmaster <= (others => '0');
ahbsi2.hmastlock <= '0';
ahbsi2.hmbsel <= (others => '0');
ahbsi2.hirq <= (others => '0');
ahbsi2.testen <= '0';
ahbsi2.testrst <= '0';
ahbsi2.scanen <= '0';
ahbsi2.testoen <= '0';
-- trace buffer:
gen6 : for i in tahbsi.haddr'range generate
ag6 : clkand generic map (tech => 0, ren => 0) port map (tahbsi.haddr(i), hclken, tahbsi2.haddr(i));
end generate;
ag7 : clkand generic map (tech => 0, ren => 0) port map (tahbsi.hwrite, hclken, tahbsi2.hwrite);
gen8 : for i in tahbsi.htrans'range generate
ag8 : clkand generic map (tech => 0, ren => 0) port map (tahbsi.htrans(i), hclken, tahbsi2.htrans(i));
end generate;
gen9 : for i in tahbsi.hsize'range generate
ag9 : clkand generic map (tech => 0, ren => 0) port map (tahbsi.hsize(i), hclken, tahbsi2.hsize(i));
end generate;
gen10 : for i in tahbsi.hburst'range generate
a10 : clkand generic map (tech => 0, ren => 0) port map (tahbsi.hburst(i), hclken, tahbsi2.hburst(i));
end generate;
gen11 : for i in tahbsi.hwdata'range generate
ag11 : clkand generic map (tech => 0, ren => 0) port map (tahbsi.hwdata(i), hclken, tahbsi2.hwdata(i));
end generate;
ag12 : clkand generic map (tech => 0, ren => 0) port map (tahbsi.hready, hclken, tahbsi2.hready);
gen12 : for i in tahbsi.hmaster'range generate
ag12 : clkand generic map (tech => 0, ren => 0) port map (tahbsi.hmaster(i), hclken, tahbsi2.hmaster(i));
end generate;
ag13 : clkand generic map (tech => 0, ren => 0) port map (tahbsi.hmastlock, hclken, tahbsi2.hmastlock);
gen14 : for i in tahbsi.hsel'range generate
ag14 : clkand generic map (tech => 0, ren => 0) port map (tahbsi.hsel(i), hclken, tahbsi2.hsel(i));
end generate;
-- not used by trace buffer:
tahbsi2.hprot <= (others => '0');
tahbsi2.hmbsel <= (others => '0');
tahbsi2.hirq <= (others => '0');
tahbsi2.testen <= '0';
tahbsi2.testrst <= '0';
tahbsi2.scanen <= '0';
tahbsi2.testoen <= '0';
gen15 : for i in hrdata2x'range generate
ag15 : clkand generic map (tech => 0, ren => 0) port map (r.slv.hrdata(i), rh.oen, hrdata2x(i));
end generate;
reg2 : process(hclk)
begin
if rising_edge(hclk) then rh <= rhin; end if;
end process;
end generate;
comb2gen1 : if (clk2x = 0) generate
ahbsi2 <= ahbsi; rh.irq <= '0'; rh.oen <= '0'; hrdata2x <= (others => '0');
tahbsi2 <= tahbsi;
end generate;
reg : process(cpuclk)
begin
if rising_edge(cpuclk) then
r <= rin;
if RESET_ALL and (rst = '0') then
r <= RRES;
for i in 0 to NCPU-1 loop
r.bn(i) <= r.dsubre(2); r.bw(i) <= r.dsubre(2);
r.be(i) <= r.dsubre(2); r.bx(i) <= r.dsubre(2);
r.bz(i) <= r.dsubre(2);
end loop;
r.dsubre <= rin.dsubre; -- Sync. regs.
r.dsuen <= rin.dsuen;
r.en <= rin.en;
end if;
end if;
end process;
tb0 : if TRACEN generate
treg : process(cpuclk)
begin
if rising_edge(cpuclk) then
tr <= trin;
if RESET_ALL and (rst = '0') then tr <= TRES; end if;
end if;
end process;
mem0 : tbufmem
generic map (tech => tech, tbuf => kbytes, testen => testen) port map (cpuclk, tbi, tbo);
-- pragma translate_off
bootmsg : report_version
generic map ("dsu3_" & tost(hindex) &
": LEON3 Debug support unit + AHB Trace Buffer, " & tost(kbytes) & " kbytes");
-- pragma translate_on
end generate;
notb : if not TRACEN generate
-- pragma translate_off
bootmsg : report_version
generic map ("dsu3_" & tost(hindex) &
": LEON3 Debug support unit");
-- pragma translate_on
end generate;
end;
| gpl-2.0 | 16393d8556d1b317febcb814863e3470 | 0.518949 | 3.352442 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/grlib/amba/ahbctrl.vhd | 1 | 41,808 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
----------------------------------------------------------------------------
-- Entity: ahbctrl
-- File: ahbctrl.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Modified: Edvin Catovic, Gaisler Research
-- Description: AMBA arbiter, decoder and multiplexer with plug&play support
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.config_types.all;
use grlib.config.all;
-- pragma translate_off
use grlib.devices.all;
use std.textio.all;
-- pragma translate_on
entity ahbctrl is
generic (
defmast : integer := 0; -- default master
split : integer := 0; -- split support
rrobin : integer := 0; -- round-robin arbitration
timeout : integer range 0 to 255 := 0; -- HREADY timeout
ioaddr : ahb_addr_type := 16#fff#; -- I/O area MSB address
iomask : ahb_addr_type := 16#fff#; -- I/O area address mask
cfgaddr : ahb_addr_type := 16#ff0#; -- config area MSB address
cfgmask : ahb_addr_type := 16#ff0#; -- config area address mask
nahbm : integer range 1 to NAHBMST := NAHBMST; -- number of masters
nahbs : integer range 1 to NAHBSLV := NAHBSLV; -- number of slaves
ioen : integer range 0 to 15 := 1; -- enable I/O area
disirq : integer range 0 to 1 := 0; -- disable interrupt routing
fixbrst : integer range 0 to 1 := 0; -- support fix-length bursts
debug : integer range 0 to 2 := 2; -- report cores to console
fpnpen : integer range 0 to 1 := 0; -- full PnP configuration decoding
icheck : integer range 0 to 1 := 1;
devid : integer := 0; -- unique device ID
enbusmon : integer range 0 to 1 := 0; --enable bus monitor
assertwarn : integer range 0 to 1 := 0; --enable assertions for warnings
asserterr : integer range 0 to 1 := 0; --enable assertions for errors
hmstdisable : integer := 0; --disable master checks
hslvdisable : integer := 0; --disable slave checks
arbdisable : integer := 0; --disable arbiter checks
mprio : integer := 0; --master with highest priority
mcheck : integer range 0 to 2 := 1; --check memory map for intersects
ccheck : integer range 0 to 1 := 1; --perform sanity checks on pnp config
acdm : integer := 0; --AMBA compliant data muxing (for hsize > word)
index : integer := 0; --Index for trace print-out
ahbtrace : integer := 0; --AHB trace enable
hwdebug : integer := 0; --Hardware debug
fourgslv : integer := 0 --1=Single slave with single 4 GB bar
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
msti : out ahb_mst_in_type;
msto : in ahb_mst_out_vector;
slvi : out ahb_slv_in_type;
slvo : in ahb_slv_out_vector;
testen : in std_ulogic := '0';
testrst : in std_ulogic := '1';
scanen : in std_ulogic := '0';
testoen : in std_ulogic := '1';
testsig : in std_logic_vector(1+GRLIB_CONFIG_ARRAY(grlib_techmap_testin_extra) downto 0) := (others => '0')
);
end;
architecture rtl of ahbctrl is
constant nahbmx : integer := 2**log2(nahbm);
type nmstarr is array (1 to 3) of integer range 0 to nahbmx-1;
type nvalarr is array (1 to 3) of boolean;
type reg_type is record
hmaster : integer range 0 to nahbmx -1;
hmasterd : integer range 0 to nahbmx -1;
hslave : integer range 0 to nahbs-1;
hmasterlock : std_ulogic;
hmasterlockd : std_ulogic;
hready : std_ulogic;
defslv : std_ulogic;
htrans : std_logic_vector(1 downto 0);
hsize : std_logic_vector(2 downto 0);
haddr : std_logic_vector(15 downto 2);
cfgsel : std_ulogic;
cfga11 : std_ulogic;
hrdatam : std_logic_vector(31 downto 0);
hrdatas : std_logic_vector(31 downto 0);
beat : std_logic_vector(3 downto 0);
defmst : std_ulogic;
ldefmst : std_ulogic;
lsplmst : integer range 0 to nahbmx-1;
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RES_r : reg_type := (
hmaster => 0, hmasterd => 0, hslave => 0, hmasterlock => '0',
hmasterlockd => '0', hready => '1', defslv => '0',
htrans => HTRANS_IDLE, hsize => (others => '0'),
haddr => (others => '0'), cfgsel => '0', cfga11 => '0',
hrdatam => (others => '0'), hrdatas => (others => '0'),
beat => (others => '0'), defmst => '0', ldefmst => '0',
lsplmst => 0);
constant RES_split : std_logic_vector(0 to nahbmx-1) := (others => '0');
constant primst : std_logic_vector(NAHBMST downto 0) := conv_std_logic_vector(mprio, NAHBMST+1);
type l0_type is array (0 to 15) of std_logic_vector(2 downto 0);
type l1_type is array (0 to 7) of std_logic_vector(3 downto 0);
type l2_type is array (0 to 3) of std_logic_vector(4 downto 0);
type l3_type is array (0 to 1) of std_logic_vector(5 downto 0);
type tztab_type is array (0 to 15) of std_logic_vector(2 downto 0);
--returns the index number of the highest priority request
--signal in the two lsb bits when indexed with a 4-bit
--request vector with the highest priority signal on the
--lsb. the returned msb bit indicates if a request was
--active ('1' = no request active corresponds to "0000")
constant tztab : tztab_type := ("100", "000", "001", "000",
"010", "000", "001", "000",
"011", "000", "001", "000",
"010", "000", "001", "000");
--calculate the number of the highest priority request signal(up to 64
--requests are supported) in vect_in using a divide and conquer
--algorithm. The lower the index in the vector the higher the priority
--of the signal. First 4-bit slices are indexed in tztab and the msb
--indicates whether there is an active request or not. Then the resulting
--3 bit vectors are compared in pairs (the one corresponding to (3:0) with
--(7:4), (11:8) with (15:12) and so on). If the least significant of the two
--contains an active signal a '0' is added to the msb side (the vector
--becomes one bit wider at each level) to the next level to indicate that
--there are active signals in the lower nibble of the two. Otherwise
--the msb is removed from the vector corresponding to the higher nibble
--and "10" is added if it does not contain active requests and "01" if
--does contain active signals. Thus the msb still indicates if the new
--slice contains active signals and a '1' is added if it is the higher
--part. This results in a 6-bit vector containing the index number
--of the highest priority master in 5:0 if bit 6 is '0' otherwise
--no master requested the bus.
function tz(vect_in : std_logic_vector) return std_logic_vector is
variable vect : std_logic_vector(63 downto 0);
variable l0 : l0_type;
variable l1 : l1_type;
variable l2 : l2_type;
variable l3 : l3_type;
variable l4 : std_logic_vector(6 downto 0);
variable bci_lsb, bci_msb : std_logic_vector(3 downto 0);
variable bco_lsb, bco_msb : std_logic_vector(2 downto 0);
variable sel : std_logic;
begin
vect := (others => '1');
vect(vect_in'length-1 downto 0) := vect_in;
-- level 0
for i in 0 to 7 loop
bci_lsb := vect(8*i+3 downto 8*i);
bci_msb := vect(8*i+7 downto 8*i+4);
--lookup the highest priority request in each nibble
bco_lsb := tztab(conv_integer(bci_lsb));
bco_msb := tztab(conv_integer(bci_msb));
--select which of two nibbles contain the highest priority ACTIVE
--signal, and forward the corresponding vector to the next level
sel := bco_lsb(2);
if sel = '0' then l1(i) := '0' & bco_lsb;
else l1(i) := bco_msb(2) & not bco_msb(2) & bco_msb(1 downto 0); end if;
end loop;
-- level 1
for i in 0 to 3 loop
sel := l1(2*i)(3);
--select which of two 8-bit vectors contain the
--highest priority ACTIVE signal. the msb set at the previous level
--for each 8-bit slice determines this
if sel = '0' then l2(i) := '0' & l1(2*i);
else
l2(i) := l1(2*i+1)(3) & not l1(2*i+1)(3) & l1(2*i+1)(2 downto 0);
end if;
end loop;
-- level 2
for i in 0 to 1 loop
--16-bit vectors, the msb set at the previous level for each 16-bit
--slice determines the higher priority slice
sel := l2(2*i)(4);
if sel = '0' then l3(i) := '0' & l2(2*i);
else
l3(i) := l2(2*i+1)(4) & not l2(2*i+1)(4) & l2(2*i+1)(3 downto 0);
end if;
end loop;
--level 3
--32-bit vectors, the msb set at the previous level for each 32-bit
--slice determines the higher priority slice
if l3(0)(5) = '0' then l4 := '0' & l3(0);
else l4 := l3(1)(5) & not l3(1)(5) & l3(1)(4 downto 0); end if;
return(l4);
end;
--invert the bit order of the hbusreq signals located in vect_in
--since the highest hbusreq has the highest priority but the
--algorithm in tz has the highest priority on lsb
function lz(vect_in : std_logic_vector) return std_logic_vector is
variable vect : std_logic_vector(vect_in'length-1 downto 0);
variable vect2 : std_logic_vector(vect_in'length-1 downto 0);
begin
vect := vect_in;
for i in vect'right to vect'left loop
vect2(i) := vect(vect'left-i);
end loop;
return(tz(vect2));
end;
-- Find next master:
-- * 2 arbitration policies: fixed priority or round-robin
-- * Fixed priority: priority is fixed, highest index has highest priority
-- * Round-robin: arbiter maintains circular queue of masters
-- * (master 0, master 1, ..., master (nahbmx-1)). First requesting master
-- * in the queue is granted access to the bus and moved to the end of the queue.
-- * splitted masters are not granted
-- * bus is re-arbited when current owner does not request the bus,
-- or when it performs non-burst accesses
-- * fix length burst transfers will not be interrupted
-- * incremental bursts should assert hbusreq until last access
procedure selmast(r : in reg_type;
msto : in ahb_mst_out_vector;
rsplit : in std_logic_vector(0 to nahbmx-1);
mast : out integer range 0 to nahbmx-1;
defmst : out std_ulogic) is
variable nmst : nmstarr;
variable nvalid : nvalarr;
variable rrvec : std_logic_vector(nahbmx*2-1 downto 0);
variable zcnt : std_logic_vector(log2(nahbmx)+1 downto 0);
variable hpvec : std_logic_vector(nahbmx-1 downto 0);
variable zcnt2 : std_logic_vector(log2(nahbmx) downto 0);
begin
nvalid(1 to 3) := (others => false); nmst(1 to 3) := (others => 0);
mast := r.hmaster;
defmst := '0';
if nahbm = 1 then
mast := 0;
elsif rrobin = 0 then
hpvec := (others => '0');
for i in 0 to nahbmx-1 loop
--masters which have received split are not granted
if ((rsplit(i) = '0') or (split = 0)) then
hpvec(i) := msto(i).hbusreq;
end if;
end loop;
--check if any bus requests are active (nvalid(2) set to true)
--and determine the index (zcnt2) of the highest priority master
zcnt2 := lz(hpvec)(log2(nahbmx) downto 0);
if zcnt2(log2(nahbmx)) = '0' then nvalid(2) := true; end if;
nmst(2) := conv_integer(not (zcnt2(log2(nahbmx)-1 downto 0)));
--find the default master number
for i in 0 to nahbmx-1 loop
if not ((nmst(3) = defmast) and nvalid(3)) then
nmst(3) := i; nvalid(3) := true;
end if;
end loop;
else
rrvec := (others => '0');
--mask requests up to and including current master. Concatenate
--an unmasked request vector above the masked vector. Otherwise
--the rules are the same as for fixed priority
for i in 0 to nahbmx-1 loop
if ((rsplit(i) = '0') or (split = 0)) then
if (i <= r.hmaster) then rrvec(i) := '0';
else rrvec(i) := msto(i).hbusreq; end if;
rrvec(nahbmx+i) := msto(i).hbusreq;
end if;
end loop;
--find the next master uzing tz which gives priority to lower
--indexes
zcnt := tz(rrvec)(log2(nahbmx)+1 downto 0);
--was there a master requesting the bus?
if zcnt(log2(nahbmx)+1) = '0' then nvalid(2) := true; end if;
nmst(2) := conv_integer(zcnt(log2(nahbmx)-1 downto 0));
--if no other master is requesting the bus select the current one
nmst(3) := r.hmaster; nvalid(3) := true;
--check if any masters configured with higher priority are requesting
--the bus
if mprio /= 0 then
for i in 0 to nahbm-1 loop
if (((rsplit(i) = '0') or (split = 0)) and (primst(i) = '1')) then
if msto(i).hbusreq = '1' then nmst(1) := i; nvalid(1) := true; end if;
end if;
end loop;
end if;
end if;
--select the next master. If for round robin a high priority master
--(mprio) requested the bus if nvalid(1) is true. Otherwise
--if nvalid(2) is true at least one master was requesting the bus
--and the one with highest priority was selected. If none of these
--were true then the default master is selected (nvalid(3) true)
for i in 1 to 3 loop
if nvalid(i) then mast := nmst(i); exit; end if;
end loop;
--if no master was requesting the bus and split is enabled
--then select builtin dummy master which only does
--idle transfers
if (not (nvalid(1) or nvalid(2))) and (split /= 0) then
defmst := orv(rsplit);
end if;
end;
constant MIMAX : integer := log2x(nahbmx) - 1;
constant SIMAX : integer := log2x(nahbs) - 1;
constant IOAREA : std_logic_vector(11 downto 0) :=
conv_std_logic_vector(ioaddr, 12);
constant IOMSK : std_logic_vector(11 downto 0) :=
conv_std_logic_vector(iomask, 12);
constant CFGAREA : std_logic_vector(11 downto 0) :=
conv_std_logic_vector(cfgaddr, 12);
constant CFGMSK : std_logic_vector(11 downto 0) :=
conv_std_logic_vector(cfgmask, 12);
constant FULLPNP : boolean := (fpnpen /= 0);
signal r, rin : reg_type;
signal rsplit, rsplitin : std_logic_vector(0 to nahbmx-1);
-- pragma translate_off
signal lmsti : ahb_mst_in_type;
signal lslvi : ahb_slv_in_type;
-- pragma translate_on
begin
comb : process(rst, msto, slvo, r, rsplit, testen, testrst, scanen, testoen, testsig)
variable v : reg_type;
variable nhmaster: integer range 0 to nahbmx -1;
variable hgrant : std_logic_vector(0 to NAHBMST-1); -- bus grant
variable hsel : std_logic_vector(0 to 31); -- slave select
variable hmbsel : std_logic_vector(0 to NAHBAMR-1);
variable nslave : natural range 0 to 31;
variable vsplit : std_logic_vector(0 to nahbmx-1);
variable bnslave : std_logic_vector(3 downto 0);
variable area : std_logic_vector(1 downto 0);
variable hready : std_ulogic;
variable defslv : std_ulogic;
variable cfgsel : std_ulogic;
variable hresp : std_logic_vector(1 downto 0);
variable hrdata : std_logic_vector(AHBDW-1 downto 0);
variable haddr : std_logic_vector(31 downto 0);
variable hirq : std_logic_vector(NAHBIRQ-1 downto 0);
variable arb : std_ulogic;
variable hconfndx : integer range 0 to 7;
variable vslvi : ahb_slv_in_type;
variable defmst : std_ulogic;
variable tmpv : std_logic_vector(0 to nahbmx-1);
begin
v := r; hgrant := (others => '0'); defmst := '0';
haddr := msto(r.hmaster).haddr;
nhmaster := r.hmaster;
--determine if bus should be rearbitrated. This is done if the current
--master is not performing a locked transfer and if not in the middle
--of burst
arb := '0';
if (r.hmasterlock or r.ldefmst) = '0' then
case msto(r.hmaster).htrans is
when HTRANS_IDLE => arb := '1';
when HTRANS_NONSEQ =>
case msto(r.hmaster).hburst is
when HBURST_SINGLE => arb := '1';
when HBURST_INCR => arb := not msto(r.hmaster).hbusreq;
when others =>
end case;
when HTRANS_SEQ =>
case msto(r.hmaster).hburst is
when HBURST_WRAP4 | HBURST_INCR4 => if (fixbrst = 1) and (r.beat(1 downto 0) = "11") then arb := '1'; end if;
when HBURST_WRAP8 | HBURST_INCR8 => if (fixbrst = 1) and (r.beat(2 downto 0) = "111") then arb := '1'; end if;
when HBURST_WRAP16 | HBURST_INCR16 => if (fixbrst = 1) and (r.beat(3 downto 0) = "1111") then arb := '1'; end if;
when HBURST_INCR => arb := not msto(r.hmaster).hbusreq;
when others =>
end case;
when others => arb := '0';
end case;
end if;
if (split /= 0) then
for i in 0 to nahbmx-1 loop
tmpv(i) := (msto(i).htrans(1) or (msto(i).hbusreq)) and not rsplit(i) and not r.ldefmst;
end loop;
if (r.defmst and orv(tmpv)) = '1' then arb := '1'; end if;
end if;
--rearbitrate bus with selmast. If not arbitrated one must
--ensure that the dummy master is selected for locked splits.
if (arb = '1') then
selmast(r, msto, rsplit, nhmaster, defmst);
elsif (split /= 0) then
defmst := r.defmst;
end if;
-- slave decoding
hsel := (others => '0'); hmbsel := (others => '0');
if fourgslv = 0 then
for i in 0 to nahbs-1 loop
for j in NAHBIR to NAHBCFG-1 loop
area := slvo(i).hconfig(j)(1 downto 0);
case area is
when "10" =>
if ((ioen = 0) or ((IOAREA and IOMSK) /= (haddr(31 downto 20) and IOMSK))) and
((slvo(i).hconfig(j)(31 downto 20) and slvo(i).hconfig(j)(15 downto 4)) =
(haddr(31 downto 20) and slvo(i).hconfig(j)(15 downto 4))) and
(slvo(i).hconfig(j)(15 downto 4) /= "000000000000")
then hsel(i) := '1'; hmbsel(j-NAHBIR) := '1'; end if;
when "11" =>
if ((ioen /= 0) and ((IOAREA and IOMSK) = (haddr(31 downto 20) and IOMSK))) and
((slvo(i).hconfig(j)(31 downto 20) and slvo(i).hconfig(j)(15 downto 4)) =
(haddr(19 downto 8) and slvo(i).hconfig(j)(15 downto 4))) and
(slvo(i).hconfig(j)(15 downto 4) /= "000000000000")
then hsel(i) := '1'; hmbsel(j-NAHBIR) := '1'; end if;
when others =>
end case;
end loop;
end loop;
else
-- There is only one slave on the bus. The slave has only one bar, which
-- maps 4 GB address space.
hsel(0) := '1'; hmbsel(0) := '1';
end if;
if r.defmst = '1' then hsel := (others => '0'); end if;
bnslave(0) := hsel(1) or hsel(3) or hsel(5) or hsel(7) or
hsel(9) or hsel(11) or hsel(13) or hsel(15);
bnslave(1) := hsel(2) or hsel(3) or hsel(6) or hsel(7) or
hsel(10) or hsel(11) or hsel(14) or hsel(15);
bnslave(2) := hsel(4) or hsel(5) or hsel(6) or hsel(7) or
hsel(12) or hsel(13) or hsel(14) or hsel(15);
bnslave(3) := hsel(8) or hsel(9) or hsel(10) or hsel(11) or
hsel(12) or hsel(13) or hsel(14) or hsel(15);
nslave := conv_integer(bnslave(SIMAX downto 0));
if ((((IOAREA and IOMSK) = (haddr(31 downto 20) and IOMSK)) and (ioen /= 0))
or ((IOAREA = haddr(31 downto 20)) and (ioen = 0))) and
((CFGAREA and CFGMSK) = (haddr(19 downto 8) and CFGMSK))
and (cfgmask /= 0)
then cfgsel := '1'; hsel := (others => '0');
else cfgsel := '0'; end if;
if (nslave = 0) and (hsel(0) = '0') and (cfgsel = '0') then defslv := '1';
else defslv := '0'; end if;
if r.defmst = '1' then
cfgsel := '0'; defslv := '1';
end if;
-- error response on undecoded area
v.hready := '0';
hready := slvo(r.hslave).hready; hresp := slvo(r.hslave).hresp;
if r.defslv = '1' then
-- default slave
if (r.htrans = HTRANS_IDLE) or (r.htrans = HTRANS_BUSY) then
hresp := HRESP_OKAY; hready := '1';
else
-- return two-cycle error in case of unimplemented slave access
hresp := HRESP_ERROR; hready := r.hready; v.hready := not r.hready;
end if;
end if;
if acdm = 0 then
hrdata := slvo(r.hslave).hrdata;
else
hrdata := ahbselectdata(slvo(r.hslave).hrdata, r.haddr(4 downto 2), r.hsize);
end if;
if cfgmask /= 0 then
-- plug&play information for masters
if FULLPNP then hconfndx := conv_integer(r.haddr(4 downto 2)); else hconfndx := 0; end if;
if (r.haddr(10 downto MIMAX+6) = zero32(10 downto MIMAX+6)) and (FULLPNP or (r.haddr(4 downto 2) = "000"))
then v.hrdatam := msto(conv_integer(r.haddr(MIMAX+5 downto 5))).hconfig(hconfndx);
else v.hrdatam := (others => '0'); end if;
-- plug&play information for slaves
if (r.haddr(10 downto SIMAX+6) = zero32(10 downto SIMAX+6)) and
(FULLPNP or (r.haddr(4 downto 2) = "000") or (r.haddr(4) = '1'))
then v.hrdatas := slvo(conv_integer(r.haddr(SIMAX+5 downto 5))).hconfig(conv_integer(r.haddr(4 downto 2)));
else v.hrdatas := (others => '0'); end if;
-- device ID, library build and potentially debug information
if r.haddr(10 downto 4) = "1111111" then
if hwdebug = 0 or r.haddr(3 downto 2) = "00" then
v.hrdatas(15 downto 0) := conv_std_logic_vector(LIBVHDL_BUILD, 16);
v.hrdatas(31 downto 16) := conv_std_logic_vector(devid, 16);
elsif r.haddr(3 downto 2) = "01" then
for i in 0 to nahbmx-1 loop v.hrdatas(i) := msto(i).hbusreq; end loop;
else
for i in 0 to nahbmx-1 loop v.hrdatas(i) := rsplit(i); end loop;
end if;
end if;
if r.cfgsel = '1' then
hrdata := (others => '0');
-- default slave
if (r.htrans = HTRANS_IDLE) or (r.htrans = HTRANS_BUSY) then
hresp := HRESP_OKAY; hready := '1';
else
-- return two-cycle read/write respons
hresp := HRESP_OKAY; hready := r.hready; v.hready := not r.hready;
end if;
if r.cfga11 = '0' then hrdata := ahbdrivedata(r.hrdatam);
else hrdata := ahbdrivedata(r.hrdatas); end if;
end if;
end if;
--degrant all masters when split occurs for locked access
if (r.hmasterlockd = '1') then
if (hresp = HRESP_RETRY) or ((split /= 0) and (hresp = HRESP_SPLIT)) then
nhmaster := r.hmaster;
end if;
if split /= 0 then
if hresp = HRESP_SPLIT then
v.ldefmst := '1'; defmst := '1';
v.lsplmst := nhmaster;
end if;
end if;
end if;
if split /= 0 and r.ldefmst = '1' then
if rsplit(r.lsplmst) = '0' then
v.ldefmst := '0'; defmst := '0';
end if;
end if;
if (split = 0) or (defmst = '0') then hgrant(nhmaster) := '1'; end if;
-- latch active master and slave
if hready = '1' then
v.hmaster := nhmaster; v.hmasterd := r.hmaster;
v.hsize := msto(r.hmaster).hsize;
v.hslave := nslave; v.defslv := defslv;
v.hmasterlockd := r.hmasterlock;
if (split = 0) or (r.defmst = '0') then v.htrans := msto(r.hmaster).htrans;
else v.htrans := HTRANS_IDLE; end if;
v.cfgsel := cfgsel;
v.cfga11 := msto(r.hmaster).haddr(11);
v.haddr := msto(r.hmaster).haddr(15 downto 2);
if (msto(r.hmaster).htrans = HTRANS_NONSEQ) or (msto(r.hmaster).htrans = HTRANS_IDLE) then
v.beat := "0001";
elsif (msto(r.hmaster).htrans = HTRANS_SEQ) then
if (fixbrst = 1) then v.beat := r.beat + 1; end if;
end if;
if (split /= 0) then v.defmst := defmst; end if;
end if;
--assign new hmasterlock, v.hmaster is used because if hready
--then master can have changed, and when not hready then the
--previous master will still be selected
v.hmasterlock := msto(v.hmaster).hlock or (r.hmasterlock and not hready);
--if the master asserting hlock received a SPLIT/RETRY response
--to the previous access then disregard the current lock request.
--the bus will otherwise be locked when the previous access is
--retried instead of treating hlock as coupled to the next access.
--use hmasterlockd to keep the bus locked for SPLIT/RETRY to locked
--accesses.
if v.hmaster = r.hmasterd and slvo(r.hslave).hresp(1) = '1' then
if r.hmasterlockd = '0' then
v.hmasterlock := '0'; v.hmasterlockd := '0';
end if;
end if;
-- split support
vsplit := (others => '0');
if SPLIT /= 0 then
vsplit := rsplit;
if slvo(r.hslave).hresp = HRESP_SPLIT then vsplit(r.hmasterd) := '1'; end if;
for i in 0 to nahbs-1 loop
for j in 0 to nahbmx-1 loop
vsplit(j) := vsplit(j) and not slvo(i).hsplit(j);
end loop;
end loop;
end if;
-- interrupt merging
hirq := (others => '0');
if disirq = 0 then
for i in 0 to nahbs-1 loop hirq := hirq or slvo(i).hirq; end loop;
for i in 0 to nahbm-1 loop hirq := hirq or msto(i).hirq; end loop;
end if;
if (split = 0) or (r.defmst = '0') then
vslvi.haddr := haddr;
vslvi.htrans := msto(r.hmaster).htrans;
vslvi.hwrite := msto(r.hmaster).hwrite;
vslvi.hsize := msto(r.hmaster).hsize;
vslvi.hburst := msto(r.hmaster).hburst;
vslvi.hready := hready;
vslvi.hprot := msto(r.hmaster).hprot;
-- vslvi.hmastlock := msto(r.hmaster).hlock;
vslvi.hmastlock := r.hmasterlock;
vslvi.hmaster := conv_std_logic_vector(r.hmaster, 4);
vslvi.hsel := hsel(0 to NAHBSLV-1);
vslvi.hmbsel := hmbsel;
vslvi.hirq := hirq;
else
vslvi := ahbs_in_none;
vslvi.hready := hready;
vslvi.hirq := hirq;
end if;
if acdm = 0 then
vslvi.hwdata := msto(r.hmasterd).hwdata;
else
vslvi.hwdata := ahbselectdata(msto(r.hmasterd).hwdata, r.haddr(4 downto 2), r.hsize);
end if;
vslvi.testen := testen;
vslvi.testrst := testrst;
vslvi.scanen := scanen and testen;
vslvi.testoen := testoen;
vslvi.testin := testen & (scanen and testen) & testsig;
-- reset operation
if (not RESET_ALL) and (rst = '0') then
v.hmaster := RES_r.hmaster; v.hmasterlock := RES_r.hmasterlock;
vsplit := (others => '0');
v.htrans := RES_r.htrans; v.defslv := RES_r.defslv;
v.hslave := RES_r.hslave; v.cfgsel := RES_r.cfgsel;
v.defmst := RES_r.defmst; v.ldefmst := RES_r.ldefmst;
end if;
-- drive master inputs
msti.hgrant <= hgrant;
msti.hready <= hready;
msti.hresp <= hresp;
msti.hrdata <= hrdata;
msti.hirq <= hirq;
msti.testen <= testen;
msti.testrst <= testrst;
msti.scanen <= scanen and testen;
msti.testoen <= testoen;
msti.testin <= testen & (scanen and testen) & testsig;
-- drive slave inputs
slvi <= vslvi;
-- pragma translate_off
--drive internal signals to bus monitor
lslvi <= vslvi;
lmsti.hgrant <= hgrant;
lmsti.hready <= hready;
lmsti.hresp <= hresp;
lmsti.hrdata <= hrdata;
lmsti.hirq <= hirq;
-- pragma translate_on
if split = 0 then v.ldefmst := '0'; v.lsplmst := 0; end if;
rin <= v; rsplitin <= vsplit;
end process;
reg0 : process(clk)
begin
if rising_edge(clk) then
r <= rin;
if RESET_ALL and rst = '0' then
r <= RES_r;
end if;
end if;
if (split = 0) then r.defmst <= '0'; end if;
end process;
splitreg : if SPLIT /= 0 generate
reg1 : process(clk)
begin
if rising_edge(clk) then
rsplit <= rsplitin;
if RESET_ALL and rst = '0' then
rsplit <= RES_split;
end if;
end if;
end process;
end generate;
nosplitreg : if SPLIT = 0 generate
rsplit <= (others => '0');
end generate;
-- pragma translate_off
ahblog : if ahbtrace /= 0 generate
log : process (clk)
variable hwrite : std_logic;
variable hsize : std_logic_vector(2 downto 0);
variable htrans : std_logic_vector(1 downto 0);
variable hmaster : std_logic_vector(3 downto 0);
variable haddr : std_logic_vector(31 downto 0);
variable hwdata, hrdata : std_logic_vector(127 downto 0);
variable mbit, bitoffs : integer;
variable t : integer;
begin
if rising_edge(clk) then
if htrans(1)='1' and lmsti.hready='0' and (lmsti.hresp="01") then
if hwrite = '1' then
grlib.testlib.print("mst" & tost(hmaster) & ": " & tost(haddr) & " write " & tost(mbit/8) & " bytes [" & tost(lslvi.hwdata(mbit-1+bitoffs downto bitoffs)) & "] - ERROR!");
else
grlib.testlib.print("mst" & tost(hmaster) & ": " & tost(haddr) & " read " & tost(mbit/8) & " bytes [" & tost(lmsti.hrdata(mbit-1+bitoffs downto bitoffs)) & "] - ERROR!");
end if;
end if;
if ((htrans(1) and lmsti.hready) = '1') and (lmsti.hresp = "00") then
mbit := 2**conv_integer(hsize)*8;
bitoffs := 0;
if mbit < ahbdw then
bitoffs := mbit * conv_integer(haddr(log2(ahbdw/8)-1 downto conv_integer(hsize)));
bitoffs := lslvi.hwdata'length-mbit-bitoffs;
end if;
t := (now/1 ns);
if hwrite = '1' then
grlib.testlib.print("mst" & tost(hmaster) & ": " & tost(haddr) & " write " & tost(mbit/8) & " bytes [" & tost(lslvi.hwdata(mbit-1+bitoffs downto bitoffs)) & "]");
else
grlib.testlib.print("mst" & tost(hmaster) & ": " & tost(haddr) & " read " & tost(mbit/8) & " bytes [" & tost(lmsti.hrdata(mbit-1+bitoffs downto bitoffs)) & "]");
end if;
end if;
if lmsti.hready = '1' then
hwrite := lslvi.hwrite;
hsize := lslvi.hsize;
haddr := lslvi.haddr;
htrans := lslvi.htrans;
hmaster := lslvi.hmaster;
end if;
end if;
end process;
end generate;
mon0 : if enbusmon /= 0 generate
mon : ahbmon
generic map(
asserterr => asserterr,
assertwarn => assertwarn,
hmstdisable => hmstdisable,
hslvdisable => hslvdisable,
arbdisable => arbdisable,
nahbm => nahbm,
nahbs => nahbs)
port map(
rst => rst,
clk => clk,
ahbmi => lmsti,
ahbmo => msto,
ahbsi => lslvi,
ahbso => slvo,
err => open);
end generate;
diag : process
type ahbsbank_type is record
start : std_logic_vector(31 downto 8);
stop : std_logic_vector(31 downto 8);
io : std_ulogic;
end record;
type ahbsbanks_type is array (0 to 3) of ahbsbank_type;
type memmap_type is array (0 to nahbs-1) of ahbsbanks_type;
variable k : integer;
variable mask : std_logic_vector(11 downto 0);
variable device : std_logic_vector(11 downto 0);
variable devicei : integer;
variable vendor : std_logic_vector( 7 downto 0);
variable area : std_logic_vector( 1 downto 0);
variable vendori : integer;
variable iosize, tmp : integer;
variable iounit : string(1 to 5) := " byte";
variable memtype : string(1 to 9);
variable iostart : std_logic_vector(11 downto 0) := IOAREA and IOMSK;
variable cfgstart : std_logic_vector(11 downto 0) := CFGAREA and CFGMSK;
variable L1 : line := new string'("");
variable S1 : string(1 to 255);
variable memmap : memmap_type;
begin
wait for 2 ns;
if debug = 0 then wait; end if;
if debug > 0 then
k := 0; mask := IOMSK;
while (k<12) and (mask(k) = '0') loop k := k+1; end loop;
print("ahbctrl: AHB arbiter/multiplexer rev 1");
if ioen /= 0 then
print("ahbctrl: Common I/O area at " & tost(iostart) & "00000, " & tost(2**k) & " Mbyte");
else
print("ahbctrl: Common I/O area disabled");
end if;
print("ahbctrl: AHB masters: " & tost(nahbm) & ", AHB slaves: " & tost(nahbs));
if cfgmask /= 0 then
print("ahbctrl: Configuration area at " & tost(iostart & cfgstart) & "00, 4 kbyte");
else
print("ahbctrl: Configuration area disabled");
end if;
end if;
for i in 0 to nahbm-1 loop
vendor := msto(i).hconfig(0)(31 downto 24);
vendori := conv_integer(vendor);
if vendori /= 0 then
if debug > 1 then
device := msto(i).hconfig(0)(23 downto 12);
devicei := conv_integer(device);
print("ahbctrl: mst" & tost(i) & ": " & iptable(vendori).vendordesc &
iptable(vendori).device_table(devicei));
end if;
for j in 1 to NAHBIR-1 loop
assert (msto(i).hconfig(j) = zx or FULLPNP or ccheck = 0 or cfgmask = 0)
report "AHB master " & tost(i) & " propagates non-zero user defined PnP data, " &
"but AHBCTRL full PnP decoding has not been enabled (check fpnpen VHDL generic)"
severity warning;
end loop;
assert (msto(i).hindex = i) or (icheck = 0)
report "AHB master index error on master " & tost(i) &
". Detected index value " & tost(msto(i).hindex) severity failure;
else
for j in 0 to NAHBCFG-1 loop
assert (msto(i).hconfig(j) = zx or ccheck = 0)
report "AHB master " & tost(i) & " appears to be disabled, " &
"but the master config record is not driven to zero " &
"(check vendor ID or drive unused bus index with appropriate values)."
severity warning;
end loop;
end if;
end loop;
if nahbm < NAHBMST then
for i in nahbm to NAHBMST-1 loop
for j in 0 to NAHBCFG-1 loop
assert (msto(i).hconfig(j) = zx or ccheck = 0)
report "AHB master " & tost(i) & " is outside the range of " &
"decoded master indexes but the master config record is not driven to zero " &
"(check nahbm VHDL generic)."
severity warning;
end loop;
end loop;
end if;
for i in 0 to nahbs-1 loop
vendor := slvo(i).hconfig(0)(31 downto 24);
vendori := conv_integer(vendor);
if vendori /= 0 then
if debug > 1 then
device := slvo(i).hconfig(0)(23 downto 12);
devicei := conv_integer(device);
std.textio.write(L1, "ahbctrl: slv" & tost(i) & ": " & iptable(vendori).vendordesc &
iptable(vendori).device_table(devicei));
std.textio.writeline(OUTPUT, L1);
end if;
for j in 1 to NAHBIR-1 loop
assert (slvo(i).hconfig(j) = zx or FULLPNP or ccheck = 0 or cfgmask = 0)
report "AHB slave " & tost(i) & " propagates non-zero user defined PnP data, " &
"but AHBCTRL full PnP decoding has not been enabled (check fpnpen VHDL generic)."
severity warning;
end loop;
for j in NAHBIR to NAHBCFG-1 loop
area := slvo(i).hconfig(j)(1 downto 0);
mask := slvo(i).hconfig(j)(15 downto 4);
memmap(i)(j mod NAHBIR).start := (others => '0');
memmap(i)(j mod NAHBIR).stop := (others => '0');
memmap(i)(j mod NAHBIR).io := slvo(i).hconfig(j)(0);
if (mask /= "000000000000" or fourgslv = 1) then
case area is
when "01" =>
when "10" =>
k := 0;
while (k<12) and (mask(k) = '0') loop k := k+1; end loop;
if debug > 1 then
std.textio.write(L1, "ahbctrl: memory at " &
tost(slvo(i).hconfig(j)(31 downto 20) and mask) &
"00000, size "& tost(2**k) & " Mbyte");
if slvo(i).hconfig(j)(16) = '1' then
std.textio.write(L1, string'(", cacheable"));
end if;
if slvo(i).hconfig(j)(17) = '1' then
std.textio.write(L1, string'(", prefetch"));
end if;
std.textio.writeline(OUTPUT, L1);
end if;
memmap(i)(j mod NAHBIR).start(31 downto 20) := slvo(i).hconfig(j)(31 downto 20);
memmap(i)(j mod NAHBIR).start(31 downto 20) :=
(slvo(i).hconfig(j)(31 downto 20) and mask);
memmap(i)(j mod NAHBIR).start(19 downto 8) := (others => '0');
memmap(i)(j mod NAHBIR).stop := memmap(i)(j mod NAHBIR).start + 2**(k+12) - 1;
-- Be verbose if an address with bits set outside the area
-- selected by the mask is encountered
assert ((slvo(i).hconfig(j)(31 downto 20) and not mask) = zero32(11 downto 0)) report
"AHB slave " & tost(i) & " may decode an area larger than intended. Bar " &
tost(j mod NAHBIR) & " will have base address " &
tost(slvo(i).hconfig(j)(31 downto 20) and mask) &
"00000, the intended base address may have been " &
tost(slvo(i).hconfig(j)(31 downto 20)) & "00000"
severity warning;
when "11" =>
if ioen /= 0 then
k := 0;
while (k<12) and (mask(k) = '0') loop k := k+1; end loop;
memmap(i)(j mod NAHBIR).start := iostart & (slvo(i).hconfig(j)(31 downto 20) and
slvo(i).hconfig(j)(15 downto 4));
memmap(i)(j mod NAHBIR).stop := memmap(i)(j mod NAHBIR).start + 2**k - 1;
if debug > 1 then
iosize := 256 * 2**k; iounit(1) := ' ';
if (iosize > 1023) then
iosize := iosize/1024; iounit(1) := 'k';
end if;
print("ahbctrl: I/O port at " & tost(iostart &
((slvo(i).hconfig(j)(31 downto 20)) and slvo(i).hconfig(j)(15 downto 4))) &
"00, size "& tost(iosize) & iounit);
end if;
assert ((slvo(i).hconfig(j)(31 downto 20) and not mask) = zero32(11 downto 0)) report
"AHB slave " & tost(i) & " may decode an I/O area larger than intended. Bar " &
tost(j mod NAHBIR) & " will have base address " &
tost(iostart & (slvo(i).hconfig(j)(31 downto 20) and mask)) &
"00, the intended base address may have been " &
tost(iostart & slvo(i).hconfig(j)(31 downto 20)) & "00"
severity warning;
else
assert false report
"AHB slave " & tost(i) & " maps bar " & tost(j mod NAHBIR) &
" to the IO area, but this AHBCTRL has been configured with VHDL generic ioen = 0"
severity warning;
end if;
when others =>
end case;
end if;
end loop;
assert (slvo(i).hindex = i) or (icheck = 0)
report "AHB slave index error on slave " & tost(i) &
". Detected index value " & tost(slvo(i).hindex) severity failure;
if mcheck /= 0 then
for j in 0 to i loop
for k in memmap(i)'range loop
if memmap(i)(k).stop /= zero32(memmap(i)(k).stop'range) then
for l in memmap(j)'range loop
assert ((memmap(i)(k).start >= memmap(j)(l).stop) or
(memmap(i)(k).stop <= memmap(j)(l).start) or
(mcheck /= 2 and (memmap(i)(k).io xor memmap(j)(l).io) = '1') or
(i = j and k = l))
report "AHB slave " & tost(i) & " bank " & tost(k) &
" intersects with AHB slave " & tost(j) & " bank " & tost(l)
severity failure;
end loop;
end if;
end loop;
end loop;
end if;
else
for j in 0 to NAHBCFG-1 loop
assert (slvo(i).hconfig(j) = zx or ccheck = 0)
report "AHB slave " & tost(i) & " appears to be disabled, " &
"but the slave config record is not driven to zero " &
"(check vendor ID or drive unused bus index with appropriate values)."
severity warning;
end loop;
end if;
end loop;
if nahbs < NAHBSLV then
for i in nahbs to NAHBSLV-1 loop
for j in 0 to NAHBCFG-1 loop
assert (slvo(i).hconfig(j) = zx or ccheck = 0)
report "AHB slave " & tost(i) & " is outside the range of " &
"decoded slave indexes but the slave config record is not driven to zero " &
"(check nahbs VHDL generic)."
severity warning;
end loop;
end loop;
end if;
wait;
end process;
-- pragma translate_on
end;
| gpl-2.0 | cb94fb6dd94db80efd3837efa043d975 | 0.573359 | 3.600103 | false | true | false | false |
eamadio/fpgaMSP430 | fmsp430/misc/fmsp_scan_mux.vhd | 1 | 3,014 | ------------------------------------------------------------------------------
--! Copyright (C) 2009 , Olivier Girard
--
--! Redistribution and use in source and binary forms, with or without
--! modification, are permitted provided that the following conditions
--! are met:
--! * Redistributions of source code must retain the above copyright
--! notice, this list of conditions and the following disclaimer.
--! * Redistributions in binary form must reproduce the above copyright
--! notice, this list of conditions and the following disclaimer in the
--! documentation and/or other materials provided with the distribution.
--! * Neither the name of the authors nor the names of its contributors
--! may be used to endorse or promote products derived from this software
--! without specific prior written permission.
--
--! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
--! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
--! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
--! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
--! OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
--! THE POSSIBILITY OF SUCH DAMAGE
--
------------------------------------------------------------------------------
--!
--! @file fmsp_scan_mux.vhd
--!
--! @brief fpgaMSP430 Generic mux for scan mode
--
--! @author Olivier Girard, [email protected]
--! @author Emmanuel Amadio, [email protected] (VHDL Rewrite)
--
------------------------------------------------------------------------------
--! @version 1
--! @date: 2017-04-21
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all; --! standard unresolved logic UX01ZWLH-
entity fmsp_scan_mux is
port (
--! INPUTs
data_in_scan : in std_logic; --! Selected data input for scan mode
data_in_func : in std_logic; --! Selected data input for functional mode
scan_mode : in std_logic; --! Scan mode
--! OUTPUTs
data_out : out std_logic --! Scan mux data output
);
end entity fmsp_scan_mux;
architecture RTL of fmsp_scan_mux is
begin
--=============================================================================
--! 1) SCAN MUX
--=============================================================================
DATA_MUX : process(scan_mode,data_in_scan,data_in_func)
begin
if (scan_mode = '1') then
data_out <= data_in_scan;
else
data_out <= data_in_func;
end if;
end process DATA_MUX;
end RTL; --! fmsp_scan_mux
| bsd-3-clause | 0199f114d7efa6896dc7ce05632401a3 | 0.601526 | 4.368116 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/led_controller/led_controller.srcs/sources_1/bd/led_controller_design/ip/led_controller_design_auto_pc_0/led_controller_design_auto_pc_0_sim_netlist.vhdl | 1 | 510,749 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 15:20:13 2017
-- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
-- Command : write_vhdl -force -mode funcsim -rename_top led_controller_design_auto_pc_0 -prefix
-- led_controller_design_auto_pc_0_ led_controller_design_auto_pc_0_sim_netlist.vhdl
-- Design : led_controller_design_auto_pc_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_incr_cmd is
port (
next_pending_r_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[0]_0\ : out STD_LOGIC;
\axlen_cnt_reg[0]_0\ : out STD_LOGIC;
\axaddr_incr_reg[11]_0\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
\m_axi_awaddr[11]\ : out STD_LOGIC;
\m_axi_awaddr[3]\ : out STD_LOGIC;
\m_axi_awaddr[2]\ : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_reg_0 : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
si_rs_awvalid : in STD_LOGIC;
\m_payload_i_reg[46]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep\ : in STD_LOGIC;
axaddr_incr : in STD_LOGIC_VECTOR ( 11 downto 0 );
\state_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[0]_rep\ : in STD_LOGIC
);
end led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_incr_cmd;
architecture STRUCTURE of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_incr_cmd is
signal \axaddr_incr[11]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_11_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_12_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_13_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_14_n_0\ : STD_LOGIC;
signal \^axaddr_incr_reg[0]_0\ : STD_LOGIC;
signal \^axaddr_incr_reg[11]_0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \axaddr_incr_reg[11]_i_4_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_4_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_4_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_4_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_4_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_4_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_4_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg_n_0_[2]\ : STD_LOGIC;
signal \axaddr_incr_reg_n_0_[3]\ : STD_LOGIC;
signal \axlen_cnt[0]_i_1__1_n_0\ : STD_LOGIC;
signal \axlen_cnt[1]_i_1_n_0\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_2__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[4]_i_1_n_0\ : STD_LOGIC;
signal \axlen_cnt[5]_i_1_n_0\ : STD_LOGIC;
signal \axlen_cnt[6]_i_1_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_2_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_3_n_0\ : STD_LOGIC;
signal \^axlen_cnt_reg[0]_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[4]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[5]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[6]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[7]\ : STD_LOGIC;
signal next_pending_r_i_5_n_0 : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \NLW_axaddr_incr_reg[11]_i_4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_incr[0]_i_1\ : label is "soft_lutpair120";
attribute SOFT_HLUTNM of \axaddr_incr[10]_i_1\ : label is "soft_lutpair122";
attribute SOFT_HLUTNM of \axaddr_incr[11]_i_2\ : label is "soft_lutpair121";
attribute SOFT_HLUTNM of \axaddr_incr[1]_i_1\ : label is "soft_lutpair125";
attribute SOFT_HLUTNM of \axaddr_incr[2]_i_1\ : label is "soft_lutpair125";
attribute SOFT_HLUTNM of \axaddr_incr[3]_i_1\ : label is "soft_lutpair121";
attribute SOFT_HLUTNM of \axaddr_incr[4]_i_1\ : label is "soft_lutpair122";
attribute SOFT_HLUTNM of \axaddr_incr[5]_i_1\ : label is "soft_lutpair124";
attribute SOFT_HLUTNM of \axaddr_incr[6]_i_1\ : label is "soft_lutpair124";
attribute SOFT_HLUTNM of \axaddr_incr[7]_i_1\ : label is "soft_lutpair123";
attribute SOFT_HLUTNM of \axaddr_incr[8]_i_1\ : label is "soft_lutpair123";
attribute SOFT_HLUTNM of \axaddr_incr[9]_i_1\ : label is "soft_lutpair120";
attribute SOFT_HLUTNM of \axlen_cnt[4]_i_1\ : label is "soft_lutpair117";
attribute SOFT_HLUTNM of \axlen_cnt[6]_i_1\ : label is "soft_lutpair119";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_2\ : label is "soft_lutpair119";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_3\ : label is "soft_lutpair117";
attribute SOFT_HLUTNM of \m_axi_awaddr[11]_INST_0_i_1\ : label is "soft_lutpair118";
attribute SOFT_HLUTNM of \m_axi_awaddr[3]_INST_0_i_1\ : label is "soft_lutpair118";
begin
\axaddr_incr_reg[0]_0\ <= \^axaddr_incr_reg[0]_0\;
\axaddr_incr_reg[11]_0\(9 downto 0) <= \^axaddr_incr_reg[11]_0\(9 downto 0);
\axlen_cnt_reg[0]_0\ <= \^axlen_cnt_reg[0]_0\;
\axaddr_incr[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axaddr_incr(0),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[3]_i_3_n_7\,
O => p_1_in(0)
);
\axaddr_incr[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axaddr_incr(10),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[11]_i_4_n_5\,
O => p_1_in(10)
);
\axaddr_incr[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^axaddr_incr_reg[0]_0\,
I1 => \state_reg[1]_rep\,
O => \axaddr_incr[11]_i_1_n_0\
);
\axaddr_incr[11]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axaddr_incr(11),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[11]_i_4_n_4\,
O => p_1_in(11)
);
\axaddr_incr[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axaddr_incr(1),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[3]_i_3_n_6\,
O => p_1_in(1)
);
\axaddr_incr[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axaddr_incr(2),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[3]_i_3_n_5\,
O => p_1_in(2)
);
\axaddr_incr[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axaddr_incr(3),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[3]_i_3_n_4\,
O => p_1_in(3)
);
\axaddr_incr[3]_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"0009"
)
port map (
I0 => \m_payload_i_reg[46]\(0),
I1 => \state_reg[1]_rep\,
I2 => \m_payload_i_reg[46]\(4),
I3 => \m_payload_i_reg[46]\(5),
O => S(0)
);
\axaddr_incr[3]_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \axaddr_incr_reg_n_0_[3]\,
I1 => \m_payload_i_reg[46]\(5),
I2 => \m_payload_i_reg[46]\(4),
O => \axaddr_incr[3]_i_11_n_0\
);
\axaddr_incr[3]_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \axaddr_incr_reg_n_0_[2]\,
I1 => \m_payload_i_reg[46]\(4),
I2 => \m_payload_i_reg[46]\(5),
O => \axaddr_incr[3]_i_12_n_0\
);
\axaddr_incr[3]_i_13\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \^axaddr_incr_reg[11]_0\(1),
I1 => \m_payload_i_reg[46]\(5),
I2 => \m_payload_i_reg[46]\(4),
O => \axaddr_incr[3]_i_13_n_0\
);
\axaddr_incr[3]_i_14\: unisim.vcomponents.LUT3
generic map(
INIT => X"A9"
)
port map (
I0 => \^axaddr_incr_reg[11]_0\(0),
I1 => \m_payload_i_reg[46]\(5),
I2 => \m_payload_i_reg[46]\(4),
O => \axaddr_incr[3]_i_14_n_0\
);
\axaddr_incr[3]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"9AAA"
)
port map (
I0 => \m_payload_i_reg[46]\(3),
I1 => \state_reg[1]_rep\,
I2 => \m_payload_i_reg[46]\(4),
I3 => \m_payload_i_reg[46]\(5),
O => S(3)
);
\axaddr_incr[3]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A9A"
)
port map (
I0 => \m_payload_i_reg[46]\(2),
I1 => \state_reg[1]_rep\,
I2 => \m_payload_i_reg[46]\(5),
I3 => \m_payload_i_reg[46]\(4),
O => S(2)
);
\axaddr_incr[3]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"009A"
)
port map (
I0 => \m_payload_i_reg[46]\(1),
I1 => \state_reg[1]_rep\,
I2 => \m_payload_i_reg[46]\(4),
I3 => \m_payload_i_reg[46]\(5),
O => S(1)
);
\axaddr_incr[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axaddr_incr(4),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[7]_i_3_n_7\,
O => p_1_in(4)
);
\axaddr_incr[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axaddr_incr(5),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[7]_i_3_n_6\,
O => p_1_in(5)
);
\axaddr_incr[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axaddr_incr(6),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[7]_i_3_n_5\,
O => p_1_in(6)
);
\axaddr_incr[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axaddr_incr(7),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[7]_i_3_n_4\,
O => p_1_in(7)
);
\axaddr_incr[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axaddr_incr(8),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[11]_i_4_n_7\,
O => p_1_in(8)
);
\axaddr_incr[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axaddr_incr(9),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[11]_i_4_n_6\,
O => p_1_in(9)
);
\axaddr_incr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[11]_i_1_n_0\,
D => p_1_in(0),
Q => \^axaddr_incr_reg[11]_0\(0),
R => '0'
);
\axaddr_incr_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[11]_i_1_n_0\,
D => p_1_in(10),
Q => \^axaddr_incr_reg[11]_0\(8),
R => '0'
);
\axaddr_incr_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[11]_i_1_n_0\,
D => p_1_in(11),
Q => \^axaddr_incr_reg[11]_0\(9),
R => '0'
);
\axaddr_incr_reg[11]_i_4\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[7]_i_3_n_0\,
CO(3) => \NLW_axaddr_incr_reg[11]_i_4_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[11]_i_4_n_1\,
CO(1) => \axaddr_incr_reg[11]_i_4_n_2\,
CO(0) => \axaddr_incr_reg[11]_i_4_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[11]_i_4_n_4\,
O(2) => \axaddr_incr_reg[11]_i_4_n_5\,
O(1) => \axaddr_incr_reg[11]_i_4_n_6\,
O(0) => \axaddr_incr_reg[11]_i_4_n_7\,
S(3 downto 0) => \^axaddr_incr_reg[11]_0\(9 downto 6)
);
\axaddr_incr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[11]_i_1_n_0\,
D => p_1_in(1),
Q => \^axaddr_incr_reg[11]_0\(1),
R => '0'
);
\axaddr_incr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[11]_i_1_n_0\,
D => p_1_in(2),
Q => \axaddr_incr_reg_n_0_[2]\,
R => '0'
);
\axaddr_incr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[11]_i_1_n_0\,
D => p_1_in(3),
Q => \axaddr_incr_reg_n_0_[3]\,
R => '0'
);
\axaddr_incr_reg[3]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[3]_i_3_n_0\,
CO(2) => \axaddr_incr_reg[3]_i_3_n_1\,
CO(1) => \axaddr_incr_reg[3]_i_3_n_2\,
CO(0) => \axaddr_incr_reg[3]_i_3_n_3\,
CYINIT => '0',
DI(3) => \axaddr_incr_reg_n_0_[3]\,
DI(2) => \axaddr_incr_reg_n_0_[2]\,
DI(1 downto 0) => \^axaddr_incr_reg[11]_0\(1 downto 0),
O(3) => \axaddr_incr_reg[3]_i_3_n_4\,
O(2) => \axaddr_incr_reg[3]_i_3_n_5\,
O(1) => \axaddr_incr_reg[3]_i_3_n_6\,
O(0) => \axaddr_incr_reg[3]_i_3_n_7\,
S(3) => \axaddr_incr[3]_i_11_n_0\,
S(2) => \axaddr_incr[3]_i_12_n_0\,
S(1) => \axaddr_incr[3]_i_13_n_0\,
S(0) => \axaddr_incr[3]_i_14_n_0\
);
\axaddr_incr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[11]_i_1_n_0\,
D => p_1_in(4),
Q => \^axaddr_incr_reg[11]_0\(2),
R => '0'
);
\axaddr_incr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[11]_i_1_n_0\,
D => p_1_in(5),
Q => \^axaddr_incr_reg[11]_0\(3),
R => '0'
);
\axaddr_incr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[11]_i_1_n_0\,
D => p_1_in(6),
Q => \^axaddr_incr_reg[11]_0\(4),
R => '0'
);
\axaddr_incr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[11]_i_1_n_0\,
D => p_1_in(7),
Q => \^axaddr_incr_reg[11]_0\(5),
R => '0'
);
\axaddr_incr_reg[7]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[3]_i_3_n_0\,
CO(3) => \axaddr_incr_reg[7]_i_3_n_0\,
CO(2) => \axaddr_incr_reg[7]_i_3_n_1\,
CO(1) => \axaddr_incr_reg[7]_i_3_n_2\,
CO(0) => \axaddr_incr_reg[7]_i_3_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[7]_i_3_n_4\,
O(2) => \axaddr_incr_reg[7]_i_3_n_5\,
O(1) => \axaddr_incr_reg[7]_i_3_n_6\,
O(0) => \axaddr_incr_reg[7]_i_3_n_7\,
S(3 downto 0) => \^axaddr_incr_reg[11]_0\(5 downto 2)
);
\axaddr_incr_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[11]_i_1_n_0\,
D => p_1_in(8),
Q => \^axaddr_incr_reg[11]_0\(6),
R => '0'
);
\axaddr_incr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[11]_i_1_n_0\,
D => p_1_in(9),
Q => \^axaddr_incr_reg[11]_0\(7),
R => '0'
);
\axlen_cnt[0]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"44444F4444444444"
)
port map (
I0 => \axlen_cnt_reg_n_0_[0]\,
I1 => \^axlen_cnt_reg[0]_0\,
I2 => Q(1),
I3 => si_rs_awvalid,
I4 => Q(0),
I5 => \m_payload_i_reg[46]\(7),
O => \axlen_cnt[0]_i_1__1_n_0\
);
\axlen_cnt[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[46]\(8),
I2 => \axlen_cnt_reg_n_0_[0]\,
I3 => \axlen_cnt_reg_n_0_[1]\,
I4 => \^axlen_cnt_reg[0]_0\,
O => \axlen_cnt[1]_i_1_n_0\
);
\axlen_cnt[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F8F8F88F88888888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[46]\(9),
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \axlen_cnt_reg_n_0_[1]\,
I4 => \axlen_cnt_reg_n_0_[0]\,
I5 => \^axlen_cnt_reg[0]_0\,
O => \axlen_cnt[2]_i_1_n_0\
);
\axlen_cnt[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA90000FFFFFFFF"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[0]\,
I3 => \axlen_cnt_reg_n_0_[1]\,
I4 => \^axlen_cnt_reg[0]_0\,
I5 => \m_payload_i_reg[47]\,
O => \axlen_cnt[3]_i_2__0_n_0\
);
\axlen_cnt[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => \axlen_cnt_reg_n_0_[4]\,
I1 => \axlen_cnt_reg_n_0_[3]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => \axlen_cnt_reg_n_0_[2]\,
O => \axlen_cnt[4]_i_1_n_0\
);
\axlen_cnt[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAAAA9"
)
port map (
I0 => \axlen_cnt_reg_n_0_[5]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \axlen_cnt_reg_n_0_[1]\,
I4 => \axlen_cnt_reg_n_0_[4]\,
I5 => \axlen_cnt_reg_n_0_[3]\,
O => \axlen_cnt[5]_i_1_n_0\
);
\axlen_cnt[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \axlen_cnt_reg_n_0_[6]\,
I1 => \axlen_cnt_reg_n_0_[5]\,
I2 => \axlen_cnt[7]_i_3_n_0\,
O => \axlen_cnt[6]_i_1_n_0\
);
\axlen_cnt[7]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"A9AA"
)
port map (
I0 => \axlen_cnt_reg_n_0_[7]\,
I1 => \axlen_cnt_reg_n_0_[5]\,
I2 => \axlen_cnt_reg_n_0_[6]\,
I3 => \axlen_cnt[7]_i_3_n_0\,
O => \axlen_cnt[7]_i_2_n_0\
);
\axlen_cnt[7]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[4]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => \axlen_cnt_reg_n_0_[0]\,
O => \axlen_cnt[7]_i_3_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[0]_i_1__1_n_0\,
Q => \axlen_cnt_reg_n_0_[0]\,
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[1]_i_1_n_0\,
Q => \axlen_cnt_reg_n_0_[1]\,
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[2]_i_1_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[3]_i_2__0_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\axlen_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[4]_i_1_n_0\,
Q => \axlen_cnt_reg_n_0_[4]\,
R => \state_reg[0]_rep\
);
\axlen_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[5]_i_1_n_0\,
Q => \axlen_cnt_reg_n_0_[5]\,
R => \state_reg[0]_rep\
);
\axlen_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[6]_i_1_n_0\,
Q => \axlen_cnt_reg_n_0_[6]\,
R => \state_reg[0]_rep\
);
\axlen_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[7]_i_2_n_0\,
Q => \axlen_cnt_reg_n_0_[7]\,
R => \state_reg[0]_rep\
);
\m_axi_awaddr[11]_INST_0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^axaddr_incr_reg[0]_0\,
I1 => \m_payload_i_reg[46]\(6),
O => \m_axi_awaddr[11]\
);
\m_axi_awaddr[2]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EF40"
)
port map (
I0 => \^axaddr_incr_reg[0]_0\,
I1 => \axaddr_incr_reg_n_0_[2]\,
I2 => \m_payload_i_reg[46]\(6),
I3 => \m_payload_i_reg[46]\(2),
O => \m_axi_awaddr[2]\
);
\m_axi_awaddr[3]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EF40"
)
port map (
I0 => \^axaddr_incr_reg[0]_0\,
I1 => \axaddr_incr_reg_n_0_[3]\,
I2 => \m_payload_i_reg[46]\(6),
I3 => \m_payload_i_reg[46]\(3),
O => \m_axi_awaddr[3]\
);
\next_pending_r_i_4__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"55545555"
)
port map (
I0 => E(0),
I1 => \axlen_cnt_reg_n_0_[6]\,
I2 => \axlen_cnt_reg_n_0_[5]\,
I3 => \axlen_cnt_reg_n_0_[7]\,
I4 => next_pending_r_i_5_n_0,
O => \^axlen_cnt_reg[0]_0\
);
next_pending_r_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \axlen_cnt_reg_n_0_[2]\,
I1 => \axlen_cnt_reg_n_0_[1]\,
I2 => \axlen_cnt_reg_n_0_[4]\,
I3 => \axlen_cnt_reg_n_0_[3]\,
O => next_pending_r_i_5_n_0
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => incr_next_pending,
Q => next_pending_r_reg_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_0,
Q => \^axaddr_incr_reg[0]_0\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_incr_cmd_2 is
port (
incr_next_pending : out STD_LOGIC;
\axaddr_incr_reg[0]_0\ : out STD_LOGIC;
\axlen_cnt_reg[0]_0\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 11 downto 0 );
\m_axi_araddr[11]\ : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
sel_first_reg_0 : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[46]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\state_reg[1]_rep\ : in STD_LOGIC;
\m_payload_i_reg[44]\ : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
si_rs_arvalid : in STD_LOGIC;
\state_reg[0]_rep\ : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]\ : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arready : in STD_LOGIC;
\state_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_incr_cmd_2 : entity is "axi_protocol_converter_v2_1_14_b2s_incr_cmd";
end led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_incr_cmd_2;
architecture STRUCTURE of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_incr_cmd_2 is
signal \^q\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \axaddr_incr[0]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[10]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[11]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[1]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[2]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_11_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_12_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_13_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_14_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[5]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[6]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[7]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[9]_i_1__0_n_0\ : STD_LOGIC;
signal \^axaddr_incr_reg[0]_0\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_4__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_4__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_4__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_4__0_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_4__0_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_4__0_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_4__0_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3__0_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3__0_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3__0_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3__0_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3__0_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3__0_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3__0_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3__0_n_7\ : STD_LOGIC;
signal \axlen_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \axlen_cnt[1]_i_1__1_n_0\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1__1_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_2__1_n_0\ : STD_LOGIC;
signal \axlen_cnt[4]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[5]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[6]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_2__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_3__0_n_0\ : STD_LOGIC;
signal \^axlen_cnt_reg[0]_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[4]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[5]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[6]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[7]\ : STD_LOGIC;
signal \^incr_next_pending\ : STD_LOGIC;
signal \next_pending_r_i_2__1_n_0\ : STD_LOGIC;
signal next_pending_r_i_4_n_0 : STD_LOGIC;
signal next_pending_r_reg_n_0 : STD_LOGIC;
signal \NLW_axaddr_incr_reg[11]_i_4__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_incr[0]_i_1__0\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \axaddr_incr[10]_i_1__0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \axaddr_incr[11]_i_2__0\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \axaddr_incr[1]_i_1__0\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \axaddr_incr[2]_i_1__0\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \axaddr_incr[3]_i_1__0\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \axaddr_incr[4]_i_1__0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \axaddr_incr[5]_i_1__0\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \axaddr_incr[6]_i_1__0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \axaddr_incr[7]_i_1__0\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \axaddr_incr[8]_i_1__0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \axaddr_incr[9]_i_1__0\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \axlen_cnt[3]_i_3__0\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \axlen_cnt[4]_i_1__2\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \axlen_cnt[6]_i_1__0\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_2__0\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_3__0\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \next_pending_r_i_2__1\ : label is "soft_lutpair6";
begin
Q(11 downto 0) <= \^q\(11 downto 0);
\axaddr_incr_reg[0]_0\ <= \^axaddr_incr_reg[0]_0\;
\axlen_cnt_reg[0]_0\ <= \^axlen_cnt_reg[0]_0\;
incr_next_pending <= \^incr_next_pending\;
\axaddr_incr[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(0),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[3]_i_3__0_n_7\,
O => \axaddr_incr[0]_i_1__0_n_0\
);
\axaddr_incr[10]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => O(2),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[11]_i_4__0_n_5\,
O => \axaddr_incr[10]_i_1__0_n_0\
);
\axaddr_incr[11]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => O(3),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[11]_i_4__0_n_4\,
O => \axaddr_incr[11]_i_2__0_n_0\
);
\axaddr_incr[1]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(1),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[3]_i_3__0_n_6\,
O => \axaddr_incr[1]_i_1__0_n_0\
);
\axaddr_incr[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(2),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[3]_i_3__0_n_5\,
O => \axaddr_incr[2]_i_1__0_n_0\
);
\axaddr_incr[3]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"0202010202020202"
)
port map (
I0 => \m_payload_i_reg[46]\(0),
I1 => \m_payload_i_reg[46]\(4),
I2 => \m_payload_i_reg[46]\(5),
I3 => m_axi_arready,
I4 => \state_reg[1]_0\(1),
I5 => \state_reg[1]_0\(0),
O => S(0)
);
\axaddr_incr[3]_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \^q\(3),
I1 => \m_payload_i_reg[46]\(5),
I2 => \m_payload_i_reg[46]\(4),
O => \axaddr_incr[3]_i_11_n_0\
);
\axaddr_incr[3]_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \^q\(2),
I1 => \m_payload_i_reg[46]\(4),
I2 => \m_payload_i_reg[46]\(5),
O => \axaddr_incr[3]_i_12_n_0\
);
\axaddr_incr[3]_i_13\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \^q\(1),
I1 => \m_payload_i_reg[46]\(5),
I2 => \m_payload_i_reg[46]\(4),
O => \axaddr_incr[3]_i_13_n_0\
);
\axaddr_incr[3]_i_14\: unisim.vcomponents.LUT3
generic map(
INIT => X"A9"
)
port map (
I0 => \^q\(0),
I1 => \m_payload_i_reg[46]\(5),
I2 => \m_payload_i_reg[46]\(4),
O => \axaddr_incr[3]_i_14_n_0\
);
\axaddr_incr[3]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(3),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[3]_i_3__0_n_4\,
O => \axaddr_incr[3]_i_1__0_n_0\
);
\axaddr_incr[3]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA6AAAAAAAAAAA"
)
port map (
I0 => \m_payload_i_reg[46]\(3),
I1 => \m_payload_i_reg[46]\(4),
I2 => \m_payload_i_reg[46]\(5),
I3 => m_axi_arready,
I4 => \state_reg[1]_0\(1),
I5 => \state_reg[1]_0\(0),
O => S(3)
);
\axaddr_incr[3]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A2A262A2A2A2A2A"
)
port map (
I0 => \m_payload_i_reg[46]\(2),
I1 => \m_payload_i_reg[46]\(5),
I2 => \m_payload_i_reg[46]\(4),
I3 => m_axi_arready,
I4 => \state_reg[1]_0\(1),
I5 => \state_reg[1]_0\(0),
O => S(2)
);
\axaddr_incr[3]_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A0A060A0A0A0A0A"
)
port map (
I0 => \m_payload_i_reg[46]\(1),
I1 => \m_payload_i_reg[46]\(4),
I2 => \m_payload_i_reg[46]\(5),
I3 => m_axi_arready,
I4 => \state_reg[1]_0\(1),
I5 => \state_reg[1]_0\(0),
O => S(1)
);
\axaddr_incr[4]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[7]\(0),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[7]_i_3__0_n_7\,
O => \axaddr_incr[4]_i_1__0_n_0\
);
\axaddr_incr[5]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[7]\(1),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[7]_i_3__0_n_6\,
O => \axaddr_incr[5]_i_1__0_n_0\
);
\axaddr_incr[6]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[7]\(2),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[7]_i_3__0_n_5\,
O => \axaddr_incr[6]_i_1__0_n_0\
);
\axaddr_incr[7]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[7]\(3),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[7]_i_3__0_n_4\,
O => \axaddr_incr[7]_i_1__0_n_0\
);
\axaddr_incr[8]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => O(0),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[11]_i_4__0_n_7\,
O => \axaddr_incr[8]_i_1__0_n_0\
);
\axaddr_incr[9]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => O(1),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[11]_i_4__0_n_6\,
O => \axaddr_incr[9]_i_1__0_n_0\
);
\axaddr_incr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_1(0),
D => \axaddr_incr[0]_i_1__0_n_0\,
Q => \^q\(0),
R => '0'
);
\axaddr_incr_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_1(0),
D => \axaddr_incr[10]_i_1__0_n_0\,
Q => \^q\(10),
R => '0'
);
\axaddr_incr_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_1(0),
D => \axaddr_incr[11]_i_2__0_n_0\,
Q => \^q\(11),
R => '0'
);
\axaddr_incr_reg[11]_i_4__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[7]_i_3__0_n_0\,
CO(3) => \NLW_axaddr_incr_reg[11]_i_4__0_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[11]_i_4__0_n_1\,
CO(1) => \axaddr_incr_reg[11]_i_4__0_n_2\,
CO(0) => \axaddr_incr_reg[11]_i_4__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[11]_i_4__0_n_4\,
O(2) => \axaddr_incr_reg[11]_i_4__0_n_5\,
O(1) => \axaddr_incr_reg[11]_i_4__0_n_6\,
O(0) => \axaddr_incr_reg[11]_i_4__0_n_7\,
S(3 downto 0) => \^q\(11 downto 8)
);
\axaddr_incr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_1(0),
D => \axaddr_incr[1]_i_1__0_n_0\,
Q => \^q\(1),
R => '0'
);
\axaddr_incr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_1(0),
D => \axaddr_incr[2]_i_1__0_n_0\,
Q => \^q\(2),
R => '0'
);
\axaddr_incr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_1(0),
D => \axaddr_incr[3]_i_1__0_n_0\,
Q => \^q\(3),
R => '0'
);
\axaddr_incr_reg[3]_i_3__0\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[3]_i_3__0_n_0\,
CO(2) => \axaddr_incr_reg[3]_i_3__0_n_1\,
CO(1) => \axaddr_incr_reg[3]_i_3__0_n_2\,
CO(0) => \axaddr_incr_reg[3]_i_3__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^q\(3 downto 0),
O(3) => \axaddr_incr_reg[3]_i_3__0_n_4\,
O(2) => \axaddr_incr_reg[3]_i_3__0_n_5\,
O(1) => \axaddr_incr_reg[3]_i_3__0_n_6\,
O(0) => \axaddr_incr_reg[3]_i_3__0_n_7\,
S(3) => \axaddr_incr[3]_i_11_n_0\,
S(2) => \axaddr_incr[3]_i_12_n_0\,
S(1) => \axaddr_incr[3]_i_13_n_0\,
S(0) => \axaddr_incr[3]_i_14_n_0\
);
\axaddr_incr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_1(0),
D => \axaddr_incr[4]_i_1__0_n_0\,
Q => \^q\(4),
R => '0'
);
\axaddr_incr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_1(0),
D => \axaddr_incr[5]_i_1__0_n_0\,
Q => \^q\(5),
R => '0'
);
\axaddr_incr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_1(0),
D => \axaddr_incr[6]_i_1__0_n_0\,
Q => \^q\(6),
R => '0'
);
\axaddr_incr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_1(0),
D => \axaddr_incr[7]_i_1__0_n_0\,
Q => \^q\(7),
R => '0'
);
\axaddr_incr_reg[7]_i_3__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[3]_i_3__0_n_0\,
CO(3) => \axaddr_incr_reg[7]_i_3__0_n_0\,
CO(2) => \axaddr_incr_reg[7]_i_3__0_n_1\,
CO(1) => \axaddr_incr_reg[7]_i_3__0_n_2\,
CO(0) => \axaddr_incr_reg[7]_i_3__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[7]_i_3__0_n_4\,
O(2) => \axaddr_incr_reg[7]_i_3__0_n_5\,
O(1) => \axaddr_incr_reg[7]_i_3__0_n_6\,
O(0) => \axaddr_incr_reg[7]_i_3__0_n_7\,
S(3 downto 0) => \^q\(7 downto 4)
);
\axaddr_incr_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_1(0),
D => \axaddr_incr[8]_i_1__0_n_0\,
Q => \^q\(8),
R => '0'
);
\axaddr_incr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_1(0),
D => \axaddr_incr[9]_i_1__0_n_0\,
Q => \^q\(9),
R => '0'
);
\axlen_cnt[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20FF2020"
)
port map (
I0 => si_rs_arvalid,
I1 => \state_reg[0]_rep\,
I2 => \m_payload_i_reg[46]\(7),
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => \^axlen_cnt_reg[0]_0\,
O => \axlen_cnt[0]_i_1_n_0\
);
\axlen_cnt[1]_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[46]\(8),
I2 => \axlen_cnt_reg_n_0_[0]\,
I3 => \axlen_cnt_reg_n_0_[1]\,
I4 => \^axlen_cnt_reg[0]_0\,
O => \axlen_cnt[1]_i_1__1_n_0\
);
\axlen_cnt[2]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F8F8F88F88888888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[46]\(9),
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \axlen_cnt_reg_n_0_[1]\,
I4 => \axlen_cnt_reg_n_0_[0]\,
I5 => \^axlen_cnt_reg[0]_0\,
O => \axlen_cnt[2]_i_1__1_n_0\
);
\axlen_cnt[3]_i_2__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA90000FFFFFFFF"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[0]\,
I3 => \axlen_cnt_reg_n_0_[1]\,
I4 => \^axlen_cnt_reg[0]_0\,
I5 => \m_payload_i_reg[47]\,
O => \axlen_cnt[3]_i_2__1_n_0\
);
\axlen_cnt[3]_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"55545555"
)
port map (
I0 => E(0),
I1 => \axlen_cnt_reg_n_0_[6]\,
I2 => \axlen_cnt_reg_n_0_[5]\,
I3 => \axlen_cnt_reg_n_0_[7]\,
I4 => next_pending_r_i_4_n_0,
O => \^axlen_cnt_reg[0]_0\
);
\axlen_cnt[4]_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => \axlen_cnt_reg_n_0_[4]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => \axlen_cnt_reg_n_0_[3]\,
O => \axlen_cnt[4]_i_1__2_n_0\
);
\axlen_cnt[5]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAAAA9"
)
port map (
I0 => \axlen_cnt_reg_n_0_[5]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => \axlen_cnt_reg_n_0_[4]\,
I5 => \axlen_cnt_reg_n_0_[1]\,
O => \axlen_cnt[5]_i_1__0_n_0\
);
\axlen_cnt[6]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"A6"
)
port map (
I0 => \axlen_cnt_reg_n_0_[6]\,
I1 => \axlen_cnt[7]_i_3__0_n_0\,
I2 => \axlen_cnt_reg_n_0_[5]\,
O => \axlen_cnt[6]_i_1__0_n_0\
);
\axlen_cnt[7]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A9AA"
)
port map (
I0 => \axlen_cnt_reg_n_0_[7]\,
I1 => \axlen_cnt_reg_n_0_[5]\,
I2 => \axlen_cnt_reg_n_0_[6]\,
I3 => \axlen_cnt[7]_i_3__0_n_0\,
O => \axlen_cnt[7]_i_2__0_n_0\
);
\axlen_cnt[7]_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => \axlen_cnt_reg_n_0_[1]\,
I1 => \axlen_cnt_reg_n_0_[4]\,
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => \axlen_cnt_reg_n_0_[0]\,
O => \axlen_cnt[7]_i_3__0_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[0]_i_1_n_0\,
Q => \axlen_cnt_reg_n_0_[0]\,
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[1]_i_1__1_n_0\,
Q => \axlen_cnt_reg_n_0_[1]\,
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[2]_i_1__1_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_2__1_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\axlen_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[4]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[4]\,
R => \state_reg[1]\
);
\axlen_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[5]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[5]\,
R => \state_reg[1]\
);
\axlen_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[6]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[6]\,
R => \state_reg[1]\
);
\axlen_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[7]_i_2__0_n_0\,
Q => \axlen_cnt_reg_n_0_[7]\,
R => \state_reg[1]\
);
\m_axi_araddr[11]_INST_0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^axaddr_incr_reg[0]_0\,
I1 => \m_payload_i_reg[46]\(6),
O => \m_axi_araddr[11]\
);
\next_pending_r_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF505C"
)
port map (
I0 => \next_pending_r_i_2__1_n_0\,
I1 => next_pending_r_reg_n_0,
I2 => \state_reg[1]_rep\,
I3 => E(0),
I4 => \m_payload_i_reg[44]\,
O => \^incr_next_pending\
);
\next_pending_r_i_2__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => next_pending_r_i_4_n_0,
I1 => \axlen_cnt_reg_n_0_[7]\,
I2 => \axlen_cnt_reg_n_0_[5]\,
I3 => \axlen_cnt_reg_n_0_[6]\,
O => \next_pending_r_i_2__1_n_0\
);
next_pending_r_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[4]\,
I3 => \axlen_cnt_reg_n_0_[1]\,
O => next_pending_r_i_4_n_0
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \^incr_next_pending\,
Q => next_pending_r_reg_n_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_0,
Q => \^axaddr_incr_reg[0]_0\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_rd_cmd_fsm is
port (
\axlen_cnt_reg[7]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[0]\ : out STD_LOGIC;
\axaddr_offset_r_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axburst_eq0_reg : out STD_LOGIC;
wrap_next_pending : out STD_LOGIC;
sel_first_i : out STD_LOGIC;
s_axburst_eq1_reg : out STD_LOGIC;
r_push_r_reg : out STD_LOGIC;
\axlen_cnt_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
sel_first_reg : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC;
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
\axaddr_incr_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_valid_i0 : out STD_LOGIC;
\m_payload_i_reg[0]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arready : in STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
\axlen_cnt_reg[6]\ : in STD_LOGIC;
s_axburst_eq1_reg_0 : in STD_LOGIC;
\cnt_read_reg[1]_rep__0\ : in STD_LOGIC;
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\wrap_second_len_r_reg[2]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_payload_i_reg[35]\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_payload_i_reg[35]_0\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_payload_i_reg[44]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_payload_i_reg[3]\ : in STD_LOGIC;
incr_next_pending : in STD_LOGIC;
\m_payload_i_reg[44]_0\ : in STD_LOGIC;
\axlen_cnt_reg[3]\ : in STD_LOGIC;
next_pending_r_reg : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
sel_first : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_ready_i_reg : in STD_LOGIC;
aclk : in STD_LOGIC
);
end led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_rd_cmd_fsm;
architecture STRUCTURE of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_rd_cmd_fsm is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^axaddr_offset_r_reg[0]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^m_payload_i_reg[0]\ : STD_LOGIC;
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal next_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^r_push_r_reg\ : STD_LOGIC;
signal \^sel_first_i\ : STD_LOGIC;
signal \wrap_cnt_r[3]_i_2__0_n_0\ : STD_LOGIC;
signal \^wrap_cnt_r_reg[0]\ : STD_LOGIC;
signal \^wrap_next_pending\ : STD_LOGIC;
signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_incr[11]_i_1__0\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \axlen_cnt[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__0\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \m_valid_i_i_1__1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of r_push_r_i_1 : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \s_axburst_eq0_i_1__0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \s_axburst_eq1_i_1__0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \state[1]_i_1__0\ : label is "soft_lutpair1";
attribute KEEP : string;
attribute KEEP of \state_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \state_reg[0]\ : label is "state_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \state_reg[0]_rep\ : label is 1;
attribute KEEP of \state_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[0]_rep\ : label is "state_reg[0]";
attribute KEEP of \state_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]\ : label is "state_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \state_reg[1]_rep\ : label is 1;
attribute KEEP of \state_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]_rep\ : label is "state_reg[1]";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[11]_i_1\ : label is "soft_lutpair2";
begin
E(0) <= \^e\(0);
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_offset_r_reg[0]\(0) <= \^axaddr_offset_r_reg[0]\(0);
\m_payload_i_reg[0]\ <= \^m_payload_i_reg[0]\;
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
r_push_r_reg <= \^r_push_r_reg\;
sel_first_i <= \^sel_first_i\;
\wrap_cnt_r_reg[0]\ <= \^wrap_cnt_r_reg[0]\;
wrap_next_pending <= \^wrap_next_pending\;
\wrap_second_len_r_reg[3]\(1 downto 0) <= \^wrap_second_len_r_reg[3]\(1 downto 0);
\axaddr_incr[11]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"AEAA"
)
port map (
I0 => sel_first,
I1 => \^m_payload_i_reg[0]_0\,
I2 => \^m_payload_i_reg[0]\,
I3 => m_axi_arready,
O => \axaddr_incr_reg[0]\(0)
);
\axaddr_offset_r[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAACAAAAAAA0AA"
)
port map (
I0 => \axaddr_offset_r_reg[3]\(0),
I1 => \m_payload_i_reg[44]\(1),
I2 => \^q\(0),
I3 => si_rs_arvalid,
I4 => \^q\(1),
I5 => \m_payload_i_reg[3]\,
O => \^axaddr_offset_r_reg[0]\(0)
);
\axlen_cnt[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0E02"
)
port map (
I0 => si_rs_arvalid,
I1 => \^q\(0),
I2 => \^q\(1),
I3 => m_axi_arready,
O => \axlen_cnt_reg[4]\(0)
);
\axlen_cnt[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002320"
)
port map (
I0 => m_axi_arready,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => si_rs_arvalid,
I4 => \axlen_cnt_reg[6]\,
O => \axlen_cnt_reg[7]\
);
m_axi_arvalid_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => \^m_payload_i_reg[0]\,
O => m_axi_arvalid
);
\m_payload_i[31]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"8F"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => \^m_payload_i_reg[0]_0\,
I2 => si_rs_arvalid,
O => \m_payload_i_reg[0]_1\(0)
);
\m_valid_i_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF70FFFF"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => \^m_payload_i_reg[0]_0\,
I2 => si_rs_arvalid,
I3 => s_axi_arvalid,
I4 => s_ready_i_reg,
O => m_valid_i0
);
\next_pending_r_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFABEEAA"
)
port map (
I0 => \m_payload_i_reg[44]_0\,
I1 => \^r_push_r_reg\,
I2 => \^e\(0),
I3 => \axlen_cnt_reg[3]\,
I4 => next_pending_r_reg,
O => \^wrap_next_pending\
);
r_push_r_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"20"
)
port map (
I0 => m_axi_arready,
I1 => \^m_payload_i_reg[0]\,
I2 => \^m_payload_i_reg[0]_0\,
O => \^r_push_r_reg\
);
\s_axburst_eq0_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => \^wrap_next_pending\,
I1 => \m_payload_i_reg[44]\(0),
I2 => \^sel_first_i\,
I3 => incr_next_pending,
O => s_axburst_eq0_reg
);
\s_axburst_eq1_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"ABA8"
)
port map (
I0 => \^wrap_next_pending\,
I1 => \m_payload_i_reg[44]\(0),
I2 => \^sel_first_i\,
I3 => incr_next_pending,
O => s_axburst_eq1_reg
);
\sel_first_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFC4C4CFCC"
)
port map (
I0 => m_axi_arready,
I1 => sel_first_reg_1,
I2 => \^q\(1),
I3 => si_rs_arvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg
);
\sel_first_i_1__3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFC4C4CFCC"
)
port map (
I0 => m_axi_arready,
I1 => sel_first,
I2 => \^q\(1),
I3 => si_rs_arvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg_0
);
\sel_first_i_1__4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFC4C4CFCC"
)
port map (
I0 => m_axi_arready,
I1 => sel_first_reg_2,
I2 => \^m_payload_i_reg[0]\,
I3 => si_rs_arvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => \^sel_first_i\
);
\state[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000770000FFFFF0"
)
port map (
I0 => s_axburst_eq1_reg_0,
I1 => m_axi_arready,
I2 => si_rs_arvalid,
I3 => \^q\(0),
I4 => \^q\(1),
I5 => \cnt_read_reg[1]_rep__0\,
O => next_state(0)
);
\state[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0FC00040"
)
port map (
I0 => s_axburst_eq1_reg_0,
I1 => m_axi_arready,
I2 => \^m_payload_i_reg[0]_0\,
I3 => \^m_payload_i_reg[0]\,
I4 => \cnt_read_reg[1]_rep__0\,
O => next_state(1)
);
\state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^q\(0),
R => areset_d1
);
\state_reg[0]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^m_payload_i_reg[0]_0\,
R => areset_d1
);
\state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(1),
Q => \^q\(1),
R => areset_d1
);
\state_reg[1]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(1),
Q => \^m_payload_i_reg[0]\,
R => areset_d1
);
\wrap_boundary_axaddr_r[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => si_rs_arvalid,
I2 => \^m_payload_i_reg[0]_0\,
O => \^e\(0)
);
\wrap_cnt_r[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA8A5575AA8A5545"
)
port map (
I0 => \wrap_second_len_r_reg[3]_0\(0),
I1 => \^q\(0),
I2 => si_rs_arvalid,
I3 => \^q\(1),
I4 => \^wrap_cnt_r_reg[0]\,
I5 => \^axaddr_offset_r_reg[0]\(0),
O => D(0)
);
\wrap_cnt_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA6AA56AAAAAAAA"
)
port map (
I0 => \wrap_second_len_r_reg[2]\(1),
I1 => \wrap_second_len_r_reg[3]_0\(0),
I2 => \^e\(0),
I3 => \^wrap_cnt_r_reg[0]\,
I4 => \^axaddr_offset_r_reg[0]\(0),
I5 => \wrap_second_len_r_reg[2]\(0),
O => D(1)
);
\wrap_cnt_r[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A6AA"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(1),
I1 => \wrap_second_len_r_reg[2]\(0),
I2 => \wrap_cnt_r[3]_i_2__0_n_0\,
I3 => \wrap_second_len_r_reg[2]\(1),
O => D(2)
);
\wrap_cnt_r[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"D1D1D1D1D1D1DFD1"
)
port map (
I0 => \wrap_second_len_r_reg[3]_0\(0),
I1 => \^e\(0),
I2 => \^axaddr_offset_r_reg[0]\(0),
I3 => \m_payload_i_reg[35]\,
I4 => \m_payload_i_reg[47]\(1),
I5 => \m_payload_i_reg[47]\(0),
O => \wrap_cnt_r[3]_i_2__0_n_0\
);
\wrap_second_len_r[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA8AAA8AAA8AAABA"
)
port map (
I0 => \wrap_second_len_r_reg[3]_0\(0),
I1 => \^q\(0),
I2 => si_rs_arvalid,
I3 => \^q\(1),
I4 => \^wrap_cnt_r_reg[0]\,
I5 => \^axaddr_offset_r_reg[0]\(0),
O => \^wrap_second_len_r_reg[3]\(0)
);
\wrap_second_len_r[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000004000404"
)
port map (
I0 => \^axaddr_offset_r_reg[0]\(0),
I1 => \m_payload_i_reg[35]\,
I2 => \m_payload_i_reg[35]_0\,
I3 => \^e\(0),
I4 => \axaddr_offset_r_reg[3]\(1),
I5 => \m_payload_i_reg[47]\(0),
O => \^wrap_cnt_r_reg[0]\
);
\wrap_second_len_r[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FB00FFFFFB00FB00"
)
port map (
I0 => \^axaddr_offset_r_reg[0]\(0),
I1 => \m_payload_i_reg[35]\,
I2 => \m_payload_i_reg[47]\(0),
I3 => \m_payload_i_reg[35]_0\,
I4 => \^e\(0),
I5 => \wrap_second_len_r_reg[3]_0\(1),
O => \^wrap_second_len_r_reg[3]\(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_simple_fifo is
port (
\cnt_read_reg[0]_rep__0_0\ : out STD_LOGIC;
\cnt_read_reg[1]_rep__0_0\ : out STD_LOGIC;
\state_reg[0]_rep\ : out STD_LOGIC;
bvalid_i_reg : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
bresp_push : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
b_push : in STD_LOGIC;
shandshake_r : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
si_rs_bvalid : in STD_LOGIC;
si_rs_bready : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
\bresp_cnt_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
mhandshake_r : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
aclk : in STD_LOGIC
);
end led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_simple_fifo;
architecture STRUCTURE of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_simple_fifo is
signal \bresp_cnt[7]_i_3_n_0\ : STD_LOGIC;
signal \bresp_cnt[7]_i_4_n_0\ : STD_LOGIC;
signal \bresp_cnt[7]_i_5_n_0\ : STD_LOGIC;
signal \bresp_cnt[7]_i_6_n_0\ : STD_LOGIC;
signal \^bresp_push\ : STD_LOGIC;
signal bvalid_i_i_2_n_0 : STD_LOGIC;
signal cnt_read : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \cnt_read[0]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[1]_i_1_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[0]_rep__0_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[1]_rep__0_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_2__0_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_3_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][1]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][2]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][3]_srl4_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \bresp_cnt[7]_i_5\ : label is "soft_lutpair127";
attribute SOFT_HLUTNM of \cnt_read[0]_i_1__0\ : label is "soft_lutpair128";
attribute SOFT_HLUTNM of \cnt_read[1]_i_1\ : label is "soft_lutpair128";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][0]_srl4 ";
attribute SOFT_HLUTNM of \memory_reg[3][0]_srl4_i_3\ : label is "soft_lutpair127";
attribute srl_bus_name of \memory_reg[3][10]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][10]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][10]_srl4 ";
attribute srl_bus_name of \memory_reg[3][11]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][11]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][11]_srl4 ";
attribute srl_bus_name of \memory_reg[3][12]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][12]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][12]_srl4 ";
attribute srl_bus_name of \memory_reg[3][13]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][13]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][13]_srl4 ";
attribute srl_bus_name of \memory_reg[3][14]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][14]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][14]_srl4 ";
attribute srl_bus_name of \memory_reg[3][15]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][15]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][15]_srl4 ";
attribute srl_bus_name of \memory_reg[3][16]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][16]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][16]_srl4 ";
attribute srl_bus_name of \memory_reg[3][17]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][17]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][17]_srl4 ";
attribute srl_bus_name of \memory_reg[3][18]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][18]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][18]_srl4 ";
attribute srl_bus_name of \memory_reg[3][19]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][19]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][19]_srl4 ";
attribute srl_bus_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][1]_srl4 ";
attribute srl_bus_name of \memory_reg[3][2]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][2]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][2]_srl4 ";
attribute srl_bus_name of \memory_reg[3][3]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][3]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][3]_srl4 ";
attribute srl_bus_name of \memory_reg[3][8]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][8]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][8]_srl4 ";
attribute srl_bus_name of \memory_reg[3][9]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][9]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][9]_srl4 ";
begin
bresp_push <= \^bresp_push\;
\cnt_read_reg[0]_rep__0_0\ <= \^cnt_read_reg[0]_rep__0_0\;
\cnt_read_reg[1]_rep__0_0\ <= \^cnt_read_reg[1]_rep__0_0\;
\bresp_cnt[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAABAAAA"
)
port map (
I0 => areset_d1,
I1 => \bresp_cnt[7]_i_3_n_0\,
I2 => \bresp_cnt[7]_i_4_n_0\,
I3 => \bresp_cnt[7]_i_5_n_0\,
I4 => \bresp_cnt[7]_i_6_n_0\,
O => SR(0)
);
\bresp_cnt[7]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"22F2FFFF22F222F2"
)
port map (
I0 => \memory_reg[3][1]_srl4_n_0\,
I1 => \bresp_cnt_reg[7]\(1),
I2 => \bresp_cnt_reg[7]\(3),
I3 => \memory_reg[3][3]_srl4_n_0\,
I4 => \bresp_cnt_reg[7]\(0),
I5 => \memory_reg[3][0]_srl4_n_0\,
O => \bresp_cnt[7]_i_3_n_0\
);
\bresp_cnt[7]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAEFFAE"
)
port map (
I0 => \bresp_cnt_reg[7]\(4),
I1 => \bresp_cnt_reg[7]\(1),
I2 => \memory_reg[3][1]_srl4_n_0\,
I3 => \bresp_cnt_reg[7]\(0),
I4 => \memory_reg[3][0]_srl4_n_0\,
O => \bresp_cnt[7]_i_4_n_0\
);
\bresp_cnt[7]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"EAFFEAEA"
)
port map (
I0 => \bresp_cnt_reg[7]\(6),
I1 => \^cnt_read_reg[0]_rep__0_0\,
I2 => \^cnt_read_reg[1]_rep__0_0\,
I3 => \bresp_cnt_reg[7]\(3),
I4 => \memory_reg[3][3]_srl4_n_0\,
O => \bresp_cnt[7]_i_5_n_0\
);
\bresp_cnt[7]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"00004004"
)
port map (
I0 => \bresp_cnt_reg[7]\(5),
I1 => mhandshake_r,
I2 => \bresp_cnt_reg[7]\(2),
I3 => \memory_reg[3][2]_srl4_n_0\,
I4 => \bresp_cnt_reg[7]\(7),
O => \bresp_cnt[7]_i_6_n_0\
);
bvalid_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"0444"
)
port map (
I0 => areset_d1,
I1 => bvalid_i_i_2_n_0,
I2 => si_rs_bvalid,
I3 => si_rs_bready,
O => bvalid_i_reg
);
bvalid_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00070707"
)
port map (
I0 => \^cnt_read_reg[0]_rep__0_0\,
I1 => \^cnt_read_reg[1]_rep__0_0\,
I2 => shandshake_r,
I3 => Q(0),
I4 => Q(1),
I5 => si_rs_bvalid,
O => bvalid_i_i_2_n_0
);
\cnt_read[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^bresp_push\,
I1 => Q(0),
I2 => shandshake_r,
O => D(0)
);
\cnt_read[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^cnt_read_reg[0]_rep__0_0\,
I1 => b_push,
I2 => shandshake_r,
O => \cnt_read[0]_i_1__0_n_0\
);
\cnt_read[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"E718"
)
port map (
I0 => \^cnt_read_reg[0]_rep__0_0\,
I1 => b_push,
I2 => shandshake_r,
I3 => \^cnt_read_reg[1]_rep__0_0\,
O => \cnt_read[1]_i_1_n_0\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => cnt_read(0),
S => areset_d1
);
\cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => \cnt_read_reg[0]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => \^cnt_read_reg[0]_rep__0_0\,
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => cnt_read(1),
S => areset_d1
);
\cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => \cnt_read_reg[1]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => \^cnt_read_reg[1]_rep__0_0\,
S => areset_d1
);
\memory_reg[3][0]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(0),
Q => \memory_reg[3][0]_srl4_n_0\
);
\memory_reg[3][0]_srl4_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000004100"
)
port map (
I0 => \bresp_cnt_reg[7]\(7),
I1 => \memory_reg[3][2]_srl4_n_0\,
I2 => \bresp_cnt_reg[7]\(2),
I3 => mhandshake_r,
I4 => \bresp_cnt_reg[7]\(5),
I5 => \memory_reg[3][0]_srl4_i_2__0_n_0\,
O => \^bresp_push\
);
\memory_reg[3][0]_srl4_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFEFFFFFFFEFFFE"
)
port map (
I0 => \bresp_cnt[7]_i_3_n_0\,
I1 => \bresp_cnt[7]_i_4_n_0\,
I2 => \bresp_cnt_reg[7]\(6),
I3 => \memory_reg[3][0]_srl4_i_3_n_0\,
I4 => \bresp_cnt_reg[7]\(3),
I5 => \memory_reg[3][3]_srl4_n_0\,
O => \memory_reg[3][0]_srl4_i_2__0_n_0\
);
\memory_reg[3][0]_srl4_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^cnt_read_reg[0]_rep__0_0\,
I1 => \^cnt_read_reg[1]_rep__0_0\,
O => \memory_reg[3][0]_srl4_i_3_n_0\
);
\memory_reg[3][10]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(6),
Q => \out\(2)
);
\memory_reg[3][11]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(7),
Q => \out\(3)
);
\memory_reg[3][12]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(8),
Q => \out\(4)
);
\memory_reg[3][13]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(9),
Q => \out\(5)
);
\memory_reg[3][14]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(10),
Q => \out\(6)
);
\memory_reg[3][15]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(11),
Q => \out\(7)
);
\memory_reg[3][16]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(12),
Q => \out\(8)
);
\memory_reg[3][17]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(13),
Q => \out\(9)
);
\memory_reg[3][18]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(14),
Q => \out\(10)
);
\memory_reg[3][19]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(15),
Q => \out\(11)
);
\memory_reg[3][1]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(1),
Q => \memory_reg[3][1]_srl4_n_0\
);
\memory_reg[3][2]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(2),
Q => \memory_reg[3][2]_srl4_n_0\
);
\memory_reg[3][3]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(3),
Q => \memory_reg[3][3]_srl4_n_0\
);
\memory_reg[3][8]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(4),
Q => \out\(0)
);
\memory_reg[3][9]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(5),
Q => \out\(1)
);
\state[0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^cnt_read_reg[1]_rep__0_0\,
I1 => \^cnt_read_reg[0]_rep__0_0\,
O => \state_reg[0]_rep\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized0\ is
port (
mhandshake : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bready : out STD_LOGIC;
\skid_buffer_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
mhandshake_r : in STD_LOGIC;
shandshake_r : in STD_LOGIC;
sel : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
aclk : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized0\ : entity is "axi_protocol_converter_v2_1_14_b2s_simple_fifo";
end \led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized0\;
architecture STRUCTURE of \led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized0\ is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \cnt_read[1]_i_1__0_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[1]_i_1__0\ : label is "soft_lutpair129";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute SOFT_HLUTNM of m_axi_bready_INST_0 : label is "soft_lutpair129";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][0]_srl4 ";
attribute srl_bus_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][1]_srl4 ";
begin
Q(1 downto 0) <= \^q\(1 downto 0);
\cnt_read[1]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9AA6"
)
port map (
I0 => \^q\(1),
I1 => shandshake_r,
I2 => \^q\(0),
I3 => sel,
O => \cnt_read[1]_i_1__0_n_0\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => D(0),
Q => \^q\(0),
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__0_n_0\,
Q => \^q\(1),
S => areset_d1
);
m_axi_bready_INST_0: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => mhandshake_r,
O => m_axi_bready
);
\memory_reg[3][0]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \^q\(0),
A1 => \^q\(1),
A2 => '0',
A3 => '0',
CE => sel,
CLK => aclk,
D => \in\(0),
Q => \skid_buffer_reg[1]\(0)
);
\memory_reg[3][1]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \^q\(0),
A1 => \^q\(1),
A2 => '0',
A3 => '0',
CE => sel,
CLK => aclk,
D => \in\(1),
Q => \skid_buffer_reg[1]\(1)
);
mhandshake_r_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => m_axi_bvalid,
I1 => mhandshake_r,
I2 => \^q\(1),
I3 => \^q\(0),
O => mhandshake
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized1\ is
port (
\cnt_read_reg[3]_rep__2_0\ : out STD_LOGIC;
wr_en0 : out STD_LOGIC;
\cnt_read_reg[4]_rep__2_0\ : out STD_LOGIC;
\cnt_read_reg[4]_rep__2_1\ : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
\state_reg[1]_rep\ : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 33 downto 0 );
s_ready_i_reg : in STD_LOGIC;
si_rs_rready : in STD_LOGIC;
\cnt_read_reg[3]_rep__0_0\ : in STD_LOGIC;
s_ready_i_reg_0 : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
aclk : in STD_LOGIC;
areset_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized1\ : entity is "axi_protocol_converter_v2_1_14_b2s_simple_fifo";
end \led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized1\;
architecture STRUCTURE of \led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized1\ is
signal cnt_read : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \cnt_read[0]_i_1__1_n_0\ : STD_LOGIC;
signal \cnt_read[1]_i_1__2_n_0\ : STD_LOGIC;
signal \cnt_read[2]_i_1_n_0\ : STD_LOGIC;
signal \cnt_read[3]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_1_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_2__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_3_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__2_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__2_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__2_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep__1_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[3]_rep__2_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep__1_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[4]_rep__2_0\ : STD_LOGIC;
signal \^cnt_read_reg[4]_rep__2_1\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep_n_0\ : STD_LOGIC;
signal \^wr_en0\ : STD_LOGIC;
signal \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[0]_i_1__1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \cnt_read[1]_i_1__2\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \cnt_read[2]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \cnt_read[4]_i_2__0\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \cnt_read[4]_i_3\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \cnt_read[4]_i_5\ : label is "soft_lutpair18";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__1\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__2\ : label is "cnt_read_reg[0]";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__1\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__2\ : label is "cnt_read_reg[1]";
attribute KEEP of \cnt_read_reg[2]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__0\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__1\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__2\ : label is "cnt_read_reg[2]";
attribute KEEP of \cnt_read_reg[3]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__0\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__1\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__2\ : label is "cnt_read_reg[3]";
attribute KEEP of \cnt_read_reg[4]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__0\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__1\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__2\ : label is "cnt_read_reg[4]";
attribute SOFT_HLUTNM of m_axi_rready_INST_0 : label is "soft_lutpair15";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][0]_srl32 ";
attribute srl_bus_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][10]_srl32 ";
attribute srl_bus_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][11]_srl32 ";
attribute srl_bus_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][12]_srl32 ";
attribute srl_bus_name of \memory_reg[31][13]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][13]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][13]_srl32 ";
attribute srl_bus_name of \memory_reg[31][14]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][14]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][14]_srl32 ";
attribute srl_bus_name of \memory_reg[31][15]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][15]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][15]_srl32 ";
attribute srl_bus_name of \memory_reg[31][16]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][16]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][16]_srl32 ";
attribute srl_bus_name of \memory_reg[31][17]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][17]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][17]_srl32 ";
attribute srl_bus_name of \memory_reg[31][18]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][18]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][18]_srl32 ";
attribute srl_bus_name of \memory_reg[31][19]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][19]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][19]_srl32 ";
attribute srl_bus_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][1]_srl32 ";
attribute srl_bus_name of \memory_reg[31][20]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][20]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][20]_srl32 ";
attribute srl_bus_name of \memory_reg[31][21]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][21]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][21]_srl32 ";
attribute srl_bus_name of \memory_reg[31][22]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][22]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][22]_srl32 ";
attribute srl_bus_name of \memory_reg[31][23]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][23]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][23]_srl32 ";
attribute srl_bus_name of \memory_reg[31][24]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][24]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][24]_srl32 ";
attribute srl_bus_name of \memory_reg[31][25]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][25]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][25]_srl32 ";
attribute srl_bus_name of \memory_reg[31][26]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][26]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][26]_srl32 ";
attribute srl_bus_name of \memory_reg[31][27]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][27]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][27]_srl32 ";
attribute srl_bus_name of \memory_reg[31][28]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][28]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][28]_srl32 ";
attribute srl_bus_name of \memory_reg[31][29]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][29]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][29]_srl32 ";
attribute srl_bus_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][2]_srl32 ";
attribute srl_bus_name of \memory_reg[31][30]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][30]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][30]_srl32 ";
attribute srl_bus_name of \memory_reg[31][31]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][31]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][31]_srl32 ";
attribute srl_bus_name of \memory_reg[31][32]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][32]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][32]_srl32 ";
attribute srl_bus_name of \memory_reg[31][33]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][33]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][33]_srl32 ";
attribute srl_bus_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][3]_srl32 ";
attribute srl_bus_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][4]_srl32 ";
attribute srl_bus_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][5]_srl32 ";
attribute srl_bus_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][6]_srl32 ";
attribute srl_bus_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][7]_srl32 ";
attribute srl_bus_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][8]_srl32 ";
attribute srl_bus_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][9]_srl32 ";
attribute SOFT_HLUTNM of \state[1]_i_4\ : label is "soft_lutpair15";
begin
\cnt_read_reg[3]_rep__2_0\ <= \^cnt_read_reg[3]_rep__2_0\;
\cnt_read_reg[4]_rep__2_0\ <= \^cnt_read_reg[4]_rep__2_0\;
\cnt_read_reg[4]_rep__2_1\ <= \^cnt_read_reg[4]_rep__2_1\;
wr_en0 <= \^wr_en0\;
\cnt_read[0]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => s_ready_i_reg,
I2 => \^wr_en0\,
O => \cnt_read[0]_i_1__1_n_0\
);
\cnt_read[1]_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"A96A"
)
port map (
I0 => \cnt_read_reg[1]_rep__2_n_0\,
I1 => \cnt_read_reg[0]_rep__2_n_0\,
I2 => \^wr_en0\,
I3 => s_ready_i_reg,
O => \cnt_read[1]_i_1__2_n_0\
);
\cnt_read[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"A6AAAA9A"
)
port map (
I0 => \cnt_read_reg[2]_rep__2_n_0\,
I1 => \^wr_en0\,
I2 => s_ready_i_reg,
I3 => \cnt_read_reg[0]_rep__2_n_0\,
I4 => \cnt_read_reg[1]_rep__2_n_0\,
O => \cnt_read[2]_i_1_n_0\
);
\cnt_read[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAA96AAAAAAA"
)
port map (
I0 => \^cnt_read_reg[3]_rep__2_0\,
I1 => \cnt_read_reg[1]_rep__2_n_0\,
I2 => \cnt_read_reg[0]_rep__2_n_0\,
I3 => \cnt_read_reg[2]_rep__2_n_0\,
I4 => \^wr_en0\,
I5 => s_ready_i_reg,
O => \cnt_read[3]_i_1__0_n_0\
);
\cnt_read[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA55AA6A6AAA6AAA"
)
port map (
I0 => \^cnt_read_reg[4]_rep__2_0\,
I1 => \cnt_read[4]_i_2__0_n_0\,
I2 => \cnt_read[4]_i_3_n_0\,
I3 => s_ready_i_reg_0,
I4 => \^cnt_read_reg[4]_rep__2_1\,
I5 => \^cnt_read_reg[3]_rep__2_0\,
O => \cnt_read[4]_i_1_n_0\
);
\cnt_read[4]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0004"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => si_rs_rready,
I2 => \cnt_read_reg[3]_rep__0_0\,
I3 => \^wr_en0\,
O => \cnt_read[4]_i_2__0_n_0\
);
\cnt_read[4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cnt_read_reg[1]_rep__2_n_0\,
I1 => \cnt_read_reg[2]_rep__2_n_0\,
O => \cnt_read[4]_i_3_n_0\
);
\cnt_read[4]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \cnt_read_reg[2]_rep__2_n_0\,
I1 => \cnt_read_reg[0]_rep__2_n_0\,
I2 => \cnt_read_reg[1]_rep__2_n_0\,
O => \^cnt_read_reg[4]_rep__2_1\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => cnt_read(0),
S => areset_d1
);
\cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => \cnt_read_reg[0]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => \cnt_read_reg[0]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => \cnt_read_reg[0]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => \cnt_read_reg[0]_rep__2_n_0\,
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => cnt_read(1),
S => areset_d1
);
\cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep__2_n_0\,
S => areset_d1
);
\cnt_read_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => cnt_read(2),
S => areset_d1
);
\cnt_read_reg[2]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep__2_n_0\,
S => areset_d1
);
\cnt_read_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => cnt_read(3),
S => areset_d1
);
\cnt_read_reg[3]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => \cnt_read_reg[3]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => \cnt_read_reg[3]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => \cnt_read_reg[3]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => \^cnt_read_reg[3]_rep__2_0\,
S => areset_d1
);
\cnt_read_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => cnt_read(4),
S => areset_d1
);
\cnt_read_reg[4]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \cnt_read_reg[4]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \cnt_read_reg[4]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \cnt_read_reg[4]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \^cnt_read_reg[4]_rep__2_0\,
S => areset_d1
);
m_axi_rready_INST_0: unisim.vcomponents.LUT5
generic map(
INIT => X"F77F777F"
)
port map (
I0 => \^cnt_read_reg[4]_rep__2_0\,
I1 => \^cnt_read_reg[3]_rep__2_0\,
I2 => \cnt_read_reg[2]_rep__2_n_0\,
I3 => \cnt_read_reg[1]_rep__2_n_0\,
I4 => \cnt_read_reg[0]_rep__2_n_0\,
O => m_axi_rready
);
\memory_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(0),
Q => \out\(0),
Q31 => \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][0]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA2A2AAA2A2A2AAA"
)
port map (
I0 => m_axi_rvalid,
I1 => \^cnt_read_reg[4]_rep__2_0\,
I2 => \^cnt_read_reg[3]_rep__2_0\,
I3 => \cnt_read_reg[2]_rep__2_n_0\,
I4 => \cnt_read_reg[1]_rep__2_n_0\,
I5 => \cnt_read_reg[0]_rep__2_n_0\,
O => \^wr_en0\
);
\memory_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(10),
Q => \out\(10),
Q31 => \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(11),
Q => \out\(11),
Q31 => \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(12),
Q => \out\(12),
Q31 => \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][13]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(13),
Q => \out\(13),
Q31 => \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][14]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(14),
Q => \out\(14),
Q31 => \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][15]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(15),
Q => \out\(15),
Q31 => \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][16]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(16),
Q => \out\(16),
Q31 => \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][17]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(17),
Q => \out\(17),
Q31 => \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][18]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(18),
Q => \out\(18),
Q31 => \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][19]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(19),
Q => \out\(19),
Q31 => \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(1),
Q => \out\(1),
Q31 => \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][20]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(20),
Q => \out\(20),
Q31 => \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][21]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(21),
Q => \out\(21),
Q31 => \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][22]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(22),
Q => \out\(22),
Q31 => \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][23]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(23),
Q => \out\(23),
Q31 => \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][24]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(24),
Q => \out\(24),
Q31 => \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][25]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(25),
Q => \out\(25),
Q31 => \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][26]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(26),
Q => \out\(26),
Q31 => \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][27]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(27),
Q => \out\(27),
Q31 => \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][28]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(28),
Q => \out\(28),
Q31 => \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][29]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(29),
Q => \out\(29),
Q31 => \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(2),
Q => \out\(2),
Q31 => \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][30]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(30),
Q => \out\(30),
Q31 => \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][31]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(31),
Q => \out\(31),
Q31 => \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][32]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(32),
Q => \out\(32),
Q31 => \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][33]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(33),
Q => \out\(33),
Q31 => \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(3),
Q => \out\(3),
Q31 => \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(4),
Q => \out\(4),
Q31 => \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(5),
Q => \out\(5),
Q31 => \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(6),
Q => \out\(6),
Q31 => \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(7),
Q => \out\(7),
Q31 => \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(8),
Q => \out\(8),
Q31 => \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(9),
Q => \out\(9),
Q31 => \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\
);
\state[1]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"7C000000"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => \cnt_read_reg[1]_rep__2_n_0\,
I2 => \cnt_read_reg[2]_rep__2_n_0\,
I3 => \^cnt_read_reg[3]_rep__2_0\,
I4 => \^cnt_read_reg[4]_rep__2_0\,
O => \state_reg[1]_rep\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized2\ is
port (
m_valid_i_reg : out STD_LOGIC;
\state_reg[1]_rep\ : out STD_LOGIC;
\cnt_read_reg[4]_rep__2\ : out STD_LOGIC;
\skid_buffer_reg[46]\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
si_rs_rready : in STD_LOGIC;
r_push_r : in STD_LOGIC;
s_ready_i_reg : in STD_LOGIC;
\cnt_read_reg[0]_rep__2\ : in STD_LOGIC;
wr_en0 : in STD_LOGIC;
\cnt_read_reg[3]_rep__2\ : in STD_LOGIC;
\cnt_read_reg[4]_rep__2_0\ : in STD_LOGIC;
\cnt_read_reg[2]_rep__2\ : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 12 downto 0 );
aclk : in STD_LOGIC;
areset_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized2\ : entity is "axi_protocol_converter_v2_1_14_b2s_simple_fifo";
end \led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized2\;
architecture STRUCTURE of \led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized2\ is
signal cnt_read : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \cnt_read[0]_i_1__2_n_0\ : STD_LOGIC;
signal \cnt_read[1]_i_1__1_n_0\ : STD_LOGIC;
signal \cnt_read[2]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[3]_i_1_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_2_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_3__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep_n_0\ : STD_LOGIC;
signal m_valid_i_i_3_n_0 : STD_LOGIC;
signal \^m_valid_i_reg\ : STD_LOGIC;
signal \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[0]_i_1__2\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \cnt_read[1]_i_1__1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \cnt_read[4]_i_2\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \cnt_read[4]_i_3__0\ : label is "soft_lutpair19";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__1\ : label is "cnt_read_reg[0]";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]";
attribute KEEP of \cnt_read_reg[2]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__0\ : label is "cnt_read_reg[2]";
attribute KEEP of \cnt_read_reg[3]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__0\ : label is "cnt_read_reg[3]";
attribute KEEP of \cnt_read_reg[4]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__0\ : label is "cnt_read_reg[4]";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][0]_srl32 ";
attribute srl_bus_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][10]_srl32 ";
attribute srl_bus_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][11]_srl32 ";
attribute srl_bus_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][12]_srl32 ";
attribute srl_bus_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][1]_srl32 ";
attribute srl_bus_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][2]_srl32 ";
attribute srl_bus_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][3]_srl32 ";
attribute srl_bus_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][4]_srl32 ";
attribute srl_bus_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][5]_srl32 ";
attribute srl_bus_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][6]_srl32 ";
attribute srl_bus_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][7]_srl32 ";
attribute srl_bus_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][8]_srl32 ";
attribute srl_bus_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][9]_srl32 ";
begin
m_valid_i_reg <= \^m_valid_i_reg\;
\cnt_read[0]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cnt_read_reg[0]_rep__1_n_0\,
I1 => s_ready_i_reg,
I2 => r_push_r,
O => \cnt_read[0]_i_1__2_n_0\
);
\cnt_read[1]_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"E718"
)
port map (
I0 => \cnt_read_reg[0]_rep__1_n_0\,
I1 => r_push_r,
I2 => s_ready_i_reg,
I3 => \cnt_read_reg[1]_rep__0_n_0\,
O => \cnt_read[1]_i_1__1_n_0\
);
\cnt_read[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FE7F0180"
)
port map (
I0 => \cnt_read_reg[1]_rep__0_n_0\,
I1 => \cnt_read_reg[0]_rep__0_n_0\,
I2 => r_push_r,
I3 => s_ready_i_reg,
I4 => \cnt_read_reg[2]_rep__0_n_0\,
O => \cnt_read[2]_i_1__0_n_0\
);
\cnt_read[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"DFFFFFFB20000004"
)
port map (
I0 => \cnt_read_reg[1]_rep__0_n_0\,
I1 => s_ready_i_reg,
I2 => r_push_r,
I3 => \cnt_read_reg[0]_rep__0_n_0\,
I4 => \cnt_read_reg[2]_rep__0_n_0\,
I5 => \cnt_read_reg[3]_rep__0_n_0\,
O => \cnt_read[3]_i_1_n_0\
);
\cnt_read[4]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9AAA9AAA9AAA9AA6"
)
port map (
I0 => \cnt_read_reg[4]_rep__0_n_0\,
I1 => \cnt_read[4]_i_2_n_0\,
I2 => \cnt_read_reg[2]_rep__0_n_0\,
I3 => \cnt_read_reg[3]_rep__0_n_0\,
I4 => \cnt_read[4]_i_3__0_n_0\,
I5 => \cnt_read_reg[0]_rep__0_n_0\,
O => \cnt_read[4]_i_1__0_n_0\
);
\cnt_read[4]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"5DFFFFFF"
)
port map (
I0 => \cnt_read_reg[1]_rep__0_n_0\,
I1 => si_rs_rready,
I2 => \^m_valid_i_reg\,
I3 => r_push_r,
I4 => \cnt_read_reg[0]_rep__1_n_0\,
O => \cnt_read[4]_i_2_n_0\
);
\cnt_read[4]_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFEF"
)
port map (
I0 => \cnt_read_reg[1]_rep__0_n_0\,
I1 => \^m_valid_i_reg\,
I2 => si_rs_rready,
I3 => r_push_r,
O => \cnt_read[4]_i_3__0_n_0\
);
\cnt_read[4]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"4F"
)
port map (
I0 => \^m_valid_i_reg\,
I1 => si_rs_rready,
I2 => wr_en0,
O => \cnt_read_reg[4]_rep__2\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__2_n_0\,
Q => cnt_read(0),
S => areset_d1
);
\cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__2_n_0\,
Q => \cnt_read_reg[0]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__2_n_0\,
Q => \cnt_read_reg[0]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__2_n_0\,
Q => \cnt_read_reg[0]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => cnt_read(1),
S => areset_d1
);
\cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => \cnt_read_reg[1]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => \cnt_read_reg[1]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1__0_n_0\,
Q => cnt_read(2),
S => areset_d1
);
\cnt_read_reg[2]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1__0_n_0\,
Q => \cnt_read_reg[2]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1__0_n_0\,
Q => \cnt_read_reg[2]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => cnt_read(3),
S => areset_d1
);
\cnt_read_reg[3]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \cnt_read_reg[3]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \cnt_read_reg[3]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1__0_n_0\,
Q => cnt_read(4),
S => areset_d1
);
\cnt_read_reg[4]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1__0_n_0\,
Q => \cnt_read_reg[4]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1__0_n_0\,
Q => \cnt_read_reg[4]_rep__0_n_0\,
S => areset_d1
);
m_valid_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FF08080808080808"
)
port map (
I0 => \cnt_read_reg[3]_rep__0_n_0\,
I1 => \cnt_read_reg[4]_rep__0_n_0\,
I2 => m_valid_i_i_3_n_0,
I3 => \cnt_read_reg[3]_rep__2\,
I4 => \cnt_read_reg[4]_rep__2_0\,
I5 => \cnt_read_reg[2]_rep__2\,
O => \^m_valid_i_reg\
);
m_valid_i_i_3: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \cnt_read_reg[0]_rep__1_n_0\,
I1 => \cnt_read_reg[2]_rep__0_n_0\,
I2 => \cnt_read_reg[1]_rep__0_n_0\,
O => m_valid_i_i_3_n_0
);
\memory_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(0),
Q => \skid_buffer_reg[46]\(0),
Q31 => \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(10),
Q => \skid_buffer_reg[46]\(10),
Q31 => \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(11),
Q => \skid_buffer_reg[46]\(11),
Q31 => \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(12),
Q => \skid_buffer_reg[46]\(12),
Q31 => \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(1),
Q => \skid_buffer_reg[46]\(1),
Q31 => \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(2),
Q => \skid_buffer_reg[46]\(2),
Q31 => \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(3),
Q => \skid_buffer_reg[46]\(3),
Q31 => \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(4),
Q => \skid_buffer_reg[46]\(4),
Q31 => \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(5),
Q => \skid_buffer_reg[46]\(5),
Q31 => \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(6),
Q => \skid_buffer_reg[46]\(6),
Q31 => \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(7),
Q => \skid_buffer_reg[46]\(7),
Q31 => \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(8),
Q => \skid_buffer_reg[46]\(8),
Q31 => \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(9),
Q => \skid_buffer_reg[46]\(9),
Q31 => \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\
);
\state[1]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"BEAAAAAAFEAAAAAA"
)
port map (
I0 => \cnt_read_reg[0]_rep__2\,
I1 => \cnt_read_reg[1]_rep__0_n_0\,
I2 => \cnt_read_reg[2]_rep__0_n_0\,
I3 => \cnt_read_reg[4]_rep__0_n_0\,
I4 => \cnt_read_reg[3]_rep__0_n_0\,
I5 => \cnt_read_reg[0]_rep__0_n_0\,
O => \state_reg[1]_rep\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_wr_cmd_fsm is
port (
E : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
\axlen_cnt_reg[0]\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axlen_cnt_reg[7]\ : out STD_LOGIC;
s_axburst_eq0_reg : out STD_LOGIC;
wrap_next_pending : out STD_LOGIC;
sel_first_i : out STD_LOGIC;
incr_next_pending : out STD_LOGIC;
s_axburst_eq1_reg : out STD_LOGIC;
sel_first_reg : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
m_axi_awvalid : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
b_push : out STD_LOGIC;
si_rs_awvalid : in STD_LOGIC;
\axlen_cnt_reg[6]\ : in STD_LOGIC;
\m_payload_i_reg[39]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[46]\ : in STD_LOGIC;
next_pending_r_reg : in STD_LOGIC;
next_pending_r_reg_0 : in STD_LOGIC;
\axlen_cnt_reg[1]\ : in STD_LOGIC;
sel_first : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
sel_first_0 : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
s_axburst_eq1_reg_0 : in STD_LOGIC;
\cnt_read_reg[1]_rep__0\ : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
\cnt_read_reg[1]_rep__0_0\ : in STD_LOGIC;
\cnt_read_reg[0]_rep__0\ : in STD_LOGIC;
aclk : in STD_LOGIC
);
end led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_wr_cmd_fsm;
architecture STRUCTURE of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_wr_cmd_fsm is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^axlen_cnt_reg[0]\ : STD_LOGIC;
signal \^b_push\ : STD_LOGIC;
signal \^incr_next_pending\ : STD_LOGIC;
signal next_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^sel_first_i\ : STD_LOGIC;
signal \state_reg[0]_rep_n_0\ : STD_LOGIC;
signal \state_reg[1]_rep_n_0\ : STD_LOGIC;
signal \^wrap_boundary_axaddr_r_reg[0]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^wrap_next_pending\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axlen_cnt[3]_i_1__0\ : label is "soft_lutpair116";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_1__0\ : label is "soft_lutpair114";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1\ : label is "soft_lutpair116";
attribute SOFT_HLUTNM of s_axburst_eq0_i_1 : label is "soft_lutpair115";
attribute SOFT_HLUTNM of s_axburst_eq1_i_1 : label is "soft_lutpair115";
attribute KEEP : string;
attribute KEEP of \state_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \state_reg[0]\ : label is "state_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \state_reg[0]_rep\ : label is 1;
attribute KEEP of \state_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[0]_rep\ : label is "state_reg[0]";
attribute KEEP of \state_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]\ : label is "state_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \state_reg[1]_rep\ : label is 1;
attribute KEEP of \state_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]_rep\ : label is "state_reg[1]";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[11]_i_1__0\ : label is "soft_lutpair114";
begin
Q(1 downto 0) <= \^q\(1 downto 0);
\axlen_cnt_reg[0]\ <= \^axlen_cnt_reg[0]\;
b_push <= \^b_push\;
incr_next_pending <= \^incr_next_pending\;
sel_first_i <= \^sel_first_i\;
\wrap_boundary_axaddr_r_reg[0]\(0) <= \^wrap_boundary_axaddr_r_reg[0]\(0);
wrap_next_pending <= \^wrap_next_pending\;
\axlen_cnt[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"04FF"
)
port map (
I0 => \^q\(0),
I1 => si_rs_awvalid,
I2 => \^q\(1),
I3 => \^axlen_cnt_reg[0]\,
O => E(0)
);
\axlen_cnt[7]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"000004FF"
)
port map (
I0 => \state_reg[0]_rep_n_0\,
I1 => si_rs_awvalid,
I2 => \state_reg[1]_rep_n_0\,
I3 => \^axlen_cnt_reg[0]\,
I4 => \axlen_cnt_reg[6]\,
O => \axlen_cnt_reg[7]\
);
m_axi_awvalid_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \state_reg[0]_rep_n_0\,
I1 => \state_reg[1]_rep_n_0\,
O => m_axi_awvalid
);
\m_payload_i[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^b_push\,
I1 => si_rs_awvalid,
O => \m_payload_i_reg[0]\(0)
);
\memory_reg[3][0]_srl4_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFCF000045000000"
)
port map (
I0 => s_axburst_eq1_reg_0,
I1 => \cnt_read_reg[0]_rep__0\,
I2 => \cnt_read_reg[1]_rep__0_0\,
I3 => m_axi_awready,
I4 => \state_reg[0]_rep_n_0\,
I5 => \state_reg[1]_rep_n_0\,
O => \^b_push\
);
next_pending_r_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \m_payload_i_reg[46]\,
I1 => \^wrap_boundary_axaddr_r_reg[0]\(0),
I2 => next_pending_r_reg,
I3 => \^axlen_cnt_reg[0]\,
I4 => \axlen_cnt_reg[6]\,
O => \^incr_next_pending\
);
\next_pending_r_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B888B8BB"
)
port map (
I0 => \m_payload_i_reg[46]\,
I1 => \^wrap_boundary_axaddr_r_reg[0]\(0),
I2 => next_pending_r_reg_0,
I3 => \^axlen_cnt_reg[0]\,
I4 => \axlen_cnt_reg[1]\,
O => \^wrap_next_pending\
);
next_pending_r_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"5555DD551515DD15"
)
port map (
I0 => \state_reg[1]_rep_n_0\,
I1 => \state_reg[0]_rep_n_0\,
I2 => m_axi_awready,
I3 => \cnt_read_reg[1]_rep__0_0\,
I4 => \cnt_read_reg[0]_rep__0\,
I5 => s_axburst_eq1_reg_0,
O => \^axlen_cnt_reg[0]\
);
s_axburst_eq0_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => \^wrap_next_pending\,
I1 => \m_payload_i_reg[39]\(0),
I2 => \^sel_first_i\,
I3 => \^incr_next_pending\,
O => s_axburst_eq0_reg
);
s_axburst_eq1_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"ABA8"
)
port map (
I0 => \^wrap_next_pending\,
I1 => \m_payload_i_reg[39]\(0),
I2 => \^sel_first_i\,
I3 => \^incr_next_pending\,
O => s_axburst_eq1_reg
);
sel_first_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF88888F88"
)
port map (
I0 => \^axlen_cnt_reg[0]\,
I1 => sel_first,
I2 => \state_reg[1]_rep_n_0\,
I3 => si_rs_awvalid,
I4 => \state_reg[0]_rep_n_0\,
I5 => areset_d1,
O => sel_first_reg
);
\sel_first_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF88888F88"
)
port map (
I0 => \^axlen_cnt_reg[0]\,
I1 => sel_first_0,
I2 => \state_reg[1]_rep_n_0\,
I3 => si_rs_awvalid,
I4 => \state_reg[0]_rep_n_0\,
I5 => areset_d1,
O => sel_first_reg_0
);
\sel_first_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF88888F88"
)
port map (
I0 => \^axlen_cnt_reg[0]\,
I1 => sel_first_reg_1,
I2 => \state_reg[1]_rep_n_0\,
I3 => si_rs_awvalid,
I4 => \state_reg[0]_rep_n_0\,
I5 => areset_d1,
O => \^sel_first_i\
);
\state[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AEFE0E0EFEFE5E5E"
)
port map (
I0 => \state_reg[1]_rep_n_0\,
I1 => si_rs_awvalid,
I2 => \state_reg[0]_rep_n_0\,
I3 => s_axburst_eq1_reg_0,
I4 => \cnt_read_reg[1]_rep__0\,
I5 => m_axi_awready,
O => next_state(0)
);
\state[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"2E220E0000000000"
)
port map (
I0 => m_axi_awready,
I1 => \state_reg[1]_rep_n_0\,
I2 => \cnt_read_reg[0]_rep__0\,
I3 => \cnt_read_reg[1]_rep__0_0\,
I4 => s_axburst_eq1_reg_0,
I5 => \state_reg[0]_rep_n_0\,
O => next_state(1)
);
\state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^q\(0),
R => areset_d1
);
\state_reg[0]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \state_reg[0]_rep_n_0\,
R => areset_d1
);
\state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(1),
Q => \^q\(1),
R => areset_d1
);
\state_reg[1]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(1),
Q => \state_reg[1]_rep_n_0\,
R => areset_d1
);
\wrap_boundary_axaddr_r[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \state_reg[1]_rep_n_0\,
I1 => si_rs_awvalid,
I2 => \state_reg[0]_rep_n_0\,
O => \^wrap_boundary_axaddr_r_reg[0]\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_wrap_cmd is
port (
next_pending_r_reg_0 : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
wrap_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
si_rs_awvalid : in STD_LOGIC;
\m_payload_i_reg[46]\ : in STD_LOGIC_VECTOR ( 17 downto 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
\axaddr_incr_reg[11]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
sel_first_reg_3 : in STD_LOGIC;
sel_first_reg_4 : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
end led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_wrap_cmd;
architecture STRUCTURE of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_wrap_cmd is
signal axaddr_wrap : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axaddr_wrap0 : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \axaddr_wrap[0]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[10]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[1]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[2]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[4]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[5]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[6]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[8]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[9]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_2_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_3\ : STD_LOGIC;
signal \axlen_cnt[0]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[1]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1__1_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_2_n_0\ : STD_LOGIC;
signal \axlen_cnt[4]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[4]\ : STD_LOGIC;
signal \^sel_first_reg_0\ : STD_LOGIC;
signal wrap_boundary_axaddr_r : STD_LOGIC_VECTOR ( 11 downto 0 );
signal wrap_cnt_r : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_axaddr_wrap_reg[11]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axlen_cnt[3]_i_2\ : label is "soft_lutpair126";
attribute SOFT_HLUTNM of \next_pending_r_i_2__0\ : label is "soft_lutpair126";
begin
sel_first_reg_0 <= \^sel_first_reg_0\;
\axaddr_offset_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(0),
Q => \axaddr_offset_r_reg[3]_0\(0),
R => '0'
);
\axaddr_offset_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(1),
Q => \axaddr_offset_r_reg[3]_0\(1),
R => '0'
);
\axaddr_offset_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(2),
Q => \axaddr_offset_r_reg[3]_0\(2),
R => '0'
);
\axaddr_offset_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(3),
Q => \axaddr_offset_r_reg[3]_0\(3),
R => '0'
);
\axaddr_wrap[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \m_payload_i_reg[46]\(0),
I1 => \state_reg[1]_rep\,
I2 => axaddr_wrap0(0),
I3 => \axaddr_wrap[11]_i_3_n_0\,
I4 => wrap_boundary_axaddr_r(0),
O => \axaddr_wrap[0]_i_1_n_0\
);
\axaddr_wrap[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \m_payload_i_reg[46]\(10),
I1 => \state_reg[1]_rep\,
I2 => axaddr_wrap0(10),
I3 => \axaddr_wrap[11]_i_3_n_0\,
I4 => wrap_boundary_axaddr_r(10),
O => \axaddr_wrap[10]_i_1_n_0\
);
\axaddr_wrap[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \m_payload_i_reg[46]\(11),
I1 => \state_reg[1]_rep\,
I2 => axaddr_wrap0(11),
I3 => \axaddr_wrap[11]_i_3_n_0\,
I4 => wrap_boundary_axaddr_r(11),
O => \axaddr_wrap[11]_i_1_n_0\
);
\axaddr_wrap[11]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFF6"
)
port map (
I0 => wrap_cnt_r(3),
I1 => \axlen_cnt_reg_n_0_[3]\,
I2 => \axaddr_wrap[11]_i_4_n_0\,
I3 => \axlen_cnt_reg_n_0_[4]\,
O => \axaddr_wrap[11]_i_3_n_0\
);
\axaddr_wrap[11]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => wrap_cnt_r(0),
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => wrap_cnt_r(1),
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => wrap_cnt_r(2),
O => \axaddr_wrap[11]_i_4_n_0\
);
\axaddr_wrap[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \m_payload_i_reg[46]\(1),
I1 => \state_reg[1]_rep\,
I2 => axaddr_wrap0(1),
I3 => \axaddr_wrap[11]_i_3_n_0\,
I4 => wrap_boundary_axaddr_r(1),
O => \axaddr_wrap[1]_i_1_n_0\
);
\axaddr_wrap[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \m_payload_i_reg[46]\(2),
I1 => \state_reg[1]_rep\,
I2 => axaddr_wrap0(2),
I3 => \axaddr_wrap[11]_i_3_n_0\,
I4 => wrap_boundary_axaddr_r(2),
O => \axaddr_wrap[2]_i_1_n_0\
);
\axaddr_wrap[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \m_payload_i_reg[46]\(3),
I1 => \state_reg[1]_rep\,
I2 => axaddr_wrap0(3),
I3 => \axaddr_wrap[11]_i_3_n_0\,
I4 => wrap_boundary_axaddr_r(3),
O => \axaddr_wrap[3]_i_1_n_0\
);
\axaddr_wrap[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => axaddr_wrap(3),
I1 => \m_payload_i_reg[46]\(13),
I2 => \m_payload_i_reg[46]\(12),
O => \axaddr_wrap[3]_i_3_n_0\
);
\axaddr_wrap[3]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => axaddr_wrap(2),
I1 => \m_payload_i_reg[46]\(12),
I2 => \m_payload_i_reg[46]\(13),
O => \axaddr_wrap[3]_i_4_n_0\
);
\axaddr_wrap[3]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => axaddr_wrap(1),
I1 => \m_payload_i_reg[46]\(13),
I2 => \m_payload_i_reg[46]\(12),
O => \axaddr_wrap[3]_i_5_n_0\
);
\axaddr_wrap[3]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"A9"
)
port map (
I0 => axaddr_wrap(0),
I1 => \m_payload_i_reg[46]\(13),
I2 => \m_payload_i_reg[46]\(12),
O => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \m_payload_i_reg[46]\(4),
I1 => \state_reg[1]_rep\,
I2 => axaddr_wrap0(4),
I3 => \axaddr_wrap[11]_i_3_n_0\,
I4 => wrap_boundary_axaddr_r(4),
O => \axaddr_wrap[4]_i_1_n_0\
);
\axaddr_wrap[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \m_payload_i_reg[46]\(5),
I1 => \state_reg[1]_rep\,
I2 => axaddr_wrap0(5),
I3 => \axaddr_wrap[11]_i_3_n_0\,
I4 => wrap_boundary_axaddr_r(5),
O => \axaddr_wrap[5]_i_1_n_0\
);
\axaddr_wrap[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \m_payload_i_reg[46]\(6),
I1 => \state_reg[1]_rep\,
I2 => axaddr_wrap0(6),
I3 => \axaddr_wrap[11]_i_3_n_0\,
I4 => wrap_boundary_axaddr_r(6),
O => \axaddr_wrap[6]_i_1_n_0\
);
\axaddr_wrap[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \m_payload_i_reg[46]\(7),
I1 => \state_reg[1]_rep\,
I2 => axaddr_wrap0(7),
I3 => \axaddr_wrap[11]_i_3_n_0\,
I4 => wrap_boundary_axaddr_r(7),
O => \axaddr_wrap[7]_i_1_n_0\
);
\axaddr_wrap[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \m_payload_i_reg[46]\(8),
I1 => \state_reg[1]_rep\,
I2 => axaddr_wrap0(8),
I3 => \axaddr_wrap[11]_i_3_n_0\,
I4 => wrap_boundary_axaddr_r(8),
O => \axaddr_wrap[8]_i_1_n_0\
);
\axaddr_wrap[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \m_payload_i_reg[46]\(9),
I1 => \state_reg[1]_rep\,
I2 => axaddr_wrap0(9),
I3 => \axaddr_wrap[11]_i_3_n_0\,
I4 => wrap_boundary_axaddr_r(9),
O => \axaddr_wrap[9]_i_1_n_0\
);
\axaddr_wrap_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[0]_i_1_n_0\,
Q => axaddr_wrap(0),
R => '0'
);
\axaddr_wrap_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[10]_i_1_n_0\,
Q => axaddr_wrap(10),
R => '0'
);
\axaddr_wrap_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[11]_i_1_n_0\,
Q => axaddr_wrap(11),
R => '0'
);
\axaddr_wrap_reg[11]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[7]_i_2_n_0\,
CO(3) => \NLW_axaddr_wrap_reg[11]_i_2_CO_UNCONNECTED\(3),
CO(2) => \axaddr_wrap_reg[11]_i_2_n_1\,
CO(1) => \axaddr_wrap_reg[11]_i_2_n_2\,
CO(0) => \axaddr_wrap_reg[11]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => axaddr_wrap0(11 downto 8),
S(3 downto 0) => axaddr_wrap(11 downto 8)
);
\axaddr_wrap_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[1]_i_1_n_0\,
Q => axaddr_wrap(1),
R => '0'
);
\axaddr_wrap_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[2]_i_1_n_0\,
Q => axaddr_wrap(2),
R => '0'
);
\axaddr_wrap_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[3]_i_1_n_0\,
Q => axaddr_wrap(3),
R => '0'
);
\axaddr_wrap_reg[3]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_wrap_reg[3]_i_2_n_0\,
CO(2) => \axaddr_wrap_reg[3]_i_2_n_1\,
CO(1) => \axaddr_wrap_reg[3]_i_2_n_2\,
CO(0) => \axaddr_wrap_reg[3]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => axaddr_wrap(3 downto 0),
O(3 downto 0) => axaddr_wrap0(3 downto 0),
S(3) => \axaddr_wrap[3]_i_3_n_0\,
S(2) => \axaddr_wrap[3]_i_4_n_0\,
S(1) => \axaddr_wrap[3]_i_5_n_0\,
S(0) => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[4]_i_1_n_0\,
Q => axaddr_wrap(4),
R => '0'
);
\axaddr_wrap_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[5]_i_1_n_0\,
Q => axaddr_wrap(5),
R => '0'
);
\axaddr_wrap_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[6]_i_1_n_0\,
Q => axaddr_wrap(6),
R => '0'
);
\axaddr_wrap_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[7]_i_1_n_0\,
Q => axaddr_wrap(7),
R => '0'
);
\axaddr_wrap_reg[7]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[3]_i_2_n_0\,
CO(3) => \axaddr_wrap_reg[7]_i_2_n_0\,
CO(2) => \axaddr_wrap_reg[7]_i_2_n_1\,
CO(1) => \axaddr_wrap_reg[7]_i_2_n_2\,
CO(0) => \axaddr_wrap_reg[7]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => axaddr_wrap0(7 downto 4),
S(3 downto 0) => axaddr_wrap(7 downto 4)
);
\axaddr_wrap_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[8]_i_1_n_0\,
Q => axaddr_wrap(8),
R => '0'
);
\axaddr_wrap_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[9]_i_1_n_0\,
Q => axaddr_wrap(9),
R => '0'
);
\axlen_cnt[0]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"44444F4444444444"
)
port map (
I0 => \axlen_cnt_reg_n_0_[0]\,
I1 => \axlen_cnt[3]_i_2_n_0\,
I2 => Q(1),
I3 => si_rs_awvalid,
I4 => Q(0),
I5 => \m_payload_i_reg[46]\(15),
O => \axlen_cnt[0]_i_1__2_n_0\
);
\axlen_cnt[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[46]\(16),
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => \axlen_cnt[3]_i_2_n_0\,
O => \axlen_cnt[1]_i_1__0_n_0\
);
\axlen_cnt[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"F8F8F88F88888888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[46]\(17),
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => \axlen_cnt_reg_n_0_[1]\,
I5 => \axlen_cnt[3]_i_2_n_0\,
O => \axlen_cnt[2]_i_1__0_n_0\
);
\axlen_cnt[3]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA90000FFFFFFFF"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => \axlen_cnt[3]_i_2_n_0\,
I5 => \m_payload_i_reg[47]\,
O => \axlen_cnt[3]_i_1__1_n_0\
);
\axlen_cnt[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"55555554"
)
port map (
I0 => E(0),
I1 => \axlen_cnt_reg_n_0_[3]\,
I2 => \axlen_cnt_reg_n_0_[4]\,
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => \axlen_cnt_reg_n_0_[1]\,
O => \axlen_cnt[3]_i_2_n_0\
);
\axlen_cnt[4]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4444444444444440"
)
port map (
I0 => E(0),
I1 => \axlen_cnt_reg_n_0_[4]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => \axlen_cnt_reg_n_0_[1]\,
I5 => \axlen_cnt_reg_n_0_[2]\,
O => \axlen_cnt[4]_i_1__0_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[0]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[0]\,
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[1]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[1]\,
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[2]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[3]_i_1__1_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\axlen_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[4]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[4]\,
R => '0'
);
\m_axi_awaddr[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(0),
I2 => \m_payload_i_reg[46]\(14),
I3 => \m_payload_i_reg[46]\(0),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(0),
O => m_axi_awaddr(0)
);
\m_axi_awaddr[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(10),
I2 => \m_payload_i_reg[46]\(14),
I3 => \m_payload_i_reg[46]\(10),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(8),
O => m_axi_awaddr(10)
);
\m_axi_awaddr[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(11),
I2 => \m_payload_i_reg[46]\(14),
I3 => \m_payload_i_reg[46]\(11),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(9),
O => m_axi_awaddr(11)
);
\m_axi_awaddr[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(1),
I2 => \m_payload_i_reg[46]\(14),
I3 => \m_payload_i_reg[46]\(1),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(1),
O => m_axi_awaddr(1)
);
\m_axi_awaddr[2]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \m_payload_i_reg[46]\(2),
I1 => \^sel_first_reg_0\,
I2 => axaddr_wrap(2),
I3 => \m_payload_i_reg[46]\(14),
I4 => sel_first_reg_4,
O => m_axi_awaddr(2)
);
\m_axi_awaddr[3]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \m_payload_i_reg[46]\(3),
I1 => \^sel_first_reg_0\,
I2 => axaddr_wrap(3),
I3 => \m_payload_i_reg[46]\(14),
I4 => sel_first_reg_3,
O => m_axi_awaddr(3)
);
\m_axi_awaddr[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(4),
I2 => \m_payload_i_reg[46]\(14),
I3 => \m_payload_i_reg[46]\(4),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(2),
O => m_axi_awaddr(4)
);
\m_axi_awaddr[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(5),
I2 => \m_payload_i_reg[46]\(14),
I3 => \m_payload_i_reg[46]\(5),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(3),
O => m_axi_awaddr(5)
);
\m_axi_awaddr[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(6),
I2 => \m_payload_i_reg[46]\(14),
I3 => \m_payload_i_reg[46]\(6),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(4),
O => m_axi_awaddr(6)
);
\m_axi_awaddr[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(7),
I2 => \m_payload_i_reg[46]\(14),
I3 => \m_payload_i_reg[46]\(7),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(5),
O => m_axi_awaddr(7)
);
\m_axi_awaddr[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(8),
I2 => \m_payload_i_reg[46]\(14),
I3 => \m_payload_i_reg[46]\(8),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(6),
O => m_axi_awaddr(8)
);
\m_axi_awaddr[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(9),
I2 => \m_payload_i_reg[46]\(14),
I3 => \m_payload_i_reg[46]\(9),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(7),
O => m_axi_awaddr(9)
);
\next_pending_r_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \axlen_cnt_reg_n_0_[1]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[4]\,
I3 => \axlen_cnt_reg_n_0_[3]\,
O => next_pending_r_reg_1
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => wrap_next_pending,
Q => next_pending_r_reg_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^sel_first_reg_0\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(0),
Q => wrap_boundary_axaddr_r(0),
R => '0'
);
\wrap_boundary_axaddr_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[46]\(10),
Q => wrap_boundary_axaddr_r(10),
R => '0'
);
\wrap_boundary_axaddr_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[46]\(11),
Q => wrap_boundary_axaddr_r(11),
R => '0'
);
\wrap_boundary_axaddr_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(1),
Q => wrap_boundary_axaddr_r(1),
R => '0'
);
\wrap_boundary_axaddr_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(2),
Q => wrap_boundary_axaddr_r(2),
R => '0'
);
\wrap_boundary_axaddr_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(3),
Q => wrap_boundary_axaddr_r(3),
R => '0'
);
\wrap_boundary_axaddr_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(4),
Q => wrap_boundary_axaddr_r(4),
R => '0'
);
\wrap_boundary_axaddr_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(5),
Q => wrap_boundary_axaddr_r(5),
R => '0'
);
\wrap_boundary_axaddr_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(6),
Q => wrap_boundary_axaddr_r(6),
R => '0'
);
\wrap_boundary_axaddr_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[46]\(7),
Q => wrap_boundary_axaddr_r(7),
R => '0'
);
\wrap_boundary_axaddr_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[46]\(8),
Q => wrap_boundary_axaddr_r(8),
R => '0'
);
\wrap_boundary_axaddr_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[46]\(9),
Q => wrap_boundary_axaddr_r(9),
R => '0'
);
\wrap_cnt_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(0),
Q => wrap_cnt_r(0),
R => '0'
);
\wrap_cnt_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(1),
Q => wrap_cnt_r(1),
R => '0'
);
\wrap_cnt_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(2),
Q => wrap_cnt_r(2),
R => '0'
);
\wrap_cnt_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(3),
Q => wrap_cnt_r(3),
R => '0'
);
\wrap_second_len_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(0),
Q => \wrap_second_len_r_reg[3]_0\(0),
R => '0'
);
\wrap_second_len_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(1),
Q => \wrap_second_len_r_reg[3]_0\(1),
R => '0'
);
\wrap_second_len_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(2),
Q => \wrap_second_len_r_reg[3]_0\(2),
R => '0'
);
\wrap_second_len_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(3),
Q => \wrap_second_len_r_reg[3]_0\(3),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_wrap_cmd_3 is
port (
next_pending_r_reg_0 : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
\axlen_cnt_reg[0]_0\ : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
wrap_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 17 downto 0 );
\state_reg[1]_rep\ : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
\axaddr_incr_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
si_rs_arvalid : in STD_LOGIC;
\state_reg[0]_rep\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC;
\m_payload_i_reg[35]\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_wrap_cmd_3 : entity is "axi_protocol_converter_v2_1_14_b2s_wrap_cmd";
end led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_wrap_cmd_3;
architecture STRUCTURE of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_wrap_cmd_3 is
signal \axaddr_wrap[0]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[10]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[1]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[2]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[4]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[5]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[6]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[8]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[9]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_2__0_n_4\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_2__0_n_5\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_2__0_n_6\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_2__0_n_7\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_4\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_5\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_6\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_7\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_4\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_5\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_6\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_7\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[0]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[10]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[11]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[1]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[2]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[3]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[4]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[5]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[6]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[7]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[8]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[9]\ : STD_LOGIC;
signal \axlen_cnt[0]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[1]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[4]_i_1__1_n_0\ : STD_LOGIC;
signal \^axlen_cnt_reg[0]_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[4]\ : STD_LOGIC;
signal \^sel_first_reg_0\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[0]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[10]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[11]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[1]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[2]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[3]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[4]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[5]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[6]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[7]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[8]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_cnt_r[1]_i_1_n_0\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[0]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[1]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[2]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[3]\ : STD_LOGIC;
signal \^wrap_second_len_r_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_axaddr_wrap_reg[11]_i_2__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
begin
\axlen_cnt_reg[0]_0\ <= \^axlen_cnt_reg[0]_0\;
sel_first_reg_0 <= \^sel_first_reg_0\;
\wrap_second_len_r_reg[3]_0\(3 downto 0) <= \^wrap_second_len_r_reg[3]_0\(3 downto 0);
\axaddr_offset_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(0),
Q => \axaddr_offset_r_reg[3]_0\(0),
R => '0'
);
\axaddr_offset_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(1),
Q => \axaddr_offset_r_reg[3]_0\(1),
R => '0'
);
\axaddr_offset_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(2),
Q => \axaddr_offset_r_reg[3]_0\(2),
R => '0'
);
\axaddr_offset_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(3),
Q => \axaddr_offset_r_reg[3]_0\(3),
R => '0'
);
\axaddr_wrap[0]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \axaddr_wrap_reg[3]_i_2__0_n_7\,
I1 => \axaddr_wrap[11]_i_3__0_n_0\,
I2 => \wrap_boundary_axaddr_r_reg_n_0_[0]\,
I3 => \state_reg[1]_rep\,
I4 => Q(0),
O => \axaddr_wrap[0]_i_1__0_n_0\
);
\axaddr_wrap[10]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \axaddr_wrap_reg[11]_i_2__0_n_5\,
I1 => \axaddr_wrap[11]_i_3__0_n_0\,
I2 => \wrap_boundary_axaddr_r_reg_n_0_[10]\,
I3 => \state_reg[1]_rep\,
I4 => Q(10),
O => \axaddr_wrap[10]_i_1__0_n_0\
);
\axaddr_wrap[11]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \axaddr_wrap_reg[11]_i_2__0_n_4\,
I1 => \axaddr_wrap[11]_i_3__0_n_0\,
I2 => \wrap_boundary_axaddr_r_reg_n_0_[11]\,
I3 => \state_reg[1]_rep\,
I4 => Q(11),
O => \axaddr_wrap[11]_i_1__0_n_0\
);
\axaddr_wrap[11]_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFF6"
)
port map (
I0 => \wrap_cnt_r_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[3]\,
I2 => \axaddr_wrap[11]_i_4__0_n_0\,
I3 => \axlen_cnt_reg_n_0_[4]\,
O => \axaddr_wrap[11]_i_3__0_n_0\
);
\axaddr_wrap[11]_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => \wrap_cnt_r_reg_n_0_[0]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \wrap_cnt_r_reg_n_0_[2]\,
I4 => \axlen_cnt_reg_n_0_[1]\,
I5 => \wrap_cnt_r_reg_n_0_[1]\,
O => \axaddr_wrap[11]_i_4__0_n_0\
);
\axaddr_wrap[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \axaddr_wrap_reg[3]_i_2__0_n_6\,
I1 => \axaddr_wrap[11]_i_3__0_n_0\,
I2 => \wrap_boundary_axaddr_r_reg_n_0_[1]\,
I3 => \state_reg[1]_rep\,
I4 => Q(1),
O => \axaddr_wrap[1]_i_1__0_n_0\
);
\axaddr_wrap[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \axaddr_wrap_reg[3]_i_2__0_n_5\,
I1 => \axaddr_wrap[11]_i_3__0_n_0\,
I2 => \wrap_boundary_axaddr_r_reg_n_0_[2]\,
I3 => \state_reg[1]_rep\,
I4 => Q(2),
O => \axaddr_wrap[2]_i_1__0_n_0\
);
\axaddr_wrap[3]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \axaddr_wrap_reg[3]_i_2__0_n_4\,
I1 => \axaddr_wrap[11]_i_3__0_n_0\,
I2 => \wrap_boundary_axaddr_r_reg_n_0_[3]\,
I3 => \state_reg[1]_rep\,
I4 => Q(3),
O => \axaddr_wrap[3]_i_1__0_n_0\
);
\axaddr_wrap[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[3]\,
I1 => Q(13),
I2 => Q(12),
O => \axaddr_wrap[3]_i_3_n_0\
);
\axaddr_wrap[3]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[2]\,
I1 => Q(12),
I2 => Q(13),
O => \axaddr_wrap[3]_i_4_n_0\
);
\axaddr_wrap[3]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[1]\,
I1 => Q(13),
I2 => Q(12),
O => \axaddr_wrap[3]_i_5_n_0\
);
\axaddr_wrap[3]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"A9"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[0]\,
I1 => Q(13),
I2 => Q(12),
O => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \axaddr_wrap_reg[7]_i_2__0_n_7\,
I1 => \axaddr_wrap[11]_i_3__0_n_0\,
I2 => \wrap_boundary_axaddr_r_reg_n_0_[4]\,
I3 => \state_reg[1]_rep\,
I4 => Q(4),
O => \axaddr_wrap[4]_i_1__0_n_0\
);
\axaddr_wrap[5]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \axaddr_wrap_reg[7]_i_2__0_n_6\,
I1 => \axaddr_wrap[11]_i_3__0_n_0\,
I2 => \wrap_boundary_axaddr_r_reg_n_0_[5]\,
I3 => \state_reg[1]_rep\,
I4 => Q(5),
O => \axaddr_wrap[5]_i_1__0_n_0\
);
\axaddr_wrap[6]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \axaddr_wrap_reg[7]_i_2__0_n_5\,
I1 => \axaddr_wrap[11]_i_3__0_n_0\,
I2 => \wrap_boundary_axaddr_r_reg_n_0_[6]\,
I3 => \state_reg[1]_rep\,
I4 => Q(6),
O => \axaddr_wrap[6]_i_1__0_n_0\
);
\axaddr_wrap[7]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \axaddr_wrap_reg[7]_i_2__0_n_4\,
I1 => \axaddr_wrap[11]_i_3__0_n_0\,
I2 => \wrap_boundary_axaddr_r_reg_n_0_[7]\,
I3 => \state_reg[1]_rep\,
I4 => Q(7),
O => \axaddr_wrap[7]_i_1__0_n_0\
);
\axaddr_wrap[8]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \axaddr_wrap_reg[11]_i_2__0_n_7\,
I1 => \axaddr_wrap[11]_i_3__0_n_0\,
I2 => \wrap_boundary_axaddr_r_reg_n_0_[8]\,
I3 => \state_reg[1]_rep\,
I4 => Q(8),
O => \axaddr_wrap[8]_i_1__0_n_0\
);
\axaddr_wrap[9]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \axaddr_wrap_reg[11]_i_2__0_n_6\,
I1 => \axaddr_wrap[11]_i_3__0_n_0\,
I2 => \wrap_boundary_axaddr_r_reg_n_0_[9]\,
I3 => \state_reg[1]_rep\,
I4 => Q(9),
O => \axaddr_wrap[9]_i_1__0_n_0\
);
\axaddr_wrap_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[0]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[0]\,
R => '0'
);
\axaddr_wrap_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[10]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[10]\,
R => '0'
);
\axaddr_wrap_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[11]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[11]\,
R => '0'
);
\axaddr_wrap_reg[11]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[7]_i_2__0_n_0\,
CO(3) => \NLW_axaddr_wrap_reg[11]_i_2__0_CO_UNCONNECTED\(3),
CO(2) => \axaddr_wrap_reg[11]_i_2__0_n_1\,
CO(1) => \axaddr_wrap_reg[11]_i_2__0_n_2\,
CO(0) => \axaddr_wrap_reg[11]_i_2__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_wrap_reg[11]_i_2__0_n_4\,
O(2) => \axaddr_wrap_reg[11]_i_2__0_n_5\,
O(1) => \axaddr_wrap_reg[11]_i_2__0_n_6\,
O(0) => \axaddr_wrap_reg[11]_i_2__0_n_7\,
S(3) => \axaddr_wrap_reg_n_0_[11]\,
S(2) => \axaddr_wrap_reg_n_0_[10]\,
S(1) => \axaddr_wrap_reg_n_0_[9]\,
S(0) => \axaddr_wrap_reg_n_0_[8]\
);
\axaddr_wrap_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[1]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[1]\,
R => '0'
);
\axaddr_wrap_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[2]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[2]\,
R => '0'
);
\axaddr_wrap_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[3]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[3]\,
R => '0'
);
\axaddr_wrap_reg[3]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_wrap_reg[3]_i_2__0_n_0\,
CO(2) => \axaddr_wrap_reg[3]_i_2__0_n_1\,
CO(1) => \axaddr_wrap_reg[3]_i_2__0_n_2\,
CO(0) => \axaddr_wrap_reg[3]_i_2__0_n_3\,
CYINIT => '0',
DI(3) => \axaddr_wrap_reg_n_0_[3]\,
DI(2) => \axaddr_wrap_reg_n_0_[2]\,
DI(1) => \axaddr_wrap_reg_n_0_[1]\,
DI(0) => \axaddr_wrap_reg_n_0_[0]\,
O(3) => \axaddr_wrap_reg[3]_i_2__0_n_4\,
O(2) => \axaddr_wrap_reg[3]_i_2__0_n_5\,
O(1) => \axaddr_wrap_reg[3]_i_2__0_n_6\,
O(0) => \axaddr_wrap_reg[3]_i_2__0_n_7\,
S(3) => \axaddr_wrap[3]_i_3_n_0\,
S(2) => \axaddr_wrap[3]_i_4_n_0\,
S(1) => \axaddr_wrap[3]_i_5_n_0\,
S(0) => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[4]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[4]\,
R => '0'
);
\axaddr_wrap_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[5]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[5]\,
R => '0'
);
\axaddr_wrap_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[6]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[6]\,
R => '0'
);
\axaddr_wrap_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[7]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[7]\,
R => '0'
);
\axaddr_wrap_reg[7]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[3]_i_2__0_n_0\,
CO(3) => \axaddr_wrap_reg[7]_i_2__0_n_0\,
CO(2) => \axaddr_wrap_reg[7]_i_2__0_n_1\,
CO(1) => \axaddr_wrap_reg[7]_i_2__0_n_2\,
CO(0) => \axaddr_wrap_reg[7]_i_2__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_wrap_reg[7]_i_2__0_n_4\,
O(2) => \axaddr_wrap_reg[7]_i_2__0_n_5\,
O(1) => \axaddr_wrap_reg[7]_i_2__0_n_6\,
O(0) => \axaddr_wrap_reg[7]_i_2__0_n_7\,
S(3) => \axaddr_wrap_reg_n_0_[7]\,
S(2) => \axaddr_wrap_reg_n_0_[6]\,
S(1) => \axaddr_wrap_reg_n_0_[5]\,
S(0) => \axaddr_wrap_reg_n_0_[4]\
);
\axaddr_wrap_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[8]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[8]\,
R => '0'
);
\axaddr_wrap_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[9]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[9]\,
R => '0'
);
\axlen_cnt[0]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"20FF2020"
)
port map (
I0 => si_rs_arvalid,
I1 => \state_reg[0]_rep\,
I2 => Q(15),
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => \^axlen_cnt_reg[0]_0\,
O => \axlen_cnt[0]_i_1__0_n_0\
);
\axlen_cnt[1]_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => E(0),
I1 => Q(16),
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => \^axlen_cnt_reg[0]_0\,
O => \axlen_cnt[1]_i_1__2_n_0\
);
\axlen_cnt[2]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F8F8F88F88888888"
)
port map (
I0 => E(0),
I1 => Q(17),
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => \axlen_cnt_reg_n_0_[1]\,
I5 => \^axlen_cnt_reg[0]_0\,
O => \axlen_cnt[2]_i_1__2_n_0\
);
\axlen_cnt[3]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA90000FFFFFFFF"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => \^axlen_cnt_reg[0]_0\,
I5 => \m_payload_i_reg[47]\,
O => \axlen_cnt[3]_i_1__2_n_0\
);
\axlen_cnt[3]_i_2__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"55555554"
)
port map (
I0 => E(0),
I1 => \axlen_cnt_reg_n_0_[3]\,
I2 => \axlen_cnt_reg_n_0_[4]\,
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => \axlen_cnt_reg_n_0_[1]\,
O => \^axlen_cnt_reg[0]_0\
);
\axlen_cnt[4]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4444444444444440"
)
port map (
I0 => E(0),
I1 => \axlen_cnt_reg_n_0_[4]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => \axlen_cnt_reg_n_0_[1]\,
I5 => \axlen_cnt_reg_n_0_[2]\,
O => \axlen_cnt[4]_i_1__1_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[0]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[0]\,
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[1]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[1]\,
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[2]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\axlen_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[4]_i_1__1_n_0\,
Q => \axlen_cnt_reg_n_0_[4]\,
R => '0'
);
\m_axi_araddr[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[0]\,
I2 => Q(14),
I3 => Q(0),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(0),
O => m_axi_araddr(0)
);
\m_axi_araddr[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[10]\,
I2 => Q(14),
I3 => Q(10),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(10),
O => m_axi_araddr(10)
);
\m_axi_araddr[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[11]\,
I2 => Q(14),
I3 => Q(11),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(11),
O => m_axi_araddr(11)
);
\m_axi_araddr[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[1]\,
I2 => Q(14),
I3 => Q(1),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(1),
O => m_axi_araddr(1)
);
\m_axi_araddr[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[2]\,
I2 => Q(14),
I3 => Q(2),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(2),
O => m_axi_araddr(2)
);
\m_axi_araddr[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[3]\,
I2 => Q(14),
I3 => Q(3),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(3),
O => m_axi_araddr(3)
);
\m_axi_araddr[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[4]\,
I2 => Q(14),
I3 => Q(4),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(4),
O => m_axi_araddr(4)
);
\m_axi_araddr[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[5]\,
I2 => Q(14),
I3 => Q(5),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(5),
O => m_axi_araddr(5)
);
\m_axi_araddr[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[6]\,
I2 => Q(14),
I3 => Q(6),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(6),
O => m_axi_araddr(6)
);
\m_axi_araddr[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[7]\,
I2 => Q(14),
I3 => Q(7),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(7),
O => m_axi_araddr(7)
);
\m_axi_araddr[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[8]\,
I2 => Q(14),
I3 => Q(8),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(8),
O => m_axi_araddr(8)
);
\m_axi_araddr[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[9]\,
I2 => Q(14),
I3 => Q(9),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(9),
O => m_axi_araddr(9)
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => wrap_next_pending,
Q => next_pending_r_reg_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^sel_first_reg_0\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(0),
Q => \wrap_boundary_axaddr_r_reg_n_0_[0]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => Q(10),
Q => \wrap_boundary_axaddr_r_reg_n_0_[10]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => Q(11),
Q => \wrap_boundary_axaddr_r_reg_n_0_[11]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(1),
Q => \wrap_boundary_axaddr_r_reg_n_0_[1]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(2),
Q => \wrap_boundary_axaddr_r_reg_n_0_[2]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(3),
Q => \wrap_boundary_axaddr_r_reg_n_0_[3]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(4),
Q => \wrap_boundary_axaddr_r_reg_n_0_[4]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(5),
Q => \wrap_boundary_axaddr_r_reg_n_0_[5]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(6),
Q => \wrap_boundary_axaddr_r_reg_n_0_[6]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => Q(7),
Q => \wrap_boundary_axaddr_r_reg_n_0_[7]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => Q(8),
Q => \wrap_boundary_axaddr_r_reg_n_0_[8]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => Q(9),
Q => \wrap_boundary_axaddr_r_reg_n_0_[9]\,
R => '0'
);
\wrap_cnt_r[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"313D020E"
)
port map (
I0 => \^wrap_second_len_r_reg[3]_0\(0),
I1 => E(0),
I2 => \axaddr_offset_r_reg[3]_1\,
I3 => \m_payload_i_reg[35]\,
I4 => \^wrap_second_len_r_reg[3]_0\(1),
O => \wrap_cnt_r[1]_i_1_n_0\
);
\wrap_cnt_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(0),
Q => \wrap_cnt_r_reg_n_0_[0]\,
R => '0'
);
\wrap_cnt_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_cnt_r[1]_i_1_n_0\,
Q => \wrap_cnt_r_reg_n_0_[1]\,
R => '0'
);
\wrap_cnt_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(1),
Q => \wrap_cnt_r_reg_n_0_[2]\,
R => '0'
);
\wrap_cnt_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(2),
Q => \wrap_cnt_r_reg_n_0_[3]\,
R => '0'
);
\wrap_second_len_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(0),
Q => \^wrap_second_len_r_reg[3]_0\(0),
R => '0'
);
\wrap_second_len_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(1),
Q => \^wrap_second_len_r_reg[3]_0\(1),
R => '0'
);
\wrap_second_len_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(2),
Q => \^wrap_second_len_r_reg[3]_0\(2),
R => '0'
);
\wrap_second_len_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(3),
Q => \^wrap_second_len_r_reg[3]_0\(3),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity led_controller_design_auto_pc_0_axi_register_slice_v2_1_14_axic_register_slice is
port (
s_axi_arready : out STD_LOGIC;
s_ready_i_reg_0 : out STD_LOGIC;
m_valid_i_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : out STD_LOGIC_VECTOR ( 53 downto 0 );
\axaddr_incr_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
O : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[2]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axaddr_offset_r_reg[1]\ : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
\wrap_second_len_r_reg[3]\ : out STD_LOGIC;
\axlen_cnt_reg[3]\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\axaddr_offset_r_reg[0]\ : out STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
m_valid_i0 : in STD_LOGIC;
\aresetn_d_reg[0]_0\ : in STD_LOGIC;
\m_payload_i_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
axaddr_offset_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep\ : in STD_LOGIC;
\wrap_second_len_r_reg[2]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\state_reg[1]_rep_0\ : in STD_LOGIC;
\state_reg[0]_rep\ : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
\state_reg[1]_rep_1\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end led_controller_design_auto_pc_0_axi_register_slice_v2_1_14_axic_register_slice;
architecture STRUCTURE of led_controller_design_auto_pc_0_axi_register_slice_v2_1_14_axic_register_slice is
signal \^q\ : STD_LOGIC_VECTOR ( 53 downto 0 );
signal \axaddr_incr[3]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_3__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_3__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_3__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_offset_r[1]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[3]_i_2__0_n_0\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[1]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^axlen_cnt_reg[3]\ : STD_LOGIC;
signal \m_payload_i[0]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[10]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[14]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[15]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[16]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[17]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[18]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[19]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[20]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[21]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[22]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[23]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[24]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[25]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[26]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[27]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[28]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[29]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[30]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[31]_i_2__0_n_0\ : STD_LOGIC;
signal \m_payload_i[32]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[33]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[34]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[35]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[36]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[38]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[39]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[44]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[45]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[46]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[47]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[50]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[51]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[52]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[53]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[54]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[55]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[56]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[57]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[58]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[59]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[60]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[61]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_1__0_n_0\ : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^s_axi_arready\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
signal si_rs_arlen : STD_LOGIC_VECTOR ( 3 to 3 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[52]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[54]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[55]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[56]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[57]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[58]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[59]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[60]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[61]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r[3]_i_2__0_n_0\ : STD_LOGIC;
signal \NLW_axaddr_incr_reg[11]_i_3__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_offset_r[1]_i_3\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \axaddr_offset_r[2]_i_2__0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__0\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__0\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__0\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__0\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__0\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__0\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__0\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__0\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__0\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__0\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__0\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__0\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__0\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__0\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__0\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__0\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__0\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__0\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__0\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__0\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__0\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__0\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_2__0\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__0\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__0\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__0\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__0\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__0\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__0\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__0\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__0\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[47]_i_1__0\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__0\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \m_payload_i[50]_i_1__0\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[51]_i_1__0\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[52]_i_1__0\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[53]_i_1__0\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[54]_i_1__0\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[55]_i_1__0\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[56]_i_1__0\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[57]_i_1__0\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[58]_i_1__0\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[59]_i_1__0\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__0\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \m_payload_i[60]_i_1__0\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[61]_i_1__0\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__0\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__0\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__0\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__0\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[3]_i_2__0\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[5]_i_1__0\ : label is "soft_lutpair21";
begin
Q(53 downto 0) <= \^q\(53 downto 0);
\axaddr_offset_r_reg[1]\ <= \^axaddr_offset_r_reg[1]\;
\axaddr_offset_r_reg[3]\(2 downto 0) <= \^axaddr_offset_r_reg[3]\(2 downto 0);
\axlen_cnt_reg[3]\ <= \^axlen_cnt_reg[3]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
s_axi_arready <= \^s_axi_arready\;
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
\aresetn_d_reg[1]_inv\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \aresetn_d_reg[0]_0\,
Q => \^m_valid_i_reg_0\,
R => '0'
);
\axaddr_incr[3]_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"2A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(36),
I2 => \^q\(35),
O => \axaddr_incr[3]_i_4__0_n_0\
);
\axaddr_incr[3]_i_5__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
O => \axaddr_incr[3]_i_5__0_n_0\
);
\axaddr_incr[3]_i_6__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \^q\(0),
I1 => \^q\(36),
I2 => \^q\(35),
O => \axaddr_incr[3]_i_6__0_n_0\
);
\axaddr_incr_reg[11]_i_3__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[7]_i_2__0_n_0\,
CO(3) => \NLW_axaddr_incr_reg[11]_i_3__0_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[11]_i_3__0_n_1\,
CO(1) => \axaddr_incr_reg[11]_i_3__0_n_2\,
CO(0) => \axaddr_incr_reg[11]_i_3__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => O(3 downto 0),
S(3 downto 0) => \^q\(11 downto 8)
);
\axaddr_incr_reg[3]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[3]_i_2__0_n_0\,
CO(2) => \axaddr_incr_reg[3]_i_2__0_n_1\,
CO(1) => \axaddr_incr_reg[3]_i_2__0_n_2\,
CO(0) => \axaddr_incr_reg[3]_i_2__0_n_3\,
CYINIT => '0',
DI(3) => \^q\(3),
DI(2) => \axaddr_incr[3]_i_4__0_n_0\,
DI(1) => \axaddr_incr[3]_i_5__0_n_0\,
DI(0) => \axaddr_incr[3]_i_6__0_n_0\,
O(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
S(3 downto 0) => \m_payload_i_reg[3]_0\(3 downto 0)
);
\axaddr_incr_reg[7]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[3]_i_2__0_n_0\,
CO(3) => \axaddr_incr_reg[7]_i_2__0_n_0\,
CO(2) => \axaddr_incr_reg[7]_i_2__0_n_1\,
CO(1) => \axaddr_incr_reg[7]_i_2__0_n_2\,
CO(0) => \axaddr_incr_reg[7]_i_2__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[7]\(3 downto 0),
S(3 downto 0) => \^q\(7 downto 4)
);
\axaddr_offset_r[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(35),
I3 => \^q\(2),
I4 => \^q\(36),
I5 => \^q\(0),
O => \axaddr_offset_r_reg[0]\
);
\axaddr_offset_r[1]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^axaddr_offset_r_reg[1]\,
O => \^axaddr_offset_r_reg[3]\(0)
);
\axaddr_offset_r[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"1FDF00001FDFFFFF"
)
port map (
I0 => \axaddr_offset_r[1]_i_3_n_0\,
I1 => \^q\(35),
I2 => \^q\(40),
I3 => \axaddr_offset_r[2]_i_3__0_n_0\,
I4 => \state_reg[1]_rep\,
I5 => \axaddr_offset_r_reg[3]_0\(0),
O => \^axaddr_offset_r_reg[1]\
);
\axaddr_offset_r[1]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(3),
I1 => \^q\(36),
I2 => \^q\(1),
O => \axaddr_offset_r[1]_i_3_n_0\
);
\axaddr_offset_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AC00FFFFAC000000"
)
port map (
I0 => \axaddr_offset_r[2]_i_2__0_n_0\,
I1 => \axaddr_offset_r[2]_i_3__0_n_0\,
I2 => \^q\(35),
I3 => \^q\(41),
I4 => \state_reg[1]_rep\,
I5 => \axaddr_offset_r_reg[3]_0\(1),
O => \^axaddr_offset_r_reg[3]\(1)
);
\axaddr_offset_r[2]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(3),
O => \axaddr_offset_r[2]_i_2__0_n_0\
);
\axaddr_offset_r[2]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(4),
I1 => \^q\(36),
I2 => \^q\(2),
O => \axaddr_offset_r[2]_i_3__0_n_0\
);
\axaddr_offset_r[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF8FF00000800"
)
port map (
I0 => si_rs_arlen(3),
I1 => \axaddr_offset_r[3]_i_2__0_n_0\,
I2 => \state_reg[1]_rep_0\,
I3 => \^s_ready_i_reg_0\,
I4 => \state_reg[0]_rep\,
I5 => \axaddr_offset_r_reg[3]_0\(2),
O => \^axaddr_offset_r_reg[3]\(2)
);
\axaddr_offset_r[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(6),
I1 => \^q\(4),
I2 => \^q\(35),
I3 => \^q\(5),
I4 => \^q\(36),
I5 => \^q\(3),
O => \axaddr_offset_r[3]_i_2__0_n_0\
);
\axlen_cnt[3]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => si_rs_arlen(3),
I1 => \state_reg[0]_rep\,
I2 => \^s_ready_i_reg_0\,
I3 => \state_reg[1]_rep_0\,
O => \^axlen_cnt_reg[3]\
);
\m_payload_i[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => \m_payload_i[0]_i_1__0_n_0\
);
\m_payload_i[10]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(10),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => \m_payload_i[10]_i_1__0_n_0\
);
\m_payload_i[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(11),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => \m_payload_i[11]_i_1__0_n_0\
);
\m_payload_i[12]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(12),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => \m_payload_i[12]_i_1__0_n_0\
);
\m_payload_i[13]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(13),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => \m_payload_i[13]_i_1__1_n_0\
);
\m_payload_i[14]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(14),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => \m_payload_i[14]_i_1__0_n_0\
);
\m_payload_i[15]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(15),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => \m_payload_i[15]_i_1__0_n_0\
);
\m_payload_i[16]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(16),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => \m_payload_i[16]_i_1__0_n_0\
);
\m_payload_i[17]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(17),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => \m_payload_i[17]_i_1__0_n_0\
);
\m_payload_i[18]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(18),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => \m_payload_i[18]_i_1__0_n_0\
);
\m_payload_i[19]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(19),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => \m_payload_i[19]_i_1__0_n_0\
);
\m_payload_i[1]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => \m_payload_i[1]_i_1__0_n_0\
);
\m_payload_i[20]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(20),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => \m_payload_i[20]_i_1__0_n_0\
);
\m_payload_i[21]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(21),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => \m_payload_i[21]_i_1__0_n_0\
);
\m_payload_i[22]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(22),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => \m_payload_i[22]_i_1__0_n_0\
);
\m_payload_i[23]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(23),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => \m_payload_i[23]_i_1__0_n_0\
);
\m_payload_i[24]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(24),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => \m_payload_i[24]_i_1__0_n_0\
);
\m_payload_i[25]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(25),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => \m_payload_i[25]_i_1__0_n_0\
);
\m_payload_i[26]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(26),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => \m_payload_i[26]_i_1__0_n_0\
);
\m_payload_i[27]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(27),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => \m_payload_i[27]_i_1__0_n_0\
);
\m_payload_i[28]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(28),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => \m_payload_i[28]_i_1__0_n_0\
);
\m_payload_i[29]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(29),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => \m_payload_i[29]_i_1__0_n_0\
);
\m_payload_i[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => \m_payload_i[2]_i_1__0_n_0\
);
\m_payload_i[30]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(30),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => \m_payload_i[30]_i_1__0_n_0\
);
\m_payload_i[31]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(31),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => \m_payload_i[31]_i_2__0_n_0\
);
\m_payload_i[32]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => \m_payload_i[32]_i_1__0_n_0\
);
\m_payload_i[33]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => \m_payload_i[33]_i_1__0_n_0\
);
\m_payload_i[34]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => \m_payload_i[34]_i_1__0_n_0\
);
\m_payload_i[35]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arsize(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => \m_payload_i[35]_i_1__0_n_0\
);
\m_payload_i[36]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arsize(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => \m_payload_i[36]_i_1__0_n_0\
);
\m_payload_i[38]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arburst(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => \m_payload_i[38]_i_1__0_n_0\
);
\m_payload_i[39]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arburst(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => \m_payload_i[39]_i_1__0_n_0\
);
\m_payload_i[3]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(3),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => \m_payload_i[3]_i_1__0_n_0\
);
\m_payload_i[44]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => \m_payload_i[44]_i_1__0_n_0\
);
\m_payload_i[45]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => \m_payload_i[45]_i_1__0_n_0\
);
\m_payload_i[46]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => \m_payload_i[46]_i_1__1_n_0\
);
\m_payload_i[47]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(3),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[47]\,
O => \m_payload_i[47]_i_1__0_n_0\
);
\m_payload_i[4]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(4),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => \m_payload_i[4]_i_1__0_n_0\
);
\m_payload_i[50]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[50]\,
O => \m_payload_i[50]_i_1__0_n_0\
);
\m_payload_i[51]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[51]\,
O => \m_payload_i[51]_i_1__0_n_0\
);
\m_payload_i[52]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[52]\,
O => \m_payload_i[52]_i_1__0_n_0\
);
\m_payload_i[53]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(3),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[53]\,
O => \m_payload_i[53]_i_1__0_n_0\
);
\m_payload_i[54]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(4),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[54]\,
O => \m_payload_i[54]_i_1__0_n_0\
);
\m_payload_i[55]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(5),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[55]\,
O => \m_payload_i[55]_i_1__0_n_0\
);
\m_payload_i[56]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(6),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[56]\,
O => \m_payload_i[56]_i_1__0_n_0\
);
\m_payload_i[57]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(7),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[57]\,
O => \m_payload_i[57]_i_1__0_n_0\
);
\m_payload_i[58]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(8),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[58]\,
O => \m_payload_i[58]_i_1__0_n_0\
);
\m_payload_i[59]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(9),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[59]\,
O => \m_payload_i[59]_i_1__0_n_0\
);
\m_payload_i[5]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(5),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => \m_payload_i[5]_i_1__0_n_0\
);
\m_payload_i[60]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(10),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[60]\,
O => \m_payload_i[60]_i_1__0_n_0\
);
\m_payload_i[61]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(11),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[61]\,
O => \m_payload_i[61]_i_1__0_n_0\
);
\m_payload_i[6]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(6),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => \m_payload_i[6]_i_1__0_n_0\
);
\m_payload_i[7]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(7),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => \m_payload_i[7]_i_1__0_n_0\
);
\m_payload_i[8]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(8),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => \m_payload_i[8]_i_1__0_n_0\
);
\m_payload_i[9]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(9),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => \m_payload_i[9]_i_1__0_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[0]_i_1__0_n_0\,
Q => \^q\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[10]_i_1__0_n_0\,
Q => \^q\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[11]_i_1__0_n_0\,
Q => \^q\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[12]_i_1__0_n_0\,
Q => \^q\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[13]_i_1__1_n_0\,
Q => \^q\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[14]_i_1__0_n_0\,
Q => \^q\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[15]_i_1__0_n_0\,
Q => \^q\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[16]_i_1__0_n_0\,
Q => \^q\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[17]_i_1__0_n_0\,
Q => \^q\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[18]_i_1__0_n_0\,
Q => \^q\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[19]_i_1__0_n_0\,
Q => \^q\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[1]_i_1__0_n_0\,
Q => \^q\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[20]_i_1__0_n_0\,
Q => \^q\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[21]_i_1__0_n_0\,
Q => \^q\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[22]_i_1__0_n_0\,
Q => \^q\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[23]_i_1__0_n_0\,
Q => \^q\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[24]_i_1__0_n_0\,
Q => \^q\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[25]_i_1__0_n_0\,
Q => \^q\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[26]_i_1__0_n_0\,
Q => \^q\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[27]_i_1__0_n_0\,
Q => \^q\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[28]_i_1__0_n_0\,
Q => \^q\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[29]_i_1__0_n_0\,
Q => \^q\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[2]_i_1__0_n_0\,
Q => \^q\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[30]_i_1__0_n_0\,
Q => \^q\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[31]_i_2__0_n_0\,
Q => \^q\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[32]_i_1__0_n_0\,
Q => \^q\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[33]_i_1__0_n_0\,
Q => \^q\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[34]_i_1__0_n_0\,
Q => \^q\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[35]_i_1__0_n_0\,
Q => \^q\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[36]_i_1__0_n_0\,
Q => \^q\(36),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[38]_i_1__0_n_0\,
Q => \^q\(37),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[39]_i_1__0_n_0\,
Q => \^q\(38),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[3]_i_1__0_n_0\,
Q => \^q\(3),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[44]_i_1__0_n_0\,
Q => \^q\(39),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[45]_i_1__0_n_0\,
Q => \^q\(40),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[46]_i_1__1_n_0\,
Q => \^q\(41),
R => '0'
);
\m_payload_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[47]_i_1__0_n_0\,
Q => si_rs_arlen(3),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[4]_i_1__0_n_0\,
Q => \^q\(4),
R => '0'
);
\m_payload_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[50]_i_1__0_n_0\,
Q => \^q\(42),
R => '0'
);
\m_payload_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[51]_i_1__0_n_0\,
Q => \^q\(43),
R => '0'
);
\m_payload_i_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[52]_i_1__0_n_0\,
Q => \^q\(44),
R => '0'
);
\m_payload_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[53]_i_1__0_n_0\,
Q => \^q\(45),
R => '0'
);
\m_payload_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[54]_i_1__0_n_0\,
Q => \^q\(46),
R => '0'
);
\m_payload_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[55]_i_1__0_n_0\,
Q => \^q\(47),
R => '0'
);
\m_payload_i_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[56]_i_1__0_n_0\,
Q => \^q\(48),
R => '0'
);
\m_payload_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[57]_i_1__0_n_0\,
Q => \^q\(49),
R => '0'
);
\m_payload_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[58]_i_1__0_n_0\,
Q => \^q\(50),
R => '0'
);
\m_payload_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[59]_i_1__0_n_0\,
Q => \^q\(51),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[5]_i_1__0_n_0\,
Q => \^q\(5),
R => '0'
);
\m_payload_i_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[60]_i_1__0_n_0\,
Q => \^q\(52),
R => '0'
);
\m_payload_i_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[61]_i_1__0_n_0\,
Q => \^q\(53),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[6]_i_1__0_n_0\,
Q => \^q\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[7]_i_1__0_n_0\,
Q => \^q\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[8]_i_1__0_n_0\,
Q => \^q\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[9]_i_1__0_n_0\,
Q => \^q\(9),
R => '0'
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^s_ready_i_reg_0\,
R => \^m_valid_i_reg_0\
);
\next_pending_r_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA8"
)
port map (
I0 => \state_reg[1]_rep\,
I1 => \^q\(39),
I2 => si_rs_arlen(3),
I3 => \^q\(40),
I4 => \^q\(41),
O => next_pending_r_reg
);
\s_ready_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F444FFFF"
)
port map (
I0 => s_axi_arvalid,
I1 => \^s_axi_arready\,
I2 => \state_reg[1]_rep_0\,
I3 => \state_reg[0]_rep\,
I4 => \^s_ready_i_reg_0\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^s_axi_arready\,
R => \aresetn_d_reg[0]\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arprot(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arprot(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arprot(2),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arsize(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arsize(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arburst(0),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arburst(1),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(0),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(1),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(2),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(3),
Q => \skid_buffer_reg_n_0_[47]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(0),
Q => \skid_buffer_reg_n_0_[50]\,
R => '0'
);
\skid_buffer_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(1),
Q => \skid_buffer_reg_n_0_[51]\,
R => '0'
);
\skid_buffer_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(2),
Q => \skid_buffer_reg_n_0_[52]\,
R => '0'
);
\skid_buffer_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(3),
Q => \skid_buffer_reg_n_0_[53]\,
R => '0'
);
\skid_buffer_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(4),
Q => \skid_buffer_reg_n_0_[54]\,
R => '0'
);
\skid_buffer_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(5),
Q => \skid_buffer_reg_n_0_[55]\,
R => '0'
);
\skid_buffer_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(6),
Q => \skid_buffer_reg_n_0_[56]\,
R => '0'
);
\skid_buffer_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(7),
Q => \skid_buffer_reg_n_0_[57]\,
R => '0'
);
\skid_buffer_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(8),
Q => \skid_buffer_reg_n_0_[58]\,
R => '0'
);
\skid_buffer_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(9),
Q => \skid_buffer_reg_n_0_[59]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(10),
Q => \skid_buffer_reg_n_0_[60]\,
R => '0'
);
\skid_buffer_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(11),
Q => \skid_buffer_reg_n_0_[61]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
\wrap_boundary_axaddr_r[0]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA8A"
)
port map (
I0 => \^q\(0),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(0)
);
\wrap_boundary_axaddr_r[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8A888AAA"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
I4 => \^q\(40),
O => \wrap_boundary_axaddr_r_reg[6]\(1)
);
\wrap_boundary_axaddr_r[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888082AAAAA082A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(35),
I2 => \^q\(40),
I3 => \^q\(41),
I4 => \^q\(36),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(2)
);
\wrap_boundary_axaddr_r[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"020202A2A2A202A2"
)
port map (
I0 => \^q\(3),
I1 => \wrap_boundary_axaddr_r[3]_i_2__0_n_0\,
I2 => \^q\(36),
I3 => \^q\(40),
I4 => \^q\(35),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(3)
);
\wrap_boundary_axaddr_r[3]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(41),
I1 => \^q\(35),
I2 => si_rs_arlen(3),
O => \wrap_boundary_axaddr_r[3]_i_2__0_n_0\
);
\wrap_boundary_axaddr_r[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"002AA02A0A2AAA2A"
)
port map (
I0 => \^q\(4),
I1 => si_rs_arlen(3),
I2 => \^q\(35),
I3 => \^q\(36),
I4 => \^q\(40),
I5 => \^q\(41),
O => \wrap_boundary_axaddr_r_reg[6]\(4)
);
\wrap_boundary_axaddr_r[5]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"2A222AAA"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(41),
I3 => \^q\(35),
I4 => si_rs_arlen(3),
O => \wrap_boundary_axaddr_r_reg[6]\(5)
);
\wrap_boundary_axaddr_r[6]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"2AAA"
)
port map (
I0 => \^q\(6),
I1 => \^q\(36),
I2 => \^q\(35),
I3 => si_rs_arlen(3),
O => \wrap_boundary_axaddr_r_reg[6]\(6)
);
\wrap_second_len_r[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0EF0FFFF0EF00000"
)
port map (
I0 => \^axaddr_offset_r_reg[3]\(1),
I1 => \^axaddr_offset_r_reg[3]\(2),
I2 => axaddr_offset_0(0),
I3 => \^axaddr_offset_r_reg[1]\,
I4 => \state_reg[1]_rep\,
I5 => \wrap_second_len_r_reg[2]_0\(0),
O => \wrap_second_len_r_reg[2]\(0)
);
\wrap_second_len_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA4AFFFFAA4A0000"
)
port map (
I0 => \^axaddr_offset_r_reg[3]\(1),
I1 => \^axaddr_offset_r_reg[3]\(2),
I2 => \^axaddr_offset_r_reg[1]\,
I3 => axaddr_offset_0(0),
I4 => \state_reg[1]_rep\,
I5 => \wrap_second_len_r_reg[2]_0\(1),
O => \wrap_second_len_r_reg[2]\(1)
);
\wrap_second_len_r[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EEE222E2"
)
port map (
I0 => \axaddr_offset_r[2]_i_2__0_n_0\,
I1 => \^q\(35),
I2 => \^q\(4),
I3 => \^q\(36),
I4 => \^q\(6),
I5 => \^axlen_cnt_reg[3]\,
O => \wrap_second_len_r_reg[3]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity led_controller_design_auto_pc_0_axi_register_slice_v2_1_14_axic_register_slice_0 is
port (
s_axi_awready : out STD_LOGIC;
s_ready_i_reg_0 : out STD_LOGIC;
m_valid_i_reg_0 : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[1]\ : out STD_LOGIC;
axaddr_incr : out STD_LOGIC_VECTOR ( 11 downto 0 );
Q : out STD_LOGIC_VECTOR ( 54 downto 0 );
wrap_second_len : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axaddr_offset_r_reg[1]\ : out STD_LOGIC;
\axaddr_offset_r_reg[3]\ : out STD_LOGIC;
axaddr_offset : out STD_LOGIC_VECTOR ( 1 downto 0 );
\axlen_cnt_reg[3]\ : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\aresetn_d_reg[1]_inv\ : out STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[1]_inv_0\ : in STD_LOGIC;
aresetn : in STD_LOGIC;
S : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[1]_rep\ : in STD_LOGIC;
\wrap_second_len_r_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
b_push : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of led_controller_design_auto_pc_0_axi_register_slice_v2_1_14_axic_register_slice_0 : entity is "axi_register_slice_v2_1_14_axic_register_slice";
end led_controller_design_auto_pc_0_axi_register_slice_v2_1_14_axic_register_slice_0;
architecture STRUCTURE of led_controller_design_auto_pc_0_axi_register_slice_v2_1_14_axic_register_slice_0 is
signal \^q\ : STD_LOGIC_VECTOR ( 54 downto 0 );
signal \aresetn_d_reg_n_0_[0]\ : STD_LOGIC;
signal \axaddr_incr[3]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_3_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_3_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_3_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_2_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_2_n_3\ : STD_LOGIC;
signal \axaddr_offset_r[0]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[0]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[1]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[3]_i_2_n_0\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[1]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC;
signal \^axlen_cnt_reg[3]\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^s_axi_awready\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 61 downto 0 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[52]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[54]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[55]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[56]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[57]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[58]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[59]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[60]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[61]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r[3]_i_2_n_0\ : STD_LOGIC;
signal \wrap_cnt_r[3]_i_2_n_0\ : STD_LOGIC;
signal \wrap_cnt_r[3]_i_3_n_0\ : STD_LOGIC;
signal \^wrap_second_len\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \wrap_second_len_r[0]_i_2_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_3_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_4_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_5_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[3]_i_2_n_0\ : STD_LOGIC;
signal \^wrap_second_len_r_reg[1]\ : STD_LOGIC;
signal \NLW_axaddr_incr_reg[11]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_offset_r[0]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \axaddr_offset_r[2]_i_3\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \axaddr_offset_r[2]_i_4\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \axlen_cnt[3]_i_3\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[0]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__0\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_2\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__0\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_payload_i[47]_i_1\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \m_payload_i[50]_i_1\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_payload_i[51]_i_1\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_payload_i[52]_i_1\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[53]_i_1\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[54]_i_1\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[55]_i_1\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[56]_i_1\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[57]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_payload_i[58]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_payload_i[59]_i_1\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \m_payload_i[60]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[61]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[3]_i_2\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[5]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \wrap_cnt_r[2]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_2\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \wrap_second_len_r[0]_i_5\ : label is "soft_lutpair53";
begin
Q(54 downto 0) <= \^q\(54 downto 0);
\axaddr_offset_r_reg[1]\ <= \^axaddr_offset_r_reg[1]\;
\axaddr_offset_r_reg[3]\ <= \^axaddr_offset_r_reg[3]\;
\axlen_cnt_reg[3]\ <= \^axlen_cnt_reg[3]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
s_axi_awready <= \^s_axi_awready\;
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
wrap_second_len(2 downto 0) <= \^wrap_second_len\(2 downto 0);
\wrap_second_len_r_reg[1]\ <= \^wrap_second_len_r_reg[1]\;
\aresetn_d[1]_inv_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \aresetn_d_reg_n_0_[0]\,
I1 => aresetn,
O => \aresetn_d_reg[1]_inv\
);
\aresetn_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => aresetn,
Q => \aresetn_d_reg_n_0_[0]\,
R => '0'
);
\axaddr_incr[3]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"2A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(36),
I2 => \^q\(35),
O => \axaddr_incr[3]_i_4_n_0\
);
\axaddr_incr[3]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
O => \axaddr_incr[3]_i_5_n_0\
);
\axaddr_incr[3]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \^q\(0),
I1 => \^q\(36),
I2 => \^q\(35),
O => \axaddr_incr[3]_i_6_n_0\
);
\axaddr_incr_reg[11]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[7]_i_2_n_0\,
CO(3) => \NLW_axaddr_incr_reg[11]_i_3_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[11]_i_3_n_1\,
CO(1) => \axaddr_incr_reg[11]_i_3_n_2\,
CO(0) => \axaddr_incr_reg[11]_i_3_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => axaddr_incr(11 downto 8),
S(3 downto 0) => \^q\(11 downto 8)
);
\axaddr_incr_reg[3]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[3]_i_2_n_0\,
CO(2) => \axaddr_incr_reg[3]_i_2_n_1\,
CO(1) => \axaddr_incr_reg[3]_i_2_n_2\,
CO(0) => \axaddr_incr_reg[3]_i_2_n_3\,
CYINIT => '0',
DI(3) => \^q\(3),
DI(2) => \axaddr_incr[3]_i_4_n_0\,
DI(1) => \axaddr_incr[3]_i_5_n_0\,
DI(0) => \axaddr_incr[3]_i_6_n_0\,
O(3 downto 0) => axaddr_incr(3 downto 0),
S(3 downto 0) => S(3 downto 0)
);
\axaddr_incr_reg[7]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[3]_i_2_n_0\,
CO(3) => \axaddr_incr_reg[7]_i_2_n_0\,
CO(2) => \axaddr_incr_reg[7]_i_2_n_1\,
CO(1) => \axaddr_incr_reg[7]_i_2_n_2\,
CO(0) => \axaddr_incr_reg[7]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => axaddr_incr(7 downto 4),
S(3 downto 0) => \^q\(7 downto 4)
);
\axaddr_offset_r[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \axaddr_offset_r[0]_i_2_n_0\,
O => axaddr_offset(0)
);
\axaddr_offset_r[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000700FFFFF7FF"
)
port map (
I0 => \^q\(39),
I1 => \axaddr_offset_r[0]_i_3_n_0\,
I2 => \state_reg[1]\(1),
I3 => \^m_valid_i_reg_0\,
I4 => \state_reg[1]\(0),
I5 => \axaddr_offset_r_reg[3]_0\(0),
O => \axaddr_offset_r[0]_i_2_n_0\
);
\axaddr_offset_r[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(35),
I3 => \^q\(2),
I4 => \^q\(36),
I5 => \^q\(0),
O => \axaddr_offset_r[0]_i_3_n_0\
);
\axaddr_offset_r[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF8FF00000800"
)
port map (
I0 => \^q\(40),
I1 => \axaddr_offset_r[1]_i_2__0_n_0\,
I2 => \state_reg[1]\(1),
I3 => \^m_valid_i_reg_0\,
I4 => \state_reg[1]\(0),
I5 => \axaddr_offset_r_reg[3]_0\(1),
O => \^axaddr_offset_r_reg[1]\
);
\axaddr_offset_r[1]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(4),
I1 => \^q\(2),
I2 => \^q\(35),
I3 => \^q\(3),
I4 => \^q\(36),
I5 => \^q\(1),
O => \axaddr_offset_r[1]_i_2__0_n_0\
);
\axaddr_offset_r[2]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \axaddr_offset_r[2]_i_2_n_0\,
O => axaddr_offset(1)
);
\axaddr_offset_r[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"03FFF3FF55555555"
)
port map (
I0 => \axaddr_offset_r_reg[3]_0\(2),
I1 => \axaddr_offset_r[2]_i_3_n_0\,
I2 => \^q\(35),
I3 => \^q\(41),
I4 => \axaddr_offset_r[2]_i_4_n_0\,
I5 => \state_reg[1]_rep\,
O => \axaddr_offset_r[2]_i_2_n_0\
);
\axaddr_offset_r[2]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(4),
I1 => \^q\(36),
I2 => \^q\(2),
O => \axaddr_offset_r[2]_i_3_n_0\
);
\axaddr_offset_r[2]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(3),
O => \axaddr_offset_r[2]_i_4_n_0\
);
\axaddr_offset_r[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF8FF00000800"
)
port map (
I0 => \^q\(42),
I1 => \axaddr_offset_r[3]_i_2_n_0\,
I2 => \state_reg[1]\(1),
I3 => \^m_valid_i_reg_0\,
I4 => \state_reg[1]\(0),
I5 => \axaddr_offset_r_reg[3]_0\(3),
O => \^axaddr_offset_r_reg[3]\
);
\axaddr_offset_r[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(6),
I1 => \^q\(4),
I2 => \^q\(35),
I3 => \^q\(5),
I4 => \^q\(36),
I5 => \^q\(3),
O => \axaddr_offset_r[3]_i_2_n_0\
);
\axlen_cnt[3]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => \^q\(42),
I1 => \state_reg[1]\(0),
I2 => \^m_valid_i_reg_0\,
I3 => \state_reg[1]\(1),
O => \^axlen_cnt_reg[3]\
);
\m_payload_i[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\m_payload_i[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(10),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(11),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(12),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[13]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(13),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(14),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(15),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(16),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(17),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(18),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(19),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => skid_buffer(1)
);
\m_payload_i[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(20),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(21),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(22),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(23),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(24),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(25),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(26),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(27),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(28),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(29),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => skid_buffer(2)
);
\m_payload_i[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(30),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[31]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(31),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[32]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awprot(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[33]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awprot(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[34]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awprot(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awsize(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awsize(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[38]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awburst(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awburst(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(3),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[44]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i[47]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(3),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[47]\,
O => skid_buffer(47)
);
\m_payload_i[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(4),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[50]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[50]\,
O => skid_buffer(50)
);
\m_payload_i[51]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[51]\,
O => skid_buffer(51)
);
\m_payload_i[52]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[52]\,
O => skid_buffer(52)
);
\m_payload_i[53]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(3),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[53]\,
O => skid_buffer(53)
);
\m_payload_i[54]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(4),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[54]\,
O => skid_buffer(54)
);
\m_payload_i[55]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(5),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[55]\,
O => skid_buffer(55)
);
\m_payload_i[56]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(6),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[56]\,
O => skid_buffer(56)
);
\m_payload_i[57]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(7),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[57]\,
O => skid_buffer(57)
);
\m_payload_i[58]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(8),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[58]\,
O => skid_buffer(58)
);
\m_payload_i[59]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(9),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[59]\,
O => skid_buffer(59)
);
\m_payload_i[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(5),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[60]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(10),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[60]\,
O => skid_buffer(60)
);
\m_payload_i[61]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(11),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[61]\,
O => skid_buffer(61)
);
\m_payload_i[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(6),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(7),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(8),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(9),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(0),
Q => \^q\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(10),
Q => \^q\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(11),
Q => \^q\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(12),
Q => \^q\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(13),
Q => \^q\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(14),
Q => \^q\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(15),
Q => \^q\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(16),
Q => \^q\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(17),
Q => \^q\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(18),
Q => \^q\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(19),
Q => \^q\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(1),
Q => \^q\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(20),
Q => \^q\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(21),
Q => \^q\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(22),
Q => \^q\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(23),
Q => \^q\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(24),
Q => \^q\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(25),
Q => \^q\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(26),
Q => \^q\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(27),
Q => \^q\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(28),
Q => \^q\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(29),
Q => \^q\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(2),
Q => \^q\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(30),
Q => \^q\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(31),
Q => \^q\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(32),
Q => \^q\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(33),
Q => \^q\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(34),
Q => \^q\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(35),
Q => \^q\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(36),
Q => \^q\(36),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(38),
Q => \^q\(37),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(39),
Q => \^q\(38),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(3),
Q => \^q\(3),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(44),
Q => \^q\(39),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(45),
Q => \^q\(40),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(46),
Q => \^q\(41),
R => '0'
);
\m_payload_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(47),
Q => \^q\(42),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(4),
Q => \^q\(4),
R => '0'
);
\m_payload_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(50),
Q => \^q\(43),
R => '0'
);
\m_payload_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(51),
Q => \^q\(44),
R => '0'
);
\m_payload_i_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(52),
Q => \^q\(45),
R => '0'
);
\m_payload_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(53),
Q => \^q\(46),
R => '0'
);
\m_payload_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(54),
Q => \^q\(47),
R => '0'
);
\m_payload_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(55),
Q => \^q\(48),
R => '0'
);
\m_payload_i_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(56),
Q => \^q\(49),
R => '0'
);
\m_payload_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(57),
Q => \^q\(50),
R => '0'
);
\m_payload_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(58),
Q => \^q\(51),
R => '0'
);
\m_payload_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(59),
Q => \^q\(52),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(5),
Q => \^q\(5),
R => '0'
);
\m_payload_i_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(60),
Q => \^q\(53),
R => '0'
);
\m_payload_i_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(61),
Q => \^q\(54),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(6),
Q => \^q\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(7),
Q => \^q\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(8),
Q => \^q\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(9),
Q => \^q\(9),
R => '0'
);
m_valid_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => b_push,
I1 => \^m_valid_i_reg_0\,
I2 => s_axi_awvalid,
I3 => \^s_axi_awready\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^m_valid_i_reg_0\,
R => \aresetn_d_reg[1]_inv_0\
);
next_pending_r_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \^q\(41),
I1 => \^q\(40),
I2 => \^q\(42),
I3 => \^q\(39),
O => next_pending_r_reg
);
\s_ready_i_i_1__1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \aresetn_d_reg_n_0_[0]\,
O => \^s_ready_i_reg_0\
);
s_ready_i_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => s_axi_awvalid,
I1 => \^s_axi_awready\,
I2 => b_push,
I3 => \^m_valid_i_reg_0\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^s_axi_awready\,
R => \^s_ready_i_reg_0\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awprot(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awprot(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awprot(2),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awsize(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awsize(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awburst(0),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awburst(1),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(0),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(1),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(2),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(3),
Q => \skid_buffer_reg_n_0_[47]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(0),
Q => \skid_buffer_reg_n_0_[50]\,
R => '0'
);
\skid_buffer_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(1),
Q => \skid_buffer_reg_n_0_[51]\,
R => '0'
);
\skid_buffer_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(2),
Q => \skid_buffer_reg_n_0_[52]\,
R => '0'
);
\skid_buffer_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(3),
Q => \skid_buffer_reg_n_0_[53]\,
R => '0'
);
\skid_buffer_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(4),
Q => \skid_buffer_reg_n_0_[54]\,
R => '0'
);
\skid_buffer_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(5),
Q => \skid_buffer_reg_n_0_[55]\,
R => '0'
);
\skid_buffer_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(6),
Q => \skid_buffer_reg_n_0_[56]\,
R => '0'
);
\skid_buffer_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(7),
Q => \skid_buffer_reg_n_0_[57]\,
R => '0'
);
\skid_buffer_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(8),
Q => \skid_buffer_reg_n_0_[58]\,
R => '0'
);
\skid_buffer_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(9),
Q => \skid_buffer_reg_n_0_[59]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(10),
Q => \skid_buffer_reg_n_0_[60]\,
R => '0'
);
\skid_buffer_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(11),
Q => \skid_buffer_reg_n_0_[61]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
\wrap_boundary_axaddr_r[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA8A"
)
port map (
I0 => \^q\(0),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(0)
);
\wrap_boundary_axaddr_r[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8A888AAA"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
I4 => \^q\(40),
O => \wrap_boundary_axaddr_r_reg[6]\(1)
);
\wrap_boundary_axaddr_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0A002A2AAAA02A2"
)
port map (
I0 => \^q\(2),
I1 => \^q\(41),
I2 => \^q\(35),
I3 => \^q\(40),
I4 => \^q\(36),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(2)
);
\wrap_boundary_axaddr_r[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"020202A2A2A202A2"
)
port map (
I0 => \^q\(3),
I1 => \wrap_boundary_axaddr_r[3]_i_2_n_0\,
I2 => \^q\(36),
I3 => \^q\(40),
I4 => \^q\(35),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(3)
);
\wrap_boundary_axaddr_r[3]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(41),
I1 => \^q\(35),
I2 => \^q\(42),
O => \wrap_boundary_axaddr_r[3]_i_2_n_0\
);
\wrap_boundary_axaddr_r[4]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"002A0A2AA02AAA2A"
)
port map (
I0 => \^q\(4),
I1 => \^q\(42),
I2 => \^q\(35),
I3 => \^q\(36),
I4 => \^q\(41),
I5 => \^q\(40),
O => \wrap_boundary_axaddr_r_reg[6]\(4)
);
\wrap_boundary_axaddr_r[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"2A222AAA"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(41),
I3 => \^q\(35),
I4 => \^q\(42),
O => \wrap_boundary_axaddr_r_reg[6]\(5)
);
\wrap_boundary_axaddr_r[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2AAA"
)
port map (
I0 => \^q\(6),
I1 => \^q\(36),
I2 => \^q\(35),
I3 => \^q\(42),
O => \wrap_boundary_axaddr_r_reg[6]\(6)
);
\wrap_cnt_r[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"DDDDD8DDAAAAA8AA"
)
port map (
I0 => \wrap_second_len_r[0]_i_2_n_0\,
I1 => \wrap_second_len_r[0]_i_3_n_0\,
I2 => \state_reg[1]\(1),
I3 => \^m_valid_i_reg_0\,
I4 => \state_reg[1]\(0),
I5 => \wrap_second_len_r_reg[3]\(0),
O => D(0)
);
\wrap_cnt_r[1]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^wrap_second_len_r_reg[1]\,
I1 => \wrap_cnt_r[3]_i_2_n_0\,
O => D(1)
);
\wrap_cnt_r[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \^wrap_second_len\(1),
I1 => \wrap_cnt_r[3]_i_2_n_0\,
I2 => \^wrap_second_len_r_reg[1]\,
O => D(2)
);
\wrap_cnt_r[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A6AA"
)
port map (
I0 => \^wrap_second_len\(2),
I1 => \^wrap_second_len_r_reg[1]\,
I2 => \wrap_cnt_r[3]_i_2_n_0\,
I3 => \^wrap_second_len\(1),
O => D(3)
);
\wrap_cnt_r[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAABAAA"
)
port map (
I0 => \wrap_cnt_r[3]_i_3_n_0\,
I1 => \^axaddr_offset_r_reg[1]\,
I2 => \axaddr_offset_r[0]_i_2_n_0\,
I3 => \axaddr_offset_r[2]_i_2_n_0\,
I4 => \^axaddr_offset_r_reg[3]\,
O => \wrap_cnt_r[3]_i_2_n_0\
);
\wrap_cnt_r[3]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000800FFFFF8FF"
)
port map (
I0 => \^q\(39),
I1 => \axaddr_offset_r[0]_i_3_n_0\,
I2 => \state_reg[1]\(1),
I3 => \^m_valid_i_reg_0\,
I4 => \state_reg[1]\(0),
I5 => \wrap_second_len_r_reg[3]\(0),
O => \wrap_cnt_r[3]_i_3_n_0\
);
\wrap_second_len_r[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000CCCCCACC"
)
port map (
I0 => \wrap_second_len_r[0]_i_2_n_0\,
I1 => \wrap_second_len_r_reg[3]\(0),
I2 => \state_reg[1]\(0),
I3 => \^m_valid_i_reg_0\,
I4 => \state_reg[1]\(1),
I5 => \wrap_second_len_r[0]_i_3_n_0\,
O => \^wrap_second_len\(0)
);
\wrap_second_len_r[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFF2FFFFFF"
)
port map (
I0 => \axaddr_offset_r_reg[3]_0\(3),
I1 => \state_reg[1]_rep\,
I2 => \wrap_second_len_r[3]_i_2_n_0\,
I3 => \axaddr_offset_r[2]_i_2_n_0\,
I4 => \axaddr_offset_r[0]_i_2_n_0\,
I5 => \^axaddr_offset_r_reg[1]\,
O => \wrap_second_len_r[0]_i_2_n_0\
);
\wrap_second_len_r[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFE200E2"
)
port map (
I0 => \^q\(0),
I1 => \^q\(36),
I2 => \^q\(2),
I3 => \^q\(35),
I4 => \wrap_second_len_r[0]_i_4_n_0\,
I5 => \wrap_second_len_r[0]_i_5_n_0\,
O => \wrap_second_len_r[0]_i_3_n_0\
);
\wrap_second_len_r[0]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(3),
I1 => \^q\(36),
I2 => \^q\(1),
O => \wrap_second_len_r[0]_i_4_n_0\
);
\wrap_second_len_r[0]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => \^q\(39),
I1 => \state_reg[1]\(0),
I2 => \^m_valid_i_reg_0\,
I3 => \state_reg[1]\(1),
O => \wrap_second_len_r[0]_i_5_n_0\
);
\wrap_second_len_r[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"2EE22E222EE22EE2"
)
port map (
I0 => \wrap_second_len_r_reg[3]\(1),
I1 => \state_reg[1]_rep\,
I2 => \axaddr_offset_r[0]_i_2_n_0\,
I3 => \^axaddr_offset_r_reg[1]\,
I4 => \^axaddr_offset_r_reg[3]\,
I5 => \axaddr_offset_r[2]_i_2_n_0\,
O => \^wrap_second_len_r_reg[1]\
);
\wrap_second_len_r[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"08F3FFFF08F30000"
)
port map (
I0 => \^axaddr_offset_r_reg[3]\,
I1 => \axaddr_offset_r[0]_i_2_n_0\,
I2 => \^axaddr_offset_r_reg[1]\,
I3 => \axaddr_offset_r[2]_i_2_n_0\,
I4 => \state_reg[1]_rep\,
I5 => \wrap_second_len_r_reg[3]\(2),
O => \^wrap_second_len\(1)
);
\wrap_second_len_r[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BF00FFFFBF00BF00"
)
port map (
I0 => \^axaddr_offset_r_reg[1]\,
I1 => \axaddr_offset_r[0]_i_2_n_0\,
I2 => \axaddr_offset_r[2]_i_2_n_0\,
I3 => \wrap_second_len_r[3]_i_2_n_0\,
I4 => \state_reg[1]_rep\,
I5 => \wrap_second_len_r_reg[3]\(3),
O => \^wrap_second_len\(2)
);
\wrap_second_len_r[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EEE222E2"
)
port map (
I0 => \axaddr_offset_r[2]_i_4_n_0\,
I1 => \^q\(35),
I2 => \^q\(4),
I3 => \^q\(36),
I4 => \^q\(6),
I5 => \^axlen_cnt_reg[3]\,
O => \wrap_second_len_r[3]_i_2_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \led_controller_design_auto_pc_0_axi_register_slice_v2_1_14_axic_register_slice__parameterized1\ is
port (
s_axi_bvalid : out STD_LOGIC;
\skid_buffer_reg[0]_0\ : out STD_LOGIC;
shandshake : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]_inv\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
si_rs_bvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\s_bresp_acc_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \led_controller_design_auto_pc_0_axi_register_slice_v2_1_14_axic_register_slice__parameterized1\ : entity is "axi_register_slice_v2_1_14_axic_register_slice";
end \led_controller_design_auto_pc_0_axi_register_slice_v2_1_14_axic_register_slice__parameterized1\;
architecture STRUCTURE of \led_controller_design_auto_pc_0_axi_register_slice_v2_1_14_axic_register_slice__parameterized1\ is
signal \m_payload_i[0]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[10]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_1__1_n_0\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal \^skid_buffer_reg[0]_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_payload_i[0]_i_1__1\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__1\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__1\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__1\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_2\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__1\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__1\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__1\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__1\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__1\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__1\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__1\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__1\ : label is "soft_lutpair85";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__1\ : label is "soft_lutpair85";
attribute SOFT_HLUTNM of s_ready_i_i_1 : label is "soft_lutpair82";
attribute SOFT_HLUTNM of shandshake_r_i_1 : label is "soft_lutpair82";
begin
s_axi_bvalid <= \^s_axi_bvalid\;
\skid_buffer_reg[0]_0\ <= \^skid_buffer_reg[0]_0\;
\m_payload_i[0]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \s_bresp_acc_reg[1]\(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => \m_payload_i[0]_i_1__1_n_0\
);
\m_payload_i[10]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(8),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => \m_payload_i[10]_i_1__1_n_0\
);
\m_payload_i[11]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(9),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => \m_payload_i[11]_i_1__1_n_0\
);
\m_payload_i[12]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(10),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => \m_payload_i[12]_i_1__1_n_0\
);
\m_payload_i[13]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
O => p_1_in
);
\m_payload_i[13]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(11),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => \m_payload_i[13]_i_2_n_0\
);
\m_payload_i[1]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \s_bresp_acc_reg[1]\(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => \m_payload_i[1]_i_1__1_n_0\
);
\m_payload_i[2]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => \m_payload_i[2]_i_1__1_n_0\
);
\m_payload_i[3]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => \m_payload_i[3]_i_1__1_n_0\
);
\m_payload_i[4]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(2),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => \m_payload_i[4]_i_1__1_n_0\
);
\m_payload_i[5]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(3),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => \m_payload_i[5]_i_1__1_n_0\
);
\m_payload_i[6]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(4),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => \m_payload_i[6]_i_1__1_n_0\
);
\m_payload_i[7]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(5),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => \m_payload_i[7]_i_1__1_n_0\
);
\m_payload_i[8]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(6),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => \m_payload_i[8]_i_1__1_n_0\
);
\m_payload_i[9]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(7),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => \m_payload_i[9]_i_1__1_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[0]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[10]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[11]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[12]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[13]_i_2_n_0\,
Q => \s_axi_bid[11]\(13),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[1]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(1),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[2]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(2),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[3]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(3),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[4]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[5]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[6]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[7]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[8]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[9]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(9),
R => '0'
);
\m_valid_i_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
I2 => si_rs_bvalid,
I3 => \^skid_buffer_reg[0]_0\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^s_axi_bvalid\,
R => \aresetn_d_reg[1]_inv\
);
s_ready_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => si_rs_bvalid,
I1 => \^skid_buffer_reg[0]_0\,
I2 => s_axi_bready,
I3 => \^s_axi_bvalid\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^skid_buffer_reg[0]_0\,
R => \aresetn_d_reg[0]\
);
shandshake_r_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^skid_buffer_reg[0]_0\,
I1 => si_rs_bvalid,
O => shandshake
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \s_bresp_acc_reg[1]\(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(8),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(9),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(10),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(11),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \s_bresp_acc_reg[1]\(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(0),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(1),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(2),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(3),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(4),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(5),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(6),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(7),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \led_controller_design_auto_pc_0_axi_register_slice_v2_1_14_axic_register_slice__parameterized2\ is
port (
s_axi_rvalid : out STD_LOGIC;
\skid_buffer_reg[0]_0\ : out STD_LOGIC;
\cnt_read_reg[0]_rep__1\ : out STD_LOGIC;
\s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\aresetn_d_reg[1]_inv\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
\cnt_read_reg[3]_rep__0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
r_push_r_reg : in STD_LOGIC_VECTOR ( 12 downto 0 );
\cnt_read_reg[4]\ : in STD_LOGIC_VECTOR ( 33 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \led_controller_design_auto_pc_0_axi_register_slice_v2_1_14_axic_register_slice__parameterized2\ : entity is "axi_register_slice_v2_1_14_axic_register_slice";
end \led_controller_design_auto_pc_0_axi_register_slice_v2_1_14_axic_register_slice__parameterized2\;
architecture STRUCTURE of \led_controller_design_auto_pc_0_axi_register_slice_v2_1_14_axic_register_slice__parameterized2\ is
signal \m_payload_i[0]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[10]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[14]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[15]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[16]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[17]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[18]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[19]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[20]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[21]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[22]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[23]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[24]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[25]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[26]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[27]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[28]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[29]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[30]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[31]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[32]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[33]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[34]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[35]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[36]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[37]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[38]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[39]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[40]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[41]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[42]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[43]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[44]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[45]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[46]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_1__2_n_0\ : STD_LOGIC;
signal \m_valid_i_i_1__2_n_0\ : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
signal \s_ready_i_i_1__2_n_0\ : STD_LOGIC;
signal \^skid_buffer_reg[0]_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[3]_i_2\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__2\ : label is "soft_lutpair109";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__2\ : label is "soft_lutpair108";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__2\ : label is "soft_lutpair108";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__2\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__1\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__1\ : label is "soft_lutpair106";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__1\ : label is "soft_lutpair106";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__1\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__1\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__1\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__2\ : label is "soft_lutpair113";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__1\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__1\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__1\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__1\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__1\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__1\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__1\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__1\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__1\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__1\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__2\ : label is "soft_lutpair113";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__1\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__1\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__1\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__1\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__1\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__1\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__1\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__1\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__1\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__2\ : label is "soft_lutpair112";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__1\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__1\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_2\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__2\ : label is "soft_lutpair112";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__2\ : label is "soft_lutpair111";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__2\ : label is "soft_lutpair111";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__2\ : label is "soft_lutpair110";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__2\ : label is "soft_lutpair110";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__2\ : label is "soft_lutpair109";
attribute SOFT_HLUTNM of \m_valid_i_i_1__2\ : label is "soft_lutpair90";
begin
s_axi_rvalid <= \^s_axi_rvalid\;
\skid_buffer_reg[0]_0\ <= \^skid_buffer_reg[0]_0\;
\cnt_read[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^skid_buffer_reg[0]_0\,
I1 => \cnt_read_reg[3]_rep__0\,
O => \cnt_read_reg[0]_rep__1\
);
\m_payload_i[0]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => \m_payload_i[0]_i_1__2_n_0\
);
\m_payload_i[10]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(10),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => \m_payload_i[10]_i_1__2_n_0\
);
\m_payload_i[11]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(11),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => \m_payload_i[11]_i_1__2_n_0\
);
\m_payload_i[12]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(12),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => \m_payload_i[12]_i_1__2_n_0\
);
\m_payload_i[13]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(13),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => \m_payload_i[13]_i_1__2_n_0\
);
\m_payload_i[14]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(14),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => \m_payload_i[14]_i_1__1_n_0\
);
\m_payload_i[15]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(15),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => \m_payload_i[15]_i_1__1_n_0\
);
\m_payload_i[16]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(16),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => \m_payload_i[16]_i_1__1_n_0\
);
\m_payload_i[17]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(17),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => \m_payload_i[17]_i_1__1_n_0\
);
\m_payload_i[18]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(18),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => \m_payload_i[18]_i_1__1_n_0\
);
\m_payload_i[19]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(19),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => \m_payload_i[19]_i_1__1_n_0\
);
\m_payload_i[1]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => \m_payload_i[1]_i_1__2_n_0\
);
\m_payload_i[20]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(20),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => \m_payload_i[20]_i_1__1_n_0\
);
\m_payload_i[21]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(21),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => \m_payload_i[21]_i_1__1_n_0\
);
\m_payload_i[22]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(22),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => \m_payload_i[22]_i_1__1_n_0\
);
\m_payload_i[23]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(23),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => \m_payload_i[23]_i_1__1_n_0\
);
\m_payload_i[24]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(24),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => \m_payload_i[24]_i_1__1_n_0\
);
\m_payload_i[25]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(25),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => \m_payload_i[25]_i_1__1_n_0\
);
\m_payload_i[26]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(26),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => \m_payload_i[26]_i_1__1_n_0\
);
\m_payload_i[27]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(27),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => \m_payload_i[27]_i_1__1_n_0\
);
\m_payload_i[28]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(28),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => \m_payload_i[28]_i_1__1_n_0\
);
\m_payload_i[29]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(29),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => \m_payload_i[29]_i_1__1_n_0\
);
\m_payload_i[2]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(2),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => \m_payload_i[2]_i_1__2_n_0\
);
\m_payload_i[30]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(30),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => \m_payload_i[30]_i_1__1_n_0\
);
\m_payload_i[31]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(31),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => \m_payload_i[31]_i_1__1_n_0\
);
\m_payload_i[32]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(32),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => \m_payload_i[32]_i_1__1_n_0\
);
\m_payload_i[33]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(33),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => \m_payload_i[33]_i_1__1_n_0\
);
\m_payload_i[34]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => \m_payload_i[34]_i_1__1_n_0\
);
\m_payload_i[35]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => \m_payload_i[35]_i_1__1_n_0\
);
\m_payload_i[36]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(2),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => \m_payload_i[36]_i_1__1_n_0\
);
\m_payload_i[37]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(3),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => \m_payload_i[37]_i_1_n_0\
);
\m_payload_i[38]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(4),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => \m_payload_i[38]_i_1__1_n_0\
);
\m_payload_i[39]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(5),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => \m_payload_i[39]_i_1__1_n_0\
);
\m_payload_i[3]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(3),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => \m_payload_i[3]_i_1__2_n_0\
);
\m_payload_i[40]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(6),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => \m_payload_i[40]_i_1_n_0\
);
\m_payload_i[41]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(7),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => \m_payload_i[41]_i_1_n_0\
);
\m_payload_i[42]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(8),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => \m_payload_i[42]_i_1_n_0\
);
\m_payload_i[43]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(9),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => \m_payload_i[43]_i_1_n_0\
);
\m_payload_i[44]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(10),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => \m_payload_i[44]_i_1__1_n_0\
);
\m_payload_i[45]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(11),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => \m_payload_i[45]_i_1__1_n_0\
);
\m_payload_i[46]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
O => p_1_in
);
\m_payload_i[46]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(12),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => \m_payload_i[46]_i_2_n_0\
);
\m_payload_i[4]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(4),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => \m_payload_i[4]_i_1__2_n_0\
);
\m_payload_i[5]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(5),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => \m_payload_i[5]_i_1__2_n_0\
);
\m_payload_i[6]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(6),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => \m_payload_i[6]_i_1__2_n_0\
);
\m_payload_i[7]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(7),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => \m_payload_i[7]_i_1__2_n_0\
);
\m_payload_i[8]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(8),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => \m_payload_i[8]_i_1__2_n_0\
);
\m_payload_i[9]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(9),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => \m_payload_i[9]_i_1__2_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[0]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[10]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[11]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[12]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[13]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[14]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[15]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[16]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[17]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[18]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[19]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[1]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[20]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[21]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[22]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[23]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[24]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[25]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[26]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[27]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[28]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[29]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[2]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[30]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[31]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[32]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[33]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[34]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[35]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[36]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(36),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[37]_i_1_n_0\,
Q => \s_axi_rid[11]\(37),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[38]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(38),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[39]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(39),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[3]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(3),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[40]_i_1_n_0\,
Q => \s_axi_rid[11]\(40),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[41]_i_1_n_0\,
Q => \s_axi_rid[11]\(41),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[42]_i_1_n_0\,
Q => \s_axi_rid[11]\(42),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[43]_i_1_n_0\,
Q => \s_axi_rid[11]\(43),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[44]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(44),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[45]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(45),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[46]_i_2_n_0\,
Q => \s_axi_rid[11]\(46),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[4]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[5]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[6]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[7]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[8]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[9]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(9),
R => '0'
);
\m_valid_i_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"4FFF"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
I2 => \^skid_buffer_reg[0]_0\,
I3 => \cnt_read_reg[3]_rep__0\,
O => \m_valid_i_i_1__2_n_0\
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_valid_i_i_1__2_n_0\,
Q => \^s_axi_rvalid\,
R => \aresetn_d_reg[1]_inv\
);
\s_ready_i_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F8FF"
)
port map (
I0 => \^skid_buffer_reg[0]_0\,
I1 => \cnt_read_reg[3]_rep__0\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
O => \s_ready_i_i_1__2_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__2_n_0\,
Q => \^skid_buffer_reg[0]_0\,
R => \aresetn_d_reg[0]\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(32),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(33),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(0),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(1),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(2),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(3),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(4),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(5),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(6),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(7),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(8),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(9),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(10),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(11),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(12),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_b_channel is
port (
si_rs_bvalid : out STD_LOGIC;
\cnt_read_reg[0]_rep__0\ : out STD_LOGIC;
\cnt_read_reg[1]_rep__0\ : out STD_LOGIC;
\state_reg[0]_rep\ : out STD_LOGIC;
m_axi_bready : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
\skid_buffer_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
areset_d1 : in STD_LOGIC;
shandshake : in STD_LOGIC;
aclk : in STD_LOGIC;
b_push : in STD_LOGIC;
si_rs_bready : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
end led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_b_channel;
architecture STRUCTURE of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_b_channel is
signal bid_fifo_0_n_3 : STD_LOGIC;
signal bid_fifo_0_n_5 : STD_LOGIC;
signal \bresp_cnt[7]_i_7_n_0\ : STD_LOGIC;
signal \bresp_cnt_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal bresp_push : STD_LOGIC;
signal cnt_read : STD_LOGIC_VECTOR ( 1 downto 0 );
signal mhandshake : STD_LOGIC;
signal mhandshake_r : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s_bresp_acc0 : STD_LOGIC;
signal \s_bresp_acc[0]_i_1_n_0\ : STD_LOGIC;
signal \s_bresp_acc[1]_i_1_n_0\ : STD_LOGIC;
signal \s_bresp_acc_reg_n_0_[0]\ : STD_LOGIC;
signal \s_bresp_acc_reg_n_0_[1]\ : STD_LOGIC;
signal shandshake_r : STD_LOGIC;
signal \^si_rs_bvalid\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \bresp_cnt[1]_i_1\ : label is "soft_lutpair132";
attribute SOFT_HLUTNM of \bresp_cnt[2]_i_1\ : label is "soft_lutpair132";
attribute SOFT_HLUTNM of \bresp_cnt[3]_i_1\ : label is "soft_lutpair130";
attribute SOFT_HLUTNM of \bresp_cnt[4]_i_1\ : label is "soft_lutpair130";
attribute SOFT_HLUTNM of \bresp_cnt[6]_i_1\ : label is "soft_lutpair131";
attribute SOFT_HLUTNM of \bresp_cnt[7]_i_2\ : label is "soft_lutpair131";
begin
si_rs_bvalid <= \^si_rs_bvalid\;
bid_fifo_0: entity work.led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_simple_fifo
port map (
D(0) => bid_fifo_0_n_5,
Q(1 downto 0) => cnt_read(1 downto 0),
SR(0) => s_bresp_acc0,
aclk => aclk,
areset_d1 => areset_d1,
b_push => b_push,
\bresp_cnt_reg[7]\(7 downto 0) => \bresp_cnt_reg__0\(7 downto 0),
bresp_push => bresp_push,
bvalid_i_reg => bid_fifo_0_n_3,
\cnt_read_reg[0]_rep__0_0\ => \cnt_read_reg[0]_rep__0\,
\cnt_read_reg[1]_rep__0_0\ => \cnt_read_reg[1]_rep__0\,
\in\(15 downto 0) => \in\(15 downto 0),
mhandshake_r => mhandshake_r,
\out\(11 downto 0) => \out\(11 downto 0),
shandshake_r => shandshake_r,
si_rs_bready => si_rs_bready,
si_rs_bvalid => \^si_rs_bvalid\,
\state_reg[0]_rep\ => \state_reg[0]_rep\
);
\bresp_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \bresp_cnt_reg__0\(0),
O => p_0_in(0)
);
\bresp_cnt[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \bresp_cnt_reg__0\(0),
I1 => \bresp_cnt_reg__0\(1),
O => p_0_in(1)
);
\bresp_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \bresp_cnt_reg__0\(2),
I1 => \bresp_cnt_reg__0\(1),
I2 => \bresp_cnt_reg__0\(0),
O => p_0_in(2)
);
\bresp_cnt[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \bresp_cnt_reg__0\(3),
I1 => \bresp_cnt_reg__0\(0),
I2 => \bresp_cnt_reg__0\(1),
I3 => \bresp_cnt_reg__0\(2),
O => p_0_in(3)
);
\bresp_cnt[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \bresp_cnt_reg__0\(4),
I1 => \bresp_cnt_reg__0\(2),
I2 => \bresp_cnt_reg__0\(1),
I3 => \bresp_cnt_reg__0\(0),
I4 => \bresp_cnt_reg__0\(3),
O => p_0_in(4)
);
\bresp_cnt[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \bresp_cnt_reg__0\(5),
I1 => \bresp_cnt_reg__0\(3),
I2 => \bresp_cnt_reg__0\(0),
I3 => \bresp_cnt_reg__0\(1),
I4 => \bresp_cnt_reg__0\(2),
I5 => \bresp_cnt_reg__0\(4),
O => p_0_in(5)
);
\bresp_cnt[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \bresp_cnt_reg__0\(6),
I1 => \bresp_cnt[7]_i_7_n_0\,
O => p_0_in(6)
);
\bresp_cnt[7]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \bresp_cnt_reg__0\(7),
I1 => \bresp_cnt[7]_i_7_n_0\,
I2 => \bresp_cnt_reg__0\(6),
O => p_0_in(7)
);
\bresp_cnt[7]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \bresp_cnt_reg__0\(5),
I1 => \bresp_cnt_reg__0\(3),
I2 => \bresp_cnt_reg__0\(0),
I3 => \bresp_cnt_reg__0\(1),
I4 => \bresp_cnt_reg__0\(2),
I5 => \bresp_cnt_reg__0\(4),
O => \bresp_cnt[7]_i_7_n_0\
);
\bresp_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(0),
Q => \bresp_cnt_reg__0\(0),
R => s_bresp_acc0
);
\bresp_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(1),
Q => \bresp_cnt_reg__0\(1),
R => s_bresp_acc0
);
\bresp_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(2),
Q => \bresp_cnt_reg__0\(2),
R => s_bresp_acc0
);
\bresp_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(3),
Q => \bresp_cnt_reg__0\(3),
R => s_bresp_acc0
);
\bresp_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(4),
Q => \bresp_cnt_reg__0\(4),
R => s_bresp_acc0
);
\bresp_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(5),
Q => \bresp_cnt_reg__0\(5),
R => s_bresp_acc0
);
\bresp_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(6),
Q => \bresp_cnt_reg__0\(6),
R => s_bresp_acc0
);
\bresp_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(7),
Q => \bresp_cnt_reg__0\(7),
R => s_bresp_acc0
);
bresp_fifo_0: entity work.\led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized0\
port map (
D(0) => bid_fifo_0_n_5,
Q(1 downto 0) => cnt_read(1 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\in\(1) => \s_bresp_acc_reg_n_0_[1]\,
\in\(0) => \s_bresp_acc_reg_n_0_[0]\,
m_axi_bready => m_axi_bready,
m_axi_bvalid => m_axi_bvalid,
mhandshake => mhandshake,
mhandshake_r => mhandshake_r,
sel => bresp_push,
shandshake_r => shandshake_r,
\skid_buffer_reg[1]\(1 downto 0) => \skid_buffer_reg[1]\(1 downto 0)
);
bvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => bid_fifo_0_n_3,
Q => \^si_rs_bvalid\,
R => '0'
);
mhandshake_r_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => mhandshake,
Q => mhandshake_r,
R => areset_d1
);
\s_bresp_acc[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EACECCCC"
)
port map (
I0 => m_axi_bresp(0),
I1 => \s_bresp_acc_reg_n_0_[0]\,
I2 => \s_bresp_acc_reg_n_0_[1]\,
I3 => m_axi_bresp(1),
I4 => mhandshake,
I5 => s_bresp_acc0,
O => \s_bresp_acc[0]_i_1_n_0\
);
\s_bresp_acc[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00EA"
)
port map (
I0 => \s_bresp_acc_reg_n_0_[1]\,
I1 => m_axi_bresp(1),
I2 => mhandshake,
I3 => s_bresp_acc0,
O => \s_bresp_acc[1]_i_1_n_0\
);
\s_bresp_acc_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \s_bresp_acc[0]_i_1_n_0\,
Q => \s_bresp_acc_reg_n_0_[0]\,
R => '0'
);
\s_bresp_acc_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \s_bresp_acc[1]_i_1_n_0\,
Q => \s_bresp_acc_reg_n_0_[1]\,
R => '0'
);
shandshake_r_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => shandshake,
Q => shandshake_r,
R => areset_d1
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_cmd_translator is
port (
next_pending_r_reg : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
sel_first_0 : out STD_LOGIC;
sel_first : out STD_LOGIC;
\axlen_cnt_reg[0]\ : out STD_LOGIC;
\state_reg[0]_rep\ : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
wrap_next_pending : in STD_LOGIC;
sel_first_i : in STD_LOGIC;
\m_payload_i_reg[39]\ : in STD_LOGIC;
\m_payload_i_reg[39]_0\ : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
si_rs_awvalid : in STD_LOGIC;
\m_payload_i_reg[46]\ : in STD_LOGIC_VECTOR ( 18 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep\ : in STD_LOGIC;
axaddr_incr : in STD_LOGIC_VECTOR ( 11 downto 0 );
\state_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[0]_rep_0\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
end led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_cmd_translator;
architecture STRUCTURE of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_cmd_translator is
signal incr_cmd_0_n_10 : STD_LOGIC;
signal incr_cmd_0_n_11 : STD_LOGIC;
signal incr_cmd_0_n_12 : STD_LOGIC;
signal incr_cmd_0_n_13 : STD_LOGIC;
signal incr_cmd_0_n_14 : STD_LOGIC;
signal incr_cmd_0_n_15 : STD_LOGIC;
signal incr_cmd_0_n_3 : STD_LOGIC;
signal incr_cmd_0_n_4 : STD_LOGIC;
signal incr_cmd_0_n_5 : STD_LOGIC;
signal incr_cmd_0_n_6 : STD_LOGIC;
signal incr_cmd_0_n_7 : STD_LOGIC;
signal incr_cmd_0_n_8 : STD_LOGIC;
signal incr_cmd_0_n_9 : STD_LOGIC;
signal s_axburst_eq0 : STD_LOGIC;
signal s_axburst_eq1 : STD_LOGIC;
begin
incr_cmd_0: entity work.led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_incr_cmd
port map (
E(0) => E(0),
Q(1 downto 0) => Q(1 downto 0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0),
\axaddr_incr_reg[0]_0\ => sel_first_0,
\axaddr_incr_reg[11]_0\(9) => incr_cmd_0_n_3,
\axaddr_incr_reg[11]_0\(8) => incr_cmd_0_n_4,
\axaddr_incr_reg[11]_0\(7) => incr_cmd_0_n_5,
\axaddr_incr_reg[11]_0\(6) => incr_cmd_0_n_6,
\axaddr_incr_reg[11]_0\(5) => incr_cmd_0_n_7,
\axaddr_incr_reg[11]_0\(4) => incr_cmd_0_n_8,
\axaddr_incr_reg[11]_0\(3) => incr_cmd_0_n_9,
\axaddr_incr_reg[11]_0\(2) => incr_cmd_0_n_10,
\axaddr_incr_reg[11]_0\(1) => incr_cmd_0_n_11,
\axaddr_incr_reg[11]_0\(0) => incr_cmd_0_n_12,
\axlen_cnt_reg[0]_0\ => \axlen_cnt_reg[0]\,
incr_next_pending => incr_next_pending,
\m_axi_awaddr[11]\ => incr_cmd_0_n_13,
\m_axi_awaddr[2]\ => incr_cmd_0_n_15,
\m_axi_awaddr[3]\ => incr_cmd_0_n_14,
\m_payload_i_reg[46]\(9 downto 7) => \m_payload_i_reg[46]\(18 downto 16),
\m_payload_i_reg[46]\(6 downto 4) => \m_payload_i_reg[46]\(14 downto 12),
\m_payload_i_reg[46]\(3 downto 0) => \m_payload_i_reg[46]\(3 downto 0),
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
next_pending_r_reg_0 => next_pending_r_reg,
sel_first_reg_0 => sel_first_reg_1,
si_rs_awvalid => si_rs_awvalid,
\state_reg[0]\(0) => \state_reg[0]\(0),
\state_reg[0]_rep\ => \state_reg[0]_rep_0\,
\state_reg[1]_rep\ => \state_reg[1]_rep\
);
\memory_reg[3][0]_srl4_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axburst_eq1,
I1 => \m_payload_i_reg[46]\(15),
I2 => s_axburst_eq0,
O => \state_reg[0]_rep\
);
s_axburst_eq0_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]\,
Q => s_axburst_eq0,
R => '0'
);
s_axburst_eq1_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]_0\,
Q => s_axburst_eq1,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_i,
Q => sel_first_reg_0,
R => '0'
);
wrap_cmd_0: entity work.led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_wrap_cmd
port map (
D(3 downto 0) => D(3 downto 0),
E(0) => E(0),
Q(1 downto 0) => Q(1 downto 0),
aclk => aclk,
\axaddr_incr_reg[11]\(9) => incr_cmd_0_n_3,
\axaddr_incr_reg[11]\(8) => incr_cmd_0_n_4,
\axaddr_incr_reg[11]\(7) => incr_cmd_0_n_5,
\axaddr_incr_reg[11]\(6) => incr_cmd_0_n_6,
\axaddr_incr_reg[11]\(5) => incr_cmd_0_n_7,
\axaddr_incr_reg[11]\(4) => incr_cmd_0_n_8,
\axaddr_incr_reg[11]\(3) => incr_cmd_0_n_9,
\axaddr_incr_reg[11]\(2) => incr_cmd_0_n_10,
\axaddr_incr_reg[11]\(1) => incr_cmd_0_n_11,
\axaddr_incr_reg[11]\(0) => incr_cmd_0_n_12,
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0),
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
\m_payload_i_reg[46]\(17 downto 14) => \m_payload_i_reg[46]\(18 downto 15),
\m_payload_i_reg[46]\(13 downto 0) => \m_payload_i_reg[46]\(13 downto 0),
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0),
next_pending_r_reg_0 => next_pending_r_reg_0,
next_pending_r_reg_1 => next_pending_r_reg_1,
sel_first_reg_0 => sel_first,
sel_first_reg_1 => sel_first_reg_2,
sel_first_reg_2 => incr_cmd_0_n_13,
sel_first_reg_3 => incr_cmd_0_n_14,
sel_first_reg_4 => incr_cmd_0_n_15,
si_rs_awvalid => si_rs_awvalid,
\state_reg[0]\(0) => \state_reg[0]\(0),
\state_reg[1]_rep\ => \state_reg[1]_rep\,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0),
\wrap_second_len_r_reg[3]_1\(3 downto 0) => \wrap_second_len_r_reg[3]_0\(3 downto 0),
\wrap_second_len_r_reg[3]_2\(3 downto 0) => \wrap_second_len_r_reg[3]_1\(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_cmd_translator_1 is
port (
incr_next_pending : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
sel_first : out STD_LOGIC;
sel_first_reg_1 : out STD_LOGIC;
\axlen_cnt_reg[0]\ : out STD_LOGIC;
\axlen_cnt_reg[0]_0\ : out STD_LOGIC;
r_rlast : out STD_LOGIC;
\state_reg[0]_rep\ : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
wrap_next_pending : in STD_LOGIC;
sel_first_i : in STD_LOGIC;
\m_payload_i_reg[39]\ : in STD_LOGIC;
\m_payload_i_reg[39]_0\ : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
sel_first_reg_3 : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 18 downto 0 );
\state_reg[1]_rep\ : in STD_LOGIC;
\m_payload_i_reg[44]\ : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
si_rs_arvalid : in STD_LOGIC;
\state_reg[0]_rep_0\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC;
\m_payload_i_reg[35]\ : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
sel_first_reg_4 : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arready : in STD_LOGIC;
\state_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_cmd_translator_1 : entity is "axi_protocol_converter_v2_1_14_b2s_cmd_translator";
end led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_cmd_translator_1;
architecture STRUCTURE of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_cmd_translator_1 is
signal incr_cmd_0_n_10 : STD_LOGIC;
signal incr_cmd_0_n_11 : STD_LOGIC;
signal incr_cmd_0_n_12 : STD_LOGIC;
signal incr_cmd_0_n_13 : STD_LOGIC;
signal incr_cmd_0_n_14 : STD_LOGIC;
signal incr_cmd_0_n_15 : STD_LOGIC;
signal incr_cmd_0_n_3 : STD_LOGIC;
signal incr_cmd_0_n_4 : STD_LOGIC;
signal incr_cmd_0_n_5 : STD_LOGIC;
signal incr_cmd_0_n_6 : STD_LOGIC;
signal incr_cmd_0_n_7 : STD_LOGIC;
signal incr_cmd_0_n_8 : STD_LOGIC;
signal incr_cmd_0_n_9 : STD_LOGIC;
signal s_axburst_eq0 : STD_LOGIC;
signal s_axburst_eq1 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of r_rlast_r_i_1 : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \state[1]_i_2\ : label is "soft_lutpair14";
begin
incr_cmd_0: entity work.led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_incr_cmd_2
port map (
E(0) => E(0),
O(3 downto 0) => O(3 downto 0),
Q(11) => incr_cmd_0_n_3,
Q(10) => incr_cmd_0_n_4,
Q(9) => incr_cmd_0_n_5,
Q(8) => incr_cmd_0_n_6,
Q(7) => incr_cmd_0_n_7,
Q(6) => incr_cmd_0_n_8,
Q(5) => incr_cmd_0_n_9,
Q(4) => incr_cmd_0_n_10,
Q(3) => incr_cmd_0_n_11,
Q(2) => incr_cmd_0_n_12,
Q(1) => incr_cmd_0_n_13,
Q(0) => incr_cmd_0_n_14,
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
\axaddr_incr_reg[0]_0\ => sel_first,
\axlen_cnt_reg[0]_0\ => \axlen_cnt_reg[0]\,
incr_next_pending => incr_next_pending,
\m_axi_araddr[11]\ => incr_cmd_0_n_15,
m_axi_arready => m_axi_arready,
\m_payload_i_reg[3]\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0),
\m_payload_i_reg[44]\ => \m_payload_i_reg[44]\,
\m_payload_i_reg[46]\(9 downto 7) => Q(18 downto 16),
\m_payload_i_reg[46]\(6 downto 4) => Q(14 downto 12),
\m_payload_i_reg[46]\(3 downto 0) => Q(3 downto 0),
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[7]\(3 downto 0) => \m_payload_i_reg[7]\(3 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
sel_first_reg_0 => sel_first_reg_2,
sel_first_reg_1(0) => sel_first_reg_4(0),
si_rs_arvalid => si_rs_arvalid,
\state_reg[0]_rep\ => \state_reg[0]_rep_0\,
\state_reg[1]\ => \state_reg[1]\,
\state_reg[1]_0\(1 downto 0) => \state_reg[1]_0\(1 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep\
);
r_rlast_r_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => s_axburst_eq0,
I1 => Q(15),
I2 => s_axburst_eq1,
O => r_rlast
);
s_axburst_eq0_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]\,
Q => s_axburst_eq0,
R => '0'
);
s_axburst_eq1_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]_0\,
Q => s_axburst_eq1,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_i,
Q => sel_first_reg_0,
R => '0'
);
\state[1]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axburst_eq1,
I1 => Q(15),
I2 => s_axburst_eq0,
O => \state_reg[0]_rep\
);
wrap_cmd_0: entity work.led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_wrap_cmd_3
port map (
D(3 downto 0) => D(3 downto 0),
E(0) => E(0),
Q(17 downto 14) => Q(18 downto 15),
Q(13 downto 0) => Q(13 downto 0),
aclk => aclk,
\axaddr_incr_reg[11]\(11) => incr_cmd_0_n_3,
\axaddr_incr_reg[11]\(10) => incr_cmd_0_n_4,
\axaddr_incr_reg[11]\(9) => incr_cmd_0_n_5,
\axaddr_incr_reg[11]\(8) => incr_cmd_0_n_6,
\axaddr_incr_reg[11]\(7) => incr_cmd_0_n_7,
\axaddr_incr_reg[11]\(6) => incr_cmd_0_n_8,
\axaddr_incr_reg[11]\(5) => incr_cmd_0_n_9,
\axaddr_incr_reg[11]\(4) => incr_cmd_0_n_10,
\axaddr_incr_reg[11]\(3) => incr_cmd_0_n_11,
\axaddr_incr_reg[11]\(2) => incr_cmd_0_n_12,
\axaddr_incr_reg[11]\(1) => incr_cmd_0_n_13,
\axaddr_incr_reg[11]\(0) => incr_cmd_0_n_14,
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]_1\ => \axaddr_offset_r_reg[3]_0\,
\axlen_cnt_reg[0]_0\ => \axlen_cnt_reg[0]_0\,
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
\m_payload_i_reg[35]\ => \m_payload_i_reg[35]\,
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
next_pending_r_reg_0 => next_pending_r_reg,
sel_first_reg_0 => sel_first_reg_1,
sel_first_reg_1 => sel_first_reg_3,
sel_first_reg_2 => incr_cmd_0_n_15,
si_rs_arvalid => si_rs_arvalid,
\state_reg[0]_rep\ => \state_reg[0]_rep_0\,
\state_reg[1]_rep\ => \state_reg[1]_rep\,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0),
\wrap_second_len_r_reg[3]_1\(3 downto 0) => \wrap_second_len_r_reg[3]_0\(3 downto 0),
\wrap_second_len_r_reg[3]_2\(2 downto 0) => \wrap_second_len_r_reg[3]_1\(2 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_r_channel is
port (
m_valid_i_reg : out STD_LOGIC;
\state_reg[1]_rep\ : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 33 downto 0 );
\skid_buffer_reg[46]\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
r_push : in STD_LOGIC;
aclk : in STD_LOGIC;
r_rlast : in STD_LOGIC;
s_ready_i_reg : in STD_LOGIC;
si_rs_rready : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
areset_d1 : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
end led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_r_channel;
architecture STRUCTURE of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_r_channel is
signal \^m_valid_i_reg\ : STD_LOGIC;
signal r_push_r : STD_LOGIC;
signal rd_data_fifo_0_n_0 : STD_LOGIC;
signal rd_data_fifo_0_n_2 : STD_LOGIC;
signal rd_data_fifo_0_n_3 : STD_LOGIC;
signal rd_data_fifo_0_n_5 : STD_LOGIC;
signal trans_in : STD_LOGIC_VECTOR ( 12 downto 0 );
signal transaction_fifo_0_n_2 : STD_LOGIC;
signal wr_en0 : STD_LOGIC;
begin
m_valid_i_reg <= \^m_valid_i_reg\;
\r_arid_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(0),
Q => trans_in(1),
R => '0'
);
\r_arid_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(10),
Q => trans_in(11),
R => '0'
);
\r_arid_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(11),
Q => trans_in(12),
R => '0'
);
\r_arid_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(1),
Q => trans_in(2),
R => '0'
);
\r_arid_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(2),
Q => trans_in(3),
R => '0'
);
\r_arid_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(3),
Q => trans_in(4),
R => '0'
);
\r_arid_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(4),
Q => trans_in(5),
R => '0'
);
\r_arid_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(5),
Q => trans_in(6),
R => '0'
);
\r_arid_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(6),
Q => trans_in(7),
R => '0'
);
\r_arid_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(7),
Q => trans_in(8),
R => '0'
);
\r_arid_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(8),
Q => trans_in(9),
R => '0'
);
\r_arid_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(9),
Q => trans_in(10),
R => '0'
);
r_push_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => r_push,
Q => r_push_r,
R => '0'
);
r_rlast_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => r_rlast,
Q => trans_in(0),
R => '0'
);
rd_data_fifo_0: entity work.\led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized1\
port map (
aclk => aclk,
areset_d1 => areset_d1,
\cnt_read_reg[3]_rep__0_0\ => \^m_valid_i_reg\,
\cnt_read_reg[3]_rep__2_0\ => rd_data_fifo_0_n_0,
\cnt_read_reg[4]_rep__2_0\ => rd_data_fifo_0_n_2,
\cnt_read_reg[4]_rep__2_1\ => rd_data_fifo_0_n_3,
\in\(33 downto 0) => \in\(33 downto 0),
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
\out\(33 downto 0) => \out\(33 downto 0),
s_ready_i_reg => s_ready_i_reg,
s_ready_i_reg_0 => transaction_fifo_0_n_2,
si_rs_rready => si_rs_rready,
\state_reg[1]_rep\ => rd_data_fifo_0_n_5,
wr_en0 => wr_en0
);
transaction_fifo_0: entity work.\led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized2\
port map (
aclk => aclk,
areset_d1 => areset_d1,
\cnt_read_reg[0]_rep__2\ => rd_data_fifo_0_n_5,
\cnt_read_reg[2]_rep__2\ => rd_data_fifo_0_n_3,
\cnt_read_reg[3]_rep__2\ => rd_data_fifo_0_n_0,
\cnt_read_reg[4]_rep__2\ => transaction_fifo_0_n_2,
\cnt_read_reg[4]_rep__2_0\ => rd_data_fifo_0_n_2,
\in\(12 downto 0) => trans_in(12 downto 0),
m_valid_i_reg => \^m_valid_i_reg\,
r_push_r => r_push_r,
s_ready_i_reg => s_ready_i_reg,
si_rs_rready => si_rs_rready,
\skid_buffer_reg[46]\(12 downto 0) => \skid_buffer_reg[46]\(12 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep\,
wr_en0 => wr_en0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity led_controller_design_auto_pc_0_axi_register_slice_v2_1_14_axi_register_slice is
port (
s_axi_awready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
si_rs_awvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
si_rs_bready : out STD_LOGIC;
si_rs_arvalid : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
si_rs_rready : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
wrap_second_len : out STD_LOGIC_VECTOR ( 3 downto 0 );
axaddr_incr : out STD_LOGIC_VECTOR ( 11 downto 0 );
Q : out STD_LOGIC_VECTOR ( 54 downto 0 );
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\s_arid_r_reg[11]\ : out STD_LOGIC_VECTOR ( 53 downto 0 );
\axaddr_incr_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
O : out STD_LOGIC_VECTOR ( 3 downto 0 );
axaddr_offset : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axlen_cnt_reg[3]\ : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
shandshake : out STD_LOGIC;
\wrap_second_len_r_reg[2]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axaddr_offset_r_reg[1]\ : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
\wrap_second_len_r_reg[3]\ : out STD_LOGIC;
\axlen_cnt_reg[3]_0\ : out STD_LOGIC;
\cnt_read_reg[0]_rep__1\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\axaddr_offset_r_reg[0]\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]_0\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
aclk : in STD_LOGIC;
m_valid_i0 : in STD_LOGIC;
aresetn : in STD_LOGIC;
\cnt_read_reg[3]_rep__0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
S : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[1]_rep\ : in STD_LOGIC;
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
b_push : in STD_LOGIC;
si_rs_bvalid : in STD_LOGIC;
axaddr_offset_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep_0\ : in STD_LOGIC;
\wrap_second_len_r_reg[2]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\state_reg[1]_rep_1\ : in STD_LOGIC;
\state_reg[0]_rep\ : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
\out\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\s_bresp_acc_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
r_push_r_reg : in STD_LOGIC_VECTOR ( 12 downto 0 );
\cnt_read_reg[4]\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep_2\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end led_controller_design_auto_pc_0_axi_register_slice_v2_1_14_axi_register_slice;
architecture STRUCTURE of led_controller_design_auto_pc_0_axi_register_slice_v2_1_14_axi_register_slice is
signal \gen_simple_ar.ar_pipe_n_2\ : STD_LOGIC;
signal \gen_simple_aw.aw_pipe_n_1\ : STD_LOGIC;
signal \gen_simple_aw.aw_pipe_n_91\ : STD_LOGIC;
begin
\gen_simple_ar.ar_pipe\: entity work.led_controller_design_auto_pc_0_axi_register_slice_v2_1_14_axic_register_slice
port map (
O(3 downto 0) => O(3 downto 0),
Q(53 downto 0) => \s_arid_r_reg[11]\(53 downto 0),
aclk => aclk,
\aresetn_d_reg[0]\ => \gen_simple_aw.aw_pipe_n_1\,
\aresetn_d_reg[0]_0\ => \gen_simple_aw.aw_pipe_n_91\,
\axaddr_incr_reg[3]\(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
\axaddr_incr_reg[7]\(3 downto 0) => \axaddr_incr_reg[7]\(3 downto 0),
axaddr_offset_0(0) => axaddr_offset_0(0),
\axaddr_offset_r_reg[0]\ => \axaddr_offset_r_reg[0]\,
\axaddr_offset_r_reg[1]\ => \axaddr_offset_r_reg[1]\,
\axaddr_offset_r_reg[3]\(2 downto 0) => \axaddr_offset_r_reg[3]\(2 downto 0),
\axaddr_offset_r_reg[3]_0\(2 downto 0) => \axaddr_offset_r_reg[3]_1\(2 downto 0),
\axlen_cnt_reg[3]\ => \axlen_cnt_reg[3]_0\,
\m_payload_i_reg[3]_0\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0),
m_valid_i0 => m_valid_i0,
m_valid_i_reg_0 => \gen_simple_ar.ar_pipe_n_2\,
next_pending_r_reg => next_pending_r_reg_0,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_ready_i_reg_0 => si_rs_arvalid,
\state_reg[0]_rep\ => \state_reg[0]_rep\,
\state_reg[1]_rep\ => \state_reg[1]_rep_0\,
\state_reg[1]_rep_0\ => \state_reg[1]_rep_1\,
\state_reg[1]_rep_1\(0) => \state_reg[1]_rep_2\(0),
\wrap_boundary_axaddr_r_reg[6]\(6 downto 0) => \wrap_boundary_axaddr_r_reg[6]\(6 downto 0),
\wrap_second_len_r_reg[2]\(1 downto 0) => \wrap_second_len_r_reg[2]\(1 downto 0),
\wrap_second_len_r_reg[2]_0\(1 downto 0) => \wrap_second_len_r_reg[2]_0\(1 downto 0),
\wrap_second_len_r_reg[3]\ => \wrap_second_len_r_reg[3]\
);
\gen_simple_aw.aw_pipe\: entity work.led_controller_design_auto_pc_0_axi_register_slice_v2_1_14_axic_register_slice_0
port map (
D(3 downto 0) => D(3 downto 0),
E(0) => E(0),
Q(54 downto 0) => Q(54 downto 0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
aresetn => aresetn,
\aresetn_d_reg[1]_inv\ => \gen_simple_aw.aw_pipe_n_91\,
\aresetn_d_reg[1]_inv_0\ => \gen_simple_ar.ar_pipe_n_2\,
axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0),
axaddr_offset(1) => axaddr_offset(2),
axaddr_offset(0) => axaddr_offset(0),
\axaddr_offset_r_reg[1]\ => axaddr_offset(1),
\axaddr_offset_r_reg[3]\ => axaddr_offset(3),
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \axaddr_offset_r_reg[3]_0\(3 downto 0),
\axlen_cnt_reg[3]\ => \axlen_cnt_reg[3]\,
b_push => b_push,
m_valid_i_reg_0 => si_rs_awvalid,
next_pending_r_reg => next_pending_r_reg,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_ready_i_reg_0 => \gen_simple_aw.aw_pipe_n_1\,
\state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep\,
\wrap_boundary_axaddr_r_reg[6]\(6 downto 0) => \wrap_boundary_axaddr_r_reg[6]_0\(6 downto 0),
wrap_second_len(2 downto 1) => wrap_second_len(3 downto 2),
wrap_second_len(0) => wrap_second_len(0),
\wrap_second_len_r_reg[1]\ => wrap_second_len(1),
\wrap_second_len_r_reg[3]\(3 downto 0) => \wrap_second_len_r_reg[3]_0\(3 downto 0)
);
\gen_simple_b.b_pipe\: entity work.\led_controller_design_auto_pc_0_axi_register_slice_v2_1_14_axic_register_slice__parameterized1\
port map (
aclk => aclk,
\aresetn_d_reg[0]\ => \gen_simple_aw.aw_pipe_n_1\,
\aresetn_d_reg[1]_inv\ => \gen_simple_ar.ar_pipe_n_2\,
\out\(11 downto 0) => \out\(11 downto 0),
\s_axi_bid[11]\(13 downto 0) => \s_axi_bid[11]\(13 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
\s_bresp_acc_reg[1]\(1 downto 0) => \s_bresp_acc_reg[1]\(1 downto 0),
shandshake => shandshake,
si_rs_bvalid => si_rs_bvalid,
\skid_buffer_reg[0]_0\ => si_rs_bready
);
\gen_simple_r.r_pipe\: entity work.\led_controller_design_auto_pc_0_axi_register_slice_v2_1_14_axic_register_slice__parameterized2\
port map (
aclk => aclk,
\aresetn_d_reg[0]\ => \gen_simple_aw.aw_pipe_n_1\,
\aresetn_d_reg[1]_inv\ => \gen_simple_ar.ar_pipe_n_2\,
\cnt_read_reg[0]_rep__1\ => \cnt_read_reg[0]_rep__1\,
\cnt_read_reg[3]_rep__0\ => \cnt_read_reg[3]_rep__0\,
\cnt_read_reg[4]\(33 downto 0) => \cnt_read_reg[4]\(33 downto 0),
r_push_r_reg(12 downto 0) => r_push_r_reg(12 downto 0),
\s_axi_rid[11]\(46 downto 0) => \s_axi_rid[11]\(46 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
\skid_buffer_reg[0]_0\ => si_rs_rready
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_ar_channel is
port (
\wrap_boundary_axaddr_r_reg[11]\ : out STD_LOGIC;
\wrap_second_len_r_reg[2]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
axaddr_offset : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
r_push : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC;
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
r_rlast : out STD_LOGIC;
m_valid_i0 : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\r_arid_r_reg[11]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
\cnt_read_reg[1]_rep__0\ : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 30 downto 0 );
D : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_payload_i_reg[35]\ : in STD_LOGIC;
\m_payload_i_reg[47]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[35]_0\ : in STD_LOGIC;
\m_payload_i_reg[3]\ : in STD_LOGIC;
\m_payload_i_reg[44]\ : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_ready_i_reg : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
end led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_ar_channel;
architecture STRUCTURE of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_ar_channel is
signal ar_cmd_fsm_0_n_0 : STD_LOGIC;
signal ar_cmd_fsm_0_n_11 : STD_LOGIC;
signal ar_cmd_fsm_0_n_14 : STD_LOGIC;
signal ar_cmd_fsm_0_n_16 : STD_LOGIC;
signal ar_cmd_fsm_0_n_17 : STD_LOGIC;
signal ar_cmd_fsm_0_n_18 : STD_LOGIC;
signal ar_cmd_fsm_0_n_21 : STD_LOGIC;
signal ar_cmd_fsm_0_n_3 : STD_LOGIC;
signal ar_cmd_fsm_0_n_4 : STD_LOGIC;
signal ar_cmd_fsm_0_n_5 : STD_LOGIC;
signal ar_cmd_fsm_0_n_6 : STD_LOGIC;
signal \^axaddr_offset\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal cmd_translator_0_n_1 : STD_LOGIC;
signal cmd_translator_0_n_2 : STD_LOGIC;
signal cmd_translator_0_n_4 : STD_LOGIC;
signal cmd_translator_0_n_5 : STD_LOGIC;
signal cmd_translator_0_n_6 : STD_LOGIC;
signal cmd_translator_0_n_8 : STD_LOGIC;
signal \incr_cmd_0/sel_first\ : STD_LOGIC;
signal incr_next_pending : STD_LOGIC;
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal \^r_push\ : STD_LOGIC;
signal sel_first_i : STD_LOGIC;
signal state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^wrap_boundary_axaddr_r_reg[11]\ : STD_LOGIC;
signal \wrap_cmd_0/axaddr_offset_r\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \wrap_cmd_0/wrap_second_len\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \wrap_cmd_0/wrap_second_len_r\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal wrap_next_pending : STD_LOGIC;
begin
axaddr_offset(0) <= \^axaddr_offset\(0);
\axaddr_offset_r_reg[3]\(2 downto 0) <= \^axaddr_offset_r_reg[3]\(2 downto 0);
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
r_push <= \^r_push\;
\wrap_boundary_axaddr_r_reg[11]\ <= \^wrap_boundary_axaddr_r_reg[11]\;
ar_cmd_fsm_0: entity work.led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_rd_cmd_fsm
port map (
D(2) => ar_cmd_fsm_0_n_3,
D(1) => ar_cmd_fsm_0_n_4,
D(0) => ar_cmd_fsm_0_n_5,
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
Q(1 downto 0) => state(1 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\axaddr_incr_reg[0]\(0) => ar_cmd_fsm_0_n_21,
\axaddr_offset_r_reg[0]\(0) => \^axaddr_offset\(0),
\axaddr_offset_r_reg[3]\(1) => \^axaddr_offset_r_reg[3]\(2),
\axaddr_offset_r_reg[3]\(0) => \wrap_cmd_0/axaddr_offset_r\(0),
\axlen_cnt_reg[3]\ => cmd_translator_0_n_6,
\axlen_cnt_reg[4]\(0) => ar_cmd_fsm_0_n_16,
\axlen_cnt_reg[6]\ => cmd_translator_0_n_5,
\axlen_cnt_reg[7]\ => ar_cmd_fsm_0_n_0,
\cnt_read_reg[1]_rep__0\ => \cnt_read_reg[1]_rep__0\,
incr_next_pending => incr_next_pending,
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
\m_payload_i_reg[0]\ => \m_payload_i_reg[0]\,
\m_payload_i_reg[0]_0\ => \^m_payload_i_reg[0]_0\,
\m_payload_i_reg[0]_1\(0) => E(0),
\m_payload_i_reg[35]\ => \m_payload_i_reg[35]\,
\m_payload_i_reg[35]_0\ => \m_payload_i_reg[35]_0\,
\m_payload_i_reg[3]\ => \m_payload_i_reg[3]\,
\m_payload_i_reg[44]\(1 downto 0) => Q(16 downto 15),
\m_payload_i_reg[44]_0\ => \m_payload_i_reg[44]\,
\m_payload_i_reg[47]\(1 downto 0) => \m_payload_i_reg[47]_0\(2 downto 1),
m_valid_i0 => m_valid_i0,
next_pending_r_reg => cmd_translator_0_n_1,
r_push_r_reg => \^r_push\,
s_axburst_eq0_reg => ar_cmd_fsm_0_n_11,
s_axburst_eq1_reg => ar_cmd_fsm_0_n_14,
s_axburst_eq1_reg_0 => cmd_translator_0_n_8,
s_axi_arvalid => s_axi_arvalid,
s_ready_i_reg => s_ready_i_reg,
sel_first => \incr_cmd_0/sel_first\,
sel_first_i => sel_first_i,
sel_first_reg => ar_cmd_fsm_0_n_17,
sel_first_reg_0 => ar_cmd_fsm_0_n_18,
sel_first_reg_1 => cmd_translator_0_n_4,
sel_first_reg_2 => cmd_translator_0_n_2,
si_rs_arvalid => si_rs_arvalid,
\wrap_cnt_r_reg[0]\ => ar_cmd_fsm_0_n_6,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[2]\(1 downto 0) => D(1 downto 0),
\wrap_second_len_r_reg[3]\(1) => \wrap_cmd_0/wrap_second_len\(3),
\wrap_second_len_r_reg[3]\(0) => \wrap_cmd_0/wrap_second_len\(0),
\wrap_second_len_r_reg[3]_0\(1) => \wrap_cmd_0/wrap_second_len_r\(3),
\wrap_second_len_r_reg[3]_0\(0) => \wrap_cmd_0/wrap_second_len_r\(0)
);
cmd_translator_0: entity work.led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_cmd_translator_1
port map (
D(3 downto 1) => \m_payload_i_reg[47]_0\(2 downto 0),
D(0) => \^axaddr_offset\(0),
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
O(3 downto 0) => O(3 downto 0),
Q(18 downto 0) => Q(18 downto 0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
\axaddr_offset_r_reg[3]\(3 downto 1) => \^axaddr_offset_r_reg[3]\(2 downto 0),
\axaddr_offset_r_reg[3]\(0) => \wrap_cmd_0/axaddr_offset_r\(0),
\axaddr_offset_r_reg[3]_0\ => ar_cmd_fsm_0_n_6,
\axlen_cnt_reg[0]\ => cmd_translator_0_n_5,
\axlen_cnt_reg[0]_0\ => cmd_translator_0_n_6,
incr_next_pending => incr_next_pending,
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
m_axi_arready => m_axi_arready,
\m_payload_i_reg[35]\ => \m_payload_i_reg[35]\,
\m_payload_i_reg[39]\ => ar_cmd_fsm_0_n_11,
\m_payload_i_reg[39]_0\ => ar_cmd_fsm_0_n_14,
\m_payload_i_reg[3]\(3 downto 0) => \m_payload_i_reg[3]_0\(3 downto 0),
\m_payload_i_reg[44]\ => \m_payload_i_reg[44]\,
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0),
\m_payload_i_reg[7]\(3 downto 0) => \m_payload_i_reg[7]\(3 downto 0),
m_valid_i_reg(0) => ar_cmd_fsm_0_n_16,
next_pending_r_reg => cmd_translator_0_n_1,
r_rlast => r_rlast,
sel_first => \incr_cmd_0/sel_first\,
sel_first_i => sel_first_i,
sel_first_reg_0 => cmd_translator_0_n_2,
sel_first_reg_1 => cmd_translator_0_n_4,
sel_first_reg_2 => ar_cmd_fsm_0_n_18,
sel_first_reg_3 => ar_cmd_fsm_0_n_17,
sel_first_reg_4(0) => ar_cmd_fsm_0_n_21,
si_rs_arvalid => si_rs_arvalid,
\state_reg[0]_rep\ => cmd_translator_0_n_8,
\state_reg[0]_rep_0\ => \^m_payload_i_reg[0]_0\,
\state_reg[1]\ => ar_cmd_fsm_0_n_0,
\state_reg[1]_0\(1 downto 0) => state(1 downto 0),
\state_reg[1]_rep\ => \^r_push\,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]\(3) => \wrap_cmd_0/wrap_second_len_r\(3),
\wrap_second_len_r_reg[3]\(2 downto 1) => \wrap_second_len_r_reg[2]\(1 downto 0),
\wrap_second_len_r_reg[3]\(0) => \wrap_cmd_0/wrap_second_len_r\(0),
\wrap_second_len_r_reg[3]_0\(3) => \wrap_cmd_0/wrap_second_len\(3),
\wrap_second_len_r_reg[3]_0\(2 downto 1) => D(1 downto 0),
\wrap_second_len_r_reg[3]_0\(0) => \wrap_cmd_0/wrap_second_len\(0),
\wrap_second_len_r_reg[3]_1\(2) => ar_cmd_fsm_0_n_3,
\wrap_second_len_r_reg[3]_1\(1) => ar_cmd_fsm_0_n_4,
\wrap_second_len_r_reg[3]_1\(0) => ar_cmd_fsm_0_n_5
);
\s_arid_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(19),
Q => \r_arid_r_reg[11]\(0),
R => '0'
);
\s_arid_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(29),
Q => \r_arid_r_reg[11]\(10),
R => '0'
);
\s_arid_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(30),
Q => \r_arid_r_reg[11]\(11),
R => '0'
);
\s_arid_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(20),
Q => \r_arid_r_reg[11]\(1),
R => '0'
);
\s_arid_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(21),
Q => \r_arid_r_reg[11]\(2),
R => '0'
);
\s_arid_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(22),
Q => \r_arid_r_reg[11]\(3),
R => '0'
);
\s_arid_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(23),
Q => \r_arid_r_reg[11]\(4),
R => '0'
);
\s_arid_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(24),
Q => \r_arid_r_reg[11]\(5),
R => '0'
);
\s_arid_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(25),
Q => \r_arid_r_reg[11]\(6),
R => '0'
);
\s_arid_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(26),
Q => \r_arid_r_reg[11]\(7),
R => '0'
);
\s_arid_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(27),
Q => \r_arid_r_reg[11]\(8),
R => '0'
);
\s_arid_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(28),
Q => \r_arid_r_reg[11]\(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_aw_channel is
port (
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
\wrap_boundary_axaddr_r_reg[0]\ : out STD_LOGIC;
m_axi_awvalid : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
b_push : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\in\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
si_rs_awvalid : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
\m_payload_i_reg[61]\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
\m_payload_i_reg[46]\ : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
\cnt_read_reg[1]_rep__0\ : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
\cnt_read_reg[1]_rep__0_0\ : in STD_LOGIC;
\cnt_read_reg[0]_rep__0\ : in STD_LOGIC;
axaddr_incr : in STD_LOGIC_VECTOR ( 11 downto 0 );
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
end led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_aw_channel;
architecture STRUCTURE of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_aw_channel is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal aw_cmd_fsm_0_n_0 : STD_LOGIC;
signal aw_cmd_fsm_0_n_10 : STD_LOGIC;
signal aw_cmd_fsm_0_n_11 : STD_LOGIC;
signal aw_cmd_fsm_0_n_12 : STD_LOGIC;
signal aw_cmd_fsm_0_n_3 : STD_LOGIC;
signal aw_cmd_fsm_0_n_5 : STD_LOGIC;
signal aw_cmd_fsm_0_n_6 : STD_LOGIC;
signal cmd_translator_0_n_0 : STD_LOGIC;
signal cmd_translator_0_n_1 : STD_LOGIC;
signal cmd_translator_0_n_2 : STD_LOGIC;
signal cmd_translator_0_n_5 : STD_LOGIC;
signal cmd_translator_0_n_6 : STD_LOGIC;
signal cmd_translator_0_n_7 : STD_LOGIC;
signal \incr_cmd_0/sel_first\ : STD_LOGIC;
signal incr_next_pending : STD_LOGIC;
signal sel_first : STD_LOGIC;
signal sel_first_i : STD_LOGIC;
signal \^wrap_boundary_axaddr_r_reg[0]\ : STD_LOGIC;
signal wrap_next_pending : STD_LOGIC;
begin
Q(1 downto 0) <= \^q\(1 downto 0);
\wrap_boundary_axaddr_r_reg[0]\ <= \^wrap_boundary_axaddr_r_reg[0]\;
aw_cmd_fsm_0: entity work.led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_wr_cmd_fsm
port map (
E(0) => aw_cmd_fsm_0_n_0,
Q(1 downto 0) => \^q\(1 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\axlen_cnt_reg[0]\ => aw_cmd_fsm_0_n_3,
\axlen_cnt_reg[1]\ => cmd_translator_0_n_7,
\axlen_cnt_reg[6]\ => cmd_translator_0_n_5,
\axlen_cnt_reg[7]\ => aw_cmd_fsm_0_n_5,
b_push => b_push,
\cnt_read_reg[0]_rep__0\ => \cnt_read_reg[0]_rep__0\,
\cnt_read_reg[1]_rep__0\ => \cnt_read_reg[1]_rep__0\,
\cnt_read_reg[1]_rep__0_0\ => \cnt_read_reg[1]_rep__0_0\,
incr_next_pending => incr_next_pending,
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
\m_payload_i_reg[0]\(0) => E(0),
\m_payload_i_reg[39]\(0) => \m_payload_i_reg[61]\(15),
\m_payload_i_reg[46]\ => \m_payload_i_reg[46]\,
next_pending_r_reg => cmd_translator_0_n_0,
next_pending_r_reg_0 => cmd_translator_0_n_1,
s_axburst_eq0_reg => aw_cmd_fsm_0_n_6,
s_axburst_eq1_reg => aw_cmd_fsm_0_n_10,
s_axburst_eq1_reg_0 => cmd_translator_0_n_6,
sel_first => sel_first,
sel_first_0 => \incr_cmd_0/sel_first\,
sel_first_i => sel_first_i,
sel_first_reg => aw_cmd_fsm_0_n_11,
sel_first_reg_0 => aw_cmd_fsm_0_n_12,
sel_first_reg_1 => cmd_translator_0_n_2,
si_rs_awvalid => si_rs_awvalid,
\wrap_boundary_axaddr_r_reg[0]\(0) => \^wrap_boundary_axaddr_r_reg[0]\,
wrap_next_pending => wrap_next_pending
);
cmd_translator_0: entity work.led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_cmd_translator
port map (
D(3 downto 0) => D(3 downto 0),
E(0) => \^wrap_boundary_axaddr_r_reg[0]\,
Q(1 downto 0) => \^q\(1 downto 0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0),
\axaddr_offset_r_reg[3]\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0),
\axlen_cnt_reg[0]\ => cmd_translator_0_n_5,
incr_next_pending => incr_next_pending,
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
\m_payload_i_reg[39]\ => aw_cmd_fsm_0_n_6,
\m_payload_i_reg[39]_0\ => aw_cmd_fsm_0_n_10,
\m_payload_i_reg[46]\(18 downto 0) => \m_payload_i_reg[61]\(18 downto 0),
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0),
next_pending_r_reg => cmd_translator_0_n_0,
next_pending_r_reg_0 => cmd_translator_0_n_1,
next_pending_r_reg_1 => cmd_translator_0_n_7,
sel_first => sel_first,
sel_first_0 => \incr_cmd_0/sel_first\,
sel_first_i => sel_first_i,
sel_first_reg_0 => cmd_translator_0_n_2,
sel_first_reg_1 => aw_cmd_fsm_0_n_12,
sel_first_reg_2 => aw_cmd_fsm_0_n_11,
si_rs_awvalid => si_rs_awvalid,
\state_reg[0]\(0) => aw_cmd_fsm_0_n_0,
\state_reg[0]_rep\ => cmd_translator_0_n_6,
\state_reg[0]_rep_0\ => aw_cmd_fsm_0_n_5,
\state_reg[1]_rep\ => aw_cmd_fsm_0_n_3,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0),
\wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]_0\(3 downto 0),
\wrap_second_len_r_reg[3]_1\(3 downto 0) => \wrap_second_len_r_reg[3]_1\(3 downto 0)
);
\s_awid_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(20),
Q => \in\(4),
R => '0'
);
\s_awid_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(30),
Q => \in\(14),
R => '0'
);
\s_awid_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(31),
Q => \in\(15),
R => '0'
);
\s_awid_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(21),
Q => \in\(5),
R => '0'
);
\s_awid_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(22),
Q => \in\(6),
R => '0'
);
\s_awid_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(23),
Q => \in\(7),
R => '0'
);
\s_awid_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(24),
Q => \in\(8),
R => '0'
);
\s_awid_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(25),
Q => \in\(9),
R => '0'
);
\s_awid_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(26),
Q => \in\(10),
R => '0'
);
\s_awid_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(27),
Q => \in\(11),
R => '0'
);
\s_awid_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(28),
Q => \in\(12),
R => '0'
);
\s_awid_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(29),
Q => \in\(13),
R => '0'
);
\s_awlen_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(16),
Q => \in\(0),
R => '0'
);
\s_awlen_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(17),
Q => \in\(1),
R => '0'
);
\s_awlen_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(18),
Q => \in\(2),
R => '0'
);
\s_awlen_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(19),
Q => \in\(3),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s is
port (
s_axi_rvalid : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 22 downto 0 );
s_axi_arready : out STD_LOGIC;
\m_axi_arprot[2]\ : out STD_LOGIC_VECTOR ( 22 downto 0 );
s_axi_bvalid : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_arready : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
aclk : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awready : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
aresetn : in STD_LOGIC
);
end led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s;
architecture STRUCTURE of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s is
signal \RD.ar_channel_0_n_0\ : STD_LOGIC;
signal \RD.ar_channel_0_n_38\ : STD_LOGIC;
signal \RD.ar_channel_0_n_39\ : STD_LOGIC;
signal \RD.ar_channel_0_n_40\ : STD_LOGIC;
signal \RD.ar_channel_0_n_41\ : STD_LOGIC;
signal \RD.ar_channel_0_n_8\ : STD_LOGIC;
signal \RD.ar_channel_0_n_9\ : STD_LOGIC;
signal \RD.r_channel_0_n_0\ : STD_LOGIC;
signal \RD.r_channel_0_n_1\ : STD_LOGIC;
signal SI_REG_n_10 : STD_LOGIC;
signal SI_REG_n_103 : STD_LOGIC;
signal SI_REG_n_141 : STD_LOGIC;
signal SI_REG_n_142 : STD_LOGIC;
signal SI_REG_n_143 : STD_LOGIC;
signal SI_REG_n_144 : STD_LOGIC;
signal SI_REG_n_145 : STD_LOGIC;
signal SI_REG_n_146 : STD_LOGIC;
signal SI_REG_n_147 : STD_LOGIC;
signal SI_REG_n_148 : STD_LOGIC;
signal SI_REG_n_153 : STD_LOGIC;
signal SI_REG_n_154 : STD_LOGIC;
signal SI_REG_n_161 : STD_LOGIC;
signal SI_REG_n_162 : STD_LOGIC;
signal SI_REG_n_163 : STD_LOGIC;
signal SI_REG_n_164 : STD_LOGIC;
signal SI_REG_n_165 : STD_LOGIC;
signal SI_REG_n_166 : STD_LOGIC;
signal SI_REG_n_167 : STD_LOGIC;
signal SI_REG_n_168 : STD_LOGIC;
signal SI_REG_n_169 : STD_LOGIC;
signal SI_REG_n_170 : STD_LOGIC;
signal SI_REG_n_171 : STD_LOGIC;
signal SI_REG_n_172 : STD_LOGIC;
signal SI_REG_n_173 : STD_LOGIC;
signal SI_REG_n_174 : STD_LOGIC;
signal SI_REG_n_175 : STD_LOGIC;
signal SI_REG_n_176 : STD_LOGIC;
signal SI_REG_n_177 : STD_LOGIC;
signal SI_REG_n_178 : STD_LOGIC;
signal SI_REG_n_179 : STD_LOGIC;
signal SI_REG_n_180 : STD_LOGIC;
signal SI_REG_n_45 : STD_LOGIC;
signal SI_REG_n_83 : STD_LOGIC;
signal SI_REG_n_84 : STD_LOGIC;
signal SI_REG_n_85 : STD_LOGIC;
signal SI_REG_n_86 : STD_LOGIC;
signal \WR.aw_channel_0_n_2\ : STD_LOGIC;
signal \WR.aw_channel_0_n_42\ : STD_LOGIC;
signal \WR.aw_channel_0_n_43\ : STD_LOGIC;
signal \WR.aw_channel_0_n_44\ : STD_LOGIC;
signal \WR.aw_channel_0_n_45\ : STD_LOGIC;
signal \WR.b_channel_0_n_1\ : STD_LOGIC;
signal \WR.b_channel_0_n_2\ : STD_LOGIC;
signal \WR.b_channel_0_n_3\ : STD_LOGIC;
signal areset_d1 : STD_LOGIC;
signal areset_d1_i_1_n_0 : STD_LOGIC;
signal \aw_cmd_fsm_0/state\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axaddr_incr : STD_LOGIC_VECTOR ( 11 downto 0 );
signal b_awid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal b_awlen : STD_LOGIC_VECTOR ( 3 downto 0 );
signal b_push : STD_LOGIC;
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_3\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len\ : STD_LOGIC_VECTOR ( 2 downto 1 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\ : STD_LOGIC_VECTOR ( 2 downto 1 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_2\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \gen_simple_ar.ar_pipe/m_valid_i0\ : STD_LOGIC;
signal \gen_simple_ar.ar_pipe/p_1_in\ : STD_LOGIC;
signal \gen_simple_aw.aw_pipe/p_1_in\ : STD_LOGIC;
signal r_push : STD_LOGIC;
signal r_rlast : STD_LOGIC;
signal s_arid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s_arid_r : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s_awid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^s_axi_arready\ : STD_LOGIC;
signal shandshake : STD_LOGIC;
signal si_rs_araddr : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_arburst : STD_LOGIC_VECTOR ( 1 to 1 );
signal si_rs_arlen : STD_LOGIC_VECTOR ( 2 downto 0 );
signal si_rs_arsize : STD_LOGIC_VECTOR ( 1 downto 0 );
signal si_rs_arvalid : STD_LOGIC;
signal si_rs_awaddr : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_awburst : STD_LOGIC_VECTOR ( 1 to 1 );
signal si_rs_awlen : STD_LOGIC_VECTOR ( 3 downto 0 );
signal si_rs_awsize : STD_LOGIC_VECTOR ( 1 downto 0 );
signal si_rs_awvalid : STD_LOGIC;
signal si_rs_bid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_bready : STD_LOGIC;
signal si_rs_bresp : STD_LOGIC_VECTOR ( 1 downto 0 );
signal si_rs_bvalid : STD_LOGIC;
signal si_rs_rdata : STD_LOGIC_VECTOR ( 31 downto 0 );
signal si_rs_rid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_rlast : STD_LOGIC;
signal si_rs_rready : STD_LOGIC;
signal si_rs_rresp : STD_LOGIC_VECTOR ( 1 downto 0 );
signal wrap_cnt : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
s_axi_arready <= \^s_axi_arready\;
\RD.ar_channel_0\: entity work.led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_ar_channel
port map (
D(1 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(2 downto 1),
E(0) => \gen_simple_ar.ar_pipe/p_1_in\,
O(3) => SI_REG_n_145,
O(2) => SI_REG_n_146,
O(1) => SI_REG_n_147,
O(0) => SI_REG_n_148,
Q(30 downto 19) => s_arid(11 downto 0),
Q(18 downto 16) => si_rs_arlen(2 downto 0),
Q(15) => si_rs_arburst(1),
Q(14) => SI_REG_n_103,
Q(13 downto 12) => si_rs_arsize(1 downto 0),
Q(11 downto 0) => si_rs_araddr(11 downto 0),
S(3) => \RD.ar_channel_0_n_38\,
S(2) => \RD.ar_channel_0_n_39\,
S(1) => \RD.ar_channel_0_n_40\,
S(0) => \RD.ar_channel_0_n_41\,
aclk => aclk,
areset_d1 => areset_d1,
axaddr_offset(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(0),
\axaddr_offset_r_reg[3]\(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(3 downto 1),
\cnt_read_reg[1]_rep__0\ => \RD.r_channel_0_n_1\,
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
\m_payload_i_reg[0]\ => \RD.ar_channel_0_n_8\,
\m_payload_i_reg[0]_0\ => \RD.ar_channel_0_n_9\,
\m_payload_i_reg[35]\ => SI_REG_n_161,
\m_payload_i_reg[35]_0\ => SI_REG_n_163,
\m_payload_i_reg[3]\ => SI_REG_n_173,
\m_payload_i_reg[3]_0\(3) => SI_REG_n_83,
\m_payload_i_reg[3]_0\(2) => SI_REG_n_84,
\m_payload_i_reg[3]_0\(1) => SI_REG_n_85,
\m_payload_i_reg[3]_0\(0) => SI_REG_n_86,
\m_payload_i_reg[44]\ => SI_REG_n_162,
\m_payload_i_reg[47]\ => SI_REG_n_164,
\m_payload_i_reg[47]_0\(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(3 downto 1),
\m_payload_i_reg[6]\(6) => SI_REG_n_166,
\m_payload_i_reg[6]\(5) => SI_REG_n_167,
\m_payload_i_reg[6]\(4) => SI_REG_n_168,
\m_payload_i_reg[6]\(3) => SI_REG_n_169,
\m_payload_i_reg[6]\(2) => SI_REG_n_170,
\m_payload_i_reg[6]\(1) => SI_REG_n_171,
\m_payload_i_reg[6]\(0) => SI_REG_n_172,
\m_payload_i_reg[7]\(3) => SI_REG_n_141,
\m_payload_i_reg[7]\(2) => SI_REG_n_142,
\m_payload_i_reg[7]\(1) => SI_REG_n_143,
\m_payload_i_reg[7]\(0) => SI_REG_n_144,
m_valid_i0 => \gen_simple_ar.ar_pipe/m_valid_i0\,
\r_arid_r_reg[11]\(11 downto 0) => s_arid_r(11 downto 0),
r_push => r_push,
r_rlast => r_rlast,
s_axi_arvalid => s_axi_arvalid,
s_ready_i_reg => \^s_axi_arready\,
si_rs_arvalid => si_rs_arvalid,
\wrap_boundary_axaddr_r_reg[11]\ => \RD.ar_channel_0_n_0\,
\wrap_second_len_r_reg[2]\(1 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(2 downto 1)
);
\RD.r_channel_0\: entity work.led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_r_channel
port map (
D(11 downto 0) => s_arid_r(11 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\in\(33 downto 0) => \in\(33 downto 0),
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
m_valid_i_reg => \RD.r_channel_0_n_0\,
\out\(33 downto 32) => si_rs_rresp(1 downto 0),
\out\(31 downto 0) => si_rs_rdata(31 downto 0),
r_push => r_push,
r_rlast => r_rlast,
s_ready_i_reg => SI_REG_n_165,
si_rs_rready => si_rs_rready,
\skid_buffer_reg[46]\(12 downto 1) => si_rs_rid(11 downto 0),
\skid_buffer_reg[46]\(0) => si_rs_rlast,
\state_reg[1]_rep\ => \RD.r_channel_0_n_1\
);
SI_REG: entity work.led_controller_design_auto_pc_0_axi_register_slice_v2_1_14_axi_register_slice
port map (
D(3 downto 2) => wrap_cnt(3 downto 2),
D(1) => SI_REG_n_10,
D(0) => wrap_cnt(0),
E(0) => \gen_simple_aw.aw_pipe/p_1_in\,
O(3) => SI_REG_n_145,
O(2) => SI_REG_n_146,
O(1) => SI_REG_n_147,
O(0) => SI_REG_n_148,
Q(54 downto 43) => s_awid(11 downto 0),
Q(42 downto 39) => si_rs_awlen(3 downto 0),
Q(38) => si_rs_awburst(1),
Q(37) => SI_REG_n_45,
Q(36 downto 35) => si_rs_awsize(1 downto 0),
Q(34 downto 12) => Q(22 downto 0),
Q(11 downto 0) => si_rs_awaddr(11 downto 0),
S(3) => \WR.aw_channel_0_n_42\,
S(2) => \WR.aw_channel_0_n_43\,
S(1) => \WR.aw_channel_0_n_44\,
S(0) => \WR.aw_channel_0_n_45\,
aclk => aclk,
aresetn => aresetn,
axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0),
\axaddr_incr_reg[3]\(3) => SI_REG_n_83,
\axaddr_incr_reg[3]\(2) => SI_REG_n_84,
\axaddr_incr_reg[3]\(1) => SI_REG_n_85,
\axaddr_incr_reg[3]\(0) => SI_REG_n_86,
\axaddr_incr_reg[7]\(3) => SI_REG_n_141,
\axaddr_incr_reg[7]\(2) => SI_REG_n_142,
\axaddr_incr_reg[7]\(1) => SI_REG_n_143,
\axaddr_incr_reg[7]\(0) => SI_REG_n_144,
axaddr_offset(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(3 downto 0),
axaddr_offset_0(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(0),
\axaddr_offset_r_reg[0]\ => SI_REG_n_173,
\axaddr_offset_r_reg[1]\ => SI_REG_n_161,
\axaddr_offset_r_reg[3]\(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(3 downto 1),
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_3\(3 downto 0),
\axaddr_offset_r_reg[3]_1\(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(3 downto 1),
\axlen_cnt_reg[3]\ => SI_REG_n_153,
\axlen_cnt_reg[3]_0\ => SI_REG_n_164,
b_push => b_push,
\cnt_read_reg[0]_rep__1\ => SI_REG_n_165,
\cnt_read_reg[3]_rep__0\ => \RD.r_channel_0_n_0\,
\cnt_read_reg[4]\(33 downto 32) => si_rs_rresp(1 downto 0),
\cnt_read_reg[4]\(31 downto 0) => si_rs_rdata(31 downto 0),
\m_payload_i_reg[3]\(3) => \RD.ar_channel_0_n_38\,
\m_payload_i_reg[3]\(2) => \RD.ar_channel_0_n_39\,
\m_payload_i_reg[3]\(1) => \RD.ar_channel_0_n_40\,
\m_payload_i_reg[3]\(0) => \RD.ar_channel_0_n_41\,
m_valid_i0 => \gen_simple_ar.ar_pipe/m_valid_i0\,
next_pending_r_reg => SI_REG_n_154,
next_pending_r_reg_0 => SI_REG_n_162,
\out\(11 downto 0) => si_rs_bid(11 downto 0),
r_push_r_reg(12 downto 1) => si_rs_rid(11 downto 0),
r_push_r_reg(0) => si_rs_rlast,
\s_arid_r_reg[11]\(53 downto 42) => s_arid(11 downto 0),
\s_arid_r_reg[11]\(41 downto 39) => si_rs_arlen(2 downto 0),
\s_arid_r_reg[11]\(38) => si_rs_arburst(1),
\s_arid_r_reg[11]\(37) => SI_REG_n_103,
\s_arid_r_reg[11]\(36 downto 35) => si_rs_arsize(1 downto 0),
\s_arid_r_reg[11]\(34 downto 12) => \m_axi_arprot[2]\(22 downto 0),
\s_arid_r_reg[11]\(11 downto 0) => si_rs_araddr(11 downto 0),
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => \^s_axi_arready\,
s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0),
s_axi_awvalid => s_axi_awvalid,
\s_axi_bid[11]\(13 downto 0) => \s_axi_bid[11]\(13 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
\s_axi_rid[11]\(46 downto 0) => \s_axi_rid[11]\(46 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
\s_bresp_acc_reg[1]\(1 downto 0) => si_rs_bresp(1 downto 0),
shandshake => shandshake,
si_rs_arvalid => si_rs_arvalid,
si_rs_awvalid => si_rs_awvalid,
si_rs_bready => si_rs_bready,
si_rs_bvalid => si_rs_bvalid,
si_rs_rready => si_rs_rready,
\state_reg[0]_rep\ => \RD.ar_channel_0_n_9\,
\state_reg[1]\(1 downto 0) => \aw_cmd_fsm_0/state\(1 downto 0),
\state_reg[1]_rep\ => \WR.aw_channel_0_n_2\,
\state_reg[1]_rep_0\ => \RD.ar_channel_0_n_0\,
\state_reg[1]_rep_1\ => \RD.ar_channel_0_n_8\,
\state_reg[1]_rep_2\(0) => \gen_simple_ar.ar_pipe/p_1_in\,
\wrap_boundary_axaddr_r_reg[6]\(6) => SI_REG_n_166,
\wrap_boundary_axaddr_r_reg[6]\(5) => SI_REG_n_167,
\wrap_boundary_axaddr_r_reg[6]\(4) => SI_REG_n_168,
\wrap_boundary_axaddr_r_reg[6]\(3) => SI_REG_n_169,
\wrap_boundary_axaddr_r_reg[6]\(2) => SI_REG_n_170,
\wrap_boundary_axaddr_r_reg[6]\(1) => SI_REG_n_171,
\wrap_boundary_axaddr_r_reg[6]\(0) => SI_REG_n_172,
\wrap_boundary_axaddr_r_reg[6]_0\(6) => SI_REG_n_174,
\wrap_boundary_axaddr_r_reg[6]_0\(5) => SI_REG_n_175,
\wrap_boundary_axaddr_r_reg[6]_0\(4) => SI_REG_n_176,
\wrap_boundary_axaddr_r_reg[6]_0\(3) => SI_REG_n_177,
\wrap_boundary_axaddr_r_reg[6]_0\(2) => SI_REG_n_178,
\wrap_boundary_axaddr_r_reg[6]_0\(1) => SI_REG_n_179,
\wrap_boundary_axaddr_r_reg[6]_0\(0) => SI_REG_n_180,
wrap_second_len(3 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(3 downto 0),
\wrap_second_len_r_reg[2]\(1 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(2 downto 1),
\wrap_second_len_r_reg[2]_0\(1 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(2 downto 1),
\wrap_second_len_r_reg[3]\ => SI_REG_n_163,
\wrap_second_len_r_reg[3]_0\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_2\(3 downto 0)
);
\WR.aw_channel_0\: entity work.led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_aw_channel
port map (
D(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(3 downto 0),
E(0) => \gen_simple_aw.aw_pipe/p_1_in\,
Q(1 downto 0) => \aw_cmd_fsm_0/state\(1 downto 0),
S(3) => \WR.aw_channel_0_n_42\,
S(2) => \WR.aw_channel_0_n_43\,
S(1) => \WR.aw_channel_0_n_44\,
S(0) => \WR.aw_channel_0_n_45\,
aclk => aclk,
areset_d1 => areset_d1,
axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0),
\axaddr_offset_r_reg[3]\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_3\(3 downto 0),
b_push => b_push,
\cnt_read_reg[0]_rep__0\ => \WR.b_channel_0_n_1\,
\cnt_read_reg[1]_rep__0\ => \WR.b_channel_0_n_3\,
\cnt_read_reg[1]_rep__0_0\ => \WR.b_channel_0_n_2\,
\in\(15 downto 4) => b_awid(11 downto 0),
\in\(3 downto 0) => b_awlen(3 downto 0),
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
\m_payload_i_reg[46]\ => SI_REG_n_154,
\m_payload_i_reg[47]\ => SI_REG_n_153,
\m_payload_i_reg[61]\(31 downto 20) => s_awid(11 downto 0),
\m_payload_i_reg[61]\(19 downto 16) => si_rs_awlen(3 downto 0),
\m_payload_i_reg[61]\(15) => si_rs_awburst(1),
\m_payload_i_reg[61]\(14) => SI_REG_n_45,
\m_payload_i_reg[61]\(13 downto 12) => si_rs_awsize(1 downto 0),
\m_payload_i_reg[61]\(11 downto 0) => si_rs_awaddr(11 downto 0),
\m_payload_i_reg[6]\(6) => SI_REG_n_174,
\m_payload_i_reg[6]\(5) => SI_REG_n_175,
\m_payload_i_reg[6]\(4) => SI_REG_n_176,
\m_payload_i_reg[6]\(3) => SI_REG_n_177,
\m_payload_i_reg[6]\(2) => SI_REG_n_178,
\m_payload_i_reg[6]\(1) => SI_REG_n_179,
\m_payload_i_reg[6]\(0) => SI_REG_n_180,
si_rs_awvalid => si_rs_awvalid,
\wrap_boundary_axaddr_r_reg[0]\ => \WR.aw_channel_0_n_2\,
\wrap_second_len_r_reg[3]\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_2\(3 downto 0),
\wrap_second_len_r_reg[3]_0\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(3 downto 0),
\wrap_second_len_r_reg[3]_1\(3 downto 2) => wrap_cnt(3 downto 2),
\wrap_second_len_r_reg[3]_1\(1) => SI_REG_n_10,
\wrap_second_len_r_reg[3]_1\(0) => wrap_cnt(0)
);
\WR.b_channel_0\: entity work.led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_b_channel
port map (
aclk => aclk,
areset_d1 => areset_d1,
b_push => b_push,
\cnt_read_reg[0]_rep__0\ => \WR.b_channel_0_n_1\,
\cnt_read_reg[1]_rep__0\ => \WR.b_channel_0_n_2\,
\in\(15 downto 4) => b_awid(11 downto 0),
\in\(3 downto 0) => b_awlen(3 downto 0),
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
\out\(11 downto 0) => si_rs_bid(11 downto 0),
shandshake => shandshake,
si_rs_bready => si_rs_bready,
si_rs_bvalid => si_rs_bvalid,
\skid_buffer_reg[1]\(1 downto 0) => si_rs_bresp(1 downto 0),
\state_reg[0]_rep\ => \WR.b_channel_0_n_3\
);
areset_d1_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aresetn,
O => areset_d1_i_1_n_0
);
areset_d1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => areset_d1_i_1_n_0,
Q => areset_d1,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_axi_protocol_converter is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 12;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is "zynq";
attribute C_IGNORE_ID : integer;
attribute C_IGNORE_ID of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 0;
attribute C_M_AXI_PROTOCOL : integer;
attribute C_M_AXI_PROTOCOL of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 2;
attribute C_S_AXI_PROTOCOL : integer;
attribute C_S_AXI_PROTOCOL of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 1;
attribute C_TRANSLATION_MODE : integer;
attribute C_TRANSLATION_MODE of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 2;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is "yes";
attribute P_AXI3 : integer;
attribute P_AXI3 of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is "3'b010";
attribute P_CONVERSION : integer;
attribute P_CONVERSION of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 2;
attribute P_DECERR : string;
attribute P_DECERR of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is "2'b11";
attribute P_INCR : string;
attribute P_INCR of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is "2'b01";
attribute P_PROTECTION : integer;
attribute P_PROTECTION of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 1;
attribute P_SLVERR : string;
attribute P_SLVERR of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is "2'b10";
end led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_axi_protocol_converter;
architecture STRUCTURE of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_axi_protocol_converter is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal \^m_axi_wready\ : STD_LOGIC;
signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_wstrb\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_wvalid\ : STD_LOGIC;
begin
\^m_axi_wready\ <= m_axi_wready;
\^s_axi_wdata\(31 downto 0) <= s_axi_wdata(31 downto 0);
\^s_axi_wstrb\(3 downto 0) <= s_axi_wstrb(3 downto 0);
\^s_axi_wvalid\ <= s_axi_wvalid;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const1>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(11) <= \<const0>\;
m_axi_arid(10) <= \<const0>\;
m_axi_arid(9) <= \<const0>\;
m_axi_arid(8) <= \<const0>\;
m_axi_arid(7) <= \<const0>\;
m_axi_arid(6) <= \<const0>\;
m_axi_arid(5) <= \<const0>\;
m_axi_arid(4) <= \<const0>\;
m_axi_arid(3) <= \<const0>\;
m_axi_arid(2) <= \<const0>\;
m_axi_arid(1) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const1>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const1>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(11) <= \<const0>\;
m_axi_awid(10) <= \<const0>\;
m_axi_awid(9) <= \<const0>\;
m_axi_awid(8) <= \<const0>\;
m_axi_awid(7) <= \<const0>\;
m_axi_awid(6) <= \<const0>\;
m_axi_awid(5) <= \<const0>\;
m_axi_awid(4) <= \<const0>\;
m_axi_awid(3) <= \<const0>\;
m_axi_awid(2) <= \<const0>\;
m_axi_awid(1) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const1>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_wdata(31 downto 0) <= \^s_axi_wdata\(31 downto 0);
m_axi_wid(11) <= \<const0>\;
m_axi_wid(10) <= \<const0>\;
m_axi_wid(9) <= \<const0>\;
m_axi_wid(8) <= \<const0>\;
m_axi_wid(7) <= \<const0>\;
m_axi_wid(6) <= \<const0>\;
m_axi_wid(5) <= \<const0>\;
m_axi_wid(4) <= \<const0>\;
m_axi_wid(3) <= \<const0>\;
m_axi_wid(2) <= \<const0>\;
m_axi_wid(1) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const1>\;
m_axi_wstrb(3 downto 0) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \^s_axi_wvalid\;
s_axi_buser(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_wready <= \^m_axi_wready\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
\gen_axilite.gen_b2s_conv.axilite_b2s\: entity work.led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s
port map (
Q(22 downto 20) => m_axi_awprot(2 downto 0),
Q(19 downto 0) => m_axi_awaddr(31 downto 12),
aclk => aclk,
aresetn => aresetn,
\in\(33 downto 32) => m_axi_rresp(1 downto 0),
\in\(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
\m_axi_arprot[2]\(22 downto 20) => m_axi_arprot(2 downto 0),
\m_axi_arprot[2]\(19 downto 0) => m_axi_araddr(31 downto 12),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0),
s_axi_awvalid => s_axi_awvalid,
\s_axi_bid[11]\(13 downto 2) => s_axi_bid(11 downto 0),
\s_axi_bid[11]\(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
\s_axi_rid[11]\(46 downto 35) => s_axi_rid(11 downto 0),
\s_axi_rid[11]\(34) => s_axi_rlast,
\s_axi_rid[11]\(33 downto 32) => s_axi_rresp(1 downto 0),
\s_axi_rid[11]\(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity led_controller_design_auto_pc_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of led_controller_design_auto_pc_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of led_controller_design_auto_pc_0 : entity is "led_controller_design_auto_pc_0,axi_protocol_converter_v2_1_14_axi_protocol_converter,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of led_controller_design_auto_pc_0 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of led_controller_design_auto_pc_0 : entity is "axi_protocol_converter_v2_1_14_axi_protocol_converter,Vivado 2017.3";
end led_controller_design_auto_pc_0;
architecture STRUCTURE of led_controller_design_auto_pc_0 is
signal NLW_inst_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_inst_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of inst : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of inst : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of inst : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of inst : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of inst : label is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of inst : label is 12;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of inst : label is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of inst : label is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of inst : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of inst : label is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "zynq";
attribute C_IGNORE_ID : integer;
attribute C_IGNORE_ID of inst : label is 0;
attribute C_M_AXI_PROTOCOL : integer;
attribute C_M_AXI_PROTOCOL of inst : label is 2;
attribute C_S_AXI_PROTOCOL : integer;
attribute C_S_AXI_PROTOCOL of inst : label is 1;
attribute C_TRANSLATION_MODE : integer;
attribute C_TRANSLATION_MODE of inst : label is 2;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute P_AXI3 : integer;
attribute P_AXI3 of inst : label is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of inst : label is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of inst : label is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of inst : label is "3'b010";
attribute P_CONVERSION : integer;
attribute P_CONVERSION of inst : label is 2;
attribute P_DECERR : string;
attribute P_DECERR of inst : label is "2'b11";
attribute P_INCR : string;
attribute P_INCR of inst : label is "2'b01";
attribute P_PROTECTION : integer;
attribute P_PROTECTION of inst : label is 1;
attribute P_SLVERR : string;
attribute P_SLVERR of inst : label is "2'b10";
attribute X_INTERFACE_INFO : string;
attribute X_INTERFACE_INFO of aclk : signal is "xilinx.com:signal:clock:1.0 CLK CLK";
attribute X_INTERFACE_PARAMETER : string;
attribute X_INTERFACE_PARAMETER of aclk : signal is "XIL_INTERFACENAME CLK, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN led_controller_design_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN";
attribute X_INTERFACE_INFO of aresetn : signal is "xilinx.com:signal:reset:1.0 RST RST";
attribute X_INTERFACE_PARAMETER of aresetn : signal is "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, TYPE INTERCONNECT";
attribute X_INTERFACE_INFO of m_axi_arready : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARREADY";
attribute X_INTERFACE_INFO of m_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARVALID";
attribute X_INTERFACE_INFO of m_axi_awready : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWREADY";
attribute X_INTERFACE_INFO of m_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWVALID";
attribute X_INTERFACE_INFO of m_axi_bready : signal is "xilinx.com:interface:aximm:1.0 M_AXI BREADY";
attribute X_INTERFACE_INFO of m_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI BVALID";
attribute X_INTERFACE_INFO of m_axi_rready : signal is "xilinx.com:interface:aximm:1.0 M_AXI RREADY";
attribute X_INTERFACE_PARAMETER of m_axi_rready : signal is "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN led_controller_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
attribute X_INTERFACE_INFO of m_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI RVALID";
attribute X_INTERFACE_INFO of m_axi_wready : signal is "xilinx.com:interface:aximm:1.0 M_AXI WREADY";
attribute X_INTERFACE_INFO of m_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI WVALID";
attribute X_INTERFACE_INFO of s_axi_arready : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
attribute X_INTERFACE_INFO of s_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
attribute X_INTERFACE_INFO of s_axi_awready : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
attribute X_INTERFACE_INFO of s_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
attribute X_INTERFACE_INFO of s_axi_bready : signal is "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
attribute X_INTERFACE_INFO of s_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
attribute X_INTERFACE_INFO of s_axi_rlast : signal is "xilinx.com:interface:aximm:1.0 S_AXI RLAST";
attribute X_INTERFACE_INFO of s_axi_rready : signal is "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
attribute X_INTERFACE_PARAMETER of s_axi_rready : signal is "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN led_controller_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
attribute X_INTERFACE_INFO of s_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
attribute X_INTERFACE_INFO of s_axi_wlast : signal is "xilinx.com:interface:aximm:1.0 S_AXI WLAST";
attribute X_INTERFACE_INFO of s_axi_wready : signal is "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
attribute X_INTERFACE_INFO of s_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
attribute X_INTERFACE_INFO of m_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARADDR";
attribute X_INTERFACE_INFO of m_axi_arprot : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARPROT";
attribute X_INTERFACE_INFO of m_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWADDR";
attribute X_INTERFACE_INFO of m_axi_awprot : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWPROT";
attribute X_INTERFACE_INFO of m_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 M_AXI BRESP";
attribute X_INTERFACE_INFO of m_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 M_AXI RDATA";
attribute X_INTERFACE_INFO of m_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 M_AXI RRESP";
attribute X_INTERFACE_INFO of m_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 M_AXI WDATA";
attribute X_INTERFACE_INFO of m_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 M_AXI WSTRB";
attribute X_INTERFACE_INFO of s_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
attribute X_INTERFACE_INFO of s_axi_arburst : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARBURST";
attribute X_INTERFACE_INFO of s_axi_arcache : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE";
attribute X_INTERFACE_INFO of s_axi_arid : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARID";
attribute X_INTERFACE_INFO of s_axi_arlen : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARLEN";
attribute X_INTERFACE_INFO of s_axi_arlock : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK";
attribute X_INTERFACE_INFO of s_axi_arprot : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARPROT";
attribute X_INTERFACE_INFO of s_axi_arqos : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARQOS";
attribute X_INTERFACE_INFO of s_axi_arsize : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE";
attribute X_INTERFACE_INFO of s_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
attribute X_INTERFACE_INFO of s_axi_awburst : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWBURST";
attribute X_INTERFACE_INFO of s_axi_awcache : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE";
attribute X_INTERFACE_INFO of s_axi_awid : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWID";
attribute X_INTERFACE_INFO of s_axi_awlen : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWLEN";
attribute X_INTERFACE_INFO of s_axi_awlock : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK";
attribute X_INTERFACE_INFO of s_axi_awprot : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWPROT";
attribute X_INTERFACE_INFO of s_axi_awqos : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWQOS";
attribute X_INTERFACE_INFO of s_axi_awsize : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE";
attribute X_INTERFACE_INFO of s_axi_bid : signal is "xilinx.com:interface:aximm:1.0 S_AXI BID";
attribute X_INTERFACE_INFO of s_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
attribute X_INTERFACE_INFO of s_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
attribute X_INTERFACE_INFO of s_axi_rid : signal is "xilinx.com:interface:aximm:1.0 S_AXI RID";
attribute X_INTERFACE_INFO of s_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
attribute X_INTERFACE_INFO of s_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
attribute X_INTERFACE_INFO of s_axi_wid : signal is "xilinx.com:interface:aximm:1.0 S_AXI WID";
attribute X_INTERFACE_INFO of s_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
begin
inst: entity work.led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_axi_protocol_converter
port map (
aclk => aclk,
aresetn => aresetn,
m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_inst_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_inst_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(11 downto 0) => NLW_inst_m_axi_arid_UNCONNECTED(11 downto 0),
m_axi_arlen(7 downto 0) => NLW_inst_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_inst_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_inst_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arregion(3 downto 0) => NLW_inst_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_inst_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_inst_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_inst_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_inst_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(11 downto 0) => NLW_inst_m_axi_awid_UNCONNECTED(11 downto 0),
m_axi_awlen(7 downto 0) => NLW_inst_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_inst_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_inst_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awregion(3 downto 0) => NLW_inst_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_inst_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_inst_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => m_axi_awvalid,
m_axi_bid(11 downto 0) => B"000000000000",
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_buser(0) => '0',
m_axi_bvalid => m_axi_bvalid,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => B"000000000000",
m_axi_rlast => '1',
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_ruser(0) => '0',
m_axi_rvalid => m_axi_rvalid,
m_axi_wdata(31 downto 0) => m_axi_wdata(31 downto 0),
m_axi_wid(11 downto 0) => NLW_inst_m_axi_wid_UNCONNECTED(11 downto 0),
m_axi_wlast => NLW_inst_m_axi_wlast_UNCONNECTED,
m_axi_wready => m_axi_wready,
m_axi_wstrb(3 downto 0) => m_axi_wstrb(3 downto 0),
m_axi_wuser(0) => NLW_inst_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => m_axi_wvalid,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0),
s_axi_arlock(1 downto 0) => s_axi_arlock(1 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_aruser(0) => '0',
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0),
s_axi_awlock(1 downto 0) => s_axi_awlock(1 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awuser(0) => '0',
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wid(11 downto 0) => s_axi_wid(11 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wuser(0) => '0',
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
| mit | afe32579575cfb0ef3cd5c74dee46256 | 0.535795 | 2.557889 | false | false | false | false |
khaledhassan/vhdl-examples | pulse_emitter/pulse_emitter_tb.vhd | 1 | 2,273 | -- Testbench for simulation of the "pulse_emitter" entity
--
-- Copyright (c) 2012 Brian Nezvadovitz <http://nezzen.net>
-- This software is distributed under the terms of the MIT License shown below.
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to
-- deal in the Software without restriction, including without limitation the
-- rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
-- sell copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
-- IN THE SOFTWARE.
library ieee;
use ieee.std_logic_1164.all;
entity pulse_emitter_tb is
end pulse_emitter_tb;
architecture TB of pulse_emitter_tb is
signal clk, rst, en, output : std_logic;
constant clk_period : time := 20 ns; -- for a 50MHz clock
begin
-- Instantiate the Unit Under Test (UUT)
UUT : entity work.pulse_emitter
generic map (
MAX => 5
)
port map (
clk => clk,
rst => rst,
en => en,
output => output
);
-- Clock process
process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
process
begin
-- Hold reset state
rst <= '1';
wait for clk_period;
-- Release reset
rst <= '0';
en <= '1';
-- Perform the simulation
wait for clk_period*20;
wait;
end process;
end TB;
| mit | 57c59a39ab98bfabe225d839f4569dda | 0.646722 | 4.256554 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/leon3v3/libfpu.vhd | 1 | 4,618 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: libfpu
-- File: libfpu.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: LEON3 FPU interface types and components
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.leon3.all;
library techmap;
use techmap.gencomp.all;
package libfpu is
type fp_rf_in_type is record
rd1addr : std_logic_vector(3 downto 0); -- read address 1
rd2addr : std_logic_vector(3 downto 0); -- read address 2
wraddr : std_logic_vector(3 downto 0); -- write address
wrdata : std_logic_vector(31 downto 0); -- write data
ren1 : std_ulogic; -- read 1 enable
ren2 : std_ulogic; -- read 2 enable
wren : std_ulogic; -- write enable
end record;
type fp_rf_out_type is record
data1 : std_logic_vector(31 downto 0); -- read data 1
data2 : std_logic_vector(31 downto 0); -- read data 2
end record;
type fpc_pipeline_control_type is record
pc : std_logic_vector(31 downto 0);
inst : std_logic_vector(31 downto 0);
cnt : std_logic_vector(1 downto 0);
trap : std_ulogic;
annul : std_ulogic;
pv : std_ulogic;
end record;
type fpc_debug_in_type is record
enable : std_ulogic;
write : std_ulogic;
fsr : std_ulogic; -- FSR access
addr : std_logic_vector(4 downto 0);
data : std_logic_vector(31 downto 0);
end record;
type fpc_debug_out_type is record
data : std_logic_vector(31 downto 0);
end record;
constant fpc_debug_none : fpc_debug_out_type := (data => X"00000000"
);
type fpc_in_type is record
flush : std_ulogic; -- pipeline flush
exack : std_ulogic; -- FP exception acknowledge
a_rs1 : std_logic_vector(4 downto 0);
d : fpc_pipeline_control_type;
a : fpc_pipeline_control_type;
e : fpc_pipeline_control_type;
m : fpc_pipeline_control_type;
x : fpc_pipeline_control_type;
lddata : std_logic_vector(31 downto 0); -- load data
dbg : fpc_debug_in_type; -- debug signals
end record;
type fpc_out_type is record
data : std_logic_vector(31 downto 0); -- store data
exc : std_logic; -- FP exception
cc : std_logic_vector(1 downto 0); -- FP condition codes
ccv : std_ulogic; -- FP condition codes valid
ldlock : std_logic; -- FP pipeline hold
holdn : std_ulogic;
dbg : fpc_debug_out_type; -- FP debug signals
end record;
constant fpc_out_none : fpc_out_type := (X"00000000", '0', "00", '1', '0', '1',
fpc_debug_none);
component grfpwxsh
generic (
tech : integer range 0 to NTECH := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
id : integer range 0 to 7 := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi : in fpc_in_type;
cpo : out fpc_out_type;
fpui : out grfpu_in_type;
fpuo : in grfpu_out_type
);
end component;
end;
| gpl-2.0 | 9bcc4141376fb7c46b711ae4a5130601 | 0.542443 | 3.970765 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/ug871-design-files/Introduction/lab3/fir_prj/solution3/syn/vhdl/fir.vhd | 1 | 30,385 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity fir is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
y : OUT STD_LOGIC_VECTOR (31 downto 0);
y_ap_vld : OUT STD_LOGIC;
c_address0 : OUT STD_LOGIC_VECTOR (3 downto 0);
c_ce0 : OUT STD_LOGIC;
c_q0 : IN STD_LOGIC_VECTOR (31 downto 0);
x : IN STD_LOGIC_VECTOR (31 downto 0);
x_ap_vld : IN STD_LOGIC );
end;
architecture behav of fir is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"fir,hls_ip_2017_2,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=8.742000,HLS_SYN_LAT=14,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=44,HLS_SYN_FF=2961,HLS_SYN_LUT=1046}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (14 downto 0) := "000000000000001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (14 downto 0) := "000000000000010";
constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (14 downto 0) := "000000000000100";
constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (14 downto 0) := "000000000001000";
constant ap_ST_fsm_state5 : STD_LOGIC_VECTOR (14 downto 0) := "000000000010000";
constant ap_ST_fsm_state6 : STD_LOGIC_VECTOR (14 downto 0) := "000000000100000";
constant ap_ST_fsm_state7 : STD_LOGIC_VECTOR (14 downto 0) := "000000001000000";
constant ap_ST_fsm_state8 : STD_LOGIC_VECTOR (14 downto 0) := "000000010000000";
constant ap_ST_fsm_state9 : STD_LOGIC_VECTOR (14 downto 0) := "000000100000000";
constant ap_ST_fsm_state10 : STD_LOGIC_VECTOR (14 downto 0) := "000001000000000";
constant ap_ST_fsm_state11 : STD_LOGIC_VECTOR (14 downto 0) := "000010000000000";
constant ap_ST_fsm_state12 : STD_LOGIC_VECTOR (14 downto 0) := "000100000000000";
constant ap_ST_fsm_state13 : STD_LOGIC_VECTOR (14 downto 0) := "001000000000000";
constant ap_ST_fsm_state14 : STD_LOGIC_VECTOR (14 downto 0) := "010000000000000";
constant ap_ST_fsm_state15 : STD_LOGIC_VECTOR (14 downto 0) := "100000000000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001100";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv32_D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001101";
constant ap_const_lv64_A : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000001010";
constant ap_const_lv64_9 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000001001";
constant ap_const_lv64_8 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000001000";
constant ap_const_lv64_7 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000111";
constant ap_const_lv64_6 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000110";
constant ap_const_lv64_5 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000101";
constant ap_const_lv64_4 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000100";
constant ap_const_lv64_3 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000011";
constant ap_const_lv64_2 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000010";
constant ap_const_lv64_1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001";
constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_lv32_E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001110";
constant ap_const_boolean_1 : BOOLEAN := true;
signal ap_CS_fsm : STD_LOGIC_VECTOR (14 downto 0) := "000000000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal x_preg : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal x_in_sig : STD_LOGIC_VECTOR (31 downto 0);
signal x_ap_vld_preg : STD_LOGIC := '0';
signal x_ap_vld_in_sig : STD_LOGIC;
signal shift_reg_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal shift_reg_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal shift_reg_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal shift_reg_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal shift_reg_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal shift_reg_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal shift_reg_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal shift_reg_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal shift_reg_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal shift_reg_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal x_blk_n : STD_LOGIC;
signal ap_CS_fsm_state13 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state13 : signal is "none";
signal reg_188 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
signal ap_CS_fsm_state5 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state5 : signal is "none";
signal ap_CS_fsm_state8 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state8 : signal is "none";
signal ap_CS_fsm_state11 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state11 : signal is "none";
signal reg_192 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state3 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state3 : signal is "none";
signal ap_CS_fsm_state6 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state6 : signal is "none";
signal ap_CS_fsm_state9 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state9 : signal is "none";
signal ap_CS_fsm_state12 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state12 : signal is "none";
signal reg_196 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state4 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state4 : signal is "none";
signal ap_CS_fsm_state10 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state10 : signal is "none";
signal grp_fu_204_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_6_reg_442 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_220_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_6_1_reg_447 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp1_fu_226_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp1_reg_462 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state7 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state7 : signal is "none";
signal c_load_5_reg_482 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_240_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_6_2_reg_492 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_256_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_6_3_reg_497 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_272_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_6_4_reg_502 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp2_fu_282_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp2_reg_517 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_297_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_6_5_reg_542 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_312_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_6_6_reg_547 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_328_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_6_7_reg_552 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp6_fu_334_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp6_reg_562 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_348_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_6_8_reg_582 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state14 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state14 : signal is "none";
signal grp_fu_364_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_6_9_reg_587 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_376_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_6_s_reg_592 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state15 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state15 : signal is "none";
signal tmp3_fu_278_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp8_fu_390_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp7_fu_394_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp5_fu_386_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp4_fu_399_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_fu_382_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_348_ce : STD_LOGIC;
signal grp_fu_364_ce : STD_LOGIC;
signal grp_fu_376_ce : STD_LOGIC;
signal ap_NS_fsm : STD_LOGIC_VECTOR (14 downto 0);
component fir_mul_32s_32s_3bkb IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
begin
fir_mul_32s_32s_3bkb_U1 : component fir_mul_32s_32s_3bkb
generic map (
ID => 1,
NUM_STAGE => 2,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => shift_reg_9,
din1 => reg_188,
ce => ap_const_logic_1,
dout => grp_fu_204_p2);
fir_mul_32s_32s_3bkb_U2 : component fir_mul_32s_32s_3bkb
generic map (
ID => 1,
NUM_STAGE => 2,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => shift_reg_8,
din1 => reg_192,
ce => ap_const_logic_1,
dout => grp_fu_220_p2);
fir_mul_32s_32s_3bkb_U3 : component fir_mul_32s_32s_3bkb
generic map (
ID => 1,
NUM_STAGE => 2,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => shift_reg_7,
din1 => reg_196,
ce => ap_const_logic_1,
dout => grp_fu_240_p2);
fir_mul_32s_32s_3bkb_U4 : component fir_mul_32s_32s_3bkb
generic map (
ID => 1,
NUM_STAGE => 2,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => shift_reg_6,
din1 => reg_188,
ce => ap_const_logic_1,
dout => grp_fu_256_p2);
fir_mul_32s_32s_3bkb_U5 : component fir_mul_32s_32s_3bkb
generic map (
ID => 1,
NUM_STAGE => 2,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => shift_reg_5,
din1 => reg_192,
ce => ap_const_logic_1,
dout => grp_fu_272_p2);
fir_mul_32s_32s_3bkb_U6 : component fir_mul_32s_32s_3bkb
generic map (
ID => 1,
NUM_STAGE => 2,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => shift_reg_4,
din1 => c_load_5_reg_482,
ce => ap_const_logic_1,
dout => grp_fu_297_p2);
fir_mul_32s_32s_3bkb_U7 : component fir_mul_32s_32s_3bkb
generic map (
ID => 1,
NUM_STAGE => 2,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => shift_reg_3,
din1 => reg_188,
ce => ap_const_logic_1,
dout => grp_fu_312_p2);
fir_mul_32s_32s_3bkb_U8 : component fir_mul_32s_32s_3bkb
generic map (
ID => 1,
NUM_STAGE => 2,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => shift_reg_2,
din1 => reg_192,
ce => ap_const_logic_1,
dout => grp_fu_328_p2);
fir_mul_32s_32s_3bkb_U9 : component fir_mul_32s_32s_3bkb
generic map (
ID => 1,
NUM_STAGE => 2,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => shift_reg_1,
din1 => reg_196,
ce => grp_fu_348_ce,
dout => grp_fu_348_p2);
fir_mul_32s_32s_3bkb_U10 : component fir_mul_32s_32s_3bkb
generic map (
ID => 1,
NUM_STAGE => 2,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => shift_reg_0,
din1 => reg_188,
ce => grp_fu_364_ce,
dout => grp_fu_364_p2);
fir_mul_32s_32s_3bkb_U11 : component fir_mul_32s_32s_3bkb
generic map (
ID => 1,
NUM_STAGE => 2,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => reg_192,
din1 => x_in_sig,
ce => grp_fu_376_ce,
dout => grp_fu_376_p2);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
x_ap_vld_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
x_ap_vld_preg <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_CS_fsm_state15)) then
x_ap_vld_preg <= ap_const_logic_0;
elsif (((ap_const_logic_1 = x_ap_vld) and not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))))) then
x_ap_vld_preg <= x_ap_vld;
end if;
end if;
end if;
end process;
x_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
x_preg <= ap_const_lv32_0;
else
if (((ap_const_logic_1 = x_ap_vld) and not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))))) then
x_preg <= x;
end if;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state7)) then
c_load_5_reg_482 <= c_q0;
shift_reg_6 <= shift_reg_5;
shift_reg_7 <= shift_reg_6;
shift_reg_8 <= shift_reg_7;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state2) or (ap_const_logic_1 = ap_CS_fsm_state5) or (ap_const_logic_1 = ap_CS_fsm_state8) or (ap_const_logic_1 = ap_CS_fsm_state11))) then
reg_188 <= c_q0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state3) or (ap_const_logic_1 = ap_CS_fsm_state6) or (ap_const_logic_1 = ap_CS_fsm_state9) or (ap_const_logic_1 = ap_CS_fsm_state12))) then
reg_192 <= c_q0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state4) or (ap_const_logic_1 = ap_CS_fsm_state10))) then
reg_196 <= c_q0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state13) and (x_ap_vld_in_sig = ap_const_logic_1))) then
shift_reg_0 <= x_in_sig;
shift_reg_1 <= shift_reg_0;
shift_reg_2 <= shift_reg_1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state10)) then
shift_reg_3 <= shift_reg_2;
shift_reg_4 <= shift_reg_3;
shift_reg_5 <= shift_reg_4;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state4)) then
shift_reg_9 <= shift_reg_8;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state6)) then
tmp1_reg_462 <= tmp1_fu_226_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state9)) then
tmp2_reg_517 <= tmp2_fu_282_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state12)) then
tmp6_reg_562 <= tmp6_fu_334_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state5)) then
tmp_6_1_reg_447 <= grp_fu_220_p2;
tmp_6_reg_442 <= grp_fu_204_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state8)) then
tmp_6_2_reg_492 <= grp_fu_240_p2;
tmp_6_3_reg_497 <= grp_fu_256_p2;
tmp_6_4_reg_502 <= grp_fu_272_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state11)) then
tmp_6_5_reg_542 <= grp_fu_297_p2;
tmp_6_6_reg_547 <= grp_fu_312_p2;
tmp_6_7_reg_552 <= grp_fu_328_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state14)) then
tmp_6_8_reg_582 <= grp_fu_348_p2;
tmp_6_9_reg_587 <= grp_fu_364_p2;
tmp_6_s_reg_592 <= grp_fu_376_p2;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, x_ap_vld_in_sig, ap_CS_fsm_state13)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
ap_NS_fsm <= ap_ST_fsm_state3;
when ap_ST_fsm_state3 =>
ap_NS_fsm <= ap_ST_fsm_state4;
when ap_ST_fsm_state4 =>
ap_NS_fsm <= ap_ST_fsm_state5;
when ap_ST_fsm_state5 =>
ap_NS_fsm <= ap_ST_fsm_state6;
when ap_ST_fsm_state6 =>
ap_NS_fsm <= ap_ST_fsm_state7;
when ap_ST_fsm_state7 =>
ap_NS_fsm <= ap_ST_fsm_state8;
when ap_ST_fsm_state8 =>
ap_NS_fsm <= ap_ST_fsm_state9;
when ap_ST_fsm_state9 =>
ap_NS_fsm <= ap_ST_fsm_state10;
when ap_ST_fsm_state10 =>
ap_NS_fsm <= ap_ST_fsm_state11;
when ap_ST_fsm_state11 =>
ap_NS_fsm <= ap_ST_fsm_state12;
when ap_ST_fsm_state12 =>
ap_NS_fsm <= ap_ST_fsm_state13;
when ap_ST_fsm_state13 =>
if (((ap_const_logic_1 = ap_CS_fsm_state13) and (x_ap_vld_in_sig = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state14;
else
ap_NS_fsm <= ap_ST_fsm_state13;
end if;
when ap_ST_fsm_state14 =>
ap_NS_fsm <= ap_ST_fsm_state15;
when ap_ST_fsm_state15 =>
ap_NS_fsm <= ap_ST_fsm_state1;
when others =>
ap_NS_fsm <= "XXXXXXXXXXXXXXX";
end case;
end process;
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state10 <= ap_CS_fsm(9);
ap_CS_fsm_state11 <= ap_CS_fsm(10);
ap_CS_fsm_state12 <= ap_CS_fsm(11);
ap_CS_fsm_state13 <= ap_CS_fsm(12);
ap_CS_fsm_state14 <= ap_CS_fsm(13);
ap_CS_fsm_state15 <= ap_CS_fsm(14);
ap_CS_fsm_state2 <= ap_CS_fsm(1);
ap_CS_fsm_state3 <= ap_CS_fsm(2);
ap_CS_fsm_state4 <= ap_CS_fsm(3);
ap_CS_fsm_state5 <= ap_CS_fsm(4);
ap_CS_fsm_state6 <= ap_CS_fsm(5);
ap_CS_fsm_state7 <= ap_CS_fsm(6);
ap_CS_fsm_state8 <= ap_CS_fsm(7);
ap_CS_fsm_state9 <= ap_CS_fsm(8);
ap_done_assign_proc : process(ap_CS_fsm_state15)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state15)) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(ap_CS_fsm_state15)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state15)) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
c_address0_assign_proc : process(ap_CS_fsm_state1, ap_CS_fsm_state2, ap_CS_fsm_state5, ap_CS_fsm_state8, ap_CS_fsm_state11, ap_CS_fsm_state3, ap_CS_fsm_state6, ap_CS_fsm_state9, ap_CS_fsm_state4, ap_CS_fsm_state10, ap_CS_fsm_state7)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state11)) then
c_address0 <= ap_const_lv64_0(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state10)) then
c_address0 <= ap_const_lv64_1(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state9)) then
c_address0 <= ap_const_lv64_2(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state8)) then
c_address0 <= ap_const_lv64_3(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state7)) then
c_address0 <= ap_const_lv64_4(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state6)) then
c_address0 <= ap_const_lv64_5(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state5)) then
c_address0 <= ap_const_lv64_6(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state4)) then
c_address0 <= ap_const_lv64_7(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state3)) then
c_address0 <= ap_const_lv64_8(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then
c_address0 <= ap_const_lv64_9(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state1)) then
c_address0 <= ap_const_lv64_A(4 - 1 downto 0);
else
c_address0 <= "XXXX";
end if;
end process;
c_ce0_assign_proc : process(ap_start, ap_CS_fsm_state1, ap_CS_fsm_state2, ap_CS_fsm_state5, ap_CS_fsm_state8, ap_CS_fsm_state11, ap_CS_fsm_state3, ap_CS_fsm_state6, ap_CS_fsm_state9, ap_CS_fsm_state4, ap_CS_fsm_state10, ap_CS_fsm_state7)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) or (ap_const_logic_1 = ap_CS_fsm_state5) or (ap_const_logic_1 = ap_CS_fsm_state8) or (ap_const_logic_1 = ap_CS_fsm_state11) or (ap_const_logic_1 = ap_CS_fsm_state3) or (ap_const_logic_1 = ap_CS_fsm_state6) or (ap_const_logic_1 = ap_CS_fsm_state9) or (ap_const_logic_1 = ap_CS_fsm_state4) or (ap_const_logic_1 = ap_CS_fsm_state10) or ((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1)) or (ap_const_logic_1 = ap_CS_fsm_state7))) then
c_ce0 <= ap_const_logic_1;
else
c_ce0 <= ap_const_logic_0;
end if;
end process;
grp_fu_348_ce_assign_proc : process(x_ap_vld_in_sig, ap_CS_fsm_state13, ap_CS_fsm_state14)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_state13) and (x_ap_vld_in_sig = ap_const_logic_1)) or (ap_const_logic_1 = ap_CS_fsm_state14))) then
grp_fu_348_ce <= ap_const_logic_1;
else
grp_fu_348_ce <= ap_const_logic_0;
end if;
end process;
grp_fu_364_ce_assign_proc : process(x_ap_vld_in_sig, ap_CS_fsm_state13, ap_CS_fsm_state14)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_state13) and (x_ap_vld_in_sig = ap_const_logic_1)) or (ap_const_logic_1 = ap_CS_fsm_state14))) then
grp_fu_364_ce <= ap_const_logic_1;
else
grp_fu_364_ce <= ap_const_logic_0;
end if;
end process;
grp_fu_376_ce_assign_proc : process(x_ap_vld_in_sig, ap_CS_fsm_state13, ap_CS_fsm_state14)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_state13) and (x_ap_vld_in_sig = ap_const_logic_1)) or (ap_const_logic_1 = ap_CS_fsm_state14))) then
grp_fu_376_ce <= ap_const_logic_1;
else
grp_fu_376_ce <= ap_const_logic_0;
end if;
end process;
tmp1_fu_226_p2 <= std_logic_vector(unsigned(tmp_6_reg_442) + unsigned(tmp_6_1_reg_447));
tmp2_fu_282_p2 <= std_logic_vector(unsigned(tmp3_fu_278_p2) + unsigned(tmp_6_2_reg_492));
tmp3_fu_278_p2 <= std_logic_vector(unsigned(tmp_6_3_reg_497) + unsigned(tmp_6_4_reg_502));
tmp4_fu_399_p2 <= std_logic_vector(unsigned(tmp7_fu_394_p2) + unsigned(tmp5_fu_386_p2));
tmp5_fu_386_p2 <= std_logic_vector(unsigned(tmp6_reg_562) + unsigned(tmp_6_5_reg_542));
tmp6_fu_334_p2 <= std_logic_vector(unsigned(tmp_6_6_reg_547) + unsigned(tmp_6_7_reg_552));
tmp7_fu_394_p2 <= std_logic_vector(unsigned(tmp8_fu_390_p2) + unsigned(tmp_6_8_reg_582));
tmp8_fu_390_p2 <= std_logic_vector(unsigned(tmp_6_9_reg_587) + unsigned(tmp_6_s_reg_592));
tmp_fu_382_p2 <= std_logic_vector(unsigned(tmp2_reg_517) + unsigned(tmp1_reg_462));
x_ap_vld_in_sig_assign_proc : process(x_ap_vld, x_ap_vld_preg)
begin
if ((ap_const_logic_1 = x_ap_vld)) then
x_ap_vld_in_sig <= x_ap_vld;
else
x_ap_vld_in_sig <= x_ap_vld_preg;
end if;
end process;
x_blk_n_assign_proc : process(x_ap_vld, ap_CS_fsm_state13)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state13)) then
x_blk_n <= x_ap_vld;
else
x_blk_n <= ap_const_logic_1;
end if;
end process;
x_in_sig_assign_proc : process(x, x_preg, x_ap_vld)
begin
if ((ap_const_logic_1 = x_ap_vld)) then
x_in_sig <= x;
else
x_in_sig <= x_preg;
end if;
end process;
y <= std_logic_vector(unsigned(tmp4_fu_399_p2) + unsigned(tmp_fu_382_p2));
y_ap_vld_assign_proc : process(ap_CS_fsm_state15)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state15)) then
y_ap_vld <= ap_const_logic_1;
else
y_ap_vld <= ap_const_logic_0;
end if;
end process;
end behav;
| mit | 6c1bcd326a843fc3040b53e971aaca1a | 0.576534 | 3.064549 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-gr-pci-xc5v/leon3mp.vhd | 1 | 39,427 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.can.all;
use gaisler.pci.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.spacewire.all;
use gaisler.grusb.all;
library esa;
use esa.memoryctrl.all;
use esa.pcicomp.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_logic;
clk : in std_logic;
pllref : in std_logic;
errorn : out std_logic;
wdogn : out std_logic;
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
sa : out std_logic_vector(14 downto 0);
sd : inout std_logic_vector(63 downto 0);
sdclk : out std_logic;
sdcke : out std_logic_vector (1 downto 0); -- sdram clock enable
sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
sdwen : out std_logic; -- sdram write enable
sdrasn : out std_logic; -- sdram ras
sdcasn : out std_logic; -- sdram cas
sddqm : out std_logic_vector (7 downto 0); -- sdram dqm
dsutx : out std_logic; -- DSU tx data
dsurx : in std_logic; -- DSU rx data
dsuen : in std_logic;
dsubre : in std_logic;
dsuact : out std_logic;
txd1 : out std_logic; -- UART1 tx data
rxd1 : in std_logic; -- UART1 rx data
txd2 : out std_logic; -- UART2 tx data
rxd2 : in std_logic; -- UART2 rx data
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_logic;
writen : out std_logic;
read : out std_logic;
iosn : out std_logic;
romsn : out std_logic_vector (1 downto 0);
brdyn : in std_logic; -- bus ready
bexcn : in std_logic; -- bus exception
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
emdio : inout std_logic; -- ethernet PHY interface
eth_macclk : in std_logic;
etx_clk : in std_logic;
erx_clk : in std_logic;
erxd : in std_logic_vector(7 downto 0);
erx_dv : in std_logic;
erx_er : in std_logic;
erx_col : in std_logic;
erx_crs : in std_logic;
emdintn : in std_logic;
etxd : out std_logic_vector(7 downto 0);
etx_en : out std_logic;
etx_er : out std_logic;
emdc : out std_logic;
pci_rst : inout std_logic; -- PCI bus
pci_clk : in std_logic;
pci_gnt : in std_logic;
pci_idsel : in std_logic;
pci_lock : inout std_logic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_logic;
pci_irdy : inout std_logic;
pci_trdy : inout std_logic;
pci_devsel : inout std_logic;
pci_stop : inout std_logic;
pci_perr : inout std_logic;
pci_par : inout std_logic;
pci_req : inout std_logic;
pci_serr : inout std_logic;
pci_host : in std_logic;
pci_66 : in std_logic;
pci_arb_req : in std_logic_vector(0 to 3);
pci_arb_gnt : out std_logic_vector(0 to 3);
can_txd : out std_logic_vector(0 to CFG_CAN_NUM-1);
can_rxd : in std_logic_vector(0 to CFG_CAN_NUM-1);
-- can_stb : out std_logic_vector(0 to CFG_CAN_NUM-1)
spw_clk : in std_logic;
spw_rxdp : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxdn : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxsp : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxsn : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txdp : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txdn : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txsp : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txsn : out std_logic_vector(0 to CFG_SPW_NUM-1);
usb_clkout : in std_logic;
usb_d : inout std_logic_vector(7 downto 0);
usb_nxt : in std_logic;
usb_stp : out std_logic;
usb_dir : in std_logic;
usb_resetn : out std_ulogic
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, pciclk, sdclkl : std_logic;
signal cgi, cgi2 : clkgen_in_type;
signal cgo, cgo2 : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal pcii : pci_in_type;
signal pcio : pci_out_type;
signal spwi : grspw_in_type_vector(0 to CFG_SPW_NUM-1);
signal spwo : grspw_out_type_vector(0 to CFG_SPW_NUM-1);
signal spw_clkl : std_logic;
signal spw_rxclk : std_logic_vector(0 to CFG_SPW_NUM-1);
signal dtmp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal stmp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_rxtxclk : std_ulogic;
signal spw_rxclkn : std_ulogic;
signal stati : ahbstat_in_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal ethclk, egtx_clk_fb : std_logic;
signal egtx_clk, legtx_clk, l2egtx_clk : std_logic;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal wdog : std_logic;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal clklock, elock, ulock : std_ulogic;
signal can_lrx, can_ltx : std_logic_vector(0 to 7);
signal lclk, pci_lclk : std_logic;
signal pci_arb_req_n, pci_arb_gnt_n : std_logic_vector(0 to 3);
signal tck, tms, tdi, tdo : std_logic;
signal usbi : grusb_in_vector(0 downto 0);
signal usbo : grusb_out_vector(0 downto 0);
signal uclk : std_ulogic := '0';
signal fpi : grfpu_in_vector_type;
signal fpo : grfpu_out_vector_type;
constant BOARD_FREQ : integer := 50000; -- Board frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant IOAEN : integer := CFG_CAN + CFG_PCI + CFG_GRUSBHC +
CFG_GRUSBDC;
constant CFG_SDEN : integer := CFG_MCTRL_SDEN;
constant CFG_INVCLK : integer := CFG_MCTRL_INVCLK;
constant OEPOL : integer := padoen_polarity(padtech);
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute keep : boolean;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
pllref_pad : clkpad generic map (tech => padtech) port map (pllref, cgi.pllref);
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
pci_clk_pad : clkpad generic map (tech => padtech, level => pci33)
port map (pci_clk, pci_lclk);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_SDEN,
CFG_INVCLK, CFG_PCI, CFG_PCIDLL, CFG_PCISYSCLK, BOARD_FREQ)
port map (lclk, pci_lclk, clkm, open, open, sdclkl, pciclk, cgi, cgo);
sdclk_pad : outpad generic map (tech => padtech, slew => 1)
port map (sdclk, sdclkl);
rst0 : rstgen -- reset generator
port map (resetn, clkm, clklock, rstn, rstraw);
clklock <= cgo.clklock and elock and ulock;
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => IOAEN,
nahbm => CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG+
CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM+
CFG_GRUSBHC*(CFG_GRUSBHC_EHC+CFG_GRUSBHC_UHC)+
CFG_GRUSBDC*CFG_GRUSBDC_AIFACE+
CFG_GRUSB_DCL,
nahbs => 8+CFG_GRUSBHC*CFG_GRUSBHC_UHC+CFG_GRUSBDC)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
cpu : for i in 0 to CFG_NCPU-1 generate
nosh : if CFG_GRFPUSH = 0 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
0, 0, CFG_MMU_PAGE, CFG_BP)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
end generate;
sh : if CFG_GRFPUSH = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3sh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
0, 0, CFG_MMU_PAGE, CFG_BP)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), fpi(i), fpo(i));
end generate;
grfpush0 : grfpushwx generic map ((CFG_FPU-1), CFG_NCPU, fabtech)
port map (clkm, rstn, fpi, fpo);
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
end generate;
-- nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.edac <= gpioo.val(2); memi.bwidth <= gpioo.val(1 downto 0);
mctrl0 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
srbanks => 4, sden => CFG_MCTRL_SDEN, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, invclk => CFG_MCTRL_INVCLK,
sepbus => CFG_MCTRL_SEPBUS, oepol => OEPOL,
sdbits => 32 + 32*CFG_MCTRL_SD64, pageburst => CFG_MCTRL_PAGE)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
addr_pad : outpadv generic map (width => 28, tech => padtech)
port map (address, memo.address(27 downto 0));
rams_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramsn, memo.ramsn(4 downto 0));
roms_pad : outpadv generic map (width => 2, tech => padtech)
port map (romsn, memo.romsn(1 downto 0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
rwen_pad : outpadv generic map (width => 4, tech => padtech)
port map (rwen, memo.wrn);
roen_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramoen, memo.ramoen(4 downto 0));
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
read_pad : outpad generic map (tech => padtech)
port map (read, memo.read);
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
data_pad : iopadvv generic map (tech => padtech, width => 32, oepol => OEPOL)
port map (data, memo.data, memo.vbdrive, memi.data);
brdyn_pad : inpad generic map (tech => padtech) port map (brdyn, memi.brdyn);
bexcn_pad : inpad generic map (tech => padtech) port map (bexcn, memi.bexcn);
memi.writen <= '1'; memi.wrn <= "1111";
sdpads : if CFG_MCTRL_SDEN = 1 generate -- SDRAM controller
sd2 : if CFG_MCTRL_SEPBUS = 1 generate
sa_pad : outpadv generic map (width => 15) port map (sa, memo.sa);
sd_pad : iopadvv generic map (tech => padtech, width => 32, oepol => OEPOL)
port map (sd(31 downto 0), memo.sddata(31 downto 0),
memo.svbdrive(31 downto 0), memi.sd(31 downto 0));
sd2 : if CFG_MCTRL_SD64 = 1 generate
sd_pad2 : iopadvv generic map (tech => padtech, width => 32)
port map (sd(63 downto 32), memo.data(31 downto 0),
memo.svbdrive(63 downto 32), memi.sd(63 downto 32));
end generate;
end generate;
sdwen_pad : outpad generic map (tech => padtech)
port map (sdwen, sdo.sdwen);
sdras_pad : outpad generic map (tech => padtech)
port map (sdrasn, sdo.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (sdcasn, sdo.casn);
sddqm_pad : outpadv generic map (width => 8, tech => padtech)
port map (sddqm, sdo.dqm);
sdcke_pad : outpadv generic map (width => 2, tech => padtech)
port map (sdcke, sdo.sdcke);
sdcsn_pad : outpadv generic map (width => 2, tech => padtech)
port map (sdcsn, sdo.sdcsn);
end generate;
end generate;
nosd0 : if (CFG_SDEN = 0) generate -- no SDRAM controller
sdcke_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcke, vcc(1 downto 0));
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, vcc(1 downto 0));
end generate;
mg0 : if CFG_MCTRL_LEON2 = 0 generate -- No PROM/SRAM controller
apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
rams_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramsn, vcc);
roms_pad : outpadv generic map (width => 2, tech => padtech)
port map (romsn, vcc(1 downto 0));
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1; u1i.ctsn <= '0'; u1i.extclk <= '0'; txd1 <= u1o.txd;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
ua2 : if CFG_UART2_ENABLE /= 0 generate
uart2 : apbuart -- UART 2
generic map (pindex => 6, paddr => 6, pirq => 3, fifosize => CFG_UART2_FIFO)
port map (rstn, clkm, apbi, apbo(6), u2i, u2o);
u2i.rxd <= rxd2; u2i.ctsn <= '0'; u2i.extclk <= '0'; txd2 <= u2o.txd;
end generate;
noua1 : if CFG_UART2_ENABLE = 0 generate apbo(6) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
-- apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
wdog <= gpto.wdogn when OEPOL = 0 else gpto.wdog;
wdogn_pad : odpad generic map (tech => padtech, oepol => OEPOL) port map (wdogn, wdog);
end generate;
-- notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
grgpio0: grgpio
generic map( pindex => 9, paddr => 9, imask => CFG_GRGPIO_IMASK,
nbits => CFG_GRGPIO_WIDTH)
port map( rstn, clkm, apbi, apbo(9), gpioi, gpioo);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
stati.cerror(0) <= memo.ce;
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 1,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
nop2 : if CFG_AHBSTAT = 0 generate apbo(15) <= apb_none; end generate;
-----------------------------------------------------------------------
--- PCI ------------------------------------------------------------
-----------------------------------------------------------------------
pp : if CFG_PCI /= 0 generate
pci_gr0 : if CFG_PCI = 1 generate -- simple target-only
pci0 : pci_target generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
device_id => CFG_PCIDID, vendor_id => CFG_PCIVID, nsync => 2)
port map (rstn, clkm, pciclk, pcii, pcio, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG));
end generate;
pci_mtf0 : if CFG_PCI = 2 generate -- master/target with fifo
pci0 : pci_mtf generic map (memtech => memtech, hmstndx => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
fifodepth => log2(CFG_PCIDEPTH), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID,
hslvndx => 4, pindex => 4, paddr => 4, haddr => 16#E00#,
ioaddr => 16#400#, nsync => 2, hostrst => 1)
port map (rstn, clkm, pciclk, pcii, pcio, apbi, apbo(4),
ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbsi, ahbso(4));
end generate;
pci_mtf1 : if CFG_PCI = 3 generate -- master/target with fifo and DMA
dma : pcidma generic map (memtech => memtech, dmstndx => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1,
dapbndx => 5, dapbaddr => 5, blength => blength, mstndx => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
fifodepth => log2(fifodepth), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID,
slvndx => 4, apbndx => 4, apbaddr => 4, haddr => 16#E00#, ioaddr => 16#800#,
nsync => 2, hostrst => 1)
port map (rstn, clkm, pciclk, pcii, pcio, apbo(5), ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1),
apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbsi, ahbso(4));
end generate;
pci_trc0 : if CFG_PCITBUFEN /= 0 generate -- PCI trace buffer
pt0 : pcitrace generic map (depth => (6 + log2(CFG_PCITBUF/256)),
memtech => memtech, pindex => 8, paddr => 16#100#, pmask => 16#f00#)
port map ( rstn, clkm, pciclk, pcii, apbi, apbo(8));
end generate;
pcia0 : if CFG_PCI_ARB = 1 generate -- PCI arbiter
pciarb0 : pciarb generic map (pindex => 8, paddr => 8,
apb_en => CFG_PCI_ARBAPB)
port map ( clk => pciclk, rst_n => pcii.rst,
req_n => pci_arb_req_n, frame_n => pcii.frame,
gnt_n => pci_arb_gnt_n, pclk => clkm,
prst_n => rstn, apbi => apbi, apbo => apbo(10)
);
pgnt_pad : outpadv generic map (tech => padtech, width => 4)
port map (pci_arb_gnt, pci_arb_gnt_n);
preq_pad : inpadv generic map (tech => padtech, width => 4)
port map (pci_arb_req, pci_arb_req_n);
end generate;
pcipads0 : pcipads generic map (padtech => padtech, host => 0) -- PCI pads
port map ( pci_rst, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr,
pci_par, pci_req, pci_serr, pci_host, pci_66, pcii, pcio );
end generate;
-- nop1 : if CFG_PCI <= 1 generate apbo(4) <= apb_none; end generate;
-- nop2 : if CFG_PCI <= 2 generate apbo(5) <= apb_none; end generate;
-- nop3 : if CFG_PCI <= 1 generate ahbso(4) <= ahbs_none; end generate;
-- notrc : if CFG_PCITBUFEN = 0 generate apbo(8) <= apb_none; end generate;
-- noarb : if CFG_PCI_ARB = 0 generate apbo(10) <= apb_none; end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth1 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(
hindex => CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG,
pindex => 14, paddr => 14, pirq => 7, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 1,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G,
enable_mdint => 1)
port map(
rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG), apbi => apbi,
apbo => apbo(14), ethi => ethi, etho => etho);
greth1g: if CFG_GRETH1G = 1 generate
eth_macclk_pad : clkpad
generic map (tech => padtech, arch => 3, hf => 1)
port map (eth_macclk, egtx_clk, cgo.clklock, elock);
end generate greth1g;
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (etx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 8)
port map (erxd, ethi.rxd(7 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
emdintn_pad : inpad generic map (tech => padtech)
port map (emdintn, ethi.mdint);
etxd_pad : outpadv generic map (tech => padtech, width => 8)
port map (etxd, etho.txd(7 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
-- emdis_pad : outpad generic map (tech => padtech)
-- port map (emddis, vcc(0));
-- eepwrdwn_pad : outpad generic map (tech => padtech)
-- port map (epwrdwn, gnd(0));
-- esleep_pad : outpad generic map (tech => padtech)
-- port map (esleep, gnd(0));
-- epause_pad : outpad generic map (tech => padtech)
-- port map (epause, gnd(0));
-- ereset_pad : outpad generic map (tech => padtech)
-- port map (ereset, gnd(0));
ethi.gtx_clk <= egtx_clk;
end generate;
noeth: if CFG_GRETH = 0 or CFG_GRETH1G = 0 generate
elock <= '1';
end generate noeth;
-----------------------------------------------------------------------
--- CAN --------------------------------------------------------------
-----------------------------------------------------------------------
can0 : if CFG_CAN = 1 generate
can0 : can_mc generic map (slvndx => 6, ioaddr => CFG_CANIO,
iomask => 16#FF0#, irq => CFG_CANIRQ, memtech => memtech,
ncores => CFG_CAN_NUM, sepirq => CFG_CANSEPIRQ)
port map (rstn, clkm, ahbsi, ahbso(6), can_lrx, can_ltx );
can_pads : for i in 0 to CFG_CAN_NUM-1 generate
can_tx_pad : outpad generic map (tech => padtech)
port map (can_txd(i), can_ltx(i));
can_rx_pad : inpad generic map (tech => padtech)
port map (can_rxd(i), can_lrx(i));
end generate;
end generate;
-- can_stb <= '0'; -- no standby
ncan : if CFG_CAN = 0 generate ahbso(6) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
-- ocram : if CFG_AHBRAMEN = 1 generate
-- ahbram0 : ftahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
-- tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pindex => 6,
-- paddr => 6, edacen => CFG_AHBRAEDAC, autoscrub => CFG_AHBRASCRU,
-- errcnten => CFG_AHBRAECNT, cntbits => CFG_AHBRAEBIT)
-- port map ( rstn, clkm, ahbsi, ahbso(7), apbi, apbo(6), open);
-- end generate;
--
-- nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- SPACEWIRE -------------------------------------------------------
-----------------------------------------------------------------------
spw : if CFG_SPW_EN > 0 generate
spw_clk_pad : clkpad generic map (tech => padtech) port map (spw_clk, spw_clkl);
-- spw_clkl <= pciclk;
spw_rxtxclk <= spw_clkl;
spw_rxclkn <= not spw_rxtxclk;
swloop : for i in 0 to CFG_SPW_NUM-1 generate
-- GRSPW2 PHY
spw2_input : if CFG_SPW_GRSPW = 2 generate
spw_phy0 : grspw2_phy
generic map(
scantest => 0,
tech => fabtech,
input_type => CFG_SPW_INPUT)
port map(
rstn => rstn,
rxclki => spw_rxtxclk,
rxclkin => spw_rxclkn,
nrxclki => spw_rxtxclk,
di => dtmp(i),
si => stmp(i),
do => spwi(i).d(1 downto 0),
dov => spwi(i).dv(1 downto 0),
dconnect => spwi(i).dconnect(1 downto 0),
rxclko => spw_rxclk(i));
spwi(i).nd <= (others => '0'); -- Only used in GRSPW
spwi(i).dv(3 downto 2) <= "00"; -- For second port
end generate spw2_input;
-- GRSPW PHY
spw1_input: if CFG_SPW_GRSPW = 1 generate
spw_phy0 : grspw_phy
generic map(
tech => fabtech,
rxclkbuftype => 1,
scantest => 0)
port map(
rxrst => spwo(i).rxrst,
di => dtmp(i),
si => stmp(i),
rxclko => spw_rxclk(i),
do => spwi(i).d(0),
ndo => spwi(i).nd(4 downto 0),
dconnect => spwi(i).dconnect(1 downto 0));
spwi(i).d(1) <= '0';
spwi(i).dv <= (others => '0'); -- Only used in GRSPW2
spwi(i).nd(9 downto 5) <= "00000"; -- For second port
end generate spw1_input;
spwi(i).d(3 downto 2) <= "00"; -- For second port
spwi(i).dconnect(3 downto 2) <= "00"; -- For second port
spwi(i).s(1 downto 0) <= "00"; -- Only used in PHY
sw0 : grspwm generic map(tech => memtech,
hindex => CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+i,
pindex => 10+i,
paddr => 10+i, pirq => 10+i,
sysfreq => CPU_FREQ, nsync => 1, rmap => CFG_SPW_RMAP,
rmapcrc => CFG_SPW_RMAPCRC, fifosize1 => CFG_SPW_AHBFIFO,
fifosize2 => CFG_SPW_RXFIFO, rxclkbuftype => 1,
rmapbufs => CFG_SPW_RMAPBUF,ft => CFG_SPW_FT, ports => 1,
dmachan => CFG_SPW_DMACHAN,
netlist => CFG_SPW_NETLIST, spwcore => CFG_SPW_GRSPW,
input_type => CFG_SPW_INPUT, output_type => CFG_SPW_OUTPUT,
rxtx_sameclk => CFG_SPW_RTSAME)
port map(rstn, clkm, spw_rxclk(i), spw_rxclk(i), spw_rxtxclk, spw_rxtxclk,
ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+i),
apbi, apbo(10+i), spwi(i), spwo(i));
spwi(i).tickin <= '0'; spwi(i).rmapen <= '0';
spwi(i).clkdiv10 <= conv_std_logic_vector(CPU_FREQ/10000-1, 8);
spwi(i).dcrstval <= (others => '0');
spwi(i).timerrstval <= (others => '0');
spw_rxd_pad : inpad_ds generic map (padtech, lvds, x25v)
port map (spw_rxdp(i), spw_rxdn(i), dtmp(i));
spw_rxs_pad : inpad_ds generic map (padtech, lvds, x25v)
port map (spw_rxsp(i), spw_rxsn(i), stmp(i));
spw_txd_pad : outpad_ds generic map (padtech, lvds, x25v)
port map (spw_txdp(i), spw_txdn(i), spwo(i).d(0), gnd(0));
spw_txs_pad : outpad_ds generic map (padtech, lvds, x25v)
port map (spw_txsp(i), spw_txsn(i), spwo(i).s(0), gnd(0));
end generate;
end generate;
nospw : if CFG_SPW_EN = 0 generate
spw_rxd_pad : inpad_ds generic map (padtech, lvds, x25v)
port map (spw_rxdp(0), spw_rxdn(0), spwi(0).d(0));
spw_rxs_pad : inpad_ds generic map (padtech, lvds, x25v)
port map (spw_rxsp(0), spw_rxsn(0), spwi(0).s(0));
spw_txd_pad : outpad_ds generic map (padtech, lvds, x25v)
port map (spw_txdp(0), spw_txdn(0), spwi(0).d(0), gnd(0));
spw_txs_pad : outpad_ds generic map (padtech, lvds, x25v)
port map (spw_txsp(0), spw_txsn(0), spwi(0).s(0), gnd(0));
end generate;
-------------------------------------------------------------------------------
-- USB ------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Note that more than one USB component can not be instantiated at the same
-- time (board has only one USB transceiver), therefore they share AHB
-- master/slave indexes
-----------------------------------------------------------------------------
-- Shared pads
-----------------------------------------------------------------------------
usbpads: if (CFG_GRUSBHC + CFG_GRUSBDC + CFG_GRUSB_DCL) /= 0 generate
-- Incoming 60 MHz clock from transceiver, arch 3 = through BUFGDLL or
-- similiar.
usb_clkout_pad : clkpad
generic map (tech => padtech, arch => 3)
port map (usb_clkout, uclk, cgo.clklock, ulock);
usb_d_pad: iopadv
generic map(tech => padtech, width => 8)
port map (usb_d, usbo(0).dataout(7 downto 0), usbo(0).oen,
usbi(0).datain(7 downto 0));
usb_nxt_pad : inpad generic map (tech => padtech)
port map (usb_nxt, usbi(0).nxt);
usb_dir_pad : inpad generic map (tech => padtech)
port map (usb_dir, usbi(0).dir);
usb_resetn_pad : outpad generic map (tech => padtech)
port map (usb_resetn, usbo(0).reset);
usb_stp_pad : outpad generic map (tech => padtech)
port map (usb_stp, usbo(0).stp);
end generate usbpads;
nousb: if (CFG_GRUSBHC + CFG_GRUSBDC + CFG_GRUSB_DCL) = 0 generate
ulock <= '1';
end generate nousb;
-----------------------------------------------------------------------------
-- USB 2.0 Host Controller
-----------------------------------------------------------------------------
usbhc0: if CFG_GRUSBHC = 1 generate
usbhc0 : grusbhc
generic map (
ehchindex => CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM,
ehcpindex => 13, ehcpaddr => 13, ehcpirq => 13, ehcpmask => 16#fff#,
uhchindex => CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM+1,
uhchsindex => 8, uhchaddr => 16#A00#, uhchmask => 16#fff#, uhchirq => 9, tech => fabtech,
memtech => memtech, ehcgen => CFG_GRUSBHC_EHC, uhcgen => CFG_GRUSBHC_UHC,
endian_conv => CFG_GRUSBHC_ENDIAN, be_regs => CFG_GRUSBHC_BEREGS,
be_desc => CFG_GRUSBHC_BEDESC, uhcblo => CFG_GRUSBHC_BLO,
bwrd => CFG_GRUSBHC_BWRD, vbusconf => CFG_GRUSBHC_VBUSCONF)
port map (
clkm,uclk,rstn,apbi,apbo(13),ahbmi,ahbsi,
ahbmo(CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM),
ahbmo(CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM+1
downto
CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM+1),
ahbso(8 downto 8),
usbo,usbi);
end generate usbhc0;
-----------------------------------------------------------------------------
-- USB 2.0 Device Controller
-----------------------------------------------------------------------------
usbdc0: if CFG_GRUSBDC = 1 generate
usbdc0: grusbdc
generic map(
hsindex => 8, hirq => 6, haddr => 16#004#, hmask => 16#FFC#,
hmindex => CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM,
aiface => CFG_GRUSBDC_AIFACE, uiface => 1,
nepi => CFG_GRUSBDC_NEPI, nepo => CFG_GRUSBDC_NEPO,
i0 => CFG_GRUSBDC_I0, i1 => CFG_GRUSBDC_I1,
i2 => CFG_GRUSBDC_I2, i3 => CFG_GRUSBDC_I3,
i4 => CFG_GRUSBDC_I4, i5 => CFG_GRUSBDC_I5,
i6 => CFG_GRUSBDC_I6, i7 => CFG_GRUSBDC_I7,
i8 => CFG_GRUSBDC_I8, i9 => CFG_GRUSBDC_I9,
i10 => CFG_GRUSBDC_I10, i11 => CFG_GRUSBDC_I11,
i12 => CFG_GRUSBDC_I12, i13 => CFG_GRUSBDC_I13,
i14 => CFG_GRUSBDC_I14, i15 => CFG_GRUSBDC_I15,
o0 => CFG_GRUSBDC_O0, o1 => CFG_GRUSBDC_O1,
o2 => CFG_GRUSBDC_O2, o3 => CFG_GRUSBDC_O3,
o4 => CFG_GRUSBDC_O4, o5 => CFG_GRUSBDC_O5,
o6 => CFG_GRUSBDC_O6, o7 => CFG_GRUSBDC_O7,
o8 => CFG_GRUSBDC_O8, o9 => CFG_GRUSBDC_O9,
o10 => CFG_GRUSBDC_O10, o11 => CFG_GRUSBDC_O11,
o12 => CFG_GRUSBDC_O12, o13 => CFG_GRUSBDC_O13,
o14 => CFG_GRUSBDC_O14, o15 => CFG_GRUSBDC_O15,
memtech => memtech, keepclk => 1)
port map(
uclk => uclk,
usbi => usbi(0),
usbo => usbo(0),
hclk => clkm,
hrst => rstn,
ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM),
ahbsi => ahbsi,
ahbso => ahbso(8)
);
end generate usbdc0;
-----------------------------------------------------------------------------
-- USB DCL
-----------------------------------------------------------------------------
usb_dcl0: if CFG_GRUSB_DCL = 1 generate
usb_dcl0: grusb_dcl
generic map (
hindex => CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM,
memtech => memtech, keepclk => 1, uiface => 1)
port map (
uclk, usbi(0), usbo(0), clkm, rstn, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM));
end generate usb_dcl0;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nam2 : if CFG_PCI > 1 generate
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+log2x(CFG_PCI)-1) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- apbo(6) <= apb_none;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 GR-PCI-XC5LX50 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-2.0 | d05627cd15139bfc83efcdb18958389b | 0.55779 | 3.407398 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/uart/uart.vhd | 1 | 2,677 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- package: uart
-- File: uart.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: UART types and components
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
package uart is
type uart_in_type is record
rxd : std_ulogic;
ctsn : std_ulogic;
extclk : std_ulogic;
end record;
type uart_out_type is record
rtsn : std_ulogic;
txd : std_ulogic;
scaler : std_logic_vector(31 downto 0);
txen : std_ulogic;
flow : std_ulogic;
rxen : std_ulogic;
end record;
component apbuart
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
console : integer := 0;
pirq : integer := 0;
parity : integer := 1;
flow : integer := 1;
fifosize : integer range 1 to 32 := 1;
abits : integer := 8;
sbits : integer range 12 to 32 := 12);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
uarti : in uart_in_type;
uarto : out uart_out_type);
end component;
component ahbuart
generic (
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
uarti : in uart_in_type;
uarto : out uart_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type);
end component;
end;
| gpl-2.0 | 5bb1c9bbf435f85770efb760f5485f41 | 0.575271 | 3.687328 | false | false | false | false |
eamadio/fpgaMSP430 | fmsp430/per/fmsp_per_package.vhd | 1 | 19,220 | ------------------------------------------------------------------------------
--! Copyright (C) 2017 , Emmanuel Amadio
--
--! Redistribution and use in source and binary forms, with or without
--! modification, are permitted provided that the following conditions
--! are met:
--! * Redistributions of source code must retain the above copyright
--! notice, this list of conditions and the following disclaimer.
--! * Redistributions in binary form must reproduce the above copyright
--! notice, this list of conditions and the following disclaimer in the
--! documentation and/or other materials provided with the distribution.
--! * Neither the name of the authors nor the names of its contributors
--! may be used to endorse or promote products derived from this software
--! without specific prior written permission.
--
--! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
--! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
--! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
--! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
--! OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
--! THE POSSIBILITY OF SUCH DAMAGE
--
------------------------------------------------------------------------------
--
--! @file fmsp_per_package.vhd
--!
--! @brief fpgaMSP430 Peripherals package
--
--! @author Emmanuel Amadio, [email protected]
--
------------------------------------------------------------------------------
--! @version 1
--! @date: 2017-04-21
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all; --! standard unresolved logic UX01ZWLH-
use ieee.numeric_std.all; --! for the signed, unsigned types and arithmetic ops
use ieee.math_real.all;
use work.fmsp_functions.all;
package fmsp_per_package is
component fmsp_clock_module is
generic (
INST_NR : integer := 0; --! Current fmsp instance number (for multicore systems)
TOTAL_NR : integer := 0; --! Total number of fmsp instances-1 (for multicore systems)
PMEM_SIZE : integer := 32768; --! Program Memory Size
DMEM_SIZE : integer := 16384; --! Data Memory Size
PER_SIZE : integer := 16384; --! Peripheral Memory Size
DEBUG_EN : boolean := false; --! Include/Exclude Serial Debug interface
WATCHDOG : boolean := false; --! Include/Exclude Watchdog timer
DMA_IF_EN : boolean := false; --! Include/Exclude DMA interface support
NMI_EN : boolean := false --! Include/Exclude Non-Maskable-Interrupt support
);
port (
mclk : in std_logic; --! Main system clock
--! INPUTs
cpu_en : in std_logic; --! Enable CPU code execution (asynchronous)
cpuoff : in std_logic; --! Turns off the CPU
dbg_cpu_reset : in std_logic; --! Reset CPU from debug interface
dbg_en : in std_logic; --! Debug interface enable (asynchronous)
lfxt_clk : in std_logic; --! Low frequency oscillator (typ 32kHz)
oscoff : in std_logic; --! Turns off LFXT1 clock input
per_addr : in std_logic_vector(13 downto 0); --! Peripheral address
per_din : in std_logic_vector(15 downto 0); --! Peripheral data input
per_en : in std_logic; --! Peripheral enable (high active)
per_we : in std_logic_vector(1 downto 0); --! Peripheral write enable (high active)
reset_n : in std_logic; --! Reset Pin (low active, asynchronous)
scg1 : in std_logic; --! System clock generator 1. Turns off the SMCLK
wdt_reset : in std_logic; --! Watchdog-timer reset
--! OUTPUTs
dbg_rst : out std_logic; --! Debug unit reset
per_dout : out std_logic_vector(15 downto 0); --! Peripheral data output
por : out std_logic; --! Power-on reset
puc_pnd_set : out std_logic; --! PUC pending set for the serial debug interface
puc_rst : out std_logic; --! Main system reset
aclk_en : out std_logic; --! ACLK enable
smclk_en : out std_logic --! SMCLK enable
);
end component fmsp_clock_module;
component fmsp_sfr is
generic (
INST_NR : integer := 0; --! Current fmsp instance number (for multicore systems)
TOTAL_NR : integer := 0; --! Total number of fmsp instances-1 (for multicore systems)
PMEM_SIZE : integer := 32768; --! Program Memory Size
DMEM_SIZE : integer := 16384; --! Data Memory Size
PER_SIZE : integer := 16384; --! Peripheral Memory Size
MULTIPLIER : boolean := false; --! Include/Exclude Hardware Multiplier
USER_VERSION : integer := 0; --! Custom user version number
WATCHDOG : boolean := false; --! Include/Exclude Watchdog timer
NMI_EN : boolean := false --! Include/Exclude Non-Maskable-Interrupt support
);
port (
mclk : in std_logic; --! Main system clock
mrst : in std_logic; --! Main system reset
--! INPUTs
nmi : in std_logic; --! Non-maskable interrupt (asynchronous)
nmi_acc : in std_logic; --! Non-Maskable interrupt request accepted
per_addr : in std_logic_vector(13 downto 0); --! Peripheral address
per_din : in std_logic_vector(15 downto 0); --! Peripheral data input
per_en : in std_logic; --! Peripheral enable (high active)
per_we : in std_logic_vector(1 downto 0); --! Peripheral write enable (high active)
wdtifg : in std_logic; --! Watchdog-timer interrupt flag
wdtnmies : in std_logic; --! Watchdog-timer NMI edge selection
--! OUTPUTs
cpu_id : out std_logic_vector(31 downto 0); --! CPU ID
nmi_pnd : out std_logic; --! NMI Pending
nmi_wkup : out std_logic; --! NMI Wakeup
per_dout : out std_logic_vector(15 downto 0); --! Peripheral data output
wdtie : out std_logic; --! Watchdog-timer interrupt enable
wdtifg_sw_clr : out std_logic; --! Watchdog-timer interrupt flag software clear
wdtifg_sw_set : out std_logic --! Watchdog-timer interrupt flag software set
);
end component fmsp_sfr;
component fmsp_watchdog is
port (
mclk : in std_logic; --! Main system clock
mrst : in std_logic; --! Main system reset
por : in std_logic; --! Power-on reset
--! INPUTs
dbg_freeze : in std_logic; --! Freeze Watchdog counter
aclk_en : in std_logic; --! ACLK enable
smclk_en : in std_logic; --! SMCLK enable
per_addr : in std_logic_vector(13 downto 0); --! Peripheral address
per_din : in std_logic_vector(15 downto 0); --! Peripheral data input
per_en : in std_logic; --! Peripheral enable (high active)
per_we : in std_logic_vector(1 downto 0); --! Peripheral write enable (high active)
wdtie : in std_logic; --! Watchdog timer interrupt enable
wdtifg_irq_clr : in std_logic; --! Watchdog-timer interrupt flag irq accepted clear
wdtifg_sw_clr : in std_logic; --! Watchdog-timer interrupt flag software clear
wdtifg_sw_set : in std_logic; --! Watchdog-timer interrupt flag software set
--! OUTPUTs
per_dout : out std_logic_vector(15 downto 0); --! Peripheral data output
wdt_irq : out std_logic; --! Watchdog-timer interrupt
wdt_reset : out std_logic; --! Watchdog-timer reset
wdt_wkup : out std_logic; --! Watchdog Wakeup
wdtifg : out std_logic; --! Watchdog-timer interrupt flag
wdtnmies : out std_logic --! Watchdog-timer NMI edge selection
);
end component fmsp_watchdog;
component fmsp_multiplier is
port (
mclk : in std_logic; --! Main system clock
mrst : in std_logic; --! Main system reset
--! INPUTs
per_addr : in std_logic_vector(13 downto 0); --! Peripheral address
per_din : in std_logic_vector(15 downto 0); --! Peripheral data input
per_en : in std_logic; --! Peripheral enable (high active)
per_we : in std_logic_vector(1 downto 0); --! Peripheral write enable (high active)
--! OUTPUTs
per_dout : out std_logic_vector(15 downto 0) --! Peripheral data output
);
end component fmsp_multiplier;
component fmsp_timerA is
-- generic (
-- INST_NR : integer := 0; --! Current fmsp instance number (for multicore systems)
-- TOTAL_NR : integer := 0; --! Total number of fmsp instances-1 (for multicore systems)
-- PMEM_SIZE : integer := 32768; --! Program Memory Size
-- DMEM_SIZE : integer := 16384; --! Data Memory Size
-- PER_SIZE : integer := 16384; --! Peripheral Memory Size
-- MULTIPLIER : boolean := false; --! Include/Exclude Hardware Multiplier
-- USER_VERSION : integer := 0; --! Custom user version number
-- WATCHDOG : boolean := false; --! Include/Exclude Watchdog timer
-- NMI_EN : boolean := false; --! Include/Exclude Non-Maskable-Interrupt support
-- SYNC_NMI_EN : boolean := true --!
-- );
port (
mclk : in std_logic; --! Main system clock
mrst : in std_logic; --! Main system reset
--! INPUTs
aclk_en : in std_logic; --! ACLK enable (from CPU)
smclk_en : in std_logic; --! SMCLK enable (from CPU)
dbg_freeze : in std_logic; --! Freeze Timer A counter
inclk : in std_logic; --! INCLK external timer clock (SLOW)
irq_ta0_acc : in std_logic; --! Interrupt request TACCR0 accepted
per_addr : in std_logic_vector(13 downto 0); --! Peripheral address
per_din : in std_logic_vector(15 downto 0); --! Peripheral data input
per_en : in std_logic; --! Peripheral enable (high active)
per_we : in std_logic_vector(1 downto 0); --! Peripheral write enable (high active)
ta_cci0a : in std_logic; --! Timer A capture 0 input A
ta_cci0b : in std_logic; --! Timer A capture 0 input B
ta_cci1a : in std_logic; --! Timer A capture 1 input A
ta_cci1b : in std_logic; --! Timer A capture 1 input B
ta_cci2a : in std_logic; --! Timer A capture 2 input A
ta_cci2b : in std_logic; --! Timer A capture 2 input B
taclk : in std_logic; --! TACLK external timer clock (SLOW)
--! OUTPUTs
irq_ta0 : out std_logic; --! Timer A interrupt: TACCR0
irq_ta1 : out std_logic; --! Timer A interrupt: TAIV, TACCR1, TACCR2
per_dout : out std_logic_vector(15 downto 0); --! Peripheral data output
ta_out0 : out std_logic; --! Timer A output 0
ta_out0_en : out std_logic; --! Timer A output 0 enable
ta_out1 : out std_logic; --! Timer A output 1
ta_out1_en : out std_logic; --! Timer A output 1 enable
ta_out2 : out std_logic; --! Timer A output 2
ta_out2_en : out std_logic --! Timer A output 2 enable
);
end component fmsp_timerA;
--
--! STATES, REGISTER FIELDS, ...
--======================================
--! Instructions type
constant C_INST_SO : integer := 0;
constant C_INST_JMP : integer := 1;
constant C_INST_TO : integer := 2;
--! Single-operand arithmetic
constant C_RRC : integer := 0;
constant C_SWPB : integer := 1;
constant C_RRA : integer := 2;
constant C_SXT : integer := 3;
constant C_PUSH : integer := 4;
constant C_CALL : integer := 5;
constant C_RETI : integer := 6;
constant C_IRQ : integer := 7;
--! Conditional jump
constant C_JNE : integer := 0;
constant C_JEQ : integer := 1;
constant C_JNC : integer := 2;
constant C_JC : integer := 3;
constant C_JN : integer := 4;
constant C_JGE : integer := 5;
constant C_JL : integer := 6;
constant C_JMP : integer := 7;
--! Two-operand arithmetic
constant C_MOV : integer := 0;
constant C_ADD : integer := 1;
constant C_ADDC : integer := 2;
constant C_SUBC : integer := 3;
constant C_SUB : integer := 4;
constant C_CMP : integer := 5;
constant C_DADD : integer := 6;
constant C_BIT : integer := 7;
constant C_BIC : integer := 8;
constant C_BIS : integer := 9;
constant C_XOR : integer := 10;
constant C_AND : integer := 11;
--! Addressing modes
constant C_DIR : integer := 0;
constant C_IDX : integer := 1;
constant C_INDIR : integer := 2;
constant C_INDIR_I : integer := 3;
constant C_SYMB : integer := 4;
constant C_IMM : integer := 5;
constant C_ABS : integer := 6;
constant C_CONST : integer := 7;
----! Instruction state machine
-- constant C_I_IRQ_FETCH : integer := 0;
-- constant C_I_IRQ_DONE : integer := 1;
-- constant C_I_DEC : integer := 2;
-- constant C_I_EXT1 : integer := 3;
-- constant C_I_EXT2 : integer := 4;
-- constant C_I_IDLE : integer := 5;
----! Instruction state machine
-- constant I_IRQ_FETCH : std_logic_vector(2 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(C_I_IRQ_FETCH,3));
-- constant I_IRQ_DONE : std_logic_vector(2 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(C_I_IRQ_DONE,3));
-- constant I_DEC : std_logic_vector(2 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(C_I_DEC,3));
-- constant I_EXT1 : std_logic_vector(2 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(C_I_EXT1,3));
-- constant I_EXT2 : std_logic_vector(2 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(C_I_EXT2,3));
-- constant I_IDLE : std_logic_vector(2 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(C_I_IDLE,3));
----! Execution state machine
-- constant C_E_IRQ_0 : integer := 0;
-- constant C_E_IRQ_1 : integer := 1;
-- constant C_E_IRQ_2 : integer := 2;
-- constant C_E_IRQ_3 : integer := 3;
-- constant C_E_IRQ_4 : integer := 4;
-- constant C_E_SRC_AD : integer := 5;
-- constant C_E_SRC_RD : integer := 6;
-- constant C_E_SRC_WR : integer := 7;
-- constant C_E_DST_AD : integer := 8;
-- constant C_E_DST_RD : integer := 9;
-- constant C_E_DST_WR : integer := 10;
-- constant C_E_EXEC : integer := 11;
-- constant C_E_JUMP : integer := 12;
-- constant C_E_IDLE : integer := 13;
--
----! Execution state machine
-- constant E_IRQ_0 : std_logic_vector(3 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(C_E_IRQ_0,4));
-- constant E_IRQ_1 : std_logic_vector(3 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(C_E_IRQ_1,4));
-- constant E_IRQ_2 : std_logic_vector(3 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(C_E_IRQ_2,4));
-- constant E_IRQ_3 : std_logic_vector(3 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(C_E_IRQ_3,4));
-- constant E_IRQ_4 : std_logic_vector(3 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(C_E_IRQ_4,4));
-- constant E_SRC_AD : std_logic_vector(3 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(C_E_SRC_AD,4));
-- constant E_SRC_RD : std_logic_vector(3 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(C_E_SRC_RD,4));
-- constant E_SRC_WR : std_logic_vector(3 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(C_E_SRC_WR,4));
-- constant E_DST_AD : std_logic_vector(3 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(C_E_DST_AD,4));
-- constant E_DST_RD : std_logic_vector(3 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(C_E_DST_RD,4));
-- constant E_DST_WR : std_logic_vector(3 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(C_E_DST_WR,4));
-- constant E_EXEC : std_logic_vector(3 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(C_E_EXEC,4));
-- constant E_JUMP : std_logic_vector(3 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(C_E_JUMP,4));
-- constant E_IDLE : std_logic_vector(3 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(C_E_IDLE,4));
--! ALU control signals
constant C_ALU_SRC_INV : integer := 0;
constant C_ALU_INC : integer := 1;
constant C_ALU_INC_C : integer := 2;
constant C_ALU_ADD : integer := 3;
constant C_ALU_AND : integer := 4;
constant C_ALU_OR : integer := 5;
constant C_ALU_XOR : integer := 6;
constant C_ALU_DADD : integer := 7;
constant C_ALU_STAT_7 : integer := 8;
constant C_ALU_STAT_F : integer := 9;
constant C_ALU_SHIFT : integer := 10;
constant C_EXEC_NO_WR : integer := 11;
--! Debug interface
constant C_DBG_UART_WR : integer := 18;
constant C_DBG_UART_BW : integer := 17;
-- constant C_DBG_UART_ADDR : integer := 16:11
--! Debug interface CPU_CTL register
constant C_HALT : integer := 0;
constant C_RUN : integer := 1;
constant C_ISTEP : integer := 2;
constant C_SW_BRK_EN : integer := 3;
constant C_FRZ_BRK_EN : integer := 4;
constant C_RST_BRK_EN : integer := 5;
constant C_CPU_RST : integer := 6;
--! Debug interface CPU_STAT register
constant C_HALT_RUN : integer := 0;
constant C_PUC_PND : integer := 1;
constant C_SWBRK_PND : integer := 3;
constant C_HWBRK0_PND : integer := 4;
constant C_HWBRK1_PND : integer := 5;
--! Debug interface BRKx_CTL register
constant C_BRK_MODE_RD : integer := 0;
constant C_BRK_MODE_WR : integer := 1;
-- constant C_BRK_MODE : integer := 1:0
constant C_BRK_EN : integer := 2;
constant C_BRK_I_EN : integer := 3;
constant C_BRK_RANGE : integer := 4;
--! Basic clock module: BCSCTL1 Control Register
-- constant C_DIVAx 5:4
constant C_DMA_CPUOFF : integer := 0;
constant C_DMA_OSCOFF : integer := 1;
constant C_DMA_SCG0 : integer := 2;
constant C_DMA_SCG1 : integer := 3;
--! Basic clock module: BCSCTL2 Control Register
constant C_SELMx : integer := 7;
constant C_SELS : integer := 3;
-- constant C_DIVSx 2:1
--
--! DEBUG INTERFACE EXTRA CONFIGURATION
--======================================
--! Debug interface: CPU version
--! 1 - FPGA support only (Pre-BSD licence era)
--! 2 - Add ASIC support
--! 3 - Add DMA interface support
constant C_CPU_VERSION : integer range 0 to 7 := 1;
--! Debug interface: Software breakpoint opcode
constant C_DBG_SWBRK_OP : std_logic_vector(15 downto 0) := x"4343";
--! Debug UART interface auto data synchronization
--! If the following define is commented out, then
--! the DBG_UART_BAUD and DBG_DCO_FREQ need to be properly
--! defined.
-- constant C_DBG_UART_AUTO_SYNC
--! Debug UART interface data rate
--! In order to properly setup the UART debug interface, you
--! need to specify the DCO_CLK frequency (DBG_DCO_FREQ) and
--! the chosen BAUD rate from the UART interface.
--
-- constant C_DBG_UART_BAUD 9600
-- constant C_DBG_UART_BAUD 19200
-- constant C_DBG_UART_BAUD 38400
-- constant C_DBG_UART_BAUD 57600
-- constant C_DBG_UART_BAUD 115200
-- constant C_DBG_UART_BAUD 230400
-- constant C_DBG_UART_BAUD 460800
-- constant C_DBG_UART_BAUD 576000
-- constant C_DBG_UART_BAUD 921600
-- constant C_DBG_UART_BAUD 2000000
-- constant C_DBG_DCO_FREQ 20000000
-- constant C_DBG_UART_CNT ((`DBG_DCO_FREQ/`DBG_UART_BAUD)-1)
--! Debug interface selection
--! constant C_DBG_UART -> Enable UART (8N1) debug interface
--! constant C_DBG_JTAG -> DON'T UNCOMMENT, NOT SUPPORTED
--
-- constant C_DBG_UART
-- constant C_DBG_JTAG
end fmsp_per_package; --! fmsp_per_package
| bsd-3-clause | d704fc323ec7297ae65abe26ff72c2ce | 0.625598 | 2.957833 | false | false | false | false |
kloboves/sicxe | vhdl/interrupt_control.vhd | 1 | 804 | library ieee;
use ieee.std_logic_1164.all;
entity interrupt_control is
Port (
clock_i : in std_logic;
reset_i : in std_logic;
enable_i : in std_logic;
event_i : in std_logic;
acknowledge_i : in std_logic;
interrupt_o : out std_logic
);
end interrupt_control;
architecture behavioral of interrupt_control is
signal interrupt : std_logic;
begin
interrupt_o <= interrupt;
interrupt_proc : process(clock_i)
begin
if (rising_edge(clock_i)) then
if (reset_i = '1') then
interrupt <= '0';
else
interrupt <= interrupt;
if (enable_i = '0' or acknowledge_i = '1') then
interrupt <= '0';
elsif (event_i = '1') then
interrupt <= '1';
end if;
end if;
end if;
end process;
end behavioral;
| mit | 083682f088514e1f9344a93c8b729e7f | 0.594527 | 3.480519 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.cache/ip/2017.2/3ff2b656dab8de5f/zqynq_lab_1_design_axi_timer_0_0_sim_netlist.vhdl | 1 | 419,058 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Wed Sep 20 21:08:01 2017
-- Host : EffulgentTome running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_axi_timer_0_0_sim_netlist.vhdl
-- Design : zqynq_lab_1_design_axi_timer_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync is
port (
captureTrig0_d0 : out STD_LOGIC;
read_Mux_In : in STD_LOGIC_VECTOR ( 0 to 0 );
capturetrig0 : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync is
signal CaptureTrig0_int : STD_LOGIC;
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
begin
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => capturetrig0,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d3,
Q => CaptureTrig0_int,
R => '0'
);
captureTrig0_d_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => read_Mux_In(0),
I1 => CaptureTrig0_int,
O => captureTrig0_d0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_1 is
port (
captureTrig1_d0 : out STD_LOGIC;
read_Mux_In : in STD_LOGIC_VECTOR ( 0 to 0 );
capturetrig1 : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_1 : entity is "cdc_sync";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_1;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_1 is
signal CaptureTrig1_int : STD_LOGIC;
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
begin
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => capturetrig1,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d3,
Q => CaptureTrig1_int,
R => '0'
);
captureTrig1_d_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => read_Mux_In(0),
I1 => CaptureTrig1_int,
O => captureTrig1_d0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_2 is
port (
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\INFERRED_GEN.icount_out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
S : out STD_LOGIC_VECTOR ( 0 to 0 );
\INFERRED_GEN.icount_out_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\TCSR0_GENERATE[20].TCSR0_FF_I\ : in STD_LOGIC;
\TCSR0_GENERATE[24].TCSR0_FF_I\ : in STD_LOGIC;
counter_TC : in STD_LOGIC_VECTOR ( 0 to 1 );
read_Mux_In : in STD_LOGIC_VECTOR ( 7 downto 0 );
generateOutPre0 : in STD_LOGIC;
\TCSR1_GENERATE[24].TCSR1_FF_I\ : in STD_LOGIC;
Load_Counter_Reg030_out : in STD_LOGIC;
Load_Counter_Reg031_out : in STD_LOGIC;
\Load_Counter_Reg0__0\ : in STD_LOGIC;
Load_Counter_Reg028_out : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
freeze : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_2 : entity is "cdc_sync";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_2;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_2 is
signal \Counter_En041_out__2\ : STD_LOGIC;
signal \Counter_En043_out__0\ : STD_LOGIC;
signal \Counter_En045_out__1\ : STD_LOGIC;
signal \Counter_En0__4\ : STD_LOGIC;
signal Freeze_int : STD_LOGIC;
signal counter_En : STD_LOGIC_VECTOR ( 0 to 1 );
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
begin
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => freeze,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d3,
Q => Freeze_int,
R => '0'
);
\INFERRED_GEN.icount_out[31]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FCFFFCAA"
)
port map (
I0 => Load_Counter_Reg030_out,
I1 => Load_Counter_Reg031_out,
I2 => \Counter_En043_out__0\,
I3 => \TCSR0_GENERATE[20].TCSR0_FF_I\,
I4 => \Counter_En041_out__2\,
O => E(0)
);
\INFERRED_GEN.icount_out[31]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FCFFFCAA"
)
port map (
I0 => \Load_Counter_Reg0__0\,
I1 => Load_Counter_Reg028_out,
I2 => \Counter_En045_out__1\,
I3 => \TCSR0_GENERATE[20].TCSR0_FF_I\,
I4 => \Counter_En0__4\,
O => \INFERRED_GEN.icount_out_reg[0]\(0)
);
\INFERRED_GEN.icount_out[31]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"00FB0000"
)
port map (
I0 => read_Mux_In(4),
I1 => counter_TC(1),
I2 => read_Mux_In(6),
I3 => Freeze_int,
I4 => \TCSR0_GENERATE[24].TCSR0_FF_I\,
O => \Counter_En043_out__0\
);
\INFERRED_GEN.icount_out[31]_i_5__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4040404040004040"
)
port map (
I0 => Freeze_int,
I1 => \TCSR0_GENERATE[24].TCSR0_FF_I\,
I2 => generateOutPre0,
I3 => read_Mux_In(6),
I4 => counter_TC(1),
I5 => read_Mux_In(4),
O => \Counter_En045_out__1\
);
\INFERRED_GEN.icount_out[31]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"4444444444444404"
)
port map (
I0 => Freeze_int,
I1 => \TCSR0_GENERATE[24].TCSR0_FF_I\,
I2 => counter_TC(0),
I3 => read_Mux_In(7),
I4 => read_Mux_In(6),
I5 => read_Mux_In(4),
O => \Counter_En041_out__2\
);
\INFERRED_GEN.icount_out[31]_i_6__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2222222222202222"
)
port map (
I0 => \TCSR1_GENERATE[24].TCSR1_FF_I\,
I1 => Freeze_int,
I2 => read_Mux_In(3),
I3 => read_Mux_In(2),
I4 => counter_TC(1),
I5 => read_Mux_In(0),
O => \Counter_En0__4\
);
icount_out0_carry_i_5: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \INFERRED_GEN.icount_out_reg[1]\(1),
I1 => counter_En(0),
I2 => read_Mux_In(5),
O => S(0)
);
\icount_out0_carry_i_5__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"6A666AAA"
)
port map (
I0 => \INFERRED_GEN.icount_out_reg[1]\(0),
I1 => counter_En(1),
I2 => read_Mux_In(5),
I3 => \TCSR0_GENERATE[20].TCSR0_FF_I\,
I4 => read_Mux_In(1),
O => \INFERRED_GEN.icount_out_reg[4]\(0)
);
icount_out0_carry_i_6: unisim.vcomponents.MUXF7
port map (
I0 => \Counter_En041_out__2\,
I1 => \Counter_En043_out__0\,
O => counter_En(0),
S => \TCSR0_GENERATE[20].TCSR0_FF_I\
);
\icount_out0_carry_i_6__0\: unisim.vcomponents.MUXF7
port map (
I0 => \Counter_En0__4\,
I1 => \Counter_En045_out__1\,
O => counter_En(1),
S => \TCSR0_GENERATE[20].TCSR0_FF_I\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_counter_f is
port (
Q : out STD_LOGIC_VECTOR ( 31 downto 0 );
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
\s_axi_rdata_i_reg[0]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[1]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[2]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[3]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[4]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[5]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[6]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[7]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[8]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[9]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[10]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[11]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[12]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[13]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[14]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[15]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[16]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[17]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[18]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[19]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[20]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[21]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[22]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[23]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[24]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[25]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[26]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[27]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[28]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[29]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[30]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[31]\ : out STD_LOGIC;
generateOutPre1_reg : out STD_LOGIC;
counter_TC : out STD_LOGIC_VECTOR ( 0 to 0 );
S : in STD_LOGIC_VECTOR ( 0 to 0 );
read_Mux_In : in STD_LOGIC_VECTOR ( 31 downto 0 );
load_Counter_Reg : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aresetn : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[31]_0\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
\counter_TC_Reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_counter_f;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_counter_f is
signal \INFERRED_GEN.icount_out[0]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[10]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[11]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[12]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[13]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[14]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[15]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[16]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[17]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[18]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[19]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[1]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[20]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[21]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[22]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[23]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[24]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[25]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[26]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[27]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[28]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[29]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[2]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[30]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[31]_i_2_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[32]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[3]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[4]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[5]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[6]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[7]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[8]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[9]_i_1_n_0\ : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^counter_tc\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \icount_out0_carry__0_i_1_n_0\ : STD_LOGIC;
signal \icount_out0_carry__0_i_2_n_0\ : STD_LOGIC;
signal \icount_out0_carry__0_i_3_n_0\ : STD_LOGIC;
signal \icount_out0_carry__0_i_4_n_0\ : STD_LOGIC;
signal \icount_out0_carry__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__0_n_1\ : STD_LOGIC;
signal \icount_out0_carry__0_n_2\ : STD_LOGIC;
signal \icount_out0_carry__0_n_3\ : STD_LOGIC;
signal \icount_out0_carry__0_n_4\ : STD_LOGIC;
signal \icount_out0_carry__0_n_5\ : STD_LOGIC;
signal \icount_out0_carry__0_n_6\ : STD_LOGIC;
signal \icount_out0_carry__0_n_7\ : STD_LOGIC;
signal \icount_out0_carry__1_i_1_n_0\ : STD_LOGIC;
signal \icount_out0_carry__1_i_2_n_0\ : STD_LOGIC;
signal \icount_out0_carry__1_i_3_n_0\ : STD_LOGIC;
signal \icount_out0_carry__1_i_4_n_0\ : STD_LOGIC;
signal \icount_out0_carry__1_n_0\ : STD_LOGIC;
signal \icount_out0_carry__1_n_1\ : STD_LOGIC;
signal \icount_out0_carry__1_n_2\ : STD_LOGIC;
signal \icount_out0_carry__1_n_3\ : STD_LOGIC;
signal \icount_out0_carry__1_n_4\ : STD_LOGIC;
signal \icount_out0_carry__1_n_5\ : STD_LOGIC;
signal \icount_out0_carry__1_n_6\ : STD_LOGIC;
signal \icount_out0_carry__1_n_7\ : STD_LOGIC;
signal \icount_out0_carry__2_i_1_n_0\ : STD_LOGIC;
signal \icount_out0_carry__2_i_2_n_0\ : STD_LOGIC;
signal \icount_out0_carry__2_i_3_n_0\ : STD_LOGIC;
signal \icount_out0_carry__2_i_4_n_0\ : STD_LOGIC;
signal \icount_out0_carry__2_n_0\ : STD_LOGIC;
signal \icount_out0_carry__2_n_1\ : STD_LOGIC;
signal \icount_out0_carry__2_n_2\ : STD_LOGIC;
signal \icount_out0_carry__2_n_3\ : STD_LOGIC;
signal \icount_out0_carry__2_n_4\ : STD_LOGIC;
signal \icount_out0_carry__2_n_5\ : STD_LOGIC;
signal \icount_out0_carry__2_n_6\ : STD_LOGIC;
signal \icount_out0_carry__2_n_7\ : STD_LOGIC;
signal \icount_out0_carry__3_i_1_n_0\ : STD_LOGIC;
signal \icount_out0_carry__3_i_2_n_0\ : STD_LOGIC;
signal \icount_out0_carry__3_i_3_n_0\ : STD_LOGIC;
signal \icount_out0_carry__3_i_4_n_0\ : STD_LOGIC;
signal \icount_out0_carry__3_n_0\ : STD_LOGIC;
signal \icount_out0_carry__3_n_1\ : STD_LOGIC;
signal \icount_out0_carry__3_n_2\ : STD_LOGIC;
signal \icount_out0_carry__3_n_3\ : STD_LOGIC;
signal \icount_out0_carry__3_n_4\ : STD_LOGIC;
signal \icount_out0_carry__3_n_5\ : STD_LOGIC;
signal \icount_out0_carry__3_n_6\ : STD_LOGIC;
signal \icount_out0_carry__3_n_7\ : STD_LOGIC;
signal \icount_out0_carry__4_i_1_n_0\ : STD_LOGIC;
signal \icount_out0_carry__4_i_2_n_0\ : STD_LOGIC;
signal \icount_out0_carry__4_i_3_n_0\ : STD_LOGIC;
signal \icount_out0_carry__4_i_4_n_0\ : STD_LOGIC;
signal \icount_out0_carry__4_n_0\ : STD_LOGIC;
signal \icount_out0_carry__4_n_1\ : STD_LOGIC;
signal \icount_out0_carry__4_n_2\ : STD_LOGIC;
signal \icount_out0_carry__4_n_3\ : STD_LOGIC;
signal \icount_out0_carry__4_n_4\ : STD_LOGIC;
signal \icount_out0_carry__4_n_5\ : STD_LOGIC;
signal \icount_out0_carry__4_n_6\ : STD_LOGIC;
signal \icount_out0_carry__4_n_7\ : STD_LOGIC;
signal \icount_out0_carry__5_i_1_n_0\ : STD_LOGIC;
signal \icount_out0_carry__5_i_2_n_0\ : STD_LOGIC;
signal \icount_out0_carry__5_i_3_n_0\ : STD_LOGIC;
signal \icount_out0_carry__5_i_4_n_0\ : STD_LOGIC;
signal \icount_out0_carry__5_n_0\ : STD_LOGIC;
signal \icount_out0_carry__5_n_1\ : STD_LOGIC;
signal \icount_out0_carry__5_n_2\ : STD_LOGIC;
signal \icount_out0_carry__5_n_3\ : STD_LOGIC;
signal \icount_out0_carry__5_n_4\ : STD_LOGIC;
signal \icount_out0_carry__5_n_5\ : STD_LOGIC;
signal \icount_out0_carry__5_n_6\ : STD_LOGIC;
signal \icount_out0_carry__5_n_7\ : STD_LOGIC;
signal \icount_out0_carry__6_i_1_n_0\ : STD_LOGIC;
signal \icount_out0_carry__6_i_2_n_0\ : STD_LOGIC;
signal \icount_out0_carry__6_i_3_n_0\ : STD_LOGIC;
signal \icount_out0_carry__6_i_4_n_0\ : STD_LOGIC;
signal \icount_out0_carry__6_n_1\ : STD_LOGIC;
signal \icount_out0_carry__6_n_2\ : STD_LOGIC;
signal \icount_out0_carry__6_n_3\ : STD_LOGIC;
signal \icount_out0_carry__6_n_4\ : STD_LOGIC;
signal \icount_out0_carry__6_n_5\ : STD_LOGIC;
signal \icount_out0_carry__6_n_6\ : STD_LOGIC;
signal \icount_out0_carry__6_n_7\ : STD_LOGIC;
signal icount_out0_carry_i_1_n_0 : STD_LOGIC;
signal icount_out0_carry_i_2_n_0 : STD_LOGIC;
signal icount_out0_carry_i_3_n_0 : STD_LOGIC;
signal icount_out0_carry_i_4_n_0 : STD_LOGIC;
signal icount_out0_carry_n_0 : STD_LOGIC;
signal icount_out0_carry_n_1 : STD_LOGIC;
signal icount_out0_carry_n_2 : STD_LOGIC;
signal icount_out0_carry_n_3 : STD_LOGIC;
signal icount_out0_carry_n_4 : STD_LOGIC;
signal icount_out0_carry_n_5 : STD_LOGIC;
signal icount_out0_carry_n_6 : STD_LOGIC;
signal icount_out0_carry_n_7 : STD_LOGIC;
signal \NLW_icount_out0_carry__6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[0]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[10]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[11]_i_1\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[12]_i_1\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[13]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[14]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[15]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[16]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[17]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[18]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[19]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[1]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[20]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[21]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[22]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[23]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[24]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[25]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[26]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[27]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[28]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[29]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[2]_i_1\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[30]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[31]_i_2\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[3]_i_1\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[4]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[5]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[6]_i_1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[7]_i_1\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[8]_i_1\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[9]_i_1\ : label is "soft_lutpair45";
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of icount_out0_carry : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__0\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__1\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__2\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__3\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__4\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__5\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__6\ : label is "{SYNTH-8 {cell *THIS*}}";
begin
Q(31 downto 0) <= \^q\(31 downto 0);
SR(0) <= \^sr\(0);
counter_TC(0) <= \^counter_tc\(0);
\GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(31),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(31),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(31),
O => \s_axi_rdata_i_reg[31]\
);
\GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(21),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(21),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(21),
O => \s_axi_rdata_i_reg[21]\
);
\GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(20),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(20),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(20),
O => \s_axi_rdata_i_reg[20]\
);
\GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(19),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(19),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(19),
O => \s_axi_rdata_i_reg[19]\
);
\GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(18),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(18),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(18),
O => \s_axi_rdata_i_reg[18]\
);
\GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(17),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(17),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(17),
O => \s_axi_rdata_i_reg[17]\
);
\GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(16),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(16),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(16),
O => \s_axi_rdata_i_reg[16]\
);
\GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(15),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(15),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(15),
O => \s_axi_rdata_i_reg[15]\
);
\GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(14),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(14),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(14),
O => \s_axi_rdata_i_reg[14]\
);
\GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(13),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(13),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(13),
O => \s_axi_rdata_i_reg[13]\
);
\GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(12),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(12),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(12),
O => \s_axi_rdata_i_reg[12]\
);
\GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(30),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(30),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(30),
O => \s_axi_rdata_i_reg[30]\
);
\GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(11),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(11),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(11),
O => \s_axi_rdata_i_reg[11]\
);
\GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(10),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(10),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(10),
O => \s_axi_rdata_i_reg[10]\
);
\GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(9),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(9),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(9),
O => \s_axi_rdata_i_reg[9]\
);
\GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(8),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(8),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(8),
O => \s_axi_rdata_i_reg[8]\
);
\GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(7),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(7),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(7),
O => \s_axi_rdata_i_reg[7]\
);
\GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(6),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(6),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(6),
O => \s_axi_rdata_i_reg[6]\
);
\GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(5),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(5),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(5),
O => \s_axi_rdata_i_reg[5]\
);
\GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(4),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(4),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(4),
O => \s_axi_rdata_i_reg[4]\
);
\GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(3),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(3),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(3),
O => \s_axi_rdata_i_reg[3]\
);
\GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(2),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(2),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(2),
O => \s_axi_rdata_i_reg[2]\
);
\GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(29),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(29),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(29),
O => \s_axi_rdata_i_reg[29]\
);
\GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(1),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(1),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(1),
O => \s_axi_rdata_i_reg[1]\
);
\GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(0),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(0),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(0),
O => \s_axi_rdata_i_reg[0]\
);
\GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(28),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(28),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(28),
O => \s_axi_rdata_i_reg[28]\
);
\GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(27),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(27),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(27),
O => \s_axi_rdata_i_reg[27]\
);
\GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(26),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(26),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(26),
O => \s_axi_rdata_i_reg[26]\
);
\GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(25),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(25),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(25),
O => \s_axi_rdata_i_reg[25]\
);
\GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(24),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(24),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(24),
O => \s_axi_rdata_i_reg[24]\
);
\GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(23),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(23),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(23),
O => \s_axi_rdata_i_reg[23]\
);
\GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(22),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(22),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(22),
O => \s_axi_rdata_i_reg[22]\
);
GenerateOut0_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_aresetn,
O => \^sr\(0)
);
\INFERRED_GEN.icount_out[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"A3"
)
port map (
I0 => read_Mux_In(0),
I1 => \^q\(0),
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[0]_i_1_n_0\
);
\INFERRED_GEN.icount_out[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(10),
I1 => \icount_out0_carry__1_n_6\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[10]_i_1_n_0\
);
\INFERRED_GEN.icount_out[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(11),
I1 => \icount_out0_carry__1_n_5\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[11]_i_1_n_0\
);
\INFERRED_GEN.icount_out[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(12),
I1 => \icount_out0_carry__1_n_4\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[12]_i_1_n_0\
);
\INFERRED_GEN.icount_out[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(13),
I1 => \icount_out0_carry__2_n_7\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[13]_i_1_n_0\
);
\INFERRED_GEN.icount_out[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(14),
I1 => \icount_out0_carry__2_n_6\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[14]_i_1_n_0\
);
\INFERRED_GEN.icount_out[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(15),
I1 => \icount_out0_carry__2_n_5\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[15]_i_1_n_0\
);
\INFERRED_GEN.icount_out[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(16),
I1 => \icount_out0_carry__2_n_4\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[16]_i_1_n_0\
);
\INFERRED_GEN.icount_out[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(17),
I1 => \icount_out0_carry__3_n_7\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[17]_i_1_n_0\
);
\INFERRED_GEN.icount_out[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(18),
I1 => \icount_out0_carry__3_n_6\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[18]_i_1_n_0\
);
\INFERRED_GEN.icount_out[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(19),
I1 => \icount_out0_carry__3_n_5\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[19]_i_1_n_0\
);
\INFERRED_GEN.icount_out[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(1),
I1 => icount_out0_carry_n_7,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[1]_i_1_n_0\
);
\INFERRED_GEN.icount_out[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(20),
I1 => \icount_out0_carry__3_n_4\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[20]_i_1_n_0\
);
\INFERRED_GEN.icount_out[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(21),
I1 => \icount_out0_carry__4_n_7\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[21]_i_1_n_0\
);
\INFERRED_GEN.icount_out[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(22),
I1 => \icount_out0_carry__4_n_6\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[22]_i_1_n_0\
);
\INFERRED_GEN.icount_out[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(23),
I1 => \icount_out0_carry__4_n_5\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[23]_i_1_n_0\
);
\INFERRED_GEN.icount_out[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(24),
I1 => \icount_out0_carry__4_n_4\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[24]_i_1_n_0\
);
\INFERRED_GEN.icount_out[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(25),
I1 => \icount_out0_carry__5_n_7\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[25]_i_1_n_0\
);
\INFERRED_GEN.icount_out[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(26),
I1 => \icount_out0_carry__5_n_6\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[26]_i_1_n_0\
);
\INFERRED_GEN.icount_out[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(27),
I1 => \icount_out0_carry__5_n_5\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[27]_i_1_n_0\
);
\INFERRED_GEN.icount_out[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(28),
I1 => \icount_out0_carry__5_n_4\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[28]_i_1_n_0\
);
\INFERRED_GEN.icount_out[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(29),
I1 => \icount_out0_carry__6_n_7\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[29]_i_1_n_0\
);
\INFERRED_GEN.icount_out[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(2),
I1 => icount_out0_carry_n_6,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[2]_i_1_n_0\
);
\INFERRED_GEN.icount_out[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(30),
I1 => \icount_out0_carry__6_n_6\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[30]_i_1_n_0\
);
\INFERRED_GEN.icount_out[31]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(31),
I1 => \icount_out0_carry__6_n_5\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[31]_i_2_n_0\
);
\INFERRED_GEN.icount_out[32]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000E200"
)
port map (
I0 => \^counter_tc\(0),
I1 => E(0),
I2 => \icount_out0_carry__6_n_4\,
I3 => s_axi_aresetn,
I4 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[32]_i_1_n_0\
);
\INFERRED_GEN.icount_out[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(3),
I1 => icount_out0_carry_n_5,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[3]_i_1_n_0\
);
\INFERRED_GEN.icount_out[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(4),
I1 => icount_out0_carry_n_4,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[4]_i_1_n_0\
);
\INFERRED_GEN.icount_out[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(5),
I1 => \icount_out0_carry__0_n_7\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[5]_i_1_n_0\
);
\INFERRED_GEN.icount_out[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(6),
I1 => \icount_out0_carry__0_n_6\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[6]_i_1_n_0\
);
\INFERRED_GEN.icount_out[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(7),
I1 => \icount_out0_carry__0_n_5\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[7]_i_1_n_0\
);
\INFERRED_GEN.icount_out[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(8),
I1 => \icount_out0_carry__0_n_4\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[8]_i_1_n_0\
);
\INFERRED_GEN.icount_out[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(9),
I1 => \icount_out0_carry__1_n_7\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[9]_i_1_n_0\
);
\INFERRED_GEN.icount_out_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[0]_i_1_n_0\,
Q => \^q\(0),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[10]_i_1_n_0\,
Q => \^q\(10),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[11]_i_1_n_0\,
Q => \^q\(11),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[12]_i_1_n_0\,
Q => \^q\(12),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[13]_i_1_n_0\,
Q => \^q\(13),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[14]_i_1_n_0\,
Q => \^q\(14),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[15]_i_1_n_0\,
Q => \^q\(15),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[16]_i_1_n_0\,
Q => \^q\(16),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[17]_i_1_n_0\,
Q => \^q\(17),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[18]_i_1_n_0\,
Q => \^q\(18),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[19]_i_1_n_0\,
Q => \^q\(19),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[1]_i_1_n_0\,
Q => \^q\(1),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[20]_i_1_n_0\,
Q => \^q\(20),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[21]_i_1_n_0\,
Q => \^q\(21),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[22]_i_1_n_0\,
Q => \^q\(22),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[23]_i_1_n_0\,
Q => \^q\(23),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[24]_i_1_n_0\,
Q => \^q\(24),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[25]_i_1_n_0\,
Q => \^q\(25),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[26]_i_1_n_0\,
Q => \^q\(26),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[27]_i_1_n_0\,
Q => \^q\(27),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[28]_i_1_n_0\,
Q => \^q\(28),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[29]_i_1_n_0\,
Q => \^q\(29),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[2]_i_1_n_0\,
Q => \^q\(2),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[30]_i_1_n_0\,
Q => \^q\(30),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[31]_i_2_n_0\,
Q => \^q\(31),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[32]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \INFERRED_GEN.icount_out[32]_i_1_n_0\,
Q => \^counter_tc\(0),
R => '0'
);
\INFERRED_GEN.icount_out_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[3]_i_1_n_0\,
Q => \^q\(3),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[4]_i_1_n_0\,
Q => \^q\(4),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[5]_i_1_n_0\,
Q => \^q\(5),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[6]_i_1_n_0\,
Q => \^q\(6),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[7]_i_1_n_0\,
Q => \^q\(7),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[8]_i_1_n_0\,
Q => \^q\(8),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[9]_i_1_n_0\,
Q => \^q\(9),
R => \^sr\(0)
);
generateOutPre1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^counter_tc\(0),
I1 => \counter_TC_Reg_reg[1]\(0),
O => generateOutPre1_reg
);
icount_out0_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => icount_out0_carry_n_0,
CO(2) => icount_out0_carry_n_1,
CO(1) => icount_out0_carry_n_2,
CO(0) => icount_out0_carry_n_3,
CYINIT => \^q\(0),
DI(3 downto 1) => \^q\(3 downto 1),
DI(0) => icount_out0_carry_i_1_n_0,
O(3) => icount_out0_carry_n_4,
O(2) => icount_out0_carry_n_5,
O(1) => icount_out0_carry_n_6,
O(0) => icount_out0_carry_n_7,
S(3) => icount_out0_carry_i_2_n_0,
S(2) => icount_out0_carry_i_3_n_0,
S(1) => icount_out0_carry_i_4_n_0,
S(0) => S(0)
);
\icount_out0_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => icount_out0_carry_n_0,
CO(3) => \icount_out0_carry__0_n_0\,
CO(2) => \icount_out0_carry__0_n_1\,
CO(1) => \icount_out0_carry__0_n_2\,
CO(0) => \icount_out0_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^q\(7 downto 4),
O(3) => \icount_out0_carry__0_n_4\,
O(2) => \icount_out0_carry__0_n_5\,
O(1) => \icount_out0_carry__0_n_6\,
O(0) => \icount_out0_carry__0_n_7\,
S(3) => \icount_out0_carry__0_i_1_n_0\,
S(2) => \icount_out0_carry__0_i_2_n_0\,
S(1) => \icount_out0_carry__0_i_3_n_0\,
S(0) => \icount_out0_carry__0_i_4_n_0\
);
\icount_out0_carry__0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(7),
I1 => \^q\(8),
O => \icount_out0_carry__0_i_1_n_0\
);
\icount_out0_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(6),
I1 => \^q\(7),
O => \icount_out0_carry__0_i_2_n_0\
);
\icount_out0_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(5),
I1 => \^q\(6),
O => \icount_out0_carry__0_i_3_n_0\
);
\icount_out0_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(4),
I1 => \^q\(5),
O => \icount_out0_carry__0_i_4_n_0\
);
\icount_out0_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \icount_out0_carry__0_n_0\,
CO(3) => \icount_out0_carry__1_n_0\,
CO(2) => \icount_out0_carry__1_n_1\,
CO(1) => \icount_out0_carry__1_n_2\,
CO(0) => \icount_out0_carry__1_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^q\(11 downto 8),
O(3) => \icount_out0_carry__1_n_4\,
O(2) => \icount_out0_carry__1_n_5\,
O(1) => \icount_out0_carry__1_n_6\,
O(0) => \icount_out0_carry__1_n_7\,
S(3) => \icount_out0_carry__1_i_1_n_0\,
S(2) => \icount_out0_carry__1_i_2_n_0\,
S(1) => \icount_out0_carry__1_i_3_n_0\,
S(0) => \icount_out0_carry__1_i_4_n_0\
);
\icount_out0_carry__1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(11),
I1 => \^q\(12),
O => \icount_out0_carry__1_i_1_n_0\
);
\icount_out0_carry__1_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(10),
I1 => \^q\(11),
O => \icount_out0_carry__1_i_2_n_0\
);
\icount_out0_carry__1_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(9),
I1 => \^q\(10),
O => \icount_out0_carry__1_i_3_n_0\
);
\icount_out0_carry__1_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(8),
I1 => \^q\(9),
O => \icount_out0_carry__1_i_4_n_0\
);
\icount_out0_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \icount_out0_carry__1_n_0\,
CO(3) => \icount_out0_carry__2_n_0\,
CO(2) => \icount_out0_carry__2_n_1\,
CO(1) => \icount_out0_carry__2_n_2\,
CO(0) => \icount_out0_carry__2_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^q\(15 downto 12),
O(3) => \icount_out0_carry__2_n_4\,
O(2) => \icount_out0_carry__2_n_5\,
O(1) => \icount_out0_carry__2_n_6\,
O(0) => \icount_out0_carry__2_n_7\,
S(3) => \icount_out0_carry__2_i_1_n_0\,
S(2) => \icount_out0_carry__2_i_2_n_0\,
S(1) => \icount_out0_carry__2_i_3_n_0\,
S(0) => \icount_out0_carry__2_i_4_n_0\
);
\icount_out0_carry__2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(15),
I1 => \^q\(16),
O => \icount_out0_carry__2_i_1_n_0\
);
\icount_out0_carry__2_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(14),
I1 => \^q\(15),
O => \icount_out0_carry__2_i_2_n_0\
);
\icount_out0_carry__2_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(13),
I1 => \^q\(14),
O => \icount_out0_carry__2_i_3_n_0\
);
\icount_out0_carry__2_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(12),
I1 => \^q\(13),
O => \icount_out0_carry__2_i_4_n_0\
);
\icount_out0_carry__3\: unisim.vcomponents.CARRY4
port map (
CI => \icount_out0_carry__2_n_0\,
CO(3) => \icount_out0_carry__3_n_0\,
CO(2) => \icount_out0_carry__3_n_1\,
CO(1) => \icount_out0_carry__3_n_2\,
CO(0) => \icount_out0_carry__3_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^q\(19 downto 16),
O(3) => \icount_out0_carry__3_n_4\,
O(2) => \icount_out0_carry__3_n_5\,
O(1) => \icount_out0_carry__3_n_6\,
O(0) => \icount_out0_carry__3_n_7\,
S(3) => \icount_out0_carry__3_i_1_n_0\,
S(2) => \icount_out0_carry__3_i_2_n_0\,
S(1) => \icount_out0_carry__3_i_3_n_0\,
S(0) => \icount_out0_carry__3_i_4_n_0\
);
\icount_out0_carry__3_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(19),
I1 => \^q\(20),
O => \icount_out0_carry__3_i_1_n_0\
);
\icount_out0_carry__3_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(18),
I1 => \^q\(19),
O => \icount_out0_carry__3_i_2_n_0\
);
\icount_out0_carry__3_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(17),
I1 => \^q\(18),
O => \icount_out0_carry__3_i_3_n_0\
);
\icount_out0_carry__3_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(16),
I1 => \^q\(17),
O => \icount_out0_carry__3_i_4_n_0\
);
\icount_out0_carry__4\: unisim.vcomponents.CARRY4
port map (
CI => \icount_out0_carry__3_n_0\,
CO(3) => \icount_out0_carry__4_n_0\,
CO(2) => \icount_out0_carry__4_n_1\,
CO(1) => \icount_out0_carry__4_n_2\,
CO(0) => \icount_out0_carry__4_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^q\(23 downto 20),
O(3) => \icount_out0_carry__4_n_4\,
O(2) => \icount_out0_carry__4_n_5\,
O(1) => \icount_out0_carry__4_n_6\,
O(0) => \icount_out0_carry__4_n_7\,
S(3) => \icount_out0_carry__4_i_1_n_0\,
S(2) => \icount_out0_carry__4_i_2_n_0\,
S(1) => \icount_out0_carry__4_i_3_n_0\,
S(0) => \icount_out0_carry__4_i_4_n_0\
);
\icount_out0_carry__4_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(23),
I1 => \^q\(24),
O => \icount_out0_carry__4_i_1_n_0\
);
\icount_out0_carry__4_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(22),
I1 => \^q\(23),
O => \icount_out0_carry__4_i_2_n_0\
);
\icount_out0_carry__4_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(21),
I1 => \^q\(22),
O => \icount_out0_carry__4_i_3_n_0\
);
\icount_out0_carry__4_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(20),
I1 => \^q\(21),
O => \icount_out0_carry__4_i_4_n_0\
);
\icount_out0_carry__5\: unisim.vcomponents.CARRY4
port map (
CI => \icount_out0_carry__4_n_0\,
CO(3) => \icount_out0_carry__5_n_0\,
CO(2) => \icount_out0_carry__5_n_1\,
CO(1) => \icount_out0_carry__5_n_2\,
CO(0) => \icount_out0_carry__5_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^q\(27 downto 24),
O(3) => \icount_out0_carry__5_n_4\,
O(2) => \icount_out0_carry__5_n_5\,
O(1) => \icount_out0_carry__5_n_6\,
O(0) => \icount_out0_carry__5_n_7\,
S(3) => \icount_out0_carry__5_i_1_n_0\,
S(2) => \icount_out0_carry__5_i_2_n_0\,
S(1) => \icount_out0_carry__5_i_3_n_0\,
S(0) => \icount_out0_carry__5_i_4_n_0\
);
\icount_out0_carry__5_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(27),
I1 => \^q\(28),
O => \icount_out0_carry__5_i_1_n_0\
);
\icount_out0_carry__5_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(26),
I1 => \^q\(27),
O => \icount_out0_carry__5_i_2_n_0\
);
\icount_out0_carry__5_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(25),
I1 => \^q\(26),
O => \icount_out0_carry__5_i_3_n_0\
);
\icount_out0_carry__5_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(24),
I1 => \^q\(25),
O => \icount_out0_carry__5_i_4_n_0\
);
\icount_out0_carry__6\: unisim.vcomponents.CARRY4
port map (
CI => \icount_out0_carry__5_n_0\,
CO(3) => \NLW_icount_out0_carry__6_CO_UNCONNECTED\(3),
CO(2) => \icount_out0_carry__6_n_1\,
CO(1) => \icount_out0_carry__6_n_2\,
CO(0) => \icount_out0_carry__6_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 0) => \^q\(30 downto 28),
O(3) => \icount_out0_carry__6_n_4\,
O(2) => \icount_out0_carry__6_n_5\,
O(1) => \icount_out0_carry__6_n_6\,
O(0) => \icount_out0_carry__6_n_7\,
S(3) => \icount_out0_carry__6_i_1_n_0\,
S(2) => \icount_out0_carry__6_i_2_n_0\,
S(1) => \icount_out0_carry__6_i_3_n_0\,
S(0) => \icount_out0_carry__6_i_4_n_0\
);
\icount_out0_carry__6_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(31),
O => \icount_out0_carry__6_i_1_n_0\
);
\icount_out0_carry__6_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(30),
I1 => \^q\(31),
O => \icount_out0_carry__6_i_2_n_0\
);
\icount_out0_carry__6_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(29),
I1 => \^q\(30),
O => \icount_out0_carry__6_i_3_n_0\
);
\icount_out0_carry__6_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(28),
I1 => \^q\(29),
O => \icount_out0_carry__6_i_4_n_0\
);
icount_out0_carry_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(1),
O => icount_out0_carry_i_1_n_0
);
icount_out0_carry_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(3),
I1 => \^q\(4),
O => icount_out0_carry_i_2_n_0
);
icount_out0_carry_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(2),
I1 => \^q\(3),
O => icount_out0_carry_i_3_n_0
);
icount_out0_carry_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(1),
I1 => \^q\(2),
O => icount_out0_carry_i_4_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_counter_f_3 is
port (
\LOAD_REG_GEN[0].LOAD_REG_I\ : out STD_LOGIC_VECTOR ( 31 downto 0 );
generateOutPre0_reg : out STD_LOGIC;
counter_TC : out STD_LOGIC_VECTOR ( 0 to 0 );
S : in STD_LOGIC_VECTOR ( 0 to 0 );
read_Mux_In : in STD_LOGIC_VECTOR ( 10 downto 0 );
load_Counter_Reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\LOAD_REG_GEN[0].LOAD_REG_I_0\ : in STD_LOGIC_VECTOR ( 20 downto 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aresetn_0 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_counter_f_3 : entity is "counter_f";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_counter_f_3;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_counter_f_3 is
signal \INFERRED_GEN.icount_out[32]_i_1_n_0\ : STD_LOGIC;
signal \^load_reg_gen[0].load_reg_i\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^counter_tc\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \icount_out0_carry__0_i_1__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__0_i_2__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__0_i_3__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__0_i_4__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__0_n_1\ : STD_LOGIC;
signal \icount_out0_carry__0_n_2\ : STD_LOGIC;
signal \icount_out0_carry__0_n_3\ : STD_LOGIC;
signal \icount_out0_carry__0_n_4\ : STD_LOGIC;
signal \icount_out0_carry__0_n_5\ : STD_LOGIC;
signal \icount_out0_carry__0_n_6\ : STD_LOGIC;
signal \icount_out0_carry__0_n_7\ : STD_LOGIC;
signal \icount_out0_carry__1_i_1__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__1_i_2__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__1_i_3__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__1_i_4__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__1_n_0\ : STD_LOGIC;
signal \icount_out0_carry__1_n_1\ : STD_LOGIC;
signal \icount_out0_carry__1_n_2\ : STD_LOGIC;
signal \icount_out0_carry__1_n_3\ : STD_LOGIC;
signal \icount_out0_carry__1_n_4\ : STD_LOGIC;
signal \icount_out0_carry__1_n_5\ : STD_LOGIC;
signal \icount_out0_carry__1_n_6\ : STD_LOGIC;
signal \icount_out0_carry__1_n_7\ : STD_LOGIC;
signal \icount_out0_carry__2_i_1__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__2_i_2__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__2_i_3__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__2_i_4__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__2_n_0\ : STD_LOGIC;
signal \icount_out0_carry__2_n_1\ : STD_LOGIC;
signal \icount_out0_carry__2_n_2\ : STD_LOGIC;
signal \icount_out0_carry__2_n_3\ : STD_LOGIC;
signal \icount_out0_carry__2_n_4\ : STD_LOGIC;
signal \icount_out0_carry__2_n_5\ : STD_LOGIC;
signal \icount_out0_carry__2_n_6\ : STD_LOGIC;
signal \icount_out0_carry__2_n_7\ : STD_LOGIC;
signal \icount_out0_carry__3_i_1__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__3_i_2__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__3_i_3__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__3_i_4__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__3_n_0\ : STD_LOGIC;
signal \icount_out0_carry__3_n_1\ : STD_LOGIC;
signal \icount_out0_carry__3_n_2\ : STD_LOGIC;
signal \icount_out0_carry__3_n_3\ : STD_LOGIC;
signal \icount_out0_carry__3_n_4\ : STD_LOGIC;
signal \icount_out0_carry__3_n_5\ : STD_LOGIC;
signal \icount_out0_carry__3_n_6\ : STD_LOGIC;
signal \icount_out0_carry__3_n_7\ : STD_LOGIC;
signal \icount_out0_carry__4_i_1__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__4_i_2__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__4_i_3__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__4_i_4__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__4_n_0\ : STD_LOGIC;
signal \icount_out0_carry__4_n_1\ : STD_LOGIC;
signal \icount_out0_carry__4_n_2\ : STD_LOGIC;
signal \icount_out0_carry__4_n_3\ : STD_LOGIC;
signal \icount_out0_carry__4_n_4\ : STD_LOGIC;
signal \icount_out0_carry__4_n_5\ : STD_LOGIC;
signal \icount_out0_carry__4_n_6\ : STD_LOGIC;
signal \icount_out0_carry__4_n_7\ : STD_LOGIC;
signal \icount_out0_carry__5_i_1__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__5_i_2__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__5_i_3__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__5_i_4__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__5_n_0\ : STD_LOGIC;
signal \icount_out0_carry__5_n_1\ : STD_LOGIC;
signal \icount_out0_carry__5_n_2\ : STD_LOGIC;
signal \icount_out0_carry__5_n_3\ : STD_LOGIC;
signal \icount_out0_carry__5_n_4\ : STD_LOGIC;
signal \icount_out0_carry__5_n_5\ : STD_LOGIC;
signal \icount_out0_carry__5_n_6\ : STD_LOGIC;
signal \icount_out0_carry__5_n_7\ : STD_LOGIC;
signal \icount_out0_carry__6_i_1__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__6_i_2__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__6_i_3__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__6_i_4__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__6_n_1\ : STD_LOGIC;
signal \icount_out0_carry__6_n_2\ : STD_LOGIC;
signal \icount_out0_carry__6_n_3\ : STD_LOGIC;
signal \icount_out0_carry__6_n_4\ : STD_LOGIC;
signal \icount_out0_carry__6_n_5\ : STD_LOGIC;
signal \icount_out0_carry__6_n_6\ : STD_LOGIC;
signal \icount_out0_carry__6_n_7\ : STD_LOGIC;
signal \icount_out0_carry_i_1__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry_i_2__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry_i_3__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry_i_4__0_n_0\ : STD_LOGIC;
signal icount_out0_carry_n_0 : STD_LOGIC;
signal icount_out0_carry_n_1 : STD_LOGIC;
signal icount_out0_carry_n_2 : STD_LOGIC;
signal icount_out0_carry_n_3 : STD_LOGIC;
signal icount_out0_carry_n_4 : STD_LOGIC;
signal icount_out0_carry_n_5 : STD_LOGIC;
signal icount_out0_carry_n_6 : STD_LOGIC;
signal icount_out0_carry_n_7 : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_icount_out0_carry__6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[0]_i_1__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[10]_i_1__0\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[11]_i_1__0\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[12]_i_1__0\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[13]_i_1__0\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[14]_i_1__0\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[15]_i_1__0\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[16]_i_1__0\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[17]_i_1__0\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[18]_i_1__0\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[19]_i_1__0\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[1]_i_1__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[20]_i_1__0\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[21]_i_1__0\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[22]_i_1__0\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[23]_i_1__0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[24]_i_1__0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[25]_i_1__0\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[26]_i_1__0\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[27]_i_1__0\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[28]_i_1__0\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[29]_i_1__0\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[2]_i_1__0\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[30]_i_1__0\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[31]_i_2__0\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[3]_i_1__0\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[4]_i_1__0\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[5]_i_1__0\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[6]_i_1__0\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[7]_i_1__0\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[8]_i_1__0\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[9]_i_1__0\ : label is "soft_lutpair29";
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of icount_out0_carry : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__0\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__1\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__2\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__3\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__4\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__5\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__6\ : label is "{SYNTH-8 {cell *THIS*}}";
begin
\LOAD_REG_GEN[0].LOAD_REG_I\(31 downto 0) <= \^load_reg_gen[0].load_reg_i\(31 downto 0);
counter_TC(0) <= \^counter_tc\(0);
\INFERRED_GEN.icount_out[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => read_Mux_In(0),
I1 => load_Counter_Reg(0),
I2 => \^load_reg_gen[0].load_reg_i\(0),
O => p_1_in(0)
);
\INFERRED_GEN.icount_out[10]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => read_Mux_In(10),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__1_n_6\,
O => p_1_in(10)
);
\INFERRED_GEN.icount_out[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(0),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__1_n_5\,
O => p_1_in(11)
);
\INFERRED_GEN.icount_out[12]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(1),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__1_n_4\,
O => p_1_in(12)
);
\INFERRED_GEN.icount_out[13]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(2),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__2_n_7\,
O => p_1_in(13)
);
\INFERRED_GEN.icount_out[14]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(3),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__2_n_6\,
O => p_1_in(14)
);
\INFERRED_GEN.icount_out[15]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(4),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__2_n_5\,
O => p_1_in(15)
);
\INFERRED_GEN.icount_out[16]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(5),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__2_n_4\,
O => p_1_in(16)
);
\INFERRED_GEN.icount_out[17]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(6),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__3_n_7\,
O => p_1_in(17)
);
\INFERRED_GEN.icount_out[18]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(7),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__3_n_6\,
O => p_1_in(18)
);
\INFERRED_GEN.icount_out[19]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(8),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__3_n_5\,
O => p_1_in(19)
);
\INFERRED_GEN.icount_out[1]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => read_Mux_In(1),
I1 => load_Counter_Reg(0),
I2 => icount_out0_carry_n_7,
O => p_1_in(1)
);
\INFERRED_GEN.icount_out[20]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(9),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__3_n_4\,
O => p_1_in(20)
);
\INFERRED_GEN.icount_out[21]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(10),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__4_n_7\,
O => p_1_in(21)
);
\INFERRED_GEN.icount_out[22]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(11),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__4_n_6\,
O => p_1_in(22)
);
\INFERRED_GEN.icount_out[23]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(12),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__4_n_5\,
O => p_1_in(23)
);
\INFERRED_GEN.icount_out[24]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(13),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__4_n_4\,
O => p_1_in(24)
);
\INFERRED_GEN.icount_out[25]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(14),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__5_n_7\,
O => p_1_in(25)
);
\INFERRED_GEN.icount_out[26]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(15),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__5_n_6\,
O => p_1_in(26)
);
\INFERRED_GEN.icount_out[27]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(16),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__5_n_5\,
O => p_1_in(27)
);
\INFERRED_GEN.icount_out[28]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(17),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__5_n_4\,
O => p_1_in(28)
);
\INFERRED_GEN.icount_out[29]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(18),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__6_n_7\,
O => p_1_in(29)
);
\INFERRED_GEN.icount_out[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => read_Mux_In(2),
I1 => load_Counter_Reg(0),
I2 => icount_out0_carry_n_6,
O => p_1_in(2)
);
\INFERRED_GEN.icount_out[30]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(19),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__6_n_6\,
O => p_1_in(30)
);
\INFERRED_GEN.icount_out[31]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(20),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__6_n_5\,
O => p_1_in(31)
);
\INFERRED_GEN.icount_out[32]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000E200"
)
port map (
I0 => \^counter_tc\(0),
I1 => E(0),
I2 => \icount_out0_carry__6_n_4\,
I3 => s_axi_aresetn,
I4 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[32]_i_1_n_0\
);
\INFERRED_GEN.icount_out[3]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => read_Mux_In(3),
I1 => load_Counter_Reg(0),
I2 => icount_out0_carry_n_5,
O => p_1_in(3)
);
\INFERRED_GEN.icount_out[4]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => read_Mux_In(4),
I1 => load_Counter_Reg(0),
I2 => icount_out0_carry_n_4,
O => p_1_in(4)
);
\INFERRED_GEN.icount_out[5]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => read_Mux_In(5),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__0_n_7\,
O => p_1_in(5)
);
\INFERRED_GEN.icount_out[6]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => read_Mux_In(6),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__0_n_6\,
O => p_1_in(6)
);
\INFERRED_GEN.icount_out[7]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => read_Mux_In(7),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__0_n_5\,
O => p_1_in(7)
);
\INFERRED_GEN.icount_out[8]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => read_Mux_In(8),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__0_n_4\,
O => p_1_in(8)
);
\INFERRED_GEN.icount_out[9]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => read_Mux_In(9),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__1_n_7\,
O => p_1_in(9)
);
\INFERRED_GEN.icount_out_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(0),
Q => \^load_reg_gen[0].load_reg_i\(0),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(10),
Q => \^load_reg_gen[0].load_reg_i\(10),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(11),
Q => \^load_reg_gen[0].load_reg_i\(11),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(12),
Q => \^load_reg_gen[0].load_reg_i\(12),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(13),
Q => \^load_reg_gen[0].load_reg_i\(13),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(14),
Q => \^load_reg_gen[0].load_reg_i\(14),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(15),
Q => \^load_reg_gen[0].load_reg_i\(15),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(16),
Q => \^load_reg_gen[0].load_reg_i\(16),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(17),
Q => \^load_reg_gen[0].load_reg_i\(17),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(18),
Q => \^load_reg_gen[0].load_reg_i\(18),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(19),
Q => \^load_reg_gen[0].load_reg_i\(19),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(1),
Q => \^load_reg_gen[0].load_reg_i\(1),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(20),
Q => \^load_reg_gen[0].load_reg_i\(20),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(21),
Q => \^load_reg_gen[0].load_reg_i\(21),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(22),
Q => \^load_reg_gen[0].load_reg_i\(22),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(23),
Q => \^load_reg_gen[0].load_reg_i\(23),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(24),
Q => \^load_reg_gen[0].load_reg_i\(24),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(25),
Q => \^load_reg_gen[0].load_reg_i\(25),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(26),
Q => \^load_reg_gen[0].load_reg_i\(26),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(27),
Q => \^load_reg_gen[0].load_reg_i\(27),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(28),
Q => \^load_reg_gen[0].load_reg_i\(28),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(29),
Q => \^load_reg_gen[0].load_reg_i\(29),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(2),
Q => \^load_reg_gen[0].load_reg_i\(2),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(30),
Q => \^load_reg_gen[0].load_reg_i\(30),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(31),
Q => \^load_reg_gen[0].load_reg_i\(31),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[32]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \INFERRED_GEN.icount_out[32]_i_1_n_0\,
Q => \^counter_tc\(0),
R => '0'
);
\INFERRED_GEN.icount_out_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(3),
Q => \^load_reg_gen[0].load_reg_i\(3),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(4),
Q => \^load_reg_gen[0].load_reg_i\(4),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(5),
Q => \^load_reg_gen[0].load_reg_i\(5),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(6),
Q => \^load_reg_gen[0].load_reg_i\(6),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(7),
Q => \^load_reg_gen[0].load_reg_i\(7),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(8),
Q => \^load_reg_gen[0].load_reg_i\(8),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(9),
Q => \^load_reg_gen[0].load_reg_i\(9),
R => s_axi_aresetn_0
);
generateOutPre0_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^counter_tc\(0),
I1 => Q(0),
O => generateOutPre0_reg
);
icount_out0_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => icount_out0_carry_n_0,
CO(2) => icount_out0_carry_n_1,
CO(1) => icount_out0_carry_n_2,
CO(0) => icount_out0_carry_n_3,
CYINIT => \^load_reg_gen[0].load_reg_i\(0),
DI(3 downto 1) => \^load_reg_gen[0].load_reg_i\(3 downto 1),
DI(0) => \icount_out0_carry_i_1__0_n_0\,
O(3) => icount_out0_carry_n_4,
O(2) => icount_out0_carry_n_5,
O(1) => icount_out0_carry_n_6,
O(0) => icount_out0_carry_n_7,
S(3) => \icount_out0_carry_i_2__0_n_0\,
S(2) => \icount_out0_carry_i_3__0_n_0\,
S(1) => \icount_out0_carry_i_4__0_n_0\,
S(0) => S(0)
);
\icount_out0_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => icount_out0_carry_n_0,
CO(3) => \icount_out0_carry__0_n_0\,
CO(2) => \icount_out0_carry__0_n_1\,
CO(1) => \icount_out0_carry__0_n_2\,
CO(0) => \icount_out0_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^load_reg_gen[0].load_reg_i\(7 downto 4),
O(3) => \icount_out0_carry__0_n_4\,
O(2) => \icount_out0_carry__0_n_5\,
O(1) => \icount_out0_carry__0_n_6\,
O(0) => \icount_out0_carry__0_n_7\,
S(3) => \icount_out0_carry__0_i_1__0_n_0\,
S(2) => \icount_out0_carry__0_i_2__0_n_0\,
S(1) => \icount_out0_carry__0_i_3__0_n_0\,
S(0) => \icount_out0_carry__0_i_4__0_n_0\
);
\icount_out0_carry__0_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(7),
I1 => \^load_reg_gen[0].load_reg_i\(8),
O => \icount_out0_carry__0_i_1__0_n_0\
);
\icount_out0_carry__0_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(6),
I1 => \^load_reg_gen[0].load_reg_i\(7),
O => \icount_out0_carry__0_i_2__0_n_0\
);
\icount_out0_carry__0_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(5),
I1 => \^load_reg_gen[0].load_reg_i\(6),
O => \icount_out0_carry__0_i_3__0_n_0\
);
\icount_out0_carry__0_i_4__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(4),
I1 => \^load_reg_gen[0].load_reg_i\(5),
O => \icount_out0_carry__0_i_4__0_n_0\
);
\icount_out0_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \icount_out0_carry__0_n_0\,
CO(3) => \icount_out0_carry__1_n_0\,
CO(2) => \icount_out0_carry__1_n_1\,
CO(1) => \icount_out0_carry__1_n_2\,
CO(0) => \icount_out0_carry__1_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^load_reg_gen[0].load_reg_i\(11 downto 8),
O(3) => \icount_out0_carry__1_n_4\,
O(2) => \icount_out0_carry__1_n_5\,
O(1) => \icount_out0_carry__1_n_6\,
O(0) => \icount_out0_carry__1_n_7\,
S(3) => \icount_out0_carry__1_i_1__0_n_0\,
S(2) => \icount_out0_carry__1_i_2__0_n_0\,
S(1) => \icount_out0_carry__1_i_3__0_n_0\,
S(0) => \icount_out0_carry__1_i_4__0_n_0\
);
\icount_out0_carry__1_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(11),
I1 => \^load_reg_gen[0].load_reg_i\(12),
O => \icount_out0_carry__1_i_1__0_n_0\
);
\icount_out0_carry__1_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(10),
I1 => \^load_reg_gen[0].load_reg_i\(11),
O => \icount_out0_carry__1_i_2__0_n_0\
);
\icount_out0_carry__1_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(9),
I1 => \^load_reg_gen[0].load_reg_i\(10),
O => \icount_out0_carry__1_i_3__0_n_0\
);
\icount_out0_carry__1_i_4__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(8),
I1 => \^load_reg_gen[0].load_reg_i\(9),
O => \icount_out0_carry__1_i_4__0_n_0\
);
\icount_out0_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \icount_out0_carry__1_n_0\,
CO(3) => \icount_out0_carry__2_n_0\,
CO(2) => \icount_out0_carry__2_n_1\,
CO(1) => \icount_out0_carry__2_n_2\,
CO(0) => \icount_out0_carry__2_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^load_reg_gen[0].load_reg_i\(15 downto 12),
O(3) => \icount_out0_carry__2_n_4\,
O(2) => \icount_out0_carry__2_n_5\,
O(1) => \icount_out0_carry__2_n_6\,
O(0) => \icount_out0_carry__2_n_7\,
S(3) => \icount_out0_carry__2_i_1__0_n_0\,
S(2) => \icount_out0_carry__2_i_2__0_n_0\,
S(1) => \icount_out0_carry__2_i_3__0_n_0\,
S(0) => \icount_out0_carry__2_i_4__0_n_0\
);
\icount_out0_carry__2_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(15),
I1 => \^load_reg_gen[0].load_reg_i\(16),
O => \icount_out0_carry__2_i_1__0_n_0\
);
\icount_out0_carry__2_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(14),
I1 => \^load_reg_gen[0].load_reg_i\(15),
O => \icount_out0_carry__2_i_2__0_n_0\
);
\icount_out0_carry__2_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(13),
I1 => \^load_reg_gen[0].load_reg_i\(14),
O => \icount_out0_carry__2_i_3__0_n_0\
);
\icount_out0_carry__2_i_4__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(12),
I1 => \^load_reg_gen[0].load_reg_i\(13),
O => \icount_out0_carry__2_i_4__0_n_0\
);
\icount_out0_carry__3\: unisim.vcomponents.CARRY4
port map (
CI => \icount_out0_carry__2_n_0\,
CO(3) => \icount_out0_carry__3_n_0\,
CO(2) => \icount_out0_carry__3_n_1\,
CO(1) => \icount_out0_carry__3_n_2\,
CO(0) => \icount_out0_carry__3_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^load_reg_gen[0].load_reg_i\(19 downto 16),
O(3) => \icount_out0_carry__3_n_4\,
O(2) => \icount_out0_carry__3_n_5\,
O(1) => \icount_out0_carry__3_n_6\,
O(0) => \icount_out0_carry__3_n_7\,
S(3) => \icount_out0_carry__3_i_1__0_n_0\,
S(2) => \icount_out0_carry__3_i_2__0_n_0\,
S(1) => \icount_out0_carry__3_i_3__0_n_0\,
S(0) => \icount_out0_carry__3_i_4__0_n_0\
);
\icount_out0_carry__3_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(19),
I1 => \^load_reg_gen[0].load_reg_i\(20),
O => \icount_out0_carry__3_i_1__0_n_0\
);
\icount_out0_carry__3_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(18),
I1 => \^load_reg_gen[0].load_reg_i\(19),
O => \icount_out0_carry__3_i_2__0_n_0\
);
\icount_out0_carry__3_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(17),
I1 => \^load_reg_gen[0].load_reg_i\(18),
O => \icount_out0_carry__3_i_3__0_n_0\
);
\icount_out0_carry__3_i_4__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(16),
I1 => \^load_reg_gen[0].load_reg_i\(17),
O => \icount_out0_carry__3_i_4__0_n_0\
);
\icount_out0_carry__4\: unisim.vcomponents.CARRY4
port map (
CI => \icount_out0_carry__3_n_0\,
CO(3) => \icount_out0_carry__4_n_0\,
CO(2) => \icount_out0_carry__4_n_1\,
CO(1) => \icount_out0_carry__4_n_2\,
CO(0) => \icount_out0_carry__4_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^load_reg_gen[0].load_reg_i\(23 downto 20),
O(3) => \icount_out0_carry__4_n_4\,
O(2) => \icount_out0_carry__4_n_5\,
O(1) => \icount_out0_carry__4_n_6\,
O(0) => \icount_out0_carry__4_n_7\,
S(3) => \icount_out0_carry__4_i_1__0_n_0\,
S(2) => \icount_out0_carry__4_i_2__0_n_0\,
S(1) => \icount_out0_carry__4_i_3__0_n_0\,
S(0) => \icount_out0_carry__4_i_4__0_n_0\
);
\icount_out0_carry__4_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(23),
I1 => \^load_reg_gen[0].load_reg_i\(24),
O => \icount_out0_carry__4_i_1__0_n_0\
);
\icount_out0_carry__4_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(22),
I1 => \^load_reg_gen[0].load_reg_i\(23),
O => \icount_out0_carry__4_i_2__0_n_0\
);
\icount_out0_carry__4_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(21),
I1 => \^load_reg_gen[0].load_reg_i\(22),
O => \icount_out0_carry__4_i_3__0_n_0\
);
\icount_out0_carry__4_i_4__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(20),
I1 => \^load_reg_gen[0].load_reg_i\(21),
O => \icount_out0_carry__4_i_4__0_n_0\
);
\icount_out0_carry__5\: unisim.vcomponents.CARRY4
port map (
CI => \icount_out0_carry__4_n_0\,
CO(3) => \icount_out0_carry__5_n_0\,
CO(2) => \icount_out0_carry__5_n_1\,
CO(1) => \icount_out0_carry__5_n_2\,
CO(0) => \icount_out0_carry__5_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^load_reg_gen[0].load_reg_i\(27 downto 24),
O(3) => \icount_out0_carry__5_n_4\,
O(2) => \icount_out0_carry__5_n_5\,
O(1) => \icount_out0_carry__5_n_6\,
O(0) => \icount_out0_carry__5_n_7\,
S(3) => \icount_out0_carry__5_i_1__0_n_0\,
S(2) => \icount_out0_carry__5_i_2__0_n_0\,
S(1) => \icount_out0_carry__5_i_3__0_n_0\,
S(0) => \icount_out0_carry__5_i_4__0_n_0\
);
\icount_out0_carry__5_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(27),
I1 => \^load_reg_gen[0].load_reg_i\(28),
O => \icount_out0_carry__5_i_1__0_n_0\
);
\icount_out0_carry__5_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(26),
I1 => \^load_reg_gen[0].load_reg_i\(27),
O => \icount_out0_carry__5_i_2__0_n_0\
);
\icount_out0_carry__5_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(25),
I1 => \^load_reg_gen[0].load_reg_i\(26),
O => \icount_out0_carry__5_i_3__0_n_0\
);
\icount_out0_carry__5_i_4__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(24),
I1 => \^load_reg_gen[0].load_reg_i\(25),
O => \icount_out0_carry__5_i_4__0_n_0\
);
\icount_out0_carry__6\: unisim.vcomponents.CARRY4
port map (
CI => \icount_out0_carry__5_n_0\,
CO(3) => \NLW_icount_out0_carry__6_CO_UNCONNECTED\(3),
CO(2) => \icount_out0_carry__6_n_1\,
CO(1) => \icount_out0_carry__6_n_2\,
CO(0) => \icount_out0_carry__6_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 0) => \^load_reg_gen[0].load_reg_i\(30 downto 28),
O(3) => \icount_out0_carry__6_n_4\,
O(2) => \icount_out0_carry__6_n_5\,
O(1) => \icount_out0_carry__6_n_6\,
O(0) => \icount_out0_carry__6_n_7\,
S(3) => \icount_out0_carry__6_i_1__0_n_0\,
S(2) => \icount_out0_carry__6_i_2__0_n_0\,
S(1) => \icount_out0_carry__6_i_3__0_n_0\,
S(0) => \icount_out0_carry__6_i_4__0_n_0\
);
\icount_out0_carry__6_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(31),
O => \icount_out0_carry__6_i_1__0_n_0\
);
\icount_out0_carry__6_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(30),
I1 => \^load_reg_gen[0].load_reg_i\(31),
O => \icount_out0_carry__6_i_2__0_n_0\
);
\icount_out0_carry__6_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(29),
I1 => \^load_reg_gen[0].load_reg_i\(30),
O => \icount_out0_carry__6_i_3__0_n_0\
);
\icount_out0_carry__6_i_4__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(28),
I1 => \^load_reg_gen[0].load_reg_i\(29),
O => \icount_out0_carry__6_i_4__0_n_0\
);
\icount_out0_carry_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(1),
O => \icount_out0_carry_i_1__0_n_0\
);
\icount_out0_carry_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(3),
I1 => \^load_reg_gen[0].load_reg_i\(4),
O => \icount_out0_carry_i_2__0_n_0\
);
\icount_out0_carry_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(2),
I1 => \^load_reg_gen[0].load_reg_i\(3),
O => \icount_out0_carry_i_3__0_n_0\
);
\icount_out0_carry_i_4__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(1),
I1 => \^load_reg_gen[0].load_reg_i\(2),
O => \icount_out0_carry_i_4__0_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mux_onehot_f is
port (
D : out STD_LOGIC_VECTOR ( 31 downto 0 );
Bus_RNW_reg_reg : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[31]\ : in STD_LOGIC;
Bus_RNW_reg_reg_0 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[30]\ : in STD_LOGIC;
Bus_RNW_reg_reg_1 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[29]\ : in STD_LOGIC;
Bus_RNW_reg_reg_2 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[28]\ : in STD_LOGIC;
Bus_RNW_reg_reg_3 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[27]\ : in STD_LOGIC;
Bus_RNW_reg_reg_4 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[26]\ : in STD_LOGIC;
Bus_RNW_reg_reg_5 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[25]\ : in STD_LOGIC;
Bus_RNW_reg_reg_6 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[24]\ : in STD_LOGIC;
Bus_RNW_reg_reg_7 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[23]\ : in STD_LOGIC;
Bus_RNW_reg_reg_8 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[22]\ : in STD_LOGIC;
Bus_RNW_reg_reg_9 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[21]\ : in STD_LOGIC;
Bus_RNW_reg_reg_10 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[20]\ : in STD_LOGIC;
Bus_RNW_reg_reg_11 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[19]\ : in STD_LOGIC;
Bus_RNW_reg_reg_12 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[18]\ : in STD_LOGIC;
Bus_RNW_reg_reg_13 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[17]\ : in STD_LOGIC;
Bus_RNW_reg_reg_14 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[16]\ : in STD_LOGIC;
Bus_RNW_reg_reg_15 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[15]\ : in STD_LOGIC;
Bus_RNW_reg_reg_16 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[14]\ : in STD_LOGIC;
Bus_RNW_reg_reg_17 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[13]\ : in STD_LOGIC;
Bus_RNW_reg_reg_18 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[12]\ : in STD_LOGIC;
\LOAD_REG_GEN[20].LOAD_REG_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[11]\ : in STD_LOGIC;
\LOAD_REG_GEN[21].LOAD_REG_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[10]\ : in STD_LOGIC;
\LOAD_REG_GEN[22].LOAD_REG_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[9]\ : in STD_LOGIC;
\LOAD_REG_GEN[23].LOAD_REG_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[8]\ : in STD_LOGIC;
\LOAD_REG_GEN[24].LOAD_REG_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[7]\ : in STD_LOGIC;
\LOAD_REG_GEN[25].LOAD_REG_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[6]\ : in STD_LOGIC;
\LOAD_REG_GEN[26].LOAD_REG_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[5]\ : in STD_LOGIC;
\LOAD_REG_GEN[27].LOAD_REG_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[4]\ : in STD_LOGIC;
\LOAD_REG_GEN[28].LOAD_REG_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[3]\ : in STD_LOGIC;
\LOAD_REG_GEN[29].LOAD_REG_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[2]\ : in STD_LOGIC;
\LOAD_REG_GEN[30].LOAD_REG_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[1]\ : in STD_LOGIC;
\LOAD_REG_GEN[31].LOAD_REG_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[0]\ : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mux_onehot_f;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mux_onehot_f is
signal \GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal cyout_1 : STD_LOGIC;
signal \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
begin
\GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(31),
CO(0) => cyout_1,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[31]\,
S(0) => Bus_RNW_reg_reg
);
\GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(21),
CO(0) => \GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[21]\,
S(0) => Bus_RNW_reg_reg_9
);
\GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(20),
CO(0) => \GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[20]\,
S(0) => Bus_RNW_reg_reg_10
);
\GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(19),
CO(0) => \GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[19]\,
S(0) => Bus_RNW_reg_reg_11
);
\GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(18),
CO(0) => \GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[18]\,
S(0) => Bus_RNW_reg_reg_12
);
\GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(17),
CO(0) => \GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[17]\,
S(0) => Bus_RNW_reg_reg_13
);
\GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(16),
CO(0) => \GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[16]\,
S(0) => Bus_RNW_reg_reg_14
);
\GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(15),
CO(0) => \GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[15]\,
S(0) => Bus_RNW_reg_reg_15
);
\GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(14),
CO(0) => \GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[14]\,
S(0) => Bus_RNW_reg_reg_16
);
\GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(13),
CO(0) => \GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[13]\,
S(0) => Bus_RNW_reg_reg_17
);
\GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(12),
CO(0) => \GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[12]\,
S(0) => Bus_RNW_reg_reg_18
);
\GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(30),
CO(0) => \GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[30]\,
S(0) => Bus_RNW_reg_reg_0
);
\GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(11),
CO(0) => \GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[11]\,
S(0) => \LOAD_REG_GEN[20].LOAD_REG_I\
);
\GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(10),
CO(0) => \GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[10]\,
S(0) => \LOAD_REG_GEN[21].LOAD_REG_I\
);
\GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(9),
CO(0) => \GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[9]\,
S(0) => \LOAD_REG_GEN[22].LOAD_REG_I\
);
\GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(8),
CO(0) => \GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[8]\,
S(0) => \LOAD_REG_GEN[23].LOAD_REG_I\
);
\GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(7),
CO(0) => \GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[7]\,
S(0) => \LOAD_REG_GEN[24].LOAD_REG_I\
);
\GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(6),
CO(0) => \GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[6]\,
S(0) => \LOAD_REG_GEN[25].LOAD_REG_I\
);
\GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(5),
CO(0) => \GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[5]\,
S(0) => \LOAD_REG_GEN[26].LOAD_REG_I\
);
\GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(4),
CO(0) => \GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[4]\,
S(0) => \LOAD_REG_GEN[27].LOAD_REG_I\
);
\GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(3),
CO(0) => \GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[3]\,
S(0) => \LOAD_REG_GEN[28].LOAD_REG_I\
);
\GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(2),
CO(0) => \GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[2]\,
S(0) => \LOAD_REG_GEN[29].LOAD_REG_I\
);
\GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(29),
CO(0) => \GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[29]\,
S(0) => Bus_RNW_reg_reg_1
);
\GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(1),
CO(0) => \GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[1]\,
S(0) => \LOAD_REG_GEN[30].LOAD_REG_I\
);
\GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(0),
CO(0) => \GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[0]\,
S(0) => \LOAD_REG_GEN[31].LOAD_REG_I\
);
\GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(28),
CO(0) => \GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[28]\,
S(0) => Bus_RNW_reg_reg_2
);
\GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(27),
CO(0) => \GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[27]\,
S(0) => Bus_RNW_reg_reg_3
);
\GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(26),
CO(0) => \GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[26]\,
S(0) => Bus_RNW_reg_reg_4
);
\GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(25),
CO(0) => \GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[25]\,
S(0) => Bus_RNW_reg_reg_5
);
\GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(24),
CO(0) => \GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[24]\,
S(0) => Bus_RNW_reg_reg_6
);
\GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(23),
CO(0) => \GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[23]\,
S(0) => Bus_RNW_reg_reg_7
);
\GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(22),
CO(0) => \GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[22]\,
S(0) => Bus_RNW_reg_reg_8
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f is
port (
ce_expnd_i_7 : out STD_LOGIC;
\bus2ip_addr_i_reg[4]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
Q : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f is
begin
CS: unisim.vcomponents.LUT4
generic map(
INIT => X"0010"
)
port map (
I0 => \bus2ip_addr_i_reg[4]\(2),
I1 => \bus2ip_addr_i_reg[4]\(1),
I2 => Q,
I3 => \bus2ip_addr_i_reg[4]\(0),
O => ce_expnd_i_7
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized1\ is
port (
ce_expnd_i_5 : out STD_LOGIC;
\bus2ip_addr_i_reg[4]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
Q : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized1\ : entity is "pselect_f";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized1\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized1\ is
begin
CS: unisim.vcomponents.LUT4
generic map(
INIT => X"1000"
)
port map (
I0 => \bus2ip_addr_i_reg[4]\(2),
I1 => \bus2ip_addr_i_reg[4]\(0),
I2 => Q,
I3 => \bus2ip_addr_i_reg[4]\(1),
O => ce_expnd_i_5
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized3\ is
port (
ce_expnd_i_3 : out STD_LOGIC;
\bus2ip_addr_i_reg[4]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
Q : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized3\ : entity is "pselect_f";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized3\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized3\ is
begin
CS: unisim.vcomponents.LUT4
generic map(
INIT => X"1000"
)
port map (
I0 => \bus2ip_addr_i_reg[4]\(1),
I1 => \bus2ip_addr_i_reg[4]\(0),
I2 => \bus2ip_addr_i_reg[4]\(2),
I3 => Q,
O => ce_expnd_i_3
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized4\ is
port (
ce_expnd_i_2 : out STD_LOGIC;
\bus2ip_addr_i_reg[4]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
Q : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized4\ : entity is "pselect_f";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized4\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized4\ is
begin
CS: unisim.vcomponents.LUT4
generic map(
INIT => X"4000"
)
port map (
I0 => \bus2ip_addr_i_reg[4]\(1),
I1 => \bus2ip_addr_i_reg[4]\(2),
I2 => Q,
I3 => \bus2ip_addr_i_reg[4]\(0),
O => ce_expnd_i_2
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized5\ is
port (
ce_expnd_i_1 : out STD_LOGIC;
\bus2ip_addr_i_reg[4]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
Q : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized5\ : entity is "pselect_f";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized5\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized5\ is
begin
CS: unisim.vcomponents.LUT4
generic map(
INIT => X"4000"
)
port map (
I0 => \bus2ip_addr_i_reg[4]\(0),
I1 => \bus2ip_addr_i_reg[4]\(2),
I2 => Q,
I3 => \bus2ip_addr_i_reg[4]\(1),
O => ce_expnd_i_1
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized6\ is
port (
ce_expnd_i_0 : out STD_LOGIC;
\bus2ip_addr_i_reg[4]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
Q : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized6\ : entity is "pselect_f";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized6\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized6\ is
begin
CS: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \bus2ip_addr_i_reg[4]\(1),
I1 => \bus2ip_addr_i_reg[4]\(0),
I2 => \bus2ip_addr_i_reg[4]\(2),
I3 => Q,
O => ce_expnd_i_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder is
port (
\LOAD_REG_GEN[31].LOAD_REG_I\ : out STD_LOGIC;
\TCSR0_GENERATE[23].TCSR0_FF_I\ : out STD_LOGIC;
\s_axi_rdata_i_reg[12]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[13]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[14]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[15]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[16]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[17]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[18]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[19]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[20]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[21]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[22]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[23]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[24]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[25]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[26]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[27]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[28]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[29]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[30]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[31]\ : out STD_LOGIC;
pair0_Select : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 1 downto 0 );
\s_axi_rdata_i_reg[11]\ : out STD_LOGIC;
\TCSR0_GENERATE[24].TCSR0_FF_I\ : out STD_LOGIC;
\TCSR1_GENERATE[24].TCSR1_FF_I\ : out STD_LOGIC;
\LOAD_REG_GEN[31].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[30].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[29].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[28].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[27].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[26].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[25].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[24].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[23].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[22].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[21].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[20].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[19].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[18].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[17].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[16].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[15].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[14].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[13].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[12].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[11].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[10].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[9].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[8].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[7].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[6].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[5].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[4].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[3].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[2].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[1].LOAD_REG_I\ : out STD_LOGIC;
D_0 : out STD_LOGIC;
\bus2ip_wrce__0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_wrce : out STD_LOGIC_VECTOR ( 1 downto 0 );
\LOAD_REG_GEN[31].LOAD_REG_I_1\ : out STD_LOGIC;
\LOAD_REG_GEN[30].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[29].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[28].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[27].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[26].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[25].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[24].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[23].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[22].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[21].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[20].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[19].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[18].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[17].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[16].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[15].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[14].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[13].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[12].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[11].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[10].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[9].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[8].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[7].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[6].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[5].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[4].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[3].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[2].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[1].LOAD_REG_I_0\ : out STD_LOGIC;
D_1 : out STD_LOGIC;
s_axi_rvalid_i_reg : out STD_LOGIC;
s_axi_rvalid_i_reg_0 : out STD_LOGIC;
s_axi_rvalid_i_reg_1 : out STD_LOGIC;
s_axi_rvalid_i_reg_2 : out STD_LOGIC;
s_axi_bvalid_i_reg : out STD_LOGIC;
\TCSR0_GENERATE[23].TCSR0_FF_I_0\ : out STD_LOGIC;
\TCSR1_GENERATE[23].TCSR1_FF_I\ : out STD_LOGIC;
\s_axi_rdata_i_reg[10]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[0]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[0]_0\ : out STD_LOGIC;
READ_DONE0_I : out STD_LOGIC;
READ_DONE1_I : out STD_LOGIC;
Q : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
read_Mux_In : in STD_LOGIC_VECTOR ( 87 downto 0 );
s_axi_aresetn : in STD_LOGIC;
\state1__2\ : in STD_LOGIC;
s_axi_arvalid_0 : in STD_LOGIC;
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arvalid : in STD_LOGIC;
is_write_reg : in STD_LOGIC;
is_read : in STD_LOGIC;
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_rready : in STD_LOGIC;
s_axi_rvalid_i_reg_3 : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_bvalid_i_reg_0 : in STD_LOGIC;
bus2ip_rnw_i : in STD_LOGIC;
D_2 : in STD_LOGIC;
read_done1 : in STD_LOGIC;
\bus2ip_addr_i_reg[4]\ : in STD_LOGIC_VECTOR ( 2 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder is
signal Bus_RNW_reg_i_1_n_0 : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg\ : STD_LOGIC;
signal \^load_reg_gen[31].load_reg_i\ : STD_LOGIC;
signal \^tcsr0_generate[23].tcsr0_ff_i\ : STD_LOGIC;
signal ce_expnd_i_0 : STD_LOGIC;
signal ce_expnd_i_1 : STD_LOGIC;
signal ce_expnd_i_2 : STD_LOGIC;
signal ce_expnd_i_3 : STD_LOGIC;
signal ce_expnd_i_5 : STD_LOGIC;
signal ce_expnd_i_6 : STD_LOGIC;
signal ce_expnd_i_7 : STD_LOGIC;
signal cs_ce_clr : STD_LOGIC;
signal \eqOp__4\ : STD_LOGIC;
signal \^s_axi_arready\ : STD_LOGIC;
signal s_axi_arready_INST_0_i_4_n_0 : STD_LOGIC;
signal \^s_axi_rvalid_i_reg\ : STD_LOGIC;
signal \^s_axi_rvalid_i_reg_0\ : STD_LOGIC;
signal \^s_axi_rvalid_i_reg_1\ : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
signal s_axi_wready_INST_0_i_1_n_0 : STD_LOGIC;
signal s_axi_wready_INST_0_i_2_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of Bus_RNW_reg_i_1 : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_2\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_3\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_2\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \LOAD_REG_GEN[0].LOAD_REG_I_i_2__0\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \LOAD_REG_GEN[0].LOAD_REG_I_i_7\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \LOAD_REG_GEN[1].LOAD_REG_I_i_1__0\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \LOAD_REG_GEN[2].LOAD_REG_I_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \LOAD_REG_GEN[2].LOAD_REG_I_i_1__0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \LOAD_REG_GEN[3].LOAD_REG_I_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \LOAD_REG_GEN[3].LOAD_REG_I_i_1__0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \LOAD_REG_GEN[4].LOAD_REG_I_i_1__0\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \LOAD_REG_GEN[9].LOAD_REG_I_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of READ_DONE0_I_i_2 : label is "soft_lutpair7";
attribute SOFT_HLUTNM of READ_DONE1_I_i_2 : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \TCSR0_GENERATE[20].TCSR0_FF_I_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \TCSR0_GENERATE[21].TCSR0_FF_I_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \TCSR0_GENERATE[23].TCSR0_FF_I_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \TCSR0_GENERATE[24].TCSR0_FF_I_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \TCSR1_GENERATE[22].TCSR1_FF_I_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \TCSR1_GENERATE[23].TCSR1_FF_I_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \TCSR1_GENERATE[24].TCSR1_FF_I_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of s_axi_arready_INST_0_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of s_axi_arready_INST_0_i_2 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of s_axi_arready_INST_0_i_3 : label is "soft_lutpair8";
attribute SOFT_HLUTNM of s_axi_arready_INST_0_i_4 : label is "soft_lutpair2";
attribute SOFT_HLUTNM of s_axi_wready_INST_0_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of s_axi_wready_INST_0_i_2 : label is "soft_lutpair2";
begin
\LOAD_REG_GEN[31].LOAD_REG_I\ <= \^load_reg_gen[31].load_reg_i\;
\TCSR0_GENERATE[23].TCSR0_FF_I\ <= \^tcsr0_generate[23].tcsr0_ff_i\;
s_axi_arready <= \^s_axi_arready\;
s_axi_rvalid_i_reg <= \^s_axi_rvalid_i_reg\;
s_axi_rvalid_i_reg_0 <= \^s_axi_rvalid_i_reg_0\;
s_axi_rvalid_i_reg_1 <= \^s_axi_rvalid_i_reg_1\;
s_axi_wready <= \^s_axi_wready\;
Bus_RNW_reg_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => bus2ip_rnw_i,
I1 => Q,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => Bus_RNW_reg_i_1_n_0
);
Bus_RNW_reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Bus_RNW_reg_i_1_n_0,
Q => \^tcsr0_generate[23].tcsr0_ff_i\,
R => '0'
);
\GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(84),
O => \s_axi_rdata_i_reg[31]\
);
\GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg\,
I1 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \s_axi_rdata_i_reg[0]_0\
);
\GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I1 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \s_axi_rdata_i_reg[0]\
);
\GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(74),
O => \s_axi_rdata_i_reg[21]\
);
\GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(73),
O => \s_axi_rdata_i_reg[20]\
);
\GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(72),
O => \s_axi_rdata_i_reg[19]\
);
\GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(71),
O => \s_axi_rdata_i_reg[18]\
);
\GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(70),
O => \s_axi_rdata_i_reg[17]\
);
\GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(69),
O => \s_axi_rdata_i_reg[16]\
);
\GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(68),
O => \s_axi_rdata_i_reg[15]\
);
\GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(67),
O => \s_axi_rdata_i_reg[14]\
);
\GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(66),
O => \s_axi_rdata_i_reg[13]\
);
\GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(65),
O => \s_axi_rdata_i_reg[12]\
);
\GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(83),
O => \s_axi_rdata_i_reg[30]\
);
\GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0777FFFF"
)
port map (
I0 => read_Mux_In(64),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(87),
I3 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
I4 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \s_axi_rdata_i_reg[11]\
);
\GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
I1 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \s_axi_rdata_i_reg[10]\
);
\GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(82),
O => \s_axi_rdata_i_reg[29]\
);
\GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(81),
O => \s_axi_rdata_i_reg[28]\
);
\GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(80),
O => \s_axi_rdata_i_reg[27]\
);
\GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(79),
O => \s_axi_rdata_i_reg[26]\
);
\GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(78),
O => \s_axi_rdata_i_reg[25]\
);
\GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(77),
O => \s_axi_rdata_i_reg[24]\
);
\GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(76),
O => \s_axi_rdata_i_reg[23]\
);
\GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(75),
O => \s_axi_rdata_i_reg[22]\
);
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => ce_expnd_i_7,
Q => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"1000"
)
port map (
I0 => \bus2ip_addr_i_reg[4]\(2),
I1 => \bus2ip_addr_i_reg[4]\(1),
I2 => Q,
I3 => \bus2ip_addr_i_reg[4]\(0),
O => ce_expnd_i_6
);
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => ce_expnd_i_6,
Q => \^load_reg_gen[31].load_reg_i\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => ce_expnd_i_5,
Q => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => ce_expnd_i_3,
Q => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => ce_expnd_i_2,
Q => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => ce_expnd_i_1,
Q => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"EF"
)
port map (
I0 => \^s_axi_wready\,
I1 => \^s_axi_arready\,
I2 => s_axi_aresetn,
O => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => ce_expnd_i_0,
Q => \GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg\,
R => cs_ce_clr
);
\LOAD_REG_GEN[0].LOAD_REG_I_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(31),
I1 => read_Mux_In(31),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => D_0
);
\LOAD_REG_GEN[0].LOAD_REG_I_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(31),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(63),
O => D_1
);
\LOAD_REG_GEN[0].LOAD_REG_I_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I1 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \bus2ip_wrce__0\(0)
);
\LOAD_REG_GEN[10].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(21),
I1 => read_Mux_In(21),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[10].LOAD_REG_I\
);
\LOAD_REG_GEN[10].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(21),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(53),
O => \LOAD_REG_GEN[10].LOAD_REG_I_0\
);
\LOAD_REG_GEN[11].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(20),
I1 => read_Mux_In(20),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[11].LOAD_REG_I\
);
\LOAD_REG_GEN[11].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(20),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(52),
O => \LOAD_REG_GEN[11].LOAD_REG_I_0\
);
\LOAD_REG_GEN[12].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(19),
I1 => read_Mux_In(19),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[12].LOAD_REG_I\
);
\LOAD_REG_GEN[12].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(19),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(51),
O => \LOAD_REG_GEN[12].LOAD_REG_I_0\
);
\LOAD_REG_GEN[13].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(18),
I1 => read_Mux_In(18),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[13].LOAD_REG_I\
);
\LOAD_REG_GEN[13].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(18),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(50),
O => \LOAD_REG_GEN[13].LOAD_REG_I_0\
);
\LOAD_REG_GEN[14].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(17),
I1 => read_Mux_In(17),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[14].LOAD_REG_I\
);
\LOAD_REG_GEN[14].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(17),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(49),
O => \LOAD_REG_GEN[14].LOAD_REG_I_0\
);
\LOAD_REG_GEN[15].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(16),
I1 => read_Mux_In(16),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[15].LOAD_REG_I\
);
\LOAD_REG_GEN[15].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(16),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(48),
O => \LOAD_REG_GEN[15].LOAD_REG_I_0\
);
\LOAD_REG_GEN[16].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(15),
I1 => read_Mux_In(15),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[16].LOAD_REG_I\
);
\LOAD_REG_GEN[16].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(15),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(47),
O => \LOAD_REG_GEN[16].LOAD_REG_I_0\
);
\LOAD_REG_GEN[17].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(14),
I1 => read_Mux_In(14),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[17].LOAD_REG_I\
);
\LOAD_REG_GEN[17].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(14),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(46),
O => \LOAD_REG_GEN[17].LOAD_REG_I_0\
);
\LOAD_REG_GEN[18].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(13),
I1 => read_Mux_In(13),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[18].LOAD_REG_I\
);
\LOAD_REG_GEN[18].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(13),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(45),
O => \LOAD_REG_GEN[18].LOAD_REG_I_0\
);
\LOAD_REG_GEN[19].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(12),
I1 => read_Mux_In(12),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[19].LOAD_REG_I\
);
\LOAD_REG_GEN[19].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(12),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(44),
O => \LOAD_REG_GEN[19].LOAD_REG_I_0\
);
\LOAD_REG_GEN[1].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(30),
I1 => read_Mux_In(30),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[1].LOAD_REG_I\
);
\LOAD_REG_GEN[1].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(30),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(62),
O => \LOAD_REG_GEN[1].LOAD_REG_I_0\
);
\LOAD_REG_GEN[20].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(11),
I1 => read_Mux_In(11),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[20].LOAD_REG_I\
);
\LOAD_REG_GEN[20].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(11),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(43),
O => \LOAD_REG_GEN[20].LOAD_REG_I_0\
);
\LOAD_REG_GEN[21].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(10),
I1 => read_Mux_In(10),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[21].LOAD_REG_I\
);
\LOAD_REG_GEN[21].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(10),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(42),
O => \LOAD_REG_GEN[21].LOAD_REG_I_0\
);
\LOAD_REG_GEN[22].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(9),
I1 => read_Mux_In(9),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[22].LOAD_REG_I\
);
\LOAD_REG_GEN[22].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(9),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(41),
O => \LOAD_REG_GEN[22].LOAD_REG_I_0\
);
\LOAD_REG_GEN[23].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(8),
I1 => read_Mux_In(8),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[23].LOAD_REG_I\
);
\LOAD_REG_GEN[23].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(8),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(40),
O => \LOAD_REG_GEN[23].LOAD_REG_I_0\
);
\LOAD_REG_GEN[24].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(7),
I1 => read_Mux_In(7),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[24].LOAD_REG_I\
);
\LOAD_REG_GEN[24].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(7),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(39),
O => \LOAD_REG_GEN[24].LOAD_REG_I_0\
);
\LOAD_REG_GEN[25].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(6),
I1 => read_Mux_In(6),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[25].LOAD_REG_I\
);
\LOAD_REG_GEN[25].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(6),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(38),
O => \LOAD_REG_GEN[25].LOAD_REG_I_0\
);
\LOAD_REG_GEN[26].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(5),
I1 => read_Mux_In(5),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[26].LOAD_REG_I\
);
\LOAD_REG_GEN[26].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(5),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(37),
O => \LOAD_REG_GEN[26].LOAD_REG_I_0\
);
\LOAD_REG_GEN[27].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(4),
I1 => read_Mux_In(4),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[27].LOAD_REG_I\
);
\LOAD_REG_GEN[27].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(4),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(36),
O => \LOAD_REG_GEN[27].LOAD_REG_I_0\
);
\LOAD_REG_GEN[28].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(3),
I1 => read_Mux_In(3),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[28].LOAD_REG_I\
);
\LOAD_REG_GEN[28].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(3),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(35),
O => \LOAD_REG_GEN[28].LOAD_REG_I_0\
);
\LOAD_REG_GEN[29].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(2),
I1 => read_Mux_In(2),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[29].LOAD_REG_I\
);
\LOAD_REG_GEN[29].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(2),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(34),
O => \LOAD_REG_GEN[29].LOAD_REG_I_0\
);
\LOAD_REG_GEN[2].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(29),
I1 => read_Mux_In(29),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[2].LOAD_REG_I\
);
\LOAD_REG_GEN[2].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(29),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(61),
O => \LOAD_REG_GEN[2].LOAD_REG_I_0\
);
\LOAD_REG_GEN[30].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(1),
I1 => read_Mux_In(1),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[30].LOAD_REG_I\
);
\LOAD_REG_GEN[30].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(1),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(33),
O => \LOAD_REG_GEN[30].LOAD_REG_I_0\
);
\LOAD_REG_GEN[31].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(0),
I1 => read_Mux_In(0),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[31].LOAD_REG_I_0\
);
\LOAD_REG_GEN[31].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(0),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(32),
O => \LOAD_REG_GEN[31].LOAD_REG_I_1\
);
\LOAD_REG_GEN[3].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(28),
I1 => read_Mux_In(28),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[3].LOAD_REG_I\
);
\LOAD_REG_GEN[3].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(28),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(60),
O => \LOAD_REG_GEN[3].LOAD_REG_I_0\
);
\LOAD_REG_GEN[4].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(27),
I1 => read_Mux_In(27),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[4].LOAD_REG_I\
);
\LOAD_REG_GEN[4].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(27),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(59),
O => \LOAD_REG_GEN[4].LOAD_REG_I_0\
);
\LOAD_REG_GEN[5].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(26),
I1 => read_Mux_In(26),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[5].LOAD_REG_I\
);
\LOAD_REG_GEN[5].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(26),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(58),
O => \LOAD_REG_GEN[5].LOAD_REG_I_0\
);
\LOAD_REG_GEN[6].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(25),
I1 => read_Mux_In(25),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[6].LOAD_REG_I\
);
\LOAD_REG_GEN[6].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(25),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(57),
O => \LOAD_REG_GEN[6].LOAD_REG_I_0\
);
\LOAD_REG_GEN[7].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(24),
I1 => read_Mux_In(24),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[7].LOAD_REG_I\
);
\LOAD_REG_GEN[7].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(24),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(56),
O => \LOAD_REG_GEN[7].LOAD_REG_I_0\
);
\LOAD_REG_GEN[8].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(23),
I1 => read_Mux_In(23),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[8].LOAD_REG_I\
);
\LOAD_REG_GEN[8].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(23),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(55),
O => \LOAD_REG_GEN[8].LOAD_REG_I_0\
);
\LOAD_REG_GEN[9].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(22),
I1 => read_Mux_In(22),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[9].LOAD_REG_I\
);
\LOAD_REG_GEN[9].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(22),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(54),
O => \LOAD_REG_GEN[9].LOAD_REG_I_0\
);
\MEM_DECODE_GEN[0].PER_CE_GEN[0].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f
port map (
Q => Q,
\bus2ip_addr_i_reg[4]\(2 downto 0) => \bus2ip_addr_i_reg[4]\(2 downto 0),
ce_expnd_i_7 => ce_expnd_i_7
);
\MEM_DECODE_GEN[0].PER_CE_GEN[2].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized1\
port map (
Q => Q,
\bus2ip_addr_i_reg[4]\(2 downto 0) => \bus2ip_addr_i_reg[4]\(2 downto 0),
ce_expnd_i_5 => ce_expnd_i_5
);
\MEM_DECODE_GEN[0].PER_CE_GEN[4].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized3\
port map (
Q => Q,
\bus2ip_addr_i_reg[4]\(2 downto 0) => \bus2ip_addr_i_reg[4]\(2 downto 0),
ce_expnd_i_3 => ce_expnd_i_3
);
\MEM_DECODE_GEN[0].PER_CE_GEN[5].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized4\
port map (
Q => Q,
\bus2ip_addr_i_reg[4]\(2 downto 0) => \bus2ip_addr_i_reg[4]\(2 downto 0),
ce_expnd_i_2 => ce_expnd_i_2
);
\MEM_DECODE_GEN[0].PER_CE_GEN[6].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized5\
port map (
Q => Q,
\bus2ip_addr_i_reg[4]\(2 downto 0) => \bus2ip_addr_i_reg[4]\(2 downto 0),
ce_expnd_i_1 => ce_expnd_i_1
);
\MEM_DECODE_GEN[0].PER_CE_GEN[7].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized6\
port map (
Q => Q,
\bus2ip_addr_i_reg[4]\(2 downto 0) => \bus2ip_addr_i_reg[4]\(2 downto 0),
ce_expnd_i_0 => ce_expnd_i_0
);
READ_DONE0_I_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^load_reg_gen[31].load_reg_i\,
I1 => D_2,
O => READ_DONE0_I
);
READ_DONE1_I_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I1 => read_done1,
O => READ_DONE1_I
);
\TCSR0_GENERATE[20].TCSR0_FF_I_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
I1 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => bus2ip_wrce(1)
);
\TCSR0_GENERATE[21].TCSR0_FF_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"32"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
I1 => \^tcsr0_generate[23].tcsr0_ff_i\,
I2 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\,
O => pair0_Select
);
\TCSR0_GENERATE[23].TCSR0_FF_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20FF"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
I1 => \^tcsr0_generate[23].tcsr0_ff_i\,
I2 => s_axi_wdata(8),
I3 => s_axi_aresetn,
O => \TCSR0_GENERATE[23].TCSR0_FF_I_0\
);
\TCSR0_GENERATE[24].TCSR0_FF_I_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EFEEEAEE"
)
port map (
I0 => s_axi_wdata(10),
I1 => read_Mux_In(86),
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
I4 => s_axi_wdata(7),
O => \TCSR0_GENERATE[24].TCSR0_FF_I\
);
\TCSR1_GENERATE[22].TCSR1_FF_I_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\,
I1 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => bus2ip_wrce(0)
);
\TCSR1_GENERATE[23].TCSR1_FF_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20FF"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\,
I1 => \^tcsr0_generate[23].tcsr0_ff_i\,
I2 => s_axi_wdata(8),
I3 => s_axi_aresetn,
O => \TCSR1_GENERATE[23].TCSR1_FF_I\
);
\TCSR1_GENERATE[24].TCSR1_FF_I_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EFEEEAEE"
)
port map (
I0 => s_axi_wdata(10),
I1 => read_Mux_In(85),
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\,
I4 => s_axi_wdata(7),
O => \TCSR1_GENERATE[24].TCSR1_FF_I\
);
s_axi_arready_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFEFFFEFFFEFF"
)
port map (
I0 => \^s_axi_rvalid_i_reg\,
I1 => \^s_axi_rvalid_i_reg_0\,
I2 => \^s_axi_rvalid_i_reg_1\,
I3 => s_axi_arready_INST_0_i_4_n_0,
I4 => is_read,
I5 => \eqOp__4\,
O => \^s_axi_arready\
);
s_axi_arready_INST_0_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^load_reg_gen[31].load_reg_i\,
I1 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \^s_axi_rvalid_i_reg\
);
s_axi_arready_INST_0_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\,
I1 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \^s_axi_rvalid_i_reg_0\
);
s_axi_arready_INST_0_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
I1 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \^s_axi_rvalid_i_reg_1\
);
s_axi_arready_INST_0_i_4: unisim.vcomponents.LUT5
generic map(
INIT => X"00FF01FF"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg\,
I2 => \GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
I4 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
O => s_axi_arready_INST_0_i_4_n_0
);
s_axi_bvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_wready\,
I1 => \state_reg[1]\(1),
I2 => \state_reg[1]\(0),
I3 => s_axi_bready,
I4 => s_axi_bvalid_i_reg_0,
O => s_axi_bvalid_i_reg
);
s_axi_rvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_arready\,
I1 => \state_reg[1]\(0),
I2 => \state_reg[1]\(1),
I3 => s_axi_rready,
I4 => s_axi_rvalid_i_reg_3,
O => s_axi_rvalid_i_reg_2
);
s_axi_wready_INST_0: unisim.vcomponents.LUT4
generic map(
INIT => X"F777"
)
port map (
I0 => s_axi_wready_INST_0_i_1_n_0,
I1 => s_axi_wready_INST_0_i_2_n_0,
I2 => is_write_reg,
I3 => \eqOp__4\,
O => \^s_axi_wready\
);
s_axi_wready_INST_0_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F0F1"
)
port map (
I0 => \^load_reg_gen[31].load_reg_i\,
I1 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
O => s_axi_wready_INST_0_i_1_n_0
);
s_axi_wready_INST_0_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"FF00FF01"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg\,
I2 => \GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
I4 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
O => s_axi_wready_INST_0_i_2_n_0
);
s_axi_wready_INST_0_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000100"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(4),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(2),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(3),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(5),
I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(0),
I5 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(1),
O => \eqOp__4\
);
\state[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"77FC44FC"
)
port map (
I0 => \state1__2\,
I1 => \state_reg[1]\(0),
I2 => s_axi_arvalid,
I3 => \state_reg[1]\(1),
I4 => \^s_axi_wready\,
O => D(0)
);
\state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"5FFC50FC"
)
port map (
I0 => \state1__2\,
I1 => s_axi_arvalid_0,
I2 => \state_reg[1]\(1),
I3 => \state_reg[1]\(0),
I4 => \^s_axi_arready\,
O => D(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_count_module is
port (
\INFERRED_GEN.icount_out_reg[31]\ : out STD_LOGIC_VECTOR ( 52 downto 0 );
read_Mux_In : out STD_LOGIC_VECTOR ( 10 downto 0 );
generateOutPre0_reg : out STD_LOGIC;
counter_TC : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aresetn_0 : in STD_LOGIC;
\TCSR0_GENERATE[27].TCSR0_FF_I\ : in STD_LOGIC;
D_1 : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_2\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_3\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_4\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_5\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_6\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_7\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_8\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_9\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_10\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_11\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_12\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_13\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_14\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_15\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_16\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_17\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_18\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_19\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_20\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_21\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_22\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_23\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_24\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_25\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_26\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_27\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_28\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_29\ : in STD_LOGIC;
S : in STD_LOGIC_VECTOR ( 0 to 0 );
load_Counter_Reg : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aresetn : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_count_module;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_count_module is
signal \^inferred_gen.icount_out_reg[31]\ : STD_LOGIC_VECTOR ( 52 downto 0 );
signal \^read_mux_in\ : STD_LOGIC_VECTOR ( 10 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of \LOAD_REG_GEN[0].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[10].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[11].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[12].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[13].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[14].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[15].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[16].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[17].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[18].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[19].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[1].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[20].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[21].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[22].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[23].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[24].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[25].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[26].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[27].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[28].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[29].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[2].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[30].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[31].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[3].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[4].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[5].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[6].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[7].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[8].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[9].LOAD_REG_I\ : label is "PRIMITIVE";
begin
\INFERRED_GEN.icount_out_reg[31]\(52 downto 0) <= \^inferred_gen.icount_out_reg[31]\(52 downto 0);
read_Mux_In(10 downto 0) <= \^read_mux_in\(10 downto 0);
COUNTER_I: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_counter_f_3
port map (
E(0) => E(0),
\LOAD_REG_GEN[0].LOAD_REG_I\(31 downto 0) => \^inferred_gen.icount_out_reg[31]\(31 downto 0),
\LOAD_REG_GEN[0].LOAD_REG_I_0\(20 downto 0) => \^inferred_gen.icount_out_reg[31]\(52 downto 32),
Q(0) => Q(0),
S(0) => S(0),
counter_TC(0) => counter_TC(0),
generateOutPre0_reg => generateOutPre0_reg,
load_Counter_Reg(0) => load_Counter_Reg(0),
read_Mux_In(10 downto 0) => \^read_mux_in\(10 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_aresetn_0 => s_axi_aresetn_0
);
\LOAD_REG_GEN[0].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => D_1,
Q => \^inferred_gen.icount_out_reg[31]\(52),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[10].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_8\,
Q => \^inferred_gen.icount_out_reg[31]\(42),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[11].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_9\,
Q => \^inferred_gen.icount_out_reg[31]\(41),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[12].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_10\,
Q => \^inferred_gen.icount_out_reg[31]\(40),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[13].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_11\,
Q => \^inferred_gen.icount_out_reg[31]\(39),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[14].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_12\,
Q => \^inferred_gen.icount_out_reg[31]\(38),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[15].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_13\,
Q => \^inferred_gen.icount_out_reg[31]\(37),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[16].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_14\,
Q => \^inferred_gen.icount_out_reg[31]\(36),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[17].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_15\,
Q => \^inferred_gen.icount_out_reg[31]\(35),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[18].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_16\,
Q => \^inferred_gen.icount_out_reg[31]\(34),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[19].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_17\,
Q => \^inferred_gen.icount_out_reg[31]\(33),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[1].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\,
Q => \^inferred_gen.icount_out_reg[31]\(51),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[20].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_18\,
Q => \^inferred_gen.icount_out_reg[31]\(32),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[21].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_19\,
Q => \^read_mux_in\(10),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[22].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_20\,
Q => \^read_mux_in\(9),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[23].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_21\,
Q => \^read_mux_in\(8),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[24].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_22\,
Q => \^read_mux_in\(7),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[25].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_23\,
Q => \^read_mux_in\(6),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[26].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_24\,
Q => \^read_mux_in\(5),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[27].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_25\,
Q => \^read_mux_in\(4),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[28].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_26\,
Q => \^read_mux_in\(3),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[29].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_27\,
Q => \^read_mux_in\(2),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[2].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\,
Q => \^inferred_gen.icount_out_reg[31]\(50),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[30].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_28\,
Q => \^read_mux_in\(1),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[31].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_29\,
Q => \^read_mux_in\(0),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[3].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1\,
Q => \^inferred_gen.icount_out_reg[31]\(49),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[4].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_2\,
Q => \^inferred_gen.icount_out_reg[31]\(48),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[5].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_3\,
Q => \^inferred_gen.icount_out_reg[31]\(47),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[6].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_4\,
Q => \^inferred_gen.icount_out_reg[31]\(46),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[7].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_5\,
Q => \^inferred_gen.icount_out_reg[31]\(45),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[8].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_6\,
Q => \^inferred_gen.icount_out_reg[31]\(44),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[9].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_7\,
Q => \^inferred_gen.icount_out_reg[31]\(43),
R => s_axi_aresetn_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_count_module_0 is
port (
\INFERRED_GEN.icount_out_reg[31]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 31 downto 0 );
\s_axi_rdata_i_reg[0]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[1]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[2]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[3]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[4]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[5]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[6]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[7]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[8]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[9]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[10]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[11]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[12]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[13]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[14]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[15]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[16]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[17]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[18]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[19]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[20]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[21]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[22]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[23]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[24]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[25]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[26]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[27]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[28]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[29]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[30]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[31]\ : out STD_LOGIC;
generateOutPre1_reg : out STD_LOGIC;
counter_TC : out STD_LOGIC_VECTOR ( 0 to 0 );
\TCSR0_GENERATE[20].TCSR0_FF_I\ : in STD_LOGIC;
D_2 : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[30]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[29]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[28]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[27]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[26]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[25]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[24]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[23]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[22]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[21]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[20]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[19]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[18]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[17]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[16]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[15]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[14]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[13]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[12]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[11]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[10]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[9]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[8]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[7]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[6]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[5]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[4]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[3]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[2]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[1]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[0]\ : in STD_LOGIC;
S : in STD_LOGIC_VECTOR ( 0 to 0 );
load_Counter_Reg : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aresetn : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[31]_0\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
\counter_TC_Reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_count_module_0 : entity is "count_module";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_count_module_0;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_count_module_0 is
signal \^inferred_gen.icount_out_reg[31]\ : STD_LOGIC;
signal read_Mux_In : STD_LOGIC_VECTOR ( 96 to 127 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of \LOAD_REG_GEN[0].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[10].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[11].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[12].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[13].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[14].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[15].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[16].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[17].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[18].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[19].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[1].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[20].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[21].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[22].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[23].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[24].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[25].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[26].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[27].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[28].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[29].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[2].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[30].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[31].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[3].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[4].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[5].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[6].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[7].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[8].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[9].LOAD_REG_I\ : label is "PRIMITIVE";
begin
\INFERRED_GEN.icount_out_reg[31]\ <= \^inferred_gen.icount_out_reg[31]\;
COUNTER_I: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_counter_f
port map (
E(0) => E(0),
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\ => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\ => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\ => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
\INFERRED_GEN.icount_out_reg[31]_0\(31 downto 0) => \INFERRED_GEN.icount_out_reg[31]_0\(31 downto 0),
Q(31 downto 0) => Q(31 downto 0),
S(0) => S(0),
SR(0) => \^inferred_gen.icount_out_reg[31]\,
counter_TC(0) => counter_TC(0),
\counter_TC_Reg_reg[1]\(0) => \counter_TC_Reg_reg[1]\(0),
generateOutPre1_reg => generateOutPre1_reg,
load_Counter_Reg(0) => load_Counter_Reg(0),
read_Mux_In(31) => read_Mux_In(96),
read_Mux_In(30) => read_Mux_In(97),
read_Mux_In(29) => read_Mux_In(98),
read_Mux_In(28) => read_Mux_In(99),
read_Mux_In(27) => read_Mux_In(100),
read_Mux_In(26) => read_Mux_In(101),
read_Mux_In(25) => read_Mux_In(102),
read_Mux_In(24) => read_Mux_In(103),
read_Mux_In(23) => read_Mux_In(104),
read_Mux_In(22) => read_Mux_In(105),
read_Mux_In(21) => read_Mux_In(106),
read_Mux_In(20) => read_Mux_In(107),
read_Mux_In(19) => read_Mux_In(108),
read_Mux_In(18) => read_Mux_In(109),
read_Mux_In(17) => read_Mux_In(110),
read_Mux_In(16) => read_Mux_In(111),
read_Mux_In(15) => read_Mux_In(112),
read_Mux_In(14) => read_Mux_In(113),
read_Mux_In(13) => read_Mux_In(114),
read_Mux_In(12) => read_Mux_In(115),
read_Mux_In(11) => read_Mux_In(116),
read_Mux_In(10) => read_Mux_In(117),
read_Mux_In(9) => read_Mux_In(118),
read_Mux_In(8) => read_Mux_In(119),
read_Mux_In(7) => read_Mux_In(120),
read_Mux_In(6) => read_Mux_In(121),
read_Mux_In(5) => read_Mux_In(122),
read_Mux_In(4) => read_Mux_In(123),
read_Mux_In(3) => read_Mux_In(124),
read_Mux_In(2) => read_Mux_In(125),
read_Mux_In(1) => read_Mux_In(126),
read_Mux_In(0) => read_Mux_In(127),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
\s_axi_rdata_i_reg[0]\ => \s_axi_rdata_i_reg[0]\,
\s_axi_rdata_i_reg[10]\ => \s_axi_rdata_i_reg[10]\,
\s_axi_rdata_i_reg[11]\ => \s_axi_rdata_i_reg[11]\,
\s_axi_rdata_i_reg[12]\ => \s_axi_rdata_i_reg[12]\,
\s_axi_rdata_i_reg[13]\ => \s_axi_rdata_i_reg[13]\,
\s_axi_rdata_i_reg[14]\ => \s_axi_rdata_i_reg[14]\,
\s_axi_rdata_i_reg[15]\ => \s_axi_rdata_i_reg[15]\,
\s_axi_rdata_i_reg[16]\ => \s_axi_rdata_i_reg[16]\,
\s_axi_rdata_i_reg[17]\ => \s_axi_rdata_i_reg[17]\,
\s_axi_rdata_i_reg[18]\ => \s_axi_rdata_i_reg[18]\,
\s_axi_rdata_i_reg[19]\ => \s_axi_rdata_i_reg[19]\,
\s_axi_rdata_i_reg[1]\ => \s_axi_rdata_i_reg[1]\,
\s_axi_rdata_i_reg[20]\ => \s_axi_rdata_i_reg[20]\,
\s_axi_rdata_i_reg[21]\ => \s_axi_rdata_i_reg[21]\,
\s_axi_rdata_i_reg[22]\ => \s_axi_rdata_i_reg[22]\,
\s_axi_rdata_i_reg[23]\ => \s_axi_rdata_i_reg[23]\,
\s_axi_rdata_i_reg[24]\ => \s_axi_rdata_i_reg[24]\,
\s_axi_rdata_i_reg[25]\ => \s_axi_rdata_i_reg[25]\,
\s_axi_rdata_i_reg[26]\ => \s_axi_rdata_i_reg[26]\,
\s_axi_rdata_i_reg[27]\ => \s_axi_rdata_i_reg[27]\,
\s_axi_rdata_i_reg[28]\ => \s_axi_rdata_i_reg[28]\,
\s_axi_rdata_i_reg[29]\ => \s_axi_rdata_i_reg[29]\,
\s_axi_rdata_i_reg[2]\ => \s_axi_rdata_i_reg[2]\,
\s_axi_rdata_i_reg[30]\ => \s_axi_rdata_i_reg[30]\,
\s_axi_rdata_i_reg[31]\ => \s_axi_rdata_i_reg[31]\,
\s_axi_rdata_i_reg[3]\ => \s_axi_rdata_i_reg[3]\,
\s_axi_rdata_i_reg[4]\ => \s_axi_rdata_i_reg[4]\,
\s_axi_rdata_i_reg[5]\ => \s_axi_rdata_i_reg[5]\,
\s_axi_rdata_i_reg[6]\ => \s_axi_rdata_i_reg[6]\,
\s_axi_rdata_i_reg[7]\ => \s_axi_rdata_i_reg[7]\,
\s_axi_rdata_i_reg[8]\ => \s_axi_rdata_i_reg[8]\,
\s_axi_rdata_i_reg[9]\ => \s_axi_rdata_i_reg[9]\
);
\LOAD_REG_GEN[0].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => D_2,
Q => read_Mux_In(96),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[10].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[21]\,
Q => read_Mux_In(106),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[11].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[20]\,
Q => read_Mux_In(107),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[12].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[19]\,
Q => read_Mux_In(108),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[13].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[18]\,
Q => read_Mux_In(109),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[14].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[17]\,
Q => read_Mux_In(110),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[15].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[16]\,
Q => read_Mux_In(111),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[16].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[15]\,
Q => read_Mux_In(112),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[17].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[14]\,
Q => read_Mux_In(113),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[18].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[13]\,
Q => read_Mux_In(114),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[19].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[12]\,
Q => read_Mux_In(115),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[1].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[30]\,
Q => read_Mux_In(97),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[20].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[11]\,
Q => read_Mux_In(116),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[21].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[10]\,
Q => read_Mux_In(117),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[22].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[9]\,
Q => read_Mux_In(118),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[23].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[8]\,
Q => read_Mux_In(119),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[24].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[7]\,
Q => read_Mux_In(120),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[25].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[6]\,
Q => read_Mux_In(121),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[26].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[5]\,
Q => read_Mux_In(122),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[27].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[4]\,
Q => read_Mux_In(123),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[28].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[3]\,
Q => read_Mux_In(124),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[29].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[2]\,
Q => read_Mux_In(125),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[2].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[29]\,
Q => read_Mux_In(98),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[30].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[1]\,
Q => read_Mux_In(126),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[31].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[0]\,
Q => read_Mux_In(127),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[3].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[28]\,
Q => read_Mux_In(99),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[4].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[27]\,
Q => read_Mux_In(100),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[5].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[26]\,
Q => read_Mux_In(101),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[6].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[25]\,
Q => read_Mux_In(102),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[7].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[24]\,
Q => read_Mux_In(103),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[8].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[23]\,
Q => read_Mux_In(104),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[9].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[22]\,
Q => read_Mux_In(105),
R => \^inferred_gen.icount_out_reg[31]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_timer_control is
port (
generateout0 : out STD_LOGIC;
generateout1 : out STD_LOGIC;
interrupt : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
\INFERRED_GEN.icount_out_reg[0]\ : out STD_LOGIC;
\TCSR0_GENERATE[24].TCSR0_FF_I_0\ : out STD_LOGIC;
\TCSR1_GENERATE[23].TCSR1_FF_I_0\ : out STD_LOGIC;
D_0 : out STD_LOGIC;
read_done1 : out STD_LOGIC;
load_Counter_Reg : out STD_LOGIC_VECTOR ( 0 to 1 );
\s_axi_rdata_i_reg[0]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[1]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[2]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[3]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[4]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[5]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[6]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[7]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[8]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[9]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[10]\ : out STD_LOGIC;
R : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\INFERRED_GEN.icount_out_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
PWM_FF_I : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 0 to 0 );
\LOAD_REG_GEN[24].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[24].LOAD_REG_I_0\ : out STD_LOGIC;
\INFERRED_GEN.icount_out_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
\INFERRED_GEN.icount_out_reg[32]\ : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[32]_0\ : in STD_LOGIC;
bus2ip_wrce : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 9 downto 0 );
\LOAD_REG_GEN[21].LOAD_REG_I\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
pair0_Select : in STD_LOGIC;
\TCSR0_GENERATE[24].TCSR0_FF_I_1\ : in STD_LOGIC;
\TCSR1_GENERATE[24].TCSR1_FF_I_0\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ : in STD_LOGIC;
counter_TC : in STD_LOGIC_VECTOR ( 0 to 1 );
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\ : in STD_LOGIC;
pwm0 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
Bus_RNW_reg : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : in STD_LOGIC;
\bus2ip_wrce__0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
freeze : in STD_LOGIC;
capturetrig0 : in STD_LOGIC;
capturetrig1 : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_timer_control;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_timer_control is
signal \^d_0\ : STD_LOGIC;
signal GenerateOut00 : STD_LOGIC;
signal GenerateOut10 : STD_LOGIC;
signal \^inferred_gen.icount_out_reg[0]\ : STD_LOGIC;
signal Interrupt0 : STD_LOGIC;
signal \LOAD_REG_GEN[0].LOAD_REG_I_i_3_n_0\ : STD_LOGIC;
signal \LOAD_REG_GEN[0].LOAD_REG_I_i_5_n_0\ : STD_LOGIC;
signal Load_Counter_Reg028_out : STD_LOGIC;
signal Load_Counter_Reg030_out : STD_LOGIC;
signal Load_Counter_Reg031_out : STD_LOGIC;
signal \Load_Counter_Reg0__0\ : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal READ_DONE0_I_i_3_n_0 : STD_LOGIC;
signal READ_DONE1_I_i_1_n_0 : STD_LOGIC;
signal READ_DONE1_I_i_3_n_0 : STD_LOGIC;
signal R_0 : STD_LOGIC;
signal \TCSR0_GENERATE[23].TCSR0_FF_I_i_2_n_0\ : STD_LOGIC;
signal \^tcsr0_generate[24].tcsr0_ff_i_0\ : STD_LOGIC;
signal \TCSR0_Set2__0\ : STD_LOGIC;
signal \^tcsr1_generate[23].tcsr1_ff_i_0\ : STD_LOGIC;
signal \TCSR1_GENERATE[23].TCSR1_FF_I_i_2_n_0\ : STD_LOGIC;
signal captureTrig0_d : STD_LOGIC;
signal captureTrig0_d0 : STD_LOGIC;
signal captureTrig0_d2 : STD_LOGIC;
signal captureTrig0_pulse_d1 : STD_LOGIC;
signal captureTrig0_pulse_d1_i_1_n_0 : STD_LOGIC;
signal captureTrig0_pulse_d2 : STD_LOGIC;
signal captureTrig1_d : STD_LOGIC;
signal captureTrig1_d0 : STD_LOGIC;
signal captureTrig1_d2 : STD_LOGIC;
signal counter_TC_Reg2 : STD_LOGIC;
signal generateOutPre0 : STD_LOGIC;
signal generateOutPre1 : STD_LOGIC;
signal \^generateout0\ : STD_LOGIC;
signal \^generateout1\ : STD_LOGIC;
signal p_33_in : STD_LOGIC;
signal p_38_in : STD_LOGIC;
signal read_Mux_In : STD_LOGIC_VECTOR ( 21 to 63 );
signal \^read_done1\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of GenerateOut0_i_2 : label is "soft_lutpair50";
attribute SOFT_HLUTNM of GenerateOut1_i_1 : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[31]_i_4\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[31]_i_4__0\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \LOAD_REG_GEN[0].LOAD_REG_I_i_3\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \LOAD_REG_GEN[0].LOAD_REG_I_i_5\ : label is "soft_lutpair53";
attribute BOX_TYPE : string;
attribute BOX_TYPE of READ_DONE0_I : label is "PRIMITIVE";
attribute IS_CE_INVERTED : string;
attribute IS_CE_INVERTED of READ_DONE0_I : label is "1'b0";
attribute IS_S_INVERTED : string;
attribute IS_S_INVERTED of READ_DONE0_I : label is "1'b0";
attribute BOX_TYPE of READ_DONE1_I : label is "PRIMITIVE";
attribute IS_CE_INVERTED of READ_DONE1_I : label is "1'b0";
attribute IS_S_INVERTED of READ_DONE1_I : label is "1'b0";
attribute SOFT_HLUTNM of READ_DONE1_I_i_3 : label is "soft_lutpair52";
attribute BOX_TYPE of \TCSR0_GENERATE[20].TCSR0_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR0_GENERATE[20].TCSR0_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR0_GENERATE[20].TCSR0_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR0_GENERATE[21].TCSR0_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR0_GENERATE[21].TCSR0_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR0_GENERATE[21].TCSR0_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR0_GENERATE[22].TCSR0_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR0_GENERATE[22].TCSR0_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR0_GENERATE[22].TCSR0_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR0_GENERATE[23].TCSR0_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR0_GENERATE[23].TCSR0_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR0_GENERATE[23].TCSR0_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR0_GENERATE[24].TCSR0_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR0_GENERATE[24].TCSR0_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR0_GENERATE[24].TCSR0_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR0_GENERATE[25].TCSR0_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR0_GENERATE[25].TCSR0_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR0_GENERATE[25].TCSR0_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR0_GENERATE[26].TCSR0_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR0_GENERATE[26].TCSR0_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR0_GENERATE[26].TCSR0_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR0_GENERATE[27].TCSR0_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR0_GENERATE[27].TCSR0_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR0_GENERATE[27].TCSR0_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR0_GENERATE[28].TCSR0_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR0_GENERATE[28].TCSR0_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR0_GENERATE[28].TCSR0_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR0_GENERATE[29].TCSR0_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR0_GENERATE[29].TCSR0_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR0_GENERATE[29].TCSR0_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR0_GENERATE[30].TCSR0_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR0_GENERATE[30].TCSR0_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR0_GENERATE[30].TCSR0_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR0_GENERATE[31].TCSR0_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR0_GENERATE[31].TCSR0_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR0_GENERATE[31].TCSR0_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR1_GENERATE[21].TCSR1_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR1_GENERATE[21].TCSR1_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR1_GENERATE[21].TCSR1_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR1_GENERATE[22].TCSR1_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR1_GENERATE[22].TCSR1_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR1_GENERATE[22].TCSR1_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR1_GENERATE[23].TCSR1_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR1_GENERATE[23].TCSR1_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR1_GENERATE[23].TCSR1_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR1_GENERATE[24].TCSR1_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR1_GENERATE[24].TCSR1_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR1_GENERATE[24].TCSR1_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR1_GENERATE[25].TCSR1_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR1_GENERATE[25].TCSR1_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR1_GENERATE[25].TCSR1_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR1_GENERATE[26].TCSR1_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR1_GENERATE[26].TCSR1_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR1_GENERATE[26].TCSR1_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR1_GENERATE[27].TCSR1_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR1_GENERATE[27].TCSR1_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR1_GENERATE[27].TCSR1_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR1_GENERATE[28].TCSR1_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR1_GENERATE[28].TCSR1_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR1_GENERATE[28].TCSR1_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR1_GENERATE[29].TCSR1_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR1_GENERATE[29].TCSR1_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR1_GENERATE[29].TCSR1_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR1_GENERATE[30].TCSR1_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR1_GENERATE[30].TCSR1_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR1_GENERATE[30].TCSR1_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR1_GENERATE[31].TCSR1_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR1_GENERATE[31].TCSR1_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR1_GENERATE[31].TCSR1_FF_I\ : label is "1'b0";
attribute SOFT_HLUTNM of captureTrig0_pulse_d1_i_1 : label is "soft_lutpair52";
begin
D_0 <= \^d_0\;
\INFERRED_GEN.icount_out_reg[0]\ <= \^inferred_gen.icount_out_reg[0]\;
Q(1 downto 0) <= \^q\(1 downto 0);
\TCSR0_GENERATE[24].TCSR0_FF_I_0\ <= \^tcsr0_generate[24].tcsr0_ff_i_0\;
\TCSR1_GENERATE[23].TCSR1_FF_I_0\ <= \^tcsr1_generate[23].tcsr1_ff_i_0\;
generateout0 <= \^generateout0\;
generateout1 <= \^generateout1\;
read_done1 <= \^read_done1\;
\GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \LOAD_REG_GEN[21].LOAD_REG_I\(10),
I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\,
I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\,
I3 => read_Mux_In(21),
I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I5 => read_Mux_In(53),
O => \s_axi_rdata_i_reg[10]\
);
\GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \LOAD_REG_GEN[21].LOAD_REG_I\(9),
I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\,
I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\,
I3 => read_Mux_In(22),
I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I5 => read_Mux_In(54),
O => \s_axi_rdata_i_reg[9]\
);
\GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \LOAD_REG_GEN[21].LOAD_REG_I\(8),
I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\,
I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\,
I3 => read_Mux_In(23),
I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I5 => read_Mux_In(55),
O => \s_axi_rdata_i_reg[8]\
);
\GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \LOAD_REG_GEN[21].LOAD_REG_I\(7),
I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\,
I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\,
I3 => \^tcsr0_generate[24].tcsr0_ff_i_0\,
I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I5 => \^tcsr1_generate[23].tcsr1_ff_i_0\,
O => \s_axi_rdata_i_reg[7]\
);
\GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \LOAD_REG_GEN[21].LOAD_REG_I\(6),
I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\,
I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\,
I3 => read_Mux_In(25),
I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I5 => read_Mux_In(57),
O => \s_axi_rdata_i_reg[6]\
);
\GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \LOAD_REG_GEN[21].LOAD_REG_I\(5),
I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\,
I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\,
I3 => read_Mux_In(26),
I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I5 => read_Mux_In(58),
O => \s_axi_rdata_i_reg[5]\
);
\GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \LOAD_REG_GEN[21].LOAD_REG_I\(4),
I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\,
I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\,
I3 => read_Mux_In(27),
I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I5 => read_Mux_In(59),
O => \s_axi_rdata_i_reg[4]\
);
\GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \LOAD_REG_GEN[21].LOAD_REG_I\(3),
I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\,
I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\,
I3 => read_Mux_In(28),
I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I5 => read_Mux_In(60),
O => \s_axi_rdata_i_reg[3]\
);
\GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \LOAD_REG_GEN[21].LOAD_REG_I\(2),
I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\,
I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\,
I3 => read_Mux_In(29),
I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I5 => read_Mux_In(61),
O => \s_axi_rdata_i_reg[2]\
);
\GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \LOAD_REG_GEN[21].LOAD_REG_I\(1),
I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\,
I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\,
I3 => read_Mux_In(30),
I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I5 => read_Mux_In(62),
O => \s_axi_rdata_i_reg[1]\
);
\GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \LOAD_REG_GEN[21].LOAD_REG_I\(0),
I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\,
I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\,
I3 => read_Mux_In(31),
I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I5 => read_Mux_In(63),
O => \s_axi_rdata_i_reg[0]\
);
GenerateOut0_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"B800"
)
port map (
I0 => generateOutPre1,
I1 => \^inferred_gen.icount_out_reg[0]\,
I2 => generateOutPre0,
I3 => read_Mux_In(29),
O => GenerateOut00
);
GenerateOut0_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GenerateOut00,
Q => \^generateout0\,
R => SR(0)
);
GenerateOut1_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"8F808080"
)
port map (
I0 => generateOutPre0,
I1 => read_Mux_In(29),
I2 => \^inferred_gen.icount_out_reg[0]\,
I3 => read_Mux_In(61),
I4 => generateOutPre1,
O => GenerateOut10
);
GenerateOut1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GenerateOut10,
Q => \^generateout1\,
R => SR(0)
);
\INFERRED_GEN.icount_out[31]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAFEAAAA"
)
port map (
I0 => read_Mux_In(26),
I1 => read_Mux_In(22),
I2 => read_Mux_In(27),
I3 => read_Mux_In(31),
I4 => counter_TC(0),
O => Load_Counter_Reg030_out
);
\INFERRED_GEN.icount_out[31]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFAAEAAAAAAAEA"
)
port map (
I0 => read_Mux_In(58),
I1 => counter_TC(1),
I2 => read_Mux_In(59),
I3 => read_Mux_In(63),
I4 => read_Mux_In(54),
I5 => counter_TC(0),
O => \Load_Counter_Reg0__0\
);
\INFERRED_GEN.icount_out[31]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FF40"
)
port map (
I0 => read_Mux_In(31),
I1 => counter_TC(1),
I2 => read_Mux_In(27),
I3 => read_Mux_In(58),
O => Load_Counter_Reg028_out
);
\INFERRED_GEN.icount_out[31]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FF40"
)
port map (
I0 => read_Mux_In(31),
I1 => counter_TC(1),
I2 => read_Mux_In(27),
I3 => read_Mux_In(26),
O => Load_Counter_Reg031_out
);
\INFERRED_GEN.icount_out[31]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF40FFFFFF400000"
)
port map (
I0 => read_Mux_In(31),
I1 => counter_TC(1),
I2 => read_Mux_In(27),
I3 => read_Mux_In(58),
I4 => \^inferred_gen.icount_out_reg[0]\,
I5 => \Load_Counter_Reg0__0\,
O => load_Counter_Reg(1)
);
\INFERRED_GEN.icount_out[31]_i_7__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF40FFFFFF400000"
)
port map (
I0 => read_Mux_In(31),
I1 => counter_TC(1),
I2 => read_Mux_In(27),
I3 => read_Mux_In(26),
I4 => \^inferred_gen.icount_out_reg[0]\,
I5 => Load_Counter_Reg030_out,
O => load_Counter_Reg(0)
);
INPUT_DOUBLE_REGS: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync
port map (
captureTrig0_d0 => captureTrig0_d0,
capturetrig0 => capturetrig0,
read_Mux_In(0) => read_Mux_In(28),
s_axi_aclk => s_axi_aclk
);
INPUT_DOUBLE_REGS2: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_1
port map (
captureTrig1_d0 => captureTrig1_d0,
capturetrig1 => capturetrig1,
read_Mux_In(0) => read_Mux_In(60),
s_axi_aclk => s_axi_aclk
);
INPUT_DOUBLE_REGS3: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_2
port map (
E(0) => E(0),
\INFERRED_GEN.icount_out_reg[0]\(0) => \INFERRED_GEN.icount_out_reg[0]_0\(0),
\INFERRED_GEN.icount_out_reg[1]\(1 downto 0) => \INFERRED_GEN.icount_out_reg[1]\(1 downto 0),
\INFERRED_GEN.icount_out_reg[4]\(0) => \INFERRED_GEN.icount_out_reg[4]\(0),
Load_Counter_Reg028_out => Load_Counter_Reg028_out,
Load_Counter_Reg030_out => Load_Counter_Reg030_out,
Load_Counter_Reg031_out => Load_Counter_Reg031_out,
\Load_Counter_Reg0__0\ => \Load_Counter_Reg0__0\,
S(0) => S(0),
\TCSR0_GENERATE[20].TCSR0_FF_I\ => \^inferred_gen.icount_out_reg[0]\,
\TCSR0_GENERATE[24].TCSR0_FF_I\ => \^tcsr0_generate[24].tcsr0_ff_i_0\,
\TCSR1_GENERATE[24].TCSR1_FF_I\ => \^tcsr1_generate[23].tcsr1_ff_i_0\,
counter_TC(0 to 1) => counter_TC(0 to 1),
freeze => freeze,
generateOutPre0 => generateOutPre0,
read_Mux_In(7) => read_Mux_In(22),
read_Mux_In(6) => read_Mux_In(27),
read_Mux_In(5) => read_Mux_In(30),
read_Mux_In(4) => read_Mux_In(31),
read_Mux_In(3) => read_Mux_In(54),
read_Mux_In(2) => read_Mux_In(59),
read_Mux_In(1) => read_Mux_In(62),
read_Mux_In(0) => read_Mux_In(63),
s_axi_aclk => s_axi_aclk
);
Interrupt_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => read_Mux_In(25),
I1 => read_Mux_In(23),
I2 => read_Mux_In(57),
I3 => read_Mux_In(55),
O => Interrupt0
);
Interrupt_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Interrupt0,
Q => interrupt,
R => SR(0)
);
\LOAD_REG_GEN[0].LOAD_REG_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"E000FFFFE000E000"
)
port map (
I0 => read_Mux_In(27),
I1 => \^d_0\,
I2 => R_0,
I3 => read_Mux_In(31),
I4 => Bus_RNW_reg,
I5 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
O => \LOAD_REG_GEN[24].LOAD_REG_I\
);
\LOAD_REG_GEN[0].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFF8080808"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_i_3_n_0\,
I1 => p_38_in,
I2 => \^inferred_gen.icount_out_reg[0]\,
I3 => \LOAD_REG_GEN[0].LOAD_REG_I_i_5_n_0\,
I4 => p_33_in,
I5 => \bus2ip_wrce__0\(0),
O => \LOAD_REG_GEN[24].LOAD_REG_I_0\
);
\LOAD_REG_GEN[0].LOAD_REG_I_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => read_Mux_In(59),
I1 => \^read_done1\,
O => \LOAD_REG_GEN[0].LOAD_REG_I_i_3_n_0\
);
\LOAD_REG_GEN[0].LOAD_REG_I_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4F4F40400000000"
)
port map (
I0 => captureTrig1_d2,
I1 => captureTrig1_d,
I2 => \^inferred_gen.icount_out_reg[0]\,
I3 => READ_DONE1_I_i_3_n_0,
I4 => READ_DONE0_I_i_3_n_0,
I5 => read_Mux_In(63),
O => p_38_in
);
\LOAD_REG_GEN[0].LOAD_REG_I_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => read_Mux_In(27),
I1 => \^read_done1\,
O => \LOAD_REG_GEN[0].LOAD_REG_I_i_5_n_0\
);
\LOAD_REG_GEN[0].LOAD_REG_I_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4F4F40400000000"
)
port map (
I0 => captureTrig1_d2,
I1 => captureTrig1_d,
I2 => \^inferred_gen.icount_out_reg[0]\,
I3 => READ_DONE1_I_i_3_n_0,
I4 => READ_DONE0_I_i_3_n_0,
I5 => read_Mux_In(31),
O => p_33_in
);
PWM_FF_I_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"AB"
)
port map (
I0 => \^generateout1\,
I1 => read_Mux_In(22),
I2 => read_Mux_In(54),
O => R
);
PWM_FF_I_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^generateout0\,
I1 => pwm0,
O => PWM_FF_I
);
READ_DONE0_I: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\,
Q => \^d_0\,
R => R_0
);
READ_DONE0_I_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"AA00AA00ABFFAA00"
)
port map (
I0 => READ_DONE0_I_i_3_n_0,
I1 => \^q\(1),
I2 => counter_TC(0),
I3 => \^inferred_gen.icount_out_reg[0]\,
I4 => captureTrig0_d,
I5 => captureTrig0_d2,
O => R_0
);
READ_DONE0_I_i_3: unisim.vcomponents.LUT3
generic map(
INIT => X"A8"
)
port map (
I0 => counter_TC_Reg2,
I1 => captureTrig0_pulse_d2,
I2 => captureTrig0_pulse_d1,
O => READ_DONE0_I_i_3_n_0
);
READ_DONE1_I: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
Q => \^read_done1\,
R => READ_DONE1_I_i_1_n_0
);
READ_DONE1_I_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"E0E0EFE0"
)
port map (
I0 => READ_DONE0_I_i_3_n_0,
I1 => READ_DONE1_I_i_3_n_0,
I2 => \^inferred_gen.icount_out_reg[0]\,
I3 => captureTrig1_d,
I4 => captureTrig1_d2,
O => READ_DONE1_I_i_1_n_0
);
READ_DONE1_I_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"0004"
)
port map (
I0 => captureTrig0_d2,
I1 => captureTrig0_d,
I2 => counter_TC(0),
I3 => \^q\(1),
O => READ_DONE1_I_i_3_n_0
);
\TCSR0_GENERATE[20].TCSR0_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(1),
D => s_axi_wdata(9),
Q => \^inferred_gen.icount_out_reg[0]\,
R => SR(0)
);
\TCSR0_GENERATE[21].TCSR0_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => pair0_Select,
D => s_axi_wdata(8),
Q => read_Mux_In(21),
R => SR(0)
);
\TCSR0_GENERATE[22].TCSR0_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(1),
D => s_axi_wdata(7),
Q => read_Mux_In(22),
R => SR(0)
);
\TCSR0_GENERATE[23].TCSR0_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \TCSR0_GENERATE[23].TCSR0_FF_I_i_2_n_0\,
Q => read_Mux_In(23),
R => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\
);
\TCSR0_GENERATE[23].TCSR0_FF_I_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFF3F2F0F2"
)
port map (
I0 => generateOutPre0,
I1 => read_Mux_In(31),
I2 => \TCSR0_Set2__0\,
I3 => \^inferred_gen.icount_out_reg[0]\,
I4 => generateOutPre1,
I5 => read_Mux_In(23),
O => \TCSR0_GENERATE[23].TCSR0_FF_I_i_2_n_0\
);
\TCSR0_GENERATE[23].TCSR0_FF_I_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"A8AAA80000000000"
)
port map (
I0 => read_Mux_In(31),
I1 => READ_DONE0_I_i_3_n_0,
I2 => READ_DONE1_I_i_3_n_0,
I3 => \^inferred_gen.icount_out_reg[0]\,
I4 => captureTrig0_pulse_d1_i_1_n_0,
I5 => \^tcsr0_generate[24].tcsr0_ff_i_0\,
O => \TCSR0_Set2__0\
);
\TCSR0_GENERATE[24].TCSR0_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => pair0_Select,
D => \TCSR0_GENERATE[24].TCSR0_FF_I_1\,
Q => \^tcsr0_generate[24].tcsr0_ff_i_0\,
R => SR(0)
);
\TCSR0_GENERATE[25].TCSR0_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(1),
D => s_axi_wdata(6),
Q => read_Mux_In(25),
R => SR(0)
);
\TCSR0_GENERATE[26].TCSR0_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(1),
D => s_axi_wdata(5),
Q => read_Mux_In(26),
R => SR(0)
);
\TCSR0_GENERATE[27].TCSR0_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(1),
D => s_axi_wdata(4),
Q => read_Mux_In(27),
R => SR(0)
);
\TCSR0_GENERATE[28].TCSR0_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(1),
D => s_axi_wdata(3),
Q => read_Mux_In(28),
R => SR(0)
);
\TCSR0_GENERATE[29].TCSR0_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(1),
D => s_axi_wdata(2),
Q => read_Mux_In(29),
R => SR(0)
);
\TCSR0_GENERATE[30].TCSR0_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(1),
D => s_axi_wdata(1),
Q => read_Mux_In(30),
R => SR(0)
);
\TCSR0_GENERATE[31].TCSR0_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(1),
D => s_axi_wdata(0),
Q => read_Mux_In(31),
R => SR(0)
);
\TCSR1_GENERATE[21].TCSR1_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => pair0_Select,
D => s_axi_wdata(8),
Q => read_Mux_In(53),
R => SR(0)
);
\TCSR1_GENERATE[22].TCSR1_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(0),
D => s_axi_wdata(7),
Q => read_Mux_In(54),
R => SR(0)
);
\TCSR1_GENERATE[23].TCSR1_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \TCSR1_GENERATE[23].TCSR1_FF_I_i_2_n_0\,
Q => read_Mux_In(55),
R => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\
);
\TCSR1_GENERATE[23].TCSR1_FF_I_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00008F80"
)
port map (
I0 => \^tcsr1_generate[23].tcsr1_ff_i_0\,
I1 => READ_DONE1_I_i_1_n_0,
I2 => read_Mux_In(63),
I3 => generateOutPre1,
I4 => \^inferred_gen.icount_out_reg[0]\,
I5 => read_Mux_In(55),
O => \TCSR1_GENERATE[23].TCSR1_FF_I_i_2_n_0\
);
\TCSR1_GENERATE[24].TCSR1_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => pair0_Select,
D => \TCSR1_GENERATE[24].TCSR1_FF_I_0\,
Q => \^tcsr1_generate[23].tcsr1_ff_i_0\,
R => SR(0)
);
\TCSR1_GENERATE[25].TCSR1_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(0),
D => s_axi_wdata(6),
Q => read_Mux_In(57),
R => SR(0)
);
\TCSR1_GENERATE[26].TCSR1_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(0),
D => s_axi_wdata(5),
Q => read_Mux_In(58),
R => SR(0)
);
\TCSR1_GENERATE[27].TCSR1_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(0),
D => s_axi_wdata(4),
Q => read_Mux_In(59),
R => SR(0)
);
\TCSR1_GENERATE[28].TCSR1_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(0),
D => s_axi_wdata(3),
Q => read_Mux_In(60),
R => SR(0)
);
\TCSR1_GENERATE[29].TCSR1_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(0),
D => s_axi_wdata(2),
Q => read_Mux_In(61),
R => SR(0)
);
\TCSR1_GENERATE[30].TCSR1_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(0),
D => s_axi_wdata(1),
Q => read_Mux_In(62),
R => SR(0)
);
\TCSR1_GENERATE[31].TCSR1_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(0),
D => s_axi_wdata(0),
Q => read_Mux_In(63),
R => SR(0)
);
captureTrig0_d2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => captureTrig0_d,
Q => captureTrig0_d2,
R => SR(0)
);
captureTrig0_d_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => captureTrig0_d0,
Q => captureTrig0_d,
R => SR(0)
);
captureTrig0_pulse_d1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => captureTrig0_d,
I1 => captureTrig0_d2,
O => captureTrig0_pulse_d1_i_1_n_0
);
captureTrig0_pulse_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => captureTrig0_pulse_d1_i_1_n_0,
Q => captureTrig0_pulse_d1,
R => SR(0)
);
captureTrig0_pulse_d2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => captureTrig0_pulse_d1,
Q => captureTrig0_pulse_d2,
R => SR(0)
);
captureTrig1_d2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => captureTrig1_d,
Q => captureTrig1_d2,
R => SR(0)
);
captureTrig1_d_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => captureTrig1_d0,
Q => captureTrig1_d,
R => SR(0)
);
counter_TC_Reg2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^q\(1),
Q => counter_TC_Reg2,
R => SR(0)
);
\counter_TC_Reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => counter_TC(0),
Q => \^q\(1),
R => SR(0)
);
\counter_TC_Reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => counter_TC(1),
Q => \^q\(0),
R => SR(0)
);
generateOutPre0_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \INFERRED_GEN.icount_out_reg[32]_0\,
Q => generateOutPre0,
R => SR(0)
);
generateOutPre1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \INFERRED_GEN.icount_out_reg[32]\,
Q => generateOutPre1,
R => SR(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment is
port (
\LOAD_REG_GEN[31].LOAD_REG_I\ : out STD_LOGIC;
\TCSR0_GENERATE[23].TCSR0_FF_I\ : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
\s_axi_rdata_i_reg[12]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[13]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[14]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[15]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[16]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[17]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[18]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[19]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[20]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[21]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[22]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[23]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[24]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[25]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[26]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[27]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[28]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[29]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[30]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[31]_0\ : out STD_LOGIC;
pair0_Select : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
\s_axi_rdata_i_reg[11]_0\ : out STD_LOGIC;
\TCSR0_GENERATE[24].TCSR0_FF_I\ : out STD_LOGIC;
\TCSR1_GENERATE[24].TCSR1_FF_I\ : out STD_LOGIC;
\LOAD_REG_GEN[31].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[30].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[29].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[28].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[27].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[26].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[25].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[24].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[23].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[22].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[21].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[20].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[19].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[18].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[17].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[16].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[15].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[14].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[13].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[12].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[11].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[10].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[9].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[8].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[7].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[6].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[5].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[4].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[3].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[2].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[1].LOAD_REG_I\ : out STD_LOGIC;
D_0 : out STD_LOGIC;
\bus2ip_wrce__0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_wrce : out STD_LOGIC_VECTOR ( 1 downto 0 );
\LOAD_REG_GEN[31].LOAD_REG_I_1\ : out STD_LOGIC;
\LOAD_REG_GEN[30].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[29].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[28].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[27].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[26].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[25].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[24].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[23].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[22].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[21].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[20].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[19].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[18].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[17].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[16].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[15].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[14].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[13].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[12].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[11].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[10].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[9].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[8].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[7].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[6].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[5].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[4].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[3].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[2].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[1].LOAD_REG_I_0\ : out STD_LOGIC;
D_1 : out STD_LOGIC;
s_axi_rvalid_i_reg_0 : out STD_LOGIC;
s_axi_rvalid_i_reg_1 : out STD_LOGIC;
s_axi_rvalid_i_reg_2 : out STD_LOGIC;
\TCSR0_GENERATE[23].TCSR0_FF_I_0\ : out STD_LOGIC;
\TCSR1_GENERATE[23].TCSR1_FF_I\ : out STD_LOGIC;
\s_axi_rdata_i_reg[10]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[0]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[0]_1\ : out STD_LOGIC;
READ_DONE0_I : out STD_LOGIC;
READ_DONE1_I : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
bus2ip_reset : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
read_Mux_In : in STD_LOGIC_VECTOR ( 87 downto 0 );
s_axi_aresetn : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
D_2 : in STD_LOGIC;
read_done1 : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment is
signal \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal I_DECODER_n_100 : STD_LOGIC;
signal I_DECODER_n_101 : STD_LOGIC;
signal I_DECODER_n_25 : STD_LOGIC;
signal I_DECODER_n_26 : STD_LOGIC;
signal bus2ip_addr : STD_LOGIC_VECTOR ( 0 to 2 );
signal \bus2ip_addr_i[2]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[3]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[4]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[4]_i_2_n_0\ : STD_LOGIC;
signal bus2ip_rnw_i : STD_LOGIC;
signal bus2ip_rnw_i06_out : STD_LOGIC;
signal clear : STD_LOGIC;
signal is_read : STD_LOGIC;
signal is_read_i_1_n_0 : STD_LOGIC;
signal is_write : STD_LOGIC;
signal is_write_i_1_n_0 : STD_LOGIC;
signal is_write_reg_n_0 : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 5 downto 0 );
signal rst : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal \s_axi_rdata_i[31]_i_1_n_0\ : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
signal start2 : STD_LOGIC;
signal start2_i_1_n_0 : STD_LOGIC;
signal state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \state1__2\ : STD_LOGIC;
signal \state[1]_i_3_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[4]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \bus2ip_addr_i[4]_i_2\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of bus2ip_rnw_i_i_1 : label is "soft_lutpair14";
attribute SOFT_HLUTNM of start2_i_1 : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \state[1]_i_3\ : label is "soft_lutpair16";
begin
s_axi_bvalid <= \^s_axi_bvalid\;
s_axi_rvalid <= \^s_axi_rvalid\;
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
O => plusOp(0)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
O => plusOp(1)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
O => plusOp(2)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
O => plusOp(3)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(4),
O => plusOp(4)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => state(0),
I1 => state(1),
O => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(4),
I5 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(5),
O => plusOp(5)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(0),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(1),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(2),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(3),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(4),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(4),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(5),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(5),
R => clear
);
I_DECODER: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder
port map (
D(1) => I_DECODER_n_25,
D(0) => I_DECODER_n_26,
D_0 => D_0,
D_1 => D_1,
D_2 => D_2,
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(5 downto 0) => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(5 downto 0),
\LOAD_REG_GEN[10].LOAD_REG_I\ => \LOAD_REG_GEN[10].LOAD_REG_I\,
\LOAD_REG_GEN[10].LOAD_REG_I_0\ => \LOAD_REG_GEN[10].LOAD_REG_I_0\,
\LOAD_REG_GEN[11].LOAD_REG_I\ => \LOAD_REG_GEN[11].LOAD_REG_I\,
\LOAD_REG_GEN[11].LOAD_REG_I_0\ => \LOAD_REG_GEN[11].LOAD_REG_I_0\,
\LOAD_REG_GEN[12].LOAD_REG_I\ => \LOAD_REG_GEN[12].LOAD_REG_I\,
\LOAD_REG_GEN[12].LOAD_REG_I_0\ => \LOAD_REG_GEN[12].LOAD_REG_I_0\,
\LOAD_REG_GEN[13].LOAD_REG_I\ => \LOAD_REG_GEN[13].LOAD_REG_I\,
\LOAD_REG_GEN[13].LOAD_REG_I_0\ => \LOAD_REG_GEN[13].LOAD_REG_I_0\,
\LOAD_REG_GEN[14].LOAD_REG_I\ => \LOAD_REG_GEN[14].LOAD_REG_I\,
\LOAD_REG_GEN[14].LOAD_REG_I_0\ => \LOAD_REG_GEN[14].LOAD_REG_I_0\,
\LOAD_REG_GEN[15].LOAD_REG_I\ => \LOAD_REG_GEN[15].LOAD_REG_I\,
\LOAD_REG_GEN[15].LOAD_REG_I_0\ => \LOAD_REG_GEN[15].LOAD_REG_I_0\,
\LOAD_REG_GEN[16].LOAD_REG_I\ => \LOAD_REG_GEN[16].LOAD_REG_I\,
\LOAD_REG_GEN[16].LOAD_REG_I_0\ => \LOAD_REG_GEN[16].LOAD_REG_I_0\,
\LOAD_REG_GEN[17].LOAD_REG_I\ => \LOAD_REG_GEN[17].LOAD_REG_I\,
\LOAD_REG_GEN[17].LOAD_REG_I_0\ => \LOAD_REG_GEN[17].LOAD_REG_I_0\,
\LOAD_REG_GEN[18].LOAD_REG_I\ => \LOAD_REG_GEN[18].LOAD_REG_I\,
\LOAD_REG_GEN[18].LOAD_REG_I_0\ => \LOAD_REG_GEN[18].LOAD_REG_I_0\,
\LOAD_REG_GEN[19].LOAD_REG_I\ => \LOAD_REG_GEN[19].LOAD_REG_I\,
\LOAD_REG_GEN[19].LOAD_REG_I_0\ => \LOAD_REG_GEN[19].LOAD_REG_I_0\,
\LOAD_REG_GEN[1].LOAD_REG_I\ => \LOAD_REG_GEN[1].LOAD_REG_I\,
\LOAD_REG_GEN[1].LOAD_REG_I_0\ => \LOAD_REG_GEN[1].LOAD_REG_I_0\,
\LOAD_REG_GEN[20].LOAD_REG_I\ => \LOAD_REG_GEN[20].LOAD_REG_I\,
\LOAD_REG_GEN[20].LOAD_REG_I_0\ => \LOAD_REG_GEN[20].LOAD_REG_I_0\,
\LOAD_REG_GEN[21].LOAD_REG_I\ => \LOAD_REG_GEN[21].LOAD_REG_I\,
\LOAD_REG_GEN[21].LOAD_REG_I_0\ => \LOAD_REG_GEN[21].LOAD_REG_I_0\,
\LOAD_REG_GEN[22].LOAD_REG_I\ => \LOAD_REG_GEN[22].LOAD_REG_I\,
\LOAD_REG_GEN[22].LOAD_REG_I_0\ => \LOAD_REG_GEN[22].LOAD_REG_I_0\,
\LOAD_REG_GEN[23].LOAD_REG_I\ => \LOAD_REG_GEN[23].LOAD_REG_I\,
\LOAD_REG_GEN[23].LOAD_REG_I_0\ => \LOAD_REG_GEN[23].LOAD_REG_I_0\,
\LOAD_REG_GEN[24].LOAD_REG_I\ => \LOAD_REG_GEN[24].LOAD_REG_I\,
\LOAD_REG_GEN[24].LOAD_REG_I_0\ => \LOAD_REG_GEN[24].LOAD_REG_I_0\,
\LOAD_REG_GEN[25].LOAD_REG_I\ => \LOAD_REG_GEN[25].LOAD_REG_I\,
\LOAD_REG_GEN[25].LOAD_REG_I_0\ => \LOAD_REG_GEN[25].LOAD_REG_I_0\,
\LOAD_REG_GEN[26].LOAD_REG_I\ => \LOAD_REG_GEN[26].LOAD_REG_I\,
\LOAD_REG_GEN[26].LOAD_REG_I_0\ => \LOAD_REG_GEN[26].LOAD_REG_I_0\,
\LOAD_REG_GEN[27].LOAD_REG_I\ => \LOAD_REG_GEN[27].LOAD_REG_I\,
\LOAD_REG_GEN[27].LOAD_REG_I_0\ => \LOAD_REG_GEN[27].LOAD_REG_I_0\,
\LOAD_REG_GEN[28].LOAD_REG_I\ => \LOAD_REG_GEN[28].LOAD_REG_I\,
\LOAD_REG_GEN[28].LOAD_REG_I_0\ => \LOAD_REG_GEN[28].LOAD_REG_I_0\,
\LOAD_REG_GEN[29].LOAD_REG_I\ => \LOAD_REG_GEN[29].LOAD_REG_I\,
\LOAD_REG_GEN[29].LOAD_REG_I_0\ => \LOAD_REG_GEN[29].LOAD_REG_I_0\,
\LOAD_REG_GEN[2].LOAD_REG_I\ => \LOAD_REG_GEN[2].LOAD_REG_I\,
\LOAD_REG_GEN[2].LOAD_REG_I_0\ => \LOAD_REG_GEN[2].LOAD_REG_I_0\,
\LOAD_REG_GEN[30].LOAD_REG_I\ => \LOAD_REG_GEN[30].LOAD_REG_I\,
\LOAD_REG_GEN[30].LOAD_REG_I_0\ => \LOAD_REG_GEN[30].LOAD_REG_I_0\,
\LOAD_REG_GEN[31].LOAD_REG_I\ => \LOAD_REG_GEN[31].LOAD_REG_I\,
\LOAD_REG_GEN[31].LOAD_REG_I_0\ => \LOAD_REG_GEN[31].LOAD_REG_I_0\,
\LOAD_REG_GEN[31].LOAD_REG_I_1\ => \LOAD_REG_GEN[31].LOAD_REG_I_1\,
\LOAD_REG_GEN[3].LOAD_REG_I\ => \LOAD_REG_GEN[3].LOAD_REG_I\,
\LOAD_REG_GEN[3].LOAD_REG_I_0\ => \LOAD_REG_GEN[3].LOAD_REG_I_0\,
\LOAD_REG_GEN[4].LOAD_REG_I\ => \LOAD_REG_GEN[4].LOAD_REG_I\,
\LOAD_REG_GEN[4].LOAD_REG_I_0\ => \LOAD_REG_GEN[4].LOAD_REG_I_0\,
\LOAD_REG_GEN[5].LOAD_REG_I\ => \LOAD_REG_GEN[5].LOAD_REG_I\,
\LOAD_REG_GEN[5].LOAD_REG_I_0\ => \LOAD_REG_GEN[5].LOAD_REG_I_0\,
\LOAD_REG_GEN[6].LOAD_REG_I\ => \LOAD_REG_GEN[6].LOAD_REG_I\,
\LOAD_REG_GEN[6].LOAD_REG_I_0\ => \LOAD_REG_GEN[6].LOAD_REG_I_0\,
\LOAD_REG_GEN[7].LOAD_REG_I\ => \LOAD_REG_GEN[7].LOAD_REG_I\,
\LOAD_REG_GEN[7].LOAD_REG_I_0\ => \LOAD_REG_GEN[7].LOAD_REG_I_0\,
\LOAD_REG_GEN[8].LOAD_REG_I\ => \LOAD_REG_GEN[8].LOAD_REG_I\,
\LOAD_REG_GEN[8].LOAD_REG_I_0\ => \LOAD_REG_GEN[8].LOAD_REG_I_0\,
\LOAD_REG_GEN[9].LOAD_REG_I\ => \LOAD_REG_GEN[9].LOAD_REG_I\,
\LOAD_REG_GEN[9].LOAD_REG_I_0\ => \LOAD_REG_GEN[9].LOAD_REG_I_0\,
Q => start2,
READ_DONE0_I => READ_DONE0_I,
READ_DONE1_I => READ_DONE1_I,
\TCSR0_GENERATE[23].TCSR0_FF_I\ => \TCSR0_GENERATE[23].TCSR0_FF_I\,
\TCSR0_GENERATE[23].TCSR0_FF_I_0\ => \TCSR0_GENERATE[23].TCSR0_FF_I_0\,
\TCSR0_GENERATE[24].TCSR0_FF_I\ => \TCSR0_GENERATE[24].TCSR0_FF_I\,
\TCSR1_GENERATE[23].TCSR1_FF_I\ => \TCSR1_GENERATE[23].TCSR1_FF_I\,
\TCSR1_GENERATE[24].TCSR1_FF_I\ => \TCSR1_GENERATE[24].TCSR1_FF_I\,
\bus2ip_addr_i_reg[4]\(2) => bus2ip_addr(0),
\bus2ip_addr_i_reg[4]\(1) => bus2ip_addr(1),
\bus2ip_addr_i_reg[4]\(0) => bus2ip_addr(2),
bus2ip_rnw_i => bus2ip_rnw_i,
bus2ip_wrce(1 downto 0) => bus2ip_wrce(1 downto 0),
\bus2ip_wrce__0\(0) => \bus2ip_wrce__0\(0),
is_read => is_read,
is_write_reg => is_write_reg_n_0,
pair0_Select => pair0_Select,
read_Mux_In(87 downto 0) => read_Mux_In(87 downto 0),
read_done1 => read_done1,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_arvalid_0 => \state[1]_i_3_n_0\,
s_axi_bready => s_axi_bready,
s_axi_bvalid_i_reg => I_DECODER_n_101,
s_axi_bvalid_i_reg_0 => \^s_axi_bvalid\,
\s_axi_rdata_i_reg[0]\ => \s_axi_rdata_i_reg[0]_0\,
\s_axi_rdata_i_reg[0]_0\ => \s_axi_rdata_i_reg[0]_1\,
\s_axi_rdata_i_reg[10]\ => \s_axi_rdata_i_reg[10]_0\,
\s_axi_rdata_i_reg[11]\ => \s_axi_rdata_i_reg[11]_0\,
\s_axi_rdata_i_reg[12]\ => \s_axi_rdata_i_reg[12]_0\,
\s_axi_rdata_i_reg[13]\ => \s_axi_rdata_i_reg[13]_0\,
\s_axi_rdata_i_reg[14]\ => \s_axi_rdata_i_reg[14]_0\,
\s_axi_rdata_i_reg[15]\ => \s_axi_rdata_i_reg[15]_0\,
\s_axi_rdata_i_reg[16]\ => \s_axi_rdata_i_reg[16]_0\,
\s_axi_rdata_i_reg[17]\ => \s_axi_rdata_i_reg[17]_0\,
\s_axi_rdata_i_reg[18]\ => \s_axi_rdata_i_reg[18]_0\,
\s_axi_rdata_i_reg[19]\ => \s_axi_rdata_i_reg[19]_0\,
\s_axi_rdata_i_reg[20]\ => \s_axi_rdata_i_reg[20]_0\,
\s_axi_rdata_i_reg[21]\ => \s_axi_rdata_i_reg[21]_0\,
\s_axi_rdata_i_reg[22]\ => \s_axi_rdata_i_reg[22]_0\,
\s_axi_rdata_i_reg[23]\ => \s_axi_rdata_i_reg[23]_0\,
\s_axi_rdata_i_reg[24]\ => \s_axi_rdata_i_reg[24]_0\,
\s_axi_rdata_i_reg[25]\ => \s_axi_rdata_i_reg[25]_0\,
\s_axi_rdata_i_reg[26]\ => \s_axi_rdata_i_reg[26]_0\,
\s_axi_rdata_i_reg[27]\ => \s_axi_rdata_i_reg[27]_0\,
\s_axi_rdata_i_reg[28]\ => \s_axi_rdata_i_reg[28]_0\,
\s_axi_rdata_i_reg[29]\ => \s_axi_rdata_i_reg[29]_0\,
\s_axi_rdata_i_reg[30]\ => \s_axi_rdata_i_reg[30]_0\,
\s_axi_rdata_i_reg[31]\ => \s_axi_rdata_i_reg[31]_0\,
s_axi_rready => s_axi_rready,
s_axi_rvalid_i_reg => s_axi_rvalid_i_reg_0,
s_axi_rvalid_i_reg_0 => s_axi_rvalid_i_reg_1,
s_axi_rvalid_i_reg_1 => s_axi_rvalid_i_reg_2,
s_axi_rvalid_i_reg_2 => I_DECODER_n_100,
s_axi_rvalid_i_reg_3 => \^s_axi_rvalid\,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wready => s_axi_wready,
\state1__2\ => \state1__2\,
\state_reg[1]\(1 downto 0) => state(1 downto 0)
);
\bus2ip_addr_i[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEFF0200"
)
port map (
I0 => s_axi_araddr(0),
I1 => state(0),
I2 => state(1),
I3 => s_axi_arvalid,
I4 => s_axi_awaddr(0),
O => \bus2ip_addr_i[2]_i_1_n_0\
);
\bus2ip_addr_i[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEFF0200"
)
port map (
I0 => s_axi_araddr(1),
I1 => state(0),
I2 => state(1),
I3 => s_axi_arvalid,
I4 => s_axi_awaddr(1),
O => \bus2ip_addr_i[3]_i_1_n_0\
);
\bus2ip_addr_i[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000000EA"
)
port map (
I0 => s_axi_arvalid,
I1 => s_axi_awvalid,
I2 => s_axi_wvalid,
I3 => state(1),
I4 => state(0),
O => \bus2ip_addr_i[4]_i_1_n_0\
);
\bus2ip_addr_i[4]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEFF0200"
)
port map (
I0 => s_axi_araddr(2),
I1 => state(0),
I2 => state(1),
I3 => s_axi_arvalid,
I4 => s_axi_awaddr(2),
O => \bus2ip_addr_i[4]_i_2_n_0\
);
\bus2ip_addr_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[4]_i_1_n_0\,
D => \bus2ip_addr_i[2]_i_1_n_0\,
Q => bus2ip_addr(2),
R => rst
);
\bus2ip_addr_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[4]_i_1_n_0\,
D => \bus2ip_addr_i[3]_i_1_n_0\,
Q => bus2ip_addr(1),
R => rst
);
\bus2ip_addr_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[4]_i_1_n_0\,
D => \bus2ip_addr_i[4]_i_2_n_0\,
Q => bus2ip_addr(0),
R => rst
);
bus2ip_rnw_i_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"10"
)
port map (
I0 => state(0),
I1 => state(1),
I2 => s_axi_arvalid,
O => bus2ip_rnw_i06_out
);
bus2ip_rnw_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[4]_i_1_n_0\,
D => bus2ip_rnw_i06_out,
Q => bus2ip_rnw_i,
R => rst
);
is_read_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"3FFA000A"
)
port map (
I0 => s_axi_arvalid,
I1 => \state1__2\,
I2 => state(0),
I3 => state(1),
I4 => is_read,
O => is_read_i_1_n_0
);
is_read_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_read_i_1_n_0,
Q => is_read,
R => rst
);
is_write_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0040FFFF00400000"
)
port map (
I0 => s_axi_arvalid,
I1 => s_axi_awvalid,
I2 => s_axi_wvalid,
I3 => state(1),
I4 => is_write,
I5 => is_write_reg_n_0,
O => is_write_i_1_n_0
);
is_write_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"F88800000000FFFF"
)
port map (
I0 => \^s_axi_rvalid\,
I1 => s_axi_rready,
I2 => \^s_axi_bvalid\,
I3 => s_axi_bready,
I4 => state(0),
I5 => state(1),
O => is_write
);
is_write_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_write_i_1_n_0,
Q => is_write_reg_n_0,
R => rst
);
rst_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => bus2ip_reset,
Q => rst,
R => '0'
);
s_axi_bvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => I_DECODER_n_101,
Q => \^s_axi_bvalid\,
R => rst
);
\s_axi_rdata_i[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => state(0),
I1 => state(1),
O => \s_axi_rdata_i[31]_i_1_n_0\
);
\s_axi_rdata_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(0),
Q => s_axi_rdata(0),
R => rst
);
\s_axi_rdata_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(10),
Q => s_axi_rdata(10),
R => rst
);
\s_axi_rdata_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(11),
Q => s_axi_rdata(11),
R => rst
);
\s_axi_rdata_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(12),
Q => s_axi_rdata(12),
R => rst
);
\s_axi_rdata_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(13),
Q => s_axi_rdata(13),
R => rst
);
\s_axi_rdata_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(14),
Q => s_axi_rdata(14),
R => rst
);
\s_axi_rdata_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(15),
Q => s_axi_rdata(15),
R => rst
);
\s_axi_rdata_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(16),
Q => s_axi_rdata(16),
R => rst
);
\s_axi_rdata_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(17),
Q => s_axi_rdata(17),
R => rst
);
\s_axi_rdata_i_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(18),
Q => s_axi_rdata(18),
R => rst
);
\s_axi_rdata_i_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(19),
Q => s_axi_rdata(19),
R => rst
);
\s_axi_rdata_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(1),
Q => s_axi_rdata(1),
R => rst
);
\s_axi_rdata_i_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(20),
Q => s_axi_rdata(20),
R => rst
);
\s_axi_rdata_i_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(21),
Q => s_axi_rdata(21),
R => rst
);
\s_axi_rdata_i_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(22),
Q => s_axi_rdata(22),
R => rst
);
\s_axi_rdata_i_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(23),
Q => s_axi_rdata(23),
R => rst
);
\s_axi_rdata_i_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(24),
Q => s_axi_rdata(24),
R => rst
);
\s_axi_rdata_i_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(25),
Q => s_axi_rdata(25),
R => rst
);
\s_axi_rdata_i_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(26),
Q => s_axi_rdata(26),
R => rst
);
\s_axi_rdata_i_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(27),
Q => s_axi_rdata(27),
R => rst
);
\s_axi_rdata_i_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(28),
Q => s_axi_rdata(28),
R => rst
);
\s_axi_rdata_i_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(29),
Q => s_axi_rdata(29),
R => rst
);
\s_axi_rdata_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(2),
Q => s_axi_rdata(2),
R => rst
);
\s_axi_rdata_i_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(30),
Q => s_axi_rdata(30),
R => rst
);
\s_axi_rdata_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(31),
Q => s_axi_rdata(31),
R => rst
);
\s_axi_rdata_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(3),
Q => s_axi_rdata(3),
R => rst
);
\s_axi_rdata_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(4),
Q => s_axi_rdata(4),
R => rst
);
\s_axi_rdata_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(5),
Q => s_axi_rdata(5),
R => rst
);
\s_axi_rdata_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(6),
Q => s_axi_rdata(6),
R => rst
);
\s_axi_rdata_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(7),
Q => s_axi_rdata(7),
R => rst
);
\s_axi_rdata_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(8),
Q => s_axi_rdata(8),
R => rst
);
\s_axi_rdata_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(9),
Q => s_axi_rdata(9),
R => rst
);
s_axi_rvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => I_DECODER_n_100,
Q => \^s_axi_rvalid\,
R => rst
);
start2_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"000000F8"
)
port map (
I0 => s_axi_awvalid,
I1 => s_axi_wvalid,
I2 => s_axi_arvalid,
I3 => state(1),
I4 => state(0),
O => start2_i_1_n_0
);
start2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => start2_i_1_n_0,
Q => start2,
R => rst
);
\state[1]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
O => \state1__2\
);
\state[1]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => s_axi_wvalid,
I1 => s_axi_awvalid,
I2 => s_axi_arvalid,
O => \state[1]_i_3_n_0\
);
\state_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => I_DECODER_n_26,
Q => state(0),
R => rst
);
\state_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => I_DECODER_n_25,
Q => state(1),
R => rst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_tc_core is
port (
D : out STD_LOGIC_VECTOR ( 31 downto 0 );
\INFERRED_GEN.icount_out_reg[0]\ : out STD_LOGIC_VECTOR ( 87 downto 0 );
bus2ip_reset : out STD_LOGIC;
generateout0 : out STD_LOGIC;
generateout1 : out STD_LOGIC;
interrupt : out STD_LOGIC;
D_0 : out STD_LOGIC;
read_done1 : out STD_LOGIC;
pwm0 : out STD_LOGIC;
Bus_RNW_reg_reg : in STD_LOGIC;
Bus_RNW_reg_reg_0 : in STD_LOGIC;
Bus_RNW_reg_reg_1 : in STD_LOGIC;
Bus_RNW_reg_reg_2 : in STD_LOGIC;
Bus_RNW_reg_reg_3 : in STD_LOGIC;
Bus_RNW_reg_reg_4 : in STD_LOGIC;
Bus_RNW_reg_reg_5 : in STD_LOGIC;
Bus_RNW_reg_reg_6 : in STD_LOGIC;
Bus_RNW_reg_reg_7 : in STD_LOGIC;
Bus_RNW_reg_reg_8 : in STD_LOGIC;
Bus_RNW_reg_reg_9 : in STD_LOGIC;
Bus_RNW_reg_reg_10 : in STD_LOGIC;
Bus_RNW_reg_reg_11 : in STD_LOGIC;
Bus_RNW_reg_reg_12 : in STD_LOGIC;
Bus_RNW_reg_reg_13 : in STD_LOGIC;
Bus_RNW_reg_reg_14 : in STD_LOGIC;
Bus_RNW_reg_reg_15 : in STD_LOGIC;
Bus_RNW_reg_reg_16 : in STD_LOGIC;
Bus_RNW_reg_reg_17 : in STD_LOGIC;
Bus_RNW_reg_reg_18 : in STD_LOGIC;
\LOAD_REG_GEN[20].LOAD_REG_I\ : in STD_LOGIC;
D_1 : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_2\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_3\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_4\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_5\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_6\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_7\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_8\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_9\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_10\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_11\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_12\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_13\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_14\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_15\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_16\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_17\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_18\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_19\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_20\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_21\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_22\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_23\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_24\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_25\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_26\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_27\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_28\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_29\ : in STD_LOGIC;
D_2 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[30]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[29]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[28]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[27]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[26]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[25]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[24]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[23]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[22]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[21]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[20]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[19]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[18]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[17]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[16]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[15]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[14]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[13]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[12]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[11]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[10]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[9]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[8]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[7]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[6]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[5]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[4]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[3]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[2]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[1]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[0]_0\ : in STD_LOGIC;
bus2ip_wrce : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 9 downto 0 );
pair0_Select : in STD_LOGIC;
\TCSR0_GENERATE[24].TCSR0_FF_I\ : in STD_LOGIC;
\TCSR1_GENERATE[24].TCSR1_FF_I\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_30\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_0\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_31\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\ : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : in STD_LOGIC;
\bus2ip_wrce__0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
freeze : in STD_LOGIC;
capturetrig0 : in STD_LOGIC;
capturetrig1 : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_tc_core;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_tc_core is
signal COUNTER_0_I_n_64 : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_33\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_34\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_35\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_36\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_37\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_38\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_39\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_40\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_41\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_42\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_43\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_44\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_45\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_46\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_47\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_48\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_49\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_50\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_51\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_52\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_53\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_54\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_55\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_56\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_57\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_58\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_59\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_60\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_61\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_62\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_63\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_64\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_65\ : STD_LOGIC;
signal \^inferred_gen.icount_out_reg[0]\ : STD_LOGIC_VECTOR ( 87 downto 0 );
signal R : STD_LOGIC;
signal TIMER_CONTROL_I_n_12 : STD_LOGIC;
signal TIMER_CONTROL_I_n_13 : STD_LOGIC;
signal TIMER_CONTROL_I_n_14 : STD_LOGIC;
signal TIMER_CONTROL_I_n_15 : STD_LOGIC;
signal TIMER_CONTROL_I_n_16 : STD_LOGIC;
signal TIMER_CONTROL_I_n_17 : STD_LOGIC;
signal TIMER_CONTROL_I_n_18 : STD_LOGIC;
signal TIMER_CONTROL_I_n_19 : STD_LOGIC;
signal TIMER_CONTROL_I_n_20 : STD_LOGIC;
signal TIMER_CONTROL_I_n_21 : STD_LOGIC;
signal TIMER_CONTROL_I_n_22 : STD_LOGIC;
signal TIMER_CONTROL_I_n_24 : STD_LOGIC;
signal TIMER_CONTROL_I_n_25 : STD_LOGIC;
signal TIMER_CONTROL_I_n_26 : STD_LOGIC;
signal TIMER_CONTROL_I_n_27 : STD_LOGIC;
signal TIMER_CONTROL_I_n_28 : STD_LOGIC;
signal TIMER_CONTROL_I_n_29 : STD_LOGIC;
signal TIMER_CONTROL_I_n_3 : STD_LOGIC;
signal TIMER_CONTROL_I_n_30 : STD_LOGIC;
signal TIMER_CONTROL_I_n_4 : STD_LOGIC;
signal \^bus2ip_reset\ : STD_LOGIC;
signal counter_TC : STD_LOGIC_VECTOR ( 0 to 1 );
signal load_Counter_Reg : STD_LOGIC_VECTOR ( 0 to 1 );
signal \^pwm0\ : STD_LOGIC;
signal read_Mux_In : STD_LOGIC_VECTOR ( 85 to 95 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of PWM_FF_I : label is "PRIMITIVE";
attribute IS_S_INVERTED : string;
attribute IS_S_INVERTED of PWM_FF_I : label is "1'b0";
begin
\INFERRED_GEN.icount_out_reg[0]\(87 downto 0) <= \^inferred_gen.icount_out_reg[0]\(87 downto 0);
bus2ip_reset <= \^bus2ip_reset\;
pwm0 <= \^pwm0\;
COUNTER_0_I: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_count_module
port map (
D_1 => D_1,
E(0) => TIMER_CONTROL_I_n_24,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_10\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_10\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_11\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_11\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_12\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_12\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_13\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_13\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_14\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_14\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_15\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_15\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_16\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_16\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_17\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_17\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_18\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_18\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_19\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_19\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_2\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_2\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_20\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_20\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_21\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_21\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_22\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_22\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_23\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_23\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_24\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_24\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_25\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_25\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_26\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_26\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_27\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_27\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_28\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_28\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_29\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_29\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_3\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_3\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_4\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_4\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_5\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_5\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_6\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_6\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_7\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_7\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_8\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_8\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_9\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_9\,
\INFERRED_GEN.icount_out_reg[31]\(52 downto 0) => \^inferred_gen.icount_out_reg[0]\(84 downto 32),
Q(0) => TIMER_CONTROL_I_n_3,
S(0) => TIMER_CONTROL_I_n_27,
\TCSR0_GENERATE[27].TCSR0_FF_I\ => TIMER_CONTROL_I_n_28,
counter_TC(0) => counter_TC(0),
generateOutPre0_reg => COUNTER_0_I_n_64,
load_Counter_Reg(0) => load_Counter_Reg(0),
read_Mux_In(10) => read_Mux_In(85),
read_Mux_In(9) => read_Mux_In(86),
read_Mux_In(8) => read_Mux_In(87),
read_Mux_In(7) => read_Mux_In(88),
read_Mux_In(6) => read_Mux_In(89),
read_Mux_In(5) => read_Mux_In(90),
read_Mux_In(4) => read_Mux_In(91),
read_Mux_In(3) => read_Mux_In(92),
read_Mux_In(2) => read_Mux_In(93),
read_Mux_In(1) => read_Mux_In(94),
read_Mux_In(0) => read_Mux_In(95),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_aresetn_0 => \^bus2ip_reset\
);
\GEN_SECOND_TIMER.COUNTER_1_I\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_count_module_0
port map (
D_2 => D_2,
E(0) => TIMER_CONTROL_I_n_25,
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\ => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\ => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_0\,
\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\ => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
\INFERRED_GEN.icount_out_reg[0]\ => \INFERRED_GEN.icount_out_reg[0]_0\,
\INFERRED_GEN.icount_out_reg[10]\ => \INFERRED_GEN.icount_out_reg[10]\,
\INFERRED_GEN.icount_out_reg[11]\ => \INFERRED_GEN.icount_out_reg[11]\,
\INFERRED_GEN.icount_out_reg[12]\ => \INFERRED_GEN.icount_out_reg[12]\,
\INFERRED_GEN.icount_out_reg[13]\ => \INFERRED_GEN.icount_out_reg[13]\,
\INFERRED_GEN.icount_out_reg[14]\ => \INFERRED_GEN.icount_out_reg[14]\,
\INFERRED_GEN.icount_out_reg[15]\ => \INFERRED_GEN.icount_out_reg[15]\,
\INFERRED_GEN.icount_out_reg[16]\ => \INFERRED_GEN.icount_out_reg[16]\,
\INFERRED_GEN.icount_out_reg[17]\ => \INFERRED_GEN.icount_out_reg[17]\,
\INFERRED_GEN.icount_out_reg[18]\ => \INFERRED_GEN.icount_out_reg[18]\,
\INFERRED_GEN.icount_out_reg[19]\ => \INFERRED_GEN.icount_out_reg[19]\,
\INFERRED_GEN.icount_out_reg[1]\ => \INFERRED_GEN.icount_out_reg[1]\,
\INFERRED_GEN.icount_out_reg[20]\ => \INFERRED_GEN.icount_out_reg[20]\,
\INFERRED_GEN.icount_out_reg[21]\ => \INFERRED_GEN.icount_out_reg[21]\,
\INFERRED_GEN.icount_out_reg[22]\ => \INFERRED_GEN.icount_out_reg[22]\,
\INFERRED_GEN.icount_out_reg[23]\ => \INFERRED_GEN.icount_out_reg[23]\,
\INFERRED_GEN.icount_out_reg[24]\ => \INFERRED_GEN.icount_out_reg[24]\,
\INFERRED_GEN.icount_out_reg[25]\ => \INFERRED_GEN.icount_out_reg[25]\,
\INFERRED_GEN.icount_out_reg[26]\ => \INFERRED_GEN.icount_out_reg[26]\,
\INFERRED_GEN.icount_out_reg[27]\ => \INFERRED_GEN.icount_out_reg[27]\,
\INFERRED_GEN.icount_out_reg[28]\ => \INFERRED_GEN.icount_out_reg[28]\,
\INFERRED_GEN.icount_out_reg[29]\ => \INFERRED_GEN.icount_out_reg[29]\,
\INFERRED_GEN.icount_out_reg[2]\ => \INFERRED_GEN.icount_out_reg[2]\,
\INFERRED_GEN.icount_out_reg[30]\ => \INFERRED_GEN.icount_out_reg[30]\,
\INFERRED_GEN.icount_out_reg[31]\ => \^bus2ip_reset\,
\INFERRED_GEN.icount_out_reg[31]_0\(31 downto 0) => \^inferred_gen.icount_out_reg[0]\(63 downto 32),
\INFERRED_GEN.icount_out_reg[3]\ => \INFERRED_GEN.icount_out_reg[3]\,
\INFERRED_GEN.icount_out_reg[4]\ => \INFERRED_GEN.icount_out_reg[4]\,
\INFERRED_GEN.icount_out_reg[5]\ => \INFERRED_GEN.icount_out_reg[5]\,
\INFERRED_GEN.icount_out_reg[6]\ => \INFERRED_GEN.icount_out_reg[6]\,
\INFERRED_GEN.icount_out_reg[7]\ => \INFERRED_GEN.icount_out_reg[7]\,
\INFERRED_GEN.icount_out_reg[8]\ => \INFERRED_GEN.icount_out_reg[8]\,
\INFERRED_GEN.icount_out_reg[9]\ => \INFERRED_GEN.icount_out_reg[9]\,
Q(31 downto 0) => \^inferred_gen.icount_out_reg[0]\(31 downto 0),
S(0) => TIMER_CONTROL_I_n_30,
\TCSR0_GENERATE[20].TCSR0_FF_I\ => TIMER_CONTROL_I_n_29,
counter_TC(0) => counter_TC(1),
\counter_TC_Reg_reg[1]\(0) => TIMER_CONTROL_I_n_4,
generateOutPre1_reg => \GEN_SECOND_TIMER.COUNTER_1_I_n_65\,
load_Counter_Reg(0) => load_Counter_Reg(1),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
\s_axi_rdata_i_reg[0]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_33\,
\s_axi_rdata_i_reg[10]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_43\,
\s_axi_rdata_i_reg[11]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_44\,
\s_axi_rdata_i_reg[12]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_45\,
\s_axi_rdata_i_reg[13]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_46\,
\s_axi_rdata_i_reg[14]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_47\,
\s_axi_rdata_i_reg[15]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_48\,
\s_axi_rdata_i_reg[16]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_49\,
\s_axi_rdata_i_reg[17]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_50\,
\s_axi_rdata_i_reg[18]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_51\,
\s_axi_rdata_i_reg[19]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_52\,
\s_axi_rdata_i_reg[1]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_34\,
\s_axi_rdata_i_reg[20]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_53\,
\s_axi_rdata_i_reg[21]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_54\,
\s_axi_rdata_i_reg[22]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_55\,
\s_axi_rdata_i_reg[23]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_56\,
\s_axi_rdata_i_reg[24]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_57\,
\s_axi_rdata_i_reg[25]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_58\,
\s_axi_rdata_i_reg[26]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_59\,
\s_axi_rdata_i_reg[27]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_60\,
\s_axi_rdata_i_reg[28]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_61\,
\s_axi_rdata_i_reg[29]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_62\,
\s_axi_rdata_i_reg[2]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_35\,
\s_axi_rdata_i_reg[30]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_63\,
\s_axi_rdata_i_reg[31]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_64\,
\s_axi_rdata_i_reg[3]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_36\,
\s_axi_rdata_i_reg[4]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_37\,
\s_axi_rdata_i_reg[5]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_38\,
\s_axi_rdata_i_reg[6]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_39\,
\s_axi_rdata_i_reg[7]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_40\,
\s_axi_rdata_i_reg[8]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_41\,
\s_axi_rdata_i_reg[9]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_42\
);
PWM_FF_I: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => TIMER_CONTROL_I_n_26,
Q => \^pwm0\,
R => R
);
READ_MUX_I: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mux_onehot_f
port map (
Bus_RNW_reg_reg => Bus_RNW_reg_reg,
Bus_RNW_reg_reg_0 => Bus_RNW_reg_reg_0,
Bus_RNW_reg_reg_1 => Bus_RNW_reg_reg_1,
Bus_RNW_reg_reg_10 => Bus_RNW_reg_reg_10,
Bus_RNW_reg_reg_11 => Bus_RNW_reg_reg_11,
Bus_RNW_reg_reg_12 => Bus_RNW_reg_reg_12,
Bus_RNW_reg_reg_13 => Bus_RNW_reg_reg_13,
Bus_RNW_reg_reg_14 => Bus_RNW_reg_reg_14,
Bus_RNW_reg_reg_15 => Bus_RNW_reg_reg_15,
Bus_RNW_reg_reg_16 => Bus_RNW_reg_reg_16,
Bus_RNW_reg_reg_17 => Bus_RNW_reg_reg_17,
Bus_RNW_reg_reg_18 => Bus_RNW_reg_reg_18,
Bus_RNW_reg_reg_2 => Bus_RNW_reg_reg_2,
Bus_RNW_reg_reg_3 => Bus_RNW_reg_reg_3,
Bus_RNW_reg_reg_4 => Bus_RNW_reg_reg_4,
Bus_RNW_reg_reg_5 => Bus_RNW_reg_reg_5,
Bus_RNW_reg_reg_6 => Bus_RNW_reg_reg_6,
Bus_RNW_reg_reg_7 => Bus_RNW_reg_reg_7,
Bus_RNW_reg_reg_8 => Bus_RNW_reg_reg_8,
Bus_RNW_reg_reg_9 => Bus_RNW_reg_reg_9,
D(31 downto 0) => D(31 downto 0),
\INFERRED_GEN.icount_out_reg[0]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_33\,
\INFERRED_GEN.icount_out_reg[10]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_43\,
\INFERRED_GEN.icount_out_reg[11]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_44\,
\INFERRED_GEN.icount_out_reg[12]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_45\,
\INFERRED_GEN.icount_out_reg[13]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_46\,
\INFERRED_GEN.icount_out_reg[14]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_47\,
\INFERRED_GEN.icount_out_reg[15]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_48\,
\INFERRED_GEN.icount_out_reg[16]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_49\,
\INFERRED_GEN.icount_out_reg[17]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_50\,
\INFERRED_GEN.icount_out_reg[18]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_51\,
\INFERRED_GEN.icount_out_reg[19]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_52\,
\INFERRED_GEN.icount_out_reg[1]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_34\,
\INFERRED_GEN.icount_out_reg[20]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_53\,
\INFERRED_GEN.icount_out_reg[21]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_54\,
\INFERRED_GEN.icount_out_reg[22]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_55\,
\INFERRED_GEN.icount_out_reg[23]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_56\,
\INFERRED_GEN.icount_out_reg[24]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_57\,
\INFERRED_GEN.icount_out_reg[25]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_58\,
\INFERRED_GEN.icount_out_reg[26]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_59\,
\INFERRED_GEN.icount_out_reg[27]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_60\,
\INFERRED_GEN.icount_out_reg[28]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_61\,
\INFERRED_GEN.icount_out_reg[29]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_62\,
\INFERRED_GEN.icount_out_reg[2]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_35\,
\INFERRED_GEN.icount_out_reg[30]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_63\,
\INFERRED_GEN.icount_out_reg[31]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_64\,
\INFERRED_GEN.icount_out_reg[3]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_36\,
\INFERRED_GEN.icount_out_reg[4]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_37\,
\INFERRED_GEN.icount_out_reg[5]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_38\,
\INFERRED_GEN.icount_out_reg[6]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_39\,
\INFERRED_GEN.icount_out_reg[7]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_40\,
\INFERRED_GEN.icount_out_reg[8]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_41\,
\INFERRED_GEN.icount_out_reg[9]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_42\,
\LOAD_REG_GEN[20].LOAD_REG_I\ => \LOAD_REG_GEN[20].LOAD_REG_I\,
\LOAD_REG_GEN[21].LOAD_REG_I\ => TIMER_CONTROL_I_n_22,
\LOAD_REG_GEN[22].LOAD_REG_I\ => TIMER_CONTROL_I_n_21,
\LOAD_REG_GEN[23].LOAD_REG_I\ => TIMER_CONTROL_I_n_20,
\LOAD_REG_GEN[24].LOAD_REG_I\ => TIMER_CONTROL_I_n_19,
\LOAD_REG_GEN[25].LOAD_REG_I\ => TIMER_CONTROL_I_n_18,
\LOAD_REG_GEN[26].LOAD_REG_I\ => TIMER_CONTROL_I_n_17,
\LOAD_REG_GEN[27].LOAD_REG_I\ => TIMER_CONTROL_I_n_16,
\LOAD_REG_GEN[28].LOAD_REG_I\ => TIMER_CONTROL_I_n_15,
\LOAD_REG_GEN[29].LOAD_REG_I\ => TIMER_CONTROL_I_n_14,
\LOAD_REG_GEN[30].LOAD_REG_I\ => TIMER_CONTROL_I_n_13,
\LOAD_REG_GEN[31].LOAD_REG_I\ => TIMER_CONTROL_I_n_12
);
TIMER_CONTROL_I: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_timer_control
port map (
Bus_RNW_reg => Bus_RNW_reg,
D_0 => D_0,
E(0) => TIMER_CONTROL_I_n_24,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\ => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_30\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_31\,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\ => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\ => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
\INFERRED_GEN.icount_out_reg[0]\ => \^inferred_gen.icount_out_reg[0]\(87),
\INFERRED_GEN.icount_out_reg[0]_0\(0) => TIMER_CONTROL_I_n_25,
\INFERRED_GEN.icount_out_reg[1]\(1) => \^inferred_gen.icount_out_reg[0]\(33),
\INFERRED_GEN.icount_out_reg[1]\(0) => \^inferred_gen.icount_out_reg[0]\(1),
\INFERRED_GEN.icount_out_reg[32]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_65\,
\INFERRED_GEN.icount_out_reg[32]_0\ => COUNTER_0_I_n_64,
\INFERRED_GEN.icount_out_reg[4]\(0) => TIMER_CONTROL_I_n_30,
\LOAD_REG_GEN[21].LOAD_REG_I\(10) => read_Mux_In(85),
\LOAD_REG_GEN[21].LOAD_REG_I\(9) => read_Mux_In(86),
\LOAD_REG_GEN[21].LOAD_REG_I\(8) => read_Mux_In(87),
\LOAD_REG_GEN[21].LOAD_REG_I\(7) => read_Mux_In(88),
\LOAD_REG_GEN[21].LOAD_REG_I\(6) => read_Mux_In(89),
\LOAD_REG_GEN[21].LOAD_REG_I\(5) => read_Mux_In(90),
\LOAD_REG_GEN[21].LOAD_REG_I\(4) => read_Mux_In(91),
\LOAD_REG_GEN[21].LOAD_REG_I\(3) => read_Mux_In(92),
\LOAD_REG_GEN[21].LOAD_REG_I\(2) => read_Mux_In(93),
\LOAD_REG_GEN[21].LOAD_REG_I\(1) => read_Mux_In(94),
\LOAD_REG_GEN[21].LOAD_REG_I\(0) => read_Mux_In(95),
\LOAD_REG_GEN[24].LOAD_REG_I\ => TIMER_CONTROL_I_n_28,
\LOAD_REG_GEN[24].LOAD_REG_I_0\ => TIMER_CONTROL_I_n_29,
PWM_FF_I => TIMER_CONTROL_I_n_26,
Q(1) => TIMER_CONTROL_I_n_3,
Q(0) => TIMER_CONTROL_I_n_4,
R => R,
S(0) => TIMER_CONTROL_I_n_27,
SR(0) => \^bus2ip_reset\,
\TCSR0_GENERATE[24].TCSR0_FF_I_0\ => \^inferred_gen.icount_out_reg[0]\(86),
\TCSR0_GENERATE[24].TCSR0_FF_I_1\ => \TCSR0_GENERATE[24].TCSR0_FF_I\,
\TCSR1_GENERATE[23].TCSR1_FF_I_0\ => \^inferred_gen.icount_out_reg[0]\(85),
\TCSR1_GENERATE[24].TCSR1_FF_I_0\ => \TCSR1_GENERATE[24].TCSR1_FF_I\,
bus2ip_wrce(1 downto 0) => bus2ip_wrce(1 downto 0),
\bus2ip_wrce__0\(0) => \bus2ip_wrce__0\(0),
capturetrig0 => capturetrig0,
capturetrig1 => capturetrig1,
counter_TC(0 to 1) => counter_TC(0 to 1),
freeze => freeze,
generateout0 => generateout0,
generateout1 => generateout1,
interrupt => interrupt,
load_Counter_Reg(0 to 1) => load_Counter_Reg(0 to 1),
pair0_Select => pair0_Select,
pwm0 => \^pwm0\,
read_done1 => read_done1,
s_axi_aclk => s_axi_aclk,
\s_axi_rdata_i_reg[0]\ => TIMER_CONTROL_I_n_12,
\s_axi_rdata_i_reg[10]\ => TIMER_CONTROL_I_n_22,
\s_axi_rdata_i_reg[1]\ => TIMER_CONTROL_I_n_13,
\s_axi_rdata_i_reg[2]\ => TIMER_CONTROL_I_n_14,
\s_axi_rdata_i_reg[3]\ => TIMER_CONTROL_I_n_15,
\s_axi_rdata_i_reg[4]\ => TIMER_CONTROL_I_n_16,
\s_axi_rdata_i_reg[5]\ => TIMER_CONTROL_I_n_17,
\s_axi_rdata_i_reg[6]\ => TIMER_CONTROL_I_n_18,
\s_axi_rdata_i_reg[7]\ => TIMER_CONTROL_I_n_19,
\s_axi_rdata_i_reg[8]\ => TIMER_CONTROL_I_n_20,
\s_axi_rdata_i_reg[9]\ => TIMER_CONTROL_I_n_21,
s_axi_wdata(9 downto 0) => s_axi_wdata(9 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif is
port (
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : out STD_LOGIC;
Bus_RNW_reg : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
\s_axi_rdata_i_reg[12]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[13]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[14]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[15]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[16]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[17]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[18]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[19]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[20]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[21]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[22]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[23]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[24]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[25]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[26]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[27]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[28]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[29]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[30]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[31]\ : out STD_LOGIC;
pair0_Select : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
\s_axi_rdata_i_reg[11]\ : out STD_LOGIC;
\TCSR0_GENERATE[24].TCSR0_FF_I\ : out STD_LOGIC;
\TCSR1_GENERATE[24].TCSR1_FF_I\ : out STD_LOGIC;
\LOAD_REG_GEN[31].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[30].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[29].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[28].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[27].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[26].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[25].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[24].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[23].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[22].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[21].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[20].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[19].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[18].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[17].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[16].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[15].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[14].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[13].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[12].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[11].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[10].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[9].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[8].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[7].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[6].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[5].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[4].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[3].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[2].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[1].LOAD_REG_I\ : out STD_LOGIC;
D_0 : out STD_LOGIC;
\bus2ip_wrce__0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_wrce : out STD_LOGIC_VECTOR ( 1 downto 0 );
\LOAD_REG_GEN[31].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[30].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[29].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[28].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[27].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[26].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[25].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[24].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[23].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[22].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[21].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[20].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[19].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[18].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[17].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[16].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[15].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[14].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[13].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[12].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[11].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[10].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[9].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[8].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[7].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[6].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[5].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[4].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[3].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[2].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[1].LOAD_REG_I_0\ : out STD_LOGIC;
D_1 : out STD_LOGIC;
s_axi_rvalid_i_reg : out STD_LOGIC;
s_axi_rvalid_i_reg_0 : out STD_LOGIC;
s_axi_rvalid_i_reg_1 : out STD_LOGIC;
\TCSR0_GENERATE[23].TCSR0_FF_I\ : out STD_LOGIC;
\TCSR1_GENERATE[23].TCSR1_FF_I\ : out STD_LOGIC;
\s_axi_rdata_i_reg[10]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[0]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[0]_0\ : out STD_LOGIC;
READ_DONE0_I : out STD_LOGIC;
READ_DONE1_I : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
bus2ip_reset : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
read_Mux_In : in STD_LOGIC_VECTOR ( 87 downto 0 );
s_axi_aresetn : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
D_2 : in STD_LOGIC;
read_done1 : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif is
begin
I_SLAVE_ATTACHMENT: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment
port map (
D(31 downto 0) => D(31 downto 0),
D_0 => D_0,
D_1 => D_1,
D_2 => D_2,
\LOAD_REG_GEN[10].LOAD_REG_I\ => \LOAD_REG_GEN[10].LOAD_REG_I\,
\LOAD_REG_GEN[10].LOAD_REG_I_0\ => \LOAD_REG_GEN[10].LOAD_REG_I_0\,
\LOAD_REG_GEN[11].LOAD_REG_I\ => \LOAD_REG_GEN[11].LOAD_REG_I\,
\LOAD_REG_GEN[11].LOAD_REG_I_0\ => \LOAD_REG_GEN[11].LOAD_REG_I_0\,
\LOAD_REG_GEN[12].LOAD_REG_I\ => \LOAD_REG_GEN[12].LOAD_REG_I\,
\LOAD_REG_GEN[12].LOAD_REG_I_0\ => \LOAD_REG_GEN[12].LOAD_REG_I_0\,
\LOAD_REG_GEN[13].LOAD_REG_I\ => \LOAD_REG_GEN[13].LOAD_REG_I\,
\LOAD_REG_GEN[13].LOAD_REG_I_0\ => \LOAD_REG_GEN[13].LOAD_REG_I_0\,
\LOAD_REG_GEN[14].LOAD_REG_I\ => \LOAD_REG_GEN[14].LOAD_REG_I\,
\LOAD_REG_GEN[14].LOAD_REG_I_0\ => \LOAD_REG_GEN[14].LOAD_REG_I_0\,
\LOAD_REG_GEN[15].LOAD_REG_I\ => \LOAD_REG_GEN[15].LOAD_REG_I\,
\LOAD_REG_GEN[15].LOAD_REG_I_0\ => \LOAD_REG_GEN[15].LOAD_REG_I_0\,
\LOAD_REG_GEN[16].LOAD_REG_I\ => \LOAD_REG_GEN[16].LOAD_REG_I\,
\LOAD_REG_GEN[16].LOAD_REG_I_0\ => \LOAD_REG_GEN[16].LOAD_REG_I_0\,
\LOAD_REG_GEN[17].LOAD_REG_I\ => \LOAD_REG_GEN[17].LOAD_REG_I\,
\LOAD_REG_GEN[17].LOAD_REG_I_0\ => \LOAD_REG_GEN[17].LOAD_REG_I_0\,
\LOAD_REG_GEN[18].LOAD_REG_I\ => \LOAD_REG_GEN[18].LOAD_REG_I\,
\LOAD_REG_GEN[18].LOAD_REG_I_0\ => \LOAD_REG_GEN[18].LOAD_REG_I_0\,
\LOAD_REG_GEN[19].LOAD_REG_I\ => \LOAD_REG_GEN[19].LOAD_REG_I\,
\LOAD_REG_GEN[19].LOAD_REG_I_0\ => \LOAD_REG_GEN[19].LOAD_REG_I_0\,
\LOAD_REG_GEN[1].LOAD_REG_I\ => \LOAD_REG_GEN[1].LOAD_REG_I\,
\LOAD_REG_GEN[1].LOAD_REG_I_0\ => \LOAD_REG_GEN[1].LOAD_REG_I_0\,
\LOAD_REG_GEN[20].LOAD_REG_I\ => \LOAD_REG_GEN[20].LOAD_REG_I\,
\LOAD_REG_GEN[20].LOAD_REG_I_0\ => \LOAD_REG_GEN[20].LOAD_REG_I_0\,
\LOAD_REG_GEN[21].LOAD_REG_I\ => \LOAD_REG_GEN[21].LOAD_REG_I\,
\LOAD_REG_GEN[21].LOAD_REG_I_0\ => \LOAD_REG_GEN[21].LOAD_REG_I_0\,
\LOAD_REG_GEN[22].LOAD_REG_I\ => \LOAD_REG_GEN[22].LOAD_REG_I\,
\LOAD_REG_GEN[22].LOAD_REG_I_0\ => \LOAD_REG_GEN[22].LOAD_REG_I_0\,
\LOAD_REG_GEN[23].LOAD_REG_I\ => \LOAD_REG_GEN[23].LOAD_REG_I\,
\LOAD_REG_GEN[23].LOAD_REG_I_0\ => \LOAD_REG_GEN[23].LOAD_REG_I_0\,
\LOAD_REG_GEN[24].LOAD_REG_I\ => \LOAD_REG_GEN[24].LOAD_REG_I\,
\LOAD_REG_GEN[24].LOAD_REG_I_0\ => \LOAD_REG_GEN[24].LOAD_REG_I_0\,
\LOAD_REG_GEN[25].LOAD_REG_I\ => \LOAD_REG_GEN[25].LOAD_REG_I\,
\LOAD_REG_GEN[25].LOAD_REG_I_0\ => \LOAD_REG_GEN[25].LOAD_REG_I_0\,
\LOAD_REG_GEN[26].LOAD_REG_I\ => \LOAD_REG_GEN[26].LOAD_REG_I\,
\LOAD_REG_GEN[26].LOAD_REG_I_0\ => \LOAD_REG_GEN[26].LOAD_REG_I_0\,
\LOAD_REG_GEN[27].LOAD_REG_I\ => \LOAD_REG_GEN[27].LOAD_REG_I\,
\LOAD_REG_GEN[27].LOAD_REG_I_0\ => \LOAD_REG_GEN[27].LOAD_REG_I_0\,
\LOAD_REG_GEN[28].LOAD_REG_I\ => \LOAD_REG_GEN[28].LOAD_REG_I\,
\LOAD_REG_GEN[28].LOAD_REG_I_0\ => \LOAD_REG_GEN[28].LOAD_REG_I_0\,
\LOAD_REG_GEN[29].LOAD_REG_I\ => \LOAD_REG_GEN[29].LOAD_REG_I\,
\LOAD_REG_GEN[29].LOAD_REG_I_0\ => \LOAD_REG_GEN[29].LOAD_REG_I_0\,
\LOAD_REG_GEN[2].LOAD_REG_I\ => \LOAD_REG_GEN[2].LOAD_REG_I\,
\LOAD_REG_GEN[2].LOAD_REG_I_0\ => \LOAD_REG_GEN[2].LOAD_REG_I_0\,
\LOAD_REG_GEN[30].LOAD_REG_I\ => \LOAD_REG_GEN[30].LOAD_REG_I\,
\LOAD_REG_GEN[30].LOAD_REG_I_0\ => \LOAD_REG_GEN[30].LOAD_REG_I_0\,
\LOAD_REG_GEN[31].LOAD_REG_I\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
\LOAD_REG_GEN[31].LOAD_REG_I_0\ => \LOAD_REG_GEN[31].LOAD_REG_I\,
\LOAD_REG_GEN[31].LOAD_REG_I_1\ => \LOAD_REG_GEN[31].LOAD_REG_I_0\,
\LOAD_REG_GEN[3].LOAD_REG_I\ => \LOAD_REG_GEN[3].LOAD_REG_I\,
\LOAD_REG_GEN[3].LOAD_REG_I_0\ => \LOAD_REG_GEN[3].LOAD_REG_I_0\,
\LOAD_REG_GEN[4].LOAD_REG_I\ => \LOAD_REG_GEN[4].LOAD_REG_I\,
\LOAD_REG_GEN[4].LOAD_REG_I_0\ => \LOAD_REG_GEN[4].LOAD_REG_I_0\,
\LOAD_REG_GEN[5].LOAD_REG_I\ => \LOAD_REG_GEN[5].LOAD_REG_I\,
\LOAD_REG_GEN[5].LOAD_REG_I_0\ => \LOAD_REG_GEN[5].LOAD_REG_I_0\,
\LOAD_REG_GEN[6].LOAD_REG_I\ => \LOAD_REG_GEN[6].LOAD_REG_I\,
\LOAD_REG_GEN[6].LOAD_REG_I_0\ => \LOAD_REG_GEN[6].LOAD_REG_I_0\,
\LOAD_REG_GEN[7].LOAD_REG_I\ => \LOAD_REG_GEN[7].LOAD_REG_I\,
\LOAD_REG_GEN[7].LOAD_REG_I_0\ => \LOAD_REG_GEN[7].LOAD_REG_I_0\,
\LOAD_REG_GEN[8].LOAD_REG_I\ => \LOAD_REG_GEN[8].LOAD_REG_I\,
\LOAD_REG_GEN[8].LOAD_REG_I_0\ => \LOAD_REG_GEN[8].LOAD_REG_I_0\,
\LOAD_REG_GEN[9].LOAD_REG_I\ => \LOAD_REG_GEN[9].LOAD_REG_I\,
\LOAD_REG_GEN[9].LOAD_REG_I_0\ => \LOAD_REG_GEN[9].LOAD_REG_I_0\,
READ_DONE0_I => READ_DONE0_I,
READ_DONE1_I => READ_DONE1_I,
\TCSR0_GENERATE[23].TCSR0_FF_I\ => Bus_RNW_reg,
\TCSR0_GENERATE[23].TCSR0_FF_I_0\ => \TCSR0_GENERATE[23].TCSR0_FF_I\,
\TCSR0_GENERATE[24].TCSR0_FF_I\ => \TCSR0_GENERATE[24].TCSR0_FF_I\,
\TCSR1_GENERATE[23].TCSR1_FF_I\ => \TCSR1_GENERATE[23].TCSR1_FF_I\,
\TCSR1_GENERATE[24].TCSR1_FF_I\ => \TCSR1_GENERATE[24].TCSR1_FF_I\,
bus2ip_reset => bus2ip_reset,
bus2ip_wrce(1 downto 0) => bus2ip_wrce(1 downto 0),
\bus2ip_wrce__0\(0) => \bus2ip_wrce__0\(0),
pair0_Select => pair0_Select,
read_Mux_In(87 downto 0) => read_Mux_In(87 downto 0),
read_done1 => read_done1,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(2 downto 0) => s_axi_araddr(2 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(2 downto 0) => s_axi_awaddr(2 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
\s_axi_rdata_i_reg[0]_0\ => \s_axi_rdata_i_reg[0]\,
\s_axi_rdata_i_reg[0]_1\ => \s_axi_rdata_i_reg[0]_0\,
\s_axi_rdata_i_reg[10]_0\ => \s_axi_rdata_i_reg[10]\,
\s_axi_rdata_i_reg[11]_0\ => \s_axi_rdata_i_reg[11]\,
\s_axi_rdata_i_reg[12]_0\ => \s_axi_rdata_i_reg[12]\,
\s_axi_rdata_i_reg[13]_0\ => \s_axi_rdata_i_reg[13]\,
\s_axi_rdata_i_reg[14]_0\ => \s_axi_rdata_i_reg[14]\,
\s_axi_rdata_i_reg[15]_0\ => \s_axi_rdata_i_reg[15]\,
\s_axi_rdata_i_reg[16]_0\ => \s_axi_rdata_i_reg[16]\,
\s_axi_rdata_i_reg[17]_0\ => \s_axi_rdata_i_reg[17]\,
\s_axi_rdata_i_reg[18]_0\ => \s_axi_rdata_i_reg[18]\,
\s_axi_rdata_i_reg[19]_0\ => \s_axi_rdata_i_reg[19]\,
\s_axi_rdata_i_reg[20]_0\ => \s_axi_rdata_i_reg[20]\,
\s_axi_rdata_i_reg[21]_0\ => \s_axi_rdata_i_reg[21]\,
\s_axi_rdata_i_reg[22]_0\ => \s_axi_rdata_i_reg[22]\,
\s_axi_rdata_i_reg[23]_0\ => \s_axi_rdata_i_reg[23]\,
\s_axi_rdata_i_reg[24]_0\ => \s_axi_rdata_i_reg[24]\,
\s_axi_rdata_i_reg[25]_0\ => \s_axi_rdata_i_reg[25]\,
\s_axi_rdata_i_reg[26]_0\ => \s_axi_rdata_i_reg[26]\,
\s_axi_rdata_i_reg[27]_0\ => \s_axi_rdata_i_reg[27]\,
\s_axi_rdata_i_reg[28]_0\ => \s_axi_rdata_i_reg[28]\,
\s_axi_rdata_i_reg[29]_0\ => \s_axi_rdata_i_reg[29]\,
\s_axi_rdata_i_reg[30]_0\ => \s_axi_rdata_i_reg[30]\,
\s_axi_rdata_i_reg[31]_0\ => \s_axi_rdata_i_reg[31]\,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_rvalid_i_reg_0 => s_axi_rvalid_i_reg,
s_axi_rvalid_i_reg_1 => s_axi_rvalid_i_reg_0,
s_axi_rvalid_i_reg_2 => s_axi_rvalid_i_reg_1,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_timer is
port (
capturetrig0 : in STD_LOGIC;
capturetrig1 : in STD_LOGIC;
generateout0 : out STD_LOGIC;
generateout1 : out STD_LOGIC;
pwm0 : out STD_LOGIC;
interrupt : out STD_LOGIC;
freeze : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC
);
attribute C_COUNT_WIDTH : integer;
attribute C_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_timer : entity is 32;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_timer : entity is "zynq";
attribute C_GEN0_ASSERT : string;
attribute C_GEN0_ASSERT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_timer : entity is "1'b1";
attribute C_GEN1_ASSERT : string;
attribute C_GEN1_ASSERT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_timer : entity is "1'b1";
attribute C_ONE_TIMER_ONLY : integer;
attribute C_ONE_TIMER_ONLY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_timer : entity is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_timer : entity is 5;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_timer : entity is 32;
attribute C_TRIG0_ASSERT : string;
attribute C_TRIG0_ASSERT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_timer : entity is "1'b1";
attribute C_TRIG1_ASSERT : string;
attribute C_TRIG1_ASSERT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_timer : entity is "1'b1";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_timer : entity is "yes";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_timer;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_timer is
signal \<const0>\ : STD_LOGIC;
signal AXI4_LITE_I_n_10 : STD_LOGIC;
signal AXI4_LITE_I_n_100 : STD_LOGIC;
signal AXI4_LITE_I_n_101 : STD_LOGIC;
signal AXI4_LITE_I_n_102 : STD_LOGIC;
signal AXI4_LITE_I_n_103 : STD_LOGIC;
signal AXI4_LITE_I_n_104 : STD_LOGIC;
signal AXI4_LITE_I_n_105 : STD_LOGIC;
signal AXI4_LITE_I_n_106 : STD_LOGIC;
signal AXI4_LITE_I_n_11 : STD_LOGIC;
signal AXI4_LITE_I_n_12 : STD_LOGIC;
signal AXI4_LITE_I_n_13 : STD_LOGIC;
signal AXI4_LITE_I_n_14 : STD_LOGIC;
signal AXI4_LITE_I_n_15 : STD_LOGIC;
signal AXI4_LITE_I_n_16 : STD_LOGIC;
signal AXI4_LITE_I_n_17 : STD_LOGIC;
signal AXI4_LITE_I_n_18 : STD_LOGIC;
signal AXI4_LITE_I_n_19 : STD_LOGIC;
signal AXI4_LITE_I_n_20 : STD_LOGIC;
signal AXI4_LITE_I_n_21 : STD_LOGIC;
signal AXI4_LITE_I_n_22 : STD_LOGIC;
signal AXI4_LITE_I_n_23 : STD_LOGIC;
signal AXI4_LITE_I_n_27 : STD_LOGIC;
signal AXI4_LITE_I_n_28 : STD_LOGIC;
signal AXI4_LITE_I_n_29 : STD_LOGIC;
signal AXI4_LITE_I_n_30 : STD_LOGIC;
signal AXI4_LITE_I_n_31 : STD_LOGIC;
signal AXI4_LITE_I_n_32 : STD_LOGIC;
signal AXI4_LITE_I_n_33 : STD_LOGIC;
signal AXI4_LITE_I_n_34 : STD_LOGIC;
signal AXI4_LITE_I_n_35 : STD_LOGIC;
signal AXI4_LITE_I_n_36 : STD_LOGIC;
signal AXI4_LITE_I_n_37 : STD_LOGIC;
signal AXI4_LITE_I_n_38 : STD_LOGIC;
signal AXI4_LITE_I_n_39 : STD_LOGIC;
signal AXI4_LITE_I_n_4 : STD_LOGIC;
signal AXI4_LITE_I_n_40 : STD_LOGIC;
signal AXI4_LITE_I_n_41 : STD_LOGIC;
signal AXI4_LITE_I_n_42 : STD_LOGIC;
signal AXI4_LITE_I_n_43 : STD_LOGIC;
signal AXI4_LITE_I_n_44 : STD_LOGIC;
signal AXI4_LITE_I_n_45 : STD_LOGIC;
signal AXI4_LITE_I_n_46 : STD_LOGIC;
signal AXI4_LITE_I_n_47 : STD_LOGIC;
signal AXI4_LITE_I_n_48 : STD_LOGIC;
signal AXI4_LITE_I_n_49 : STD_LOGIC;
signal AXI4_LITE_I_n_5 : STD_LOGIC;
signal AXI4_LITE_I_n_50 : STD_LOGIC;
signal AXI4_LITE_I_n_51 : STD_LOGIC;
signal AXI4_LITE_I_n_52 : STD_LOGIC;
signal AXI4_LITE_I_n_53 : STD_LOGIC;
signal AXI4_LITE_I_n_54 : STD_LOGIC;
signal AXI4_LITE_I_n_55 : STD_LOGIC;
signal AXI4_LITE_I_n_56 : STD_LOGIC;
signal AXI4_LITE_I_n_57 : STD_LOGIC;
signal AXI4_LITE_I_n_58 : STD_LOGIC;
signal AXI4_LITE_I_n_59 : STD_LOGIC;
signal AXI4_LITE_I_n_6 : STD_LOGIC;
signal AXI4_LITE_I_n_60 : STD_LOGIC;
signal AXI4_LITE_I_n_65 : STD_LOGIC;
signal AXI4_LITE_I_n_66 : STD_LOGIC;
signal AXI4_LITE_I_n_67 : STD_LOGIC;
signal AXI4_LITE_I_n_68 : STD_LOGIC;
signal AXI4_LITE_I_n_69 : STD_LOGIC;
signal AXI4_LITE_I_n_7 : STD_LOGIC;
signal AXI4_LITE_I_n_70 : STD_LOGIC;
signal AXI4_LITE_I_n_71 : STD_LOGIC;
signal AXI4_LITE_I_n_72 : STD_LOGIC;
signal AXI4_LITE_I_n_73 : STD_LOGIC;
signal AXI4_LITE_I_n_74 : STD_LOGIC;
signal AXI4_LITE_I_n_75 : STD_LOGIC;
signal AXI4_LITE_I_n_76 : STD_LOGIC;
signal AXI4_LITE_I_n_77 : STD_LOGIC;
signal AXI4_LITE_I_n_78 : STD_LOGIC;
signal AXI4_LITE_I_n_79 : STD_LOGIC;
signal AXI4_LITE_I_n_8 : STD_LOGIC;
signal AXI4_LITE_I_n_80 : STD_LOGIC;
signal AXI4_LITE_I_n_81 : STD_LOGIC;
signal AXI4_LITE_I_n_82 : STD_LOGIC;
signal AXI4_LITE_I_n_83 : STD_LOGIC;
signal AXI4_LITE_I_n_84 : STD_LOGIC;
signal AXI4_LITE_I_n_85 : STD_LOGIC;
signal AXI4_LITE_I_n_86 : STD_LOGIC;
signal AXI4_LITE_I_n_87 : STD_LOGIC;
signal AXI4_LITE_I_n_88 : STD_LOGIC;
signal AXI4_LITE_I_n_89 : STD_LOGIC;
signal AXI4_LITE_I_n_9 : STD_LOGIC;
signal AXI4_LITE_I_n_90 : STD_LOGIC;
signal AXI4_LITE_I_n_91 : STD_LOGIC;
signal AXI4_LITE_I_n_92 : STD_LOGIC;
signal AXI4_LITE_I_n_93 : STD_LOGIC;
signal AXI4_LITE_I_n_94 : STD_LOGIC;
signal AXI4_LITE_I_n_95 : STD_LOGIC;
signal AXI4_LITE_I_n_97 : STD_LOGIC;
signal AXI4_LITE_I_n_98 : STD_LOGIC;
signal AXI4_LITE_I_n_99 : STD_LOGIC;
signal \COUNTER_0_I/D\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I/D\ : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\ : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : STD_LOGIC;
signal \TIMER_CONTROL_I/D\ : STD_LOGIC;
signal \TIMER_CONTROL_I/pair0_Select\ : STD_LOGIC;
signal \TIMER_CONTROL_I/read_done1\ : STD_LOGIC;
signal bus2ip_reset : STD_LOGIC;
signal bus2ip_wrce : STD_LOGIC_VECTOR ( 0 to 4 );
signal \bus2ip_wrce__0\ : STD_LOGIC_VECTOR ( 5 to 5 );
signal ip2bus_data : STD_LOGIC_VECTOR ( 0 to 31 );
signal read_Mux_In : STD_LOGIC_VECTOR ( 20 to 191 );
signal \^s_axi_wready\ : STD_LOGIC;
begin
s_axi_awready <= \^s_axi_wready\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_wready <= \^s_axi_wready\;
AXI4_LITE_I: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif
port map (
Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\,
D(31) => ip2bus_data(0),
D(30) => ip2bus_data(1),
D(29) => ip2bus_data(2),
D(28) => ip2bus_data(3),
D(27) => ip2bus_data(4),
D(26) => ip2bus_data(5),
D(25) => ip2bus_data(6),
D(24) => ip2bus_data(7),
D(23) => ip2bus_data(8),
D(22) => ip2bus_data(9),
D(21) => ip2bus_data(10),
D(20) => ip2bus_data(11),
D(19) => ip2bus_data(12),
D(18) => ip2bus_data(13),
D(17) => ip2bus_data(14),
D(16) => ip2bus_data(15),
D(15) => ip2bus_data(16),
D(14) => ip2bus_data(17),
D(13) => ip2bus_data(18),
D(12) => ip2bus_data(19),
D(11) => ip2bus_data(20),
D(10) => ip2bus_data(21),
D(9) => ip2bus_data(22),
D(8) => ip2bus_data(23),
D(7) => ip2bus_data(24),
D(6) => ip2bus_data(25),
D(5) => ip2bus_data(26),
D(4) => ip2bus_data(27),
D(3) => ip2bus_data(28),
D(2) => ip2bus_data(29),
D(1) => ip2bus_data(30),
D(0) => ip2bus_data(31),
D_0 => \GEN_SECOND_TIMER.COUNTER_1_I/D\,
D_1 => \COUNTER_0_I/D\,
D_2 => \TIMER_CONTROL_I/D\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
\LOAD_REG_GEN[10].LOAD_REG_I\ => AXI4_LITE_I_n_51,
\LOAD_REG_GEN[10].LOAD_REG_I_0\ => AXI4_LITE_I_n_86,
\LOAD_REG_GEN[11].LOAD_REG_I\ => AXI4_LITE_I_n_50,
\LOAD_REG_GEN[11].LOAD_REG_I_0\ => AXI4_LITE_I_n_85,
\LOAD_REG_GEN[12].LOAD_REG_I\ => AXI4_LITE_I_n_49,
\LOAD_REG_GEN[12].LOAD_REG_I_0\ => AXI4_LITE_I_n_84,
\LOAD_REG_GEN[13].LOAD_REG_I\ => AXI4_LITE_I_n_48,
\LOAD_REG_GEN[13].LOAD_REG_I_0\ => AXI4_LITE_I_n_83,
\LOAD_REG_GEN[14].LOAD_REG_I\ => AXI4_LITE_I_n_47,
\LOAD_REG_GEN[14].LOAD_REG_I_0\ => AXI4_LITE_I_n_82,
\LOAD_REG_GEN[15].LOAD_REG_I\ => AXI4_LITE_I_n_46,
\LOAD_REG_GEN[15].LOAD_REG_I_0\ => AXI4_LITE_I_n_81,
\LOAD_REG_GEN[16].LOAD_REG_I\ => AXI4_LITE_I_n_45,
\LOAD_REG_GEN[16].LOAD_REG_I_0\ => AXI4_LITE_I_n_80,
\LOAD_REG_GEN[17].LOAD_REG_I\ => AXI4_LITE_I_n_44,
\LOAD_REG_GEN[17].LOAD_REG_I_0\ => AXI4_LITE_I_n_79,
\LOAD_REG_GEN[18].LOAD_REG_I\ => AXI4_LITE_I_n_43,
\LOAD_REG_GEN[18].LOAD_REG_I_0\ => AXI4_LITE_I_n_78,
\LOAD_REG_GEN[19].LOAD_REG_I\ => AXI4_LITE_I_n_42,
\LOAD_REG_GEN[19].LOAD_REG_I_0\ => AXI4_LITE_I_n_77,
\LOAD_REG_GEN[1].LOAD_REG_I\ => AXI4_LITE_I_n_60,
\LOAD_REG_GEN[1].LOAD_REG_I_0\ => AXI4_LITE_I_n_95,
\LOAD_REG_GEN[20].LOAD_REG_I\ => AXI4_LITE_I_n_41,
\LOAD_REG_GEN[20].LOAD_REG_I_0\ => AXI4_LITE_I_n_76,
\LOAD_REG_GEN[21].LOAD_REG_I\ => AXI4_LITE_I_n_40,
\LOAD_REG_GEN[21].LOAD_REG_I_0\ => AXI4_LITE_I_n_75,
\LOAD_REG_GEN[22].LOAD_REG_I\ => AXI4_LITE_I_n_39,
\LOAD_REG_GEN[22].LOAD_REG_I_0\ => AXI4_LITE_I_n_74,
\LOAD_REG_GEN[23].LOAD_REG_I\ => AXI4_LITE_I_n_38,
\LOAD_REG_GEN[23].LOAD_REG_I_0\ => AXI4_LITE_I_n_73,
\LOAD_REG_GEN[24].LOAD_REG_I\ => AXI4_LITE_I_n_37,
\LOAD_REG_GEN[24].LOAD_REG_I_0\ => AXI4_LITE_I_n_72,
\LOAD_REG_GEN[25].LOAD_REG_I\ => AXI4_LITE_I_n_36,
\LOAD_REG_GEN[25].LOAD_REG_I_0\ => AXI4_LITE_I_n_71,
\LOAD_REG_GEN[26].LOAD_REG_I\ => AXI4_LITE_I_n_35,
\LOAD_REG_GEN[26].LOAD_REG_I_0\ => AXI4_LITE_I_n_70,
\LOAD_REG_GEN[27].LOAD_REG_I\ => AXI4_LITE_I_n_34,
\LOAD_REG_GEN[27].LOAD_REG_I_0\ => AXI4_LITE_I_n_69,
\LOAD_REG_GEN[28].LOAD_REG_I\ => AXI4_LITE_I_n_33,
\LOAD_REG_GEN[28].LOAD_REG_I_0\ => AXI4_LITE_I_n_68,
\LOAD_REG_GEN[29].LOAD_REG_I\ => AXI4_LITE_I_n_32,
\LOAD_REG_GEN[29].LOAD_REG_I_0\ => AXI4_LITE_I_n_67,
\LOAD_REG_GEN[2].LOAD_REG_I\ => AXI4_LITE_I_n_59,
\LOAD_REG_GEN[2].LOAD_REG_I_0\ => AXI4_LITE_I_n_94,
\LOAD_REG_GEN[30].LOAD_REG_I\ => AXI4_LITE_I_n_31,
\LOAD_REG_GEN[30].LOAD_REG_I_0\ => AXI4_LITE_I_n_66,
\LOAD_REG_GEN[31].LOAD_REG_I\ => AXI4_LITE_I_n_30,
\LOAD_REG_GEN[31].LOAD_REG_I_0\ => AXI4_LITE_I_n_65,
\LOAD_REG_GEN[3].LOAD_REG_I\ => AXI4_LITE_I_n_58,
\LOAD_REG_GEN[3].LOAD_REG_I_0\ => AXI4_LITE_I_n_93,
\LOAD_REG_GEN[4].LOAD_REG_I\ => AXI4_LITE_I_n_57,
\LOAD_REG_GEN[4].LOAD_REG_I_0\ => AXI4_LITE_I_n_92,
\LOAD_REG_GEN[5].LOAD_REG_I\ => AXI4_LITE_I_n_56,
\LOAD_REG_GEN[5].LOAD_REG_I_0\ => AXI4_LITE_I_n_91,
\LOAD_REG_GEN[6].LOAD_REG_I\ => AXI4_LITE_I_n_55,
\LOAD_REG_GEN[6].LOAD_REG_I_0\ => AXI4_LITE_I_n_90,
\LOAD_REG_GEN[7].LOAD_REG_I\ => AXI4_LITE_I_n_54,
\LOAD_REG_GEN[7].LOAD_REG_I_0\ => AXI4_LITE_I_n_89,
\LOAD_REG_GEN[8].LOAD_REG_I\ => AXI4_LITE_I_n_53,
\LOAD_REG_GEN[8].LOAD_REG_I_0\ => AXI4_LITE_I_n_88,
\LOAD_REG_GEN[9].LOAD_REG_I\ => AXI4_LITE_I_n_52,
\LOAD_REG_GEN[9].LOAD_REG_I_0\ => AXI4_LITE_I_n_87,
READ_DONE0_I => AXI4_LITE_I_n_105,
READ_DONE1_I => AXI4_LITE_I_n_106,
\TCSR0_GENERATE[23].TCSR0_FF_I\ => AXI4_LITE_I_n_100,
\TCSR0_GENERATE[24].TCSR0_FF_I\ => AXI4_LITE_I_n_28,
\TCSR1_GENERATE[23].TCSR1_FF_I\ => AXI4_LITE_I_n_101,
\TCSR1_GENERATE[24].TCSR1_FF_I\ => AXI4_LITE_I_n_29,
bus2ip_reset => bus2ip_reset,
bus2ip_wrce(1) => bus2ip_wrce(0),
bus2ip_wrce(0) => bus2ip_wrce(4),
\bus2ip_wrce__0\(0) => \bus2ip_wrce__0\(5),
pair0_Select => \TIMER_CONTROL_I/pair0_Select\,
read_Mux_In(87) => read_Mux_In(20),
read_Mux_In(86) => read_Mux_In(24),
read_Mux_In(85) => read_Mux_In(56),
read_Mux_In(84) => read_Mux_In(64),
read_Mux_In(83) => read_Mux_In(65),
read_Mux_In(82) => read_Mux_In(66),
read_Mux_In(81) => read_Mux_In(67),
read_Mux_In(80) => read_Mux_In(68),
read_Mux_In(79) => read_Mux_In(69),
read_Mux_In(78) => read_Mux_In(70),
read_Mux_In(77) => read_Mux_In(71),
read_Mux_In(76) => read_Mux_In(72),
read_Mux_In(75) => read_Mux_In(73),
read_Mux_In(74) => read_Mux_In(74),
read_Mux_In(73) => read_Mux_In(75),
read_Mux_In(72) => read_Mux_In(76),
read_Mux_In(71) => read_Mux_In(77),
read_Mux_In(70) => read_Mux_In(78),
read_Mux_In(69) => read_Mux_In(79),
read_Mux_In(68) => read_Mux_In(80),
read_Mux_In(67) => read_Mux_In(81),
read_Mux_In(66) => read_Mux_In(82),
read_Mux_In(65) => read_Mux_In(83),
read_Mux_In(64) => read_Mux_In(84),
read_Mux_In(63) => read_Mux_In(128),
read_Mux_In(62) => read_Mux_In(129),
read_Mux_In(61) => read_Mux_In(130),
read_Mux_In(60) => read_Mux_In(131),
read_Mux_In(59) => read_Mux_In(132),
read_Mux_In(58) => read_Mux_In(133),
read_Mux_In(57) => read_Mux_In(134),
read_Mux_In(56) => read_Mux_In(135),
read_Mux_In(55) => read_Mux_In(136),
read_Mux_In(54) => read_Mux_In(137),
read_Mux_In(53) => read_Mux_In(138),
read_Mux_In(52) => read_Mux_In(139),
read_Mux_In(51) => read_Mux_In(140),
read_Mux_In(50) => read_Mux_In(141),
read_Mux_In(49) => read_Mux_In(142),
read_Mux_In(48) => read_Mux_In(143),
read_Mux_In(47) => read_Mux_In(144),
read_Mux_In(46) => read_Mux_In(145),
read_Mux_In(45) => read_Mux_In(146),
read_Mux_In(44) => read_Mux_In(147),
read_Mux_In(43) => read_Mux_In(148),
read_Mux_In(42) => read_Mux_In(149),
read_Mux_In(41) => read_Mux_In(150),
read_Mux_In(40) => read_Mux_In(151),
read_Mux_In(39) => read_Mux_In(152),
read_Mux_In(38) => read_Mux_In(153),
read_Mux_In(37) => read_Mux_In(154),
read_Mux_In(36) => read_Mux_In(155),
read_Mux_In(35) => read_Mux_In(156),
read_Mux_In(34) => read_Mux_In(157),
read_Mux_In(33) => read_Mux_In(158),
read_Mux_In(32) => read_Mux_In(159),
read_Mux_In(31) => read_Mux_In(160),
read_Mux_In(30) => read_Mux_In(161),
read_Mux_In(29) => read_Mux_In(162),
read_Mux_In(28) => read_Mux_In(163),
read_Mux_In(27) => read_Mux_In(164),
read_Mux_In(26) => read_Mux_In(165),
read_Mux_In(25) => read_Mux_In(166),
read_Mux_In(24) => read_Mux_In(167),
read_Mux_In(23) => read_Mux_In(168),
read_Mux_In(22) => read_Mux_In(169),
read_Mux_In(21) => read_Mux_In(170),
read_Mux_In(20) => read_Mux_In(171),
read_Mux_In(19) => read_Mux_In(172),
read_Mux_In(18) => read_Mux_In(173),
read_Mux_In(17) => read_Mux_In(174),
read_Mux_In(16) => read_Mux_In(175),
read_Mux_In(15) => read_Mux_In(176),
read_Mux_In(14) => read_Mux_In(177),
read_Mux_In(13) => read_Mux_In(178),
read_Mux_In(12) => read_Mux_In(179),
read_Mux_In(11) => read_Mux_In(180),
read_Mux_In(10) => read_Mux_In(181),
read_Mux_In(9) => read_Mux_In(182),
read_Mux_In(8) => read_Mux_In(183),
read_Mux_In(7) => read_Mux_In(184),
read_Mux_In(6) => read_Mux_In(185),
read_Mux_In(5) => read_Mux_In(186),
read_Mux_In(4) => read_Mux_In(187),
read_Mux_In(3) => read_Mux_In(188),
read_Mux_In(2) => read_Mux_In(189),
read_Mux_In(1) => read_Mux_In(190),
read_Mux_In(0) => read_Mux_In(191),
read_done1 => \TIMER_CONTROL_I/read_done1\,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(2 downto 0) => s_axi_araddr(4 downto 2),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(2 downto 0) => s_axi_awaddr(4 downto 2),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
\s_axi_rdata_i_reg[0]\ => AXI4_LITE_I_n_103,
\s_axi_rdata_i_reg[0]_0\ => AXI4_LITE_I_n_104,
\s_axi_rdata_i_reg[10]\ => AXI4_LITE_I_n_102,
\s_axi_rdata_i_reg[11]\ => AXI4_LITE_I_n_27,
\s_axi_rdata_i_reg[12]\ => AXI4_LITE_I_n_4,
\s_axi_rdata_i_reg[13]\ => AXI4_LITE_I_n_5,
\s_axi_rdata_i_reg[14]\ => AXI4_LITE_I_n_6,
\s_axi_rdata_i_reg[15]\ => AXI4_LITE_I_n_7,
\s_axi_rdata_i_reg[16]\ => AXI4_LITE_I_n_8,
\s_axi_rdata_i_reg[17]\ => AXI4_LITE_I_n_9,
\s_axi_rdata_i_reg[18]\ => AXI4_LITE_I_n_10,
\s_axi_rdata_i_reg[19]\ => AXI4_LITE_I_n_11,
\s_axi_rdata_i_reg[20]\ => AXI4_LITE_I_n_12,
\s_axi_rdata_i_reg[21]\ => AXI4_LITE_I_n_13,
\s_axi_rdata_i_reg[22]\ => AXI4_LITE_I_n_14,
\s_axi_rdata_i_reg[23]\ => AXI4_LITE_I_n_15,
\s_axi_rdata_i_reg[24]\ => AXI4_LITE_I_n_16,
\s_axi_rdata_i_reg[25]\ => AXI4_LITE_I_n_17,
\s_axi_rdata_i_reg[26]\ => AXI4_LITE_I_n_18,
\s_axi_rdata_i_reg[27]\ => AXI4_LITE_I_n_19,
\s_axi_rdata_i_reg[28]\ => AXI4_LITE_I_n_20,
\s_axi_rdata_i_reg[29]\ => AXI4_LITE_I_n_21,
\s_axi_rdata_i_reg[30]\ => AXI4_LITE_I_n_22,
\s_axi_rdata_i_reg[31]\ => AXI4_LITE_I_n_23,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_rvalid_i_reg => AXI4_LITE_I_n_97,
s_axi_rvalid_i_reg_0 => AXI4_LITE_I_n_98,
s_axi_rvalid_i_reg_1 => AXI4_LITE_I_n_99,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wready => \^s_axi_wready\,
s_axi_wvalid => s_axi_wvalid
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
TC_CORE_I: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_tc_core
port map (
Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\,
Bus_RNW_reg_reg => AXI4_LITE_I_n_23,
Bus_RNW_reg_reg_0 => AXI4_LITE_I_n_22,
Bus_RNW_reg_reg_1 => AXI4_LITE_I_n_21,
Bus_RNW_reg_reg_10 => AXI4_LITE_I_n_12,
Bus_RNW_reg_reg_11 => AXI4_LITE_I_n_11,
Bus_RNW_reg_reg_12 => AXI4_LITE_I_n_10,
Bus_RNW_reg_reg_13 => AXI4_LITE_I_n_9,
Bus_RNW_reg_reg_14 => AXI4_LITE_I_n_8,
Bus_RNW_reg_reg_15 => AXI4_LITE_I_n_7,
Bus_RNW_reg_reg_16 => AXI4_LITE_I_n_6,
Bus_RNW_reg_reg_17 => AXI4_LITE_I_n_5,
Bus_RNW_reg_reg_18 => AXI4_LITE_I_n_4,
Bus_RNW_reg_reg_2 => AXI4_LITE_I_n_20,
Bus_RNW_reg_reg_3 => AXI4_LITE_I_n_19,
Bus_RNW_reg_reg_4 => AXI4_LITE_I_n_18,
Bus_RNW_reg_reg_5 => AXI4_LITE_I_n_17,
Bus_RNW_reg_reg_6 => AXI4_LITE_I_n_16,
Bus_RNW_reg_reg_7 => AXI4_LITE_I_n_15,
Bus_RNW_reg_reg_8 => AXI4_LITE_I_n_14,
Bus_RNW_reg_reg_9 => AXI4_LITE_I_n_13,
D(31) => ip2bus_data(0),
D(30) => ip2bus_data(1),
D(29) => ip2bus_data(2),
D(28) => ip2bus_data(3),
D(27) => ip2bus_data(4),
D(26) => ip2bus_data(5),
D(25) => ip2bus_data(6),
D(24) => ip2bus_data(7),
D(23) => ip2bus_data(8),
D(22) => ip2bus_data(9),
D(21) => ip2bus_data(10),
D(20) => ip2bus_data(11),
D(19) => ip2bus_data(12),
D(18) => ip2bus_data(13),
D(17) => ip2bus_data(14),
D(16) => ip2bus_data(15),
D(15) => ip2bus_data(16),
D(14) => ip2bus_data(17),
D(13) => ip2bus_data(18),
D(12) => ip2bus_data(19),
D(11) => ip2bus_data(20),
D(10) => ip2bus_data(21),
D(9) => ip2bus_data(22),
D(8) => ip2bus_data(23),
D(7) => ip2bus_data(24),
D(6) => ip2bus_data(25),
D(5) => ip2bus_data(26),
D(4) => ip2bus_data(27),
D(3) => ip2bus_data(28),
D(2) => ip2bus_data(29),
D(1) => ip2bus_data(30),
D(0) => ip2bus_data(31),
D_0 => \TIMER_CONTROL_I/D\,
D_1 => \COUNTER_0_I/D\,
D_2 => \GEN_SECOND_TIMER.COUNTER_1_I/D\,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ => AXI4_LITE_I_n_100,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\ => AXI4_LITE_I_n_102,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ => AXI4_LITE_I_n_95,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\ => AXI4_LITE_I_n_94,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1\ => AXI4_LITE_I_n_93,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_10\ => AXI4_LITE_I_n_84,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_11\ => AXI4_LITE_I_n_83,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_12\ => AXI4_LITE_I_n_82,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_13\ => AXI4_LITE_I_n_81,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_14\ => AXI4_LITE_I_n_80,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_15\ => AXI4_LITE_I_n_79,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_16\ => AXI4_LITE_I_n_78,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_17\ => AXI4_LITE_I_n_77,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_18\ => AXI4_LITE_I_n_76,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_19\ => AXI4_LITE_I_n_75,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_2\ => AXI4_LITE_I_n_92,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_20\ => AXI4_LITE_I_n_74,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_21\ => AXI4_LITE_I_n_73,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_22\ => AXI4_LITE_I_n_72,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_23\ => AXI4_LITE_I_n_71,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_24\ => AXI4_LITE_I_n_70,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_25\ => AXI4_LITE_I_n_69,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_26\ => AXI4_LITE_I_n_68,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_27\ => AXI4_LITE_I_n_67,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_28\ => AXI4_LITE_I_n_66,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_29\ => AXI4_LITE_I_n_65,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_3\ => AXI4_LITE_I_n_91,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_30\ => AXI4_LITE_I_n_105,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_31\ => AXI4_LITE_I_n_97,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_4\ => AXI4_LITE_I_n_90,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_5\ => AXI4_LITE_I_n_89,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_6\ => AXI4_LITE_I_n_88,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_7\ => AXI4_LITE_I_n_87,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_8\ => AXI4_LITE_I_n_86,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_9\ => AXI4_LITE_I_n_85,
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\ => AXI4_LITE_I_n_99,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ => AXI4_LITE_I_n_101,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\ => AXI4_LITE_I_n_98,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\ => AXI4_LITE_I_n_106,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_0\ => AXI4_LITE_I_n_103,
\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\ => AXI4_LITE_I_n_104,
\INFERRED_GEN.icount_out_reg[0]\(87) => read_Mux_In(20),
\INFERRED_GEN.icount_out_reg[0]\(86) => read_Mux_In(24),
\INFERRED_GEN.icount_out_reg[0]\(85) => read_Mux_In(56),
\INFERRED_GEN.icount_out_reg[0]\(84) => read_Mux_In(64),
\INFERRED_GEN.icount_out_reg[0]\(83) => read_Mux_In(65),
\INFERRED_GEN.icount_out_reg[0]\(82) => read_Mux_In(66),
\INFERRED_GEN.icount_out_reg[0]\(81) => read_Mux_In(67),
\INFERRED_GEN.icount_out_reg[0]\(80) => read_Mux_In(68),
\INFERRED_GEN.icount_out_reg[0]\(79) => read_Mux_In(69),
\INFERRED_GEN.icount_out_reg[0]\(78) => read_Mux_In(70),
\INFERRED_GEN.icount_out_reg[0]\(77) => read_Mux_In(71),
\INFERRED_GEN.icount_out_reg[0]\(76) => read_Mux_In(72),
\INFERRED_GEN.icount_out_reg[0]\(75) => read_Mux_In(73),
\INFERRED_GEN.icount_out_reg[0]\(74) => read_Mux_In(74),
\INFERRED_GEN.icount_out_reg[0]\(73) => read_Mux_In(75),
\INFERRED_GEN.icount_out_reg[0]\(72) => read_Mux_In(76),
\INFERRED_GEN.icount_out_reg[0]\(71) => read_Mux_In(77),
\INFERRED_GEN.icount_out_reg[0]\(70) => read_Mux_In(78),
\INFERRED_GEN.icount_out_reg[0]\(69) => read_Mux_In(79),
\INFERRED_GEN.icount_out_reg[0]\(68) => read_Mux_In(80),
\INFERRED_GEN.icount_out_reg[0]\(67) => read_Mux_In(81),
\INFERRED_GEN.icount_out_reg[0]\(66) => read_Mux_In(82),
\INFERRED_GEN.icount_out_reg[0]\(65) => read_Mux_In(83),
\INFERRED_GEN.icount_out_reg[0]\(64) => read_Mux_In(84),
\INFERRED_GEN.icount_out_reg[0]\(63) => read_Mux_In(128),
\INFERRED_GEN.icount_out_reg[0]\(62) => read_Mux_In(129),
\INFERRED_GEN.icount_out_reg[0]\(61) => read_Mux_In(130),
\INFERRED_GEN.icount_out_reg[0]\(60) => read_Mux_In(131),
\INFERRED_GEN.icount_out_reg[0]\(59) => read_Mux_In(132),
\INFERRED_GEN.icount_out_reg[0]\(58) => read_Mux_In(133),
\INFERRED_GEN.icount_out_reg[0]\(57) => read_Mux_In(134),
\INFERRED_GEN.icount_out_reg[0]\(56) => read_Mux_In(135),
\INFERRED_GEN.icount_out_reg[0]\(55) => read_Mux_In(136),
\INFERRED_GEN.icount_out_reg[0]\(54) => read_Mux_In(137),
\INFERRED_GEN.icount_out_reg[0]\(53) => read_Mux_In(138),
\INFERRED_GEN.icount_out_reg[0]\(52) => read_Mux_In(139),
\INFERRED_GEN.icount_out_reg[0]\(51) => read_Mux_In(140),
\INFERRED_GEN.icount_out_reg[0]\(50) => read_Mux_In(141),
\INFERRED_GEN.icount_out_reg[0]\(49) => read_Mux_In(142),
\INFERRED_GEN.icount_out_reg[0]\(48) => read_Mux_In(143),
\INFERRED_GEN.icount_out_reg[0]\(47) => read_Mux_In(144),
\INFERRED_GEN.icount_out_reg[0]\(46) => read_Mux_In(145),
\INFERRED_GEN.icount_out_reg[0]\(45) => read_Mux_In(146),
\INFERRED_GEN.icount_out_reg[0]\(44) => read_Mux_In(147),
\INFERRED_GEN.icount_out_reg[0]\(43) => read_Mux_In(148),
\INFERRED_GEN.icount_out_reg[0]\(42) => read_Mux_In(149),
\INFERRED_GEN.icount_out_reg[0]\(41) => read_Mux_In(150),
\INFERRED_GEN.icount_out_reg[0]\(40) => read_Mux_In(151),
\INFERRED_GEN.icount_out_reg[0]\(39) => read_Mux_In(152),
\INFERRED_GEN.icount_out_reg[0]\(38) => read_Mux_In(153),
\INFERRED_GEN.icount_out_reg[0]\(37) => read_Mux_In(154),
\INFERRED_GEN.icount_out_reg[0]\(36) => read_Mux_In(155),
\INFERRED_GEN.icount_out_reg[0]\(35) => read_Mux_In(156),
\INFERRED_GEN.icount_out_reg[0]\(34) => read_Mux_In(157),
\INFERRED_GEN.icount_out_reg[0]\(33) => read_Mux_In(158),
\INFERRED_GEN.icount_out_reg[0]\(32) => read_Mux_In(159),
\INFERRED_GEN.icount_out_reg[0]\(31) => read_Mux_In(160),
\INFERRED_GEN.icount_out_reg[0]\(30) => read_Mux_In(161),
\INFERRED_GEN.icount_out_reg[0]\(29) => read_Mux_In(162),
\INFERRED_GEN.icount_out_reg[0]\(28) => read_Mux_In(163),
\INFERRED_GEN.icount_out_reg[0]\(27) => read_Mux_In(164),
\INFERRED_GEN.icount_out_reg[0]\(26) => read_Mux_In(165),
\INFERRED_GEN.icount_out_reg[0]\(25) => read_Mux_In(166),
\INFERRED_GEN.icount_out_reg[0]\(24) => read_Mux_In(167),
\INFERRED_GEN.icount_out_reg[0]\(23) => read_Mux_In(168),
\INFERRED_GEN.icount_out_reg[0]\(22) => read_Mux_In(169),
\INFERRED_GEN.icount_out_reg[0]\(21) => read_Mux_In(170),
\INFERRED_GEN.icount_out_reg[0]\(20) => read_Mux_In(171),
\INFERRED_GEN.icount_out_reg[0]\(19) => read_Mux_In(172),
\INFERRED_GEN.icount_out_reg[0]\(18) => read_Mux_In(173),
\INFERRED_GEN.icount_out_reg[0]\(17) => read_Mux_In(174),
\INFERRED_GEN.icount_out_reg[0]\(16) => read_Mux_In(175),
\INFERRED_GEN.icount_out_reg[0]\(15) => read_Mux_In(176),
\INFERRED_GEN.icount_out_reg[0]\(14) => read_Mux_In(177),
\INFERRED_GEN.icount_out_reg[0]\(13) => read_Mux_In(178),
\INFERRED_GEN.icount_out_reg[0]\(12) => read_Mux_In(179),
\INFERRED_GEN.icount_out_reg[0]\(11) => read_Mux_In(180),
\INFERRED_GEN.icount_out_reg[0]\(10) => read_Mux_In(181),
\INFERRED_GEN.icount_out_reg[0]\(9) => read_Mux_In(182),
\INFERRED_GEN.icount_out_reg[0]\(8) => read_Mux_In(183),
\INFERRED_GEN.icount_out_reg[0]\(7) => read_Mux_In(184),
\INFERRED_GEN.icount_out_reg[0]\(6) => read_Mux_In(185),
\INFERRED_GEN.icount_out_reg[0]\(5) => read_Mux_In(186),
\INFERRED_GEN.icount_out_reg[0]\(4) => read_Mux_In(187),
\INFERRED_GEN.icount_out_reg[0]\(3) => read_Mux_In(188),
\INFERRED_GEN.icount_out_reg[0]\(2) => read_Mux_In(189),
\INFERRED_GEN.icount_out_reg[0]\(1) => read_Mux_In(190),
\INFERRED_GEN.icount_out_reg[0]\(0) => read_Mux_In(191),
\INFERRED_GEN.icount_out_reg[0]_0\ => AXI4_LITE_I_n_30,
\INFERRED_GEN.icount_out_reg[10]\ => AXI4_LITE_I_n_40,
\INFERRED_GEN.icount_out_reg[11]\ => AXI4_LITE_I_n_41,
\INFERRED_GEN.icount_out_reg[12]\ => AXI4_LITE_I_n_42,
\INFERRED_GEN.icount_out_reg[13]\ => AXI4_LITE_I_n_43,
\INFERRED_GEN.icount_out_reg[14]\ => AXI4_LITE_I_n_44,
\INFERRED_GEN.icount_out_reg[15]\ => AXI4_LITE_I_n_45,
\INFERRED_GEN.icount_out_reg[16]\ => AXI4_LITE_I_n_46,
\INFERRED_GEN.icount_out_reg[17]\ => AXI4_LITE_I_n_47,
\INFERRED_GEN.icount_out_reg[18]\ => AXI4_LITE_I_n_48,
\INFERRED_GEN.icount_out_reg[19]\ => AXI4_LITE_I_n_49,
\INFERRED_GEN.icount_out_reg[1]\ => AXI4_LITE_I_n_31,
\INFERRED_GEN.icount_out_reg[20]\ => AXI4_LITE_I_n_50,
\INFERRED_GEN.icount_out_reg[21]\ => AXI4_LITE_I_n_51,
\INFERRED_GEN.icount_out_reg[22]\ => AXI4_LITE_I_n_52,
\INFERRED_GEN.icount_out_reg[23]\ => AXI4_LITE_I_n_53,
\INFERRED_GEN.icount_out_reg[24]\ => AXI4_LITE_I_n_54,
\INFERRED_GEN.icount_out_reg[25]\ => AXI4_LITE_I_n_55,
\INFERRED_GEN.icount_out_reg[26]\ => AXI4_LITE_I_n_56,
\INFERRED_GEN.icount_out_reg[27]\ => AXI4_LITE_I_n_57,
\INFERRED_GEN.icount_out_reg[28]\ => AXI4_LITE_I_n_58,
\INFERRED_GEN.icount_out_reg[29]\ => AXI4_LITE_I_n_59,
\INFERRED_GEN.icount_out_reg[2]\ => AXI4_LITE_I_n_32,
\INFERRED_GEN.icount_out_reg[30]\ => AXI4_LITE_I_n_60,
\INFERRED_GEN.icount_out_reg[3]\ => AXI4_LITE_I_n_33,
\INFERRED_GEN.icount_out_reg[4]\ => AXI4_LITE_I_n_34,
\INFERRED_GEN.icount_out_reg[5]\ => AXI4_LITE_I_n_35,
\INFERRED_GEN.icount_out_reg[6]\ => AXI4_LITE_I_n_36,
\INFERRED_GEN.icount_out_reg[7]\ => AXI4_LITE_I_n_37,
\INFERRED_GEN.icount_out_reg[8]\ => AXI4_LITE_I_n_38,
\INFERRED_GEN.icount_out_reg[9]\ => AXI4_LITE_I_n_39,
\LOAD_REG_GEN[20].LOAD_REG_I\ => AXI4_LITE_I_n_27,
\TCSR0_GENERATE[24].TCSR0_FF_I\ => AXI4_LITE_I_n_28,
\TCSR1_GENERATE[24].TCSR1_FF_I\ => AXI4_LITE_I_n_29,
bus2ip_reset => bus2ip_reset,
bus2ip_wrce(1) => bus2ip_wrce(0),
bus2ip_wrce(0) => bus2ip_wrce(4),
\bus2ip_wrce__0\(0) => \bus2ip_wrce__0\(5),
capturetrig0 => capturetrig0,
capturetrig1 => capturetrig1,
freeze => freeze,
generateout0 => generateout0,
generateout1 => generateout1,
interrupt => interrupt,
pair0_Select => \TIMER_CONTROL_I/pair0_Select\,
pwm0 => pwm0,
read_done1 => \TIMER_CONTROL_I/read_done1\,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_wdata(9 downto 7) => s_axi_wdata(11 downto 9),
s_axi_wdata(6 downto 0) => s_axi_wdata(6 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
capturetrig0 : in STD_LOGIC;
capturetrig1 : in STD_LOGIC;
generateout0 : out STD_LOGIC;
generateout1 : out STD_LOGIC;
pwm0 : out STD_LOGIC;
interrupt : out STD_LOGIC;
freeze : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "zqynq_lab_1_design_axi_timer_0_0,axi_timer,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "axi_timer,Vivado 2017.2";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute C_COUNT_WIDTH : integer;
attribute C_COUNT_WIDTH of U0 : label is 32;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_GEN0_ASSERT : string;
attribute C_GEN0_ASSERT of U0 : label is "1'b1";
attribute C_GEN1_ASSERT : string;
attribute C_GEN1_ASSERT of U0 : label is "1'b1";
attribute C_ONE_TIMER_ONLY : integer;
attribute C_ONE_TIMER_ONLY of U0 : label is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of U0 : label is 5;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of U0 : label is 32;
attribute C_TRIG0_ASSERT : string;
attribute C_TRIG0_ASSERT of U0 : label is "1'b1";
attribute C_TRIG1_ASSERT : string;
attribute C_TRIG1_ASSERT of U0 : label is "1'b1";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_timer
port map (
capturetrig0 => capturetrig0,
capturetrig1 => capturetrig1,
freeze => freeze,
generateout0 => generateout0,
generateout1 => generateout1,
interrupt => interrupt,
pwm0 => pwm0,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(4 downto 0) => s_axi_araddr(4 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(4 downto 0) => s_axi_awaddr(4 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
| mit | 85c9fd25b0f78d53abe8de0d0edac910 | 0.576763 | 2.538023 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/techmap/maps/syncreg.vhd | 1 | 2,378 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: syncreg
-- File: syncreg.vhd
-- Author: Aeroflex Gaisler AB
-- Description: Technology wrapper for sync registers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity syncreg is
generic (
tech : integer := 0;
stages : integer range 1 to 5 := 2
);
port (
clk : in std_ulogic;
d : in std_ulogic;
q : out std_ulogic
);
end;
architecture tmap of syncreg is
begin
sync0 : if has_syncreg(tech) = 0 generate
--syncreg : block
-- signal c : std_logic_vector(stages-1 downto 0);
--begin
-- x0 : process(clk)
-- begin
-- if rising_edge(clk) then
-- for i in 0 to stages-1 loop
-- c(i) <= d;
-- if i /= 0 then c(i) = c(i-1); end if;
-- end loop;
-- end if;
-- end process;
-- q <= c(stages-1);
--end block syncreg;
syncreg : block
signal c : std_logic_vector(stages downto 0);
begin
c(0) <= d;
syncregs : for i in 1 to stages generate
dff : grdff
generic map(tech => tech)
port map(clk => clk, d => c(i-1), q => c(i));
end generate;
q <= c(stages);
end block syncreg;
end generate;
end;
| gpl-2.0 | 2b78b3d95be60b6a9651a1696589f77e | 0.555929 | 3.976589 | false | false | false | false |
VerkhovtsovPavel/BSUIR_Labs | Master/POCP/My_Designs/Stack/src/TestBench/onehot_TB.vhd | 1 | 1,477 | library ieee;
use ieee.STD_LOGIC_UNSIGNED.all;
use ieee.std_logic_1164.all;
library stack;
use stack.OneHotStack.all;
-- Add your library and packages declaration here ...
entity onehot_tb is
end onehot_tb;
architecture TB_ARCHITECTURE of onehot_tb is
-- Component declaration of the tested unit
component onehot
port(
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
Start : in STD_LOGIC;
Stop : out STD_LOGIC );
end component;
-- Stimulus signals - signals mapped to the input and inout ports of tested entity
signal CLK : STD_LOGIC;
signal RST : STD_LOGIC;
signal Start : STD_LOGIC;
-- Observed signals - signals mapped to the output ports of tested entity
signal Stop : STD_LOGIC;
constant CLK_period: time := 10 ns;
begin
-- Unit Under Test port map
UUT : onehot
port map (
CLK => CLK,
RST => RST,
Start => Start,
Stop => Stop
);
CLK_Process: process
begin
CLK <= '0';
wait for CLK_Period/2;
CLK <= '1';
wait for CLK_Period/2;
end process;
main: process
begin
rst <= '1';
wait for 1 * CLK_PERIOD;
rst <= '0';
start <= '1';
wait for 100 * CLK_PERIOD;
wait;
end process;
end TB_ARCHITECTURE;
configuration TESTBENCH_FOR_onehot of onehot_tb is
for TB_ARCHITECTURE
for UUT : onehot
use entity work.onehot(beh);
end for;
end for;
end TESTBENCH_FOR_onehot;
| mit | 03d716b1798f28907fc29c03b48a7376 | 0.61476 | 3.533493 | false | true | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_axi_timer_0_1/synth/zqynq_lab_1_design_axi_timer_0_1.vhd | 1 | 9,383 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_timer:2.0
-- IP Revision: 15
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_timer_v2_0_15;
USE axi_timer_v2_0_15.axi_timer;
ENTITY zqynq_lab_1_design_axi_timer_0_1 IS
PORT (
capturetrig0 : IN STD_LOGIC;
capturetrig1 : IN STD_LOGIC;
generateout0 : OUT STD_LOGIC;
generateout1 : OUT STD_LOGIC;
pwm0 : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
freeze : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC
);
END zqynq_lab_1_design_axi_timer_0_1;
ARCHITECTURE zqynq_lab_1_design_axi_timer_0_1_arch OF zqynq_lab_1_design_axi_timer_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF zqynq_lab_1_design_axi_timer_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT axi_timer IS
GENERIC (
C_FAMILY : STRING;
C_COUNT_WIDTH : INTEGER;
C_ONE_TIMER_ONLY : INTEGER;
C_TRIG0_ASSERT : STD_LOGIC;
C_TRIG1_ASSERT : STD_LOGIC;
C_GEN0_ASSERT : STD_LOGIC;
C_GEN1_ASSERT : STD_LOGIC;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER
);
PORT (
capturetrig0 : IN STD_LOGIC;
capturetrig1 : IN STD_LOGIC;
generateout0 : OUT STD_LOGIC;
generateout1 : OUT STD_LOGIC;
pwm0 : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
freeze : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC
);
END COMPONENT axi_timer;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF zqynq_lab_1_design_axi_timer_0_1_arch: ARCHITECTURE IS "axi_timer,Vivado 2017.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF zqynq_lab_1_design_axi_timer_0_1_arch : ARCHITECTURE IS "zqynq_lab_1_design_axi_timer_0_1,axi_timer,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF zqynq_lab_1_design_axi_timer_0_1_arch: ARCHITECTURE IS "zqynq_lab_1_design_axi_timer_0_1,axi_timer,{x_ipProduct=Vivado 2017.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_timer,x_ipVersion=2.0,x_ipCoreRevision=15,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_COUNT_WIDTH=32,C_ONE_TIMER_ONLY=0,C_TRIG0_ASSERT=1,C_TRIG1_ASSERT=1,C_GEN0_ASSERT=1,C_GEN1_ASSERT=1,C_S_AXI_DATA_WIDTH=32,C_S_AXI_ADDR_WIDTH=5}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF interrupt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 INTERRUPT INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_RST RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
BEGIN
U0 : axi_timer
GENERIC MAP (
C_FAMILY => "zynq",
C_COUNT_WIDTH => 32,
C_ONE_TIMER_ONLY => 0,
C_TRIG0_ASSERT => '1',
C_TRIG1_ASSERT => '1',
C_GEN0_ASSERT => '1',
C_GEN1_ASSERT => '1',
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ADDR_WIDTH => 5
)
PORT MAP (
capturetrig0 => capturetrig0,
capturetrig1 => capturetrig1,
generateout0 => generateout0,
generateout1 => generateout1,
pwm0 => pwm0,
interrupt => interrupt,
freeze => freeze,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready
);
END zqynq_lab_1_design_axi_timer_0_1_arch;
| mit | 5b3d1c9366374bae74d8dd4f8c879688 | 0.692529 | 3.25234 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-gr-cpci-xc4v/config.vhd | 1 | 8,219 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := virtex4;
constant CFG_MEMTECH : integer := virtex4;
constant CFG_PADTECH : integer := virtex4;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := virtex4;
constant CFG_CLKMUL : integer := (6);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (4);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 16;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 1;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 1;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2;
constant CFG_ATBSZ : integer := 2;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0059#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000059#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 1;
constant CFG_MCTRL_SEPBUS : integer := 1;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 1;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- CAN 2.0 interface
constant CFG_CAN : integer := 0;
constant CFG_CAN_NUM : integer := 1;
constant CFG_CANIO : integer := 16#0#;
constant CFG_CANIRQ : integer := 0;
constant CFG_CANSEPIRQ: integer := 0;
constant CFG_CAN_SYNCRST : integer := 0;
constant CFG_CANFT : integer := 0;
-- Spacewire interface
constant CFG_SPW_EN : integer := 0;
constant CFG_SPW_NUM : integer := 1;
constant CFG_SPW_AHBFIFO : integer := 4;
constant CFG_SPW_RXFIFO : integer := 16;
constant CFG_SPW_RMAP : integer := 0;
constant CFG_SPW_RMAPBUF : integer := 4;
constant CFG_SPW_RMAPCRC : integer := 0;
constant CFG_SPW_NETLIST : integer := 0;
constant CFG_SPW_FT : integer := 0;
constant CFG_SPW_GRSPW : integer := 2;
constant CFG_SPW_RXUNAL : integer := 0;
constant CFG_SPW_DMACHAN : integer := 1;
constant CFG_SPW_PORTS : integer := 1;
constant CFG_SPW_INPUT : integer := 2;
constant CFG_SPW_OUTPUT : integer := 0;
constant CFG_SPW_RTSAME : integer := 0;
-- PCI interface
constant CFG_PCI : integer := 3;
constant CFG_PCIVID : integer := 16#1AC8#;
constant CFG_PCIDID : integer := 16#0054#;
constant CFG_PCIDEPTH : integer := 8;
constant CFG_PCI_MTF : integer := 1;
-- GRPCI2 interface
constant CFG_GRPCI2_MASTER : integer := 0;
constant CFG_GRPCI2_TARGET : integer := 0;
constant CFG_GRPCI2_DMA : integer := 0;
constant CFG_GRPCI2_VID : integer := 16#0#;
constant CFG_GRPCI2_DID : integer := 16#0#;
constant CFG_GRPCI2_CLASS : integer := 16#0#;
constant CFG_GRPCI2_RID : integer := 16#0#;
constant CFG_GRPCI2_CAP : integer := 16#40#;
constant CFG_GRPCI2_NCAP : integer := 16#0#;
constant CFG_GRPCI2_BAR0 : integer := 0;
constant CFG_GRPCI2_BAR1 : integer := 0;
constant CFG_GRPCI2_BAR2 : integer := 0;
constant CFG_GRPCI2_BAR3 : integer := 0;
constant CFG_GRPCI2_BAR4 : integer := 0;
constant CFG_GRPCI2_BAR5 : integer := 0;
constant CFG_GRPCI2_FDEPTH : integer := 3;
constant CFG_GRPCI2_FCOUNT : integer := 2;
constant CFG_GRPCI2_ENDIAN : integer := 0;
constant CFG_GRPCI2_DEVINT : integer := 1;
constant CFG_GRPCI2_DEVINTMSK : integer := 16#0#;
constant CFG_GRPCI2_HOSTINT : integer := 1;
constant CFG_GRPCI2_HOSTINTMSK: integer := 16#0#;
constant CFG_GRPCI2_TRACE : integer := 1024;
constant CFG_GRPCI2_TRACEAPB : integer := 0;
constant CFG_GRPCI2_BYPASS : integer := 0;
constant CFG_GRPCI2_EXTCFG : integer := (0);
-- PCI arbiter
constant CFG_PCI_ARB : integer := 1;
constant CFG_PCI_ARBAPB : integer := 1;
constant CFG_PCI_ARB_NGNT : integer := (4);
-- PCI trace buffer
constant CFG_PCITBUFEN: integer := 0;
constant CFG_PCITBUF : integer := 256;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- UART 2
constant CFG_UART2_ENABLE : integer := 1;
constant CFG_UART2_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (3);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 1;
constant CFG_GPT_WDOG : integer := 16#FFFFFF#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#FE#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-2.0 | 665618d4085fe70b620e62bc036e0eb7 | 0.651417 | 3.545729 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/ug871-design-files/Interface_Synthesis/lab3/array_io_prj/solution2/syn/vhdl/array_io.vhd | 1 | 79,836 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity array_io is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
d_o_din : OUT STD_LOGIC_VECTOR (15 downto 0);
d_o_full_n : IN STD_LOGIC;
d_o_write : OUT STD_LOGIC;
d_i_address0 : OUT STD_LOGIC_VECTOR (4 downto 0);
d_i_ce0 : OUT STD_LOGIC;
d_i_q0 : IN STD_LOGIC_VECTOR (15 downto 0);
d_i_address1 : OUT STD_LOGIC_VECTOR (4 downto 0);
d_i_ce1 : OUT STD_LOGIC;
d_i_q1 : IN STD_LOGIC_VECTOR (15 downto 0) );
end;
architecture behav of array_io is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"array_io,hls_ip_2017_2,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7k160tfbg484-1,HLS_INPUT_CLOCK=4.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=3.361000,HLS_SYN_LAT=33,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=3962,HLS_SYN_LUT=2021}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000000000000000000001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000000000000000000010";
constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000000000000000000100";
constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000000000000000001000";
constant ap_ST_fsm_state5 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000000000000000010000";
constant ap_ST_fsm_state6 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000000000000000100000";
constant ap_ST_fsm_state7 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000000000000001000000";
constant ap_ST_fsm_state8 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000000000000010000000";
constant ap_ST_fsm_state9 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000000000000100000000";
constant ap_ST_fsm_state10 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000000000001000000000";
constant ap_ST_fsm_state11 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000000000010000000000";
constant ap_ST_fsm_state12 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000000000100000000000";
constant ap_ST_fsm_state13 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000000001000000000000";
constant ap_ST_fsm_state14 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000000010000000000000";
constant ap_ST_fsm_state15 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000000100000000000000";
constant ap_ST_fsm_state16 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000001000000000000000";
constant ap_ST_fsm_state17 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000010000000000000000";
constant ap_ST_fsm_state18 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000100000000000000000";
constant ap_ST_fsm_state19 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000001000000000000000000";
constant ap_ST_fsm_state20 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000010000000000000000000";
constant ap_ST_fsm_state21 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000100000000000000000000";
constant ap_ST_fsm_state22 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000001000000000000000000000";
constant ap_ST_fsm_state23 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000010000000000000000000000";
constant ap_ST_fsm_state24 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000100000000000000000000000";
constant ap_ST_fsm_state25 : STD_LOGIC_VECTOR (33 downto 0) := "0000000001000000000000000000000000";
constant ap_ST_fsm_state26 : STD_LOGIC_VECTOR (33 downto 0) := "0000000010000000000000000000000000";
constant ap_ST_fsm_state27 : STD_LOGIC_VECTOR (33 downto 0) := "0000000100000000000000000000000000";
constant ap_ST_fsm_state28 : STD_LOGIC_VECTOR (33 downto 0) := "0000001000000000000000000000000000";
constant ap_ST_fsm_state29 : STD_LOGIC_VECTOR (33 downto 0) := "0000010000000000000000000000000000";
constant ap_ST_fsm_state30 : STD_LOGIC_VECTOR (33 downto 0) := "0000100000000000000000000000000000";
constant ap_ST_fsm_state31 : STD_LOGIC_VECTOR (33 downto 0) := "0001000000000000000000000000000000";
constant ap_ST_fsm_state32 : STD_LOGIC_VECTOR (33 downto 0) := "0010000000000000000000000000000000";
constant ap_ST_fsm_state33 : STD_LOGIC_VECTOR (33 downto 0) := "0100000000000000000000000000000000";
constant ap_ST_fsm_state34 : STD_LOGIC_VECTOR (33 downto 0) := "1000000000000000000000000000000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011";
constant ap_const_lv32_C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001100";
constant ap_const_lv32_D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001101";
constant ap_const_lv32_E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001110";
constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
constant ap_const_lv32_11 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010001";
constant ap_const_lv32_12 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010010";
constant ap_const_lv32_13 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010011";
constant ap_const_lv32_14 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010100";
constant ap_const_lv32_15 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010101";
constant ap_const_lv32_16 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010110";
constant ap_const_lv32_17 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010111";
constant ap_const_lv32_18 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011000";
constant ap_const_lv32_19 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011001";
constant ap_const_lv32_1A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011010";
constant ap_const_lv32_1B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011011";
constant ap_const_lv32_1C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011100";
constant ap_const_lv32_1D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011101";
constant ap_const_lv32_1E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011110";
constant ap_const_lv32_1F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011111";
constant ap_const_lv32_20 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100000";
constant ap_const_lv32_21 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100001";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_boolean_1 : BOOLEAN := true;
signal ap_CS_fsm : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000000000000000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal acc_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal acc_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal acc_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal acc_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal acc_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal acc_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal acc_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal acc_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal d_o_blk_n : STD_LOGIC;
signal ap_CS_fsm_state3 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state3 : signal is "none";
signal ap_CS_fsm_state4 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state4 : signal is "none";
signal ap_CS_fsm_state5 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state5 : signal is "none";
signal ap_CS_fsm_state6 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state6 : signal is "none";
signal ap_CS_fsm_state7 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state7 : signal is "none";
signal ap_CS_fsm_state8 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state8 : signal is "none";
signal ap_CS_fsm_state9 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state9 : signal is "none";
signal ap_CS_fsm_state10 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state10 : signal is "none";
signal ap_CS_fsm_state11 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state11 : signal is "none";
signal ap_CS_fsm_state12 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state12 : signal is "none";
signal ap_CS_fsm_state13 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state13 : signal is "none";
signal ap_CS_fsm_state14 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state14 : signal is "none";
signal ap_CS_fsm_state15 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state15 : signal is "none";
signal ap_CS_fsm_state16 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state16 : signal is "none";
signal ap_CS_fsm_state17 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state17 : signal is "none";
signal ap_CS_fsm_state18 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state18 : signal is "none";
signal ap_CS_fsm_state19 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state19 : signal is "none";
signal ap_CS_fsm_state20 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state20 : signal is "none";
signal ap_CS_fsm_state21 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state21 : signal is "none";
signal ap_CS_fsm_state22 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state22 : signal is "none";
signal ap_CS_fsm_state23 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state23 : signal is "none";
signal ap_CS_fsm_state24 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state24 : signal is "none";
signal ap_CS_fsm_state25 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state25 : signal is "none";
signal ap_CS_fsm_state26 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state26 : signal is "none";
signal ap_CS_fsm_state27 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state27 : signal is "none";
signal ap_CS_fsm_state28 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state28 : signal is "none";
signal ap_CS_fsm_state29 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state29 : signal is "none";
signal ap_CS_fsm_state30 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state30 : signal is "none";
signal ap_CS_fsm_state31 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state31 : signal is "none";
signal ap_CS_fsm_state32 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state32 : signal is "none";
signal ap_CS_fsm_state33 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state33 : signal is "none";
signal ap_CS_fsm_state34 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state34 : signal is "none";
signal reg_406 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_CS_fsm_state2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
signal reg_410 : STD_LOGIC_VECTOR (15 downto 0);
signal reg_414 : STD_LOGIC_VECTOR (15 downto 0);
signal reg_418 : STD_LOGIC_VECTOR (15 downto 0);
signal reg_422 : STD_LOGIC_VECTOR (15 downto 0);
signal reg_426 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_8_fu_438_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_8_reg_1080 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_1_fu_453_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_1_reg_1100 : STD_LOGIC_VECTOR (15 downto 0);
signal d_i_load_4_reg_1105 : STD_LOGIC_VECTOR (15 downto 0);
signal d_i_load_5_reg_1111 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_2_fu_468_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_2_reg_1132 : STD_LOGIC_VECTOR (15 downto 0);
signal d_i_load_6_reg_1137 : STD_LOGIC_VECTOR (15 downto 0);
signal d_i_load_7_reg_1143 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_3_fu_483_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_3_reg_1164 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_4_fu_498_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_4_reg_1184 : STD_LOGIC_VECTOR (15 downto 0);
signal d_i_load_10_reg_1189 : STD_LOGIC_VECTOR (15 downto 0);
signal d_i_load_11_reg_1195 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_5_fu_512_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_5_reg_1216 : STD_LOGIC_VECTOR (15 downto 0);
signal d_i_load_12_reg_1221 : STD_LOGIC_VECTOR (15 downto 0);
signal d_i_load_13_reg_1227 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_6_fu_526_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_6_reg_1248 : STD_LOGIC_VECTOR (15 downto 0);
signal d_i_load_14_reg_1253 : STD_LOGIC_VECTOR (15 downto 0);
signal d_i_load_15_reg_1259 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_7_fu_540_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_7_reg_1280 : STD_LOGIC_VECTOR (15 downto 0);
signal d_i_load_16_reg_1285 : STD_LOGIC_VECTOR (15 downto 0);
signal d_i_load_17_reg_1291 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_8_fu_546_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_8_reg_1307 : STD_LOGIC_VECTOR (15 downto 0);
signal d_i_load_18_reg_1312 : STD_LOGIC_VECTOR (15 downto 0);
signal d_i_load_19_reg_1318 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_9_fu_552_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_9_reg_1334 : STD_LOGIC_VECTOR (15 downto 0);
signal d_i_load_20_reg_1339 : STD_LOGIC_VECTOR (15 downto 0);
signal d_i_load_21_reg_1345 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_s_fu_558_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_s_reg_1361 : STD_LOGIC_VECTOR (15 downto 0);
signal d_i_load_22_reg_1366 : STD_LOGIC_VECTOR (15 downto 0);
signal d_i_load_23_reg_1372 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_10_fu_563_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_10_reg_1388 : STD_LOGIC_VECTOR (15 downto 0);
signal d_i_load_24_reg_1393 : STD_LOGIC_VECTOR (15 downto 0);
signal d_i_load_25_reg_1399 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_11_fu_576_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_11_reg_1415 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_15_fu_584_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_15_reg_1420 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_16_fu_591_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_16_reg_1426 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp2_fu_608_p2 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp2_reg_1432 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp5_fu_627_p2 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp5_reg_1437 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_1_12_fu_647_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_12_reg_1452 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_17_fu_655_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_17_reg_1457 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_18_fu_662_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_18_reg_1463 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp8_fu_720_p2 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp8_reg_1469 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp11_fu_740_p2 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp11_reg_1474 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_1_13_fu_760_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_13_reg_1489 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_19_fu_768_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_19_reg_1494 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_20_fu_775_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_20_reg_1500 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp14_fu_833_p2 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp14_reg_1506 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp17_fu_853_p2 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp17_reg_1511 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_1_21_fu_879_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_21_reg_1516 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_22_fu_886_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_22_reg_1522 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp20_fu_945_p2 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp20_reg_1528 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp23_fu_965_p2 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp23_reg_1533 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_1_23_fu_977_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_23_reg_1538 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_24_fu_1021_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_24_reg_1543 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_25_fu_1025_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_25_reg_1548 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_26_fu_1030_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_26_reg_1553 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_27_fu_1035_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_27_reg_1558 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_28_fu_1040_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_28_reg_1563 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_29_fu_1045_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_29_reg_1568 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_30_fu_1050_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_30_reg_1573 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_14_fu_871_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal temp_s_fu_674_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_1_fu_694_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_2_fu_787_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_3_fu_807_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_4_fu_899_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_5_fu_919_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_6_fu_989_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_7_fu_1009_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_1_fu_434_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_9_fu_449_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_10_fu_464_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_11_fu_479_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_12_fu_494_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_13_fu_508_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_14_fu_522_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_15_fu_536_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_16_cast_fu_581_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_24_cast_fu_595_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp3_fu_598_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp3_cast_fu_604_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_8_cast_fu_568_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_17_cast_fu_588_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_25_cast_fu_614_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp6_fu_617_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp6_cast_fu_623_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_9_cast_fu_572_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_fu_633_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp2_cast_fu_671_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp1_fu_666_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_s_fu_637_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp5_cast_fu_691_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp4_fu_686_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_18_cast_fu_652_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_26_cast_fu_706_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp9_fu_710_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp9_cast_fu_716_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_10_cast_fu_641_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_19_cast_fu_659_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_27_cast_fu_726_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp12_fu_730_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp12_cast_fu_736_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_11_cast_fu_644_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_2_fu_746_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp8_cast_fu_784_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp7_fu_779_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_3_fu_750_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp11_cast_fu_804_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp10_fu_799_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_cast_fu_765_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_28_cast_fu_819_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp15_fu_823_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp15_cast_fu_829_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_12_cast_fu_754_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_21_cast_fu_772_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_29_cast_fu_839_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp18_fu_843_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp18_cast_fu_849_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_13_cast_fu_757_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_4_fu_859_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp14_cast_fu_896_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp13_fu_891_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_5_fu_862_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp17_cast_fu_916_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp16_fu_911_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_22_cast_fu_876_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_30_cast_fu_931_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp21_fu_935_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp21_cast_fu_941_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_14_cast_fu_865_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_23_cast_fu_883_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_31_cast_fu_951_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp24_fu_955_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp24_cast_fu_961_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_15_cast_fu_868_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_6_fu_971_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp20_cast_fu_986_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp19_fu_981_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_7_fu_974_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp23_cast_fu_1006_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp22_fu_1001_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (33 downto 0);
begin
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state16) and (d_o_full_n = ap_const_logic_1))) then
acc_0 <= temp_s_fu_674_p2;
acc_1 <= temp_1_fu_694_p2;
tmp11_reg_1474 <= tmp11_fu_740_p2;
tmp8_reg_1469 <= tmp8_fu_720_p2;
tmp_1_12_reg_1452 <= tmp_1_12_fu_647_p2;
tmp_1_17_reg_1457 <= tmp_1_17_fu_655_p2;
tmp_1_18_reg_1463 <= tmp_1_18_fu_662_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state17) and (d_o_full_n = ap_const_logic_1))) then
acc_2 <= temp_2_fu_787_p2;
acc_3 <= temp_3_fu_807_p2;
tmp14_reg_1506 <= tmp14_fu_833_p2;
tmp17_reg_1511 <= tmp17_fu_853_p2;
tmp_1_13_reg_1489 <= tmp_1_13_fu_760_p2;
tmp_1_19_reg_1494 <= tmp_1_19_fu_768_p2;
tmp_1_20_reg_1500 <= tmp_1_20_fu_775_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state18) and (d_o_full_n = ap_const_logic_1))) then
acc_4 <= temp_4_fu_899_p2;
acc_5 <= temp_5_fu_919_p2;
tmp20_reg_1528 <= tmp20_fu_945_p2;
tmp23_reg_1533 <= tmp23_fu_965_p2;
tmp_1_21_reg_1516 <= tmp_1_21_fu_879_p2;
tmp_1_22_reg_1522 <= tmp_1_22_fu_886_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state19) and (d_o_full_n = ap_const_logic_1))) then
acc_6 <= temp_6_fu_989_p2;
acc_7 <= temp_7_fu_1009_p2;
tmp_1_23_reg_1538 <= tmp_1_23_fu_977_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state7) and (d_o_full_n = ap_const_logic_1))) then
d_i_load_10_reg_1189 <= d_i_q0;
d_i_load_11_reg_1195 <= d_i_q1;
tmp_1_4_reg_1184 <= tmp_1_4_fu_498_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state8) and (d_o_full_n = ap_const_logic_1))) then
d_i_load_12_reg_1221 <= d_i_q0;
d_i_load_13_reg_1227 <= d_i_q1;
tmp_1_5_reg_1216 <= tmp_1_5_fu_512_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state9) and (d_o_full_n = ap_const_logic_1))) then
d_i_load_14_reg_1253 <= d_i_q0;
d_i_load_15_reg_1259 <= d_i_q1;
tmp_1_6_reg_1248 <= tmp_1_6_fu_526_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state10) and (d_o_full_n = ap_const_logic_1))) then
d_i_load_16_reg_1285 <= d_i_q0;
d_i_load_17_reg_1291 <= d_i_q1;
tmp_1_7_reg_1280 <= tmp_1_7_fu_540_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state11) and (d_o_full_n = ap_const_logic_1))) then
d_i_load_18_reg_1312 <= d_i_q0;
d_i_load_19_reg_1318 <= d_i_q1;
tmp_1_8_reg_1307 <= tmp_1_8_fu_546_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state12) and (d_o_full_n = ap_const_logic_1))) then
d_i_load_20_reg_1339 <= d_i_q0;
d_i_load_21_reg_1345 <= d_i_q1;
tmp_1_9_reg_1334 <= tmp_1_9_fu_552_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state13) and (d_o_full_n = ap_const_logic_1))) then
d_i_load_22_reg_1366 <= d_i_q0;
d_i_load_23_reg_1372 <= d_i_q1;
tmp_1_s_reg_1361 <= tmp_1_s_fu_558_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state14) and (d_o_full_n = ap_const_logic_1))) then
d_i_load_24_reg_1393 <= d_i_q0;
d_i_load_25_reg_1399 <= d_i_q1;
tmp_1_10_reg_1388 <= tmp_1_10_fu_563_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state4) and (d_o_full_n = ap_const_logic_1))) then
d_i_load_4_reg_1105 <= d_i_q0;
d_i_load_5_reg_1111 <= d_i_q1;
tmp_1_1_reg_1100 <= tmp_1_1_fu_453_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state5) and (d_o_full_n = ap_const_logic_1))) then
d_i_load_6_reg_1137 <= d_i_q0;
d_i_load_7_reg_1143 <= d_i_q1;
tmp_1_2_reg_1132 <= tmp_1_2_fu_468_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state2) or ((ap_const_logic_1 = ap_CS_fsm_state16) and (d_o_full_n = ap_const_logic_1)))) then
reg_406 <= d_i_q0;
reg_410 <= d_i_q1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_const_logic_1 = ap_CS_fsm_state3) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state17) and (d_o_full_n = ap_const_logic_1)))) then
reg_414 <= d_i_q0;
reg_418 <= d_i_q1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_const_logic_1 = ap_CS_fsm_state6) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state15) and (d_o_full_n = ap_const_logic_1)))) then
reg_422 <= d_i_q0;
reg_426 <= d_i_q1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state15) and (d_o_full_n = ap_const_logic_1))) then
tmp2_reg_1432 <= tmp2_fu_608_p2;
tmp5_reg_1437 <= tmp5_fu_627_p2;
tmp_1_11_reg_1415 <= tmp_1_11_fu_576_p2;
tmp_1_15_reg_1420 <= tmp_1_15_fu_584_p2;
tmp_1_16_reg_1426 <= tmp_1_16_fu_591_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state20) and (d_o_full_n = ap_const_logic_1))) then
tmp_1_24_reg_1543 <= tmp_1_24_fu_1021_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state21) and (d_o_full_n = ap_const_logic_1))) then
tmp_1_25_reg_1548 <= tmp_1_25_fu_1025_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state22) and (d_o_full_n = ap_const_logic_1))) then
tmp_1_26_reg_1553 <= tmp_1_26_fu_1030_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state23) and (d_o_full_n = ap_const_logic_1))) then
tmp_1_27_reg_1558 <= tmp_1_27_fu_1035_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state24) and (d_o_full_n = ap_const_logic_1))) then
tmp_1_28_reg_1563 <= tmp_1_28_fu_1040_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state25) and (d_o_full_n = ap_const_logic_1))) then
tmp_1_29_reg_1568 <= tmp_1_29_fu_1045_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state26) and (d_o_full_n = ap_const_logic_1))) then
tmp_1_30_reg_1573 <= tmp_1_30_fu_1050_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state6) and (d_o_full_n = ap_const_logic_1))) then
tmp_1_3_reg_1164 <= tmp_1_3_fu_483_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state3) and (d_o_full_n = ap_const_logic_1))) then
tmp_8_reg_1080 <= tmp_8_fu_438_p2;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, d_o_full_n, ap_CS_fsm_state3, ap_CS_fsm_state4, ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, ap_CS_fsm_state8, ap_CS_fsm_state9, ap_CS_fsm_state10, ap_CS_fsm_state11, ap_CS_fsm_state12, ap_CS_fsm_state13, ap_CS_fsm_state14, ap_CS_fsm_state15, ap_CS_fsm_state16, ap_CS_fsm_state17, ap_CS_fsm_state18, ap_CS_fsm_state19, ap_CS_fsm_state20, ap_CS_fsm_state21, ap_CS_fsm_state22, ap_CS_fsm_state23, ap_CS_fsm_state24, ap_CS_fsm_state25, ap_CS_fsm_state26, ap_CS_fsm_state27, ap_CS_fsm_state28, ap_CS_fsm_state29, ap_CS_fsm_state30, ap_CS_fsm_state31, ap_CS_fsm_state32, ap_CS_fsm_state33, ap_CS_fsm_state34)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
ap_NS_fsm <= ap_ST_fsm_state3;
when ap_ST_fsm_state3 =>
if (((ap_const_logic_1 = ap_CS_fsm_state3) and (d_o_full_n = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state4;
else
ap_NS_fsm <= ap_ST_fsm_state3;
end if;
when ap_ST_fsm_state4 =>
if (((ap_const_logic_1 = ap_CS_fsm_state4) and (d_o_full_n = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state5;
else
ap_NS_fsm <= ap_ST_fsm_state4;
end if;
when ap_ST_fsm_state5 =>
if (((ap_const_logic_1 = ap_CS_fsm_state5) and (d_o_full_n = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state6;
else
ap_NS_fsm <= ap_ST_fsm_state5;
end if;
when ap_ST_fsm_state6 =>
if (((ap_const_logic_1 = ap_CS_fsm_state6) and (d_o_full_n = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state7;
else
ap_NS_fsm <= ap_ST_fsm_state6;
end if;
when ap_ST_fsm_state7 =>
if (((ap_const_logic_1 = ap_CS_fsm_state7) and (d_o_full_n = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state8;
else
ap_NS_fsm <= ap_ST_fsm_state7;
end if;
when ap_ST_fsm_state8 =>
if (((ap_const_logic_1 = ap_CS_fsm_state8) and (d_o_full_n = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state9;
else
ap_NS_fsm <= ap_ST_fsm_state8;
end if;
when ap_ST_fsm_state9 =>
if (((ap_const_logic_1 = ap_CS_fsm_state9) and (d_o_full_n = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state10;
else
ap_NS_fsm <= ap_ST_fsm_state9;
end if;
when ap_ST_fsm_state10 =>
if (((ap_const_logic_1 = ap_CS_fsm_state10) and (d_o_full_n = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state11;
else
ap_NS_fsm <= ap_ST_fsm_state10;
end if;
when ap_ST_fsm_state11 =>
if (((ap_const_logic_1 = ap_CS_fsm_state11) and (d_o_full_n = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state12;
else
ap_NS_fsm <= ap_ST_fsm_state11;
end if;
when ap_ST_fsm_state12 =>
if (((ap_const_logic_1 = ap_CS_fsm_state12) and (d_o_full_n = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state13;
else
ap_NS_fsm <= ap_ST_fsm_state12;
end if;
when ap_ST_fsm_state13 =>
if (((ap_const_logic_1 = ap_CS_fsm_state13) and (d_o_full_n = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state14;
else
ap_NS_fsm <= ap_ST_fsm_state13;
end if;
when ap_ST_fsm_state14 =>
if (((ap_const_logic_1 = ap_CS_fsm_state14) and (d_o_full_n = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state15;
else
ap_NS_fsm <= ap_ST_fsm_state14;
end if;
when ap_ST_fsm_state15 =>
if (((ap_const_logic_1 = ap_CS_fsm_state15) and (d_o_full_n = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state16;
else
ap_NS_fsm <= ap_ST_fsm_state15;
end if;
when ap_ST_fsm_state16 =>
if (((ap_const_logic_1 = ap_CS_fsm_state16) and (d_o_full_n = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state17;
else
ap_NS_fsm <= ap_ST_fsm_state16;
end if;
when ap_ST_fsm_state17 =>
if (((ap_const_logic_1 = ap_CS_fsm_state17) and (d_o_full_n = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state18;
else
ap_NS_fsm <= ap_ST_fsm_state17;
end if;
when ap_ST_fsm_state18 =>
if (((ap_const_logic_1 = ap_CS_fsm_state18) and (d_o_full_n = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state19;
else
ap_NS_fsm <= ap_ST_fsm_state18;
end if;
when ap_ST_fsm_state19 =>
if (((ap_const_logic_1 = ap_CS_fsm_state19) and (d_o_full_n = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state20;
else
ap_NS_fsm <= ap_ST_fsm_state19;
end if;
when ap_ST_fsm_state20 =>
if (((ap_const_logic_1 = ap_CS_fsm_state20) and (d_o_full_n = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state21;
else
ap_NS_fsm <= ap_ST_fsm_state20;
end if;
when ap_ST_fsm_state21 =>
if (((ap_const_logic_1 = ap_CS_fsm_state21) and (d_o_full_n = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state22;
else
ap_NS_fsm <= ap_ST_fsm_state21;
end if;
when ap_ST_fsm_state22 =>
if (((ap_const_logic_1 = ap_CS_fsm_state22) and (d_o_full_n = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state23;
else
ap_NS_fsm <= ap_ST_fsm_state22;
end if;
when ap_ST_fsm_state23 =>
if (((ap_const_logic_1 = ap_CS_fsm_state23) and (d_o_full_n = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state24;
else
ap_NS_fsm <= ap_ST_fsm_state23;
end if;
when ap_ST_fsm_state24 =>
if (((ap_const_logic_1 = ap_CS_fsm_state24) and (d_o_full_n = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state25;
else
ap_NS_fsm <= ap_ST_fsm_state24;
end if;
when ap_ST_fsm_state25 =>
if (((ap_const_logic_1 = ap_CS_fsm_state25) and (d_o_full_n = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state26;
else
ap_NS_fsm <= ap_ST_fsm_state25;
end if;
when ap_ST_fsm_state26 =>
if (((ap_const_logic_1 = ap_CS_fsm_state26) and (d_o_full_n = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state27;
else
ap_NS_fsm <= ap_ST_fsm_state26;
end if;
when ap_ST_fsm_state27 =>
if (((ap_const_logic_1 = ap_CS_fsm_state27) and (d_o_full_n = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state28;
else
ap_NS_fsm <= ap_ST_fsm_state27;
end if;
when ap_ST_fsm_state28 =>
if (((ap_const_logic_1 = ap_CS_fsm_state28) and (d_o_full_n = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state29;
else
ap_NS_fsm <= ap_ST_fsm_state28;
end if;
when ap_ST_fsm_state29 =>
if (((ap_const_logic_1 = ap_CS_fsm_state29) and (d_o_full_n = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state30;
else
ap_NS_fsm <= ap_ST_fsm_state29;
end if;
when ap_ST_fsm_state30 =>
if (((ap_const_logic_1 = ap_CS_fsm_state30) and (d_o_full_n = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state31;
else
ap_NS_fsm <= ap_ST_fsm_state30;
end if;
when ap_ST_fsm_state31 =>
if (((ap_const_logic_1 = ap_CS_fsm_state31) and (d_o_full_n = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state32;
else
ap_NS_fsm <= ap_ST_fsm_state31;
end if;
when ap_ST_fsm_state32 =>
if (((ap_const_logic_1 = ap_CS_fsm_state32) and (d_o_full_n = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state33;
else
ap_NS_fsm <= ap_ST_fsm_state32;
end if;
when ap_ST_fsm_state33 =>
if (((ap_const_logic_1 = ap_CS_fsm_state33) and (d_o_full_n = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state34;
else
ap_NS_fsm <= ap_ST_fsm_state33;
end if;
when ap_ST_fsm_state34 =>
if (((ap_const_logic_1 = ap_CS_fsm_state34) and (d_o_full_n = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state1;
else
ap_NS_fsm <= ap_ST_fsm_state34;
end if;
when others =>
ap_NS_fsm <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end case;
end process;
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state10 <= ap_CS_fsm(9);
ap_CS_fsm_state11 <= ap_CS_fsm(10);
ap_CS_fsm_state12 <= ap_CS_fsm(11);
ap_CS_fsm_state13 <= ap_CS_fsm(12);
ap_CS_fsm_state14 <= ap_CS_fsm(13);
ap_CS_fsm_state15 <= ap_CS_fsm(14);
ap_CS_fsm_state16 <= ap_CS_fsm(15);
ap_CS_fsm_state17 <= ap_CS_fsm(16);
ap_CS_fsm_state18 <= ap_CS_fsm(17);
ap_CS_fsm_state19 <= ap_CS_fsm(18);
ap_CS_fsm_state2 <= ap_CS_fsm(1);
ap_CS_fsm_state20 <= ap_CS_fsm(19);
ap_CS_fsm_state21 <= ap_CS_fsm(20);
ap_CS_fsm_state22 <= ap_CS_fsm(21);
ap_CS_fsm_state23 <= ap_CS_fsm(22);
ap_CS_fsm_state24 <= ap_CS_fsm(23);
ap_CS_fsm_state25 <= ap_CS_fsm(24);
ap_CS_fsm_state26 <= ap_CS_fsm(25);
ap_CS_fsm_state27 <= ap_CS_fsm(26);
ap_CS_fsm_state28 <= ap_CS_fsm(27);
ap_CS_fsm_state29 <= ap_CS_fsm(28);
ap_CS_fsm_state3 <= ap_CS_fsm(2);
ap_CS_fsm_state30 <= ap_CS_fsm(29);
ap_CS_fsm_state31 <= ap_CS_fsm(30);
ap_CS_fsm_state32 <= ap_CS_fsm(31);
ap_CS_fsm_state33 <= ap_CS_fsm(32);
ap_CS_fsm_state34 <= ap_CS_fsm(33);
ap_CS_fsm_state4 <= ap_CS_fsm(3);
ap_CS_fsm_state5 <= ap_CS_fsm(4);
ap_CS_fsm_state6 <= ap_CS_fsm(5);
ap_CS_fsm_state7 <= ap_CS_fsm(6);
ap_CS_fsm_state8 <= ap_CS_fsm(7);
ap_CS_fsm_state9 <= ap_CS_fsm(8);
ap_done_assign_proc : process(d_o_full_n, ap_CS_fsm_state34)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state34) and (d_o_full_n = ap_const_logic_1))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(d_o_full_n, ap_CS_fsm_state34)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state34) and (d_o_full_n = ap_const_logic_1))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
d_i_address0_assign_proc : process(ap_CS_fsm_state1, ap_CS_fsm_state3, ap_CS_fsm_state4, ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, ap_CS_fsm_state8, ap_CS_fsm_state9, ap_CS_fsm_state10, ap_CS_fsm_state11, ap_CS_fsm_state12, ap_CS_fsm_state13, ap_CS_fsm_state14, ap_CS_fsm_state15, ap_CS_fsm_state16, ap_CS_fsm_state2)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state16)) then
d_i_address0 <= ap_const_lv32_1E(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state15)) then
d_i_address0 <= ap_const_lv32_1C(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state14)) then
d_i_address0 <= ap_const_lv32_1A(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state13)) then
d_i_address0 <= ap_const_lv32_18(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state12)) then
d_i_address0 <= ap_const_lv32_16(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state11)) then
d_i_address0 <= ap_const_lv32_14(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state10)) then
d_i_address0 <= ap_const_lv32_12(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state9)) then
d_i_address0 <= ap_const_lv32_10(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state8)) then
d_i_address0 <= ap_const_lv32_E(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state7)) then
d_i_address0 <= ap_const_lv32_C(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state6)) then
d_i_address0 <= ap_const_lv32_A(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state5)) then
d_i_address0 <= ap_const_lv32_8(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state4)) then
d_i_address0 <= ap_const_lv32_6(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state3)) then
d_i_address0 <= ap_const_lv32_4(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then
d_i_address0 <= ap_const_lv32_2(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state1)) then
d_i_address0 <= ap_const_lv32_0(5 - 1 downto 0);
else
d_i_address0 <= "XXXXX";
end if;
end process;
d_i_address1_assign_proc : process(ap_CS_fsm_state1, ap_CS_fsm_state3, ap_CS_fsm_state4, ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, ap_CS_fsm_state8, ap_CS_fsm_state9, ap_CS_fsm_state10, ap_CS_fsm_state11, ap_CS_fsm_state12, ap_CS_fsm_state13, ap_CS_fsm_state14, ap_CS_fsm_state15, ap_CS_fsm_state16, ap_CS_fsm_state2)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state16)) then
d_i_address1 <= ap_const_lv32_1F(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state15)) then
d_i_address1 <= ap_const_lv32_1D(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state14)) then
d_i_address1 <= ap_const_lv32_1B(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state13)) then
d_i_address1 <= ap_const_lv32_19(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state12)) then
d_i_address1 <= ap_const_lv32_17(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state11)) then
d_i_address1 <= ap_const_lv32_15(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state10)) then
d_i_address1 <= ap_const_lv32_13(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state9)) then
d_i_address1 <= ap_const_lv32_11(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state8)) then
d_i_address1 <= ap_const_lv32_F(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state7)) then
d_i_address1 <= ap_const_lv32_D(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state6)) then
d_i_address1 <= ap_const_lv32_B(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state5)) then
d_i_address1 <= ap_const_lv32_9(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state4)) then
d_i_address1 <= ap_const_lv32_7(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state3)) then
d_i_address1 <= ap_const_lv32_5(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then
d_i_address1 <= ap_const_lv32_3(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state1)) then
d_i_address1 <= ap_const_lv32_1(5 - 1 downto 0);
else
d_i_address1 <= "XXXXX";
end if;
end process;
d_i_ce0_assign_proc : process(ap_start, ap_CS_fsm_state1, d_o_full_n, ap_CS_fsm_state3, ap_CS_fsm_state4, ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, ap_CS_fsm_state8, ap_CS_fsm_state9, ap_CS_fsm_state10, ap_CS_fsm_state11, ap_CS_fsm_state12, ap_CS_fsm_state13, ap_CS_fsm_state14, ap_CS_fsm_state15, ap_CS_fsm_state16, ap_CS_fsm_state2)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) or ((ap_const_logic_1 = ap_CS_fsm_state16) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state3) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state6) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state15) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state4) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state5) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state7) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state8) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state9) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state10) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state11) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state12) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state13) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state14) and (d_o_full_n = ap_const_logic_1)))) then
d_i_ce0 <= ap_const_logic_1;
else
d_i_ce0 <= ap_const_logic_0;
end if;
end process;
d_i_ce1_assign_proc : process(ap_start, ap_CS_fsm_state1, d_o_full_n, ap_CS_fsm_state3, ap_CS_fsm_state4, ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, ap_CS_fsm_state8, ap_CS_fsm_state9, ap_CS_fsm_state10, ap_CS_fsm_state11, ap_CS_fsm_state12, ap_CS_fsm_state13, ap_CS_fsm_state14, ap_CS_fsm_state15, ap_CS_fsm_state16, ap_CS_fsm_state2)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) or ((ap_const_logic_1 = ap_CS_fsm_state16) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state3) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state6) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state15) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state4) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state5) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state7) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state8) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state9) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state10) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state11) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state12) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state13) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state14) and (d_o_full_n = ap_const_logic_1)))) then
d_i_ce1 <= ap_const_logic_1;
else
d_i_ce1 <= ap_const_logic_0;
end if;
end process;
d_o_blk_n_assign_proc : process(d_o_full_n, ap_CS_fsm_state3, ap_CS_fsm_state4, ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, ap_CS_fsm_state8, ap_CS_fsm_state9, ap_CS_fsm_state10, ap_CS_fsm_state11, ap_CS_fsm_state12, ap_CS_fsm_state13, ap_CS_fsm_state14, ap_CS_fsm_state15, ap_CS_fsm_state16, ap_CS_fsm_state17, ap_CS_fsm_state18, ap_CS_fsm_state19, ap_CS_fsm_state20, ap_CS_fsm_state21, ap_CS_fsm_state22, ap_CS_fsm_state23, ap_CS_fsm_state24, ap_CS_fsm_state25, ap_CS_fsm_state26, ap_CS_fsm_state27, ap_CS_fsm_state28, ap_CS_fsm_state29, ap_CS_fsm_state30, ap_CS_fsm_state31, ap_CS_fsm_state32, ap_CS_fsm_state33, ap_CS_fsm_state34)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state3) or (ap_const_logic_1 = ap_CS_fsm_state4) or (ap_const_logic_1 = ap_CS_fsm_state5) or (ap_const_logic_1 = ap_CS_fsm_state6) or (ap_const_logic_1 = ap_CS_fsm_state7) or (ap_const_logic_1 = ap_CS_fsm_state8) or (ap_const_logic_1 = ap_CS_fsm_state9) or (ap_const_logic_1 = ap_CS_fsm_state10) or (ap_const_logic_1 = ap_CS_fsm_state11) or (ap_const_logic_1 = ap_CS_fsm_state12) or (ap_const_logic_1 = ap_CS_fsm_state13) or (ap_const_logic_1 = ap_CS_fsm_state14) or (ap_const_logic_1 = ap_CS_fsm_state15) or (ap_const_logic_1 = ap_CS_fsm_state16) or (ap_const_logic_1 = ap_CS_fsm_state17) or (ap_const_logic_1 = ap_CS_fsm_state18) or (ap_const_logic_1 = ap_CS_fsm_state19) or (ap_const_logic_1 = ap_CS_fsm_state20) or (ap_const_logic_1 = ap_CS_fsm_state21) or (ap_const_logic_1 = ap_CS_fsm_state22) or (ap_const_logic_1 = ap_CS_fsm_state23) or (ap_const_logic_1 = ap_CS_fsm_state24) or (ap_const_logic_1 = ap_CS_fsm_state25) or (ap_const_logic_1 = ap_CS_fsm_state26) or (ap_const_logic_1 = ap_CS_fsm_state27) or (ap_const_logic_1 = ap_CS_fsm_state28) or (ap_const_logic_1 = ap_CS_fsm_state29) or (ap_const_logic_1 = ap_CS_fsm_state30) or (ap_const_logic_1 = ap_CS_fsm_state31) or (ap_const_logic_1 = ap_CS_fsm_state32) or (ap_const_logic_1 = ap_CS_fsm_state33) or (ap_const_logic_1 = ap_CS_fsm_state34))) then
d_o_blk_n <= d_o_full_n;
else
d_o_blk_n <= ap_const_logic_1;
end if;
end process;
d_o_din_assign_proc : process(d_o_full_n, ap_CS_fsm_state3, ap_CS_fsm_state4, ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, ap_CS_fsm_state8, ap_CS_fsm_state9, ap_CS_fsm_state10, ap_CS_fsm_state11, ap_CS_fsm_state12, ap_CS_fsm_state13, ap_CS_fsm_state14, ap_CS_fsm_state15, ap_CS_fsm_state16, ap_CS_fsm_state17, ap_CS_fsm_state18, ap_CS_fsm_state19, ap_CS_fsm_state20, ap_CS_fsm_state21, ap_CS_fsm_state22, ap_CS_fsm_state23, ap_CS_fsm_state24, ap_CS_fsm_state25, ap_CS_fsm_state26, ap_CS_fsm_state27, ap_CS_fsm_state28, ap_CS_fsm_state29, ap_CS_fsm_state30, ap_CS_fsm_state31, ap_CS_fsm_state32, ap_CS_fsm_state33, ap_CS_fsm_state34, tmp_8_fu_438_p2, tmp_1_1_fu_453_p2, tmp_1_2_fu_468_p2, tmp_1_3_fu_483_p2, tmp_1_4_fu_498_p2, tmp_1_5_fu_512_p2, tmp_1_6_fu_526_p2, tmp_1_7_fu_540_p2, tmp_1_8_fu_546_p2, tmp_1_9_fu_552_p2, tmp_1_s_fu_558_p2, tmp_1_10_fu_563_p2, tmp_1_11_fu_576_p2, tmp_1_15_reg_1420, tmp_1_16_reg_1426, tmp_1_12_fu_647_p2, tmp_1_17_reg_1457, tmp_1_18_reg_1463, tmp_1_13_fu_760_p2, tmp_1_19_reg_1494, tmp_1_20_reg_1500, tmp_1_21_reg_1516, tmp_1_22_reg_1522, tmp_1_23_reg_1538, tmp_1_24_reg_1543, tmp_1_25_reg_1548, tmp_1_26_reg_1553, tmp_1_27_reg_1558, tmp_1_28_reg_1563, tmp_1_29_reg_1568, tmp_1_30_reg_1573, tmp_1_14_fu_871_p2)
begin
if ((d_o_full_n = ap_const_logic_1)) then
if ((ap_const_logic_1 = ap_CS_fsm_state34)) then
d_o_din <= tmp_1_30_reg_1573;
elsif ((ap_const_logic_1 = ap_CS_fsm_state33)) then
d_o_din <= tmp_1_29_reg_1568;
elsif ((ap_const_logic_1 = ap_CS_fsm_state32)) then
d_o_din <= tmp_1_28_reg_1563;
elsif ((ap_const_logic_1 = ap_CS_fsm_state31)) then
d_o_din <= tmp_1_27_reg_1558;
elsif ((ap_const_logic_1 = ap_CS_fsm_state30)) then
d_o_din <= tmp_1_26_reg_1553;
elsif ((ap_const_logic_1 = ap_CS_fsm_state29)) then
d_o_din <= tmp_1_25_reg_1548;
elsif ((ap_const_logic_1 = ap_CS_fsm_state28)) then
d_o_din <= tmp_1_24_reg_1543;
elsif ((ap_const_logic_1 = ap_CS_fsm_state27)) then
d_o_din <= tmp_1_23_reg_1538;
elsif ((ap_const_logic_1 = ap_CS_fsm_state26)) then
d_o_din <= tmp_1_22_reg_1522;
elsif ((ap_const_logic_1 = ap_CS_fsm_state25)) then
d_o_din <= tmp_1_21_reg_1516;
elsif ((ap_const_logic_1 = ap_CS_fsm_state24)) then
d_o_din <= tmp_1_20_reg_1500;
elsif ((ap_const_logic_1 = ap_CS_fsm_state23)) then
d_o_din <= tmp_1_19_reg_1494;
elsif ((ap_const_logic_1 = ap_CS_fsm_state22)) then
d_o_din <= tmp_1_18_reg_1463;
elsif ((ap_const_logic_1 = ap_CS_fsm_state21)) then
d_o_din <= tmp_1_17_reg_1457;
elsif ((ap_const_logic_1 = ap_CS_fsm_state20)) then
d_o_din <= tmp_1_16_reg_1426;
elsif ((ap_const_logic_1 = ap_CS_fsm_state19)) then
d_o_din <= tmp_1_15_reg_1420;
elsif ((ap_const_logic_1 = ap_CS_fsm_state18)) then
d_o_din <= tmp_1_14_fu_871_p2;
elsif ((ap_const_logic_1 = ap_CS_fsm_state17)) then
d_o_din <= tmp_1_13_fu_760_p2;
elsif ((ap_const_logic_1 = ap_CS_fsm_state16)) then
d_o_din <= tmp_1_12_fu_647_p2;
elsif ((ap_const_logic_1 = ap_CS_fsm_state15)) then
d_o_din <= tmp_1_11_fu_576_p2;
elsif ((ap_const_logic_1 = ap_CS_fsm_state14)) then
d_o_din <= tmp_1_10_fu_563_p2;
elsif ((ap_const_logic_1 = ap_CS_fsm_state13)) then
d_o_din <= tmp_1_s_fu_558_p2;
elsif ((ap_const_logic_1 = ap_CS_fsm_state12)) then
d_o_din <= tmp_1_9_fu_552_p2;
elsif ((ap_const_logic_1 = ap_CS_fsm_state11)) then
d_o_din <= tmp_1_8_fu_546_p2;
elsif ((ap_const_logic_1 = ap_CS_fsm_state10)) then
d_o_din <= tmp_1_7_fu_540_p2;
elsif ((ap_const_logic_1 = ap_CS_fsm_state9)) then
d_o_din <= tmp_1_6_fu_526_p2;
elsif ((ap_const_logic_1 = ap_CS_fsm_state8)) then
d_o_din <= tmp_1_5_fu_512_p2;
elsif ((ap_const_logic_1 = ap_CS_fsm_state7)) then
d_o_din <= tmp_1_4_fu_498_p2;
elsif ((ap_const_logic_1 = ap_CS_fsm_state6)) then
d_o_din <= tmp_1_3_fu_483_p2;
elsif ((ap_const_logic_1 = ap_CS_fsm_state5)) then
d_o_din <= tmp_1_2_fu_468_p2;
elsif ((ap_const_logic_1 = ap_CS_fsm_state4)) then
d_o_din <= tmp_1_1_fu_453_p2;
elsif ((ap_const_logic_1 = ap_CS_fsm_state3)) then
d_o_din <= tmp_8_fu_438_p2;
else
d_o_din <= "XXXXXXXXXXXXXXXX";
end if;
else
d_o_din <= "XXXXXXXXXXXXXXXX";
end if;
end process;
d_o_write_assign_proc : process(d_o_full_n, ap_CS_fsm_state3, ap_CS_fsm_state4, ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, ap_CS_fsm_state8, ap_CS_fsm_state9, ap_CS_fsm_state10, ap_CS_fsm_state11, ap_CS_fsm_state12, ap_CS_fsm_state13, ap_CS_fsm_state14, ap_CS_fsm_state15, ap_CS_fsm_state16, ap_CS_fsm_state17, ap_CS_fsm_state18, ap_CS_fsm_state19, ap_CS_fsm_state20, ap_CS_fsm_state21, ap_CS_fsm_state22, ap_CS_fsm_state23, ap_CS_fsm_state24, ap_CS_fsm_state25, ap_CS_fsm_state26, ap_CS_fsm_state27, ap_CS_fsm_state28, ap_CS_fsm_state29, ap_CS_fsm_state30, ap_CS_fsm_state31, ap_CS_fsm_state32, ap_CS_fsm_state33, ap_CS_fsm_state34)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_state16) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state3) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state17) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state6) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state15) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state4) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state5) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state7) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state8) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state9) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state10) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state11) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state12) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state13) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state14) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state18) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state19) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state20) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state21) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state22) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state23) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state24) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state25) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state26) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state27) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state28) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state29) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state30) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state31) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state32) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state33) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state34) and (d_o_full_n = ap_const_logic_1)))) then
d_o_write <= ap_const_logic_1;
else
d_o_write <= ap_const_logic_0;
end if;
end process;
temp_1_fu_694_p2 <= std_logic_vector(signed(tmp5_cast_fu_691_p1) + signed(tmp4_fu_686_p2));
temp_2_fu_787_p2 <= std_logic_vector(signed(tmp8_cast_fu_784_p1) + signed(tmp7_fu_779_p2));
temp_3_fu_807_p2 <= std_logic_vector(signed(tmp11_cast_fu_804_p1) + signed(tmp10_fu_799_p2));
temp_4_fu_899_p2 <= std_logic_vector(signed(tmp14_cast_fu_896_p1) + signed(tmp13_fu_891_p2));
temp_5_fu_919_p2 <= std_logic_vector(signed(tmp17_cast_fu_916_p1) + signed(tmp16_fu_911_p2));
temp_6_fu_989_p2 <= std_logic_vector(signed(tmp20_cast_fu_986_p1) + signed(tmp19_fu_981_p2));
temp_7_fu_1009_p2 <= std_logic_vector(signed(tmp23_cast_fu_1006_p1) + signed(tmp22_fu_1001_p2));
temp_s_fu_674_p2 <= std_logic_vector(signed(tmp2_cast_fu_671_p1) + signed(tmp1_fu_666_p2));
tmp10_fu_799_p2 <= std_logic_vector(unsigned(acc_3) + unsigned(tmp_3_fu_750_p1));
tmp11_cast_fu_804_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp11_reg_1474),32));
tmp11_fu_740_p2 <= std_logic_vector(signed(tmp12_cast_fu_736_p1) + signed(tmp_11_cast_fu_644_p1));
tmp12_cast_fu_736_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp12_fu_730_p2),18));
tmp12_fu_730_p2 <= std_logic_vector(signed(tmp_19_cast_fu_659_p1) + signed(tmp_27_cast_fu_726_p1));
tmp13_fu_891_p2 <= std_logic_vector(unsigned(acc_4) + unsigned(tmp_4_fu_859_p1));
tmp14_cast_fu_896_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp14_reg_1506),32));
tmp14_fu_833_p2 <= std_logic_vector(signed(tmp15_cast_fu_829_p1) + signed(tmp_12_cast_fu_754_p1));
tmp15_cast_fu_829_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp15_fu_823_p2),18));
tmp15_fu_823_p2 <= std_logic_vector(signed(tmp_20_cast_fu_765_p1) + signed(tmp_28_cast_fu_819_p1));
tmp16_fu_911_p2 <= std_logic_vector(unsigned(acc_5) + unsigned(tmp_5_fu_862_p1));
tmp17_cast_fu_916_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp17_reg_1511),32));
tmp17_fu_853_p2 <= std_logic_vector(signed(tmp18_cast_fu_849_p1) + signed(tmp_13_cast_fu_757_p1));
tmp18_cast_fu_849_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp18_fu_843_p2),18));
tmp18_fu_843_p2 <= std_logic_vector(signed(tmp_21_cast_fu_772_p1) + signed(tmp_29_cast_fu_839_p1));
tmp19_fu_981_p2 <= std_logic_vector(unsigned(acc_6) + unsigned(tmp_6_fu_971_p1));
tmp1_fu_666_p2 <= std_logic_vector(unsigned(acc_0) + unsigned(tmp_fu_633_p1));
tmp20_cast_fu_986_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp20_reg_1528),32));
tmp20_fu_945_p2 <= std_logic_vector(signed(tmp21_cast_fu_941_p1) + signed(tmp_14_cast_fu_865_p1));
tmp21_cast_fu_941_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp21_fu_935_p2),18));
tmp21_fu_935_p2 <= std_logic_vector(signed(tmp_22_cast_fu_876_p1) + signed(tmp_30_cast_fu_931_p1));
tmp22_fu_1001_p2 <= std_logic_vector(unsigned(acc_7) + unsigned(tmp_7_fu_974_p1));
tmp23_cast_fu_1006_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp23_reg_1533),32));
tmp23_fu_965_p2 <= std_logic_vector(signed(tmp24_cast_fu_961_p1) + signed(tmp_15_cast_fu_868_p1));
tmp24_cast_fu_961_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp24_fu_955_p2),18));
tmp24_fu_955_p2 <= std_logic_vector(signed(tmp_23_cast_fu_883_p1) + signed(tmp_31_cast_fu_951_p1));
tmp2_cast_fu_671_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp2_reg_1432),32));
tmp2_fu_608_p2 <= std_logic_vector(signed(tmp3_cast_fu_604_p1) + signed(tmp_8_cast_fu_568_p1));
tmp3_cast_fu_604_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp3_fu_598_p2),18));
tmp3_fu_598_p2 <= std_logic_vector(signed(tmp_16_cast_fu_581_p1) + signed(tmp_24_cast_fu_595_p1));
tmp4_fu_686_p2 <= std_logic_vector(unsigned(acc_1) + unsigned(tmp_s_fu_637_p1));
tmp5_cast_fu_691_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp5_reg_1437),32));
tmp5_fu_627_p2 <= std_logic_vector(signed(tmp6_cast_fu_623_p1) + signed(tmp_9_cast_fu_572_p1));
tmp6_cast_fu_623_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp6_fu_617_p2),18));
tmp6_fu_617_p2 <= std_logic_vector(signed(tmp_17_cast_fu_588_p1) + signed(tmp_25_cast_fu_614_p1));
tmp7_fu_779_p2 <= std_logic_vector(unsigned(acc_2) + unsigned(tmp_2_fu_746_p1));
tmp8_cast_fu_784_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp8_reg_1469),32));
tmp8_fu_720_p2 <= std_logic_vector(signed(tmp9_cast_fu_716_p1) + signed(tmp_10_cast_fu_641_p1));
tmp9_cast_fu_716_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp9_fu_710_p2),18));
tmp9_fu_710_p2 <= std_logic_vector(signed(tmp_18_cast_fu_652_p1) + signed(tmp_26_cast_fu_706_p1));
tmp_10_cast_fu_641_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_load_10_reg_1189),18));
tmp_10_fu_464_p1 <= acc_2(16 - 1 downto 0);
tmp_11_cast_fu_644_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_load_11_reg_1195),18));
tmp_11_fu_479_p1 <= acc_3(16 - 1 downto 0);
tmp_12_cast_fu_754_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_load_12_reg_1221),18));
tmp_12_fu_494_p1 <= acc_4(16 - 1 downto 0);
tmp_13_cast_fu_757_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_load_13_reg_1227),18));
tmp_13_fu_508_p1 <= acc_5(16 - 1 downto 0);
tmp_14_cast_fu_865_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_load_14_reg_1253),18));
tmp_14_fu_522_p1 <= acc_6(16 - 1 downto 0);
tmp_15_cast_fu_868_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_load_15_reg_1259),18));
tmp_15_fu_536_p1 <= acc_7(16 - 1 downto 0);
tmp_16_cast_fu_581_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_load_16_reg_1285),17));
tmp_17_cast_fu_588_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_load_17_reg_1291),17));
tmp_18_cast_fu_652_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_load_18_reg_1312),17));
tmp_19_cast_fu_659_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_load_19_reg_1318),17));
tmp_1_10_fu_563_p2 <= std_logic_vector(unsigned(d_i_load_11_reg_1195) + unsigned(tmp_1_3_reg_1164));
tmp_1_11_fu_576_p2 <= std_logic_vector(unsigned(d_i_load_12_reg_1221) + unsigned(tmp_1_4_reg_1184));
tmp_1_12_fu_647_p2 <= std_logic_vector(unsigned(d_i_load_13_reg_1227) + unsigned(tmp_1_5_reg_1216));
tmp_1_13_fu_760_p2 <= std_logic_vector(unsigned(d_i_load_14_reg_1253) + unsigned(tmp_1_6_reg_1248));
tmp_1_14_fu_871_p2 <= std_logic_vector(unsigned(d_i_load_15_reg_1259) + unsigned(tmp_1_7_reg_1280));
tmp_1_15_fu_584_p2 <= std_logic_vector(unsigned(d_i_load_16_reg_1285) + unsigned(tmp_1_8_reg_1307));
tmp_1_16_fu_591_p2 <= std_logic_vector(unsigned(d_i_load_17_reg_1291) + unsigned(tmp_1_9_reg_1334));
tmp_1_17_fu_655_p2 <= std_logic_vector(unsigned(d_i_load_18_reg_1312) + unsigned(tmp_1_s_reg_1361));
tmp_1_18_fu_662_p2 <= std_logic_vector(unsigned(d_i_load_19_reg_1318) + unsigned(tmp_1_10_reg_1388));
tmp_1_19_fu_768_p2 <= std_logic_vector(unsigned(d_i_load_20_reg_1339) + unsigned(tmp_1_11_reg_1415));
tmp_1_1_fu_453_p2 <= std_logic_vector(unsigned(reg_410) + unsigned(tmp_9_fu_449_p1));
tmp_1_20_fu_775_p2 <= std_logic_vector(unsigned(d_i_load_21_reg_1345) + unsigned(tmp_1_12_reg_1452));
tmp_1_21_fu_879_p2 <= std_logic_vector(unsigned(d_i_load_22_reg_1366) + unsigned(tmp_1_13_reg_1489));
tmp_1_22_fu_886_p2 <= std_logic_vector(unsigned(d_i_load_23_reg_1372) + unsigned(tmp_1_14_fu_871_p2));
tmp_1_23_fu_977_p2 <= std_logic_vector(unsigned(d_i_load_24_reg_1393) + unsigned(tmp_1_15_reg_1420));
tmp_1_24_fu_1021_p2 <= std_logic_vector(unsigned(d_i_load_25_reg_1399) + unsigned(tmp_1_16_reg_1426));
tmp_1_25_fu_1025_p2 <= std_logic_vector(unsigned(reg_422) + unsigned(tmp_1_17_reg_1457));
tmp_1_26_fu_1030_p2 <= std_logic_vector(unsigned(reg_426) + unsigned(tmp_1_18_reg_1463));
tmp_1_27_fu_1035_p2 <= std_logic_vector(unsigned(reg_406) + unsigned(tmp_1_19_reg_1494));
tmp_1_28_fu_1040_p2 <= std_logic_vector(unsigned(reg_410) + unsigned(tmp_1_20_reg_1500));
tmp_1_29_fu_1045_p2 <= std_logic_vector(unsigned(reg_414) + unsigned(tmp_1_21_reg_1516));
tmp_1_2_fu_468_p2 <= std_logic_vector(unsigned(reg_414) + unsigned(tmp_10_fu_464_p1));
tmp_1_30_fu_1050_p2 <= std_logic_vector(unsigned(reg_418) + unsigned(tmp_1_22_reg_1522));
tmp_1_3_fu_483_p2 <= std_logic_vector(unsigned(reg_418) + unsigned(tmp_11_fu_479_p1));
tmp_1_4_fu_498_p2 <= std_logic_vector(unsigned(d_i_load_4_reg_1105) + unsigned(tmp_12_fu_494_p1));
tmp_1_5_fu_512_p2 <= std_logic_vector(unsigned(d_i_load_5_reg_1111) + unsigned(tmp_13_fu_508_p1));
tmp_1_6_fu_526_p2 <= std_logic_vector(unsigned(d_i_load_6_reg_1137) + unsigned(tmp_14_fu_522_p1));
tmp_1_7_fu_540_p2 <= std_logic_vector(unsigned(d_i_load_7_reg_1143) + unsigned(tmp_15_fu_536_p1));
tmp_1_8_fu_546_p2 <= std_logic_vector(unsigned(reg_422) + unsigned(tmp_8_reg_1080));
tmp_1_9_fu_552_p2 <= std_logic_vector(unsigned(reg_426) + unsigned(tmp_1_1_reg_1100));
tmp_1_fu_434_p1 <= acc_0(16 - 1 downto 0);
tmp_1_s_fu_558_p2 <= std_logic_vector(unsigned(d_i_load_10_reg_1189) + unsigned(tmp_1_2_reg_1132));
tmp_20_cast_fu_765_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_load_20_reg_1339),17));
tmp_21_cast_fu_772_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_load_21_reg_1345),17));
tmp_22_cast_fu_876_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_load_22_reg_1366),17));
tmp_23_cast_fu_883_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_load_23_reg_1372),17));
tmp_24_cast_fu_595_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_load_24_reg_1393),17));
tmp_25_cast_fu_614_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_load_25_reg_1399),17));
tmp_26_cast_fu_706_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_422),17));
tmp_27_cast_fu_726_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_426),17));
tmp_28_cast_fu_819_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_406),17));
tmp_29_cast_fu_839_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_410),17));
tmp_2_fu_746_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_414),32));
tmp_30_cast_fu_931_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_414),17));
tmp_31_cast_fu_951_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_418),17));
tmp_3_fu_750_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_418),32));
tmp_4_fu_859_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_load_4_reg_1105),32));
tmp_5_fu_862_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_load_5_reg_1111),32));
tmp_6_fu_971_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_load_6_reg_1137),32));
tmp_7_fu_974_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_load_7_reg_1143),32));
tmp_8_cast_fu_568_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_422),18));
tmp_8_fu_438_p2 <= std_logic_vector(unsigned(reg_406) + unsigned(tmp_1_fu_434_p1));
tmp_9_cast_fu_572_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_426),18));
tmp_9_fu_449_p1 <= acc_1(16 - 1 downto 0);
tmp_fu_633_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_406),32));
tmp_s_fu_637_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_410),32));
end behav;
| mit | 5bb84879548ed2e46fe57a67b5a6626a | 0.590774 | 2.782033 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/ug871-design-files/Introduction/lab3/fir_prj/solution2/syn/vhdl/fir.vhd | 1 | 18,991 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity fir is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
y : OUT STD_LOGIC_VECTOR (31 downto 0);
y_ap_vld : OUT STD_LOGIC;
c_address0 : OUT STD_LOGIC_VECTOR (3 downto 0);
c_ce0 : OUT STD_LOGIC;
c_q0 : IN STD_LOGIC_VECTOR (31 downto 0);
x : IN STD_LOGIC_VECTOR (31 downto 0);
x_ap_vld : IN STD_LOGIC );
end;
architecture behav of fir is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"fir,hls_ip_2017_2,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=6.912000,HLS_SYN_LAT=67,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=4,HLS_SYN_FF=561,HLS_SYN_LUT=266}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (6 downto 0) := "0000001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (6 downto 0) := "0000010";
constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (6 downto 0) := "0000100";
constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (6 downto 0) := "0001000";
constant ap_ST_fsm_state5 : STD_LOGIC_VECTOR (6 downto 0) := "0010000";
constant ap_ST_fsm_state6 : STD_LOGIC_VECTOR (6 downto 0) := "0100000";
constant ap_ST_fsm_state7 : STD_LOGIC_VECTOR (6 downto 0) := "1000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv5_A : STD_LOGIC_VECTOR (4 downto 0) := "01010";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
constant ap_const_lv5_1F : STD_LOGIC_VECTOR (4 downto 0) := "11111";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv5_0 : STD_LOGIC_VECTOR (4 downto 0) := "00000";
constant ap_const_boolean_1 : BOOLEAN := true;
signal ap_CS_fsm : STD_LOGIC_VECTOR (6 downto 0) := "0000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal x_preg : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal x_in_sig : STD_LOGIC_VECTOR (31 downto 0);
signal x_ap_vld_preg : STD_LOGIC := '0';
signal x_ap_vld_in_sig : STD_LOGIC;
signal shift_reg_address0 : STD_LOGIC_VECTOR (3 downto 0);
signal shift_reg_ce0 : STD_LOGIC;
signal shift_reg_we0 : STD_LOGIC;
signal shift_reg_d0 : STD_LOGIC_VECTOR (31 downto 0);
signal shift_reg_q0 : STD_LOGIC_VECTOR (31 downto 0);
signal x_blk_n : STD_LOGIC;
signal ap_block_state1 : BOOLEAN;
signal i_cast_fu_143_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal i_cast_reg_190 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
signal tmp_1_fu_155_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_1_reg_199 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_fu_147_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state3 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state3 : signal is "none";
signal grp_fu_136_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal i_1_reg_218 : STD_LOGIC_VECTOR (4 downto 0);
signal c_load_reg_223 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state4 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state4 : signal is "none";
signal grp_fu_174_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_6_reg_228 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state6 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state6 : signal is "none";
signal acc_1_fu_179_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state7 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state7 : signal is "none";
signal acc_reg_101 : STD_LOGIC_VECTOR (31 downto 0);
signal i_phi_fu_118_p4 : STD_LOGIC_VECTOR (4 downto 0);
signal i_reg_114 : STD_LOGIC_VECTOR (4 downto 0);
signal data1_reg_126 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_3_fu_161_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_4_fu_166_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_5_fu_170_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_136_p0 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_CS_fsm_state5 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state5 : signal is "none";
signal ap_NS_fsm : STD_LOGIC_VECTOR (6 downto 0);
component fir_mul_32s_32s_3bkb IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component fir_shift_reg IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (3 downto 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR (31 downto 0);
q0 : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
begin
shift_reg_U : component fir_shift_reg
generic map (
DataWidth => 32,
AddressRange => 11,
AddressWidth => 4)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => shift_reg_address0,
ce0 => shift_reg_ce0,
we0 => shift_reg_we0,
d0 => shift_reg_d0,
q0 => shift_reg_q0);
fir_mul_32s_32s_3bkb_U1 : component fir_mul_32s_32s_3bkb
generic map (
ID => 1,
NUM_STAGE => 2,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => c_load_reg_223,
din1 => data1_reg_126,
ce => ap_const_logic_1,
dout => grp_fu_174_p2);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
x_ap_vld_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
x_ap_vld_preg <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_147_p3 = ap_const_lv1_1))) then
x_ap_vld_preg <= ap_const_logic_0;
elsif (((ap_const_logic_1 = x_ap_vld) and not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))))) then
x_ap_vld_preg <= x_ap_vld;
end if;
end if;
end if;
end process;
x_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
x_preg <= ap_const_lv32_0;
else
if (((ap_const_logic_1 = x_ap_vld) and not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))))) then
x_preg <= x;
end if;
end if;
end if;
end process;
acc_reg_101_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state7)) then
acc_reg_101 <= acc_1_fu_179_p2;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = x_ap_vld_in_sig))))) then
acc_reg_101 <= ap_const_lv32_0;
end if;
end if;
end process;
data1_reg_126_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state3) and (tmp_1_reg_199 = ap_const_lv1_0))) then
data1_reg_126 <= shift_reg_q0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_147_p3 = ap_const_lv1_0) and (tmp_1_fu_155_p2 = ap_const_lv1_1))) then
data1_reg_126 <= x_in_sig;
end if;
end if;
end process;
i_reg_114_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state7)) then
i_reg_114 <= i_1_reg_218;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = x_ap_vld_in_sig))))) then
i_reg_114 <= ap_const_lv5_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state4)) then
c_load_reg_223 <= c_q0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
i_1_reg_218 <= grp_fu_136_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
i_cast_reg_190 <= i_cast_fu_143_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_147_p3 = ap_const_lv1_0))) then
tmp_1_reg_199 <= tmp_1_fu_155_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state6)) then
tmp_6_reg_228 <= grp_fu_174_p2;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, x_ap_vld_in_sig, ap_CS_fsm_state2, tmp_fu_147_p3)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = x_ap_vld_in_sig))))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_147_p3 = ap_const_lv1_1))) then
ap_NS_fsm <= ap_ST_fsm_state1;
else
ap_NS_fsm <= ap_ST_fsm_state3;
end if;
when ap_ST_fsm_state3 =>
ap_NS_fsm <= ap_ST_fsm_state4;
when ap_ST_fsm_state4 =>
ap_NS_fsm <= ap_ST_fsm_state5;
when ap_ST_fsm_state5 =>
ap_NS_fsm <= ap_ST_fsm_state6;
when ap_ST_fsm_state6 =>
ap_NS_fsm <= ap_ST_fsm_state7;
when ap_ST_fsm_state7 =>
ap_NS_fsm <= ap_ST_fsm_state2;
when others =>
ap_NS_fsm <= "XXXXXXX";
end case;
end process;
acc_1_fu_179_p2 <= std_logic_vector(unsigned(tmp_6_reg_228) + unsigned(acc_reg_101));
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state2 <= ap_CS_fsm(1);
ap_CS_fsm_state3 <= ap_CS_fsm(2);
ap_CS_fsm_state4 <= ap_CS_fsm(3);
ap_CS_fsm_state5 <= ap_CS_fsm(4);
ap_CS_fsm_state6 <= ap_CS_fsm(5);
ap_CS_fsm_state7 <= ap_CS_fsm(6);
ap_block_state1_assign_proc : process(ap_start, x_ap_vld_in_sig)
begin
ap_block_state1 <= ((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = x_ap_vld_in_sig));
end process;
ap_done_assign_proc : process(ap_CS_fsm_state2, tmp_fu_147_p3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_147_p3 = ap_const_lv1_1))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(ap_CS_fsm_state2, tmp_fu_147_p3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_147_p3 = ap_const_lv1_1))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
c_address0 <= tmp_5_fu_170_p1(4 - 1 downto 0);
c_ce0_assign_proc : process(ap_CS_fsm_state3)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
c_ce0 <= ap_const_logic_1;
else
c_ce0 <= ap_const_logic_0;
end if;
end process;
grp_fu_136_p0_assign_proc : process(ap_CS_fsm_state2, ap_CS_fsm_state3, i_phi_fu_118_p4, i_reg_114)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
grp_fu_136_p0 <= i_reg_114;
elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then
grp_fu_136_p0 <= i_phi_fu_118_p4;
else
grp_fu_136_p0 <= "XXXXX";
end if;
end process;
grp_fu_136_p2 <= std_logic_vector(unsigned(grp_fu_136_p0) + unsigned(ap_const_lv5_1F));
i_cast_fu_143_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(i_reg_114),32));
i_phi_fu_118_p4 <= i_reg_114;
shift_reg_address0_assign_proc : process(ap_CS_fsm_state2, tmp_1_fu_155_p2, tmp_fu_147_p3, ap_CS_fsm_state3, tmp_3_fu_161_p1, tmp_4_fu_166_p1)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
shift_reg_address0 <= tmp_4_fu_166_p1(4 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_147_p3 = ap_const_lv1_0) and (tmp_1_fu_155_p2 = ap_const_lv1_1))) then
shift_reg_address0 <= ap_const_lv4_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_147_p3 = ap_const_lv1_0) and (tmp_1_fu_155_p2 = ap_const_lv1_0))) then
shift_reg_address0 <= tmp_3_fu_161_p1(4 - 1 downto 0);
else
shift_reg_address0 <= "XXXX";
end if;
end process;
shift_reg_ce0_assign_proc : process(ap_CS_fsm_state2, tmp_1_fu_155_p2, tmp_fu_147_p3, ap_CS_fsm_state3)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_147_p3 = ap_const_lv1_0) and (tmp_1_fu_155_p2 = ap_const_lv1_0)) or (ap_const_logic_1 = ap_CS_fsm_state3) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_147_p3 = ap_const_lv1_0) and (tmp_1_fu_155_p2 = ap_const_lv1_1)))) then
shift_reg_ce0 <= ap_const_logic_1;
else
shift_reg_ce0 <= ap_const_logic_0;
end if;
end process;
shift_reg_d0_assign_proc : process(x_in_sig, shift_reg_q0, ap_CS_fsm_state2, tmp_1_fu_155_p2, tmp_fu_147_p3, ap_CS_fsm_state3)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
shift_reg_d0 <= shift_reg_q0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_147_p3 = ap_const_lv1_0) and (tmp_1_fu_155_p2 = ap_const_lv1_1))) then
shift_reg_d0 <= x_in_sig;
else
shift_reg_d0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
shift_reg_we0_assign_proc : process(ap_CS_fsm_state2, tmp_1_fu_155_p2, tmp_1_reg_199, tmp_fu_147_p3, ap_CS_fsm_state3)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_state3) and (tmp_1_reg_199 = ap_const_lv1_0)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_147_p3 = ap_const_lv1_0) and (tmp_1_fu_155_p2 = ap_const_lv1_1)))) then
shift_reg_we0 <= ap_const_logic_1;
else
shift_reg_we0 <= ap_const_logic_0;
end if;
end process;
tmp_1_fu_155_p2 <= "1" when (i_reg_114 = ap_const_lv5_0) else "0";
tmp_3_fu_161_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(grp_fu_136_p2),64));
tmp_4_fu_166_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_cast_reg_190),64));
tmp_5_fu_170_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_cast_reg_190),64));
tmp_fu_147_p3 <= i_reg_114(4 downto 4);
x_ap_vld_in_sig_assign_proc : process(x_ap_vld, x_ap_vld_preg)
begin
if ((ap_const_logic_1 = x_ap_vld)) then
x_ap_vld_in_sig <= x_ap_vld;
else
x_ap_vld_in_sig <= x_ap_vld_preg;
end if;
end process;
x_blk_n_assign_proc : process(ap_start, ap_CS_fsm_state1, x_ap_vld)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
x_blk_n <= x_ap_vld;
else
x_blk_n <= ap_const_logic_1;
end if;
end process;
x_in_sig_assign_proc : process(x, x_preg, x_ap_vld)
begin
if ((ap_const_logic_1 = x_ap_vld)) then
x_in_sig <= x;
else
x_in_sig <= x_preg;
end if;
end process;
y <= acc_reg_101;
y_ap_vld_assign_proc : process(ap_CS_fsm_state2, tmp_fu_147_p3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_147_p3 = ap_const_lv1_1))) then
y_ap_vld <= ap_const_logic_1;
else
y_ap_vld <= ap_const_logic_0;
end if;
end process;
end behav;
| mit | 94cf864f6b545d4293b192041c46601a | 0.564057 | 2.910052 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/ug871-design-files/Interface_Synthesis/lab3/array_io_prj/solution3/syn/vhdl/array_io.vhd | 1 | 77,721 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity array_io is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
d_o_0_din : OUT STD_LOGIC_VECTOR (15 downto 0);
d_o_0_full_n : IN STD_LOGIC;
d_o_0_write : OUT STD_LOGIC;
d_o_1_din : OUT STD_LOGIC_VECTOR (15 downto 0);
d_o_1_full_n : IN STD_LOGIC;
d_o_1_write : OUT STD_LOGIC;
d_o_2_din : OUT STD_LOGIC_VECTOR (15 downto 0);
d_o_2_full_n : IN STD_LOGIC;
d_o_2_write : OUT STD_LOGIC;
d_o_3_din : OUT STD_LOGIC_VECTOR (15 downto 0);
d_o_3_full_n : IN STD_LOGIC;
d_o_3_write : OUT STD_LOGIC;
d_i_0_address0 : OUT STD_LOGIC_VECTOR (3 downto 0);
d_i_0_ce0 : OUT STD_LOGIC;
d_i_0_q0 : IN STD_LOGIC_VECTOR (15 downto 0);
d_i_0_address1 : OUT STD_LOGIC_VECTOR (3 downto 0);
d_i_0_ce1 : OUT STD_LOGIC;
d_i_0_q1 : IN STD_LOGIC_VECTOR (15 downto 0);
d_i_1_address0 : OUT STD_LOGIC_VECTOR (3 downto 0);
d_i_1_ce0 : OUT STD_LOGIC;
d_i_1_q0 : IN STD_LOGIC_VECTOR (15 downto 0);
d_i_1_address1 : OUT STD_LOGIC_VECTOR (3 downto 0);
d_i_1_ce1 : OUT STD_LOGIC;
d_i_1_q1 : IN STD_LOGIC_VECTOR (15 downto 0) );
end;
architecture behav of array_io is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"array_io,hls_ip_2017_2,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7k160tfbg484-1,HLS_INPUT_CLOCK=4.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=3.359333,HLS_SYN_LAT=11,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=3532,HLS_SYN_LUT=2008}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (11 downto 0) := "000000000001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (11 downto 0) := "000000000010";
constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (11 downto 0) := "000000000100";
constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (11 downto 0) := "000000001000";
constant ap_ST_fsm_state5 : STD_LOGIC_VECTOR (11 downto 0) := "000000010000";
constant ap_ST_fsm_state6 : STD_LOGIC_VECTOR (11 downto 0) := "000000100000";
constant ap_ST_fsm_state7 : STD_LOGIC_VECTOR (11 downto 0) := "000001000000";
constant ap_ST_fsm_state8 : STD_LOGIC_VECTOR (11 downto 0) := "000010000000";
constant ap_ST_fsm_state9 : STD_LOGIC_VECTOR (11 downto 0) := "000100000000";
constant ap_ST_fsm_state10 : STD_LOGIC_VECTOR (11 downto 0) := "001000000000";
constant ap_ST_fsm_state11 : STD_LOGIC_VECTOR (11 downto 0) := "010000000000";
constant ap_ST_fsm_state12 : STD_LOGIC_VECTOR (11 downto 0) := "100000000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001100";
constant ap_const_lv32_D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001101";
constant ap_const_lv32_E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001110";
constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
constant ap_const_boolean_1 : BOOLEAN := true;
signal ap_CS_fsm : STD_LOGIC_VECTOR (11 downto 0) := "000000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal acc_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal acc_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal acc_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal acc_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal acc_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal acc_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal acc_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal acc_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal d_o_0_blk_n : STD_LOGIC;
signal ap_CS_fsm_state5 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state5 : signal is "none";
signal ap_CS_fsm_state6 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state6 : signal is "none";
signal ap_CS_fsm_state7 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state7 : signal is "none";
signal ap_CS_fsm_state8 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state8 : signal is "none";
signal ap_CS_fsm_state9 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state9 : signal is "none";
signal ap_CS_fsm_state10 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state10 : signal is "none";
signal ap_CS_fsm_state11 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state11 : signal is "none";
signal ap_CS_fsm_state12 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state12 : signal is "none";
signal d_o_1_blk_n : STD_LOGIC;
signal d_o_2_blk_n : STD_LOGIC;
signal d_o_3_blk_n : STD_LOGIC;
signal reg_410 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_CS_fsm_state2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
signal ap_CS_fsm_state4 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state4 : signal is "none";
signal ap_block_state6 : BOOLEAN;
signal ap_block_state8 : BOOLEAN;
signal ap_block_state10 : BOOLEAN;
signal reg_414 : STD_LOGIC_VECTOR (15 downto 0);
signal reg_418 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_block_state5 : BOOLEAN;
signal ap_block_state7 : BOOLEAN;
signal ap_block_state9 : BOOLEAN;
signal reg_423 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_CS_fsm_state3 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state3 : signal is "none";
signal reg_427 : STD_LOGIC_VECTOR (15 downto 0);
signal reg_431 : STD_LOGIC_VECTOR (15 downto 0);
signal reg_436 : STD_LOGIC_VECTOR (15 downto 0);
signal reg_440 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_8_fu_452_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_8_reg_1148 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp3_fu_466_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp3_reg_1169 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_1_1_fu_484_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_1_reg_1184 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_8_fu_494_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_8_reg_1195 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_15_fu_499_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_15_reg_1205 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp6_fu_543_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp6_reg_1216 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_1_2_fu_561_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_2_reg_1231 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_9_fu_571_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_9_reg_1242 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_16_fu_576_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_16_reg_1252 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp9_fu_626_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp9_reg_1263 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_1_3_fu_644_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_3_reg_1278 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_s_fu_654_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_s_reg_1289 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_17_fu_659_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_17_reg_1299 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp12_fu_709_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp12_reg_1310 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_1_4_fu_727_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_4_reg_1325 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_10_fu_737_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_10_reg_1336 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_18_fu_742_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_18_reg_1346 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp15_fu_792_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp15_reg_1357 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_1_5_fu_810_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_5_reg_1372 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_11_fu_820_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_11_reg_1383 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_19_fu_825_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_19_reg_1393 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp18_fu_875_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp18_reg_1404 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_1_6_fu_893_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_6_reg_1419 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_12_fu_903_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_12_reg_1425 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_20_fu_908_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_20_reg_1435 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp21_fu_958_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp21_reg_1441 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_1_7_fu_976_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_7_reg_1451 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_13_fu_986_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_13_reg_1457 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_21_fu_991_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_21_reg_1462 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp24_fu_1041_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp24_reg_1468 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_1_14_fu_1055_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_14_reg_1473 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_block_state11 : BOOLEAN;
signal tmp_1_22_fu_1060_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_22_reg_1478 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_block_state12 : BOOLEAN;
signal tmp_1_23_fu_586_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_24_fu_669_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_25_fu_752_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_26_fu_835_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_27_fu_918_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_28_fu_1001_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_29_fu_1066_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_30_fu_1102_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal temp_s_fu_527_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_1_fu_610_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_2_fu_693_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_3_fu_776_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_4_fu_859_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_5_fu_942_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_6_fu_1025_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_7_fu_1090_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_1_fu_448_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_16_cast_fu_458_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_24_cast_fu_462_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_9_fu_480_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_fu_472_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp3_cast_fu_514_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_8_cast_fu_490_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp2_fu_517_p2 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp2_cast_fu_523_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp1_fu_509_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_17_cast_fu_505_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_25_cast_fu_539_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_10_fu_557_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_s_fu_549_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp6_cast_fu_597_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_9_cast_fu_567_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp5_fu_600_p2 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp5_cast_fu_606_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp4_fu_592_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_18_cast_fu_582_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_26_cast_fu_622_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_11_fu_640_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_fu_632_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp9_cast_fu_680_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_10_cast_fu_650_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp8_fu_683_p2 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp8_cast_fu_689_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp7_fu_675_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_cast_fu_665_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_27_cast_fu_705_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_12_fu_723_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_fu_715_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp12_cast_fu_763_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_11_cast_fu_733_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp11_fu_766_p2 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp11_cast_fu_772_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp10_fu_758_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_cast_fu_748_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_28_cast_fu_788_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_13_fu_806_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_4_fu_798_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp15_cast_fu_846_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_12_cast_fu_816_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp14_fu_849_p2 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp14_cast_fu_855_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp13_fu_841_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_21_cast_fu_831_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_29_cast_fu_871_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_14_fu_889_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_5_fu_881_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp18_cast_fu_929_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_13_cast_fu_899_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp17_fu_932_p2 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp17_cast_fu_938_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp16_fu_924_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_22_cast_fu_914_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_30_cast_fu_954_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_15_fu_972_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_6_fu_964_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp21_cast_fu_1012_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_14_cast_fu_982_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp20_fu_1015_p2 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp20_cast_fu_1021_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp19_fu_1007_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_23_cast_fu_997_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_31_cast_fu_1037_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_7_fu_1047_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp24_cast_fu_1077_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_15_cast_fu_1051_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp23_fu_1080_p2 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp23_cast_fu_1086_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp22_fu_1072_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (11 downto 0);
signal ap_condition_145 : BOOLEAN;
begin
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
reg_418_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_const_logic_1 = ap_CS_fsm_state5) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state7) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state9) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))))) then
reg_418 <= d_i_1_q0;
elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then
reg_418 <= d_i_1_q1;
end if;
end if;
end process;
reg_431_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_const_logic_1 = ap_CS_fsm_state8) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state5) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))))) then
reg_431 <= d_i_1_q1;
elsif ((ap_const_logic_1 = ap_CS_fsm_state3)) then
reg_431 <= d_i_1_q0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state4)) then
acc_0 <= temp_s_fu_527_p2;
tmp6_reg_1216 <= tmp6_fu_543_p2;
tmp_1_15_reg_1205 <= tmp_1_15_fu_499_p2;
tmp_1_1_reg_1184 <= tmp_1_1_fu_484_p2;
tmp_1_8_reg_1195 <= tmp_1_8_fu_494_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state5) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n))))) then
acc_1 <= temp_1_fu_610_p2;
tmp9_reg_1263 <= tmp9_fu_626_p2;
tmp_1_16_reg_1252 <= tmp_1_16_fu_576_p2;
tmp_1_2_reg_1231 <= tmp_1_2_fu_561_p2;
tmp_1_9_reg_1242 <= tmp_1_9_fu_571_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state6) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n))))) then
acc_2 <= temp_2_fu_693_p2;
tmp12_reg_1310 <= tmp12_fu_709_p2;
tmp_1_17_reg_1299 <= tmp_1_17_fu_659_p2;
tmp_1_3_reg_1278 <= tmp_1_3_fu_644_p2;
tmp_1_s_reg_1289 <= tmp_1_s_fu_654_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state7) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n))))) then
acc_3 <= temp_3_fu_776_p2;
tmp15_reg_1357 <= tmp15_fu_792_p2;
tmp_1_10_reg_1336 <= tmp_1_10_fu_737_p2;
tmp_1_18_reg_1346 <= tmp_1_18_fu_742_p2;
tmp_1_4_reg_1325 <= tmp_1_4_fu_727_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state8) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n))))) then
acc_4 <= temp_4_fu_859_p2;
tmp18_reg_1404 <= tmp18_fu_875_p2;
tmp_1_11_reg_1383 <= tmp_1_11_fu_820_p2;
tmp_1_19_reg_1393 <= tmp_1_19_fu_825_p2;
tmp_1_5_reg_1372 <= tmp_1_5_fu_810_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state9) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n))))) then
acc_5 <= temp_5_fu_942_p2;
tmp21_reg_1441 <= tmp21_fu_958_p2;
tmp_1_12_reg_1425 <= tmp_1_12_fu_903_p2;
tmp_1_20_reg_1435 <= tmp_1_20_fu_908_p2;
tmp_1_6_reg_1419 <= tmp_1_6_fu_893_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state10) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n))))) then
acc_6 <= temp_6_fu_1025_p2;
tmp24_reg_1468 <= tmp24_fu_1041_p2;
tmp_1_13_reg_1457 <= tmp_1_13_fu_986_p2;
tmp_1_21_reg_1462 <= tmp_1_21_fu_991_p2;
tmp_1_7_reg_1451 <= tmp_1_7_fu_976_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state11) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n))))) then
acc_7 <= temp_7_fu_1090_p2;
tmp_1_14_reg_1473 <= tmp_1_14_fu_1055_p2;
tmp_1_22_reg_1478 <= tmp_1_22_fu_1060_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state2) or (ap_const_logic_1 = ap_CS_fsm_state4) or ((ap_const_logic_1 = ap_CS_fsm_state6) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state8) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state10) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))))) then
reg_410 <= d_i_0_q0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state2) or (ap_const_logic_1 = ap_CS_fsm_state4) or ((ap_const_logic_1 = ap_CS_fsm_state6) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state8) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))))) then
reg_414 <= d_i_1_q0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_const_logic_1 = ap_CS_fsm_state5) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state7) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state9) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or (ap_const_logic_1 = ap_CS_fsm_state3))) then
reg_423 <= d_i_0_q0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state4) or ((ap_const_logic_1 = ap_CS_fsm_state6) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state8) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state5) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state7) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state9) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or (ap_const_logic_1 = ap_CS_fsm_state3))) then
reg_427 <= d_i_0_q1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_const_logic_1 = ap_CS_fsm_state6) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state9) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or (ap_const_logic_1 = ap_CS_fsm_state3))) then
reg_436 <= d_i_1_q1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state4) or ((ap_const_logic_1 = ap_CS_fsm_state7) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))))) then
reg_440 <= d_i_1_q1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
tmp3_reg_1169 <= tmp3_fu_466_p2;
tmp_8_reg_1148 <= tmp_8_fu_452_p2;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n, ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, ap_CS_fsm_state8, ap_CS_fsm_state9, ap_CS_fsm_state10, ap_CS_fsm_state11, ap_CS_fsm_state12)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
ap_NS_fsm <= ap_ST_fsm_state3;
when ap_ST_fsm_state3 =>
ap_NS_fsm <= ap_ST_fsm_state4;
when ap_ST_fsm_state4 =>
ap_NS_fsm <= ap_ST_fsm_state5;
when ap_ST_fsm_state5 =>
if (((ap_const_logic_1 = ap_CS_fsm_state5) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n))))) then
ap_NS_fsm <= ap_ST_fsm_state6;
else
ap_NS_fsm <= ap_ST_fsm_state5;
end if;
when ap_ST_fsm_state6 =>
if (((ap_const_logic_1 = ap_CS_fsm_state6) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n))))) then
ap_NS_fsm <= ap_ST_fsm_state7;
else
ap_NS_fsm <= ap_ST_fsm_state6;
end if;
when ap_ST_fsm_state7 =>
if (((ap_const_logic_1 = ap_CS_fsm_state7) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n))))) then
ap_NS_fsm <= ap_ST_fsm_state8;
else
ap_NS_fsm <= ap_ST_fsm_state7;
end if;
when ap_ST_fsm_state8 =>
if (((ap_const_logic_1 = ap_CS_fsm_state8) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n))))) then
ap_NS_fsm <= ap_ST_fsm_state9;
else
ap_NS_fsm <= ap_ST_fsm_state8;
end if;
when ap_ST_fsm_state9 =>
if (((ap_const_logic_1 = ap_CS_fsm_state9) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n))))) then
ap_NS_fsm <= ap_ST_fsm_state10;
else
ap_NS_fsm <= ap_ST_fsm_state9;
end if;
when ap_ST_fsm_state10 =>
if (((ap_const_logic_1 = ap_CS_fsm_state10) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n))))) then
ap_NS_fsm <= ap_ST_fsm_state11;
else
ap_NS_fsm <= ap_ST_fsm_state10;
end if;
when ap_ST_fsm_state11 =>
if (((ap_const_logic_1 = ap_CS_fsm_state11) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n))))) then
ap_NS_fsm <= ap_ST_fsm_state12;
else
ap_NS_fsm <= ap_ST_fsm_state11;
end if;
when ap_ST_fsm_state12 =>
if (((ap_const_logic_1 = ap_CS_fsm_state12) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n))))) then
ap_NS_fsm <= ap_ST_fsm_state1;
else
ap_NS_fsm <= ap_ST_fsm_state12;
end if;
when others =>
ap_NS_fsm <= "XXXXXXXXXXXX";
end case;
end process;
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state10 <= ap_CS_fsm(9);
ap_CS_fsm_state11 <= ap_CS_fsm(10);
ap_CS_fsm_state12 <= ap_CS_fsm(11);
ap_CS_fsm_state2 <= ap_CS_fsm(1);
ap_CS_fsm_state3 <= ap_CS_fsm(2);
ap_CS_fsm_state4 <= ap_CS_fsm(3);
ap_CS_fsm_state5 <= ap_CS_fsm(4);
ap_CS_fsm_state6 <= ap_CS_fsm(5);
ap_CS_fsm_state7 <= ap_CS_fsm(6);
ap_CS_fsm_state8 <= ap_CS_fsm(7);
ap_CS_fsm_state9 <= ap_CS_fsm(8);
ap_block_state10_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n)
begin
ap_block_state10 <= ((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n));
end process;
ap_block_state11_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n)
begin
ap_block_state11 <= ((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n));
end process;
ap_block_state12_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n)
begin
ap_block_state12 <= ((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n));
end process;
ap_block_state5_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n)
begin
ap_block_state5 <= ((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n));
end process;
ap_block_state6_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n)
begin
ap_block_state6 <= ((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n));
end process;
ap_block_state7_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n)
begin
ap_block_state7 <= ((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n));
end process;
ap_block_state8_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n)
begin
ap_block_state8 <= ((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n));
end process;
ap_block_state9_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n)
begin
ap_block_state9 <= ((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n));
end process;
ap_condition_145_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n)
begin
ap_condition_145 <= not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)));
end process;
ap_done_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n, ap_CS_fsm_state12)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state12) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n))))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n, ap_CS_fsm_state12)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state12) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n))))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
d_i_0_address0_assign_proc : process(ap_CS_fsm_state1, ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, ap_CS_fsm_state8, ap_CS_fsm_state9, ap_CS_fsm_state2, ap_CS_fsm_state4, ap_CS_fsm_state3)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state9)) then
d_i_0_address0 <= ap_const_lv32_F(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state8)) then
d_i_0_address0 <= ap_const_lv32_7(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state7)) then
d_i_0_address0 <= ap_const_lv32_6(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state6)) then
d_i_0_address0 <= ap_const_lv32_5(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state5)) then
d_i_0_address0 <= ap_const_lv32_4(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state4)) then
d_i_0_address0 <= ap_const_lv32_3(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state3)) then
d_i_0_address0 <= ap_const_lv32_2(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then
d_i_0_address0 <= ap_const_lv32_1(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state1)) then
d_i_0_address0 <= ap_const_lv32_0(4 - 1 downto 0);
else
d_i_0_address0 <= "XXXX";
end if;
end process;
d_i_0_address1_assign_proc : process(ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, ap_CS_fsm_state8, ap_CS_fsm_state2, ap_CS_fsm_state4, ap_CS_fsm_state3)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state8)) then
d_i_0_address1 <= ap_const_lv32_E(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state7)) then
d_i_0_address1 <= ap_const_lv32_D(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state6)) then
d_i_0_address1 <= ap_const_lv32_C(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state5)) then
d_i_0_address1 <= ap_const_lv32_B(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state4)) then
d_i_0_address1 <= ap_const_lv32_A(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state3)) then
d_i_0_address1 <= ap_const_lv32_9(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then
d_i_0_address1 <= ap_const_lv32_8(4 - 1 downto 0);
else
d_i_0_address1 <= "XXXX";
end if;
end process;
d_i_0_ce0_assign_proc : process(ap_start, ap_CS_fsm_state1, d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n, ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, ap_CS_fsm_state8, ap_CS_fsm_state9, ap_CS_fsm_state2, ap_CS_fsm_state4, ap_CS_fsm_state3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) or (ap_const_logic_1 = ap_CS_fsm_state4) or ((ap_const_logic_1 = ap_CS_fsm_state6) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state8) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state5) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state7) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state9) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or (ap_const_logic_1 = ap_CS_fsm_state3) or ((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1)))) then
d_i_0_ce0 <= ap_const_logic_1;
else
d_i_0_ce0 <= ap_const_logic_0;
end if;
end process;
d_i_0_ce1_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n, ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, ap_CS_fsm_state8, ap_CS_fsm_state2, ap_CS_fsm_state4, ap_CS_fsm_state3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) or (ap_const_logic_1 = ap_CS_fsm_state4) or ((ap_const_logic_1 = ap_CS_fsm_state6) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state8) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state5) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state7) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or (ap_const_logic_1 = ap_CS_fsm_state3))) then
d_i_0_ce1 <= ap_const_logic_1;
else
d_i_0_ce1 <= ap_const_logic_0;
end if;
end process;
d_i_1_address0_assign_proc : process(ap_CS_fsm_state1, ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, ap_CS_fsm_state8, ap_CS_fsm_state2, ap_CS_fsm_state4, ap_CS_fsm_state3)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state8)) then
d_i_1_address0 <= ap_const_lv32_7(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state7)) then
d_i_1_address0 <= ap_const_lv32_6(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state6)) then
d_i_1_address0 <= ap_const_lv32_5(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state5)) then
d_i_1_address0 <= ap_const_lv32_4(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state4)) then
d_i_1_address0 <= ap_const_lv32_3(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state3)) then
d_i_1_address0 <= ap_const_lv32_2(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then
d_i_1_address0 <= ap_const_lv32_1(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state1)) then
d_i_1_address0 <= ap_const_lv32_0(4 - 1 downto 0);
else
d_i_1_address0 <= "XXXX";
end if;
end process;
d_i_1_address1_assign_proc : process(ap_CS_fsm_state1, ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, ap_CS_fsm_state8, ap_CS_fsm_state2, ap_CS_fsm_state4, ap_CS_fsm_state3)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state8)) then
d_i_1_address1 <= ap_const_lv32_F(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state7)) then
d_i_1_address1 <= ap_const_lv32_E(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state6)) then
d_i_1_address1 <= ap_const_lv32_D(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state5)) then
d_i_1_address1 <= ap_const_lv32_C(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state4)) then
d_i_1_address1 <= ap_const_lv32_B(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state3)) then
d_i_1_address1 <= ap_const_lv32_A(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then
d_i_1_address1 <= ap_const_lv32_9(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state1)) then
d_i_1_address1 <= ap_const_lv32_8(4 - 1 downto 0);
else
d_i_1_address1 <= "XXXX";
end if;
end process;
d_i_1_ce0_assign_proc : process(ap_start, ap_CS_fsm_state1, d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n, ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, ap_CS_fsm_state8, ap_CS_fsm_state2, ap_CS_fsm_state4, ap_CS_fsm_state3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) or (ap_const_logic_1 = ap_CS_fsm_state4) or ((ap_const_logic_1 = ap_CS_fsm_state6) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state8) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state5) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state7) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or (ap_const_logic_1 = ap_CS_fsm_state3) or ((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1)))) then
d_i_1_ce0 <= ap_const_logic_1;
else
d_i_1_ce0 <= ap_const_logic_0;
end if;
end process;
d_i_1_ce1_assign_proc : process(ap_start, ap_CS_fsm_state1, d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n, ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, ap_CS_fsm_state8, ap_CS_fsm_state2, ap_CS_fsm_state4, ap_CS_fsm_state3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) or (ap_const_logic_1 = ap_CS_fsm_state4) or ((ap_const_logic_1 = ap_CS_fsm_state6) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state8) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state5) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state7) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or (ap_const_logic_1 = ap_CS_fsm_state3) or ((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1)))) then
d_i_1_ce1 <= ap_const_logic_1;
else
d_i_1_ce1 <= ap_const_logic_0;
end if;
end process;
d_o_0_blk_n_assign_proc : process(d_o_0_full_n, ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, ap_CS_fsm_state8, ap_CS_fsm_state9, ap_CS_fsm_state10, ap_CS_fsm_state11, ap_CS_fsm_state12)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state5) or (ap_const_logic_1 = ap_CS_fsm_state6) or (ap_const_logic_1 = ap_CS_fsm_state7) or (ap_const_logic_1 = ap_CS_fsm_state8) or (ap_const_logic_1 = ap_CS_fsm_state9) or (ap_const_logic_1 = ap_CS_fsm_state10) or (ap_const_logic_1 = ap_CS_fsm_state11) or (ap_const_logic_1 = ap_CS_fsm_state12))) then
d_o_0_blk_n <= d_o_0_full_n;
else
d_o_0_blk_n <= ap_const_logic_1;
end if;
end process;
d_o_0_din_assign_proc : process(ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, ap_CS_fsm_state8, ap_CS_fsm_state9, ap_CS_fsm_state10, ap_CS_fsm_state11, ap_CS_fsm_state12, tmp_8_reg_1148, tmp_1_1_reg_1184, tmp_1_2_reg_1231, tmp_1_3_reg_1278, tmp_1_4_reg_1325, tmp_1_5_reg_1372, tmp_1_6_reg_1419, tmp_1_7_reg_1451, ap_condition_145)
begin
if ((ap_condition_145 = ap_const_boolean_1)) then
if ((ap_const_logic_1 = ap_CS_fsm_state12)) then
d_o_0_din <= tmp_1_7_reg_1451;
elsif ((ap_const_logic_1 = ap_CS_fsm_state11)) then
d_o_0_din <= tmp_1_6_reg_1419;
elsif ((ap_const_logic_1 = ap_CS_fsm_state10)) then
d_o_0_din <= tmp_1_5_reg_1372;
elsif ((ap_const_logic_1 = ap_CS_fsm_state9)) then
d_o_0_din <= tmp_1_4_reg_1325;
elsif ((ap_const_logic_1 = ap_CS_fsm_state8)) then
d_o_0_din <= tmp_1_3_reg_1278;
elsif ((ap_const_logic_1 = ap_CS_fsm_state7)) then
d_o_0_din <= tmp_1_2_reg_1231;
elsif ((ap_const_logic_1 = ap_CS_fsm_state6)) then
d_o_0_din <= tmp_1_1_reg_1184;
elsif ((ap_const_logic_1 = ap_CS_fsm_state5)) then
d_o_0_din <= tmp_8_reg_1148;
else
d_o_0_din <= "XXXXXXXXXXXXXXXX";
end if;
else
d_o_0_din <= "XXXXXXXXXXXXXXXX";
end if;
end process;
d_o_0_write_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n, ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, ap_CS_fsm_state8, ap_CS_fsm_state9, ap_CS_fsm_state10, ap_CS_fsm_state11, ap_CS_fsm_state12)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_state6) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state8) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state10) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state5) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state7) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state9) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state11) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state12) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))))) then
d_o_0_write <= ap_const_logic_1;
else
d_o_0_write <= ap_const_logic_0;
end if;
end process;
d_o_1_blk_n_assign_proc : process(d_o_1_full_n, ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, ap_CS_fsm_state8, ap_CS_fsm_state9, ap_CS_fsm_state10, ap_CS_fsm_state11, ap_CS_fsm_state12)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state5) or (ap_const_logic_1 = ap_CS_fsm_state6) or (ap_const_logic_1 = ap_CS_fsm_state7) or (ap_const_logic_1 = ap_CS_fsm_state8) or (ap_const_logic_1 = ap_CS_fsm_state9) or (ap_const_logic_1 = ap_CS_fsm_state10) or (ap_const_logic_1 = ap_CS_fsm_state11) or (ap_const_logic_1 = ap_CS_fsm_state12))) then
d_o_1_blk_n <= d_o_1_full_n;
else
d_o_1_blk_n <= ap_const_logic_1;
end if;
end process;
d_o_1_din_assign_proc : process(ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, ap_CS_fsm_state8, ap_CS_fsm_state9, ap_CS_fsm_state10, ap_CS_fsm_state11, ap_CS_fsm_state12, tmp_1_8_reg_1195, tmp_1_9_reg_1242, tmp_1_s_reg_1289, tmp_1_10_reg_1336, tmp_1_11_reg_1383, tmp_1_12_reg_1425, tmp_1_13_reg_1457, tmp_1_14_reg_1473, ap_condition_145)
begin
if ((ap_condition_145 = ap_const_boolean_1)) then
if ((ap_const_logic_1 = ap_CS_fsm_state12)) then
d_o_1_din <= tmp_1_14_reg_1473;
elsif ((ap_const_logic_1 = ap_CS_fsm_state11)) then
d_o_1_din <= tmp_1_13_reg_1457;
elsif ((ap_const_logic_1 = ap_CS_fsm_state10)) then
d_o_1_din <= tmp_1_12_reg_1425;
elsif ((ap_const_logic_1 = ap_CS_fsm_state9)) then
d_o_1_din <= tmp_1_11_reg_1383;
elsif ((ap_const_logic_1 = ap_CS_fsm_state8)) then
d_o_1_din <= tmp_1_10_reg_1336;
elsif ((ap_const_logic_1 = ap_CS_fsm_state7)) then
d_o_1_din <= tmp_1_s_reg_1289;
elsif ((ap_const_logic_1 = ap_CS_fsm_state6)) then
d_o_1_din <= tmp_1_9_reg_1242;
elsif ((ap_const_logic_1 = ap_CS_fsm_state5)) then
d_o_1_din <= tmp_1_8_reg_1195;
else
d_o_1_din <= "XXXXXXXXXXXXXXXX";
end if;
else
d_o_1_din <= "XXXXXXXXXXXXXXXX";
end if;
end process;
d_o_1_write_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n, ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, ap_CS_fsm_state8, ap_CS_fsm_state9, ap_CS_fsm_state10, ap_CS_fsm_state11, ap_CS_fsm_state12)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_state6) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state8) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state10) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state5) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state7) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state9) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state11) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state12) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))))) then
d_o_1_write <= ap_const_logic_1;
else
d_o_1_write <= ap_const_logic_0;
end if;
end process;
d_o_2_blk_n_assign_proc : process(d_o_2_full_n, ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, ap_CS_fsm_state8, ap_CS_fsm_state9, ap_CS_fsm_state10, ap_CS_fsm_state11, ap_CS_fsm_state12)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state5) or (ap_const_logic_1 = ap_CS_fsm_state6) or (ap_const_logic_1 = ap_CS_fsm_state7) or (ap_const_logic_1 = ap_CS_fsm_state8) or (ap_const_logic_1 = ap_CS_fsm_state9) or (ap_const_logic_1 = ap_CS_fsm_state10) or (ap_const_logic_1 = ap_CS_fsm_state11) or (ap_const_logic_1 = ap_CS_fsm_state12))) then
d_o_2_blk_n <= d_o_2_full_n;
else
d_o_2_blk_n <= ap_const_logic_1;
end if;
end process;
d_o_2_din_assign_proc : process(ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, ap_CS_fsm_state8, ap_CS_fsm_state9, ap_CS_fsm_state10, ap_CS_fsm_state11, ap_CS_fsm_state12, tmp_1_15_reg_1205, tmp_1_16_reg_1252, tmp_1_17_reg_1299, tmp_1_18_reg_1346, tmp_1_19_reg_1393, tmp_1_20_reg_1435, tmp_1_21_reg_1462, tmp_1_22_reg_1478, ap_condition_145)
begin
if ((ap_condition_145 = ap_const_boolean_1)) then
if ((ap_const_logic_1 = ap_CS_fsm_state12)) then
d_o_2_din <= tmp_1_22_reg_1478;
elsif ((ap_const_logic_1 = ap_CS_fsm_state11)) then
d_o_2_din <= tmp_1_21_reg_1462;
elsif ((ap_const_logic_1 = ap_CS_fsm_state10)) then
d_o_2_din <= tmp_1_20_reg_1435;
elsif ((ap_const_logic_1 = ap_CS_fsm_state9)) then
d_o_2_din <= tmp_1_19_reg_1393;
elsif ((ap_const_logic_1 = ap_CS_fsm_state8)) then
d_o_2_din <= tmp_1_18_reg_1346;
elsif ((ap_const_logic_1 = ap_CS_fsm_state7)) then
d_o_2_din <= tmp_1_17_reg_1299;
elsif ((ap_const_logic_1 = ap_CS_fsm_state6)) then
d_o_2_din <= tmp_1_16_reg_1252;
elsif ((ap_const_logic_1 = ap_CS_fsm_state5)) then
d_o_2_din <= tmp_1_15_reg_1205;
else
d_o_2_din <= "XXXXXXXXXXXXXXXX";
end if;
else
d_o_2_din <= "XXXXXXXXXXXXXXXX";
end if;
end process;
d_o_2_write_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n, ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, ap_CS_fsm_state8, ap_CS_fsm_state9, ap_CS_fsm_state10, ap_CS_fsm_state11, ap_CS_fsm_state12)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_state6) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state8) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state10) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state5) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state7) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state9) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state11) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state12) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))))) then
d_o_2_write <= ap_const_logic_1;
else
d_o_2_write <= ap_const_logic_0;
end if;
end process;
d_o_3_blk_n_assign_proc : process(d_o_3_full_n, ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, ap_CS_fsm_state8, ap_CS_fsm_state9, ap_CS_fsm_state10, ap_CS_fsm_state11, ap_CS_fsm_state12)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state5) or (ap_const_logic_1 = ap_CS_fsm_state6) or (ap_const_logic_1 = ap_CS_fsm_state7) or (ap_const_logic_1 = ap_CS_fsm_state8) or (ap_const_logic_1 = ap_CS_fsm_state9) or (ap_const_logic_1 = ap_CS_fsm_state10) or (ap_const_logic_1 = ap_CS_fsm_state11) or (ap_const_logic_1 = ap_CS_fsm_state12))) then
d_o_3_blk_n <= d_o_3_full_n;
else
d_o_3_blk_n <= ap_const_logic_1;
end if;
end process;
d_o_3_din_assign_proc : process(ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, ap_CS_fsm_state8, ap_CS_fsm_state9, ap_CS_fsm_state10, ap_CS_fsm_state11, ap_CS_fsm_state12, tmp_1_23_fu_586_p2, tmp_1_24_fu_669_p2, tmp_1_25_fu_752_p2, tmp_1_26_fu_835_p2, tmp_1_27_fu_918_p2, tmp_1_28_fu_1001_p2, tmp_1_29_fu_1066_p2, tmp_1_30_fu_1102_p2, ap_condition_145)
begin
if ((ap_condition_145 = ap_const_boolean_1)) then
if ((ap_const_logic_1 = ap_CS_fsm_state12)) then
d_o_3_din <= tmp_1_30_fu_1102_p2;
elsif ((ap_const_logic_1 = ap_CS_fsm_state11)) then
d_o_3_din <= tmp_1_29_fu_1066_p2;
elsif ((ap_const_logic_1 = ap_CS_fsm_state10)) then
d_o_3_din <= tmp_1_28_fu_1001_p2;
elsif ((ap_const_logic_1 = ap_CS_fsm_state9)) then
d_o_3_din <= tmp_1_27_fu_918_p2;
elsif ((ap_const_logic_1 = ap_CS_fsm_state8)) then
d_o_3_din <= tmp_1_26_fu_835_p2;
elsif ((ap_const_logic_1 = ap_CS_fsm_state7)) then
d_o_3_din <= tmp_1_25_fu_752_p2;
elsif ((ap_const_logic_1 = ap_CS_fsm_state6)) then
d_o_3_din <= tmp_1_24_fu_669_p2;
elsif ((ap_const_logic_1 = ap_CS_fsm_state5)) then
d_o_3_din <= tmp_1_23_fu_586_p2;
else
d_o_3_din <= "XXXXXXXXXXXXXXXX";
end if;
else
d_o_3_din <= "XXXXXXXXXXXXXXXX";
end if;
end process;
d_o_3_write_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n, ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, ap_CS_fsm_state8, ap_CS_fsm_state9, ap_CS_fsm_state10, ap_CS_fsm_state11, ap_CS_fsm_state12)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_state6) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state8) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state10) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state5) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state7) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state9) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state11) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state12) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))))) then
d_o_3_write <= ap_const_logic_1;
else
d_o_3_write <= ap_const_logic_0;
end if;
end process;
temp_1_fu_610_p2 <= std_logic_vector(signed(tmp5_cast_fu_606_p1) + signed(tmp4_fu_592_p2));
temp_2_fu_693_p2 <= std_logic_vector(signed(tmp8_cast_fu_689_p1) + signed(tmp7_fu_675_p2));
temp_3_fu_776_p2 <= std_logic_vector(signed(tmp11_cast_fu_772_p1) + signed(tmp10_fu_758_p2));
temp_4_fu_859_p2 <= std_logic_vector(signed(tmp14_cast_fu_855_p1) + signed(tmp13_fu_841_p2));
temp_5_fu_942_p2 <= std_logic_vector(signed(tmp17_cast_fu_938_p1) + signed(tmp16_fu_924_p2));
temp_6_fu_1025_p2 <= std_logic_vector(signed(tmp20_cast_fu_1021_p1) + signed(tmp19_fu_1007_p2));
temp_7_fu_1090_p2 <= std_logic_vector(signed(tmp23_cast_fu_1086_p1) + signed(tmp22_fu_1072_p2));
temp_s_fu_527_p2 <= std_logic_vector(signed(tmp2_cast_fu_523_p1) + signed(tmp1_fu_509_p2));
tmp10_fu_758_p2 <= std_logic_vector(unsigned(acc_3) + unsigned(tmp_3_fu_715_p1));
tmp11_cast_fu_772_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp11_fu_766_p2),32));
tmp11_fu_766_p2 <= std_logic_vector(signed(tmp12_cast_fu_763_p1) + signed(tmp_11_cast_fu_733_p1));
tmp12_cast_fu_763_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp12_reg_1310),18));
tmp12_fu_709_p2 <= std_logic_vector(signed(tmp_19_cast_fu_665_p1) + signed(tmp_27_cast_fu_705_p1));
tmp13_fu_841_p2 <= std_logic_vector(unsigned(acc_4) + unsigned(tmp_4_fu_798_p1));
tmp14_cast_fu_855_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp14_fu_849_p2),32));
tmp14_fu_849_p2 <= std_logic_vector(signed(tmp15_cast_fu_846_p1) + signed(tmp_12_cast_fu_816_p1));
tmp15_cast_fu_846_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp15_reg_1357),18));
tmp15_fu_792_p2 <= std_logic_vector(signed(tmp_20_cast_fu_748_p1) + signed(tmp_28_cast_fu_788_p1));
tmp16_fu_924_p2 <= std_logic_vector(unsigned(acc_5) + unsigned(tmp_5_fu_881_p1));
tmp17_cast_fu_938_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp17_fu_932_p2),32));
tmp17_fu_932_p2 <= std_logic_vector(signed(tmp18_cast_fu_929_p1) + signed(tmp_13_cast_fu_899_p1));
tmp18_cast_fu_929_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp18_reg_1404),18));
tmp18_fu_875_p2 <= std_logic_vector(signed(tmp_21_cast_fu_831_p1) + signed(tmp_29_cast_fu_871_p1));
tmp19_fu_1007_p2 <= std_logic_vector(unsigned(acc_6) + unsigned(tmp_6_fu_964_p1));
tmp1_fu_509_p2 <= std_logic_vector(unsigned(acc_0) + unsigned(tmp_fu_472_p1));
tmp20_cast_fu_1021_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp20_fu_1015_p2),32));
tmp20_fu_1015_p2 <= std_logic_vector(signed(tmp21_cast_fu_1012_p1) + signed(tmp_14_cast_fu_982_p1));
tmp21_cast_fu_1012_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp21_reg_1441),18));
tmp21_fu_958_p2 <= std_logic_vector(signed(tmp_22_cast_fu_914_p1) + signed(tmp_30_cast_fu_954_p1));
tmp22_fu_1072_p2 <= std_logic_vector(unsigned(acc_7) + unsigned(tmp_7_fu_1047_p1));
tmp23_cast_fu_1086_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp23_fu_1080_p2),32));
tmp23_fu_1080_p2 <= std_logic_vector(signed(tmp24_cast_fu_1077_p1) + signed(tmp_15_cast_fu_1051_p1));
tmp24_cast_fu_1077_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp24_reg_1468),18));
tmp24_fu_1041_p2 <= std_logic_vector(signed(tmp_23_cast_fu_997_p1) + signed(tmp_31_cast_fu_1037_p1));
tmp2_cast_fu_523_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp2_fu_517_p2),32));
tmp2_fu_517_p2 <= std_logic_vector(signed(tmp3_cast_fu_514_p1) + signed(tmp_8_cast_fu_490_p1));
tmp3_cast_fu_514_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp3_reg_1169),18));
tmp3_fu_466_p2 <= std_logic_vector(signed(tmp_16_cast_fu_458_p1) + signed(tmp_24_cast_fu_462_p1));
tmp4_fu_592_p2 <= std_logic_vector(unsigned(acc_1) + unsigned(tmp_s_fu_549_p1));
tmp5_cast_fu_606_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp5_fu_600_p2),32));
tmp5_fu_600_p2 <= std_logic_vector(signed(tmp6_cast_fu_597_p1) + signed(tmp_9_cast_fu_567_p1));
tmp6_cast_fu_597_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp6_reg_1216),18));
tmp6_fu_543_p2 <= std_logic_vector(signed(tmp_17_cast_fu_505_p1) + signed(tmp_25_cast_fu_539_p1));
tmp7_fu_675_p2 <= std_logic_vector(unsigned(acc_2) + unsigned(tmp_2_fu_632_p1));
tmp8_cast_fu_689_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp8_fu_683_p2),32));
tmp8_fu_683_p2 <= std_logic_vector(signed(tmp9_cast_fu_680_p1) + signed(tmp_10_cast_fu_650_p1));
tmp9_cast_fu_680_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp9_reg_1263),18));
tmp9_fu_626_p2 <= std_logic_vector(signed(tmp_18_cast_fu_582_p1) + signed(tmp_26_cast_fu_622_p1));
tmp_10_cast_fu_650_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_427),18));
tmp_10_fu_557_p1 <= acc_2(16 - 1 downto 0);
tmp_11_cast_fu_733_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_427),18));
tmp_11_fu_640_p1 <= acc_3(16 - 1 downto 0);
tmp_12_cast_fu_816_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_427),18));
tmp_12_fu_723_p1 <= acc_4(16 - 1 downto 0);
tmp_13_cast_fu_899_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_427),18));
tmp_13_fu_806_p1 <= acc_5(16 - 1 downto 0);
tmp_14_cast_fu_982_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_427),18));
tmp_14_fu_889_p1 <= acc_6(16 - 1 downto 0);
tmp_15_cast_fu_1051_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_410),18));
tmp_15_fu_972_p1 <= acc_7(16 - 1 downto 0);
tmp_16_cast_fu_458_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_414),17));
tmp_17_cast_fu_505_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_431),17));
tmp_18_cast_fu_582_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_414),17));
tmp_19_cast_fu_665_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_418),17));
tmp_1_10_fu_737_p2 <= std_logic_vector(unsigned(reg_427) + unsigned(tmp_1_3_reg_1278));
tmp_1_11_fu_820_p2 <= std_logic_vector(unsigned(reg_427) + unsigned(tmp_1_4_reg_1325));
tmp_1_12_fu_903_p2 <= std_logic_vector(unsigned(reg_427) + unsigned(tmp_1_5_reg_1372));
tmp_1_13_fu_986_p2 <= std_logic_vector(unsigned(reg_427) + unsigned(tmp_1_6_reg_1419));
tmp_1_14_fu_1055_p2 <= std_logic_vector(unsigned(reg_410) + unsigned(tmp_1_7_reg_1451));
tmp_1_15_fu_499_p2 <= std_logic_vector(unsigned(reg_414) + unsigned(tmp_1_8_fu_494_p2));
tmp_1_16_fu_576_p2 <= std_logic_vector(unsigned(reg_431) + unsigned(tmp_1_9_fu_571_p2));
tmp_1_17_fu_659_p2 <= std_logic_vector(unsigned(reg_414) + unsigned(tmp_1_s_fu_654_p2));
tmp_1_18_fu_742_p2 <= std_logic_vector(unsigned(reg_418) + unsigned(tmp_1_10_fu_737_p2));
tmp_1_19_fu_825_p2 <= std_logic_vector(unsigned(reg_414) + unsigned(tmp_1_11_fu_820_p2));
tmp_1_1_fu_484_p2 <= std_logic_vector(unsigned(reg_423) + unsigned(tmp_9_fu_480_p1));
tmp_1_20_fu_908_p2 <= std_logic_vector(unsigned(reg_418) + unsigned(tmp_1_12_fu_903_p2));
tmp_1_21_fu_991_p2 <= std_logic_vector(unsigned(reg_414) + unsigned(tmp_1_13_fu_986_p2));
tmp_1_22_fu_1060_p2 <= std_logic_vector(unsigned(reg_418) + unsigned(tmp_1_14_fu_1055_p2));
tmp_1_23_fu_586_p2 <= std_logic_vector(unsigned(reg_418) + unsigned(tmp_1_15_reg_1205));
tmp_1_24_fu_669_p2 <= std_logic_vector(unsigned(reg_436) + unsigned(tmp_1_16_reg_1252));
tmp_1_25_fu_752_p2 <= std_logic_vector(unsigned(reg_440) + unsigned(tmp_1_17_reg_1299));
tmp_1_26_fu_835_p2 <= std_logic_vector(unsigned(reg_431) + unsigned(tmp_1_18_reg_1346));
tmp_1_27_fu_918_p2 <= std_logic_vector(unsigned(reg_436) + unsigned(tmp_1_19_reg_1393));
tmp_1_28_fu_1001_p2 <= std_logic_vector(unsigned(reg_440) + unsigned(tmp_1_20_reg_1435));
tmp_1_29_fu_1066_p2 <= std_logic_vector(unsigned(reg_431) + unsigned(tmp_1_21_reg_1462));
tmp_1_2_fu_561_p2 <= std_logic_vector(unsigned(reg_410) + unsigned(tmp_10_fu_557_p1));
tmp_1_30_fu_1102_p2 <= std_logic_vector(unsigned(reg_436) + unsigned(tmp_1_22_reg_1478));
tmp_1_3_fu_644_p2 <= std_logic_vector(unsigned(reg_423) + unsigned(tmp_11_fu_640_p1));
tmp_1_4_fu_727_p2 <= std_logic_vector(unsigned(reg_410) + unsigned(tmp_12_fu_723_p1));
tmp_1_5_fu_810_p2 <= std_logic_vector(unsigned(reg_423) + unsigned(tmp_13_fu_806_p1));
tmp_1_6_fu_893_p2 <= std_logic_vector(unsigned(reg_410) + unsigned(tmp_14_fu_889_p1));
tmp_1_7_fu_976_p2 <= std_logic_vector(unsigned(reg_423) + unsigned(tmp_15_fu_972_p1));
tmp_1_8_fu_494_p2 <= std_logic_vector(unsigned(reg_427) + unsigned(tmp_8_reg_1148));
tmp_1_9_fu_571_p2 <= std_logic_vector(unsigned(reg_427) + unsigned(tmp_1_1_reg_1184));
tmp_1_fu_448_p1 <= acc_0(16 - 1 downto 0);
tmp_1_s_fu_654_p2 <= std_logic_vector(unsigned(reg_427) + unsigned(tmp_1_2_reg_1231));
tmp_20_cast_fu_748_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_414),17));
tmp_21_cast_fu_831_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_418),17));
tmp_22_cast_fu_914_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_414),17));
tmp_23_cast_fu_997_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_418),17));
tmp_24_cast_fu_462_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_418),17));
tmp_25_cast_fu_539_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_436),17));
tmp_26_cast_fu_622_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_440),17));
tmp_27_cast_fu_705_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_431),17));
tmp_28_cast_fu_788_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_436),17));
tmp_29_cast_fu_871_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_440),17));
tmp_2_fu_632_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_410),32));
tmp_30_cast_fu_954_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_431),17));
tmp_31_cast_fu_1037_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_436),17));
tmp_3_fu_715_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_423),32));
tmp_4_fu_798_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_410),32));
tmp_5_fu_881_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_423),32));
tmp_6_fu_964_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_410),32));
tmp_7_fu_1047_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_423),32));
tmp_8_cast_fu_490_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_427),18));
tmp_8_fu_452_p2 <= std_logic_vector(unsigned(reg_410) + unsigned(tmp_1_fu_448_p1));
tmp_9_cast_fu_567_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_427),18));
tmp_9_fu_480_p1 <= acc_1(16 - 1 downto 0);
tmp_fu_472_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_410),32));
tmp_s_fu_549_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_423),32));
end behav;
| mit | fc7ac5432dca9136264dc1a56d76cc6d | 0.592658 | 2.501239 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/tech/altera/simprims/altera_primitives_components.vhd | 2 | 14,655 | -- Copyright (C) 1991-2009 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 9.0 Build 235 03/01/2009
----------------------------------------------------------------------------
-- ALtera Primitives Component Declaration File
----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
package dffeas_pack is
-- default generic values
CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns);
CONSTANT DefSetupHoldCnst : TIME := 0 ns;
CONSTANT DefPulseWdthCnst : TIME := 0 ns;
CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;
CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;
CONSTANT DefGlitchXOn : BOOLEAN := FALSE;
CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;
CONSTANT DefXOnChecks : BOOLEAN := TRUE;
end dffeas_pack;
library ieee;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.dffeas_pack.all;
package altera_primitives_components is
component carry
port (
a_in : in std_logic;
a_out : out std_logic );
end component;
component cascade
port (
a_in : in std_logic;
a_out : out std_logic );
end component;
component global
port (
a_in : in std_logic;
a_out : out std_logic);
end component;
component tri
port(
a_in : in std_logic;
oe : in std_logic;
a_out : out std_logic);
end component;
component carry_sum
port (
sin : in std_logic;
cin : in std_logic;
sout : out std_logic;
cout : out std_logic );
end component;
component exp
port (
a_in : in std_logic;
a_out : out std_logic);
end component;
component soft
port (
a_in : in std_logic;
a_out : out std_logic );
end component;
component opndrn
port (
a_in : in std_logic;
a_out : out std_logic );
end component;
component row_global
port (
a_in : in std_logic;
a_out : out std_logic );
end component;
component lut_input
port(
a_in : in std_logic;
a_out : out std_logic);
end component;
component lut_output
port(
a_in : in std_logic;
a_out : out std_logic);
end component;
component dlatch
port(
d : in std_logic;
ena : in std_logic;
clrn : in std_logic;
prn : in std_logic;
q : out std_logic);
end component;
component latch
port(
d : in std_logic;
ena : in std_logic;
q : out std_logic);
end component;
component dff
port(
d, clk, clrn, prn : in std_logic;
q : out std_logic);
end component;
component dffe
port(
d, clk, ena, clrn, prn : in std_logic;
q : out std_logic);
end component;
component dffea
port(
d, clk, ena, clrn, prn, aload, adata : in std_logic;
q : out std_logic);
end component;
component dffeas
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*" );
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic );
end component;
component tff
port(
t, clk, clrn, prn : in std_logic;
q : out std_logic);
end component;
component tffe
port(
t, clk, ena, clrn, prn : in std_logic;
q : out std_logic);
end component;
component jkff
port(
j, k, clk, clrn, prn : in std_logic;
q : out std_logic);
end component;
component jkffe
port(
j, k, clk, ena, clrn, prn : in std_logic;
q : out std_logic);
end component;
component srff
port(
s, r, clk, clrn, prn : in std_logic;
q : out std_logic);
end component;
component srffe
port(
s, r, clk, ena, clrn, prn : in std_logic;
q : out std_logic);
end component;
component clklock
generic(
input_frequency : natural := 10000;
clockboost : natural := 1);
port(
inclk : in std_logic;
outclk : out std_logic);
end component;
component alt_inbuf
generic(
io_standard : string := "NONE";
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
lpm_type : string := "alt_inbuf" );
port(
i : in std_logic;
o : out std_logic);
end component;
component alt_outbuf
generic(
io_standard : string := "NONE";
current_strength : string := "NONE";
current_strength_new : string := "NONE";
slew_rate : integer := -1;
slow_slew_rate : string := "NONE";
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
lpm_type : string := "alt_outbuf" );
port(
i : in std_logic;
o : out std_logic);
end component;
component alt_outbuf_tri
generic(
io_standard : string := "NONE";
current_strength : string := "NONE";
current_strength_new : string := "NONE";
slew_rate : integer := -1;
slow_slew_rate : string := "NONE";
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
lpm_type : string := "alt_outbuf_tri" );
port(
i : in std_logic;
oe : in std_logic;
o : out std_logic);
end component;
component alt_iobuf
generic(
io_standard : string := "NONE";
current_strength : string := "NONE";
current_strength_new : string := "NONE";
slew_rate : integer := -1;
slow_slew_rate : string := "NONE";
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
input_termination : string := "NONE";
output_termination : string := "NONE";
lpm_type : string := "alt_iobuf" );
port(
i : in std_logic;
oe : in std_logic;
io : inout std_logic;
o : out std_logic);
end component;
component alt_inbuf_diff
generic(
io_standard : string := "NONE";
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
lpm_type : string := "alt_inbuf_diff" );
port(
i : in std_logic;
ibar : in std_logic;
o : out std_logic);
end component;
component alt_outbuf_diff
generic (
io_standard : string := "NONE";
current_strength : string := "NONE";
current_strength_new : string := "NONE";
slew_rate : integer := -1;
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
lpm_type : string := "alt_outbuf_diff" );
port(
i : in std_logic;
o : out std_logic;
obar : out std_logic );
end component;
component alt_outbuf_tri_diff
generic (
io_standard : string := "NONE";
current_strength : string := "NONE";
current_strength_new : string := "NONE";
slew_rate : integer := -1;
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
lpm_type : string := "alt_outbuf_tri_diff" );
port(
i : in std_logic;
oe : in std_logic;
o : out std_logic;
obar : out std_logic );
end component;
component alt_iobuf_diff
generic (
io_standard : string := "NONE";
current_strength : string := "NONE";
current_strength_new : string := "NONE";
slew_rate : integer := -1;
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
input_termination : string := "NONE";
output_termination : string := "NONE";
lpm_type : string := "alt_iobuf_diff" );
port(
i : in std_logic;
oe : in std_logic;
io : inout std_logic;
iobar : inout std_logic;
o : out std_logic );
end component;
component alt_bidir_diff
generic (
io_standard : string := "NONE";
current_strength : string := "NONE";
current_strength_new : string := "NONE";
slew_rate : integer := -1;
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
input_termination : string := "NONE";
output_termination : string := "NONE";
lpm_type : string := "alt_bidir_diff" );
port(
oe : in std_logic;
bidirin : inout std_logic;
io : inout std_logic;
iobar : inout std_logic );
end component;
component alt_bidir_buf
generic (
io_standard : string := "NONE";
current_strength : string := "NONE";
current_strength_new : string := "NONE";
slew_rate : integer := -1;
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
input_termination : string := "NONE";
output_termination : string := "NONE";
lpm_type : string := "alt_bidir_buf" );
port(
oe : in std_logic;
bidirin : inout std_logic;
io : inout std_logic );
end component;
end altera_primitives_components;
| gpl-2.0 | 680d72f41f8d9623587721bc8e13afe4 | 0.511293 | 3.972621 | false | false | false | false |
VerkhovtsovPavel/BSUIR_Labs | Master/POCP/My_Designs/Accum/src/TestBench/mrom_TB.vhd | 1 | 1,406 | library accum;
use accum.OneHotAccum.all;
library ieee;
use ieee.STD_LOGIC_UNSIGNED.all;
use ieee.std_logic_1164.all;
-- Add your library and packages declaration here ...
entity mrom_tb is
end mrom_tb;
architecture TB_ARCHITECTURE of mrom_tb is
-- Component declaration of the tested unit
component mrom
port(
RE : in STD_LOGIC;
ADDR : in mem_addr;
DOUT : out command );
end component;
-- Stimulus signals - signals mapped to the input and inout ports of tested entity
signal RE : STD_LOGIC;
signal ADDR : mem_addr;
-- Observed signals - signals mapped to the output ports of tested entity
signal DOUT : command;
-- Add your code here ...
constant WAIT_period: time := 10 ns;
begin
-- Unit Under Test port map
UUT : mrom
port map (
RE => RE,
ADDR => ADDR,
DOUT => DOUT
);
-- Add your stimulus here ...
main: process
begin
re <= '0';
addr <= "00010";
wait for 1 * WAIT_period;
re <= '1';
wait for 1 * WAIT_period;
addr <= "00000";
re <= '1';
wait for 1 * WAIT_period;
re <= '0';
wait for 100 * WAIT_period;
wait;
end process;
end TB_ARCHITECTURE;
configuration TESTBENCH_FOR_mrom of mrom_tb is
for TB_ARCHITECTURE
for UUT : mrom
use entity work.mrom(beh);
end for;
end for;
end TESTBENCH_FOR_mrom;
| mit | db639f474a1cf8a2588c25fed8808657 | 0.608108 | 3.446078 | false | true | false | false |
a4a881d4/ringbus4xilinx | src/bus/busEP.vhd | 2 | 2,811 | ---------------------------------------------------------------------------------------------------
--
-- Title : Bus End Point
-- Design : Ring Bus
-- Author : Zhao Ming
-- Company : a4a881d4
--
---------------------------------------------------------------------------------------------------
--
-- File : busEP.vhd
-- Generated : 2013/9/5
-- From :
-- By :
--
---------------------------------------------------------------------------------------------------
--
-- Description : Ring bus end point
--
-- Rev: 3.1
--
---------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library work;
use work.rb_config.all;
entity BUSEP is
generic(
Bwidth : natural := 128;
POS : integer := 1
);
port(
-- send to bus
tx: in std_logic_vector(Bwidth-1 downto 0);
Req : in std_logic;
tx_sop : out std_logic;
-- read from bus
rx_sop : out std_logic;
rx: out std_logic_vector(Bwidth-1 downto 0);
-- Ring Bus internal signal
clk : in STD_LOGIC;
rst : in STD_LOGIC;
fin : in std_logic;
D : in STD_LOGIC_VECTOR(Bwidth-1 downto 0);
Q : out STD_LOGIC_VECTOR(Bwidth-1 downto 0);
fout : out std_logic
--
);
end BUSEP;
architecture behave of BUSEP is
signal inCommand : std_logic_vector( command_end downto command_start ) := (others => '0');
signal inDBUS : std_logic_vector( dbusid_end downto dbusid_start ) := (others => '0');
signal inAddr : std_logic_vector( daddr_end downto daddr_start ) := (others => '0');
signal hold : std_logic := '0';
signal tx_sop_i : std_logic := '0';
signal rx_sop_i : std_logic := '0';
begin
inCommand <= D( command_end downto command_start );
inAddr <= D( daddr_end downto daddr_start );
inDBus <= D( dbusid_end downto dbusid_start );
tx_sop<=tx_sop_i;
rx_sop<=rx_sop_i;
rx<=D;
rx_sop_i<='1' when fin='1' and inDBus=zeros(dbusid_end downto dbusid_start) and inAddr=POS and inCommand/=command_idle else '0';
tx_sop_i<='1' when fin='1' and Req='1' and ( inCommand=command_idle or rx_sop_i='1') else '0';
busP:process(clk,rst)
begin
if rst='1' then
Q<=(others => '0');
hold<='0';
fout<='0';
elsif rising_edge(clk) then
if fin='1' then
if tx_sop_i='1' then
Q<=tx;
elsif rx_sop_i='1' then
Q( Bwidth-1 downto daddr_start )<=D( Bwidth-1 downto daddr_start );
Q( command_end downto command_start )<=command_idle;
else
Q<=D;
end if;
if tx_sop_i='1' then
hold<='1';
else
hold<='0';
end if;
elsif hold='1' then
Q<=tx;
end if;
fout<=fin;
end if;
end process;
end behave;
| gpl-2.0 | 3073d86e00c25bb3086c3dbf5ad78b49 | 0.502312 | 3.112957 | false | false | false | false |
khaledhassan/vhdl-examples | adder_tree/adder.vhd | 1 | 2,067 | -- Copyright (c) 2012 Brian Nezvadovitz <http://nezzen.net>
-- This software is distributed under the terms of the MIT License shown below.
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to
-- deal in the Software without restriction, including without limitation the
-- rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
-- sell copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
-- IN THE SOFTWARE.
-- Implements an adder of variable width with carry signals.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adder is
generic (
WIDTH : positive := 8
);
port (
input1 : in std_logic_vector(WIDTH-1 downto 0);
input2 : in std_logic_vector(WIDTH-1 downto 0);
c_in : in std_logic;
output : out std_logic_vector(WIDTH-1 downto 0);
c_out : out std_logic
);
end;
architecture BHV of adder is
signal full_sum : std_logic_vector(WIDTH downto 0);
signal c_in_vec : std_logic_vector(0 downto 0);
begin
c_in_vec(0) <= c_in;
full_sum <= std_logic_vector( resize(unsigned(input1), WIDTH+1) + resize(unsigned(input2), WIDTH+1) + resize(unsigned(c_in_vec), WIDTH+1) );
output <= full_sum(WIDTH-1 downto 0);
c_out <= full_sum(WIDTH);
end BHV;
| mit | 5ec1dcb096351e81c3341773f89cbec8 | 0.709724 | 3.813653 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | VHDL_funcs_and_procs/sevseg_package.vhd | 1 | 1,972 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Functions can have multiple inputs and one return value.
-- Procedures have multiple 'return' values
PACKAGE MY IS
-- Function to convert into to 7 seg output.
-- This part is the 'protoype' similar to c/c++:
FUNCTION INT_TO7SEG (A:INTEGER) return STD_LOGIC_VECTOR;
-- Procedure to select value of each hex display given A:
PROCEDURE HEX_DEC (SIGNAL NUMBER:IN Integer;
SIGNAL DIGIT0, DIGIT1, DIGIT2, DIGIT3: OUT INTEGER RANGE 0 to 9);
END MY;
-- This part is the function definition:
package body MY IS
function INT_TO7SEG (A:integer) return STD_LOGIC_VECTOR is
VARIABLE RESULT: STD_LOGIC_VECTOR(6 downto 0);
BEGIN
CASE A IS
-- NOTE:
-- <= Assignment of Signals
-- := Assignment of Variables and Signal Initialization
-- https://www.nandland.com/vhdl/examples/example-assignment-operators.html
WHEN 0 => RESULT:="1000000";
WHEN 1 => RESULT:="1111001";
WHEN 2 => RESULT:="0100100";
WHEN 3 => RESULT:="0110000";
WHEN 4 => RESULT:="0011001";
WHEN 5 => RESULT:="0010010";
WHEN 6 => RESULT:="0000010";
WHEN 7 => RESULT:="1111000";
WHEN 8 => RESULT:="0000000";
WHEN 9 => RESULT:="0011000";
WHEN OTHERS => RESULT:=(OTHERS=>'0');
end case;
return RESULT;
END INT_TO7SEG;
-- Define procedure behavior:
PROCEDURE HEX_DEC (SIGNAL NUMBER:IN Integer;
SIGNAL DIGIT0, DIGIT1, DIGIT2, DIGIT3: OUT INTEGER RANGE 0 to 9) IS
VARIABLE TEMP: INTEGER range 0 to 9999;
VARIABLE D0: INTEGER range 0 to 9;
VARIABLE D1: INTEGER range 0 to 9;
VARIABLE D2: INTEGER range 0 to 9;
VARIABLE D3: INTEGER range 0 to 9;
BEGIN
TEMP:=NUMBER;
D3:=TEMP/1000;
TEMP:=TEMP-(D3*1000);
D2:=TEMP/100;
TEMP:=TEMP-(D2*100);
D1:=TEMP/10;
TEMP:=TEMP-(D1*10);
D0:=TEMP;
DIGIT0<=D0;
DIGIT1<=D1;
DIGIT2<=D2;
DIGIT3<=D3;
END HEX_DEC;
end MY;
-- Procedures can have multiple inputs and do not return anything.
-- Procedure to convert int to 7 seg output: | mit | 939678367f4e2bcd81f2c6af04e06870 | 0.687627 | 3.1552 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_axi_bram_ctrl_0_0/synth/zqynq_lab_1_design_axi_bram_ctrl_0_0.vhd | 1 | 17,400 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_bram_ctrl:4.0
-- IP Revision: 11
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_bram_ctrl_v4_0_11;
USE axi_bram_ctrl_v4_0_11.axi_bram_ctrl;
ENTITY zqynq_lab_1_design_axi_bram_ctrl_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rst_b : OUT STD_LOGIC;
bram_clk_b : OUT STD_LOGIC;
bram_en_b : OUT STD_LOGIC;
bram_we_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_b : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
bram_wrdata_b : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_b : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END zqynq_lab_1_design_axi_bram_ctrl_0_0;
ARCHITECTURE zqynq_lab_1_design_axi_bram_ctrl_0_0_arch OF zqynq_lab_1_design_axi_bram_ctrl_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF zqynq_lab_1_design_axi_bram_ctrl_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_bram_ctrl IS
GENERIC (
C_BRAM_INST_MODE : STRING;
C_MEMORY_DEPTH : INTEGER;
C_BRAM_ADDR_WIDTH : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ID_WIDTH : INTEGER;
C_S_AXI_PROTOCOL : STRING;
C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER;
C_SINGLE_PORT_BRAM : INTEGER;
C_FAMILY : STRING;
C_SELECT_XPM : INTEGER;
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_DATA_WIDTH : INTEGER;
C_ECC : INTEGER;
C_ECC_TYPE : INTEGER;
C_FAULT_INJECT : INTEGER;
C_ECC_ONOFF_RESET_VALUE : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
ecc_interrupt : OUT STD_LOGIC;
ecc_ue : OUT STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_ctrl_awvalid : IN STD_LOGIC;
s_axi_ctrl_awready : OUT STD_LOGIC;
s_axi_ctrl_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wvalid : IN STD_LOGIC;
s_axi_ctrl_wready : OUT STD_LOGIC;
s_axi_ctrl_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_bvalid : OUT STD_LOGIC;
s_axi_ctrl_bready : IN STD_LOGIC;
s_axi_ctrl_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_arvalid : IN STD_LOGIC;
s_axi_ctrl_arready : OUT STD_LOGIC;
s_axi_ctrl_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_rvalid : OUT STD_LOGIC;
s_axi_ctrl_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rst_b : OUT STD_LOGIC;
bram_clk_b : OUT STD_LOGIC;
bram_en_b : OUT STD_LOGIC;
bram_we_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_b : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
bram_wrdata_b : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_b : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_bram_ctrl;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF zqynq_lab_1_design_axi_bram_ctrl_0_0_arch: ARCHITECTURE IS "axi_bram_ctrl,Vivado 2017.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF zqynq_lab_1_design_axi_bram_ctrl_0_0_arch : ARCHITECTURE IS "zqynq_lab_1_design_axi_bram_ctrl_0_0,axi_bram_ctrl,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF zqynq_lab_1_design_axi_bram_ctrl_0_0_arch: ARCHITECTURE IS "zqynq_lab_1_design_axi_bram_ctrl_0_0,axi_bram_ctrl,{x_ipProduct=Vivado 2017.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_bram_ctrl,x_ipVersion=4.0,x_ipCoreRevision=11,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_BRAM_INST_MODE=EXTERNAL,C_MEMORY_DEPTH=16384,C_BRAM_ADDR_WIDTH=14,C_S_AXI_ADDR_WIDTH=16,C_S_AXI_DATA_WIDTH=32,C_S_AXI_ID_WIDTH=1,C_S_AXI_PROTOCOL=AXI4,C_S_AXI_SUPPORTS_NARROW_BURST=0,C_SINGLE_PORT_BRAM=0,C_FAMILY=zynq,C_SELECT_XPM=0,C_S_AXI_CTRL_ADDR_WIDTH=32,C_S_AXI_CTRL_DATA_WID" &
"TH=32,C_ECC=0,C_ECC_TYPE=0,C_FAULT_INJECT=0,C_ECC_ONOFF_RESET_VALUE=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLKIF CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 RSTIF RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF bram_rst_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST";
ATTRIBUTE X_INTERFACE_INFO OF bram_clk_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF bram_en_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF bram_we_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF bram_addr_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF bram_wrdata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF bram_rddata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
ATTRIBUTE X_INTERFACE_INFO OF bram_rst_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB RST";
ATTRIBUTE X_INTERFACE_INFO OF bram_clk_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF bram_en_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
ATTRIBUTE X_INTERFACE_INFO OF bram_we_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB WE";
ATTRIBUTE X_INTERFACE_INFO OF bram_addr_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF bram_wrdata_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN";
ATTRIBUTE X_INTERFACE_INFO OF bram_rddata_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : axi_bram_ctrl
GENERIC MAP (
C_BRAM_INST_MODE => "EXTERNAL",
C_MEMORY_DEPTH => 16384,
C_BRAM_ADDR_WIDTH => 14,
C_S_AXI_ADDR_WIDTH => 16,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ID_WIDTH => 1,
C_S_AXI_PROTOCOL => "AXI4",
C_S_AXI_SUPPORTS_NARROW_BURST => 0,
C_SINGLE_PORT_BRAM => 0,
C_FAMILY => "zynq",
C_SELECT_XPM => 0,
C_S_AXI_CTRL_ADDR_WIDTH => 32,
C_S_AXI_CTRL_DATA_WIDTH => 32,
C_ECC => 0,
C_ECC_TYPE => 0,
C_FAULT_INJECT => 0,
C_ECC_ONOFF_RESET_VALUE => 0
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => s_axi_awaddr,
s_axi_awlen => s_axi_awlen,
s_axi_awsize => s_axi_awsize,
s_axi_awburst => s_axi_awburst,
s_axi_awlock => s_axi_awlock,
s_axi_awcache => s_axi_awcache,
s_axi_awprot => s_axi_awprot,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wlast => s_axi_wlast,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => s_axi_araddr,
s_axi_arlen => s_axi_arlen,
s_axi_arsize => s_axi_arsize,
s_axi_arburst => s_axi_arburst,
s_axi_arlock => s_axi_arlock,
s_axi_arcache => s_axi_arcache,
s_axi_arprot => s_axi_arprot,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rlast => s_axi_rlast,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
s_axi_ctrl_awvalid => '0',
s_axi_ctrl_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wvalid => '0',
s_axi_ctrl_bready => '0',
s_axi_ctrl_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_arvalid => '0',
s_axi_ctrl_rready => '0',
bram_rst_a => bram_rst_a,
bram_clk_a => bram_clk_a,
bram_en_a => bram_en_a,
bram_we_a => bram_we_a,
bram_addr_a => bram_addr_a,
bram_wrdata_a => bram_wrdata_a,
bram_rddata_a => bram_rddata_a,
bram_rst_b => bram_rst_b,
bram_clk_b => bram_clk_b,
bram_en_b => bram_en_b,
bram_we_b => bram_we_b,
bram_addr_b => bram_addr_b,
bram_wrdata_b => bram_wrdata_b,
bram_rddata_b => bram_rddata_b
);
END zqynq_lab_1_design_axi_bram_ctrl_0_0_arch;
| mit | 7d24279f50e5b193f815c65739f612cd | 0.676494 | 3.045152 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/techmap/unisim/tap_unisim.vhd | 1 | 24,308 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: tap_xilinx
-- File: tap_xilinx.vhd
-- Author: Edvin Catovic, Jiri Gaisler - Gaisler Research
-- Description: Xilinx TAP controllers wrappers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.all;
-- pragma translate_on
entity virtex_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of virtex_tap is
component BSCAN_VIRTEX
port (CAPTURE : out STD_ULOGIC;
DRCK1 : out STD_ULOGIC;
DRCK2 : out STD_ULOGIC;
RESET : out STD_ULOGIC;
SEL1 : out STD_ULOGIC;
SEL2 : out STD_ULOGIC;
SHIFT : out STD_ULOGIC;
TDI : out STD_ULOGIC;
UPDATE : out STD_ULOGIC;
TDO1 : in STD_ULOGIC;
TDO2 : in STD_ULOGIC);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
begin
u0 : BSCAN_VIRTEX
port map (
DRCK1 => drck1,
DRCK2 => drck2,
RESET => tapo_rst,
SEL1 => sel1,
SEL2 => sel2,
SHIFT => tapo_shft,
TDI => tapo_tdi,
UPDATE => tapo_upd,
TDO1 => tapi_tdo1,
TDO2 => tapi_tdo2);
tapo_tck <= drck1 when sel1 = '1' else drck2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2; tapo_capt <= '0';
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.all;
-- pragma translate_on
entity virtex2_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of virtex2_tap is
component BSCAN_VIRTEX2
port (CAPTURE : out STD_ULOGIC;
DRCK1 : out STD_ULOGIC;
DRCK2 : out STD_ULOGIC;
RESET : out STD_ULOGIC;
SEL1 : out STD_ULOGIC;
SEL2 : out STD_ULOGIC;
SHIFT : out STD_ULOGIC;
TDI : out STD_ULOGIC;
UPDATE : out STD_ULOGIC;
TDO1 : in STD_ULOGIC;
TDO2 : in STD_ULOGIC);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
begin
u0 : BSCAN_VIRTEX2
port map (CAPTURE => tapo_capt,
DRCK1 => drck1,
DRCK2 => drck2,
RESET => tapo_rst,
SEL1 => sel1,
SEL2 => sel2,
SHIFT => tapo_shft,
TDI => tapo_tdi,
UPDATE => tapo_upd,
TDO1 => tapi_tdo1,
TDO2 => tapi_tdo2);
tapo_tck <= drck1 when sel1 = '1' else drck2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BSCAN_SPARTAN3;
-- pragma translate_on
entity spartan3_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of spartan3_tap is
component BSCAN_SPARTAN3
port (CAPTURE : out STD_ULOGIC;
DRCK1 : out STD_ULOGIC;
DRCK2 : out STD_ULOGIC;
RESET : out STD_ULOGIC;
SEL1 : out STD_ULOGIC;
SEL2 : out STD_ULOGIC;
SHIFT : out STD_ULOGIC;
TDI : out STD_ULOGIC;
UPDATE : out STD_ULOGIC;
TDO1 : in STD_ULOGIC;
TDO2 : in STD_ULOGIC);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
begin
u0 : BSCAN_SPARTAN3
port map (CAPTURE => tapo_capt,
DRCK1 => drck1,
DRCK2 => drck2,
RESET => tapo_rst,
SEL1 => sel1,
SEL2 => sel2,
SHIFT => tapo_shft,
TDI => tapo_tdi,
UPDATE => tapo_upd,
TDO1 => tapi_tdo1,
TDO2 => tapi_tdo2);
tapo_tck <= drck1 when sel1 = '1' else drck2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BSCAN_VIRTEX4;
-- pragma translate_on
entity virtex4_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of virtex4_tap is
component BSCAN_VIRTEX4 generic ( JTAG_CHAIN : integer := 1);
port ( CAPTURE : out std_ulogic;
DRCK : out std_ulogic;
RESET : out std_ulogic;
SEL : out std_ulogic;
SHIFT : out std_ulogic;
TDI : out std_ulogic;
UPDATE : out std_ulogic;
TDO : in std_ulogic);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
signal capt1, capt2, rst1, rst2 : std_ulogic;
signal shift1, shift2, tdi1, tdi2 : std_ulogic;
signal update1, update2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
attribute dont_touch of u1 : label is true;
begin
u0 : BSCAN_VIRTEX4
generic map (JTAG_CHAIN => 1)
port map (
CAPTURE => capt1,
DRCK => drck1,
RESET => rst1,
SEL => sel1,
SHIFT => shift1,
TDI => tdi1,
UPDATE => update1,
TDO => tapi_tdo1
);
u1 : BSCAN_VIRTEX4
generic map (JTAG_CHAIN => 2)
port map (
CAPTURE => capt2,
DRCK => drck2,
RESET => rst2,
SEL => sel2,
SHIFT => shift2,
TDI => tdi2,
UPDATE => update2,
TDO => tapi_tdo2
);
tapo_capt <= capt1 when sel1 = '1' else capt2;
tapo_tck <= drck1 when sel1 = '1' else drck2;
tapo_rst <= rst1 when sel1 = '1' else rst2;
tapo_shft <= shift1 when sel1 = '1' else shift2;
tapo_tdi <= tdi1 when sel1 = '1' else tdi2;
tapo_upd <= update1 when sel1 ='1' else update2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BSCAN_VIRTEX5;
-- pragma translate_on
entity virtex5_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of virtex5_tap is
component BSCAN_VIRTEX5 generic ( JTAG_CHAIN : integer := 1);
port ( CAPTURE : out std_ulogic;
DRCK : out std_ulogic;
RESET : out std_ulogic;
SEL : out std_ulogic;
SHIFT : out std_ulogic;
TDI : out std_ulogic;
UPDATE : out std_ulogic;
TDO : in std_ulogic);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
signal capt1, capt2, rst1, rst2 : std_ulogic;
signal shift1, shift2, tdi1, tdi2 : std_ulogic;
signal update1, update2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
attribute dont_touch of u1 : label is true;
begin
u0 : BSCAN_VIRTEX5
generic map (JTAG_CHAIN => 1)
port map (
CAPTURE => capt1,
DRCK => drck1,
RESET => rst1,
SEL => sel1,
SHIFT => shift1,
TDI => tdi1,
UPDATE => update1,
TDO => tapi_tdo1
);
u1 : BSCAN_VIRTEX5
generic map (JTAG_CHAIN => 2)
port map (
CAPTURE => capt2,
DRCK => drck2,
RESET => rst2,
SEL => sel2,
SHIFT => shift2,
TDI => tdi2,
UPDATE => update2,
TDO => tapi_tdo2
);
tapo_capt <= capt1 when sel1 = '1' else capt2;
tapo_tck <= drck1 when sel1 = '1' else drck2;
tapo_rst <= rst1 when sel1 = '1' else rst2;
tapo_shft <= shift1 when sel1 = '1' else shift2;
tapo_tdi <= tdi1 when sel1 = '1' else tdi2;
tapo_upd <= update1 when sel1 ='1' else update2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.all;
-- pragma translate_on
entity virtex6_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of virtex6_tap is
component BSCAN_VIRTEX6
generic (
DISABLE_JTAG : boolean := FALSE;
JTAG_CHAIN : integer := 1
);
port (
CAPTURE : out std_ulogic := 'H';
DRCK : out std_ulogic := 'H';
RESET : out std_ulogic := 'H';
RUNTEST : out std_ulogic := 'L';
SEL : out std_ulogic := 'L';
SHIFT : out std_ulogic := 'L';
TCK : out std_ulogic := 'L';
TDI : out std_ulogic := 'L';
TMS : out std_ulogic := 'L';
UPDATE : out std_ulogic := 'L';
TDO : in std_ulogic := 'X'
);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
signal capt1, capt2, rst1, rst2 : std_ulogic;
signal shift1, shift2, tdi1, tdi2 : std_ulogic;
signal update1, update2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
attribute dont_touch of u1 : label is true;
begin
u0 : BSCAN_VIRTEX6
generic map (JTAG_CHAIN => 1)
port map (
CAPTURE => capt1,
DRCK => drck1,
RESET => rst1,
SEL => sel1,
SHIFT => shift1,
TDI => tdi1,
UPDATE => update1,
TDO => tapi_tdo1,
TCK => tapo_tck
);
u1 : BSCAN_VIRTEX6
generic map (JTAG_CHAIN => 2)
port map (
CAPTURE => capt2,
DRCK => drck2,
RESET => rst2,
SEL => sel2,
SHIFT => shift2,
TDI => tdi2,
UPDATE => update2,
TDO => tapi_tdo2
);
tapo_capt <= capt1 when sel1 = '1' else capt2;
tapo_rst <= rst1 when sel1 = '1' else rst2;
tapo_shft <= shift1 when sel1 = '1' else shift2;
tapo_tdi <= tdi1 when sel1 = '1' else tdi2;
tapo_upd <= update1 when sel1 ='1' else update2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.all;
-- pragma translate_on
entity spartan6_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of spartan6_tap is
component BSCAN_SPARTAN6
generic (
JTAG_CHAIN : integer := 1
);
port (
CAPTURE : out std_ulogic := 'H';
DRCK : out std_ulogic := 'H';
RESET : out std_ulogic := 'H';
RUNTEST : out std_ulogic := 'L';
SEL : out std_ulogic := 'L';
SHIFT : out std_ulogic := 'L';
TCK : out std_ulogic := 'L';
TDI : out std_ulogic := 'L';
TMS : out std_ulogic := 'L';
UPDATE : out std_ulogic := 'L';
TDO : in std_ulogic := 'X'
);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
signal capt1, capt2, rst1, rst2 : std_ulogic;
signal shift1, shift2, tdi1, tdi2 : std_ulogic;
signal update1, update2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
attribute dont_touch of u1 : label is true;
begin
u0 : BSCAN_SPARTAN6
generic map (JTAG_CHAIN => 1)
port map (
CAPTURE => capt1,
DRCK => drck1,
RESET => rst1,
SEL => sel1,
SHIFT => shift1,
TDI => tdi1,
UPDATE => update1,
TDO => tapi_tdo1,
TCK => tapo_tck
);
u1 : BSCAN_SPARTAN6
generic map (JTAG_CHAIN => 2)
port map (
CAPTURE => capt2,
DRCK => drck2,
RESET => rst2,
SEL => sel2,
SHIFT => shift2,
TDI => tdi2,
UPDATE => update2,
TDO => tapi_tdo2
);
tapo_capt <= capt1 when sel1 = '1' else capt2;
tapo_rst <= rst1 when sel1 = '1' else rst2;
tapo_shft <= shift1 when sel1 = '1' else shift2;
tapo_tdi <= tdi1 when sel1 = '1' else tdi2;
tapo_upd <= update1 when sel1 ='1' else update2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.all;
-- pragma translate_on
entity virtex7_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of virtex7_tap is
component BSCANE2
generic (
DISABLE_JTAG : string := "FALSE";
JTAG_CHAIN : integer := 1
);
port (
CAPTURE : out std_ulogic := 'H';
DRCK : out std_ulogic := 'H';
RESET : out std_ulogic := 'H';
RUNTEST : out std_ulogic := 'L';
SEL : out std_ulogic := 'L';
SHIFT : out std_ulogic := 'L';
TCK : out std_ulogic := 'L';
TDI : out std_ulogic := 'L';
TMS : out std_ulogic := 'L';
UPDATE : out std_ulogic := 'L';
TDO : in std_ulogic := 'X'
);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
signal capt1, capt2, rst1, rst2 : std_ulogic;
signal shift1, shift2, tdi1, tdi2 : std_ulogic;
signal update1, update2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
attribute dont_touch of u1 : label is true;
begin
u0 : BSCANE2
generic map (JTAG_CHAIN => 1)
port map (
CAPTURE => capt1,
DRCK => drck1,
RESET => rst1,
SEL => sel1,
SHIFT => shift1,
TDI => tdi1,
UPDATE => update1,
TDO => tapi_tdo1,
TCK => tapo_tck
);
u1 : BSCANE2
generic map (JTAG_CHAIN => 2)
port map (
CAPTURE => capt2,
DRCK => drck2,
RESET => rst2,
SEL => sel2,
SHIFT => shift2,
TDI => tdi2,
UPDATE => update2,
TDO => tapi_tdo2
);
tapo_capt <= capt1 when sel1 = '1' else capt2;
tapo_rst <= rst1 when sel1 = '1' else rst2;
tapo_shft <= shift1 when sel1 = '1' else shift2;
tapo_tdi <= tdi1 when sel1 = '1' else tdi2;
tapo_upd <= update1 when sel1 ='1' else update2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.all;
-- pragma translate_on
entity kintex7_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of kintex7_tap is
component BSCANE2
generic (
DISABLE_JTAG : string := "FALSE";
JTAG_CHAIN : integer := 1
);
port (
CAPTURE : out std_ulogic := 'H';
DRCK : out std_ulogic := 'H';
RESET : out std_ulogic := 'H';
RUNTEST : out std_ulogic := 'L';
SEL : out std_ulogic := 'L';
SHIFT : out std_ulogic := 'L';
TCK : out std_ulogic := 'L';
TDI : out std_ulogic := 'L';
TMS : out std_ulogic := 'L';
UPDATE : out std_ulogic := 'L';
TDO : in std_ulogic := 'X'
);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
signal capt1, capt2, rst1, rst2 : std_ulogic;
signal shift1, shift2, tdi1, tdi2 : std_ulogic;
signal update1, update2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
attribute dont_touch of u1 : label is true;
begin
u0 : BSCANE2
generic map (JTAG_CHAIN => 1)
port map (
CAPTURE => capt1,
DRCK => drck1,
RESET => rst1,
SEL => sel1,
SHIFT => shift1,
TDI => tdi1,
UPDATE => update1,
TDO => tapi_tdo1,
TCK => tapo_tck
);
u1 : BSCANE2
generic map (JTAG_CHAIN => 2)
port map (
CAPTURE => capt2,
DRCK => drck2,
RESET => rst2,
SEL => sel2,
SHIFT => shift2,
TDI => tdi2,
UPDATE => update2,
TDO => tapi_tdo2
);
tapo_capt <= capt1 when sel1 = '1' else capt2;
tapo_rst <= rst1 when sel1 = '1' else rst2;
tapo_shft <= shift1 when sel1 = '1' else shift2;
tapo_tdi <= tdi1 when sel1 = '1' else tdi2;
tapo_upd <= update1 when sel1 ='1' else update2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.all;
-- pragma translate_on
entity artix7_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of artix7_tap is
component BSCANE2
generic (
DISABLE_JTAG : string := "FALSE";
JTAG_CHAIN : integer := 1
);
port (
CAPTURE : out std_ulogic := 'H';
DRCK : out std_ulogic := 'H';
RESET : out std_ulogic := 'H';
RUNTEST : out std_ulogic := 'L';
SEL : out std_ulogic := 'L';
SHIFT : out std_ulogic := 'L';
TCK : out std_ulogic := 'L';
TDI : out std_ulogic := 'L';
TMS : out std_ulogic := 'L';
UPDATE : out std_ulogic := 'L';
TDO : in std_ulogic := 'X'
);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
signal capt1, capt2, rst1, rst2 : std_ulogic;
signal shift1, shift2, tdi1, tdi2 : std_ulogic;
signal update1, update2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
attribute dont_touch of u1 : label is true;
begin
u0 : BSCANE2
generic map (JTAG_CHAIN => 1)
port map (
CAPTURE => capt1,
DRCK => drck1,
RESET => rst1,
SEL => sel1,
SHIFT => shift1,
TDI => tdi1,
UPDATE => update1,
TDO => tapi_tdo1,
TCK => tapo_tck
);
u1 : BSCANE2
generic map (JTAG_CHAIN => 2)
port map (
CAPTURE => capt2,
DRCK => drck2,
RESET => rst2,
SEL => sel2,
SHIFT => shift2,
TDI => tdi2,
UPDATE => update2,
TDO => tapi_tdo2
);
tapo_capt <= capt1 when sel1 = '1' else capt2;
tapo_rst <= rst1 when sel1 = '1' else rst2;
tapo_shft <= shift1 when sel1 = '1' else shift2;
tapo_tdi <= tdi1 when sel1 = '1' else tdi2;
tapo_upd <= update1 when sel1 ='1' else update2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
| gpl-2.0 | f29b67bafb1e07e116b5fe7d37599992 | 0.498025 | 3.750656 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/led_controller/led_controller.srcs/sources_1/bd/led_controller_design/ip/led_controller_design_led_controller_0_0/led_controller_design_led_controller_0_0_sim_netlist.vhdl | 1 | 66,944 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 15:44:52 2017
-- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
-- Command : write_vhdl -force -mode funcsim
-- /home/mark/Documents/Repos/FPGA_Sandbox/RecComp/Lab3/led_controller/led_controller.srcs/sources_1/bd/led_controller_design/ip/led_controller_design_led_controller_0_0/led_controller_design_led_controller_0_0_sim_netlist.vhdl
-- Design : led_controller_design_led_controller_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity led_controller_design_led_controller_0_0_led_controller_v1_0_S00_AXI is
port (
S_AXI_ARREADY : out STD_LOGIC;
S_AXI_AWREADY : out STD_LOGIC;
S_AXI_WREADY : out STD_LOGIC;
LEDs_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_bvalid : out STD_LOGIC;
s00_axi_arvalid : in STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_araddr : in STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_aresetn : in STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_rready : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of led_controller_design_led_controller_0_0_led_controller_v1_0_S00_AXI : entity is "led_controller_v1_0_S00_AXI";
end led_controller_design_led_controller_0_0_led_controller_v1_0_S00_AXI;
architecture STRUCTURE of led_controller_design_led_controller_0_0_led_controller_v1_0_S00_AXI is
signal \^leds_out\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^s_axi_arready\ : STD_LOGIC;
signal \^s_axi_awready\ : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
signal aw_en_i_1_n_0 : STD_LOGIC;
signal aw_en_reg_n_0 : STD_LOGIC;
signal axi_araddr : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \axi_araddr[2]_i_1_n_0\ : STD_LOGIC;
signal \axi_araddr[3]_i_1_n_0\ : STD_LOGIC;
signal axi_arready_i_1_n_0 : STD_LOGIC;
signal \axi_awaddr[2]_i_1_n_0\ : STD_LOGIC;
signal \axi_awaddr[3]_i_1_n_0\ : STD_LOGIC;
signal axi_awready0 : STD_LOGIC;
signal axi_bvalid_i_1_n_0 : STD_LOGIC;
signal axi_rvalid_i_1_n_0 : STD_LOGIC;
signal axi_wready0 : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 1 downto 0 );
signal p_1_in : STD_LOGIC_VECTOR ( 31 downto 7 );
signal reg_data_out : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s00_axi_bvalid\ : STD_LOGIC;
signal \^s00_axi_rvalid\ : STD_LOGIC;
signal slv_reg0 : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \slv_reg0[7]_i_1_n_0\ : STD_LOGIC;
signal slv_reg1 : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \slv_reg1[15]_i_1_n_0\ : STD_LOGIC;
signal \slv_reg1[23]_i_1_n_0\ : STD_LOGIC;
signal \slv_reg1[31]_i_1_n_0\ : STD_LOGIC;
signal \slv_reg1[7]_i_1_n_0\ : STD_LOGIC;
signal slv_reg2 : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \slv_reg2[15]_i_1_n_0\ : STD_LOGIC;
signal \slv_reg2[23]_i_1_n_0\ : STD_LOGIC;
signal \slv_reg2[31]_i_1_n_0\ : STD_LOGIC;
signal \slv_reg2[7]_i_1_n_0\ : STD_LOGIC;
signal slv_reg3 : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \slv_reg3[15]_i_1_n_0\ : STD_LOGIC;
signal \slv_reg3[23]_i_1_n_0\ : STD_LOGIC;
signal \slv_reg3[31]_i_1_n_0\ : STD_LOGIC;
signal \slv_reg3[7]_i_1_n_0\ : STD_LOGIC;
signal \slv_reg_rden__0\ : STD_LOGIC;
signal \slv_reg_wren__0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axi_araddr[3]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of axi_arready_i_1 : label is "soft_lutpair1";
attribute SOFT_HLUTNM of axi_wready_i_1 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \slv_reg0[7]_i_3\ : label is "soft_lutpair0";
begin
LEDs_out(7 downto 0) <= \^leds_out\(7 downto 0);
S_AXI_ARREADY <= \^s_axi_arready\;
S_AXI_AWREADY <= \^s_axi_awready\;
S_AXI_WREADY <= \^s_axi_wready\;
s00_axi_bvalid <= \^s00_axi_bvalid\;
s00_axi_rvalid <= \^s00_axi_rvalid\;
aw_en_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"F7FFC4CCC4CCC4CC"
)
port map (
I0 => s00_axi_wvalid,
I1 => aw_en_reg_n_0,
I2 => \^s_axi_awready\,
I3 => s00_axi_awvalid,
I4 => s00_axi_bready,
I5 => \^s00_axi_bvalid\,
O => aw_en_i_1_n_0
);
aw_en_reg: unisim.vcomponents.FDSE
port map (
C => s00_axi_aclk,
CE => '1',
D => aw_en_i_1_n_0,
Q => aw_en_reg_n_0,
S => \slv_reg0[7]_i_1_n_0\
);
\axi_araddr[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s00_axi_araddr(0),
I1 => s00_axi_arvalid,
I2 => \^s_axi_arready\,
I3 => axi_araddr(2),
O => \axi_araddr[2]_i_1_n_0\
);
\axi_araddr[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s00_axi_araddr(1),
I1 => s00_axi_arvalid,
I2 => \^s_axi_arready\,
I3 => axi_araddr(3),
O => \axi_araddr[3]_i_1_n_0\
);
\axi_araddr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => '1',
D => \axi_araddr[2]_i_1_n_0\,
Q => axi_araddr(2),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_araddr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => '1',
D => \axi_araddr[3]_i_1_n_0\,
Q => axi_araddr(3),
R => \slv_reg0[7]_i_1_n_0\
);
axi_arready_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s00_axi_arvalid,
I1 => \^s_axi_arready\,
O => axi_arready_i_1_n_0
);
axi_arready_reg: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => '1',
D => axi_arready_i_1_n_0,
Q => \^s_axi_arready\,
R => \slv_reg0[7]_i_1_n_0\
);
\axi_awaddr[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FBFFFFFF08000000"
)
port map (
I0 => s00_axi_awaddr(0),
I1 => s00_axi_awvalid,
I2 => \^s_axi_awready\,
I3 => aw_en_reg_n_0,
I4 => s00_axi_wvalid,
I5 => p_0_in(0),
O => \axi_awaddr[2]_i_1_n_0\
);
\axi_awaddr[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FBFFFFFF08000000"
)
port map (
I0 => s00_axi_awaddr(1),
I1 => s00_axi_awvalid,
I2 => \^s_axi_awready\,
I3 => aw_en_reg_n_0,
I4 => s00_axi_wvalid,
I5 => p_0_in(1),
O => \axi_awaddr[3]_i_1_n_0\
);
\axi_awaddr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => '1',
D => \axi_awaddr[2]_i_1_n_0\,
Q => p_0_in(0),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_awaddr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => '1',
D => \axi_awaddr[3]_i_1_n_0\,
Q => p_0_in(1),
R => \slv_reg0[7]_i_1_n_0\
);
axi_awready_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => s00_axi_awvalid,
I1 => \^s_axi_awready\,
I2 => aw_en_reg_n_0,
I3 => s00_axi_wvalid,
O => axi_awready0
);
axi_awready_reg: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => '1',
D => axi_awready0,
Q => \^s_axi_awready\,
R => \slv_reg0[7]_i_1_n_0\
);
axi_bvalid_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFF80008000"
)
port map (
I0 => \^s_axi_wready\,
I1 => \^s_axi_awready\,
I2 => s00_axi_awvalid,
I3 => s00_axi_wvalid,
I4 => s00_axi_bready,
I5 => \^s00_axi_bvalid\,
O => axi_bvalid_i_1_n_0
);
axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => '1',
D => axi_bvalid_i_1_n_0,
Q => \^s00_axi_bvalid\,
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(0),
I1 => \^leds_out\(0),
I2 => slv_reg3(0),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(0),
O => reg_data_out(0)
);
\axi_rdata[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(10),
I1 => slv_reg0(10),
I2 => slv_reg3(10),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(10),
O => reg_data_out(10)
);
\axi_rdata[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(11),
I1 => slv_reg0(11),
I2 => slv_reg3(11),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(11),
O => reg_data_out(11)
);
\axi_rdata[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(12),
I1 => slv_reg0(12),
I2 => slv_reg3(12),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(12),
O => reg_data_out(12)
);
\axi_rdata[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(13),
I1 => slv_reg0(13),
I2 => slv_reg3(13),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(13),
O => reg_data_out(13)
);
\axi_rdata[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(14),
I1 => slv_reg0(14),
I2 => slv_reg3(14),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(14),
O => reg_data_out(14)
);
\axi_rdata[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(15),
I1 => slv_reg0(15),
I2 => slv_reg3(15),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(15),
O => reg_data_out(15)
);
\axi_rdata[16]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(16),
I1 => slv_reg0(16),
I2 => slv_reg3(16),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(16),
O => reg_data_out(16)
);
\axi_rdata[17]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(17),
I1 => slv_reg0(17),
I2 => slv_reg3(17),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(17),
O => reg_data_out(17)
);
\axi_rdata[18]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(18),
I1 => slv_reg0(18),
I2 => slv_reg3(18),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(18),
O => reg_data_out(18)
);
\axi_rdata[19]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(19),
I1 => slv_reg0(19),
I2 => slv_reg3(19),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(19),
O => reg_data_out(19)
);
\axi_rdata[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(1),
I1 => \^leds_out\(1),
I2 => slv_reg3(1),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(1),
O => reg_data_out(1)
);
\axi_rdata[20]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(20),
I1 => slv_reg0(20),
I2 => slv_reg3(20),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(20),
O => reg_data_out(20)
);
\axi_rdata[21]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(21),
I1 => slv_reg0(21),
I2 => slv_reg3(21),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(21),
O => reg_data_out(21)
);
\axi_rdata[22]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(22),
I1 => slv_reg0(22),
I2 => slv_reg3(22),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(22),
O => reg_data_out(22)
);
\axi_rdata[23]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(23),
I1 => slv_reg0(23),
I2 => slv_reg3(23),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(23),
O => reg_data_out(23)
);
\axi_rdata[24]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(24),
I1 => slv_reg0(24),
I2 => slv_reg3(24),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(24),
O => reg_data_out(24)
);
\axi_rdata[25]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(25),
I1 => slv_reg0(25),
I2 => slv_reg3(25),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(25),
O => reg_data_out(25)
);
\axi_rdata[26]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(26),
I1 => slv_reg0(26),
I2 => slv_reg3(26),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(26),
O => reg_data_out(26)
);
\axi_rdata[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(27),
I1 => slv_reg0(27),
I2 => slv_reg3(27),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(27),
O => reg_data_out(27)
);
\axi_rdata[28]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(28),
I1 => slv_reg0(28),
I2 => slv_reg3(28),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(28),
O => reg_data_out(28)
);
\axi_rdata[29]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(29),
I1 => slv_reg0(29),
I2 => slv_reg3(29),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(29),
O => reg_data_out(29)
);
\axi_rdata[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(2),
I1 => \^leds_out\(2),
I2 => slv_reg3(2),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(2),
O => reg_data_out(2)
);
\axi_rdata[30]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(30),
I1 => slv_reg0(30),
I2 => slv_reg3(30),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(30),
O => reg_data_out(30)
);
\axi_rdata[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(31),
I1 => slv_reg0(31),
I2 => slv_reg3(31),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(31),
O => reg_data_out(31)
);
\axi_rdata[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(3),
I1 => \^leds_out\(3),
I2 => slv_reg3(3),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(3),
O => reg_data_out(3)
);
\axi_rdata[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(4),
I1 => \^leds_out\(4),
I2 => slv_reg3(4),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(4),
O => reg_data_out(4)
);
\axi_rdata[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(5),
I1 => \^leds_out\(5),
I2 => slv_reg3(5),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(5),
O => reg_data_out(5)
);
\axi_rdata[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(6),
I1 => \^leds_out\(6),
I2 => slv_reg3(6),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(6),
O => reg_data_out(6)
);
\axi_rdata[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(7),
I1 => \^leds_out\(7),
I2 => slv_reg3(7),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(7),
O => reg_data_out(7)
);
\axi_rdata[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(8),
I1 => slv_reg0(8),
I2 => slv_reg3(8),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(8),
O => reg_data_out(8)
);
\axi_rdata[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(9),
I1 => slv_reg0(9),
I2 => slv_reg3(9),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(9),
O => reg_data_out(9)
);
\axi_rdata_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(0),
Q => s00_axi_rdata(0),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(10),
Q => s00_axi_rdata(10),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(11),
Q => s00_axi_rdata(11),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(12),
Q => s00_axi_rdata(12),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(13),
Q => s00_axi_rdata(13),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(14),
Q => s00_axi_rdata(14),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(15),
Q => s00_axi_rdata(15),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(16),
Q => s00_axi_rdata(16),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(17),
Q => s00_axi_rdata(17),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(18),
Q => s00_axi_rdata(18),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(19),
Q => s00_axi_rdata(19),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(1),
Q => s00_axi_rdata(1),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(20),
Q => s00_axi_rdata(20),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(21),
Q => s00_axi_rdata(21),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(22),
Q => s00_axi_rdata(22),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(23),
Q => s00_axi_rdata(23),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(24),
Q => s00_axi_rdata(24),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(25),
Q => s00_axi_rdata(25),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(26),
Q => s00_axi_rdata(26),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(27),
Q => s00_axi_rdata(27),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(28),
Q => s00_axi_rdata(28),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(29),
Q => s00_axi_rdata(29),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(2),
Q => s00_axi_rdata(2),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(30),
Q => s00_axi_rdata(30),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(31),
Q => s00_axi_rdata(31),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(3),
Q => s00_axi_rdata(3),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(4),
Q => s00_axi_rdata(4),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(5),
Q => s00_axi_rdata(5),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(6),
Q => s00_axi_rdata(6),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(7),
Q => s00_axi_rdata(7),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(8),
Q => s00_axi_rdata(8),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(9),
Q => s00_axi_rdata(9),
R => \slv_reg0[7]_i_1_n_0\
);
axi_rvalid_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"08F8"
)
port map (
I0 => \^s_axi_arready\,
I1 => s00_axi_arvalid,
I2 => \^s00_axi_rvalid\,
I3 => s00_axi_rready,
O => axi_rvalid_i_1_n_0
);
axi_rvalid_reg: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => '1',
D => axi_rvalid_i_1_n_0,
Q => \^s00_axi_rvalid\,
R => \slv_reg0[7]_i_1_n_0\
);
axi_wready_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"4000"
)
port map (
I0 => \^s_axi_wready\,
I1 => s00_axi_wvalid,
I2 => s00_axi_awvalid,
I3 => aw_en_reg_n_0,
O => axi_wready0
);
axi_wready_reg: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => '1',
D => axi_wready0,
Q => \^s_axi_wready\,
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0[15]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0200"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => p_0_in(0),
I3 => s00_axi_wstrb(1),
O => p_1_in(15)
);
\slv_reg0[23]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0200"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => p_0_in(0),
I3 => s00_axi_wstrb(2),
O => p_1_in(23)
);
\slv_reg0[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0200"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => p_0_in(0),
I3 => s00_axi_wstrb(3),
O => p_1_in(31)
);
\slv_reg0[7]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s00_axi_aresetn,
O => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0[7]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0200"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => p_0_in(0),
I3 => s00_axi_wstrb(0),
O => p_1_in(7)
);
\slv_reg0[7]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^s_axi_wready\,
I1 => \^s_axi_awready\,
I2 => s00_axi_awvalid,
I3 => s00_axi_wvalid,
O => \slv_reg_wren__0\
);
\slv_reg0_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(7),
D => s00_axi_wdata(0),
Q => \^leds_out\(0),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(15),
D => s00_axi_wdata(10),
Q => slv_reg0(10),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(15),
D => s00_axi_wdata(11),
Q => slv_reg0(11),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(15),
D => s00_axi_wdata(12),
Q => slv_reg0(12),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(15),
D => s00_axi_wdata(13),
Q => slv_reg0(13),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(15),
D => s00_axi_wdata(14),
Q => slv_reg0(14),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(15),
D => s00_axi_wdata(15),
Q => slv_reg0(15),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(23),
D => s00_axi_wdata(16),
Q => slv_reg0(16),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(23),
D => s00_axi_wdata(17),
Q => slv_reg0(17),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(23),
D => s00_axi_wdata(18),
Q => slv_reg0(18),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(23),
D => s00_axi_wdata(19),
Q => slv_reg0(19),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(7),
D => s00_axi_wdata(1),
Q => \^leds_out\(1),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(23),
D => s00_axi_wdata(20),
Q => slv_reg0(20),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(23),
D => s00_axi_wdata(21),
Q => slv_reg0(21),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(23),
D => s00_axi_wdata(22),
Q => slv_reg0(22),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(23),
D => s00_axi_wdata(23),
Q => slv_reg0(23),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(31),
D => s00_axi_wdata(24),
Q => slv_reg0(24),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(31),
D => s00_axi_wdata(25),
Q => slv_reg0(25),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(31),
D => s00_axi_wdata(26),
Q => slv_reg0(26),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(31),
D => s00_axi_wdata(27),
Q => slv_reg0(27),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(31),
D => s00_axi_wdata(28),
Q => slv_reg0(28),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(31),
D => s00_axi_wdata(29),
Q => slv_reg0(29),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(7),
D => s00_axi_wdata(2),
Q => \^leds_out\(2),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(31),
D => s00_axi_wdata(30),
Q => slv_reg0(30),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(31),
D => s00_axi_wdata(31),
Q => slv_reg0(31),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(7),
D => s00_axi_wdata(3),
Q => \^leds_out\(3),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(7),
D => s00_axi_wdata(4),
Q => \^leds_out\(4),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(7),
D => s00_axi_wdata(5),
Q => \^leds_out\(5),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(7),
D => s00_axi_wdata(6),
Q => \^leds_out\(6),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(7),
D => s00_axi_wdata(7),
Q => \^leds_out\(7),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(15),
D => s00_axi_wdata(8),
Q => slv_reg0(8),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(15),
D => s00_axi_wdata(9),
Q => slv_reg0(9),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1[15]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => s00_axi_wstrb(1),
I3 => p_0_in(0),
O => \slv_reg1[15]_i_1_n_0\
);
\slv_reg1[23]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => s00_axi_wstrb(2),
I3 => p_0_in(0),
O => \slv_reg1[23]_i_1_n_0\
);
\slv_reg1[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => s00_axi_wstrb(3),
I3 => p_0_in(0),
O => \slv_reg1[31]_i_1_n_0\
);
\slv_reg1[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => s00_axi_wstrb(0),
I3 => p_0_in(0),
O => \slv_reg1[7]_i_1_n_0\
);
\slv_reg1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[7]_i_1_n_0\,
D => s00_axi_wdata(0),
Q => slv_reg1(0),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[15]_i_1_n_0\,
D => s00_axi_wdata(10),
Q => slv_reg1(10),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[15]_i_1_n_0\,
D => s00_axi_wdata(11),
Q => slv_reg1(11),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[15]_i_1_n_0\,
D => s00_axi_wdata(12),
Q => slv_reg1(12),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[15]_i_1_n_0\,
D => s00_axi_wdata(13),
Q => slv_reg1(13),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[15]_i_1_n_0\,
D => s00_axi_wdata(14),
Q => slv_reg1(14),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[15]_i_1_n_0\,
D => s00_axi_wdata(15),
Q => slv_reg1(15),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[23]_i_1_n_0\,
D => s00_axi_wdata(16),
Q => slv_reg1(16),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[23]_i_1_n_0\,
D => s00_axi_wdata(17),
Q => slv_reg1(17),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[23]_i_1_n_0\,
D => s00_axi_wdata(18),
Q => slv_reg1(18),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[23]_i_1_n_0\,
D => s00_axi_wdata(19),
Q => slv_reg1(19),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[7]_i_1_n_0\,
D => s00_axi_wdata(1),
Q => slv_reg1(1),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[23]_i_1_n_0\,
D => s00_axi_wdata(20),
Q => slv_reg1(20),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[23]_i_1_n_0\,
D => s00_axi_wdata(21),
Q => slv_reg1(21),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[23]_i_1_n_0\,
D => s00_axi_wdata(22),
Q => slv_reg1(22),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[23]_i_1_n_0\,
D => s00_axi_wdata(23),
Q => slv_reg1(23),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[31]_i_1_n_0\,
D => s00_axi_wdata(24),
Q => slv_reg1(24),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[31]_i_1_n_0\,
D => s00_axi_wdata(25),
Q => slv_reg1(25),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[31]_i_1_n_0\,
D => s00_axi_wdata(26),
Q => slv_reg1(26),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[31]_i_1_n_0\,
D => s00_axi_wdata(27),
Q => slv_reg1(27),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[31]_i_1_n_0\,
D => s00_axi_wdata(28),
Q => slv_reg1(28),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[31]_i_1_n_0\,
D => s00_axi_wdata(29),
Q => slv_reg1(29),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[7]_i_1_n_0\,
D => s00_axi_wdata(2),
Q => slv_reg1(2),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[31]_i_1_n_0\,
D => s00_axi_wdata(30),
Q => slv_reg1(30),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[31]_i_1_n_0\,
D => s00_axi_wdata(31),
Q => slv_reg1(31),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[7]_i_1_n_0\,
D => s00_axi_wdata(3),
Q => slv_reg1(3),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[7]_i_1_n_0\,
D => s00_axi_wdata(4),
Q => slv_reg1(4),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[7]_i_1_n_0\,
D => s00_axi_wdata(5),
Q => slv_reg1(5),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[7]_i_1_n_0\,
D => s00_axi_wdata(6),
Q => slv_reg1(6),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[7]_i_1_n_0\,
D => s00_axi_wdata(7),
Q => slv_reg1(7),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[15]_i_1_n_0\,
D => s00_axi_wdata(8),
Q => slv_reg1(8),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[15]_i_1_n_0\,
D => s00_axi_wdata(9),
Q => slv_reg1(9),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2[15]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => s00_axi_wstrb(1),
I3 => p_0_in(0),
O => \slv_reg2[15]_i_1_n_0\
);
\slv_reg2[23]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => s00_axi_wstrb(2),
I3 => p_0_in(0),
O => \slv_reg2[23]_i_1_n_0\
);
\slv_reg2[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => s00_axi_wstrb(3),
I3 => p_0_in(0),
O => \slv_reg2[31]_i_1_n_0\
);
\slv_reg2[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => s00_axi_wstrb(0),
I3 => p_0_in(0),
O => \slv_reg2[7]_i_1_n_0\
);
\slv_reg2_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[7]_i_1_n_0\,
D => s00_axi_wdata(0),
Q => slv_reg2(0),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[15]_i_1_n_0\,
D => s00_axi_wdata(10),
Q => slv_reg2(10),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[15]_i_1_n_0\,
D => s00_axi_wdata(11),
Q => slv_reg2(11),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[15]_i_1_n_0\,
D => s00_axi_wdata(12),
Q => slv_reg2(12),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[15]_i_1_n_0\,
D => s00_axi_wdata(13),
Q => slv_reg2(13),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[15]_i_1_n_0\,
D => s00_axi_wdata(14),
Q => slv_reg2(14),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[15]_i_1_n_0\,
D => s00_axi_wdata(15),
Q => slv_reg2(15),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[23]_i_1_n_0\,
D => s00_axi_wdata(16),
Q => slv_reg2(16),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[23]_i_1_n_0\,
D => s00_axi_wdata(17),
Q => slv_reg2(17),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[23]_i_1_n_0\,
D => s00_axi_wdata(18),
Q => slv_reg2(18),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[23]_i_1_n_0\,
D => s00_axi_wdata(19),
Q => slv_reg2(19),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[7]_i_1_n_0\,
D => s00_axi_wdata(1),
Q => slv_reg2(1),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[23]_i_1_n_0\,
D => s00_axi_wdata(20),
Q => slv_reg2(20),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[23]_i_1_n_0\,
D => s00_axi_wdata(21),
Q => slv_reg2(21),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[23]_i_1_n_0\,
D => s00_axi_wdata(22),
Q => slv_reg2(22),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[23]_i_1_n_0\,
D => s00_axi_wdata(23),
Q => slv_reg2(23),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[31]_i_1_n_0\,
D => s00_axi_wdata(24),
Q => slv_reg2(24),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[31]_i_1_n_0\,
D => s00_axi_wdata(25),
Q => slv_reg2(25),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[31]_i_1_n_0\,
D => s00_axi_wdata(26),
Q => slv_reg2(26),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[31]_i_1_n_0\,
D => s00_axi_wdata(27),
Q => slv_reg2(27),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[31]_i_1_n_0\,
D => s00_axi_wdata(28),
Q => slv_reg2(28),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[31]_i_1_n_0\,
D => s00_axi_wdata(29),
Q => slv_reg2(29),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[7]_i_1_n_0\,
D => s00_axi_wdata(2),
Q => slv_reg2(2),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[31]_i_1_n_0\,
D => s00_axi_wdata(30),
Q => slv_reg2(30),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[31]_i_1_n_0\,
D => s00_axi_wdata(31),
Q => slv_reg2(31),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[7]_i_1_n_0\,
D => s00_axi_wdata(3),
Q => slv_reg2(3),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[7]_i_1_n_0\,
D => s00_axi_wdata(4),
Q => slv_reg2(4),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[7]_i_1_n_0\,
D => s00_axi_wdata(5),
Q => slv_reg2(5),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[7]_i_1_n_0\,
D => s00_axi_wdata(6),
Q => slv_reg2(6),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[7]_i_1_n_0\,
D => s00_axi_wdata(7),
Q => slv_reg2(7),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[15]_i_1_n_0\,
D => s00_axi_wdata(8),
Q => slv_reg2(8),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[15]_i_1_n_0\,
D => s00_axi_wdata(9),
Q => slv_reg2(9),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3[15]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => s00_axi_wstrb(1),
I2 => p_0_in(0),
I3 => p_0_in(1),
O => \slv_reg3[15]_i_1_n_0\
);
\slv_reg3[23]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => s00_axi_wstrb(2),
I2 => p_0_in(0),
I3 => p_0_in(1),
O => \slv_reg3[23]_i_1_n_0\
);
\slv_reg3[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => s00_axi_wstrb(3),
I2 => p_0_in(0),
I3 => p_0_in(1),
O => \slv_reg3[31]_i_1_n_0\
);
\slv_reg3[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => s00_axi_wstrb(0),
I2 => p_0_in(0),
I3 => p_0_in(1),
O => \slv_reg3[7]_i_1_n_0\
);
\slv_reg3_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[7]_i_1_n_0\,
D => s00_axi_wdata(0),
Q => slv_reg3(0),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[15]_i_1_n_0\,
D => s00_axi_wdata(10),
Q => slv_reg3(10),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[15]_i_1_n_0\,
D => s00_axi_wdata(11),
Q => slv_reg3(11),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[15]_i_1_n_0\,
D => s00_axi_wdata(12),
Q => slv_reg3(12),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[15]_i_1_n_0\,
D => s00_axi_wdata(13),
Q => slv_reg3(13),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[15]_i_1_n_0\,
D => s00_axi_wdata(14),
Q => slv_reg3(14),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[15]_i_1_n_0\,
D => s00_axi_wdata(15),
Q => slv_reg3(15),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[23]_i_1_n_0\,
D => s00_axi_wdata(16),
Q => slv_reg3(16),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[23]_i_1_n_0\,
D => s00_axi_wdata(17),
Q => slv_reg3(17),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[23]_i_1_n_0\,
D => s00_axi_wdata(18),
Q => slv_reg3(18),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[23]_i_1_n_0\,
D => s00_axi_wdata(19),
Q => slv_reg3(19),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[7]_i_1_n_0\,
D => s00_axi_wdata(1),
Q => slv_reg3(1),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[23]_i_1_n_0\,
D => s00_axi_wdata(20),
Q => slv_reg3(20),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[23]_i_1_n_0\,
D => s00_axi_wdata(21),
Q => slv_reg3(21),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[23]_i_1_n_0\,
D => s00_axi_wdata(22),
Q => slv_reg3(22),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[23]_i_1_n_0\,
D => s00_axi_wdata(23),
Q => slv_reg3(23),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[31]_i_1_n_0\,
D => s00_axi_wdata(24),
Q => slv_reg3(24),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[31]_i_1_n_0\,
D => s00_axi_wdata(25),
Q => slv_reg3(25),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[31]_i_1_n_0\,
D => s00_axi_wdata(26),
Q => slv_reg3(26),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[31]_i_1_n_0\,
D => s00_axi_wdata(27),
Q => slv_reg3(27),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[31]_i_1_n_0\,
D => s00_axi_wdata(28),
Q => slv_reg3(28),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[31]_i_1_n_0\,
D => s00_axi_wdata(29),
Q => slv_reg3(29),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[7]_i_1_n_0\,
D => s00_axi_wdata(2),
Q => slv_reg3(2),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[31]_i_1_n_0\,
D => s00_axi_wdata(30),
Q => slv_reg3(30),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[31]_i_1_n_0\,
D => s00_axi_wdata(31),
Q => slv_reg3(31),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[7]_i_1_n_0\,
D => s00_axi_wdata(3),
Q => slv_reg3(3),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[7]_i_1_n_0\,
D => s00_axi_wdata(4),
Q => slv_reg3(4),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[7]_i_1_n_0\,
D => s00_axi_wdata(5),
Q => slv_reg3(5),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[7]_i_1_n_0\,
D => s00_axi_wdata(6),
Q => slv_reg3(6),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[7]_i_1_n_0\,
D => s00_axi_wdata(7),
Q => slv_reg3(7),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[15]_i_1_n_0\,
D => s00_axi_wdata(8),
Q => slv_reg3(8),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[15]_i_1_n_0\,
D => s00_axi_wdata(9),
Q => slv_reg3(9),
R => \slv_reg0[7]_i_1_n_0\
);
slv_reg_rden: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \^s00_axi_rvalid\,
I1 => s00_axi_arvalid,
I2 => \^s_axi_arready\,
O => \slv_reg_rden__0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity led_controller_design_led_controller_0_0_led_controller_v1_0 is
port (
S_AXI_ARREADY : out STD_LOGIC;
S_AXI_AWREADY : out STD_LOGIC;
S_AXI_WREADY : out STD_LOGIC;
LEDs_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_bvalid : out STD_LOGIC;
s00_axi_arvalid : in STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_araddr : in STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_aresetn : in STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_rready : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of led_controller_design_led_controller_0_0_led_controller_v1_0 : entity is "led_controller_v1_0";
end led_controller_design_led_controller_0_0_led_controller_v1_0;
architecture STRUCTURE of led_controller_design_led_controller_0_0_led_controller_v1_0 is
begin
led_controller_v1_0_S00_AXI_inst: entity work.led_controller_design_led_controller_0_0_led_controller_v1_0_S00_AXI
port map (
LEDs_out(7 downto 0) => LEDs_out(7 downto 0),
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WREADY => S_AXI_WREADY,
s00_axi_aclk => s00_axi_aclk,
s00_axi_araddr(1 downto 0) => s00_axi_araddr(1 downto 0),
s00_axi_aresetn => s00_axi_aresetn,
s00_axi_arvalid => s00_axi_arvalid,
s00_axi_awaddr(1 downto 0) => s00_axi_awaddr(1 downto 0),
s00_axi_awvalid => s00_axi_awvalid,
s00_axi_bready => s00_axi_bready,
s00_axi_bvalid => s00_axi_bvalid,
s00_axi_rdata(31 downto 0) => s00_axi_rdata(31 downto 0),
s00_axi_rready => s00_axi_rready,
s00_axi_rvalid => s00_axi_rvalid,
s00_axi_wdata(31 downto 0) => s00_axi_wdata(31 downto 0),
s00_axi_wstrb(3 downto 0) => s00_axi_wstrb(3 downto 0),
s00_axi_wvalid => s00_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity led_controller_design_led_controller_0_0 is
port (
LEDs_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_awready : out STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wready : out STD_LOGIC;
s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_bvalid : out STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_arvalid : in STD_LOGIC;
s00_axi_arready : out STD_LOGIC;
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of led_controller_design_led_controller_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of led_controller_design_led_controller_0_0 : entity is "led_controller_design_led_controller_0_0,led_controller_v1_0,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of led_controller_design_led_controller_0_0 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of led_controller_design_led_controller_0_0 : entity is "led_controller_v1_0,Vivado 2017.3";
end led_controller_design_led_controller_0_0;
architecture STRUCTURE of led_controller_design_led_controller_0_0 is
signal \<const0>\ : STD_LOGIC;
attribute X_INTERFACE_INFO : string;
attribute X_INTERFACE_INFO of s00_axi_aclk : signal is "xilinx.com:signal:clock:1.0 S00_AXI_CLK CLK";
attribute X_INTERFACE_PARAMETER : string;
attribute X_INTERFACE_PARAMETER of s00_axi_aclk : signal is "XIL_INTERFACENAME S00_AXI_CLK, ASSOCIATED_BUSIF S00_AXI, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN led_controller_design_processing_system7_0_0_FCLK_CLK0";
attribute X_INTERFACE_INFO of s00_axi_aresetn : signal is "xilinx.com:signal:reset:1.0 S00_AXI_RST RST";
attribute X_INTERFACE_PARAMETER of s00_axi_aresetn : signal is "XIL_INTERFACENAME S00_AXI_RST, POLARITY ACTIVE_LOW";
attribute X_INTERFACE_INFO of s00_axi_arready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY";
attribute X_INTERFACE_INFO of s00_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID";
attribute X_INTERFACE_INFO of s00_axi_awready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY";
attribute X_INTERFACE_INFO of s00_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID";
attribute X_INTERFACE_INFO of s00_axi_bready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI BREADY";
attribute X_INTERFACE_INFO of s00_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI BVALID";
attribute X_INTERFACE_INFO of s00_axi_rready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RREADY";
attribute X_INTERFACE_PARAMETER of s00_axi_rready : signal is "XIL_INTERFACENAME S00_AXI, WIZ_DATA_WIDTH 32, WIZ_NUM_REG 4, SUPPORTS_NARROW_BURST 0, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 4, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN led_controller_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
attribute X_INTERFACE_INFO of s00_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RVALID";
attribute X_INTERFACE_INFO of s00_axi_wready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WREADY";
attribute X_INTERFACE_INFO of s00_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WVALID";
attribute X_INTERFACE_INFO of s00_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR";
attribute X_INTERFACE_INFO of s00_axi_arprot : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT";
attribute X_INTERFACE_INFO of s00_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR";
attribute X_INTERFACE_INFO of s00_axi_awprot : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT";
attribute X_INTERFACE_INFO of s00_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 S00_AXI BRESP";
attribute X_INTERFACE_INFO of s00_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RDATA";
attribute X_INTERFACE_INFO of s00_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RRESP";
attribute X_INTERFACE_INFO of s00_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WDATA";
attribute X_INTERFACE_INFO of s00_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB";
begin
s00_axi_bresp(1) <= \<const0>\;
s00_axi_bresp(0) <= \<const0>\;
s00_axi_rresp(1) <= \<const0>\;
s00_axi_rresp(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst: entity work.led_controller_design_led_controller_0_0_led_controller_v1_0
port map (
LEDs_out(7 downto 0) => LEDs_out(7 downto 0),
S_AXI_ARREADY => s00_axi_arready,
S_AXI_AWREADY => s00_axi_awready,
S_AXI_WREADY => s00_axi_wready,
s00_axi_aclk => s00_axi_aclk,
s00_axi_araddr(1 downto 0) => s00_axi_araddr(3 downto 2),
s00_axi_aresetn => s00_axi_aresetn,
s00_axi_arvalid => s00_axi_arvalid,
s00_axi_awaddr(1 downto 0) => s00_axi_awaddr(3 downto 2),
s00_axi_awvalid => s00_axi_awvalid,
s00_axi_bready => s00_axi_bready,
s00_axi_bvalid => s00_axi_bvalid,
s00_axi_rdata(31 downto 0) => s00_axi_rdata(31 downto 0),
s00_axi_rready => s00_axi_rready,
s00_axi_rvalid => s00_axi_rvalid,
s00_axi_wdata(31 downto 0) => s00_axi_wdata(31 downto 0),
s00_axi_wstrb(3 downto 0) => s00_axi_wstrb(3 downto 0),
s00_axi_wvalid => s00_axi_wvalid
);
end STRUCTURE;
| mit | 0fdb9df4bbe7719bf04ebbc995b5a67b | 0.514893 | 2.535662 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/ug871-design-files/Interface_Synthesis/lab4/axi_interfaces_prj/solution1/syn/vhdl/axi_interfaces.vhd | 1 | 112,999 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity axi_interfaces is
port (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
d_o_0_TREADY : IN STD_LOGIC;
d_o_1_TREADY : IN STD_LOGIC;
d_o_2_TREADY : IN STD_LOGIC;
d_o_3_TREADY : IN STD_LOGIC;
d_o_4_TREADY : IN STD_LOGIC;
d_o_5_TREADY : IN STD_LOGIC;
d_o_6_TREADY : IN STD_LOGIC;
d_o_7_TREADY : IN STD_LOGIC;
d_o_0_TDATA : OUT STD_LOGIC_VECTOR (15 downto 0);
d_o_0_TVALID : OUT STD_LOGIC;
d_o_1_TDATA : OUT STD_LOGIC_VECTOR (15 downto 0);
d_o_1_TVALID : OUT STD_LOGIC;
d_o_2_TDATA : OUT STD_LOGIC_VECTOR (15 downto 0);
d_o_2_TVALID : OUT STD_LOGIC;
d_o_3_TDATA : OUT STD_LOGIC_VECTOR (15 downto 0);
d_o_3_TVALID : OUT STD_LOGIC;
d_o_4_TDATA : OUT STD_LOGIC_VECTOR (15 downto 0);
d_o_4_TVALID : OUT STD_LOGIC;
d_o_5_TDATA : OUT STD_LOGIC_VECTOR (15 downto 0);
d_o_5_TVALID : OUT STD_LOGIC;
d_o_6_TDATA : OUT STD_LOGIC_VECTOR (15 downto 0);
d_o_6_TVALID : OUT STD_LOGIC;
d_o_7_TDATA : OUT STD_LOGIC_VECTOR (15 downto 0);
d_o_7_TVALID : OUT STD_LOGIC;
d_i_0_TDATA : IN STD_LOGIC_VECTOR (15 downto 0);
d_i_0_TVALID : IN STD_LOGIC;
d_i_0_TREADY : OUT STD_LOGIC;
d_i_1_TDATA : IN STD_LOGIC_VECTOR (15 downto 0);
d_i_1_TVALID : IN STD_LOGIC;
d_i_1_TREADY : OUT STD_LOGIC;
d_i_2_TDATA : IN STD_LOGIC_VECTOR (15 downto 0);
d_i_2_TVALID : IN STD_LOGIC;
d_i_2_TREADY : OUT STD_LOGIC;
d_i_3_TDATA : IN STD_LOGIC_VECTOR (15 downto 0);
d_i_3_TVALID : IN STD_LOGIC;
d_i_3_TREADY : OUT STD_LOGIC;
d_i_4_TDATA : IN STD_LOGIC_VECTOR (15 downto 0);
d_i_4_TVALID : IN STD_LOGIC;
d_i_4_TREADY : OUT STD_LOGIC;
d_i_5_TDATA : IN STD_LOGIC_VECTOR (15 downto 0);
d_i_5_TVALID : IN STD_LOGIC;
d_i_5_TREADY : OUT STD_LOGIC;
d_i_6_TDATA : IN STD_LOGIC_VECTOR (15 downto 0);
d_i_6_TVALID : IN STD_LOGIC;
d_i_6_TREADY : OUT STD_LOGIC;
d_i_7_TDATA : IN STD_LOGIC_VECTOR (15 downto 0);
d_i_7_TVALID : IN STD_LOGIC;
d_i_7_TREADY : OUT STD_LOGIC );
end;
architecture behav of axi_interfaces is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"axi_interfaces,hls_ip_2017_2,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7k160tfbg484-1,HLS_INPUT_CLOCK=4.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=4.162500,HLS_SYN_LAT=5,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=2103,HLS_SYN_LUT=1156}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_boolean_1 : BOOLEAN := true;
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_boolean_0 : BOOLEAN := false;
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_const_lv2_3 : STD_LOGIC_VECTOR (1 downto 0) := "11";
constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_const_lv5_0 : STD_LOGIC_VECTOR (4 downto 0) := "00000";
constant ap_const_lv6_8 : STD_LOGIC_VECTOR (5 downto 0) := "001000";
constant ap_const_lv6_20 : STD_LOGIC_VECTOR (5 downto 0) := "100000";
signal ap_rst_n_inv : STD_LOGIC;
signal ap_CS_fsm : STD_LOGIC_VECTOR (1 downto 0) := "01";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal exitcond_fu_244_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
signal ap_enable_reg_pp0_iter0 : STD_LOGIC;
signal ap_block_state2_pp0_stage0_iter0 : BOOLEAN;
signal d_i_0_0_vld_out : STD_LOGIC;
signal d_i_1_0_vld_out : STD_LOGIC;
signal d_i_2_0_vld_out : STD_LOGIC;
signal d_i_3_0_vld_out : STD_LOGIC;
signal d_i_4_0_vld_out : STD_LOGIC;
signal d_i_5_0_vld_out : STD_LOGIC;
signal d_i_6_0_vld_out : STD_LOGIC;
signal d_i_7_0_vld_out : STD_LOGIC;
signal ap_block_state4_pp0_stage0_iter1 : BOOLEAN;
signal d_o_0_1_ack_in : STD_LOGIC;
signal d_o_1_1_ack_in : STD_LOGIC;
signal d_o_2_1_ack_in : STD_LOGIC;
signal d_o_3_1_ack_in : STD_LOGIC;
signal d_o_4_1_ack_in : STD_LOGIC;
signal d_o_5_1_ack_in : STD_LOGIC;
signal d_o_6_1_ack_in : STD_LOGIC;
signal d_o_7_1_ack_in : STD_LOGIC;
signal ap_block_state4_io : BOOLEAN;
signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
signal ap_block_state3_pp0_stage0_iter2 : BOOLEAN;
signal ap_block_state3_io : BOOLEAN;
signal ap_enable_reg_pp0_iter2 : STD_LOGIC := '0';
signal ap_block_pp0_stage0_flag00011001 : BOOLEAN;
signal d_o_0_1_data_out : STD_LOGIC_VECTOR (15 downto 0);
signal d_o_0_1_vld_in : STD_LOGIC;
signal d_o_0_1_vld_out : STD_LOGIC;
signal d_o_0_1_ack_out : STD_LOGIC;
signal d_o_0_1_payload_A : STD_LOGIC_VECTOR (15 downto 0);
signal d_o_0_1_payload_B : STD_LOGIC_VECTOR (15 downto 0);
signal d_o_0_1_sel_rd : STD_LOGIC := '0';
signal d_o_0_1_sel_wr : STD_LOGIC := '0';
signal d_o_0_1_sel : STD_LOGIC;
signal d_o_0_1_load_A : STD_LOGIC;
signal d_o_0_1_load_B : STD_LOGIC;
signal d_o_0_1_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal d_o_0_1_state_cmp_full : STD_LOGIC;
signal d_o_1_1_data_out : STD_LOGIC_VECTOR (15 downto 0);
signal d_o_1_1_vld_in : STD_LOGIC;
signal d_o_1_1_vld_out : STD_LOGIC;
signal d_o_1_1_ack_out : STD_LOGIC;
signal d_o_1_1_payload_A : STD_LOGIC_VECTOR (15 downto 0);
signal d_o_1_1_payload_B : STD_LOGIC_VECTOR (15 downto 0);
signal d_o_1_1_sel_rd : STD_LOGIC := '0';
signal d_o_1_1_sel_wr : STD_LOGIC := '0';
signal d_o_1_1_sel : STD_LOGIC;
signal d_o_1_1_load_A : STD_LOGIC;
signal d_o_1_1_load_B : STD_LOGIC;
signal d_o_1_1_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal d_o_1_1_state_cmp_full : STD_LOGIC;
signal d_o_2_1_data_out : STD_LOGIC_VECTOR (15 downto 0);
signal d_o_2_1_vld_in : STD_LOGIC;
signal d_o_2_1_vld_out : STD_LOGIC;
signal d_o_2_1_ack_out : STD_LOGIC;
signal d_o_2_1_payload_A : STD_LOGIC_VECTOR (15 downto 0);
signal d_o_2_1_payload_B : STD_LOGIC_VECTOR (15 downto 0);
signal d_o_2_1_sel_rd : STD_LOGIC := '0';
signal d_o_2_1_sel_wr : STD_LOGIC := '0';
signal d_o_2_1_sel : STD_LOGIC;
signal d_o_2_1_load_A : STD_LOGIC;
signal d_o_2_1_load_B : STD_LOGIC;
signal d_o_2_1_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal d_o_2_1_state_cmp_full : STD_LOGIC;
signal d_o_3_1_data_out : STD_LOGIC_VECTOR (15 downto 0);
signal d_o_3_1_vld_in : STD_LOGIC;
signal d_o_3_1_vld_out : STD_LOGIC;
signal d_o_3_1_ack_out : STD_LOGIC;
signal d_o_3_1_payload_A : STD_LOGIC_VECTOR (15 downto 0);
signal d_o_3_1_payload_B : STD_LOGIC_VECTOR (15 downto 0);
signal d_o_3_1_sel_rd : STD_LOGIC := '0';
signal d_o_3_1_sel_wr : STD_LOGIC := '0';
signal d_o_3_1_sel : STD_LOGIC;
signal d_o_3_1_load_A : STD_LOGIC;
signal d_o_3_1_load_B : STD_LOGIC;
signal d_o_3_1_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal d_o_3_1_state_cmp_full : STD_LOGIC;
signal d_o_4_1_data_out : STD_LOGIC_VECTOR (15 downto 0);
signal d_o_4_1_vld_in : STD_LOGIC;
signal d_o_4_1_vld_out : STD_LOGIC;
signal d_o_4_1_ack_out : STD_LOGIC;
signal d_o_4_1_payload_A : STD_LOGIC_VECTOR (15 downto 0);
signal d_o_4_1_payload_B : STD_LOGIC_VECTOR (15 downto 0);
signal d_o_4_1_sel_rd : STD_LOGIC := '0';
signal d_o_4_1_sel_wr : STD_LOGIC := '0';
signal d_o_4_1_sel : STD_LOGIC;
signal d_o_4_1_load_A : STD_LOGIC;
signal d_o_4_1_load_B : STD_LOGIC;
signal d_o_4_1_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal d_o_4_1_state_cmp_full : STD_LOGIC;
signal d_o_5_1_data_out : STD_LOGIC_VECTOR (15 downto 0);
signal d_o_5_1_vld_in : STD_LOGIC;
signal d_o_5_1_vld_out : STD_LOGIC;
signal d_o_5_1_ack_out : STD_LOGIC;
signal d_o_5_1_payload_A : STD_LOGIC_VECTOR (15 downto 0);
signal d_o_5_1_payload_B : STD_LOGIC_VECTOR (15 downto 0);
signal d_o_5_1_sel_rd : STD_LOGIC := '0';
signal d_o_5_1_sel_wr : STD_LOGIC := '0';
signal d_o_5_1_sel : STD_LOGIC;
signal d_o_5_1_load_A : STD_LOGIC;
signal d_o_5_1_load_B : STD_LOGIC;
signal d_o_5_1_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal d_o_5_1_state_cmp_full : STD_LOGIC;
signal d_o_6_1_data_out : STD_LOGIC_VECTOR (15 downto 0);
signal d_o_6_1_vld_in : STD_LOGIC;
signal d_o_6_1_vld_out : STD_LOGIC;
signal d_o_6_1_ack_out : STD_LOGIC;
signal d_o_6_1_payload_A : STD_LOGIC_VECTOR (15 downto 0);
signal d_o_6_1_payload_B : STD_LOGIC_VECTOR (15 downto 0);
signal d_o_6_1_sel_rd : STD_LOGIC := '0';
signal d_o_6_1_sel_wr : STD_LOGIC := '0';
signal d_o_6_1_sel : STD_LOGIC;
signal d_o_6_1_load_A : STD_LOGIC;
signal d_o_6_1_load_B : STD_LOGIC;
signal d_o_6_1_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal d_o_6_1_state_cmp_full : STD_LOGIC;
signal d_o_7_1_data_out : STD_LOGIC_VECTOR (15 downto 0);
signal d_o_7_1_vld_in : STD_LOGIC;
signal d_o_7_1_vld_out : STD_LOGIC;
signal d_o_7_1_ack_out : STD_LOGIC;
signal d_o_7_1_payload_A : STD_LOGIC_VECTOR (15 downto 0);
signal d_o_7_1_payload_B : STD_LOGIC_VECTOR (15 downto 0);
signal d_o_7_1_sel_rd : STD_LOGIC := '0';
signal d_o_7_1_sel_wr : STD_LOGIC := '0';
signal d_o_7_1_sel : STD_LOGIC;
signal d_o_7_1_load_A : STD_LOGIC;
signal d_o_7_1_load_B : STD_LOGIC;
signal d_o_7_1_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal d_o_7_1_state_cmp_full : STD_LOGIC;
signal d_i_0_0_data_out : STD_LOGIC_VECTOR (15 downto 0);
signal d_i_0_0_vld_in : STD_LOGIC;
signal d_i_0_0_ack_in : STD_LOGIC;
signal d_i_0_0_ack_out : STD_LOGIC;
signal d_i_0_0_payload_A : STD_LOGIC_VECTOR (15 downto 0);
signal d_i_0_0_payload_B : STD_LOGIC_VECTOR (15 downto 0);
signal d_i_0_0_sel_rd : STD_LOGIC := '0';
signal d_i_0_0_sel_wr : STD_LOGIC := '0';
signal d_i_0_0_sel : STD_LOGIC;
signal d_i_0_0_load_A : STD_LOGIC;
signal d_i_0_0_load_B : STD_LOGIC;
signal d_i_0_0_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal d_i_0_0_state_cmp_full : STD_LOGIC;
signal d_i_1_0_data_out : STD_LOGIC_VECTOR (15 downto 0);
signal d_i_1_0_vld_in : STD_LOGIC;
signal d_i_1_0_ack_in : STD_LOGIC;
signal d_i_1_0_ack_out : STD_LOGIC;
signal d_i_1_0_payload_A : STD_LOGIC_VECTOR (15 downto 0);
signal d_i_1_0_payload_B : STD_LOGIC_VECTOR (15 downto 0);
signal d_i_1_0_sel_rd : STD_LOGIC := '0';
signal d_i_1_0_sel_wr : STD_LOGIC := '0';
signal d_i_1_0_sel : STD_LOGIC;
signal d_i_1_0_load_A : STD_LOGIC;
signal d_i_1_0_load_B : STD_LOGIC;
signal d_i_1_0_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal d_i_1_0_state_cmp_full : STD_LOGIC;
signal d_i_2_0_data_out : STD_LOGIC_VECTOR (15 downto 0);
signal d_i_2_0_vld_in : STD_LOGIC;
signal d_i_2_0_ack_in : STD_LOGIC;
signal d_i_2_0_ack_out : STD_LOGIC;
signal d_i_2_0_payload_A : STD_LOGIC_VECTOR (15 downto 0);
signal d_i_2_0_payload_B : STD_LOGIC_VECTOR (15 downto 0);
signal d_i_2_0_sel_rd : STD_LOGIC := '0';
signal d_i_2_0_sel_wr : STD_LOGIC := '0';
signal d_i_2_0_sel : STD_LOGIC;
signal d_i_2_0_load_A : STD_LOGIC;
signal d_i_2_0_load_B : STD_LOGIC;
signal d_i_2_0_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal d_i_2_0_state_cmp_full : STD_LOGIC;
signal d_i_3_0_data_out : STD_LOGIC_VECTOR (15 downto 0);
signal d_i_3_0_vld_in : STD_LOGIC;
signal d_i_3_0_ack_in : STD_LOGIC;
signal d_i_3_0_ack_out : STD_LOGIC;
signal d_i_3_0_payload_A : STD_LOGIC_VECTOR (15 downto 0);
signal d_i_3_0_payload_B : STD_LOGIC_VECTOR (15 downto 0);
signal d_i_3_0_sel_rd : STD_LOGIC := '0';
signal d_i_3_0_sel_wr : STD_LOGIC := '0';
signal d_i_3_0_sel : STD_LOGIC;
signal d_i_3_0_load_A : STD_LOGIC;
signal d_i_3_0_load_B : STD_LOGIC;
signal d_i_3_0_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal d_i_3_0_state_cmp_full : STD_LOGIC;
signal d_i_4_0_data_out : STD_LOGIC_VECTOR (15 downto 0);
signal d_i_4_0_vld_in : STD_LOGIC;
signal d_i_4_0_ack_in : STD_LOGIC;
signal d_i_4_0_ack_out : STD_LOGIC;
signal d_i_4_0_payload_A : STD_LOGIC_VECTOR (15 downto 0);
signal d_i_4_0_payload_B : STD_LOGIC_VECTOR (15 downto 0);
signal d_i_4_0_sel_rd : STD_LOGIC := '0';
signal d_i_4_0_sel_wr : STD_LOGIC := '0';
signal d_i_4_0_sel : STD_LOGIC;
signal d_i_4_0_load_A : STD_LOGIC;
signal d_i_4_0_load_B : STD_LOGIC;
signal d_i_4_0_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal d_i_4_0_state_cmp_full : STD_LOGIC;
signal d_i_5_0_data_out : STD_LOGIC_VECTOR (15 downto 0);
signal d_i_5_0_vld_in : STD_LOGIC;
signal d_i_5_0_ack_in : STD_LOGIC;
signal d_i_5_0_ack_out : STD_LOGIC;
signal d_i_5_0_payload_A : STD_LOGIC_VECTOR (15 downto 0);
signal d_i_5_0_payload_B : STD_LOGIC_VECTOR (15 downto 0);
signal d_i_5_0_sel_rd : STD_LOGIC := '0';
signal d_i_5_0_sel_wr : STD_LOGIC := '0';
signal d_i_5_0_sel : STD_LOGIC;
signal d_i_5_0_load_A : STD_LOGIC;
signal d_i_5_0_load_B : STD_LOGIC;
signal d_i_5_0_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal d_i_5_0_state_cmp_full : STD_LOGIC;
signal d_i_6_0_data_out : STD_LOGIC_VECTOR (15 downto 0);
signal d_i_6_0_vld_in : STD_LOGIC;
signal d_i_6_0_ack_in : STD_LOGIC;
signal d_i_6_0_ack_out : STD_LOGIC;
signal d_i_6_0_payload_A : STD_LOGIC_VECTOR (15 downto 0);
signal d_i_6_0_payload_B : STD_LOGIC_VECTOR (15 downto 0);
signal d_i_6_0_sel_rd : STD_LOGIC := '0';
signal d_i_6_0_sel_wr : STD_LOGIC := '0';
signal d_i_6_0_sel : STD_LOGIC;
signal d_i_6_0_load_A : STD_LOGIC;
signal d_i_6_0_load_B : STD_LOGIC;
signal d_i_6_0_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal d_i_6_0_state_cmp_full : STD_LOGIC;
signal d_i_7_0_data_out : STD_LOGIC_VECTOR (15 downto 0);
signal d_i_7_0_vld_in : STD_LOGIC;
signal d_i_7_0_ack_in : STD_LOGIC;
signal d_i_7_0_ack_out : STD_LOGIC;
signal d_i_7_0_payload_A : STD_LOGIC_VECTOR (15 downto 0);
signal d_i_7_0_payload_B : STD_LOGIC_VECTOR (15 downto 0);
signal d_i_7_0_sel_rd : STD_LOGIC := '0';
signal d_i_7_0_sel_wr : STD_LOGIC := '0';
signal d_i_7_0_sel : STD_LOGIC;
signal d_i_7_0_load_A : STD_LOGIC;
signal d_i_7_0_load_B : STD_LOGIC;
signal d_i_7_0_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal d_i_7_0_state_cmp_full : STD_LOGIC;
signal acc_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal acc_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal acc_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal acc_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal acc_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal acc_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal acc_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal acc_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal d_o_0_TDATA_blk_n : STD_LOGIC;
signal ap_block_pp0_stage0_flag00000000 : BOOLEAN;
signal d_o_1_TDATA_blk_n : STD_LOGIC;
signal d_o_2_TDATA_blk_n : STD_LOGIC;
signal d_o_3_TDATA_blk_n : STD_LOGIC;
signal d_o_4_TDATA_blk_n : STD_LOGIC;
signal d_o_5_TDATA_blk_n : STD_LOGIC;
signal d_o_6_TDATA_blk_n : STD_LOGIC;
signal d_o_7_TDATA_blk_n : STD_LOGIC;
signal d_i_0_TDATA_blk_n : STD_LOGIC;
signal d_i_1_TDATA_blk_n : STD_LOGIC;
signal d_i_2_TDATA_blk_n : STD_LOGIC;
signal d_i_3_TDATA_blk_n : STD_LOGIC;
signal d_i_4_TDATA_blk_n : STD_LOGIC;
signal d_i_5_TDATA_blk_n : STD_LOGIC;
signal d_i_6_TDATA_blk_n : STD_LOGIC;
signal d_i_7_TDATA_blk_n : STD_LOGIC;
signal i1_reg_216 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_17_fu_240_p1 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_17_reg_500 : STD_LOGIC_VECTOR (4 downto 0);
signal exitcond_reg_505 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter1_exitcond_reg_505 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_8_fu_276_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_1_fu_307_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_2_fu_338_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_3_fu_369_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_4_fu_400_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_5_fu_431_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_6_fu_462_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_7_fu_493_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_block_pp0_stage0_flag00011011 : BOOLEAN;
signal i1_phi_fu_220_p6 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_1_fu_264_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_1_1_fu_295_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_1_2_fu_326_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_1_3_fu_357_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_1_4_fu_388_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_1_5_fu_419_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_1_6_fu_450_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_1_7_fu_481_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_block_pp0_stage0_flag00001001 : BOOLEAN;
signal i1_cast_fu_230_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal i_1_7_fu_234_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp1_fu_256_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_2_fu_260_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_s_fu_287_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_fu_291_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_9_fu_318_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_fu_322_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_fu_349_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_fu_353_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_4_fu_380_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_13_fu_384_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_5_fu_411_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_14_fu_415_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_6_fu_442_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_15_fu_446_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_7_fu_473_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_16_fu_477_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (1 downto 0);
signal ap_idle_pp0_0to1 : STD_LOGIC;
signal ap_reset_idle_pp0 : STD_LOGIC;
signal ap_idle_pp0 : STD_LOGIC;
signal ap_enable_pp0 : STD_LOGIC;
signal ap_condition_1051 : BOOLEAN;
begin
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter1 <= ap_start;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_enable_reg_pp0_iter2 <= ap_const_logic_0;
else
if ((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0)) then
ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_enable_reg_pp0_iter2 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
d_i_0_0_sel_rd_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
d_i_0_0_sel_rd <= ap_const_logic_0;
else
if (((ap_const_logic_1 = d_i_0_0_ack_out) and (ap_const_logic_1 = d_i_0_0_vld_out))) then
d_i_0_0_sel_rd <= not(d_i_0_0_sel_rd);
end if;
end if;
end if;
end process;
d_i_0_0_sel_wr_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
d_i_0_0_sel_wr <= ap_const_logic_0;
else
if (((ap_const_logic_1 = d_i_0_0_vld_in) and (ap_const_logic_1 = d_i_0_0_ack_in))) then
d_i_0_0_sel_wr <= not(d_i_0_0_sel_wr);
end if;
end if;
end if;
end process;
d_i_0_0_state_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
d_i_0_0_state <= ap_const_lv2_0;
else
if ((((ap_const_logic_0 = d_i_0_0_vld_in) and (ap_const_logic_1 = d_i_0_0_ack_out) and (ap_const_lv2_3 = d_i_0_0_state)) or ((ap_const_logic_0 = d_i_0_0_vld_in) and (ap_const_lv2_2 = d_i_0_0_state)))) then
d_i_0_0_state <= ap_const_lv2_2;
elsif ((((ap_const_logic_1 = d_i_0_0_vld_in) and (ap_const_logic_0 = d_i_0_0_ack_out) and (ap_const_lv2_3 = d_i_0_0_state)) or ((ap_const_logic_0 = d_i_0_0_ack_out) and (ap_const_lv2_1 = d_i_0_0_state)))) then
d_i_0_0_state <= ap_const_lv2_1;
elsif ((((ap_const_logic_1 = d_i_0_0_vld_in) and (ap_const_lv2_2 = d_i_0_0_state)) or ((ap_const_logic_1 = d_i_0_0_ack_out) and (ap_const_lv2_1 = d_i_0_0_state)) or ((ap_const_lv2_3 = d_i_0_0_state) and not(((ap_const_logic_1 = d_i_0_0_vld_in) and (ap_const_logic_0 = d_i_0_0_ack_out))) and not(((ap_const_logic_0 = d_i_0_0_vld_in) and (ap_const_logic_1 = d_i_0_0_ack_out)))))) then
d_i_0_0_state <= ap_const_lv2_3;
else
d_i_0_0_state <= ap_const_lv2_2;
end if;
end if;
end if;
end process;
d_i_1_0_sel_rd_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
d_i_1_0_sel_rd <= ap_const_logic_0;
else
if (((ap_const_logic_1 = d_i_1_0_ack_out) and (ap_const_logic_1 = d_i_1_0_vld_out))) then
d_i_1_0_sel_rd <= not(d_i_1_0_sel_rd);
end if;
end if;
end if;
end process;
d_i_1_0_sel_wr_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
d_i_1_0_sel_wr <= ap_const_logic_0;
else
if (((ap_const_logic_1 = d_i_1_0_vld_in) and (ap_const_logic_1 = d_i_1_0_ack_in))) then
d_i_1_0_sel_wr <= not(d_i_1_0_sel_wr);
end if;
end if;
end if;
end process;
d_i_1_0_state_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
d_i_1_0_state <= ap_const_lv2_0;
else
if ((((ap_const_logic_0 = d_i_1_0_vld_in) and (ap_const_logic_1 = d_i_1_0_ack_out) and (ap_const_lv2_3 = d_i_1_0_state)) or ((ap_const_logic_0 = d_i_1_0_vld_in) and (ap_const_lv2_2 = d_i_1_0_state)))) then
d_i_1_0_state <= ap_const_lv2_2;
elsif ((((ap_const_logic_1 = d_i_1_0_vld_in) and (ap_const_logic_0 = d_i_1_0_ack_out) and (ap_const_lv2_3 = d_i_1_0_state)) or ((ap_const_logic_0 = d_i_1_0_ack_out) and (ap_const_lv2_1 = d_i_1_0_state)))) then
d_i_1_0_state <= ap_const_lv2_1;
elsif ((((ap_const_logic_1 = d_i_1_0_vld_in) and (ap_const_lv2_2 = d_i_1_0_state)) or ((ap_const_logic_1 = d_i_1_0_ack_out) and (ap_const_lv2_1 = d_i_1_0_state)) or ((ap_const_lv2_3 = d_i_1_0_state) and not(((ap_const_logic_1 = d_i_1_0_vld_in) and (ap_const_logic_0 = d_i_1_0_ack_out))) and not(((ap_const_logic_0 = d_i_1_0_vld_in) and (ap_const_logic_1 = d_i_1_0_ack_out)))))) then
d_i_1_0_state <= ap_const_lv2_3;
else
d_i_1_0_state <= ap_const_lv2_2;
end if;
end if;
end if;
end process;
d_i_2_0_sel_rd_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
d_i_2_0_sel_rd <= ap_const_logic_0;
else
if (((ap_const_logic_1 = d_i_2_0_ack_out) and (ap_const_logic_1 = d_i_2_0_vld_out))) then
d_i_2_0_sel_rd <= not(d_i_2_0_sel_rd);
end if;
end if;
end if;
end process;
d_i_2_0_sel_wr_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
d_i_2_0_sel_wr <= ap_const_logic_0;
else
if (((ap_const_logic_1 = d_i_2_0_vld_in) and (ap_const_logic_1 = d_i_2_0_ack_in))) then
d_i_2_0_sel_wr <= not(d_i_2_0_sel_wr);
end if;
end if;
end if;
end process;
d_i_2_0_state_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
d_i_2_0_state <= ap_const_lv2_0;
else
if ((((ap_const_logic_0 = d_i_2_0_vld_in) and (ap_const_logic_1 = d_i_2_0_ack_out) and (ap_const_lv2_3 = d_i_2_0_state)) or ((ap_const_logic_0 = d_i_2_0_vld_in) and (ap_const_lv2_2 = d_i_2_0_state)))) then
d_i_2_0_state <= ap_const_lv2_2;
elsif ((((ap_const_logic_1 = d_i_2_0_vld_in) and (ap_const_logic_0 = d_i_2_0_ack_out) and (ap_const_lv2_3 = d_i_2_0_state)) or ((ap_const_logic_0 = d_i_2_0_ack_out) and (ap_const_lv2_1 = d_i_2_0_state)))) then
d_i_2_0_state <= ap_const_lv2_1;
elsif ((((ap_const_logic_1 = d_i_2_0_vld_in) and (ap_const_lv2_2 = d_i_2_0_state)) or ((ap_const_logic_1 = d_i_2_0_ack_out) and (ap_const_lv2_1 = d_i_2_0_state)) or ((ap_const_lv2_3 = d_i_2_0_state) and not(((ap_const_logic_1 = d_i_2_0_vld_in) and (ap_const_logic_0 = d_i_2_0_ack_out))) and not(((ap_const_logic_0 = d_i_2_0_vld_in) and (ap_const_logic_1 = d_i_2_0_ack_out)))))) then
d_i_2_0_state <= ap_const_lv2_3;
else
d_i_2_0_state <= ap_const_lv2_2;
end if;
end if;
end if;
end process;
d_i_3_0_sel_rd_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
d_i_3_0_sel_rd <= ap_const_logic_0;
else
if (((ap_const_logic_1 = d_i_3_0_ack_out) and (ap_const_logic_1 = d_i_3_0_vld_out))) then
d_i_3_0_sel_rd <= not(d_i_3_0_sel_rd);
end if;
end if;
end if;
end process;
d_i_3_0_sel_wr_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
d_i_3_0_sel_wr <= ap_const_logic_0;
else
if (((ap_const_logic_1 = d_i_3_0_vld_in) and (ap_const_logic_1 = d_i_3_0_ack_in))) then
d_i_3_0_sel_wr <= not(d_i_3_0_sel_wr);
end if;
end if;
end if;
end process;
d_i_3_0_state_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
d_i_3_0_state <= ap_const_lv2_0;
else
if ((((ap_const_logic_0 = d_i_3_0_vld_in) and (ap_const_logic_1 = d_i_3_0_ack_out) and (ap_const_lv2_3 = d_i_3_0_state)) or ((ap_const_logic_0 = d_i_3_0_vld_in) and (ap_const_lv2_2 = d_i_3_0_state)))) then
d_i_3_0_state <= ap_const_lv2_2;
elsif ((((ap_const_logic_1 = d_i_3_0_vld_in) and (ap_const_logic_0 = d_i_3_0_ack_out) and (ap_const_lv2_3 = d_i_3_0_state)) or ((ap_const_logic_0 = d_i_3_0_ack_out) and (ap_const_lv2_1 = d_i_3_0_state)))) then
d_i_3_0_state <= ap_const_lv2_1;
elsif ((((ap_const_logic_1 = d_i_3_0_vld_in) and (ap_const_lv2_2 = d_i_3_0_state)) or ((ap_const_logic_1 = d_i_3_0_ack_out) and (ap_const_lv2_1 = d_i_3_0_state)) or ((ap_const_lv2_3 = d_i_3_0_state) and not(((ap_const_logic_1 = d_i_3_0_vld_in) and (ap_const_logic_0 = d_i_3_0_ack_out))) and not(((ap_const_logic_0 = d_i_3_0_vld_in) and (ap_const_logic_1 = d_i_3_0_ack_out)))))) then
d_i_3_0_state <= ap_const_lv2_3;
else
d_i_3_0_state <= ap_const_lv2_2;
end if;
end if;
end if;
end process;
d_i_4_0_sel_rd_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
d_i_4_0_sel_rd <= ap_const_logic_0;
else
if (((ap_const_logic_1 = d_i_4_0_ack_out) and (ap_const_logic_1 = d_i_4_0_vld_out))) then
d_i_4_0_sel_rd <= not(d_i_4_0_sel_rd);
end if;
end if;
end if;
end process;
d_i_4_0_sel_wr_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
d_i_4_0_sel_wr <= ap_const_logic_0;
else
if (((ap_const_logic_1 = d_i_4_0_vld_in) and (ap_const_logic_1 = d_i_4_0_ack_in))) then
d_i_4_0_sel_wr <= not(d_i_4_0_sel_wr);
end if;
end if;
end if;
end process;
d_i_4_0_state_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
d_i_4_0_state <= ap_const_lv2_0;
else
if ((((ap_const_logic_0 = d_i_4_0_vld_in) and (ap_const_logic_1 = d_i_4_0_ack_out) and (ap_const_lv2_3 = d_i_4_0_state)) or ((ap_const_logic_0 = d_i_4_0_vld_in) and (ap_const_lv2_2 = d_i_4_0_state)))) then
d_i_4_0_state <= ap_const_lv2_2;
elsif ((((ap_const_logic_1 = d_i_4_0_vld_in) and (ap_const_logic_0 = d_i_4_0_ack_out) and (ap_const_lv2_3 = d_i_4_0_state)) or ((ap_const_logic_0 = d_i_4_0_ack_out) and (ap_const_lv2_1 = d_i_4_0_state)))) then
d_i_4_0_state <= ap_const_lv2_1;
elsif ((((ap_const_logic_1 = d_i_4_0_vld_in) and (ap_const_lv2_2 = d_i_4_0_state)) or ((ap_const_logic_1 = d_i_4_0_ack_out) and (ap_const_lv2_1 = d_i_4_0_state)) or ((ap_const_lv2_3 = d_i_4_0_state) and not(((ap_const_logic_1 = d_i_4_0_vld_in) and (ap_const_logic_0 = d_i_4_0_ack_out))) and not(((ap_const_logic_0 = d_i_4_0_vld_in) and (ap_const_logic_1 = d_i_4_0_ack_out)))))) then
d_i_4_0_state <= ap_const_lv2_3;
else
d_i_4_0_state <= ap_const_lv2_2;
end if;
end if;
end if;
end process;
d_i_5_0_sel_rd_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
d_i_5_0_sel_rd <= ap_const_logic_0;
else
if (((ap_const_logic_1 = d_i_5_0_ack_out) and (ap_const_logic_1 = d_i_5_0_vld_out))) then
d_i_5_0_sel_rd <= not(d_i_5_0_sel_rd);
end if;
end if;
end if;
end process;
d_i_5_0_sel_wr_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
d_i_5_0_sel_wr <= ap_const_logic_0;
else
if (((ap_const_logic_1 = d_i_5_0_vld_in) and (ap_const_logic_1 = d_i_5_0_ack_in))) then
d_i_5_0_sel_wr <= not(d_i_5_0_sel_wr);
end if;
end if;
end if;
end process;
d_i_5_0_state_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
d_i_5_0_state <= ap_const_lv2_0;
else
if ((((ap_const_logic_0 = d_i_5_0_vld_in) and (ap_const_logic_1 = d_i_5_0_ack_out) and (ap_const_lv2_3 = d_i_5_0_state)) or ((ap_const_logic_0 = d_i_5_0_vld_in) and (ap_const_lv2_2 = d_i_5_0_state)))) then
d_i_5_0_state <= ap_const_lv2_2;
elsif ((((ap_const_logic_1 = d_i_5_0_vld_in) and (ap_const_logic_0 = d_i_5_0_ack_out) and (ap_const_lv2_3 = d_i_5_0_state)) or ((ap_const_logic_0 = d_i_5_0_ack_out) and (ap_const_lv2_1 = d_i_5_0_state)))) then
d_i_5_0_state <= ap_const_lv2_1;
elsif ((((ap_const_logic_1 = d_i_5_0_vld_in) and (ap_const_lv2_2 = d_i_5_0_state)) or ((ap_const_logic_1 = d_i_5_0_ack_out) and (ap_const_lv2_1 = d_i_5_0_state)) or ((ap_const_lv2_3 = d_i_5_0_state) and not(((ap_const_logic_1 = d_i_5_0_vld_in) and (ap_const_logic_0 = d_i_5_0_ack_out))) and not(((ap_const_logic_0 = d_i_5_0_vld_in) and (ap_const_logic_1 = d_i_5_0_ack_out)))))) then
d_i_5_0_state <= ap_const_lv2_3;
else
d_i_5_0_state <= ap_const_lv2_2;
end if;
end if;
end if;
end process;
d_i_6_0_sel_rd_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
d_i_6_0_sel_rd <= ap_const_logic_0;
else
if (((ap_const_logic_1 = d_i_6_0_ack_out) and (ap_const_logic_1 = d_i_6_0_vld_out))) then
d_i_6_0_sel_rd <= not(d_i_6_0_sel_rd);
end if;
end if;
end if;
end process;
d_i_6_0_sel_wr_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
d_i_6_0_sel_wr <= ap_const_logic_0;
else
if (((ap_const_logic_1 = d_i_6_0_vld_in) and (ap_const_logic_1 = d_i_6_0_ack_in))) then
d_i_6_0_sel_wr <= not(d_i_6_0_sel_wr);
end if;
end if;
end if;
end process;
d_i_6_0_state_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
d_i_6_0_state <= ap_const_lv2_0;
else
if ((((ap_const_logic_0 = d_i_6_0_vld_in) and (ap_const_logic_1 = d_i_6_0_ack_out) and (ap_const_lv2_3 = d_i_6_0_state)) or ((ap_const_logic_0 = d_i_6_0_vld_in) and (ap_const_lv2_2 = d_i_6_0_state)))) then
d_i_6_0_state <= ap_const_lv2_2;
elsif ((((ap_const_logic_1 = d_i_6_0_vld_in) and (ap_const_logic_0 = d_i_6_0_ack_out) and (ap_const_lv2_3 = d_i_6_0_state)) or ((ap_const_logic_0 = d_i_6_0_ack_out) and (ap_const_lv2_1 = d_i_6_0_state)))) then
d_i_6_0_state <= ap_const_lv2_1;
elsif ((((ap_const_logic_1 = d_i_6_0_vld_in) and (ap_const_lv2_2 = d_i_6_0_state)) or ((ap_const_logic_1 = d_i_6_0_ack_out) and (ap_const_lv2_1 = d_i_6_0_state)) or ((ap_const_lv2_3 = d_i_6_0_state) and not(((ap_const_logic_1 = d_i_6_0_vld_in) and (ap_const_logic_0 = d_i_6_0_ack_out))) and not(((ap_const_logic_0 = d_i_6_0_vld_in) and (ap_const_logic_1 = d_i_6_0_ack_out)))))) then
d_i_6_0_state <= ap_const_lv2_3;
else
d_i_6_0_state <= ap_const_lv2_2;
end if;
end if;
end if;
end process;
d_i_7_0_sel_rd_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
d_i_7_0_sel_rd <= ap_const_logic_0;
else
if (((ap_const_logic_1 = d_i_7_0_ack_out) and (ap_const_logic_1 = d_i_7_0_vld_out))) then
d_i_7_0_sel_rd <= not(d_i_7_0_sel_rd);
end if;
end if;
end if;
end process;
d_i_7_0_sel_wr_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
d_i_7_0_sel_wr <= ap_const_logic_0;
else
if (((ap_const_logic_1 = d_i_7_0_vld_in) and (ap_const_logic_1 = d_i_7_0_ack_in))) then
d_i_7_0_sel_wr <= not(d_i_7_0_sel_wr);
end if;
end if;
end if;
end process;
d_i_7_0_state_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
d_i_7_0_state <= ap_const_lv2_0;
else
if ((((ap_const_logic_0 = d_i_7_0_vld_in) and (ap_const_logic_1 = d_i_7_0_ack_out) and (ap_const_lv2_3 = d_i_7_0_state)) or ((ap_const_logic_0 = d_i_7_0_vld_in) and (ap_const_lv2_2 = d_i_7_0_state)))) then
d_i_7_0_state <= ap_const_lv2_2;
elsif ((((ap_const_logic_1 = d_i_7_0_vld_in) and (ap_const_logic_0 = d_i_7_0_ack_out) and (ap_const_lv2_3 = d_i_7_0_state)) or ((ap_const_logic_0 = d_i_7_0_ack_out) and (ap_const_lv2_1 = d_i_7_0_state)))) then
d_i_7_0_state <= ap_const_lv2_1;
elsif ((((ap_const_logic_1 = d_i_7_0_vld_in) and (ap_const_lv2_2 = d_i_7_0_state)) or ((ap_const_logic_1 = d_i_7_0_ack_out) and (ap_const_lv2_1 = d_i_7_0_state)) or ((ap_const_lv2_3 = d_i_7_0_state) and not(((ap_const_logic_1 = d_i_7_0_vld_in) and (ap_const_logic_0 = d_i_7_0_ack_out))) and not(((ap_const_logic_0 = d_i_7_0_vld_in) and (ap_const_logic_1 = d_i_7_0_ack_out)))))) then
d_i_7_0_state <= ap_const_lv2_3;
else
d_i_7_0_state <= ap_const_lv2_2;
end if;
end if;
end if;
end process;
d_o_0_1_sel_rd_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
d_o_0_1_sel_rd <= ap_const_logic_0;
else
if (((ap_const_logic_1 = d_o_0_1_ack_out) and (ap_const_logic_1 = d_o_0_1_vld_out))) then
d_o_0_1_sel_rd <= not(d_o_0_1_sel_rd);
end if;
end if;
end if;
end process;
d_o_0_1_sel_wr_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
d_o_0_1_sel_wr <= ap_const_logic_0;
else
if (((ap_const_logic_1 = d_o_0_1_vld_in) and (ap_const_logic_1 = d_o_0_1_ack_in))) then
d_o_0_1_sel_wr <= not(d_o_0_1_sel_wr);
end if;
end if;
end if;
end process;
d_o_0_1_state_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
d_o_0_1_state <= ap_const_lv2_0;
else
if ((((ap_const_logic_0 = d_o_0_1_vld_in) and (ap_const_logic_1 = d_o_0_1_ack_out) and (d_o_0_1_state = ap_const_lv2_3)) or ((ap_const_logic_0 = d_o_0_1_vld_in) and (d_o_0_1_state = ap_const_lv2_2)))) then
d_o_0_1_state <= ap_const_lv2_2;
elsif ((((ap_const_logic_1 = d_o_0_1_vld_in) and (ap_const_logic_0 = d_o_0_1_ack_out) and (d_o_0_1_state = ap_const_lv2_3)) or ((ap_const_logic_0 = d_o_0_1_ack_out) and (d_o_0_1_state = ap_const_lv2_1)))) then
d_o_0_1_state <= ap_const_lv2_1;
elsif ((((ap_const_logic_1 = d_o_0_1_vld_in) and (d_o_0_1_state = ap_const_lv2_2)) or ((ap_const_logic_1 = d_o_0_1_ack_out) and (d_o_0_1_state = ap_const_lv2_1)) or ((d_o_0_1_state = ap_const_lv2_3) and not(((ap_const_logic_1 = d_o_0_1_vld_in) and (ap_const_logic_0 = d_o_0_1_ack_out))) and not(((ap_const_logic_0 = d_o_0_1_vld_in) and (ap_const_logic_1 = d_o_0_1_ack_out)))))) then
d_o_0_1_state <= ap_const_lv2_3;
else
d_o_0_1_state <= ap_const_lv2_2;
end if;
end if;
end if;
end process;
d_o_1_1_sel_rd_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
d_o_1_1_sel_rd <= ap_const_logic_0;
else
if (((ap_const_logic_1 = d_o_1_1_ack_out) and (ap_const_logic_1 = d_o_1_1_vld_out))) then
d_o_1_1_sel_rd <= not(d_o_1_1_sel_rd);
end if;
end if;
end if;
end process;
d_o_1_1_sel_wr_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
d_o_1_1_sel_wr <= ap_const_logic_0;
else
if (((ap_const_logic_1 = d_o_1_1_vld_in) and (ap_const_logic_1 = d_o_1_1_ack_in))) then
d_o_1_1_sel_wr <= not(d_o_1_1_sel_wr);
end if;
end if;
end if;
end process;
d_o_1_1_state_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
d_o_1_1_state <= ap_const_lv2_0;
else
if ((((ap_const_logic_0 = d_o_1_1_vld_in) and (ap_const_logic_1 = d_o_1_1_ack_out) and (ap_const_lv2_3 = d_o_1_1_state)) or ((ap_const_logic_0 = d_o_1_1_vld_in) and (ap_const_lv2_2 = d_o_1_1_state)))) then
d_o_1_1_state <= ap_const_lv2_2;
elsif ((((ap_const_logic_1 = d_o_1_1_vld_in) and (ap_const_logic_0 = d_o_1_1_ack_out) and (ap_const_lv2_3 = d_o_1_1_state)) or ((ap_const_logic_0 = d_o_1_1_ack_out) and (ap_const_lv2_1 = d_o_1_1_state)))) then
d_o_1_1_state <= ap_const_lv2_1;
elsif ((((ap_const_logic_1 = d_o_1_1_vld_in) and (ap_const_lv2_2 = d_o_1_1_state)) or ((ap_const_logic_1 = d_o_1_1_ack_out) and (ap_const_lv2_1 = d_o_1_1_state)) or ((ap_const_lv2_3 = d_o_1_1_state) and not(((ap_const_logic_1 = d_o_1_1_vld_in) and (ap_const_logic_0 = d_o_1_1_ack_out))) and not(((ap_const_logic_0 = d_o_1_1_vld_in) and (ap_const_logic_1 = d_o_1_1_ack_out)))))) then
d_o_1_1_state <= ap_const_lv2_3;
else
d_o_1_1_state <= ap_const_lv2_2;
end if;
end if;
end if;
end process;
d_o_2_1_sel_rd_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
d_o_2_1_sel_rd <= ap_const_logic_0;
else
if (((ap_const_logic_1 = d_o_2_1_ack_out) and (ap_const_logic_1 = d_o_2_1_vld_out))) then
d_o_2_1_sel_rd <= not(d_o_2_1_sel_rd);
end if;
end if;
end if;
end process;
d_o_2_1_sel_wr_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
d_o_2_1_sel_wr <= ap_const_logic_0;
else
if (((ap_const_logic_1 = d_o_2_1_vld_in) and (ap_const_logic_1 = d_o_2_1_ack_in))) then
d_o_2_1_sel_wr <= not(d_o_2_1_sel_wr);
end if;
end if;
end if;
end process;
d_o_2_1_state_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
d_o_2_1_state <= ap_const_lv2_0;
else
if ((((ap_const_logic_0 = d_o_2_1_vld_in) and (ap_const_logic_1 = d_o_2_1_ack_out) and (ap_const_lv2_3 = d_o_2_1_state)) or ((ap_const_logic_0 = d_o_2_1_vld_in) and (ap_const_lv2_2 = d_o_2_1_state)))) then
d_o_2_1_state <= ap_const_lv2_2;
elsif ((((ap_const_logic_1 = d_o_2_1_vld_in) and (ap_const_logic_0 = d_o_2_1_ack_out) and (ap_const_lv2_3 = d_o_2_1_state)) or ((ap_const_logic_0 = d_o_2_1_ack_out) and (ap_const_lv2_1 = d_o_2_1_state)))) then
d_o_2_1_state <= ap_const_lv2_1;
elsif ((((ap_const_logic_1 = d_o_2_1_vld_in) and (ap_const_lv2_2 = d_o_2_1_state)) or ((ap_const_logic_1 = d_o_2_1_ack_out) and (ap_const_lv2_1 = d_o_2_1_state)) or ((ap_const_lv2_3 = d_o_2_1_state) and not(((ap_const_logic_1 = d_o_2_1_vld_in) and (ap_const_logic_0 = d_o_2_1_ack_out))) and not(((ap_const_logic_0 = d_o_2_1_vld_in) and (ap_const_logic_1 = d_o_2_1_ack_out)))))) then
d_o_2_1_state <= ap_const_lv2_3;
else
d_o_2_1_state <= ap_const_lv2_2;
end if;
end if;
end if;
end process;
d_o_3_1_sel_rd_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
d_o_3_1_sel_rd <= ap_const_logic_0;
else
if (((ap_const_logic_1 = d_o_3_1_ack_out) and (ap_const_logic_1 = d_o_3_1_vld_out))) then
d_o_3_1_sel_rd <= not(d_o_3_1_sel_rd);
end if;
end if;
end if;
end process;
d_o_3_1_sel_wr_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
d_o_3_1_sel_wr <= ap_const_logic_0;
else
if (((ap_const_logic_1 = d_o_3_1_vld_in) and (ap_const_logic_1 = d_o_3_1_ack_in))) then
d_o_3_1_sel_wr <= not(d_o_3_1_sel_wr);
end if;
end if;
end if;
end process;
d_o_3_1_state_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
d_o_3_1_state <= ap_const_lv2_0;
else
if ((((ap_const_logic_0 = d_o_3_1_vld_in) and (ap_const_logic_1 = d_o_3_1_ack_out) and (ap_const_lv2_3 = d_o_3_1_state)) or ((ap_const_logic_0 = d_o_3_1_vld_in) and (ap_const_lv2_2 = d_o_3_1_state)))) then
d_o_3_1_state <= ap_const_lv2_2;
elsif ((((ap_const_logic_1 = d_o_3_1_vld_in) and (ap_const_logic_0 = d_o_3_1_ack_out) and (ap_const_lv2_3 = d_o_3_1_state)) or ((ap_const_logic_0 = d_o_3_1_ack_out) and (ap_const_lv2_1 = d_o_3_1_state)))) then
d_o_3_1_state <= ap_const_lv2_1;
elsif ((((ap_const_logic_1 = d_o_3_1_vld_in) and (ap_const_lv2_2 = d_o_3_1_state)) or ((ap_const_logic_1 = d_o_3_1_ack_out) and (ap_const_lv2_1 = d_o_3_1_state)) or ((ap_const_lv2_3 = d_o_3_1_state) and not(((ap_const_logic_1 = d_o_3_1_vld_in) and (ap_const_logic_0 = d_o_3_1_ack_out))) and not(((ap_const_logic_0 = d_o_3_1_vld_in) and (ap_const_logic_1 = d_o_3_1_ack_out)))))) then
d_o_3_1_state <= ap_const_lv2_3;
else
d_o_3_1_state <= ap_const_lv2_2;
end if;
end if;
end if;
end process;
d_o_4_1_sel_rd_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
d_o_4_1_sel_rd <= ap_const_logic_0;
else
if (((ap_const_logic_1 = d_o_4_1_ack_out) and (ap_const_logic_1 = d_o_4_1_vld_out))) then
d_o_4_1_sel_rd <= not(d_o_4_1_sel_rd);
end if;
end if;
end if;
end process;
d_o_4_1_sel_wr_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
d_o_4_1_sel_wr <= ap_const_logic_0;
else
if (((ap_const_logic_1 = d_o_4_1_vld_in) and (ap_const_logic_1 = d_o_4_1_ack_in))) then
d_o_4_1_sel_wr <= not(d_o_4_1_sel_wr);
end if;
end if;
end if;
end process;
d_o_4_1_state_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
d_o_4_1_state <= ap_const_lv2_0;
else
if ((((ap_const_logic_0 = d_o_4_1_vld_in) and (ap_const_logic_1 = d_o_4_1_ack_out) and (ap_const_lv2_3 = d_o_4_1_state)) or ((ap_const_logic_0 = d_o_4_1_vld_in) and (ap_const_lv2_2 = d_o_4_1_state)))) then
d_o_4_1_state <= ap_const_lv2_2;
elsif ((((ap_const_logic_1 = d_o_4_1_vld_in) and (ap_const_logic_0 = d_o_4_1_ack_out) and (ap_const_lv2_3 = d_o_4_1_state)) or ((ap_const_logic_0 = d_o_4_1_ack_out) and (ap_const_lv2_1 = d_o_4_1_state)))) then
d_o_4_1_state <= ap_const_lv2_1;
elsif ((((ap_const_logic_1 = d_o_4_1_vld_in) and (ap_const_lv2_2 = d_o_4_1_state)) or ((ap_const_logic_1 = d_o_4_1_ack_out) and (ap_const_lv2_1 = d_o_4_1_state)) or ((ap_const_lv2_3 = d_o_4_1_state) and not(((ap_const_logic_1 = d_o_4_1_vld_in) and (ap_const_logic_0 = d_o_4_1_ack_out))) and not(((ap_const_logic_0 = d_o_4_1_vld_in) and (ap_const_logic_1 = d_o_4_1_ack_out)))))) then
d_o_4_1_state <= ap_const_lv2_3;
else
d_o_4_1_state <= ap_const_lv2_2;
end if;
end if;
end if;
end process;
d_o_5_1_sel_rd_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
d_o_5_1_sel_rd <= ap_const_logic_0;
else
if (((ap_const_logic_1 = d_o_5_1_ack_out) and (ap_const_logic_1 = d_o_5_1_vld_out))) then
d_o_5_1_sel_rd <= not(d_o_5_1_sel_rd);
end if;
end if;
end if;
end process;
d_o_5_1_sel_wr_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
d_o_5_1_sel_wr <= ap_const_logic_0;
else
if (((ap_const_logic_1 = d_o_5_1_vld_in) and (ap_const_logic_1 = d_o_5_1_ack_in))) then
d_o_5_1_sel_wr <= not(d_o_5_1_sel_wr);
end if;
end if;
end if;
end process;
d_o_5_1_state_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
d_o_5_1_state <= ap_const_lv2_0;
else
if ((((ap_const_logic_0 = d_o_5_1_vld_in) and (ap_const_logic_1 = d_o_5_1_ack_out) and (ap_const_lv2_3 = d_o_5_1_state)) or ((ap_const_logic_0 = d_o_5_1_vld_in) and (ap_const_lv2_2 = d_o_5_1_state)))) then
d_o_5_1_state <= ap_const_lv2_2;
elsif ((((ap_const_logic_1 = d_o_5_1_vld_in) and (ap_const_logic_0 = d_o_5_1_ack_out) and (ap_const_lv2_3 = d_o_5_1_state)) or ((ap_const_logic_0 = d_o_5_1_ack_out) and (ap_const_lv2_1 = d_o_5_1_state)))) then
d_o_5_1_state <= ap_const_lv2_1;
elsif ((((ap_const_logic_1 = d_o_5_1_vld_in) and (ap_const_lv2_2 = d_o_5_1_state)) or ((ap_const_logic_1 = d_o_5_1_ack_out) and (ap_const_lv2_1 = d_o_5_1_state)) or ((ap_const_lv2_3 = d_o_5_1_state) and not(((ap_const_logic_1 = d_o_5_1_vld_in) and (ap_const_logic_0 = d_o_5_1_ack_out))) and not(((ap_const_logic_0 = d_o_5_1_vld_in) and (ap_const_logic_1 = d_o_5_1_ack_out)))))) then
d_o_5_1_state <= ap_const_lv2_3;
else
d_o_5_1_state <= ap_const_lv2_2;
end if;
end if;
end if;
end process;
d_o_6_1_sel_rd_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
d_o_6_1_sel_rd <= ap_const_logic_0;
else
if (((ap_const_logic_1 = d_o_6_1_ack_out) and (ap_const_logic_1 = d_o_6_1_vld_out))) then
d_o_6_1_sel_rd <= not(d_o_6_1_sel_rd);
end if;
end if;
end if;
end process;
d_o_6_1_sel_wr_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
d_o_6_1_sel_wr <= ap_const_logic_0;
else
if (((ap_const_logic_1 = d_o_6_1_vld_in) and (ap_const_logic_1 = d_o_6_1_ack_in))) then
d_o_6_1_sel_wr <= not(d_o_6_1_sel_wr);
end if;
end if;
end if;
end process;
d_o_6_1_state_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
d_o_6_1_state <= ap_const_lv2_0;
else
if ((((ap_const_logic_0 = d_o_6_1_vld_in) and (ap_const_logic_1 = d_o_6_1_ack_out) and (ap_const_lv2_3 = d_o_6_1_state)) or ((ap_const_logic_0 = d_o_6_1_vld_in) and (ap_const_lv2_2 = d_o_6_1_state)))) then
d_o_6_1_state <= ap_const_lv2_2;
elsif ((((ap_const_logic_1 = d_o_6_1_vld_in) and (ap_const_logic_0 = d_o_6_1_ack_out) and (ap_const_lv2_3 = d_o_6_1_state)) or ((ap_const_logic_0 = d_o_6_1_ack_out) and (ap_const_lv2_1 = d_o_6_1_state)))) then
d_o_6_1_state <= ap_const_lv2_1;
elsif ((((ap_const_logic_1 = d_o_6_1_vld_in) and (ap_const_lv2_2 = d_o_6_1_state)) or ((ap_const_logic_1 = d_o_6_1_ack_out) and (ap_const_lv2_1 = d_o_6_1_state)) or ((ap_const_lv2_3 = d_o_6_1_state) and not(((ap_const_logic_1 = d_o_6_1_vld_in) and (ap_const_logic_0 = d_o_6_1_ack_out))) and not(((ap_const_logic_0 = d_o_6_1_vld_in) and (ap_const_logic_1 = d_o_6_1_ack_out)))))) then
d_o_6_1_state <= ap_const_lv2_3;
else
d_o_6_1_state <= ap_const_lv2_2;
end if;
end if;
end if;
end process;
d_o_7_1_sel_rd_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
d_o_7_1_sel_rd <= ap_const_logic_0;
else
if (((ap_const_logic_1 = d_o_7_1_ack_out) and (ap_const_logic_1 = d_o_7_1_vld_out))) then
d_o_7_1_sel_rd <= not(d_o_7_1_sel_rd);
end if;
end if;
end if;
end process;
d_o_7_1_sel_wr_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
d_o_7_1_sel_wr <= ap_const_logic_0;
else
if (((ap_const_logic_1 = d_o_7_1_vld_in) and (ap_const_logic_1 = d_o_7_1_ack_in))) then
d_o_7_1_sel_wr <= not(d_o_7_1_sel_wr);
end if;
end if;
end if;
end process;
d_o_7_1_state_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
d_o_7_1_state <= ap_const_lv2_0;
else
if ((((ap_const_logic_0 = d_o_7_1_vld_in) and (ap_const_logic_1 = d_o_7_1_ack_out) and (ap_const_lv2_3 = d_o_7_1_state)) or ((ap_const_logic_0 = d_o_7_1_vld_in) and (ap_const_lv2_2 = d_o_7_1_state)))) then
d_o_7_1_state <= ap_const_lv2_2;
elsif ((((ap_const_logic_1 = d_o_7_1_vld_in) and (ap_const_logic_0 = d_o_7_1_ack_out) and (ap_const_lv2_3 = d_o_7_1_state)) or ((ap_const_logic_0 = d_o_7_1_ack_out) and (ap_const_lv2_1 = d_o_7_1_state)))) then
d_o_7_1_state <= ap_const_lv2_1;
elsif ((((ap_const_logic_1 = d_o_7_1_vld_in) and (ap_const_lv2_2 = d_o_7_1_state)) or ((ap_const_logic_1 = d_o_7_1_ack_out) and (ap_const_lv2_1 = d_o_7_1_state)) or ((ap_const_lv2_3 = d_o_7_1_state) and not(((ap_const_logic_1 = d_o_7_1_vld_in) and (ap_const_logic_0 = d_o_7_1_ack_out))) and not(((ap_const_logic_0 = d_o_7_1_vld_in) and (ap_const_logic_1 = d_o_7_1_ack_out)))))) then
d_o_7_1_state <= ap_const_lv2_3;
else
d_o_7_1_state <= ap_const_lv2_2;
end if;
end if;
end if;
end process;
i1_reg_216_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_lv1_0 = exitcond_reg_505))) then
i1_reg_216 <= tmp_17_reg_500;
elsif ((((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_lv1_1 = exitcond_reg_505)))) then
i1_reg_216 <= ap_const_lv5_0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
acc_0 <= tmp_1_fu_264_p2;
acc_1 <= tmp_1_1_fu_295_p2;
acc_2 <= tmp_1_2_fu_326_p2;
acc_3 <= tmp_1_3_fu_357_p2;
acc_4 <= tmp_1_4_fu_388_p2;
acc_5 <= tmp_1_5_fu_419_p2;
acc_6 <= tmp_1_6_fu_450_p2;
acc_7 <= tmp_1_7_fu_481_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
ap_reg_pp0_iter1_exitcond_reg_505 <= exitcond_reg_505;
exitcond_reg_505 <= exitcond_fu_244_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = d_i_0_0_load_A)) then
d_i_0_0_payload_A <= d_i_0_TDATA;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = d_i_0_0_load_B)) then
d_i_0_0_payload_B <= d_i_0_TDATA;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = d_i_1_0_load_A)) then
d_i_1_0_payload_A <= d_i_1_TDATA;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = d_i_1_0_load_B)) then
d_i_1_0_payload_B <= d_i_1_TDATA;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = d_i_2_0_load_A)) then
d_i_2_0_payload_A <= d_i_2_TDATA;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = d_i_2_0_load_B)) then
d_i_2_0_payload_B <= d_i_2_TDATA;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = d_i_3_0_load_A)) then
d_i_3_0_payload_A <= d_i_3_TDATA;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = d_i_3_0_load_B)) then
d_i_3_0_payload_B <= d_i_3_TDATA;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = d_i_4_0_load_A)) then
d_i_4_0_payload_A <= d_i_4_TDATA;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = d_i_4_0_load_B)) then
d_i_4_0_payload_B <= d_i_4_TDATA;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = d_i_5_0_load_A)) then
d_i_5_0_payload_A <= d_i_5_TDATA;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = d_i_5_0_load_B)) then
d_i_5_0_payload_B <= d_i_5_TDATA;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = d_i_6_0_load_A)) then
d_i_6_0_payload_A <= d_i_6_TDATA;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = d_i_6_0_load_B)) then
d_i_6_0_payload_B <= d_i_6_TDATA;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = d_i_7_0_load_A)) then
d_i_7_0_payload_A <= d_i_7_TDATA;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = d_i_7_0_load_B)) then
d_i_7_0_payload_B <= d_i_7_TDATA;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = d_o_0_1_load_A)) then
d_o_0_1_payload_A <= tmp_8_fu_276_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = d_o_0_1_load_B)) then
d_o_0_1_payload_B <= tmp_8_fu_276_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = d_o_1_1_load_A)) then
d_o_1_1_payload_A <= tmp_2_1_fu_307_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = d_o_1_1_load_B)) then
d_o_1_1_payload_B <= tmp_2_1_fu_307_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = d_o_2_1_load_A)) then
d_o_2_1_payload_A <= tmp_2_2_fu_338_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = d_o_2_1_load_B)) then
d_o_2_1_payload_B <= tmp_2_2_fu_338_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = d_o_3_1_load_A)) then
d_o_3_1_payload_A <= tmp_2_3_fu_369_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = d_o_3_1_load_B)) then
d_o_3_1_payload_B <= tmp_2_3_fu_369_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = d_o_4_1_load_A)) then
d_o_4_1_payload_A <= tmp_2_4_fu_400_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = d_o_4_1_load_B)) then
d_o_4_1_payload_B <= tmp_2_4_fu_400_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = d_o_5_1_load_A)) then
d_o_5_1_payload_A <= tmp_2_5_fu_431_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = d_o_5_1_load_B)) then
d_o_5_1_payload_B <= tmp_2_5_fu_431_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = d_o_6_1_load_A)) then
d_o_6_1_payload_A <= tmp_2_6_fu_462_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = d_o_6_1_load_B)) then
d_o_6_1_payload_B <= tmp_2_6_fu_462_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = d_o_7_1_load_A)) then
d_o_7_1_payload_A <= tmp_2_7_fu_493_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = d_o_7_1_load_B)) then
d_o_7_1_payload_B <= tmp_2_7_fu_493_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
tmp_17_reg_500 <= tmp_17_fu_240_p1;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, ap_block_pp0_stage0_flag00011011, ap_reset_idle_pp0)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_pp0_stage0 =>
if ((ap_reset_idle_pp0 = ap_const_logic_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
elsif (((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (ap_const_logic_1 = ap_reset_idle_pp0))) then
ap_NS_fsm <= ap_ST_fsm_state1;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
end if;
when others =>
ap_NS_fsm <= "XX";
end case;
end process;
ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(1);
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_block_pp0_stage0_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage0_flag00001001_assign_proc : process(d_i_0_0_vld_out, d_i_1_0_vld_out, d_i_2_0_vld_out, d_i_3_0_vld_out, d_i_4_0_vld_out, d_i_5_0_vld_out, d_i_6_0_vld_out, d_i_7_0_vld_out, d_o_0_1_ack_in, d_o_1_1_ack_in, d_o_2_1_ack_in, d_o_3_1_ack_in, d_o_4_1_ack_in, d_o_5_1_ack_in, d_o_6_1_ack_in, d_o_7_1_ack_in, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2)
begin
ap_block_pp0_stage0_flag00001001 <= ((((ap_const_logic_0 = d_i_0_0_vld_out) or (ap_const_logic_0 = d_i_1_0_vld_out) or (ap_const_logic_0 = d_i_2_0_vld_out) or (ap_const_logic_0 = d_i_3_0_vld_out) or (ap_const_logic_0 = d_i_4_0_vld_out) or (ap_const_logic_0 = d_i_5_0_vld_out) or (ap_const_logic_0 = d_i_6_0_vld_out) or (ap_const_logic_0 = d_i_7_0_vld_out)) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or (((ap_const_logic_0 = d_o_0_1_ack_in) or (ap_const_logic_0 = d_o_1_1_ack_in) or (ap_const_logic_0 = d_o_2_1_ack_in) or (ap_const_logic_0 = d_o_3_1_ack_in) or (ap_const_logic_0 = d_o_4_1_ack_in) or (ap_const_logic_0 = d_o_5_1_ack_in) or (ap_const_logic_0 = d_o_6_1_ack_in) or (ap_const_logic_0 = d_o_7_1_ack_in)) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2)));
end process;
ap_block_pp0_stage0_flag00011001_assign_proc : process(d_i_0_0_vld_out, d_i_1_0_vld_out, d_i_2_0_vld_out, d_i_3_0_vld_out, d_i_4_0_vld_out, d_i_5_0_vld_out, d_i_6_0_vld_out, d_i_7_0_vld_out, d_o_0_1_ack_in, d_o_1_1_ack_in, d_o_2_1_ack_in, d_o_3_1_ack_in, d_o_4_1_ack_in, d_o_5_1_ack_in, d_o_6_1_ack_in, d_o_7_1_ack_in, ap_block_state4_io, ap_enable_reg_pp0_iter1, ap_block_state3_io, ap_enable_reg_pp0_iter2)
begin
ap_block_pp0_stage0_flag00011001 <= ((((ap_const_logic_0 = d_i_0_0_vld_out) or (ap_const_logic_0 = d_i_1_0_vld_out) or (ap_const_logic_0 = d_i_2_0_vld_out) or (ap_const_logic_0 = d_i_3_0_vld_out) or (ap_const_logic_0 = d_i_4_0_vld_out) or (ap_const_logic_0 = d_i_5_0_vld_out) or (ap_const_logic_0 = d_i_6_0_vld_out) or (ap_const_logic_0 = d_i_7_0_vld_out) or (ap_const_boolean_1 = ap_block_state4_io)) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or (((ap_const_logic_0 = d_o_0_1_ack_in) or (ap_const_logic_0 = d_o_1_1_ack_in) or (ap_const_logic_0 = d_o_2_1_ack_in) or (ap_const_logic_0 = d_o_3_1_ack_in) or (ap_const_logic_0 = d_o_4_1_ack_in) or (ap_const_logic_0 = d_o_5_1_ack_in) or (ap_const_logic_0 = d_o_6_1_ack_in) or (ap_const_logic_0 = d_o_7_1_ack_in) or (ap_const_boolean_1 = ap_block_state3_io)) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2)));
end process;
ap_block_pp0_stage0_flag00011011_assign_proc : process(d_i_0_0_vld_out, d_i_1_0_vld_out, d_i_2_0_vld_out, d_i_3_0_vld_out, d_i_4_0_vld_out, d_i_5_0_vld_out, d_i_6_0_vld_out, d_i_7_0_vld_out, d_o_0_1_ack_in, d_o_1_1_ack_in, d_o_2_1_ack_in, d_o_3_1_ack_in, d_o_4_1_ack_in, d_o_5_1_ack_in, d_o_6_1_ack_in, d_o_7_1_ack_in, ap_block_state4_io, ap_enable_reg_pp0_iter1, ap_block_state3_io, ap_enable_reg_pp0_iter2)
begin
ap_block_pp0_stage0_flag00011011 <= ((((ap_const_logic_0 = d_i_0_0_vld_out) or (ap_const_logic_0 = d_i_1_0_vld_out) or (ap_const_logic_0 = d_i_2_0_vld_out) or (ap_const_logic_0 = d_i_3_0_vld_out) or (ap_const_logic_0 = d_i_4_0_vld_out) or (ap_const_logic_0 = d_i_5_0_vld_out) or (ap_const_logic_0 = d_i_6_0_vld_out) or (ap_const_logic_0 = d_i_7_0_vld_out) or (ap_const_boolean_1 = ap_block_state4_io)) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or (((ap_const_logic_0 = d_o_0_1_ack_in) or (ap_const_logic_0 = d_o_1_1_ack_in) or (ap_const_logic_0 = d_o_2_1_ack_in) or (ap_const_logic_0 = d_o_3_1_ack_in) or (ap_const_logic_0 = d_o_4_1_ack_in) or (ap_const_logic_0 = d_o_5_1_ack_in) or (ap_const_logic_0 = d_o_6_1_ack_in) or (ap_const_logic_0 = d_o_7_1_ack_in) or (ap_const_boolean_1 = ap_block_state3_io)) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2)));
end process;
ap_block_state2_pp0_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state3_io_assign_proc : process(d_o_0_1_ack_in, d_o_1_1_ack_in, d_o_2_1_ack_in, d_o_3_1_ack_in, d_o_4_1_ack_in, d_o_5_1_ack_in, d_o_6_1_ack_in, d_o_7_1_ack_in)
begin
ap_block_state3_io <= ((ap_const_logic_0 = d_o_0_1_ack_in) or (ap_const_logic_0 = d_o_1_1_ack_in) or (ap_const_logic_0 = d_o_2_1_ack_in) or (ap_const_logic_0 = d_o_3_1_ack_in) or (ap_const_logic_0 = d_o_4_1_ack_in) or (ap_const_logic_0 = d_o_5_1_ack_in) or (ap_const_logic_0 = d_o_6_1_ack_in) or (ap_const_logic_0 = d_o_7_1_ack_in));
end process;
ap_block_state3_pp0_stage0_iter2_assign_proc : process(d_o_0_1_ack_in, d_o_1_1_ack_in, d_o_2_1_ack_in, d_o_3_1_ack_in, d_o_4_1_ack_in, d_o_5_1_ack_in, d_o_6_1_ack_in, d_o_7_1_ack_in)
begin
ap_block_state3_pp0_stage0_iter2 <= ((ap_const_logic_0 = d_o_0_1_ack_in) or (ap_const_logic_0 = d_o_1_1_ack_in) or (ap_const_logic_0 = d_o_2_1_ack_in) or (ap_const_logic_0 = d_o_3_1_ack_in) or (ap_const_logic_0 = d_o_4_1_ack_in) or (ap_const_logic_0 = d_o_5_1_ack_in) or (ap_const_logic_0 = d_o_6_1_ack_in) or (ap_const_logic_0 = d_o_7_1_ack_in));
end process;
ap_block_state4_io_assign_proc : process(d_o_0_1_ack_in, d_o_1_1_ack_in, d_o_2_1_ack_in, d_o_3_1_ack_in, d_o_4_1_ack_in, d_o_5_1_ack_in, d_o_6_1_ack_in, d_o_7_1_ack_in)
begin
ap_block_state4_io <= ((ap_const_logic_0 = d_o_0_1_ack_in) or (ap_const_logic_0 = d_o_1_1_ack_in) or (ap_const_logic_0 = d_o_2_1_ack_in) or (ap_const_logic_0 = d_o_3_1_ack_in) or (ap_const_logic_0 = d_o_4_1_ack_in) or (ap_const_logic_0 = d_o_5_1_ack_in) or (ap_const_logic_0 = d_o_6_1_ack_in) or (ap_const_logic_0 = d_o_7_1_ack_in));
end process;
ap_block_state4_pp0_stage0_iter1_assign_proc : process(d_i_0_0_vld_out, d_i_1_0_vld_out, d_i_2_0_vld_out, d_i_3_0_vld_out, d_i_4_0_vld_out, d_i_5_0_vld_out, d_i_6_0_vld_out, d_i_7_0_vld_out)
begin
ap_block_state4_pp0_stage0_iter1 <= ((ap_const_logic_0 = d_i_0_0_vld_out) or (ap_const_logic_0 = d_i_1_0_vld_out) or (ap_const_logic_0 = d_i_2_0_vld_out) or (ap_const_logic_0 = d_i_3_0_vld_out) or (ap_const_logic_0 = d_i_4_0_vld_out) or (ap_const_logic_0 = d_i_5_0_vld_out) or (ap_const_logic_0 = d_i_6_0_vld_out) or (ap_const_logic_0 = d_i_7_0_vld_out));
end process;
ap_condition_1051_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00000000)
begin
ap_condition_1051 <= ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0));
end process;
ap_done_assign_proc : process(ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00011001, ap_reg_pp0_iter1_exitcond_reg_505)
begin
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_lv1_1 = ap_reg_pp0_iter1_exitcond_reg_505))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);
ap_enable_reg_pp0_iter0 <= ap_start;
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2)
begin
if (((ap_const_logic_0 = ap_enable_reg_pp0_iter0) and (ap_const_logic_0 = ap_enable_reg_pp0_iter1) and (ap_const_logic_0 = ap_enable_reg_pp0_iter2))) then
ap_idle_pp0 <= ap_const_logic_1;
else
ap_idle_pp0 <= ap_const_logic_0;
end if;
end process;
ap_idle_pp0_0to1_assign_proc : process(ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter1)
begin
if (((ap_const_logic_0 = ap_enable_reg_pp0_iter0) and (ap_const_logic_0 = ap_enable_reg_pp0_iter1))) then
ap_idle_pp0_0to1 <= ap_const_logic_1;
else
ap_idle_pp0_0to1 <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(exitcond_fu_244_p2, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_block_pp0_stage0_flag00011001)
begin
if (((exitcond_fu_244_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_reset_idle_pp0_assign_proc : process(ap_start, ap_idle_pp0_0to1)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_idle_pp0_0to1))) then
ap_reset_idle_pp0 <= ap_const_logic_1;
else
ap_reset_idle_pp0 <= ap_const_logic_0;
end if;
end process;
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
d_i_0_0_ack_in <= d_i_0_0_state(1);
d_i_0_0_ack_out_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
d_i_0_0_ack_out <= ap_const_logic_1;
else
d_i_0_0_ack_out <= ap_const_logic_0;
end if;
end process;
d_i_0_0_data_out_assign_proc : process(d_i_0_0_payload_A, d_i_0_0_payload_B, d_i_0_0_sel)
begin
if ((ap_const_logic_1 = d_i_0_0_sel)) then
d_i_0_0_data_out <= d_i_0_0_payload_B;
else
d_i_0_0_data_out <= d_i_0_0_payload_A;
end if;
end process;
d_i_0_0_load_A <= (d_i_0_0_state_cmp_full and not(d_i_0_0_sel_wr));
d_i_0_0_load_B <= (d_i_0_0_sel_wr and d_i_0_0_state_cmp_full);
d_i_0_0_sel <= d_i_0_0_sel_rd;
d_i_0_0_state_cmp_full <= '0' when (d_i_0_0_state = ap_const_lv2_1) else '1';
d_i_0_0_vld_in <= d_i_0_TVALID;
d_i_0_0_vld_out <= d_i_0_0_state(0);
d_i_0_TDATA_blk_n_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, d_i_0_0_state, ap_block_pp0_stage0_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
d_i_0_TDATA_blk_n <= d_i_0_0_state(0);
else
d_i_0_TDATA_blk_n <= ap_const_logic_1;
end if;
end process;
d_i_0_TREADY <= d_i_0_0_state(1);
d_i_1_0_ack_in <= d_i_1_0_state(1);
d_i_1_0_ack_out_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
d_i_1_0_ack_out <= ap_const_logic_1;
else
d_i_1_0_ack_out <= ap_const_logic_0;
end if;
end process;
d_i_1_0_data_out_assign_proc : process(d_i_1_0_payload_A, d_i_1_0_payload_B, d_i_1_0_sel)
begin
if ((ap_const_logic_1 = d_i_1_0_sel)) then
d_i_1_0_data_out <= d_i_1_0_payload_B;
else
d_i_1_0_data_out <= d_i_1_0_payload_A;
end if;
end process;
d_i_1_0_load_A <= (d_i_1_0_state_cmp_full and not(d_i_1_0_sel_wr));
d_i_1_0_load_B <= (d_i_1_0_sel_wr and d_i_1_0_state_cmp_full);
d_i_1_0_sel <= d_i_1_0_sel_rd;
d_i_1_0_state_cmp_full <= '0' when (d_i_1_0_state = ap_const_lv2_1) else '1';
d_i_1_0_vld_in <= d_i_1_TVALID;
d_i_1_0_vld_out <= d_i_1_0_state(0);
d_i_1_TDATA_blk_n_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, d_i_1_0_state, ap_block_pp0_stage0_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
d_i_1_TDATA_blk_n <= d_i_1_0_state(0);
else
d_i_1_TDATA_blk_n <= ap_const_logic_1;
end if;
end process;
d_i_1_TREADY <= d_i_1_0_state(1);
d_i_2_0_ack_in <= d_i_2_0_state(1);
d_i_2_0_ack_out_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
d_i_2_0_ack_out <= ap_const_logic_1;
else
d_i_2_0_ack_out <= ap_const_logic_0;
end if;
end process;
d_i_2_0_data_out_assign_proc : process(d_i_2_0_payload_A, d_i_2_0_payload_B, d_i_2_0_sel)
begin
if ((ap_const_logic_1 = d_i_2_0_sel)) then
d_i_2_0_data_out <= d_i_2_0_payload_B;
else
d_i_2_0_data_out <= d_i_2_0_payload_A;
end if;
end process;
d_i_2_0_load_A <= (d_i_2_0_state_cmp_full and not(d_i_2_0_sel_wr));
d_i_2_0_load_B <= (d_i_2_0_sel_wr and d_i_2_0_state_cmp_full);
d_i_2_0_sel <= d_i_2_0_sel_rd;
d_i_2_0_state_cmp_full <= '0' when (d_i_2_0_state = ap_const_lv2_1) else '1';
d_i_2_0_vld_in <= d_i_2_TVALID;
d_i_2_0_vld_out <= d_i_2_0_state(0);
d_i_2_TDATA_blk_n_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, d_i_2_0_state, ap_block_pp0_stage0_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
d_i_2_TDATA_blk_n <= d_i_2_0_state(0);
else
d_i_2_TDATA_blk_n <= ap_const_logic_1;
end if;
end process;
d_i_2_TREADY <= d_i_2_0_state(1);
d_i_3_0_ack_in <= d_i_3_0_state(1);
d_i_3_0_ack_out_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
d_i_3_0_ack_out <= ap_const_logic_1;
else
d_i_3_0_ack_out <= ap_const_logic_0;
end if;
end process;
d_i_3_0_data_out_assign_proc : process(d_i_3_0_payload_A, d_i_3_0_payload_B, d_i_3_0_sel)
begin
if ((ap_const_logic_1 = d_i_3_0_sel)) then
d_i_3_0_data_out <= d_i_3_0_payload_B;
else
d_i_3_0_data_out <= d_i_3_0_payload_A;
end if;
end process;
d_i_3_0_load_A <= (d_i_3_0_state_cmp_full and not(d_i_3_0_sel_wr));
d_i_3_0_load_B <= (d_i_3_0_sel_wr and d_i_3_0_state_cmp_full);
d_i_3_0_sel <= d_i_3_0_sel_rd;
d_i_3_0_state_cmp_full <= '0' when (d_i_3_0_state = ap_const_lv2_1) else '1';
d_i_3_0_vld_in <= d_i_3_TVALID;
d_i_3_0_vld_out <= d_i_3_0_state(0);
d_i_3_TDATA_blk_n_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, d_i_3_0_state, ap_block_pp0_stage0_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
d_i_3_TDATA_blk_n <= d_i_3_0_state(0);
else
d_i_3_TDATA_blk_n <= ap_const_logic_1;
end if;
end process;
d_i_3_TREADY <= d_i_3_0_state(1);
d_i_4_0_ack_in <= d_i_4_0_state(1);
d_i_4_0_ack_out_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
d_i_4_0_ack_out <= ap_const_logic_1;
else
d_i_4_0_ack_out <= ap_const_logic_0;
end if;
end process;
d_i_4_0_data_out_assign_proc : process(d_i_4_0_payload_A, d_i_4_0_payload_B, d_i_4_0_sel)
begin
if ((ap_const_logic_1 = d_i_4_0_sel)) then
d_i_4_0_data_out <= d_i_4_0_payload_B;
else
d_i_4_0_data_out <= d_i_4_0_payload_A;
end if;
end process;
d_i_4_0_load_A <= (d_i_4_0_state_cmp_full and not(d_i_4_0_sel_wr));
d_i_4_0_load_B <= (d_i_4_0_sel_wr and d_i_4_0_state_cmp_full);
d_i_4_0_sel <= d_i_4_0_sel_rd;
d_i_4_0_state_cmp_full <= '0' when (d_i_4_0_state = ap_const_lv2_1) else '1';
d_i_4_0_vld_in <= d_i_4_TVALID;
d_i_4_0_vld_out <= d_i_4_0_state(0);
d_i_4_TDATA_blk_n_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, d_i_4_0_state, ap_block_pp0_stage0_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
d_i_4_TDATA_blk_n <= d_i_4_0_state(0);
else
d_i_4_TDATA_blk_n <= ap_const_logic_1;
end if;
end process;
d_i_4_TREADY <= d_i_4_0_state(1);
d_i_5_0_ack_in <= d_i_5_0_state(1);
d_i_5_0_ack_out_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
d_i_5_0_ack_out <= ap_const_logic_1;
else
d_i_5_0_ack_out <= ap_const_logic_0;
end if;
end process;
d_i_5_0_data_out_assign_proc : process(d_i_5_0_payload_A, d_i_5_0_payload_B, d_i_5_0_sel)
begin
if ((ap_const_logic_1 = d_i_5_0_sel)) then
d_i_5_0_data_out <= d_i_5_0_payload_B;
else
d_i_5_0_data_out <= d_i_5_0_payload_A;
end if;
end process;
d_i_5_0_load_A <= (d_i_5_0_state_cmp_full and not(d_i_5_0_sel_wr));
d_i_5_0_load_B <= (d_i_5_0_sel_wr and d_i_5_0_state_cmp_full);
d_i_5_0_sel <= d_i_5_0_sel_rd;
d_i_5_0_state_cmp_full <= '0' when (d_i_5_0_state = ap_const_lv2_1) else '1';
d_i_5_0_vld_in <= d_i_5_TVALID;
d_i_5_0_vld_out <= d_i_5_0_state(0);
d_i_5_TDATA_blk_n_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, d_i_5_0_state, ap_block_pp0_stage0_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
d_i_5_TDATA_blk_n <= d_i_5_0_state(0);
else
d_i_5_TDATA_blk_n <= ap_const_logic_1;
end if;
end process;
d_i_5_TREADY <= d_i_5_0_state(1);
d_i_6_0_ack_in <= d_i_6_0_state(1);
d_i_6_0_ack_out_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
d_i_6_0_ack_out <= ap_const_logic_1;
else
d_i_6_0_ack_out <= ap_const_logic_0;
end if;
end process;
d_i_6_0_data_out_assign_proc : process(d_i_6_0_payload_A, d_i_6_0_payload_B, d_i_6_0_sel)
begin
if ((ap_const_logic_1 = d_i_6_0_sel)) then
d_i_6_0_data_out <= d_i_6_0_payload_B;
else
d_i_6_0_data_out <= d_i_6_0_payload_A;
end if;
end process;
d_i_6_0_load_A <= (d_i_6_0_state_cmp_full and not(d_i_6_0_sel_wr));
d_i_6_0_load_B <= (d_i_6_0_sel_wr and d_i_6_0_state_cmp_full);
d_i_6_0_sel <= d_i_6_0_sel_rd;
d_i_6_0_state_cmp_full <= '0' when (d_i_6_0_state = ap_const_lv2_1) else '1';
d_i_6_0_vld_in <= d_i_6_TVALID;
d_i_6_0_vld_out <= d_i_6_0_state(0);
d_i_6_TDATA_blk_n_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, d_i_6_0_state, ap_block_pp0_stage0_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
d_i_6_TDATA_blk_n <= d_i_6_0_state(0);
else
d_i_6_TDATA_blk_n <= ap_const_logic_1;
end if;
end process;
d_i_6_TREADY <= d_i_6_0_state(1);
d_i_7_0_ack_in <= d_i_7_0_state(1);
d_i_7_0_ack_out_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
d_i_7_0_ack_out <= ap_const_logic_1;
else
d_i_7_0_ack_out <= ap_const_logic_0;
end if;
end process;
d_i_7_0_data_out_assign_proc : process(d_i_7_0_payload_A, d_i_7_0_payload_B, d_i_7_0_sel)
begin
if ((ap_const_logic_1 = d_i_7_0_sel)) then
d_i_7_0_data_out <= d_i_7_0_payload_B;
else
d_i_7_0_data_out <= d_i_7_0_payload_A;
end if;
end process;
d_i_7_0_load_A <= (d_i_7_0_state_cmp_full and not(d_i_7_0_sel_wr));
d_i_7_0_load_B <= (d_i_7_0_sel_wr and d_i_7_0_state_cmp_full);
d_i_7_0_sel <= d_i_7_0_sel_rd;
d_i_7_0_state_cmp_full <= '0' when (d_i_7_0_state = ap_const_lv2_1) else '1';
d_i_7_0_vld_in <= d_i_7_TVALID;
d_i_7_0_vld_out <= d_i_7_0_state(0);
d_i_7_TDATA_blk_n_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, d_i_7_0_state, ap_block_pp0_stage0_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
d_i_7_TDATA_blk_n <= d_i_7_0_state(0);
else
d_i_7_TDATA_blk_n <= ap_const_logic_1;
end if;
end process;
d_i_7_TREADY <= d_i_7_0_state(1);
d_o_0_1_ack_in <= d_o_0_1_state(1);
d_o_0_1_ack_out <= d_o_0_TREADY;
d_o_0_1_data_out_assign_proc : process(d_o_0_1_payload_A, d_o_0_1_payload_B, d_o_0_1_sel)
begin
if ((ap_const_logic_1 = d_o_0_1_sel)) then
d_o_0_1_data_out <= d_o_0_1_payload_B;
else
d_o_0_1_data_out <= d_o_0_1_payload_A;
end if;
end process;
d_o_0_1_load_A <= (d_o_0_1_state_cmp_full and not(d_o_0_1_sel_wr));
d_o_0_1_load_B <= (d_o_0_1_sel_wr and d_o_0_1_state_cmp_full);
d_o_0_1_sel <= d_o_0_1_sel_rd;
d_o_0_1_state_cmp_full <= '0' when (d_o_0_1_state = ap_const_lv2_1) else '1';
d_o_0_1_vld_in_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
d_o_0_1_vld_in <= ap_const_logic_1;
else
d_o_0_1_vld_in <= ap_const_logic_0;
end if;
end process;
d_o_0_1_vld_out <= d_o_0_1_state(0);
d_o_0_TDATA <= d_o_0_1_data_out;
d_o_0_TDATA_blk_n_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2, d_o_0_1_state, ap_block_pp0_stage0_flag00000000)
begin
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0)))) then
d_o_0_TDATA_blk_n <= d_o_0_1_state(1);
else
d_o_0_TDATA_blk_n <= ap_const_logic_1;
end if;
end process;
d_o_0_TVALID <= d_o_0_1_state(0);
d_o_1_1_ack_in <= d_o_1_1_state(1);
d_o_1_1_ack_out <= d_o_1_TREADY;
d_o_1_1_data_out_assign_proc : process(d_o_1_1_payload_A, d_o_1_1_payload_B, d_o_1_1_sel)
begin
if ((ap_const_logic_1 = d_o_1_1_sel)) then
d_o_1_1_data_out <= d_o_1_1_payload_B;
else
d_o_1_1_data_out <= d_o_1_1_payload_A;
end if;
end process;
d_o_1_1_load_A <= (d_o_1_1_state_cmp_full and not(d_o_1_1_sel_wr));
d_o_1_1_load_B <= (d_o_1_1_sel_wr and d_o_1_1_state_cmp_full);
d_o_1_1_sel <= d_o_1_1_sel_rd;
d_o_1_1_state_cmp_full <= '0' when (d_o_1_1_state = ap_const_lv2_1) else '1';
d_o_1_1_vld_in_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
d_o_1_1_vld_in <= ap_const_logic_1;
else
d_o_1_1_vld_in <= ap_const_logic_0;
end if;
end process;
d_o_1_1_vld_out <= d_o_1_1_state(0);
d_o_1_TDATA <= d_o_1_1_data_out;
d_o_1_TDATA_blk_n_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2, d_o_1_1_state, ap_block_pp0_stage0_flag00000000)
begin
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0)))) then
d_o_1_TDATA_blk_n <= d_o_1_1_state(1);
else
d_o_1_TDATA_blk_n <= ap_const_logic_1;
end if;
end process;
d_o_1_TVALID <= d_o_1_1_state(0);
d_o_2_1_ack_in <= d_o_2_1_state(1);
d_o_2_1_ack_out <= d_o_2_TREADY;
d_o_2_1_data_out_assign_proc : process(d_o_2_1_payload_A, d_o_2_1_payload_B, d_o_2_1_sel)
begin
if ((ap_const_logic_1 = d_o_2_1_sel)) then
d_o_2_1_data_out <= d_o_2_1_payload_B;
else
d_o_2_1_data_out <= d_o_2_1_payload_A;
end if;
end process;
d_o_2_1_load_A <= (d_o_2_1_state_cmp_full and not(d_o_2_1_sel_wr));
d_o_2_1_load_B <= (d_o_2_1_sel_wr and d_o_2_1_state_cmp_full);
d_o_2_1_sel <= d_o_2_1_sel_rd;
d_o_2_1_state_cmp_full <= '0' when (d_o_2_1_state = ap_const_lv2_1) else '1';
d_o_2_1_vld_in_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
d_o_2_1_vld_in <= ap_const_logic_1;
else
d_o_2_1_vld_in <= ap_const_logic_0;
end if;
end process;
d_o_2_1_vld_out <= d_o_2_1_state(0);
d_o_2_TDATA <= d_o_2_1_data_out;
d_o_2_TDATA_blk_n_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2, d_o_2_1_state, ap_block_pp0_stage0_flag00000000)
begin
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0)))) then
d_o_2_TDATA_blk_n <= d_o_2_1_state(1);
else
d_o_2_TDATA_blk_n <= ap_const_logic_1;
end if;
end process;
d_o_2_TVALID <= d_o_2_1_state(0);
d_o_3_1_ack_in <= d_o_3_1_state(1);
d_o_3_1_ack_out <= d_o_3_TREADY;
d_o_3_1_data_out_assign_proc : process(d_o_3_1_payload_A, d_o_3_1_payload_B, d_o_3_1_sel)
begin
if ((ap_const_logic_1 = d_o_3_1_sel)) then
d_o_3_1_data_out <= d_o_3_1_payload_B;
else
d_o_3_1_data_out <= d_o_3_1_payload_A;
end if;
end process;
d_o_3_1_load_A <= (d_o_3_1_state_cmp_full and not(d_o_3_1_sel_wr));
d_o_3_1_load_B <= (d_o_3_1_sel_wr and d_o_3_1_state_cmp_full);
d_o_3_1_sel <= d_o_3_1_sel_rd;
d_o_3_1_state_cmp_full <= '0' when (d_o_3_1_state = ap_const_lv2_1) else '1';
d_o_3_1_vld_in_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
d_o_3_1_vld_in <= ap_const_logic_1;
else
d_o_3_1_vld_in <= ap_const_logic_0;
end if;
end process;
d_o_3_1_vld_out <= d_o_3_1_state(0);
d_o_3_TDATA <= d_o_3_1_data_out;
d_o_3_TDATA_blk_n_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2, d_o_3_1_state, ap_block_pp0_stage0_flag00000000)
begin
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0)))) then
d_o_3_TDATA_blk_n <= d_o_3_1_state(1);
else
d_o_3_TDATA_blk_n <= ap_const_logic_1;
end if;
end process;
d_o_3_TVALID <= d_o_3_1_state(0);
d_o_4_1_ack_in <= d_o_4_1_state(1);
d_o_4_1_ack_out <= d_o_4_TREADY;
d_o_4_1_data_out_assign_proc : process(d_o_4_1_payload_A, d_o_4_1_payload_B, d_o_4_1_sel)
begin
if ((ap_const_logic_1 = d_o_4_1_sel)) then
d_o_4_1_data_out <= d_o_4_1_payload_B;
else
d_o_4_1_data_out <= d_o_4_1_payload_A;
end if;
end process;
d_o_4_1_load_A <= (d_o_4_1_state_cmp_full and not(d_o_4_1_sel_wr));
d_o_4_1_load_B <= (d_o_4_1_sel_wr and d_o_4_1_state_cmp_full);
d_o_4_1_sel <= d_o_4_1_sel_rd;
d_o_4_1_state_cmp_full <= '0' when (d_o_4_1_state = ap_const_lv2_1) else '1';
d_o_4_1_vld_in_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
d_o_4_1_vld_in <= ap_const_logic_1;
else
d_o_4_1_vld_in <= ap_const_logic_0;
end if;
end process;
d_o_4_1_vld_out <= d_o_4_1_state(0);
d_o_4_TDATA <= d_o_4_1_data_out;
d_o_4_TDATA_blk_n_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2, d_o_4_1_state, ap_block_pp0_stage0_flag00000000)
begin
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0)))) then
d_o_4_TDATA_blk_n <= d_o_4_1_state(1);
else
d_o_4_TDATA_blk_n <= ap_const_logic_1;
end if;
end process;
d_o_4_TVALID <= d_o_4_1_state(0);
d_o_5_1_ack_in <= d_o_5_1_state(1);
d_o_5_1_ack_out <= d_o_5_TREADY;
d_o_5_1_data_out_assign_proc : process(d_o_5_1_payload_A, d_o_5_1_payload_B, d_o_5_1_sel)
begin
if ((ap_const_logic_1 = d_o_5_1_sel)) then
d_o_5_1_data_out <= d_o_5_1_payload_B;
else
d_o_5_1_data_out <= d_o_5_1_payload_A;
end if;
end process;
d_o_5_1_load_A <= (d_o_5_1_state_cmp_full and not(d_o_5_1_sel_wr));
d_o_5_1_load_B <= (d_o_5_1_sel_wr and d_o_5_1_state_cmp_full);
d_o_5_1_sel <= d_o_5_1_sel_rd;
d_o_5_1_state_cmp_full <= '0' when (d_o_5_1_state = ap_const_lv2_1) else '1';
d_o_5_1_vld_in_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
d_o_5_1_vld_in <= ap_const_logic_1;
else
d_o_5_1_vld_in <= ap_const_logic_0;
end if;
end process;
d_o_5_1_vld_out <= d_o_5_1_state(0);
d_o_5_TDATA <= d_o_5_1_data_out;
d_o_5_TDATA_blk_n_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2, d_o_5_1_state, ap_block_pp0_stage0_flag00000000)
begin
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0)))) then
d_o_5_TDATA_blk_n <= d_o_5_1_state(1);
else
d_o_5_TDATA_blk_n <= ap_const_logic_1;
end if;
end process;
d_o_5_TVALID <= d_o_5_1_state(0);
d_o_6_1_ack_in <= d_o_6_1_state(1);
d_o_6_1_ack_out <= d_o_6_TREADY;
d_o_6_1_data_out_assign_proc : process(d_o_6_1_payload_A, d_o_6_1_payload_B, d_o_6_1_sel)
begin
if ((ap_const_logic_1 = d_o_6_1_sel)) then
d_o_6_1_data_out <= d_o_6_1_payload_B;
else
d_o_6_1_data_out <= d_o_6_1_payload_A;
end if;
end process;
d_o_6_1_load_A <= (d_o_6_1_state_cmp_full and not(d_o_6_1_sel_wr));
d_o_6_1_load_B <= (d_o_6_1_sel_wr and d_o_6_1_state_cmp_full);
d_o_6_1_sel <= d_o_6_1_sel_rd;
d_o_6_1_state_cmp_full <= '0' when (d_o_6_1_state = ap_const_lv2_1) else '1';
d_o_6_1_vld_in_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
d_o_6_1_vld_in <= ap_const_logic_1;
else
d_o_6_1_vld_in <= ap_const_logic_0;
end if;
end process;
d_o_6_1_vld_out <= d_o_6_1_state(0);
d_o_6_TDATA <= d_o_6_1_data_out;
d_o_6_TDATA_blk_n_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2, d_o_6_1_state, ap_block_pp0_stage0_flag00000000)
begin
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0)))) then
d_o_6_TDATA_blk_n <= d_o_6_1_state(1);
else
d_o_6_TDATA_blk_n <= ap_const_logic_1;
end if;
end process;
d_o_6_TVALID <= d_o_6_1_state(0);
d_o_7_1_ack_in <= d_o_7_1_state(1);
d_o_7_1_ack_out <= d_o_7_TREADY;
d_o_7_1_data_out_assign_proc : process(d_o_7_1_payload_A, d_o_7_1_payload_B, d_o_7_1_sel)
begin
if ((ap_const_logic_1 = d_o_7_1_sel)) then
d_o_7_1_data_out <= d_o_7_1_payload_B;
else
d_o_7_1_data_out <= d_o_7_1_payload_A;
end if;
end process;
d_o_7_1_load_A <= (d_o_7_1_state_cmp_full and not(d_o_7_1_sel_wr));
d_o_7_1_load_B <= (d_o_7_1_sel_wr and d_o_7_1_state_cmp_full);
d_o_7_1_sel <= d_o_7_1_sel_rd;
d_o_7_1_state_cmp_full <= '0' when (d_o_7_1_state = ap_const_lv2_1) else '1';
d_o_7_1_vld_in_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
d_o_7_1_vld_in <= ap_const_logic_1;
else
d_o_7_1_vld_in <= ap_const_logic_0;
end if;
end process;
d_o_7_1_vld_out <= d_o_7_1_state(0);
d_o_7_TDATA <= d_o_7_1_data_out;
d_o_7_TDATA_blk_n_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2, d_o_7_1_state, ap_block_pp0_stage0_flag00000000)
begin
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0)))) then
d_o_7_TDATA_blk_n <= d_o_7_1_state(1);
else
d_o_7_TDATA_blk_n <= ap_const_logic_1;
end if;
end process;
d_o_7_TVALID <= d_o_7_1_state(0);
exitcond_fu_244_p2 <= "1" when (i_1_7_fu_234_p2 = ap_const_lv6_20) else "0";
i1_cast_fu_230_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i1_phi_fu_220_p6),6));
i1_phi_fu_220_p6_assign_proc : process(i1_reg_216, tmp_17_reg_500, exitcond_reg_505, ap_condition_1051)
begin
if ((ap_condition_1051 = ap_const_boolean_1)) then
if ((ap_const_lv1_1 = exitcond_reg_505)) then
i1_phi_fu_220_p6 <= ap_const_lv5_0;
elsif ((ap_const_lv1_0 = exitcond_reg_505)) then
i1_phi_fu_220_p6 <= tmp_17_reg_500;
else
i1_phi_fu_220_p6 <= i1_reg_216;
end if;
else
i1_phi_fu_220_p6 <= i1_reg_216;
end if;
end process;
i_1_7_fu_234_p2 <= std_logic_vector(unsigned(ap_const_lv6_8) + unsigned(i1_cast_fu_230_p1));
tmp1_fu_256_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_0_0_data_out),32));
tmp_10_fu_291_p1 <= acc_1(16 - 1 downto 0);
tmp_11_fu_322_p1 <= acc_2(16 - 1 downto 0);
tmp_12_fu_353_p1 <= acc_3(16 - 1 downto 0);
tmp_13_fu_384_p1 <= acc_4(16 - 1 downto 0);
tmp_14_fu_415_p1 <= acc_5(16 - 1 downto 0);
tmp_15_fu_446_p1 <= acc_6(16 - 1 downto 0);
tmp_16_fu_477_p1 <= acc_7(16 - 1 downto 0);
tmp_17_fu_240_p1 <= i_1_7_fu_234_p2(5 - 1 downto 0);
tmp_1_1_fu_295_p2 <= std_logic_vector(signed(tmp_s_fu_287_p1) + signed(acc_1));
tmp_1_2_fu_326_p2 <= std_logic_vector(signed(tmp_9_fu_318_p1) + signed(acc_2));
tmp_1_3_fu_357_p2 <= std_logic_vector(signed(tmp_3_fu_349_p1) + signed(acc_3));
tmp_1_4_fu_388_p2 <= std_logic_vector(signed(tmp_4_fu_380_p1) + signed(acc_4));
tmp_1_5_fu_419_p2 <= std_logic_vector(signed(tmp_5_fu_411_p1) + signed(acc_5));
tmp_1_6_fu_450_p2 <= std_logic_vector(signed(tmp_6_fu_442_p1) + signed(acc_6));
tmp_1_7_fu_481_p2 <= std_logic_vector(signed(tmp_7_fu_473_p1) + signed(acc_7));
tmp_1_fu_264_p2 <= std_logic_vector(signed(tmp1_fu_256_p1) + signed(acc_0));
tmp_2_1_fu_307_p2 <= std_logic_vector(unsigned(tmp_10_fu_291_p1) + unsigned(d_i_1_0_data_out));
tmp_2_2_fu_338_p2 <= std_logic_vector(unsigned(tmp_11_fu_322_p1) + unsigned(d_i_2_0_data_out));
tmp_2_3_fu_369_p2 <= std_logic_vector(unsigned(tmp_12_fu_353_p1) + unsigned(d_i_3_0_data_out));
tmp_2_4_fu_400_p2 <= std_logic_vector(unsigned(tmp_13_fu_384_p1) + unsigned(d_i_4_0_data_out));
tmp_2_5_fu_431_p2 <= std_logic_vector(unsigned(tmp_14_fu_415_p1) + unsigned(d_i_5_0_data_out));
tmp_2_6_fu_462_p2 <= std_logic_vector(unsigned(tmp_15_fu_446_p1) + unsigned(d_i_6_0_data_out));
tmp_2_7_fu_493_p2 <= std_logic_vector(unsigned(tmp_16_fu_477_p1) + unsigned(d_i_7_0_data_out));
tmp_2_fu_260_p1 <= acc_0(16 - 1 downto 0);
tmp_3_fu_349_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_3_0_data_out),32));
tmp_4_fu_380_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_4_0_data_out),32));
tmp_5_fu_411_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_5_0_data_out),32));
tmp_6_fu_442_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_6_0_data_out),32));
tmp_7_fu_473_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_7_0_data_out),32));
tmp_8_fu_276_p2 <= std_logic_vector(unsigned(tmp_2_fu_260_p1) + unsigned(d_i_0_0_data_out));
tmp_9_fu_318_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_2_0_data_out),32));
tmp_s_fu_287_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_1_0_data_out),32));
end behav;
| mit | 7a958047caee24f5ec6339da2163b807 | 0.529704 | 2.462066 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-xilinx-vc707/ahbram_sim.vhd | 2 | 11,817 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahbram
-- File: ahbram.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Modified: Jan Andersson - Aeroflex Gaisler
-- Description: AHB ram. 0-waitstate read, 0/1-waitstate write.
-- Added Sx-Record read function
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use IEEE.Numeric_Std.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use grlib.stdio.all;
library techmap;
use techmap.gencomp.all;
entity ahbram_sim is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := DEFMEMTECH;
kbytes : integer := 1;
pipe : integer := 0;
maccsz : integer := AHBDW;
fname : string := "ram.dat"
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbram_sim is
constant abits : integer := log2ext(kbytes) + 8 - maccsz/64;
constant dw : integer := maccsz;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBRAM, 0, abits+2+maccsz/64, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
others => zero32);
type reg_type is record
hwrite : std_ulogic;
hready : std_ulogic;
hsel : std_ulogic;
addr : std_logic_vector(abits-1+log2(dw/8) downto 0);
size : std_logic_vector(2 downto 0);
prdata : std_logic_vector((dw-1)*pipe downto 0);
pwrite : std_ulogic;
pready : std_ulogic;
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RES : reg_type :=
(hwrite => '0', hready => '1', hsel => '0', addr => (others => '0'),
size => (others => '0'), prdata => (others => '0'), pwrite => '0',
pready => '1');
signal r, c : reg_type;
signal ramsel : std_logic_vector(dw/8-1 downto 0);
signal write : std_logic_vector(dw/8-1 downto 0);
signal ramaddr : std_logic_vector(abits-1 downto 0);
signal ramdata : std_logic_vector(dw-1 downto 0);
signal hwdata : std_logic_vector(dw-1 downto 0);
type ram_type is array (0 to (2**ramaddr'length)-1) of std_logic_vector(ramdata'range);
signal ram : ram_type;
signal read_address : std_logic_vector(ramaddr'range);
begin
comb : process (ahbsi, r, rst, ramdata)
variable bs : std_logic_vector(dw/8-1 downto 0);
variable v : reg_type;
variable haddr : std_logic_vector(abits-1 downto 0);
variable hrdata : std_logic_vector(dw-1 downto 0);
variable seldata : std_logic_vector(dw-1 downto 0);
variable raddr : std_logic_vector(3 downto 2);
variable adsel : std_logic;
begin
v := r; v.hready := '1'; bs := (others => '0');
v.pready := r.hready;
if pipe=0 then
adsel := r.hwrite or not r.hready;
else
adsel := r.hwrite or r.pwrite;
v.hready := r.hready or not r.pwrite;
end if;
if adsel = '1' then
haddr := r.addr(abits-1+log2(dw/8) downto log2(dw/8));
else
haddr := ahbsi.haddr(abits-1+log2(dw/8) downto log2(dw/8));
bs := (others => '0');
end if;
raddr := (others => '0');
v.pwrite := '0';
if pipe/=0 and (r.hready='1' or r.pwrite='0') then
v.addr := ahbsi.haddr(abits-1+log2(dw/8) downto 0);
end if;
if ahbsi.hready = '1' then
if pipe=0 then
v.addr := ahbsi.haddr(abits-1+log2(dw/8) downto 0);
end if;
v.hsel := ahbsi.hsel(hindex) and ahbsi.htrans(1);
v.size := ahbsi.hsize(2 downto 0);
v.hwrite := ahbsi.hwrite and v.hsel;
if pipe = 1 and v.hsel = '1' and ahbsi.hwrite = '0' and (r.pready='1' or ahbsi.htrans(0)='0') then
v.hready := '0';
v.pwrite := r.hwrite;
end if;
end if;
if r.hwrite = '1' then
case r.size is
when HSIZE_BYTE =>
bs(bs'left-conv_integer(r.addr(log2(dw/16) downto 0))) := '1';
when HSIZE_HWORD =>
for i in 0 to dw/16-1 loop
if i = conv_integer(r.addr(log2(dw/16) downto 1)) then
bs(bs'left-i*2 downto bs'left-i*2-1) := (others => '1');
end if;
end loop; -- i
when HSIZE_WORD =>
if dw = 32 then bs := (others => '1');
else
for i in 0 to dw/32-1 loop
if i = conv_integer(r.addr(log2(dw/8)-1 downto 2)) then
bs(bs'left-i*4 downto bs'left-i*4-3) := (others => '1');
end if;
end loop; -- i
end if;
when HSIZE_DWORD =>
if dw = 32 then null;
elsif dw = 64 then bs := (others => '1');
else
for i in 0 to dw/64-1 loop
if i = conv_integer(r.addr(3)) then
bs(bs'left-i*8 downto bs'left-i*8-7) := (others => '1');
end if;
end loop; -- i
end if;
when HSIZE_4WORD =>
if dw < 128 then null;
elsif dw = 128 then bs := (others => '1');
else
for i in 0 to dw/64-1 loop
if i = conv_integer(r.addr(3)) then
bs(bs'left-i*8 downto bs'left-i*8-7) := (others => '1');
end if;
end loop; -- i
end if;
when others => --HSIZE_8WORD
if dw < 256 then null;
else bs := (others => '1'); end if;
end case;
v.hready := not (v.hsel and not ahbsi.hwrite);
v.hwrite := v.hwrite and v.hready;
end if;
-- Duplicate read data on word basis, unless CORE_ACDM is enabled
if CORE_ACDM = 0 then
if dw = 32 then
seldata := ramdata;
elsif dw = 64 then
if r.size = HSIZE_DWORD then seldata := ramdata; else
if r.addr(2) = '0' then
seldata(dw/2-1 downto 0) := ramdata(dw-1 downto dw/2);
else
seldata(dw/2-1 downto 0) := ramdata(dw/2-1 downto 0);
end if;
seldata(dw-1 downto dw/2) := seldata(dw/2-1 downto 0);
end if;
elsif dw = 128 then
if r.size = HSIZE_4WORD then
seldata := ramdata;
elsif r.size = HSIZE_DWORD then
if r.addr(3) = '0' then seldata(dw/2-1 downto 0) := ramdata(dw-1 downto dw/2);
else seldata(dw/2-1 downto 0) := ramdata(dw/2-1 downto 0); end if;
seldata(dw-1 downto dw/2) := seldata(dw/2-1 downto 0);
else
raddr := r.addr(3 downto 2);
case raddr is
when "00" => seldata(dw/4-1 downto 0) := ramdata(4*dw/4-1 downto 3*dw/4);
when "01" => seldata(dw/4-1 downto 0) := ramdata(3*dw/4-1 downto 2*dw/4);
when "10" => seldata(dw/4-1 downto 0) := ramdata(2*dw/4-1 downto 1*dw/4);
when others => seldata(dw/4-1 downto 0) := ramdata(dw/4-1 downto 0);
end case;
seldata(dw-1 downto dw/4) := seldata(dw/4-1 downto 0) &
seldata(dw/4-1 downto 0) &
seldata(dw/4-1 downto 0);
end if;
else
seldata := ahbselectdata(ramdata, r.addr(4 downto 2), r.size);
end if;
else
seldata := ramdata;
end if;
if pipe = 0 then
v.prdata := (others => '0');
hrdata := seldata;
else
v.prdata := seldata;
hrdata := r.prdata;
end if;
if (not RESET_ALL) and (rst = '0') then
v.hwrite := RES.hwrite; v.hready := RES.hready;
end if;
write <= bs; for i in 0 to dw/8-1 loop ramsel(i) <= v.hsel or r.hwrite; end loop;
ramaddr <= haddr; c <= v;
ahbso.hrdata <= ahbdrivedata(hrdata);
ahbso.hready <= r.hready;
end process;
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
-- Select correct write data
hwdata <= ahbreaddata(ahbsi.hwdata, r.addr(4 downto 2),
conv_std_logic_vector(log2(dw/8), 3));
-- aram : syncrambw generic map (tech, abits, dw, scantest) port map (
-- clk, ramaddr, hwdata, ramdata, ramsel, write, ahbsi.testin);
RamProc: process(clk) is
variable L1 : line;
variable FIRST : boolean := true;
variable ADR : std_logic_vector(19 downto 0);
variable BUF : std_logic_vector(31 downto 0);
variable CH : character;
variable ai : integer := 0;
variable len : integer := 0;
file TCF : text open read_mode is fname;
variable rectype : std_logic_vector(3 downto 0);
variable recaddr : std_logic_vector(31 downto 0);
variable reclen : std_logic_vector(7 downto 0);
variable recdata : std_logic_vector(0 to 16*8-1);
begin
if rising_edge(clk) then
if conv_integer(write) > 0 then
for i in 0 to dw/8-1 loop
if (write(i) = '1') then
ram(to_integer(unsigned(ramaddr)))(i*8+7 downto 0) <= hwdata(i*8+7 downto 0);
end if;
end loop;
end if;
read_address <= ramaddr;
end if;
if (rst = '0') and (FIRST = true) then
ram <= (others => (others => '0'));
L1:= new string'("");
while not endfile(TCF) loop
readline(TCF,L1);
if (L1'length /= 0) then --'
while (not (L1'length=0)) and (L1(L1'left) = ' ') loop
std.textio.read(L1,CH);
end loop;
if L1'length > 0 then --'
read(L1, ch);
if (ch = 'S') or (ch = 's') then
hread(L1, rectype);
hread(L1, reclen);
len := conv_integer(reclen)-1;
recaddr := (others => '0');
case rectype is
when "0001" =>
hread(L1, recaddr(15 downto 0));
when "0010" =>
hread(L1, recaddr(23 downto 0));
when "0011" =>
hread(L1, recaddr);
when others => next;
end case;
hread(L1, recdata);
recaddr(31 downto abits+2) := (others => '0');
ai := conv_integer(recaddr)/4;
for i in 0 to 3 loop
ram(ai+i) <= recdata((i*32) to (i*32+31));
end loop;
if ai = 0 then
ai := 1;
end if;
end if;
end if;
end if;
end loop;
FIRST := false;
end if;
end process RamProc;
ramdata <= ram(to_integer(unsigned(read_address)));
reg : process (clk)
begin
if rising_edge(clk) then
r <= c;
if RESET_ALL and rst = '0' then
r <= RES;
end if;
end if;
end process;
bootmsg : report_version
generic map ("ahbram" & tost(hindex) &
": AHB SRAM Module rev 1, " & tost(kbytes) & " kbytes");
end;
-- pragma translate_on
| gpl-2.0 | 40059039a3d35402b07926ba72a5fd29 | 0.542862 | 3.427204 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/solution1_4/syn/vhdl/convolve_kernel_fcud.vhd | 1 | 3,077 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity convolve_kernel_fcud is
generic (
ID : integer := 2;
NUM_STAGE : integer := 5;
din0_WIDTH : integer := 32;
din1_WIDTH : integer := 32;
dout_WIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of convolve_kernel_fcud is
--------------------- Component ---------------------
component convolve_kernel_ap_fmul_3_max_dsp_32 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(31 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(31 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
convolve_kernel_ap_fmul_3_max_dsp_32_u : component convolve_kernel_ap_fmul_3_max_dsp_32
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= din0_buf1;
b_tvalid <= '1';
b_tdata <= din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
| mit | c7b5bfc0ee345c721876ae0743ef2ac3 | 0.480338 | 3.667461 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/techmap/saed32/memory_saed32.vhd | 1 | 5,531 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: memory_saed32.vhd
-- Author: Fredrik Ringhage - Aeroflex Gaisler AB
-- Description: Memory generators for SAED32
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library saed32;
use saed32.SRAM1RW64x32;
use saed32.SRAM1RW128x48;
use saed32.SRAM1RW128x48;
-- pragma translate_on
entity saed32_syncram is
generic ( abits : integer := 10; dbits : integer := 8);
port (
clk : in std_ulogic;
address : in std_logic_vector(abits -1 downto 0);
datain : in std_logic_vector(dbits -1 downto 0);
dataout : out std_logic_vector(dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end;
architecture rtl of saed32_syncram is
component SRAM1RW64x32 is
port (
A : in std_logic_vector( 5 downto 0 );
CE : in std_logic;
WEB : in std_logic;
OEB : in std_logic;
CSB : in std_logic;
I : in std_logic_vector( 31 downto 0 );
O : out std_logic_vector( 31 downto 0 )
);
end component;
component SRAM1RW128x48 is
port (
A : in std_logic_vector( 6 downto 0 );
CE : in std_logic;
WEB : in std_logic;
OEB : in std_logic;
CSB : in std_logic;
I : in std_logic_vector( 47 downto 0 );
O : out std_logic_vector( 47 downto 0 )
);
end component;
component SRAM1RW1024x8 is
port (
A : in std_logic_vector( 9 downto 0 );
CE : in std_logic;
WEB : in std_logic;
OEB : in std_logic;
CSB : in std_logic;
I : in std_logic_vector( 7 downto 0 );
O : out std_logic_vector( 7 downto 0 )
);
end component;
signal d, q, gnd : std_logic_vector(48 downto 0);
signal a : std_logic_vector(17 downto 0);
signal vcc, csn, wen : std_ulogic;
--constant synopsys_bug : std_logic_vector(31 downto 0) := (others => '0');
begin
csn <= not enable; wen <= not write;
gnd <= (others => '0'); vcc <= '1';
a(17 downto abits) <= (others => '0');
d(48 downto dbits) <= (others => '0');
a(abits -1 downto 0) <= address;
d(dbits -1 downto 0) <= datain(dbits -1 downto 0);
a6 : if (abits <= 6) generate
id0 : SRAM1RW64x32 port map (A => a(5 downto 0), CE => clk, WEB => wen, OEB => gnd(0), CSB => csn, I => d(31 downto 0), O => q(31 downto 0));
end generate;
a7 : if (abits = 7) generate
id0 : SRAM1RW128x48 port map (A => a(6 downto 0), CE => clk, WEB => wen, OEB => gnd(0), CSB => csn, I => d(47 downto 0), O => q(47 downto 0));
end generate;
a10 : if (abits >= 8 and abits <= 10) generate
x : for i in 0 to ((dbits-1)/8) generate
id0 : SRAM1RW1024x8 port map (A => a(9 downto 0), CE => clk, WEB => wen, OEB => gnd(0), CSB => csn, I => d(((i+1)*8)-1 downto i*8), O => q(((i+1)*8)-1 downto i*8));
end generate;
end generate;
dataout <= q(dbits -1 downto 0);
-- pragma translate_off
a_to_high : if (abits > 10) or (dbits > 32) generate
x : process
begin
assert false
report "Unsupported memory size (saed32)"
severity failure;
wait;
end process;
end generate;
-- pragma translate_on
end;
library ieee;
use ieee.std_logic_1164.all;
entity saed32_syncram_dp is
generic ( abits : integer := 6; dbits : integer := 8 );
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end;
architecture rtl of saed32_syncram_dp is
begin
end;
library ieee;
use ieee.std_logic_1164.all;
entity saed32_syncram_2p is
generic ( abits : integer := 8; dbits : integer := 32; sepclk : integer := 0);
port (
rclk : in std_ulogic;
rena : in std_ulogic;
raddr : in std_logic_vector (abits -1 downto 0);
dout : out std_logic_vector (dbits -1 downto 0);
wclk : in std_ulogic;
waddr : in std_logic_vector (abits -1 downto 0);
din : in std_logic_vector (dbits -1 downto 0);
write : in std_ulogic);
end;
architecture rtl of saed32_syncram_2p is
begin
end;
| gpl-2.0 | 6ce91abe124234a89564906f71053e53 | 0.595733 | 3.292262 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/techmap/unisim/ddr_phy_unisim.vhd | 1 | 103,327 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: ddr_phy_unisim.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: DDR PHY for Virtex-2 and Virtex-4
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.DCM;
use unisim.ODDR;
use unisim.FD;
use unisim.IDDR;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
------------------------------------------------------------------
-- Virtex4 DDR PHY -----------------------------------------------
------------------------------------------------------------------
entity virtex4_ddr_phy is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; rskew : integer := 0;
phyiconf : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0);
ck : in std_logic_vector(2 downto 0)
);
end;
architecture rtl of virtex4_ddr_phy is
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
component ODDR
generic
( DDR_CLK_EDGE : string := "OPPOSITE_EDGE";
-- INIT : bit := '0';
SRTYPE : string := "SYNC");
port
(
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
component FD
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic);
end component;
component IDDR
generic ( DDR_CLK_EDGE : string := "SAME_EDGE";
INIT_Q1 : bit := '0';
INIT_Q2 : bit := '0';
SRTYPE : string := "ASYNC");
port
( Q1 : out std_ulogic;
Q2 : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
signal vcc, gnd, dqsn, oe, lockl : std_ulogic;
signal ddr_clk_fb_outr : std_ulogic;
signal ddr_clk_fbl, fbclk : std_ulogic;
signal ddr_rasnr, ddr_casnr, ddr_wenr : std_ulogic;
signal ddr_clkl, ddr_clkbl : std_logic_vector(2 downto 0);
signal ddr_csnr, ddr_ckenr, ckel : std_logic_vector(1 downto 0);
signal clk_0ro, clk_90ro, clk_180ro, clk_270ro : std_ulogic;
signal clk_0r, clk_90r, clk_180r, clk_270r : std_ulogic;
signal clk0r, clk90r, clk180r, clk270r : std_ulogic;
signal locked, vlockl, ddrclkfbl, dllfb : std_ulogic;
signal ddr_dqin : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqout : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqoen : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_adr : std_logic_vector (13 downto 0); -- ddr address
signal ddr_bar : std_logic_vector (1 downto 0); -- ddr address
signal ddr_dmr : std_logic_vector (dbits/8-1 downto 0); -- ddr address
signal ddr_dqsin : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoen : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoutl : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsdel, dqsclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal da : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dqinl : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dllrst : std_logic_vector(0 to 3);
signal dll0rst, dll2rst : std_logic_vector(0 to 3);
signal mlock, mclkfb, mclk, mclkfx, mclk0 : std_ulogic;
signal rclk270b, rclk90b, rclk0b : std_ulogic;
signal rclk270, rclk90, rclk0 : std_ulogic;
constant DDR_FREQ : integer := (MHz * clk_mul) / clk_div;
attribute keep : boolean;
attribute keep of rclk90b : signal is true;
attribute syn_keep : boolean;
attribute syn_keep of rclk90b : signal is true;
attribute syn_preserve : boolean;
attribute syn_preserve of rclk90b : signal is true;
-- To prevent synplify 9.4 to remove any of these registers.
attribute syn_noprune : boolean;
attribute syn_noprune of FD : component is true;
attribute syn_noprune of IDDR : component is true;
attribute syn_noprune of ODDR : component is true;
begin
oe <= not oen;
vcc <= '1'; gnd <= '0';
-- Optional DDR clock multiplication
noclkscale : if clk_mul = clk_div generate
mclk <= clk;
end generate;
clkscale : if clk_mul /= clk_div generate
rstdel : process (clk, rst)
begin
if rst = '0' then dll0rst <= (others => '1');
elsif rising_edge(clk) then
dll0rst <= dll0rst(1 to 3) & '0';
end if;
end process;
bufg0 : BUFG port map (I => mclkfx, O => mclk);
bufg1 : BUFG port map (I => mclk0, O => mclkfb);
dllm : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div)
port map ( CLKIN => clk, CLKFB => mclkfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst(0), CLK0 => mclk0,
LOCKED => mlock, CLKFX => mclkfx );
end generate;
-- DDR clock generation
ddrref_pad : clkpad generic map (tech => virtex4)
port map (ddr_clk_fb, ddrclkfbl);
bufg1 : BUFG port map (I => clk_0ro, O => clk_0r);
-- bufg2 : BUFG port map (I => clk_90ro, O => clk_90r);
clk_90r <= not clk_270r;
-- bufg3 : BUFG port map (I => clk_180ro, O => clk_180r);
clk_180r <= not clk_0r;
bufg4 : BUFG port map (I => clk_270ro, O => clk_270r);
clkout <= clk_270r; clk0r <= clk_270r; clk90r <= clk_0r;
clk180r <= clk_90r; clk270r <= clk_180r;
dllfb <= clk_0r;
dll : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2)
port map ( CLKIN => mclk, CLKFB => dllfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst(0), CLK0 => clk_0ro,
CLK90 => clk_90ro, CLK180 => clk_180ro, CLK270 => clk_270ro,
LOCKED => lockl);
rstdel : process (mclk, rst)
begin
if rst = '0' then dllrst <= (others => '1');
elsif rising_edge(mclk) then
dllrst <= dllrst(1 to 3) & '0';
end if;
end process;
rdel : if rstdelay /= 0 generate
rcnt : process (clk_0r)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk_0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*DDR_FREQ, 16); vlock := '0';
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
-- Generate external DDR clock
fbdclk0r : ODDR port map ( Q => ddr_clk_fb_outr, C => clk90r, CE => vcc,
D1 => vcc, D2 => gnd, R => gnd, S => gnd);
fbclk_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clk_fb_out, ddr_clk_fb_outr);
ddrclkdiffio : if phyiconf = 0 generate
ddrclocks0 : for i in 0 to 2 generate
dclk0r : ODDR port map ( Q => ddr_clkl(i), C => clk90r, CE => vcc,
D1 => vcc, D2 => gnd, R => gnd, S => gnd);
ddrclk_pad : outpad_ds generic map (tech => virtex4, level => sstl2_ii)
port map (ddr_clk(i), ddr_clkb(i), ddr_clkl(i), '1');
end generate;
end generate;
ddrclknodiffio : if phyiconf = 1 generate
ddrclocks1 : for i in 0 to 2 generate
dclk0r : ODDR port map ( Q => ddr_clkl(i), C => clk90r, CE => vcc,
D1 => vcc, D2 => gnd, R => gnd, S => gnd);
ddrclk1_pad : outpad generic map (tech => virtex4, level => sstl2_ii)
port map (ddr_clk(i), ddr_clkl(i));
dclk0rb : ODDR port map ( Q => ddr_clkbl(i), C => clk90r, CE => vcc,
D1 => gnd, D2 => vcc, R => gnd, S => gnd);
ddrclk1b_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clkb(i), ddr_clkbl(i));
end generate;
end generate;
ddrbanks : for i in 0 to 1 generate
csn0gen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_csnr(i), C => clk0r, CE => vcc,
D1 => csn(i), D2 => csn(i), R => gnd, S => gnd);
csn0_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_csb(i), ddr_csnr(i));
ckel(i) <= cke(i) and locked;
ckegen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_ckenr(i), C => clk0r, CE => vcc,
D1 => ckel(i), D2 => ckel(i), R => gnd, S => gnd);
cke_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_cke(i), ddr_ckenr(i));
end generate;
rasgen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_rasnr, C => clk0r, CE => vcc,
D1 => rasn, D2 => rasn, R => gnd, S => gnd);
rasn_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_rasb, ddr_rasnr);
casgen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_casnr, C => clk0r, CE => vcc,
D1 => casn, D2 => casn, R => gnd, S => gnd);
casn_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_casb, ddr_casnr);
wengen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_wenr, C => clk0r, CE => vcc,
D1 => wen, D2 => wen, R => gnd, S => gnd);
wen_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_web, ddr_wenr);
dmgen : for i in 0 to dbits/8-1 generate
da0 : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_dmr(i), C => clk0r, CE => vcc,
D1 => dm(i+dbits/8), D2 => dm(i), R => gnd, S => gnd);
ddr_bm_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_dm(i), ddr_dmr(i));
end generate;
bagen : for i in 0 to 1 generate
da0 : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_bar(i), C => clk0r, CE => vcc,
D1 => ba(i), D2 => ba(i), R => gnd, S => gnd);
ddr_ba_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_ba(i), ddr_bar(i));
end generate;
dagen : for i in 0 to 13 generate
da0 : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_adr(i), C => clk0r, CE => vcc,
D1 => addr(i), D2 => addr(i), R => gnd, S => gnd);
ddr_ad_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_ad(i), ddr_adr(i));
end generate;
-- DQS generation
dsqreg : FD port map ( Q => dqsn, C => clk180r, D => oe);
dqsgen : for i in 0 to dbits/8-1 generate
da0 : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_dqsin(i), C => clk90r, CE => vcc,
D1 => dqsn, D2 => gnd, R => gnd, S => gnd);
doen : FD port map ( Q => ddr_dqsoen(i), C => clk0r, D => dqsoen);
dqs_pad : iopad generic map (tech => virtex4, level => sstl2_ii)
port map (pad => ddr_dqs(i), i => ddr_dqsin(i), en => ddr_dqsoen(i),
o => ddr_dqsoutl(i));
end generate;
-- Data bus
read_rstdel : process (clk_0r, lockl)
begin
if lockl = '0' then dll2rst <= (others => '1');
elsif rising_edge(clk_0r) then
dll2rst <= dll2rst(1 to 3) & '0';
end if;
end process;
bufg7 : BUFG port map (I => rclk0, O => rclk0b);
bufg8 : BUFG port map (I => rclk90, O => rclk90b);
-- bufg9 : BUFG port map (I => rclk270, O => rclk270b);
rclk270b <= not rclk90b;
nops : if rskew = 0 generate
read_dll : DCM
generic map (clkin_period => 10.0, DESKEW_ADJUST => "SOURCE_SYNCHRONOUS")
port map ( CLKIN => ddrclkfbl, CLKFB => rclk0b, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2rst(0), CLK0 => rclk0,
CLK90 => rclk90, CLK270 => rclk270);
end generate;
ps : if rskew /= 0 generate
read_dll : DCM
generic map (clkin_period => 10.0, DESKEW_ADJUST => "SOURCE_SYNCHRONOUS",
CLKOUT_PHASE_SHIFT => "FIXED", PHASE_SHIFT => rskew)
port map ( CLKIN => ddrclkfbl, CLKFB => rclk0b, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2rst(0), CLK0 => rclk0,
CLK90 => rclk90, CLK270 => rclk270);
end generate;
ddgen : for i in 0 to dbits-1 generate
qi : IDDR generic map (DDR_CLK_EDGE => "OPPOSITE_EDGE")
port map ( Q1 => dqinl(i), --(i+dbits), -- 1-bit output for positive edge of clock
Q2 => dqin(i), -- 1-bit output for negative edge of clock
C => rclk90b, --clk270r, --dqsclk((2*i)/dbits), -- 1-bit clock input
CE => vcc, -- 1-bit clock enable input
D => ddr_dqin(i), -- 1-bit DDR data input
R => gnd, -- 1-bit reset
S => gnd -- 1-bit set
);
dinq1 : FD port map ( Q => dqin(i+dbits), C => rclk270b, D => dqinl(i));
dout : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_dqout(i), C => clk0r, CE => vcc,
D1 => dqout(i+dbits), D2 => dqout(i), R => gnd, S => gnd);
doen : FD port map ( Q => ddr_dqoen(i), C => clk0r, D => oen);
dq_pad : iopad generic map (tech => virtex4, level => sstl2_ii)
port map (pad => ddr_dq(i), i => ddr_dqout(i), en => ddr_dqoen(i), o => ddr_dqin(i));
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.DCM;
use unisim.FDDRRSE;
use unisim.IFDDRRSE;
use unisim.FD;
-- pragma translate_on
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
use techmap.oddrv2;
------------------------------------------------------------------
-- Virtex2 DDR PHY -----------------------------------------------
------------------------------------------------------------------
entity virtex2_ddr_phy is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; rskew : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0)
);
end;
architecture rtl of virtex2_ddr_phy is
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
component FDDRRSE
-- generic ( INIT : bit := '0');
port
(
Q : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D0 : in std_ulogic;
D1 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
component IFDDRRSE
port (
Q0 : out std_ulogic;
Q1 : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component FD
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic);
end component;
component oddrv2
generic ( tech : integer := virtex4);
port
( Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
signal vcc, gnd, dqsn, oe, lockl : std_ulogic;
signal ddr_clk_fb_outr : std_ulogic;
signal ddr_clk_fbl, fbclk : std_ulogic;
signal ddr_rasnr, ddr_casnr, ddr_wenr : std_ulogic;
signal ddr_clkl, ddr_clkbl : std_logic_vector(2 downto 0);
signal ddr_csnr, ddr_ckenr, ckel : std_logic_vector(1 downto 0);
signal clk_0ro, clk_90ro, clk_180ro, clk_270ro : std_ulogic;
signal clk_0r, clk_90r, clk_180r, clk_270r : std_ulogic;
signal clk0r, clk90r, clk180r, clk270r : std_ulogic;
signal locked, vlockl, ddrclkfbl : std_ulogic;
signal ddr_dqin : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqout : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqoen : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_adr : std_logic_vector (13 downto 0); -- ddr address
signal ddr_bar : std_logic_vector (1 downto 0); -- ddr address
signal ddr_dmr : std_logic_vector (dbits/8-1 downto 0); -- ddr address
signal ddr_dqsin : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoen : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoutl : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsdel, dqsclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal da : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dqinl : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dllrst : std_logic_vector(0 to 3);
signal dll0rst, dll2rst : std_logic_vector(0 to 3);
signal mlock, mclkfb, mclk, mclkfx, mclk0 : std_ulogic;
signal rclk270b, rclk90b, rclk0b : std_ulogic;
signal rclk270, rclk90, rclk0 : std_ulogic;
constant DDR_FREQ : integer := (MHz * clk_mul) / clk_div;
-- To prevent synplify 9.4 to remove any of these registers.
attribute syn_noprune : boolean;
attribute syn_noprune of FD : component is true;
attribute syn_noprune of FDDRRSE : component is true;
attribute syn_noprune of IFDDRRSE : component is true;
attribute syn_noprune of oddrv2 : component is true;
begin
oe <= not oen;
vcc <= '1'; gnd <= '0';
-- Optional DDR clock multiplication
noclkscale : if clk_mul = clk_div generate
mclk <= clk; mlock <= rst;
end generate;
clkscale : if clk_mul /= clk_div generate
rstdel : process (clk, rst)
begin
if rst = '0' then dll0rst <= (others => '1');
elsif rising_edge(clk) then
dll0rst <= dll0rst(1 to 3) & '0';
end if;
end process;
bufg0 : BUFG port map (I => mclkfx, O => mclk);
bufg1 : BUFG port map (I => mclk0, O => mclkfb);
dllm : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div,
CLKIN_PERIOD => 10.0)
port map ( CLKIN => clk, CLKFB => mclkfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst(0), CLK0 => mclk0,
LOCKED => mlock, CLKFX => mclkfx );
end generate;
-- DDR output clock generation
bufg1 : BUFG port map (I => clk_0ro, O => clk_0r);
-- bufg2 : BUFG port map (I => clk_90ro, O => clk_90r);
clk_90r <= not clk_270r;
-- bufg3 : BUFG port map (I => clk_180ro, O => clk_180r);
clk_180r <= not clk_0r;
bufg4 : BUFG port map (I => clk_270ro, O => clk_270r);
clkout <= clk_270r; clk0r <= clk_270r; clk90r <= clk_0r;
clk180r <= clk_90r; clk270r <= clk_180r;
dll : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2)
port map ( CLKIN => mclk, CLKFB => clk_0r, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst(0), CLK0 => clk_0ro,
CLK90 => clk_90ro, CLK180 => clk_180ro, CLK270 => clk_270ro,
LOCKED => lockl);
rstdel : process (mclk, mlock)
begin
if mlock = '0' then dllrst <= (others => '1');
elsif rising_edge(mclk) then
dllrst <= dllrst(1 to 3) & '0';
end if;
end process;
rdel : if rstdelay /= 0 generate
rcnt : process (clk_0r)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk_0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*DDR_FREQ, 16); vlock := '0';
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
-- Generate external DDR clock
fbdclk0r : FDDRRSE port map ( Q => ddr_clk_fb_outr, C0 => clk90r, C1 => clk270r,
CE => vcc, D0 => vcc, D1 => gnd, R => gnd, S => gnd);
fbclk_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clk_fb_out, ddr_clk_fb_outr);
ddrclocks : for i in 0 to 2 generate
dclk0r : FDDRRSE port map ( Q => ddr_clkl(i), C0 => clk90r, C1 => clk270r,
CE => vcc, D0 => vcc, D1 => gnd, R => gnd, S => gnd);
ddrclk_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clk(i), ddr_clkl(i));
dclk0rb : FDDRRSE port map ( Q => ddr_clkbl(i), C0 => clk90r, C1 => clk270r,
CE => vcc, D0 => gnd, D1 => vcc, R => gnd, S => gnd);
ddrclkb_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clkb(i), ddr_clkbl(i));
end generate;
ddrbanks : for i in 0 to 1 generate
csn0gen : FD port map ( Q => ddr_csnr(i), C => clk0r, D => csn(i));
csn0_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_csb(i), ddr_csnr(i));
ckel(i) <= cke(i) and locked;
ckegen : FD port map ( Q => ddr_ckenr(i), C => clk0r, D => ckel(i));
cke_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_cke(i), ddr_ckenr(i));
end generate;
-- DDR single-edge control signals
rasgen : FD port map ( Q => ddr_rasnr, C => clk0r, D => rasn);
rasn_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_rasb, ddr_rasnr);
casgen : FD port map ( Q => ddr_casnr, C => clk0r, D => casn);
casn_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_casb, ddr_casnr);
wengen : FD port map ( Q => ddr_wenr, C => clk0r, D => wen);
wen_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_web, ddr_wenr);
dmgen : for i in 0 to dbits/8-1 generate
da0 : oddrv2 port map ( Q => ddr_dmr(i), C1 => clk0r, C2 => clk180r,
CE => vcc, D1 => dm(i+dbits/8), D2 => dm(i), R => gnd, S => gnd);
ddr_bm_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_dm(i), ddr_dmr(i));
end generate;
bagen : for i in 0 to 1 generate
da0 : FD port map ( Q => ddr_bar(i), C => clk0r, D => ba(i));
ddr_ba_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_ba(i), ddr_bar(i));
end generate;
dagen : for i in 0 to 13 generate
da0 : FD port map ( Q => ddr_adr(i), C => clk0r, D => addr(i));
ddr_ad_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_ad(i), ddr_adr(i));
end generate;
-- DQS generation
dsqreg : FD port map ( Q => dqsn, C => clk180r, D => oe);
dqsgen : for i in 0 to dbits/8-1 generate
da0 : oddrv2
port map ( Q => ddr_dqsin(i), C1 => clk90r, C2 => clk270r,
CE => vcc, D1 => dqsn, D2 => gnd, R => gnd, S => gnd);
doen : FD port map ( Q => ddr_dqsoen(i), C => clk0r, D => dqsoen);
dqs_pad : iopad generic map (tech => virtex4, level => sstl2_ii)
port map (pad => ddr_dqs(i), i => ddr_dqsin(i), en => ddr_dqsoen(i),
o => ddr_dqsoutl(i));
end generate;
-- Data bus
ddrref_pad : clkpad generic map (tech => virtex2)
port map (ddr_clk_fb, ddrclkfbl);
read_rstdel : process (clk_0r, lockl)
begin
if lockl = '0' then dll2rst <= (others => '1');
elsif rising_edge(clk_0r) then
dll2rst <= dll2rst(1 to 3) & '0';
end if;
end process;
bufg7 : BUFG port map (I => rclk0, O => rclk0b);
bufg8 : BUFG port map (I => rclk90, O => rclk90b);
-- bufg9 : BUFG port map (I => rclk270, O => rclk270b);
rclk270b <= not rclk90b;
nops : if rskew = 0 generate
read_dll : DCM
generic map (clkin_period => 10.0, DESKEW_ADJUST => "SOURCE_SYNCHRONOUS")
port map ( CLKIN => ddrclkfbl, CLKFB => rclk0b, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2rst(0), CLK0 => rclk0,
CLK90 => rclk90, CLK270 => rclk270);
end generate;
ps : if rskew /= 0 generate
read_dll : DCM
generic map (clkin_period => 10.0, DESKEW_ADJUST => "SOURCE_SYNCHRONOUS",
CLKOUT_PHASE_SHIFT => "FIXED", PHASE_SHIFT => rskew)
port map ( CLKIN => ddrclkfbl, CLKFB => rclk0b, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2rst(0), CLK0 => rclk0,
CLK90 => rclk90, CLK270 => rclk270);
end generate;
ddgen : for i in 0 to dbits-1 generate
qi : IFDDRRSE
port map ( Q0 => dqinl(i), --(i+dbits), -- 1-bit output for positive edge of clock
Q1 => dqin(i), -- 1-bit output for negative edge of clock
C0 => rclk90b, -- clk270r, --dqsclk((2*i)/dbits), -- 1-bit clock input
C1 => rclk270b, -- clk90r, --dqsclk((2*i)/dbits), -- 1-bit clock input
CE => vcc, -- 1-bit clock enable input
D => ddr_dq(i), -- 1-bit DDR data input
R => gnd, -- 1-bit reset
S => gnd -- 1-bit set
);
-- dinq1 : FD port map ( Q => dqin(i+dbits), C => clk90r, D => dqinl(i));
dinq1 : FD port map ( Q => dqin(i+dbits), C => rclk270b, D => dqinl(i));
dout : oddrv2
port map ( Q => ddr_dqout(i), C1 => clk0r, C2 => clk180r, CE => vcc,
D1 => dqout(i+dbits), D2 => dqout(i), R => gnd, S => gnd);
doen : FD port map ( Q => ddr_dqoen(i), C => clk0r, D => oen);
dq_pad : iopad generic map (tech => virtex4, level => sstl2_ii)
port map (pad => ddr_dq(i), i => ddr_dqout(i), en => ddr_dqoen(i), o => open); -- o => ddr_dqin(i));
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.DCM;
use unisim.ODDR2;
use unisim.IDDR2;
use unisim.FD;
-- pragma translate_on
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
use techmap.oddrc3e;
------------------------------------------------------------------
-- Spartan3E DDR PHY -----------------------------------------------
------------------------------------------------------------------
entity spartan3e_ddr_phy is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; rskew : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- DDR state clock
clkread : out std_ulogic; -- DDR read clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0)
);
end;
architecture rtl of spartan3e_ddr_phy is
component oddrc3e
generic ( tech : integer := virtex4);
port
( Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
component FD
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic);
end component;
component ODDR2
generic
(
DDR_ALIGNMENT : string := "NONE";
INIT : bit := '0';
SRTYPE : string := "SYNC"
);
port
(
Q : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D0 : in std_ulogic;
D1 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
component IDDR2
generic
(
DDR_ALIGNMENT : string := "NONE";
INIT_Q0 : bit := '0';
INIT_Q1 : bit := '0';
SRTYPE : string := "SYNC"
);
port
(
Q0 : out std_ulogic;
Q1 : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
signal vcc, gnd, dqsn, oe, lockl : std_ulogic;
signal ddr_clk_fb_outr : std_ulogic;
signal ddr_clk_fbl, fbclk : std_ulogic;
signal ddr_rasnr, ddr_casnr, ddr_wenr : std_ulogic;
signal ddr_clkl, ddr_clkbl : std_logic_vector(2 downto 0);
signal ddr_csnr, ddr_ckenr, ckel : std_logic_vector(1 downto 0);
signal clk_0ro, clk_90ro, clk_180ro, clk_270ro : std_ulogic;
signal clk_0r, clk_90r, clk_180r, clk_270r : std_ulogic;
signal clk0r, clk90r, clk180r, clk270r : std_ulogic;
signal locked, vlockl, ddrclkfbl, dllfb : std_ulogic;
signal ddr_dqin : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqout : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqoen : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_adr : std_logic_vector (13 downto 0); -- ddr address
signal ddr_bar : std_logic_vector (1 downto 0); -- ddr address
signal ddr_dmr : std_logic_vector (dbits/8-1 downto 0); -- ddr address
signal ddr_dqsin : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoen : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoutl : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsdel, dqsclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal da : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dqinl : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dllrst : std_logic_vector(0 to 3);
signal dll0rst, dll2rst : std_logic_vector(0 to 3);
signal mlock, mclkfb, mclk, mclkfx, mclk0 : std_ulogic;
signal rclk270b, rclk90b, rclk0b : std_ulogic;
signal rclk270, rclk90, rclk0 : std_ulogic;
constant DDR_FREQ : integer := (MHz * clk_mul) / clk_div;
-- To prevent synplify 9.4 to remove any of these registers.
attribute syn_noprune : boolean;
attribute syn_noprune of FD : component is true;
attribute syn_noprune of IDDR2 : component is true;
attribute syn_noprune of ODDR2 : component is true;
attribute syn_noprune of oddrc3e : component is true;
begin
oe <= not oen;
vcc <= '1'; gnd <= '0';
-- Optional DDR clock multiplication
noclkscale : if clk_mul = clk_div generate
mclk <= clk; mlock <= rst;
end generate;
clkscale : if clk_mul /= clk_div generate
rstdel : process (clk, rst)
begin
if rst = '0' then dll0rst <= (others => '1');
elsif rising_edge(clk) then
dll0rst <= dll0rst(1 to 3) & '0';
end if;
end process;
bufg0 : BUFG port map (I => mclkfx, O => mclk);
bufg1 : BUFG port map (I => mclk0, O => mclkfb);
dllm : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div,
CLKIN_PERIOD => 10.0)
port map ( CLKIN => clk, CLKFB => mclkfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst(0), CLK0 => mclk0,
LOCKED => mlock, CLKFX => mclkfx );
end generate;
-- DDR output clock generation
bufg1 : BUFG port map (I => clk_0ro, O => clk_0r);
-- bufg2 : BUFG port map (I => clk_90ro, O => clk_90r);
clk_90r <= not clk_270r;
-- bufg3 : BUFG port map (I => clk_180ro, O => clk_180r);
clk_180r <= not clk_0r;
bufg4 : BUFG port map (I => clk_270ro, O => clk_270r);
clkout <= clk_270r;
-- clkout <= clk_90r when DDR_FREQ > 120 else clk_0r;
clk0r <= clk_270r; clk90r <= clk_0r;
clk180r <= clk_90r; clk270r <= clk_180r;
dll : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2)
port map ( CLKIN => mclk, CLKFB => clk_0r, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst(0), CLK0 => clk_0ro,
CLK90 => clk_90ro, CLK180 => clk_180ro, CLK270 => clk_270ro,
LOCKED => lockl);
rstdel : process (mclk, mlock)
begin
if mlock = '0' then dllrst <= (others => '1');
elsif rising_edge(mclk) then
dllrst <= dllrst(1 to 3) & '0';
end if;
end process;
rdel : if rstdelay /= 0 generate
rcnt : process (clk_0r)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk_0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*DDR_FREQ, 16); vlock := '0';
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
-- Generate external DDR clock
fbdclk0r : ODDR2 port map ( Q => ddr_clk_fb_outr, C0 => clk90r, C1 => clk270r,
CE => vcc, D0 => vcc, D1 => gnd, R => gnd, S => gnd);
fbclk_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clk_fb_out, ddr_clk_fb_outr);
ddrclocks : for i in 0 to 2 generate
dclk0r : ODDR2 port map ( Q => ddr_clkl(i), C0 => clk90r, C1 => clk270r,
CE => vcc, D0 => vcc, D1 => gnd, R => gnd, S => gnd);
ddrclk_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clk(i), ddr_clkl(i));
dclk0rb : ODDR2 port map ( Q => ddr_clkbl(i), C0 => clk90r, C1 => clk270r,
CE => vcc, D0 => gnd, D1 => vcc, R => gnd, S => gnd);
ddrclkb_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clkb(i), ddr_clkbl(i));
end generate;
ddrbanks : for i in 0 to 1 generate
csn0gen : FD port map ( Q => ddr_csnr(i), C => clk0r, D => csn(i));
csn0_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_csb(i), ddr_csnr(i));
ckel(i) <= cke(i) and locked;
ckegen : FD port map ( Q => ddr_ckenr(i), C => clk0r, D => ckel(i));
cke_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_cke(i), ddr_ckenr(i));
end generate;
-- DDR single-edge control signals
rasgen : FD port map ( Q => ddr_rasnr, C => clk0r, D => rasn);
rasn_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_rasb, ddr_rasnr);
casgen : FD port map ( Q => ddr_casnr, C => clk0r, D => casn);
casn_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_casb, ddr_casnr);
wengen : FD port map ( Q => ddr_wenr, C => clk0r, D => wen);
wen_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_web, ddr_wenr);
dmgen : for i in 0 to dbits/8-1 generate
da0 : oddrc3e
port map ( Q => ddr_dmr(i), C1 => clk0r, C2 => clk180r,
CE => vcc, D1 => dm(i+dbits/8), D2 => dm(i), R => gnd, S => gnd);
ddr_bm_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_dm(i), ddr_dmr(i));
end generate;
bagen : for i in 0 to 1 generate
da0 : FD port map ( Q => ddr_bar(i), C => clk0r, D => ba(i));
ddr_ba_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_ba(i), ddr_bar(i));
end generate;
dagen : for i in 0 to 13 generate
da0 : FD port map ( Q => ddr_adr(i), C => clk0r, D => addr(i));
ddr_ad_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_ad(i), ddr_adr(i));
end generate;
-- DQS generation
dsqreg : FD port map ( Q => dqsn, C => clk180r, D => oe);
dqsgen : for i in 0 to dbits/8-1 generate
da0 : oddrc3e
port map ( Q => ddr_dqsin(i), C1 => clk90r, C2 => clk270r,
CE => vcc, D1 => dqsn, D2 => gnd, R => gnd, S => gnd);
doen : FD port map ( Q => ddr_dqsoen(i), C => clk0r, D => dqsoen);
dqs_pad : iopad generic map (tech => virtex4, level => sstl2_i)
port map (pad => ddr_dqs(i), i => ddr_dqsin(i), en => ddr_dqsoen(i),
o => ddr_dqsoutl(i));
end generate;
-- Data bus
ddrref_pad : clkpad generic map (tech => virtex2)
port map (ddr_clk_fb, ddrclkfbl);
read_rstdel : process (clk_0r, lockl)
begin
if lockl = '0' then dll2rst <= (others => '1');
elsif rising_edge(clk_0r) then
dll2rst <= dll2rst(1 to 3) & '0';
end if;
end process;
bufg7 : BUFG port map (I => rclk0, O => rclk0b);
bufg8 : BUFG port map (I => rclk90, O => rclk90b);
-- bufg9 : BUFG port map (I => rclk270, O => rclk270b);
rclk270b <= not rclk90b;
clkread <= not rclk90b;
nops : if rskew = 0 generate
read_dll : DCM
generic map (clkin_period => 10.0, DESKEW_ADJUST => "SOURCE_SYNCHRONOUS")
port map ( CLKIN => ddrclkfbl, CLKFB => rclk0b, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2rst(0), CLK0 => rclk0,
CLK90 => rclk90, CLK270 => rclk270);
end generate;
ps : if rskew /= 0 generate
read_dll : DCM
generic map (clkin_period => 10.0, DESKEW_ADJUST => "SOURCE_SYNCHRONOUS",
CLKOUT_PHASE_SHIFT => "FIXED", PHASE_SHIFT => rskew)
port map ( CLKIN => ddrclkfbl, CLKFB => rclk0b, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2rst(0), CLK0 => rclk0,
CLK90 => rclk90, CLK270 => rclk270);
end generate;
ddgen : for i in 0 to dbits-1 generate
qi : IDDR2
port map ( Q0 => dqinl(i), Q1 => dqin(i), C0 => rclk90b, C1 => rclk270b,
CE => vcc, D => ddr_dqin(i), R => gnd, S => gnd );
dinq1 : FD port map ( Q => dqin(i+dbits), C => rclk270b, D => dqinl(i));
dout : oddrc3e
port map ( Q => ddr_dqout(i), C1 => clk0r, C2 => clk180r, CE => vcc,
D1 => dqout(i+dbits), D2 => dqout(i), R => gnd, S => gnd);
doen : FD port map ( Q => ddr_dqoen(i), C => clk0r, D => oen);
dq_pad : iopad generic map (tech => virtex4, level => sstl2_i)
port map (pad => ddr_dq(i), i => ddr_dqout(i), en => ddr_dqoen(i), o => ddr_dqin(i));
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.DCM;
use unisim.ODDR;
use unisim.FD;
use unisim.IDELAY;
use unisim.ISERDES;
use unisim.BUFIO;
use unisim.IDELAYCTRL;
use unisim.IDDR;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
------------------------------------------------------------------
-- Virtex5 DDR2 PHY ----------------------------------------------
------------------------------------------------------------------
entity virtex5_ddr2_phy_wo_pads is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2; clk_div : integer := 2;
ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0;
ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0;
ddelayb6 : integer := 0; ddelayb7 : integer := 0; ddelayb8 : integer := 0;
ddelayb9 : integer := 0; ddelayb10: integer := 0; ddelayb11: integer := 0;
numidelctrl : integer := 4; norefclk : integer := 0;
tech : integer := virtex5; odten : integer := 0;
eightbanks : integer range 0 to 1 := 0;
dqsse : integer range 0 to 1 := 0; abits: integer := 14; nclk: integer := 3;
ncs: integer := 2);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref200 : in std_logic; -- input 200MHz clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock return
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0);
addr : in std_logic_vector (abits-1 downto 0); -- ddr address
ba : in std_logic_vector ( 2 downto 0); -- ddr bank address
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
cal_en : in std_logic_vector(dbits/8-1 downto 0);
cal_inc : in std_logic_vector(dbits/8-1 downto 0);
cal_rst : in std_logic;
odt : in std_logic_vector(ncs-1 downto 0)
);
end;
architecture rtl of virtex5_ddr2_phy_wo_pads is
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
component ODDR
generic
( DDR_CLK_EDGE : string := "OPPOSITE_EDGE";
-- INIT : bit := '0';
SRTYPE : string := "SYNC");
port
(
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
component FD
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic);
end component;
component IDDR
generic ( DDR_CLK_EDGE : string := "SAME_EDGE";
INIT_Q1 : bit := '0';
INIT_Q2 : bit := '0';
SRTYPE : string := "ASYNC");
port
( Q1 : out std_ulogic;
Q2 : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component IDELAY
generic ( IOBDELAY_TYPE : string := "DEFAULT";
IOBDELAY_VALUE : integer := 0);
port ( O : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
I : in std_ulogic;
INC : in std_ulogic;
RST : in std_ulogic);
end component;
component OBUFDS
generic (
CAPACITANCE : string := "DONT_CARE";
IOSTANDARD : string := "DEFAULT";
SLEW : string := "SLOW"
);
port (
O : out std_ulogic;
OB : out std_ulogic;
I : in std_ulogic
);
end component;
component IDELAYCTRL
port ( RDY : out std_ulogic;
REFCLK : in std_ulogic;
RST : in std_ulogic);
end component;
signal vcc, gnd, oe, lockl : std_ulogic;
signal dqsn : std_logic_vector(dbits/8-1 downto 0);
signal cbdqsn : std_logic_vector(dbits/8-1 downto 0);
signal ddr_clk_fb_outr : std_ulogic;
signal ddr_clk_fbl, fbclk : std_ulogic;
signal ddr_rasnr, ddr_casnr, ddr_wenr : std_ulogic;
signal ddr_rasnr2, ddr_casnr2, ddr_wenr2 : std_ulogic;
signal ddr_clkl, ddr_clkbl : std_logic_vector(nclk-1 downto 0);
signal ddr_csnr, ddr_ckenr, ckel : std_logic_vector(ncs-1 downto 0);
signal clk_0ro, clk_90ro, clk_180ro, clk_270ro : std_ulogic;
signal clk_0r, clk_90r, clk_180r, clk_270r : std_ulogic;
signal clk90r, clk180r, clk270r : std_ulogic;
signal locked, vlockl, ddrclkfbl, dllfb : std_ulogic;
signal ddr_dqin, ddr_dqin_nodel : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqout : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqoen : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_cbdqin, ddr_cbdqin_nodel : std_logic_vector (dbits-1 downto 0); -- ddr checkbits
signal ddr_cbdqout : std_logic_vector (dbits-1 downto 0); -- ddr checkbits
signal ddr_cbdqoen : std_logic_vector (dbits-1 downto 0); -- ddr checkbits
signal ddr_adr : std_logic_vector (abits-1 downto 0); -- ddr address
signal ddr_bar : std_logic_vector (1+eightbanks downto 0); -- ddr address
signal ddr_adr2 : std_logic_vector (abits-1 downto 0); -- ddr address
signal ddr_bar2 : std_logic_vector (1+eightbanks downto 0); -- ddr address
signal ddr_dmr : std_logic_vector (dbits/8-1 downto 0); -- ddr data mask
signal ddr_cbdmr : std_logic_vector (dbits/8-1 downto 0); -- ddr checkbit mask
signal ddr_dqsin : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoen_reg: std_logic_vector (dbits/8-1 downto 0); -- ddr dqs reg
signal ddr_dqsoen : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoutl : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_cbdqsin : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_cbdqsoen_reg: std_logic_vector (dbits/8-1 downto 0); -- ddr dqs reg
signal ddr_cbdqsoen : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_cbdqsoutl : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsdel, dqsclk, dqsclkn : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal da : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dqinl : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dllrst : std_logic_vector(0 to 3);
signal dll0rst, dll2rst : std_logic_vector(0 to 3);
signal mlock, mclkfb, mclk, mclkfx, mclk0 : std_ulogic;
signal rclk270b, rclk90b, rclk0b : std_ulogic;
signal rclk270, rclk90, rclk0 : std_ulogic;
signal clk200, clk200_0, clk200fb, clk200fx, lock200 : std_logic;
signal odtl : std_logic_vector(ncs-1 downto 0);
signal refclk_rdy : std_logic_vector(numidelctrl-1 downto 0);
constant DDR_FREQ : integer := (MHz * clk_mul) / clk_div;
type ddelay_type is array (0 to 11) of integer;
constant ddelay : ddelay_type := (ddelayb0, ddelayb1, ddelayb2,
ddelayb3, ddelayb4, ddelayb5,
ddelayb6, ddelayb7, ddelayb8,
ddelayb9, ddelayb10, ddelayb11);
attribute syn_noprune : boolean;
attribute syn_noprune of IDELAYCTRL : component is true;
attribute syn_keep : boolean;
attribute syn_keep of dqsclk : signal is true;
attribute syn_preserve : boolean;
attribute syn_preserve of dqsclk : signal is true;
attribute syn_keep of dqsn : signal is true;
attribute syn_preserve of dqsn : signal is true;
-- To prevent synplify 9.4 to remove any of these registers.
attribute syn_noprune of FD : component is true;
attribute syn_noprune of IDDR : component is true;
attribute syn_noprune of ODDR : component is true;
attribute keep : boolean;
attribute keep of mclkfx : signal is true;
attribute keep of clk_90ro : signal is true;
attribute syn_keep of mclkfx : signal is true;
attribute syn_keep of clk_90ro : signal is true;
begin
-- Generate 200 MHz ref clock if not supplied
refclkx : if norefclk = 0 generate
buf_clk200 : BUFG port map( I => clkref200, O => clk200);
lock200 <= '1';
end generate;
norefclkx : if norefclk /= 0 generate
bufg0 : BUFG port map (I => clk200fx, O => clk200);
HMODE_dll200 : if (tech = virtex4 and MHz >= 210) or (tech = virtex5) generate
dll200 : DCM
generic map (
CLKFX_MULTIPLY => 400/MHz, CLKFX_DIVIDE => 2,
DFS_FREQUENCY_MODE => "HIGH", DLL_FREQUENCY_MODE => "HIGH",
CLK_FEEDBACK => "NONE")
port map (
CLKIN => clk, CLKFB => clk200fb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst(0),
LOCKED => lock200, CLKFX => clk200fx);
end generate;
LMODE_dll200 : if not ((tech = virtex4 and MHz >= 210) or (tech = virtex5)) generate
dll200 : DCM
generic map (
CLKFX_MULTIPLY => 400/MHz, CLKFX_DIVIDE => 2,
DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW",
CLK_FEEDBACK => "NONE")
port map (
CLKIN => clk, CLKFB => clk200fb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst(0),
LOCKED => lock200, CLKFX => clk200fx);
end generate;
end generate;
-- Delay control
idelctrl : for i in 0 to numidelctrl-1 generate
u : IDELAYCTRL port map (rst => dllrst(0), refclk => clk200, rdy => refclk_rdy(i));
end generate;
oe <= not oen;
vcc <= '1';
gnd <= '0';
-- Optional DDR clock multiplication
noclkscale : if clk_mul = clk_div generate
dll0rst <= dllrst;
mlock <= '1';
mbufg0 : BUFG port map (I => clk, O => mclk);
end generate;
clkscale : if clk_mul /= clk_div generate
rstdel : process (clk, rst)
begin
if rst = '0' then
dll0rst <= (others => '1');
elsif rising_edge(clk) then
dll0rst <= dll0rst(1 to 3) & '0';
end if;
end process;
bufg0 : BUFG port map (I => mclkfx, O => mclk);
bufg1 : BUFG port map (I => mclk0, O => mclkfb);
HMODE_dllm : if (tech = virtex4 and (((MHz*clk_mul)/clk_div >= 210) or (MHz >= 210)))
or (tech = virtex5 and (((MHz*clk_mul)/clk_div > 140) or (MHz > 120))) generate
dllm : DCM
generic map (
CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div,
DFS_FREQUENCY_MODE => "HIGH", DLL_FREQUENCY_MODE => "HIGH")
port map (
CLKIN => clk, CLKFB => mclkfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst(0), CLK0 => mclk0,
LOCKED => mlock, CLKFX => mclkfx );
end generate;
LMODE_dllm : if not ((tech = virtex4 and (((MHz*clk_mul)/clk_div >= 210) or (MHz >= 210)))
or (tech = virtex5 and (((MHz*clk_mul)/clk_div > 140) or (MHz > 120)))) generate
dllm : DCM
generic map (
CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div,
DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW")
port map (
CLKIN => clk, CLKFB => mclkfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst(0), CLK0 => mclk0,
LOCKED => mlock, CLKFX => mclkfx );
end generate;
end generate;
-- DDR clock generation
bufg2 : BUFG port map (I => clk_90ro, O => clk90r);
clk180r <= not mclk;
clkout <= mclk;
dllfb <= clk90r;
HMODE_dll : if (tech = virtex4 and ((MHz*clk_mul)/clk_div >= 150))
or (tech = virtex5 and ((MHz*clk_mul)/clk_div >= 120)) generate
dll : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2,
DFS_FREQUENCY_MODE => "HIGH", DLL_FREQUENCY_MODE => "HIGH", --"HIGH")
PHASE_SHIFT => 64, CLKOUT_PHASE_SHIFT => "FIXED")--, CLKIN_PERIOD => real((1000*clk_div)/(MHz*clk_mul)))
port map ( CLKIN => mclk, CLKFB => dllfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst(0), CLK0 => clk_90ro,
CLK90 => open, CLK180 => open, CLK270 => open,
LOCKED => lockl);
end generate;
LMODE_dll : if not ((tech = virtex4 and ((MHz*clk_mul)/clk_div >= 150))
or (tech = virtex5 and ((MHz*clk_mul)/clk_div >= 120))) generate
dll : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2,
DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW", --"HIGH")
PHASE_SHIFT => 64, CLKOUT_PHASE_SHIFT => "FIXED")--, CLKIN_PERIOD => real((1000*clk_div)/(MHz*clk_mul)))
port map ( CLKIN => mclk, CLKFB => dllfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst(0), CLK0 => clk_90ro,
CLK90 => open, CLK180 => open, CLK270 => open,
LOCKED => lockl);
end generate;
rstdel : process (mclk, rst, mlock, lock200)
begin
if rst = '0' or mlock = '0' or lock200 = '0' then dllrst <= (others => '1');
elsif rising_edge(mclk) then
dllrst <= dllrst(1 to 3) & '0';
end if;
end process;
rdel : if rstdelay /= 0 generate
--rcnt : process (clk_0r)
rcnt : process (clkoutret)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
--if rising_edge(clk_0r) then
if rising_edge(clkoutret) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*DDR_FREQ, 16); vlock := '0';
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked and orv(refclk_rdy);
-- Generate external DDR clock
ddrclocks : for i in 0 to nclk-1 generate
dclk0r : ODDR port map ( Q => ddr_clk(i), C => clk90r, CE => vcc,
D1 => vcc, D2 => gnd, R => gnd, S => gnd);
ddr_clkb(i) <= '0'; -- unused
end generate;
-- ODT
odtgen : for i in 0 to ncs-1 generate
odtl(i) <= locked and orv(refclk_rdy) and odt(i);
ddr_odt(i) <= odtl(i);
end generate;
ddrbanks : for i in 0 to ncs-1 generate
csn0gen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_csnr(i), C => clk180r, CE => vcc,
D1 => csn(i), D2 => csn(i), R => gnd, S => gnd);
ddr_csb(i) <= ddr_csnr(i);
ckel(i) <= cke(i) and locked;
ckegen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_ckenr(i), C => clk180r, CE => vcc,
D1 => ckel(i), D2 => ckel(i), R => gnd, S => gnd);
ddr_cke(i) <= ddr_ckenr(i);
end generate;
rasgen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_rasnr, C => clk180r, CE => vcc,
D1 => rasn, D2 => rasn, R => gnd, S => gnd);
ddr_rasb <= ddr_rasnr;
casgen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_casnr, C => clk180r, CE => vcc,
D1 => casn, D2 => casn, R => gnd, S => gnd);
ddr_casb <= ddr_casnr;
wengen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_wenr, C => clk180r, CE => vcc,
D1 => wen, D2 => wen, R => gnd, S => gnd);
ddr_web <= ddr_wenr;
dmgen : for i in 0 to dbits/8-1 generate
da0 : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_dmr(i), C => clkoutret, CE => vcc,
D1 => dm(i+dbits/8), D2 => dm(i), R => gnd, S => gnd);
end generate;
ddr_dm <= ddr_dmr;
bagen : for i in 0 to 1+eightbanks generate
da0 : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_bar(i), C => clk180r, CE => vcc,
D1 => ba(i), D2 => ba(i), R => gnd, S => gnd);
end generate;
ddr_ba <= ddr_bar;
dagen : for i in 0 to abits-1 generate
da0 : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_adr(i), C => clk180r, CE => vcc,
D1 => addr(i), D2 => addr(i), R => gnd, S => gnd);
end generate;
ddr_ad <= ddr_adr;
-- DQS generation
dqsgen : for i in 0 to dbits/8-1 generate
dsqreg : FD port map ( Q => dqsn(i), C => clk180r, D => oe);
da0 : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_dqsin(i), C => clk90r, CE => vcc,
--D1 => dqsn, D2 => gnd, R => gnd, S => gnd);
D1 => dqsn(i), D2 => gnd, R => gnd, S => gnd);
doen_reg : FD port map ( Q => ddr_dqsoen_reg(i), C => clk180r, D => dqsoen);
doen : FD port map ( Q => ddr_dqsoen(i), C => clk90r, D => ddr_dqsoen_reg(i));
end generate;
ddr_dqs_out <= ddr_dqsin;
ddr_dqs_oen <= ddr_dqsoen;
ddr_dqsoutl <= ddr_dqs_in;
-- Data bus
ddgen : for i in 0 to dbits-1 generate
del_dq0 : IDELAY generic map(IOBDELAY_TYPE => "VARIABLE", IOBDELAY_VALUE => ddelay(i/8))
port map(O => ddr_dqin(i), I => ddr_dqin_nodel(i), C => clkoutret, CE => cal_en(i/8),
INC => cal_inc(i/8), RST => cal_rst);
qi : IDDR generic map (DDR_CLK_EDGE => "OPPOSITE_EDGE")
port map ( Q1 => dqinl(i), --(i+dbits), -- 1-bit output for positive edge of clock
Q2 => dqin(i), --dqin(i), -- 1-bit output for negative edge of clock
C => clk180r, --clk270r, --dqsclk((2*i)/dbits), -- 1-bit clock input
CE => vcc, -- 1-bit clock enable input
D => ddr_dqin(i), -- 1-bit DDR data input
R => gnd, -- 1-bit reset
S => gnd -- 1-bit set
);
dinq1 : FD port map ( Q => dqin(i+dbits), C => clkoutret, D => dqinl(i));
dout : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_dqout(i), C => clkoutret, CE => vcc,
D1 => dqout(i+dbits), D2 => dqout(i), R => gnd, S => gnd);
doen : FD
generic map (INIT => '1')
port map ( Q => ddr_dqoen(i), C => clkoutret, D => oen);
end generate;
ddr_dq_out <= ddr_dqout;
ddr_dq_oen <= ddr_dqoen;
ddr_dqin_nodel <= ddr_dq_in;
end;
------------------------------------------------------------------
-- Spartan 3A DDR2 PHY -------------------------------------------
------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.DCM;
use unisim.IDDR2;
use unisim.ODDR2;
use unisim.FD;
use unisim.BUFIO;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity spartan3a_ddr2_phy is
generic (MHz : integer := 125; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2;
clk_div : integer := 2; tech : integer := spartan3;
rskew : integer := 0; eightbanks : integer range 0 to 1 := 0);
port ( rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- DDR clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqsn
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(1 downto 0);
addr : in std_logic_vector (13 downto 0); -- row address
ba : in std_logic_vector ( 2 downto 0); -- bank address
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr output data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0);
cal_pll : in std_logic_vector(1 downto 0);
odt : in std_logic_vector(1 downto 0));
end;
architecture rtl of spartan3a_ddr2_phy is
component DCM
generic (CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false);
port ( CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFG
port (O : out std_logic;
I : in std_logic);
end component;
component ODDR2
generic (DDR_ALIGNMENT : string := "NONE"; -- Sets output alignment to "NONE", "C0" or "C1"
INIT : bit := '0'; -- Sets initial state of the Q0
SRTYPE : string := "SYNC"); -- Specifies "SYNC" or "ASYNC" set/reset
port ( Q : out std_ulogic; -- 1-bit DDR output data
C0 : in std_ulogic; -- 1-bit clock input
C1 : in std_ulogic; -- 1-bit clock input
CE : in std_ulogic; -- 1-bit clock enable input
D0 : in std_ulogic; -- 1-bit data input (associated with C1)
D1 : in std_ulogic; -- 1-bit data input (associated with C1)
R : in std_ulogic; -- 1-bit reset input
S : in std_ulogic); -- 1-bit set input
end component;
component FD
generic (INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic);
end component;
component IDDR2
generic (DDR_ALIGNMENT : string := "NONE"; -- Sets output alignment to "NONE", "C0" or "C1"
INIT_Q0 : bit := '0'; -- Sets initial state of the Q0
INIT_Q1 : bit := '0'; -- Sets initial state of the Q1
SRTYPE : string := "SYNC"); -- Specifies "SYNC" or "ASYNC" set/reset
port ( Q0 : out std_ulogic; -- 1-bit output captured with C0 clock
Q1 : out std_ulogic; -- 1-bit output captured with C1 clock
C0 : in std_ulogic; -- 1-bit clock input
C1 : in std_ulogic; -- 1-bit clock input
CE : in std_ulogic; -- 1-bit clock enable input
D : in std_ulogic; -- 1-bit DDR data input
R : in std_ulogic; -- 1-bit reset input
S : in std_ulogic); -- 1-bit set input
end component;
signal vcc, gnd, oe, lockl : std_ulogic;
signal dqsn : std_logic_vector(dbits/8-1 downto 0);
signal ddr_rasnr, ddr_casnr, ddr_wenr : std_ulogic;
signal ddr_clkl, ddr_clkbl : std_logic_vector(2 downto 0);
signal ddr_csnr, ddr_ckenr, ckel : std_logic_vector(1 downto 0);
signal ddr_clk_fbl, ddr_clk_fb_outl : std_ulogic;
signal clk_90ro : std_ulogic;
signal clk0r, clk90r, clk180r, clk270r : std_ulogic;
signal rclk0b, rclk90b, rclk180b, rclk270b : std_ulogic;
signal rclk0, rclk90, rclk180, rclk270 : std_ulogic;
signal rclk0b_high, rclk90b_high, rclk270b_high : std_ulogic;
signal rclk0_high, rclk90_high, rclk270_high : std_ulogic;
signal locked, vlockl, dllfb : std_ulogic;
signal ddr_dqin : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqout : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqoen : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_adr : std_logic_vector (13 downto 0); -- ddr row address
signal ddr_bar : std_logic_vector (1+eightbanks downto 0); -- ddr bank address
signal ddr_dmr : std_logic_vector (dbits/8-1 downto 0); -- ddr mask
signal ddr_dqsin : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoen : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoutl : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqinl : std_logic_vector (dbits*2-1 downto 0); -- ddr data
signal dllrst : std_logic_vector(0 to 3);
signal dll0rst : std_ulogic;
signal dll1rst : std_ulogic;
signal mlock, mclkfb, mclk, mclkfx, mclk0 : std_ulogic;
signal odtl : std_logic_vector(1 downto 0);
--signals needed for alignment with DQS
signal dm_delay : std_logic_vector (dbits/8-1 downto 0);
signal dqout_delay : std_logic_vector (dbits-1 downto 0);
constant DDR_FREQ : integer := (MHz * clk_mul) / clk_div;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of dqsn : signal is true;
attribute syn_preserve of dqsn : signal is true;
attribute keep of mclkfx : signal is true;
attribute keep of clk_90ro : signal is true;
attribute syn_keep of mclkfx : signal is true;
attribute syn_keep of clk_90ro : signal is true;
-- To prevent synplify 9.4 to remove any of these registers.
attribute syn_noprune : boolean;
attribute syn_noprune of FD : component is true;
attribute syn_noprune of IDDR2 : component is true;
attribute syn_noprune of ODDR2 : component is true;
begin
oe <= not oen;
vcc <= '1'; gnd <= '0';
-- Optional DDR clock multiplication
noclkscale : if clk_mul = clk_div generate
mlock <= '1';
mbufg0 : BUFG port map (I => clk, O => mclk);
end generate;
clkscale : if clk_mul /= clk_div generate
rstdel : process (clk, rst)
begin
if rst = '0' then
dll0rst <= '1';
elsif rising_edge(clk) then
dll0rst <= '0';
end if;
end process;
bufg0 : BUFG port map (I => mclkfx, O => mclk);
bufg1 : BUFG port map (I => mclk0, O => mclkfb);
dllm : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div)
port map (CLKIN => clk, CLKFB => mclkfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst, CLK0 => mclk0,
LOCKED => mlock, CLKFX => mclkfx );
end generate;
-- DDR clock generation (90 degrees phase-shifted DLL)
bufg2 : BUFG port map (I => clk_90ro, O => clk90r);
dllfb <= clk90r;
dll : DCM
generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2,
CLKOUT_PHASE_SHIFT => "FIXED", PHASE_SHIFT => 64)
port map (CLKIN => mclk, CLKFB => dllfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst(0), CLK0 => clk_90ro,
CLK90 => open, CLK180 => open, CLK270 => open,
LOCKED => lockl);
clk0r <= mclk;
clk180r <= not mclk;
clk270r <= not clk90r;
clkout <= mclk;
rstdel : process (mclk, rst, mlock)
begin
if rst = '0' or mlock = '0' then
dllrst <= (others => '1');
elsif rising_edge(mclk) then
dllrst <= dllrst(1 to 3) & '0';
end if;
end process;
rdel : if rstdelay /= 0 generate
rcnt : process (clk0r)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*DDR_FREQ, 16);
vlock := '0';
elsif vlock = '0' then
cnt := cnt -1;
vlock := cnt(15) and not co;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
-- Generate external DDR clock
ddrclocks : for i in 0 to 2 generate
dclk0r : ODDR2
port map (Q => ddr_clkl(i), C0 => clk90r, C1 => clk270r, CE => vcc,
D0 => vcc, D1 => gnd, R => gnd, S => gnd);
ddrclk_pad : outpad
generic map (tech => virtex4, level => sstl18_i)
port map (ddr_clk(i), ddr_clkl(i));
dclk0rb : ODDR2
port map (Q => ddr_clkbl(i), C0 => clk90r, C1 => clk270r, CE => vcc,
D0 => gnd, D1 => vcc, R => gnd, S => gnd);
ddrclkb_pad : outpad
generic map (tech => virtex4, level => sstl18_i)
port map (ddr_clkb(i), ddr_clkbl(i));
end generate;
-- Generate the DDR clock to be fed back for DQ synchronization
dclkfb0r : ODDR2
port map (Q => ddr_clk_fb_outl, C0 => clk90r, C1 => clk270r, CE => vcc,
D0 => vcc, D1 => gnd, R => gnd, S => gnd);
ddrclkfb_pad : outpad
generic map (tech => virtex4, level => sstl18_i)
port map (ddr_clk_fb_out, ddr_clk_fb_outl);
-- The above clock fed back for DQ synchronization
ddrref_pad : clkpad generic map (tech => virtex4)
port map (ddr_clk_fb, ddr_clk_fbl);
-- ODT pads
odtgen : for i in 0 to 1 generate
odtl(i) <= locked and odt(i);
ddr_odt_pad : outpad
generic map (tech => virtex4, level => sstl18_i)
port map (ddr_odt(i), odtl(i));
end generate;
-- DDR single-edge control signals
ddrbanks : for i in 0 to 1 generate
csn0gen : FD
port map ( Q => ddr_csnr(i), C => clk0r, D => csn(i));
csn0_pad : outpad
generic map (tech => virtex4, level => sstl18_i)
port map (ddr_csb(i), ddr_csnr(i));
ckel(i) <= cke(i) and locked;
ckegen : FD
port map ( Q => ddr_ckenr(i), C => clk0r, D => ckel(i));
cke_pad : outpad
generic map (tech => virtex4, level => sstl18_i)
port map (ddr_cke(i), ddr_ckenr(i));
end generate;
rasgen : FD
port map ( Q => ddr_rasnr, C => clk0r, D => rasn);
rasn_pad : outpad
generic map (tech => virtex4, level => sstl18_i)
port map (ddr_rasb, ddr_rasnr);
casgen : FD
port map ( Q => ddr_casnr, C => clk0r, D => casn);
casn_pad : outpad
generic map (tech => virtex4, level => sstl18_i)
port map (ddr_casb, ddr_casnr);
wengen : FD
port map ( Q => ddr_wenr, C => clk0r, D => wen);
wen_pad : outpad
generic map (tech => virtex4, level => sstl18_i)
port map (ddr_web, ddr_wenr);
bagen : for i in 0 to 1+eightbanks generate
ba0 : FD
port map ( Q => ddr_bar(i), C => clk0r, D => ba(i));
ddr_ba_pad : outpad
generic map (tech => virtex4, level => sstl18_i)
port map (ddr_ba(i), ddr_bar(i));
end generate;
addrgen : for i in 0 to 13 generate
addr0 : FD
port map ( Q => ddr_adr(i), C => clk0r, D => addr(i));
ddr_ad_pad : outpad
generic map (tech => virtex4, level => sstl18_i)
port map (ddr_ad(i), ddr_adr(i));
end generate;
-- Data mask (DM) generation
dmgen : for i in 0 to dbits/8-1 generate
dq_delay : FD
port map ( Q => dm_delay(i), C => clk0r, D => dm(i));
dm0 : ODDR2
generic map (DDR_ALIGNMENT => "NONE")
port map (Q => ddr_dmr(i), C0 => clk0r, C1 => clk180r, CE => vcc,
D0 => dm(i+dbits/8), D1 => dm_delay(i), R => gnd, S => gnd);
ddr_bm_pad : outpad
generic map (tech => virtex4, level => sstl18_i)
port map (ddr_dm(i), ddr_dmr(i));
end generate;
-- Data strobe (DQS) generation
dqsgen : for i in 0 to dbits/8-1 generate
dsqreg : FD port map ( Q => dqsn(i), C => clk180r, D => oe);
da0 : ODDR2
port map ( Q => ddr_dqsin(i), C0 => clk90r, C1 => clk270r, CE => vcc,
D0 => dqsn(i), D1 => gnd, R => gnd, S => gnd);
doen : FD
port map ( Q => ddr_dqsoen(i), C => clk0r, D => dqsoen);
dqs_pad : iopad_ds
generic map (tech => virtex5, level => sstl18_ii)
port map (padp => ddr_dqs(i), padn => ddr_dqsn(i), i => ddr_dqsin(i),
en => ddr_dqsoen(i), o => ddr_dqsoutl(i));
end generate;
-- Phase shift the feedback clock and use it to latch DQ
rstphase : process (ddr_clk_fbl, rst, lockl)
begin
if rst = '0' or lockl = '0' then
dll1rst <= '1';
elsif rising_edge(ddr_clk_fbl) then
dll1rst <= '0';
end if;
end process;
bufg7 : BUFG port map (I => rclk90, O => rclk90b);
-- bufg8 : BUFG port map (I => rclk270, O => rclk270b);
rclk270b <= not rclk90b;
bufg9 : BUFG port map (I => rclk180, O => rclk180b);
read_dll : DCM
generic map (clkin_period => 8.0, DESKEW_ADJUST => "SOURCE_SYNCHRONOUS",
CLKOUT_PHASE_SHIFT => "VARIABLE", PHASE_SHIFT => rskew)
port map ( CLKIN => ddr_clk_fbl, CLKFB => rclk90b, DSSEN => gnd, PSCLK => mclk,
PSEN => cal_pll(0), PSINCDEC => cal_pll(1), RST => dll1rst, CLK0 => rclk90,
CLK90 => rclk180); --, CLK180 => rclk270);
-- Data bus
ddgen : for i in 0 to dbits-1 generate
qi : IDDR2
port map (Q0 => dqinl(i+dbits), -- 1-bit output for positive edge of C0
Q1 => dqinl(i), -- 1-bit output for negative edge of C1
C0 => rclk90b, -- 1-bit clock input
C1 => rclk270b, -- 1-bit clock input
CE => vcc, -- 1-bit clock enable input
D => ddr_dqin(i), -- 1-bit DDR data input
R => gnd, -- 1-bit reset
S => gnd); -- 1-bit set
dinq0 : FD
port map ( Q => dqin(i+dbits), C => rclk180b, D => dqinl(i));
dinq1 : FD
port map ( Q => dqin(i), C => rclk180b, D => dqinl(i+dbits));
dq_delay : FD
port map ( Q => dqout_delay(i), C => clk0r, D => dqout(i));
dout : ODDR2
generic map (DDR_ALIGNMENT => "NONE")
port map (Q => ddr_dqout(i), C0 => clk0r, C1 => clk180r, CE => vcc,
D0 => dqout(i+dbits), D1 => dqout_delay(i), R => gnd, S => gnd);
doen : FD
port map (Q => ddr_dqoen(i), C => clk0r, D => oen);
dq_pad : iopad
generic map (tech => virtex4, level => sstl18_ii)
port map (pad => ddr_dq(i), i => ddr_dqout(i), en => ddr_dqoen(i), o => ddr_dqin(i));
end generate;
end;
------------------------------------------------------------------
-- Spartan 6 DDR2 PHY -------------------------------------------
------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.DCM_SP;
use unisim.IDDR2;
use unisim.ODDR2;
use unisim.FD;
use unisim.IODELAY2;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity spartan6_ddr2_phy_wo_pads is
generic (MHz : integer := 125; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2;
clk_div : integer := 2; tech : integer := spartan6;
rskew : integer := 0; eightbanks : integer range 0 to 1 := 0;
abits : integer := 14;
nclk : integer := 3; ncs : integer := 2 );
port ( rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- DDR clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0);
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0);
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0);
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0);
addr : in std_logic_vector (abits-1 downto 0); -- row address
ba : in std_logic_vector ( 2 downto 0); -- bank address
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr output data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
cal_en : in std_logic_vector(dbits/8-1 downto 0);
cal_inc : in std_logic_vector(dbits/8-1 downto 0);
cal_rst : in std_logic;
odt : in std_logic_vector(ncs-1 downto 0));
end;
architecture rtl of spartan6_ddr2_phy_wo_pads is
component DCM_SP is
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false );
port (
CLK0 : out std_ulogic;
CLK180 : out std_ulogic;
CLK270 : out std_ulogic;
CLK2X : out std_ulogic;
CLK2X180 : out std_ulogic;
CLK90 : out std_ulogic;
CLKDV : out std_ulogic;
CLKFX : out std_ulogic;
CLKFX180 : out std_ulogic;
LOCKED : out std_ulogic;
PSDONE : out std_ulogic;
STATUS : out std_logic_vector(7 downto 0);
CLKFB : in std_ulogic;
CLKIN : in std_ulogic;
DSSEN : in std_ulogic;
PSCLK : in std_ulogic;
PSEN : in std_ulogic;
PSINCDEC : in std_ulogic;
RST : in std_ulogic );
end component;
component BUFG
port (O : out std_logic;
I : in std_logic);
end component;
component ODDR2
generic (DDR_ALIGNMENT : string := "NONE"; -- Sets output alignment to "NONE", "C0" or "C1"
INIT : bit := '0'; -- Sets initial state of the Q0
SRTYPE : string := "SYNC"); -- Specifies "SYNC" or "ASYNC" set/reset
port ( Q : out std_ulogic; -- 1-bit DDR output data
C0 : in std_ulogic; -- 1-bit clock input
C1 : in std_ulogic; -- 1-bit clock input
CE : in std_ulogic; -- 1-bit clock enable input
D0 : in std_ulogic; -- 1-bit data input (associated with C1)
D1 : in std_ulogic; -- 1-bit data input (associated with C1)
R : in std_ulogic; -- 1-bit reset input
S : in std_ulogic); -- 1-bit set input
end component;
component FD
generic (INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic);
end component;
component IDDR2
generic (DDR_ALIGNMENT : string := "NONE"; -- Sets output alignment to "NONE", "C0" or "C1"
INIT_Q0 : bit := '0'; -- Sets initial state of the Q0
INIT_Q1 : bit := '0'; -- Sets initial state of the Q1
SRTYPE : string := "SYNC"); -- Specifies "SYNC" or "ASYNC" set/reset
port ( Q0 : out std_ulogic; -- 1-bit output captured with C0 clock
Q1 : out std_ulogic; -- 1-bit output captured with C1 clock
C0 : in std_ulogic; -- 1-bit clock input
C1 : in std_ulogic; -- 1-bit clock input
CE : in std_ulogic; -- 1-bit clock enable input
D : in std_ulogic; -- 1-bit DDR data input
R : in std_ulogic; -- 1-bit reset input
S : in std_ulogic); -- 1-bit set input
end component;
component IODELAY2 is
generic (
COUNTER_WRAPAROUND : string := "WRAPAROUND";
DATA_RATE : string := "SDR";
DELAY_SRC : string := "IO";
IDELAY2_VALUE : integer := 0;
IDELAY_MODE : string := "NORMAL";
IDELAY_TYPE : string := "DEFAULT";
IDELAY_VALUE : integer := 0;
ODELAY_VALUE : integer := 0;
SERDES_MODE : string := "NONE";
SIM_TAPDELAY_VALUE : integer := 75 );
port (
BUSY : out std_ulogic;
DATAOUT : out std_ulogic;
DATAOUT2 : out std_ulogic;
DOUT : out std_ulogic;
TOUT : out std_ulogic;
CAL : in std_ulogic;
CE : in std_ulogic;
CLK : in std_ulogic;
IDATAIN : in std_ulogic;
INC : in std_ulogic;
IOCLK0 : in std_ulogic;
IOCLK1 : in std_ulogic;
ODATAIN : in std_ulogic;
RST : in std_ulogic;
T : in std_ulogic );
end component;
signal vcc, gnd, oe, lockl : std_ulogic;
signal dqsn : std_logic_vector(dbits/8-1 downto 0);
signal dqsoen_reg : std_logic_vector(dbits/8-1 downto 0);
signal ddr_dq_indel : std_logic_vector(dbits-1 downto 0);
signal ckel : std_logic_vector(ncs-1 downto 0);
signal clk_90ro : std_ulogic;
signal clk0r, clk90r, clk180r, clk270r : std_ulogic;
signal locked, vlockl, dllfb : std_ulogic;
signal dllrst : std_logic_vector(0 to 3);
signal dll0rst : std_logic_vector(0 to 3);
signal mlock, mclkfb, mclk, mclkfx, mclk0 : std_ulogic;
signal delay_cal : std_ulogic;
signal dcal_started : std_ulogic;
constant DDR_FREQ : integer := (MHz * clk_mul) / clk_div;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of dqsn : signal is true;
attribute syn_preserve of dqsn : signal is true;
attribute keep of mclkfx : signal is true;
attribute keep of clk_90ro : signal is true;
attribute syn_keep of mclkfx : signal is true;
attribute syn_keep of clk_90ro : signal is true;
-- To prevent synplify 9.4 to remove any of these registers.
attribute syn_noprune : boolean;
attribute syn_noprune of FD : component is true;
attribute syn_noprune of IDDR2 : component is true;
attribute syn_noprune of ODDR2 : component is true;
begin
oe <= not oen;
vcc <= '1'; gnd <= '0';
-- Optional DDR clock multiplication
noclkscale : if clk_mul = clk_div generate
mlock <= '1';
mclk <= clk;
-- mbufg0 : BUFG port map (I => clk, O => mclk);
end generate;
clkscale : if clk_mul /= clk_div generate
-- Extend DCM reset signal.
dll0rstdel : process (clk, rst)
begin
if rst = '0' then
dll0rst <= (others => '1');
elsif rising_edge(clk) then
dll0rst <= dll0rst(1 to 3) & "0";
end if;
end process;
bufg0 : BUFG port map (I => mclkfx, O => mclk);
bufg1 : BUFG port map (I => mclk0, O => mclkfb);
dllm : DCM_SP
generic map (
CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div,
CLK_FEEDBACK => "1X", CLKIN_PERIOD => 1000.0/real(MHz) )
port map (CLKIN => clk, CLKFB => mclkfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst(0), CLK0 => mclk0,
LOCKED => mlock, CLKFX => mclkfx );
end generate;
-- DDR clock generation (90 degrees phase-shifted DLL)
bufg2 : BUFG port map (I => clk_90ro, O => clk90r);
dllfb <= clk90r;
dll : DCM_SP
generic map ( CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2,
CLKOUT_PHASE_SHIFT => "FIXED", PHASE_SHIFT => 64 )
port map (CLKIN => mclk, CLKFB => dllfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst(0), CLK0 => clk_90ro,
CLK90 => open, CLK180 => open, CLK270 => open,
LOCKED => lockl);
clk0r <= mclk;
clk180r <= not mclk;
clk270r <= not clk90r;
clkout <= mclk;
-- Extend DCM reset signal.
dllrstdel : process (mclk, rst, mlock)
begin
if rst = '0' or mlock = '0' then
dllrst <= (others => '1');
elsif rising_edge(mclk) then
dllrst <= dllrst(1 to 3) & "0";
end if;
end process;
-- Delay lock signal.
rdel : if rstdelay /= 0 generate
rcnt : process (clk0r)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*DDR_FREQ, 16);
vlock := '0';
elsif vlock = '0' then
cnt := cnt -1;
vlock := cnt(15) and not co;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
-- Generate external DDR clock
ddrclocks : for i in 0 to nclk-1 generate
dclk0r : ODDR2
port map ( Q => ddr_clk(i), C0 => clk90r, C1 => clk270r, CE => vcc,
D0 => vcc, D1 => gnd, R => gnd, S => gnd );
end generate;
-- DDR single-edge control signals
ddrbanks : for i in 0 to ncs-1 generate
ddr_odt(i) <= locked and odt(i);
csn0gen : ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => ddr_csb(i), C0 => clk0r, C1 => clk180r, CE => vcc,
D0 => csn(i), D1 => csn(i), R => gnd, S => gnd );
ckel(i) <= cke(i) and locked;
ckegen : ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => ddr_cke(i), C0 => clk0r, C1 => clk180r, CE => vcc,
D0 => ckel(i), D1 => ckel(i), R => gnd, S => gnd );
end generate;
rasgen : ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => ddr_rasb, C0 => clk0r, C1 => clk180r, CE => vcc,
D0 => rasn, D1 => rasn, R => gnd, S => gnd );
casgen : ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => ddr_casb, C0 => clk0r, C1 => clk180r, CE => vcc,
D0 => casn, D1 => casn, R => gnd, S => gnd );
wengen : ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => ddr_web, C0 => clk0r, C1 => clk180r, CE => vcc,
D0 => wen, D1 => wen, R => gnd, S => gnd );
bagen : for i in 0 to 1+eightbanks generate
ba0 : ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => ddr_ba(i), C0 => clk0r, C1 => clk180r, CE => vcc,
D0 => ba(i), D1 => ba(i), R => gnd, S => gnd );
end generate;
addrgen : for i in 0 to abits-1 generate
addr0 : ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => ddr_ad(i), C0 => clk0r, C1 => clk180r, CE => vcc,
D0 => addr(i), D1 => addr(i), R => gnd, S => gnd );
end generate;
-- Data mask (DM) generation
dmgen : for i in 0 to dbits/8-1 generate
dmgen0 : ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => ddr_dm(i), C0 => clk0r, C1 => clk180r, CE => vcc,
D0 => dm(i+dbits/8), D1 => dm(i), R => gnd, S => gnd );
end generate;
-- Data strobe (DQS) generation
dqsgen : for i in 0 to dbits/8-1 generate
dqsreg : FD
port map ( Q => dqsn(i), C => clk180r, D => oe );
dqsgen0 : ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => ddr_dqs_out(i), C0 => clk90r, C1 => clk270r, CE => vcc,
D0 => dqsn(i), D1 => gnd, R => gnd, S => gnd );
doenreg : FD
port map ( Q => dqsoen_reg(i), C => clk180r, D => dqsoen );
doen0 : ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => ddr_dqs_oen(i), C0 => clk90r, C1 => clk270r, CE => vcc,
D0 => dqsoen_reg(i), D1 => dqsoen_reg(i), R => gnd, S => gnd );
end generate;
-- Data bus
ddgen : for i in 0 to dbits-1 generate
dqdelay : IODELAY2
generic map ( DATA_RATE => "DDR", DELAY_SRC => "IDATAIN",
IDELAY_TYPE => "VARIABLE_FROM_ZERO" )
port map ( BUSY => open, CAL => delay_cal, CE => cal_en(i/8), CLK => clk0r,
DATAOUT => ddr_dq_indel(i), DATAOUT2 => open, DOUT => open,
IDATAIN => ddr_dq_in(i), INC => cal_inc(i/8),
IOCLK0 => clk0r, IOCLK1 => clk180r,
ODATAIN => gnd, RST => cal_rst, T => vcc, TOUT => open );
din : IDDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( D => ddr_dq_indel(i), C0 => clk0r, C1 => clk180r, CE => vcc,
R => gnd, S => gnd, Q0 => dqin(i), Q1 => dqin(i+dbits) );
dout : ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => ddr_dq_out(i), C0 => clk0r, C1 => clk180r, CE => vcc,
D0 => dqout(i+dbits), D1 => dqout(i), R => gnd, S => gnd );
doen : ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => ddr_dq_oen(i), C0 => clk0r, C1 => clk180r, CE => vcc,
D0 => oen, D1 => oen, R => gnd, S => gnd );
end generate;
-- Generate IODELAY calibration command after core reset.
calcmd : process (mclk, rst)
begin
if rst = '0' then
dcal_started <= '0';
delay_cal <= '0';
elsif rising_edge(mclk) then
if mlock = '1' then
dcal_started <= '1';
delay_cal <= not dcal_started;
end if;
end if;
end process;
end architecture;
| gpl-2.0 | 6b52ec863fcb781857970fc0167df9e1 | 0.547069 | 3.327762 | false | false | false | false |
thinkoco/de1_soc_opencl | de10_standard_sharedonly_vga/system/system_inst.vhd | 1 | 20,729 | component system is
port (
clk_50_clk : in std_logic := 'X'; -- clk
kernel_clk_clk : out std_logic; -- clk
memory_mem_a : out std_logic_vector(14 downto 0); -- mem_a
memory_mem_ba : out std_logic_vector(2 downto 0); -- mem_ba
memory_mem_ck : out std_logic; -- mem_ck
memory_mem_ck_n : out std_logic; -- mem_ck_n
memory_mem_cke : out std_logic; -- mem_cke
memory_mem_cs_n : out std_logic; -- mem_cs_n
memory_mem_ras_n : out std_logic; -- mem_ras_n
memory_mem_cas_n : out std_logic; -- mem_cas_n
memory_mem_we_n : out std_logic; -- mem_we_n
memory_mem_reset_n : out std_logic; -- mem_reset_n
memory_mem_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- mem_dq
memory_mem_dqs : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs
memory_mem_dqs_n : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_n
memory_mem_odt : out std_logic; -- mem_odt
memory_mem_dm : out std_logic_vector(3 downto 0); -- mem_dm
memory_oct_rzqin : in std_logic := 'X'; -- oct_rzqin
peripheral_hps_io_emac1_inst_TX_CLK : out std_logic; -- hps_io_emac1_inst_TX_CLK
peripheral_hps_io_emac1_inst_TXD0 : out std_logic; -- hps_io_emac1_inst_TXD0
peripheral_hps_io_emac1_inst_TXD1 : out std_logic; -- hps_io_emac1_inst_TXD1
peripheral_hps_io_emac1_inst_TXD2 : out std_logic; -- hps_io_emac1_inst_TXD2
peripheral_hps_io_emac1_inst_TXD3 : out std_logic; -- hps_io_emac1_inst_TXD3
peripheral_hps_io_emac1_inst_RXD0 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD0
peripheral_hps_io_emac1_inst_MDIO : inout std_logic := 'X'; -- hps_io_emac1_inst_MDIO
peripheral_hps_io_emac1_inst_MDC : out std_logic; -- hps_io_emac1_inst_MDC
peripheral_hps_io_emac1_inst_RX_CTL : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CTL
peripheral_hps_io_emac1_inst_TX_CTL : out std_logic; -- hps_io_emac1_inst_TX_CTL
peripheral_hps_io_emac1_inst_RX_CLK : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CLK
peripheral_hps_io_emac1_inst_RXD1 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD1
peripheral_hps_io_emac1_inst_RXD2 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD2
peripheral_hps_io_emac1_inst_RXD3 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD3
peripheral_hps_io_sdio_inst_CMD : inout std_logic := 'X'; -- hps_io_sdio_inst_CMD
peripheral_hps_io_sdio_inst_D0 : inout std_logic := 'X'; -- hps_io_sdio_inst_D0
peripheral_hps_io_sdio_inst_D1 : inout std_logic := 'X'; -- hps_io_sdio_inst_D1
peripheral_hps_io_sdio_inst_CLK : out std_logic; -- hps_io_sdio_inst_CLK
peripheral_hps_io_sdio_inst_D2 : inout std_logic := 'X'; -- hps_io_sdio_inst_D2
peripheral_hps_io_sdio_inst_D3 : inout std_logic := 'X'; -- hps_io_sdio_inst_D3
peripheral_hps_io_usb1_inst_D0 : inout std_logic := 'X'; -- hps_io_usb1_inst_D0
peripheral_hps_io_usb1_inst_D1 : inout std_logic := 'X'; -- hps_io_usb1_inst_D1
peripheral_hps_io_usb1_inst_D2 : inout std_logic := 'X'; -- hps_io_usb1_inst_D2
peripheral_hps_io_usb1_inst_D3 : inout std_logic := 'X'; -- hps_io_usb1_inst_D3
peripheral_hps_io_usb1_inst_D4 : inout std_logic := 'X'; -- hps_io_usb1_inst_D4
peripheral_hps_io_usb1_inst_D5 : inout std_logic := 'X'; -- hps_io_usb1_inst_D5
peripheral_hps_io_usb1_inst_D6 : inout std_logic := 'X'; -- hps_io_usb1_inst_D6
peripheral_hps_io_usb1_inst_D7 : inout std_logic := 'X'; -- hps_io_usb1_inst_D7
peripheral_hps_io_usb1_inst_CLK : in std_logic := 'X'; -- hps_io_usb1_inst_CLK
peripheral_hps_io_usb1_inst_STP : out std_logic; -- hps_io_usb1_inst_STP
peripheral_hps_io_usb1_inst_DIR : in std_logic := 'X'; -- hps_io_usb1_inst_DIR
peripheral_hps_io_usb1_inst_NXT : in std_logic := 'X'; -- hps_io_usb1_inst_NXT
peripheral_hps_io_uart0_inst_RX : in std_logic := 'X'; -- hps_io_uart0_inst_RX
peripheral_hps_io_uart0_inst_TX : out std_logic; -- hps_io_uart0_inst_TX
peripheral_hps_io_i2c1_inst_SDA : inout std_logic := 'X'; -- hps_io_i2c1_inst_SDA
peripheral_hps_io_i2c1_inst_SCL : inout std_logic := 'X'; -- hps_io_i2c1_inst_SCL
peripheral_hps_io_gpio_inst_GPIO53 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO53
reset_50_reset_n : in std_logic := 'X'; -- reset_n
acl_iface_clock_130_clk : in std_logic := 'X'; -- clk
acl_iface_alt_vip_itc_0_clocked_video_vid_clk : in std_logic := 'X'; -- vid_clk
acl_iface_alt_vip_itc_0_clocked_video_vid_data : out std_logic_vector(31 downto 0); -- vid_data
acl_iface_alt_vip_itc_0_clocked_video_underflow : out std_logic; -- underflow
acl_iface_alt_vip_itc_0_clocked_video_vid_datavalid : out std_logic; -- vid_datavalid
acl_iface_alt_vip_itc_0_clocked_video_vid_v_sync : out std_logic; -- vid_v_sync
acl_iface_alt_vip_itc_0_clocked_video_vid_h_sync : out std_logic; -- vid_h_sync
acl_iface_alt_vip_itc_0_clocked_video_vid_f : out std_logic; -- vid_f
acl_iface_alt_vip_itc_0_clocked_video_vid_h : out std_logic; -- vid_h
acl_iface_alt_vip_itc_0_clocked_video_vid_v : out std_logic -- vid_v
);
end component system;
u0 : component system
port map (
clk_50_clk => CONNECTED_TO_clk_50_clk, -- clk_50.clk
kernel_clk_clk => CONNECTED_TO_kernel_clk_clk, -- kernel_clk.clk
memory_mem_a => CONNECTED_TO_memory_mem_a, -- memory.mem_a
memory_mem_ba => CONNECTED_TO_memory_mem_ba, -- .mem_ba
memory_mem_ck => CONNECTED_TO_memory_mem_ck, -- .mem_ck
memory_mem_ck_n => CONNECTED_TO_memory_mem_ck_n, -- .mem_ck_n
memory_mem_cke => CONNECTED_TO_memory_mem_cke, -- .mem_cke
memory_mem_cs_n => CONNECTED_TO_memory_mem_cs_n, -- .mem_cs_n
memory_mem_ras_n => CONNECTED_TO_memory_mem_ras_n, -- .mem_ras_n
memory_mem_cas_n => CONNECTED_TO_memory_mem_cas_n, -- .mem_cas_n
memory_mem_we_n => CONNECTED_TO_memory_mem_we_n, -- .mem_we_n
memory_mem_reset_n => CONNECTED_TO_memory_mem_reset_n, -- .mem_reset_n
memory_mem_dq => CONNECTED_TO_memory_mem_dq, -- .mem_dq
memory_mem_dqs => CONNECTED_TO_memory_mem_dqs, -- .mem_dqs
memory_mem_dqs_n => CONNECTED_TO_memory_mem_dqs_n, -- .mem_dqs_n
memory_mem_odt => CONNECTED_TO_memory_mem_odt, -- .mem_odt
memory_mem_dm => CONNECTED_TO_memory_mem_dm, -- .mem_dm
memory_oct_rzqin => CONNECTED_TO_memory_oct_rzqin, -- .oct_rzqin
peripheral_hps_io_emac1_inst_TX_CLK => CONNECTED_TO_peripheral_hps_io_emac1_inst_TX_CLK, -- peripheral.hps_io_emac1_inst_TX_CLK
peripheral_hps_io_emac1_inst_TXD0 => CONNECTED_TO_peripheral_hps_io_emac1_inst_TXD0, -- .hps_io_emac1_inst_TXD0
peripheral_hps_io_emac1_inst_TXD1 => CONNECTED_TO_peripheral_hps_io_emac1_inst_TXD1, -- .hps_io_emac1_inst_TXD1
peripheral_hps_io_emac1_inst_TXD2 => CONNECTED_TO_peripheral_hps_io_emac1_inst_TXD2, -- .hps_io_emac1_inst_TXD2
peripheral_hps_io_emac1_inst_TXD3 => CONNECTED_TO_peripheral_hps_io_emac1_inst_TXD3, -- .hps_io_emac1_inst_TXD3
peripheral_hps_io_emac1_inst_RXD0 => CONNECTED_TO_peripheral_hps_io_emac1_inst_RXD0, -- .hps_io_emac1_inst_RXD0
peripheral_hps_io_emac1_inst_MDIO => CONNECTED_TO_peripheral_hps_io_emac1_inst_MDIO, -- .hps_io_emac1_inst_MDIO
peripheral_hps_io_emac1_inst_MDC => CONNECTED_TO_peripheral_hps_io_emac1_inst_MDC, -- .hps_io_emac1_inst_MDC
peripheral_hps_io_emac1_inst_RX_CTL => CONNECTED_TO_peripheral_hps_io_emac1_inst_RX_CTL, -- .hps_io_emac1_inst_RX_CTL
peripheral_hps_io_emac1_inst_TX_CTL => CONNECTED_TO_peripheral_hps_io_emac1_inst_TX_CTL, -- .hps_io_emac1_inst_TX_CTL
peripheral_hps_io_emac1_inst_RX_CLK => CONNECTED_TO_peripheral_hps_io_emac1_inst_RX_CLK, -- .hps_io_emac1_inst_RX_CLK
peripheral_hps_io_emac1_inst_RXD1 => CONNECTED_TO_peripheral_hps_io_emac1_inst_RXD1, -- .hps_io_emac1_inst_RXD1
peripheral_hps_io_emac1_inst_RXD2 => CONNECTED_TO_peripheral_hps_io_emac1_inst_RXD2, -- .hps_io_emac1_inst_RXD2
peripheral_hps_io_emac1_inst_RXD3 => CONNECTED_TO_peripheral_hps_io_emac1_inst_RXD3, -- .hps_io_emac1_inst_RXD3
peripheral_hps_io_sdio_inst_CMD => CONNECTED_TO_peripheral_hps_io_sdio_inst_CMD, -- .hps_io_sdio_inst_CMD
peripheral_hps_io_sdio_inst_D0 => CONNECTED_TO_peripheral_hps_io_sdio_inst_D0, -- .hps_io_sdio_inst_D0
peripheral_hps_io_sdio_inst_D1 => CONNECTED_TO_peripheral_hps_io_sdio_inst_D1, -- .hps_io_sdio_inst_D1
peripheral_hps_io_sdio_inst_CLK => CONNECTED_TO_peripheral_hps_io_sdio_inst_CLK, -- .hps_io_sdio_inst_CLK
peripheral_hps_io_sdio_inst_D2 => CONNECTED_TO_peripheral_hps_io_sdio_inst_D2, -- .hps_io_sdio_inst_D2
peripheral_hps_io_sdio_inst_D3 => CONNECTED_TO_peripheral_hps_io_sdio_inst_D3, -- .hps_io_sdio_inst_D3
peripheral_hps_io_usb1_inst_D0 => CONNECTED_TO_peripheral_hps_io_usb1_inst_D0, -- .hps_io_usb1_inst_D0
peripheral_hps_io_usb1_inst_D1 => CONNECTED_TO_peripheral_hps_io_usb1_inst_D1, -- .hps_io_usb1_inst_D1
peripheral_hps_io_usb1_inst_D2 => CONNECTED_TO_peripheral_hps_io_usb1_inst_D2, -- .hps_io_usb1_inst_D2
peripheral_hps_io_usb1_inst_D3 => CONNECTED_TO_peripheral_hps_io_usb1_inst_D3, -- .hps_io_usb1_inst_D3
peripheral_hps_io_usb1_inst_D4 => CONNECTED_TO_peripheral_hps_io_usb1_inst_D4, -- .hps_io_usb1_inst_D4
peripheral_hps_io_usb1_inst_D5 => CONNECTED_TO_peripheral_hps_io_usb1_inst_D5, -- .hps_io_usb1_inst_D5
peripheral_hps_io_usb1_inst_D6 => CONNECTED_TO_peripheral_hps_io_usb1_inst_D6, -- .hps_io_usb1_inst_D6
peripheral_hps_io_usb1_inst_D7 => CONNECTED_TO_peripheral_hps_io_usb1_inst_D7, -- .hps_io_usb1_inst_D7
peripheral_hps_io_usb1_inst_CLK => CONNECTED_TO_peripheral_hps_io_usb1_inst_CLK, -- .hps_io_usb1_inst_CLK
peripheral_hps_io_usb1_inst_STP => CONNECTED_TO_peripheral_hps_io_usb1_inst_STP, -- .hps_io_usb1_inst_STP
peripheral_hps_io_usb1_inst_DIR => CONNECTED_TO_peripheral_hps_io_usb1_inst_DIR, -- .hps_io_usb1_inst_DIR
peripheral_hps_io_usb1_inst_NXT => CONNECTED_TO_peripheral_hps_io_usb1_inst_NXT, -- .hps_io_usb1_inst_NXT
peripheral_hps_io_uart0_inst_RX => CONNECTED_TO_peripheral_hps_io_uart0_inst_RX, -- .hps_io_uart0_inst_RX
peripheral_hps_io_uart0_inst_TX => CONNECTED_TO_peripheral_hps_io_uart0_inst_TX, -- .hps_io_uart0_inst_TX
peripheral_hps_io_i2c1_inst_SDA => CONNECTED_TO_peripheral_hps_io_i2c1_inst_SDA, -- .hps_io_i2c1_inst_SDA
peripheral_hps_io_i2c1_inst_SCL => CONNECTED_TO_peripheral_hps_io_i2c1_inst_SCL, -- .hps_io_i2c1_inst_SCL
peripheral_hps_io_gpio_inst_GPIO53 => CONNECTED_TO_peripheral_hps_io_gpio_inst_GPIO53, -- .hps_io_gpio_inst_GPIO53
reset_50_reset_n => CONNECTED_TO_reset_50_reset_n, -- reset_50.reset_n
acl_iface_clock_130_clk => CONNECTED_TO_acl_iface_clock_130_clk, -- acl_iface_clock_130.clk
acl_iface_alt_vip_itc_0_clocked_video_vid_clk => CONNECTED_TO_acl_iface_alt_vip_itc_0_clocked_video_vid_clk, -- acl_iface_alt_vip_itc_0_clocked_video.vid_clk
acl_iface_alt_vip_itc_0_clocked_video_vid_data => CONNECTED_TO_acl_iface_alt_vip_itc_0_clocked_video_vid_data, -- .vid_data
acl_iface_alt_vip_itc_0_clocked_video_underflow => CONNECTED_TO_acl_iface_alt_vip_itc_0_clocked_video_underflow, -- .underflow
acl_iface_alt_vip_itc_0_clocked_video_vid_datavalid => CONNECTED_TO_acl_iface_alt_vip_itc_0_clocked_video_vid_datavalid, -- .vid_datavalid
acl_iface_alt_vip_itc_0_clocked_video_vid_v_sync => CONNECTED_TO_acl_iface_alt_vip_itc_0_clocked_video_vid_v_sync, -- .vid_v_sync
acl_iface_alt_vip_itc_0_clocked_video_vid_h_sync => CONNECTED_TO_acl_iface_alt_vip_itc_0_clocked_video_vid_h_sync, -- .vid_h_sync
acl_iface_alt_vip_itc_0_clocked_video_vid_f => CONNECTED_TO_acl_iface_alt_vip_itc_0_clocked_video_vid_f, -- .vid_f
acl_iface_alt_vip_itc_0_clocked_video_vid_h => CONNECTED_TO_acl_iface_alt_vip_itc_0_clocked_video_vid_h, -- .vid_h
acl_iface_alt_vip_itc_0_clocked_video_vid_v => CONNECTED_TO_acl_iface_alt_vip_itc_0_clocked_video_vid_v -- .vid_v
);
| apache-2.0 | aa8e65967dff7c31655d4a16da01f6f5 | 0.387911 | 4.021145 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-digilent-xup/testbench.vhd | 1 | 8,879 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 10; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 18; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal sys_clk : std_logic := '0';
signal sysace_clk : std_logic := '0';
signal sys_rst_in : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal errorn : std_logic;
signal address : std_logic_vector(27 downto 0);
signal data : std_logic_vector(15 downto 0);
signal xdata : std_logic_vector(31 downto 0);
signal romsn : std_logic;
signal iosn : std_ulogic;
signal writen, read : std_ulogic;
signal oen : std_ulogic;
signal flash_rstn : std_logic;
signal ddr_clk : std_logic_vector(2 downto 0);
signal ddr_clkb : std_logic_vector(2 downto 0);
signal ddr_clk_fb : std_logic;
signal ddr_clk_fb_out : std_logic;
signal ddr_cke : std_logic_vector(1 downto 0);
signal ddr_csb : std_logic_vector(1 downto 0);
signal ddr_web : std_ulogic; -- ddr write enable
signal ddr_rasb : std_ulogic; -- ddr ras
signal ddr_casb : std_ulogic; -- ddr cas
signal ddr_dm : std_logic_vector (7 downto 0); -- ddr dm
signal ddr_dqs : std_logic_vector (7 downto 0); -- ddr dqs
signal ddr_ad : std_logic_vector (13 downto 0); -- ddr address
signal ddr_ba : std_logic_vector (1 downto 0); -- ddr bank address
signal ddr_dq : std_logic_vector (63 downto 0); -- ddr data
signal txd1 : std_logic; -- UART1 tx data
signal rxd1 : std_logic; -- UART1 rx data
signal gpio : std_logic_vector(31 downto 0); -- I/O port
signal flash_cex : std_logic;
signal etx_clk, erx_clk, erx_dv, erx_er, erx_col, erx_crs, etx_en, etx_er : std_logic:='0';
signal erxd, etxd: std_logic_vector(3 downto 0):=(others=>'0');
signal emdc, emdio, eresetn : std_logic;
signal etx_slew : std_logic_vector(1 downto 0);
signal leds : std_logic_vector(1 downto 0);
signal vid_clock : std_ulogic;
signal vid_blankn : std_ulogic;
signal vid_syncn : std_ulogic;
signal vid_hsync : std_ulogic;
signal vid_vsync : std_ulogic;
signal vid_r : std_logic_vector(7 downto 0);
signal vid_g : std_logic_vector(7 downto 0);
signal vid_b : std_logic_vector(7 downto 0);
signal ps2clk : std_logic_vector(1 downto 0);
signal ps2data : std_logic_vector(1 downto 0);
signal cf_mpa : std_logic_vector(6 downto 0);
signal cf_mpd : std_logic_vector(15 downto 0);
signal cf_mp_ce_z : std_ulogic;
signal cf_mp_oe_z : std_ulogic;
signal cf_mp_we_z : std_ulogic;
signal cf_mpirq : std_ulogic;
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
constant lresp : boolean := false;
signal dsuen : std_ulogic;
signal dsubre : std_ulogic;
signal dsuact : std_ulogic;
begin
-- clock and reset
sys_clk <= not sys_clk after ct * 1 ns;
sysace_clk <= not sysace_clk after 15 ns;
sys_rst_in <= '0', '1' after 200 ns;
rxd1 <= 'H'; errorn <= 'H'; dsuen <= '0'; dsubre <= 'H';
ddr_clk_fb <= ddr_clk_fb_out; rxd1 <= txd1;
cf_mpd <= (others => 'H'); cf_mpirq <= 'L';
cpu : entity work.leon3mp
generic map ( fabtech, memtech, padtech, ncpu, disas, dbguart, pclow )
port map ( sys_rst_in, sys_clk, sysace_clk, errorn, dsuen, dsubre, dsuact,
ddr_clk, ddr_clkb, ddr_clk_fb, ddr_clk_fb_out, ddr_cke, ddr_csb,
ddr_web, ddr_rasb, ddr_casb, ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
rxd1, txd1, leds(0), leds(1),
-- gpio,
emdio, etx_clk, erx_clk, erxd, erx_dv, erx_er, erx_col, erx_crs,
etxd, etx_en, etx_er, emdc, eresetn, etx_slew, ps2clk, ps2data,
vid_clock, vid_blankn, vid_syncn, vid_hsync, vid_vsync,
vid_r, vid_g, vid_b,
cf_mpa, cf_mpd, cf_mp_ce_z, cf_mp_oe_z, cf_mp_we_z, cf_mpirq
);
ddrmem : for i in 0 to 1 generate
-- u3 : mt46v16m16
-- generic map (index => 3, fname => sdramfile, bbits => 64)
-- PORT MAP(
-- Dq => ddr_dq(15 downto 0), Dqs => ddr_dqs(1 downto 0), Addr => ddr_ad(12 downto 0),
-- Ba => ddr_ba, Clk => ddr_clk(i), Clk_n => ddr_clkb(i), Cke => ddr_cke(i),
-- Cs_n => ddr_csb(i), Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
-- Dm => ddr_dm(1 downto 0));
-- u2 : mt46v16m16
-- generic map (index => 2, fname => sdramfile, bbits => 64)
-- PORT MAP(
-- Dq => ddr_dq(31 downto 16), Dqs => ddr_dqs(3 downto 2), Addr => ddr_ad(12 downto 0),
-- Ba => ddr_ba, Clk => ddr_clk(i), Clk_n => ddr_clkb(i), Cke => ddr_cke(i),
-- Cs_n => ddr_csb(i), Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
-- Dm => ddr_dm(3 downto 2));
-- u1 : mt46v16m16
-- generic map (index => 1, fname => sdramfile, bbits => 64)
-- PORT MAP(
-- Dq => ddr_dq(47 downto 32), Dqs => ddr_dqs(5 downto 4), Addr => ddr_ad(12 downto 0),
-- Ba => ddr_ba, Clk => ddr_clk(i), Clk_n => ddr_clkb(i), Cke => ddr_cke(i),
-- Cs_n => ddr_csb(i), Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
-- Dm => ddr_dm(5 downto 4));
-- u0 : mt46v16m16
-- generic map (index => 0, fname => sdramfile, bbits => 64)
-- PORT MAP(
-- Dq => ddr_dq(63 downto 48), Dqs => ddr_dqs(7 downto 6), Addr => ddr_ad(12 downto 0),
-- Ba => ddr_ba, Clk => ddr_clk(i), Clk_n => ddr_clkb(i), Cke => ddr_cke(i),
-- Cs_n => ddr_csb(i), Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
-- Dm => ddr_dm(7 downto 6));
ddr0 : ddrram
generic map(width => 64, abits => 14, colbits => 9, rowbits => 14,
implbanks => 1, fname => sdramfile, speedbin => 1, density => 1)
port map (ck => ddr_clk(i), cke => ddr_cke(i), csn => ddr_csb(i),
rasn => ddr_rasb, casn => ddr_casb, wen => ddr_web,
dm => ddr_dm, ba => ddr_ba, a => ddr_ad, dq => ddr_dq,
dqs => ddr_dqs);
end generate;
prom0 : sram16 generic map (index => 4, abits => romdepth, fname => promfile)
port map (address(romdepth-1 downto 0), data,
gnd, gnd, romsn, writen, oen);
iuerr : process
begin
wait for 5000 ns;
if to_x01(errorn) = '1' then wait on errorn; end if;
assert (to_x01(errorn) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
xdata <= "0000000000000000" & data;
test0 : grtestmod
port map ( sys_rst_in, sys_clk, errorn, address(20 downto 1), xdata,
iosn, oen, writen, open);
data <= buskeep(data), (others => 'H') after 250 ns;
ddr_dq <= buskeep(ddr_dq), (others => 'H') after 250 ns;
end ;
| gpl-2.0 | a592498194e5c8ace3217d2184dd8755 | 0.593085 | 3.155295 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_1/embedded_lab_1.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_processing_system7_0_2/zynq_design_1_processing_system7_0_2_sim_netlist.vhdl | 1 | 197,246 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Tue Sep 19 00:29:49 2017
-- Host : DarkCube running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/embedded_lab_1/embedded_lab_1.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_processing_system7_0_2/zynq_design_1_processing_system7_0_2_sim_netlist.vhdl
-- Design : zynq_design_1_processing_system7_0_2
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 is
port (
CAN0_PHY_TX : out STD_LOGIC;
CAN0_PHY_RX : in STD_LOGIC;
CAN1_PHY_TX : out STD_LOGIC;
CAN1_PHY_RX : in STD_LOGIC;
ENET0_GMII_TX_EN : out STD_LOGIC;
ENET0_GMII_TX_ER : out STD_LOGIC;
ENET0_MDIO_MDC : out STD_LOGIC;
ENET0_MDIO_O : out STD_LOGIC;
ENET0_MDIO_T : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET0_SOF_RX : out STD_LOGIC;
ENET0_SOF_TX : out STD_LOGIC;
ENET0_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ENET0_GMII_COL : in STD_LOGIC;
ENET0_GMII_CRS : in STD_LOGIC;
ENET0_GMII_RX_CLK : in STD_LOGIC;
ENET0_GMII_RX_DV : in STD_LOGIC;
ENET0_GMII_RX_ER : in STD_LOGIC;
ENET0_GMII_TX_CLK : in STD_LOGIC;
ENET0_MDIO_I : in STD_LOGIC;
ENET0_EXT_INTIN : in STD_LOGIC;
ENET0_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
ENET1_GMII_TX_EN : out STD_LOGIC;
ENET1_GMII_TX_ER : out STD_LOGIC;
ENET1_MDIO_MDC : out STD_LOGIC;
ENET1_MDIO_O : out STD_LOGIC;
ENET1_MDIO_T : out STD_LOGIC;
ENET1_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET1_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET1_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET1_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET1_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET1_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET1_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET1_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET1_SOF_RX : out STD_LOGIC;
ENET1_SOF_TX : out STD_LOGIC;
ENET1_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ENET1_GMII_COL : in STD_LOGIC;
ENET1_GMII_CRS : in STD_LOGIC;
ENET1_GMII_RX_CLK : in STD_LOGIC;
ENET1_GMII_RX_DV : in STD_LOGIC;
ENET1_GMII_RX_ER : in STD_LOGIC;
ENET1_GMII_TX_CLK : in STD_LOGIC;
ENET1_MDIO_I : in STD_LOGIC;
ENET1_EXT_INTIN : in STD_LOGIC;
ENET1_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
GPIO_I : in STD_LOGIC_VECTOR ( 63 downto 0 );
GPIO_O : out STD_LOGIC_VECTOR ( 63 downto 0 );
GPIO_T : out STD_LOGIC_VECTOR ( 63 downto 0 );
I2C0_SDA_I : in STD_LOGIC;
I2C0_SDA_O : out STD_LOGIC;
I2C0_SDA_T : out STD_LOGIC;
I2C0_SCL_I : in STD_LOGIC;
I2C0_SCL_O : out STD_LOGIC;
I2C0_SCL_T : out STD_LOGIC;
I2C1_SDA_I : in STD_LOGIC;
I2C1_SDA_O : out STD_LOGIC;
I2C1_SDA_T : out STD_LOGIC;
I2C1_SCL_I : in STD_LOGIC;
I2C1_SCL_O : out STD_LOGIC;
I2C1_SCL_T : out STD_LOGIC;
PJTAG_TCK : in STD_LOGIC;
PJTAG_TMS : in STD_LOGIC;
PJTAG_TDI : in STD_LOGIC;
PJTAG_TDO : out STD_LOGIC;
SDIO0_CLK : out STD_LOGIC;
SDIO0_CLK_FB : in STD_LOGIC;
SDIO0_CMD_O : out STD_LOGIC;
SDIO0_CMD_I : in STD_LOGIC;
SDIO0_CMD_T : out STD_LOGIC;
SDIO0_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_LED : out STD_LOGIC;
SDIO0_CDN : in STD_LOGIC;
SDIO0_WP : in STD_LOGIC;
SDIO0_BUSPOW : out STD_LOGIC;
SDIO0_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 );
SDIO1_CLK : out STD_LOGIC;
SDIO1_CLK_FB : in STD_LOGIC;
SDIO1_CMD_O : out STD_LOGIC;
SDIO1_CMD_I : in STD_LOGIC;
SDIO1_CMD_T : out STD_LOGIC;
SDIO1_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_LED : out STD_LOGIC;
SDIO1_CDN : in STD_LOGIC;
SDIO1_WP : in STD_LOGIC;
SDIO1_BUSPOW : out STD_LOGIC;
SDIO1_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 );
SPI0_SCLK_I : in STD_LOGIC;
SPI0_SCLK_O : out STD_LOGIC;
SPI0_SCLK_T : out STD_LOGIC;
SPI0_MOSI_I : in STD_LOGIC;
SPI0_MOSI_O : out STD_LOGIC;
SPI0_MOSI_T : out STD_LOGIC;
SPI0_MISO_I : in STD_LOGIC;
SPI0_MISO_O : out STD_LOGIC;
SPI0_MISO_T : out STD_LOGIC;
SPI0_SS_I : in STD_LOGIC;
SPI0_SS_O : out STD_LOGIC;
SPI0_SS1_O : out STD_LOGIC;
SPI0_SS2_O : out STD_LOGIC;
SPI0_SS_T : out STD_LOGIC;
SPI1_SCLK_I : in STD_LOGIC;
SPI1_SCLK_O : out STD_LOGIC;
SPI1_SCLK_T : out STD_LOGIC;
SPI1_MOSI_I : in STD_LOGIC;
SPI1_MOSI_O : out STD_LOGIC;
SPI1_MOSI_T : out STD_LOGIC;
SPI1_MISO_I : in STD_LOGIC;
SPI1_MISO_O : out STD_LOGIC;
SPI1_MISO_T : out STD_LOGIC;
SPI1_SS_I : in STD_LOGIC;
SPI1_SS_O : out STD_LOGIC;
SPI1_SS1_O : out STD_LOGIC;
SPI1_SS2_O : out STD_LOGIC;
SPI1_SS_T : out STD_LOGIC;
UART0_DTRN : out STD_LOGIC;
UART0_RTSN : out STD_LOGIC;
UART0_TX : out STD_LOGIC;
UART0_CTSN : in STD_LOGIC;
UART0_DCDN : in STD_LOGIC;
UART0_DSRN : in STD_LOGIC;
UART0_RIN : in STD_LOGIC;
UART0_RX : in STD_LOGIC;
UART1_DTRN : out STD_LOGIC;
UART1_RTSN : out STD_LOGIC;
UART1_TX : out STD_LOGIC;
UART1_CTSN : in STD_LOGIC;
UART1_DCDN : in STD_LOGIC;
UART1_DSRN : in STD_LOGIC;
UART1_RIN : in STD_LOGIC;
UART1_RX : in STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
TTC0_CLK0_IN : in STD_LOGIC;
TTC0_CLK1_IN : in STD_LOGIC;
TTC0_CLK2_IN : in STD_LOGIC;
TTC1_WAVE0_OUT : out STD_LOGIC;
TTC1_WAVE1_OUT : out STD_LOGIC;
TTC1_WAVE2_OUT : out STD_LOGIC;
TTC1_CLK0_IN : in STD_LOGIC;
TTC1_CLK1_IN : in STD_LOGIC;
TTC1_CLK2_IN : in STD_LOGIC;
WDT_CLK_IN : in STD_LOGIC;
WDT_RST_OUT : out STD_LOGIC;
TRACE_CLK : in STD_LOGIC;
TRACE_CTL : out STD_LOGIC;
TRACE_DATA : out STD_LOGIC_VECTOR ( 1 downto 0 );
TRACE_CLK_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
USB1_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB1_VBUS_PWRSELECT : out STD_LOGIC;
USB1_VBUS_PWRFAULT : in STD_LOGIC;
SRAM_INTIN : in STD_LOGIC;
M_AXI_GP0_ARESETN : out STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARESETN : out STD_LOGIC;
M_AXI_GP1_ARVALID : out STD_LOGIC;
M_AXI_GP1_AWVALID : out STD_LOGIC;
M_AXI_GP1_BREADY : out STD_LOGIC;
M_AXI_GP1_RREADY : out STD_LOGIC;
M_AXI_GP1_WLAST : out STD_LOGIC;
M_AXI_GP1_WVALID : out STD_LOGIC;
M_AXI_GP1_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ACLK : in STD_LOGIC;
M_AXI_GP1_ARREADY : in STD_LOGIC;
M_AXI_GP1_AWREADY : in STD_LOGIC;
M_AXI_GP1_BVALID : in STD_LOGIC;
M_AXI_GP1_RLAST : in STD_LOGIC;
M_AXI_GP1_RVALID : in STD_LOGIC;
M_AXI_GP1_WREADY : in STD_LOGIC;
M_AXI_GP1_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_ARESETN : out STD_LOGIC;
S_AXI_GP0_ARREADY : out STD_LOGIC;
S_AXI_GP0_AWREADY : out STD_LOGIC;
S_AXI_GP0_BVALID : out STD_LOGIC;
S_AXI_GP0_RLAST : out STD_LOGIC;
S_AXI_GP0_RVALID : out STD_LOGIC;
S_AXI_GP0_WREADY : out STD_LOGIC;
S_AXI_GP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_ACLK : in STD_LOGIC;
S_AXI_GP0_ARVALID : in STD_LOGIC;
S_AXI_GP0_AWVALID : in STD_LOGIC;
S_AXI_GP0_BREADY : in STD_LOGIC;
S_AXI_GP0_RREADY : in STD_LOGIC;
S_AXI_GP0_WLAST : in STD_LOGIC;
S_AXI_GP0_WVALID : in STD_LOGIC;
S_AXI_GP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_ARESETN : out STD_LOGIC;
S_AXI_GP1_ARREADY : out STD_LOGIC;
S_AXI_GP1_AWREADY : out STD_LOGIC;
S_AXI_GP1_BVALID : out STD_LOGIC;
S_AXI_GP1_RLAST : out STD_LOGIC;
S_AXI_GP1_RVALID : out STD_LOGIC;
S_AXI_GP1_WREADY : out STD_LOGIC;
S_AXI_GP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_ACLK : in STD_LOGIC;
S_AXI_GP1_ARVALID : in STD_LOGIC;
S_AXI_GP1_AWVALID : in STD_LOGIC;
S_AXI_GP1_BREADY : in STD_LOGIC;
S_AXI_GP1_RREADY : in STD_LOGIC;
S_AXI_GP1_WLAST : in STD_LOGIC;
S_AXI_GP1_WVALID : in STD_LOGIC;
S_AXI_GP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_ACP_ARESETN : out STD_LOGIC;
S_AXI_ACP_ARREADY : out STD_LOGIC;
S_AXI_ACP_AWREADY : out STD_LOGIC;
S_AXI_ACP_BVALID : out STD_LOGIC;
S_AXI_ACP_RLAST : out STD_LOGIC;
S_AXI_ACP_RVALID : out STD_LOGIC;
S_AXI_ACP_WREADY : out STD_LOGIC;
S_AXI_ACP_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_BID : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_RID : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_ACP_ACLK : in STD_LOGIC;
S_AXI_ACP_ARVALID : in STD_LOGIC;
S_AXI_ACP_AWVALID : in STD_LOGIC;
S_AXI_ACP_BREADY : in STD_LOGIC;
S_AXI_ACP_RREADY : in STD_LOGIC;
S_AXI_ACP_WLAST : in STD_LOGIC;
S_AXI_ACP_WVALID : in STD_LOGIC;
S_AXI_ACP_ARID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_WID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACP_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACP_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARUSER : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_ACP_AWUSER : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_ACP_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_ACP_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_ARESETN : out STD_LOGIC;
S_AXI_HP0_ARREADY : out STD_LOGIC;
S_AXI_HP0_AWREADY : out STD_LOGIC;
S_AXI_HP0_BVALID : out STD_LOGIC;
S_AXI_HP0_RLAST : out STD_LOGIC;
S_AXI_HP0_RVALID : out STD_LOGIC;
S_AXI_HP0_WREADY : out STD_LOGIC;
S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_ACLK : in STD_LOGIC;
S_AXI_HP0_ARVALID : in STD_LOGIC;
S_AXI_HP0_AWVALID : in STD_LOGIC;
S_AXI_HP0_BREADY : in STD_LOGIC;
S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_RREADY : in STD_LOGIC;
S_AXI_HP0_WLAST : in STD_LOGIC;
S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_WVALID : in STD_LOGIC;
S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_ARESETN : out STD_LOGIC;
S_AXI_HP1_ARREADY : out STD_LOGIC;
S_AXI_HP1_AWREADY : out STD_LOGIC;
S_AXI_HP1_BVALID : out STD_LOGIC;
S_AXI_HP1_RLAST : out STD_LOGIC;
S_AXI_HP1_RVALID : out STD_LOGIC;
S_AXI_HP1_WREADY : out STD_LOGIC;
S_AXI_HP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP1_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_ACLK : in STD_LOGIC;
S_AXI_HP1_ARVALID : in STD_LOGIC;
S_AXI_HP1_AWVALID : in STD_LOGIC;
S_AXI_HP1_BREADY : in STD_LOGIC;
S_AXI_HP1_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP1_RREADY : in STD_LOGIC;
S_AXI_HP1_WLAST : in STD_LOGIC;
S_AXI_HP1_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP1_WVALID : in STD_LOGIC;
S_AXI_HP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP1_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_ARESETN : out STD_LOGIC;
S_AXI_HP2_ARREADY : out STD_LOGIC;
S_AXI_HP2_AWREADY : out STD_LOGIC;
S_AXI_HP2_BVALID : out STD_LOGIC;
S_AXI_HP2_RLAST : out STD_LOGIC;
S_AXI_HP2_RVALID : out STD_LOGIC;
S_AXI_HP2_WREADY : out STD_LOGIC;
S_AXI_HP2_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP2_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_ACLK : in STD_LOGIC;
S_AXI_HP2_ARVALID : in STD_LOGIC;
S_AXI_HP2_AWVALID : in STD_LOGIC;
S_AXI_HP2_BREADY : in STD_LOGIC;
S_AXI_HP2_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP2_RREADY : in STD_LOGIC;
S_AXI_HP2_WLAST : in STD_LOGIC;
S_AXI_HP2_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP2_WVALID : in STD_LOGIC;
S_AXI_HP2_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP2_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP2_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP2_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_ARESETN : out STD_LOGIC;
S_AXI_HP3_ARREADY : out STD_LOGIC;
S_AXI_HP3_AWREADY : out STD_LOGIC;
S_AXI_HP3_BVALID : out STD_LOGIC;
S_AXI_HP3_RLAST : out STD_LOGIC;
S_AXI_HP3_RVALID : out STD_LOGIC;
S_AXI_HP3_WREADY : out STD_LOGIC;
S_AXI_HP3_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP3_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_ACLK : in STD_LOGIC;
S_AXI_HP3_ARVALID : in STD_LOGIC;
S_AXI_HP3_AWVALID : in STD_LOGIC;
S_AXI_HP3_BREADY : in STD_LOGIC;
S_AXI_HP3_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP3_RREADY : in STD_LOGIC;
S_AXI_HP3_WLAST : in STD_LOGIC;
S_AXI_HP3_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP3_WVALID : in STD_LOGIC;
S_AXI_HP3_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP3_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP3_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP3_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
IRQ_P2F_DMAC_ABORT : out STD_LOGIC;
IRQ_P2F_DMAC0 : out STD_LOGIC;
IRQ_P2F_DMAC1 : out STD_LOGIC;
IRQ_P2F_DMAC2 : out STD_LOGIC;
IRQ_P2F_DMAC3 : out STD_LOGIC;
IRQ_P2F_DMAC4 : out STD_LOGIC;
IRQ_P2F_DMAC5 : out STD_LOGIC;
IRQ_P2F_DMAC6 : out STD_LOGIC;
IRQ_P2F_DMAC7 : out STD_LOGIC;
IRQ_P2F_SMC : out STD_LOGIC;
IRQ_P2F_QSPI : out STD_LOGIC;
IRQ_P2F_CTI : out STD_LOGIC;
IRQ_P2F_GPIO : out STD_LOGIC;
IRQ_P2F_USB0 : out STD_LOGIC;
IRQ_P2F_ENET0 : out STD_LOGIC;
IRQ_P2F_ENET_WAKE0 : out STD_LOGIC;
IRQ_P2F_SDIO0 : out STD_LOGIC;
IRQ_P2F_I2C0 : out STD_LOGIC;
IRQ_P2F_SPI0 : out STD_LOGIC;
IRQ_P2F_UART0 : out STD_LOGIC;
IRQ_P2F_CAN0 : out STD_LOGIC;
IRQ_P2F_USB1 : out STD_LOGIC;
IRQ_P2F_ENET1 : out STD_LOGIC;
IRQ_P2F_ENET_WAKE1 : out STD_LOGIC;
IRQ_P2F_SDIO1 : out STD_LOGIC;
IRQ_P2F_I2C1 : out STD_LOGIC;
IRQ_P2F_SPI1 : out STD_LOGIC;
IRQ_P2F_UART1 : out STD_LOGIC;
IRQ_P2F_CAN1 : out STD_LOGIC;
IRQ_F2P : in STD_LOGIC_VECTOR ( 0 to 0 );
Core0_nFIQ : in STD_LOGIC;
Core0_nIRQ : in STD_LOGIC;
Core1_nFIQ : in STD_LOGIC;
Core1_nIRQ : in STD_LOGIC;
DMA0_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA0_DAVALID : out STD_LOGIC;
DMA0_DRREADY : out STD_LOGIC;
DMA0_RSTN : out STD_LOGIC;
DMA1_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DAVALID : out STD_LOGIC;
DMA1_DRREADY : out STD_LOGIC;
DMA1_RSTN : out STD_LOGIC;
DMA2_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DAVALID : out STD_LOGIC;
DMA2_DRREADY : out STD_LOGIC;
DMA2_RSTN : out STD_LOGIC;
DMA3_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA3_DAVALID : out STD_LOGIC;
DMA3_DRREADY : out STD_LOGIC;
DMA3_RSTN : out STD_LOGIC;
DMA0_ACLK : in STD_LOGIC;
DMA0_DAREADY : in STD_LOGIC;
DMA0_DRLAST : in STD_LOGIC;
DMA0_DRVALID : in STD_LOGIC;
DMA1_ACLK : in STD_LOGIC;
DMA1_DAREADY : in STD_LOGIC;
DMA1_DRLAST : in STD_LOGIC;
DMA1_DRVALID : in STD_LOGIC;
DMA2_ACLK : in STD_LOGIC;
DMA2_DAREADY : in STD_LOGIC;
DMA2_DRLAST : in STD_LOGIC;
DMA2_DRVALID : in STD_LOGIC;
DMA3_ACLK : in STD_LOGIC;
DMA3_DAREADY : in STD_LOGIC;
DMA3_DRLAST : in STD_LOGIC;
DMA3_DRVALID : in STD_LOGIC;
DMA0_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA3_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
FCLK_CLK3 : out STD_LOGIC;
FCLK_CLK2 : out STD_LOGIC;
FCLK_CLK1 : out STD_LOGIC;
FCLK_CLK0 : out STD_LOGIC;
FCLK_CLKTRIG3_N : in STD_LOGIC;
FCLK_CLKTRIG2_N : in STD_LOGIC;
FCLK_CLKTRIG1_N : in STD_LOGIC;
FCLK_CLKTRIG0_N : in STD_LOGIC;
FCLK_RESET3_N : out STD_LOGIC;
FCLK_RESET2_N : out STD_LOGIC;
FCLK_RESET1_N : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
FTMD_TRACEIN_DATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FTMD_TRACEIN_VALID : in STD_LOGIC;
FTMD_TRACEIN_CLK : in STD_LOGIC;
FTMD_TRACEIN_ATID : in STD_LOGIC_VECTOR ( 3 downto 0 );
FTMT_F2P_TRIG_0 : in STD_LOGIC;
FTMT_F2P_TRIGACK_0 : out STD_LOGIC;
FTMT_F2P_TRIG_1 : in STD_LOGIC;
FTMT_F2P_TRIGACK_1 : out STD_LOGIC;
FTMT_F2P_TRIG_2 : in STD_LOGIC;
FTMT_F2P_TRIGACK_2 : out STD_LOGIC;
FTMT_F2P_TRIG_3 : in STD_LOGIC;
FTMT_F2P_TRIGACK_3 : out STD_LOGIC;
FTMT_F2P_DEBUG : in STD_LOGIC_VECTOR ( 31 downto 0 );
FTMT_P2F_TRIGACK_0 : in STD_LOGIC;
FTMT_P2F_TRIG_0 : out STD_LOGIC;
FTMT_P2F_TRIGACK_1 : in STD_LOGIC;
FTMT_P2F_TRIG_1 : out STD_LOGIC;
FTMT_P2F_TRIGACK_2 : in STD_LOGIC;
FTMT_P2F_TRIG_2 : out STD_LOGIC;
FTMT_P2F_TRIGACK_3 : in STD_LOGIC;
FTMT_P2F_TRIG_3 : out STD_LOGIC;
FTMT_P2F_DEBUG : out STD_LOGIC_VECTOR ( 31 downto 0 );
FPGA_IDLE_N : in STD_LOGIC;
EVENT_EVENTO : out STD_LOGIC;
EVENT_STANDBYWFE : out STD_LOGIC_VECTOR ( 1 downto 0 );
EVENT_STANDBYWFI : out STD_LOGIC_VECTOR ( 1 downto 0 );
EVENT_EVENTI : in STD_LOGIC;
DDR_ARB : in STD_LOGIC_VECTOR ( 3 downto 0 );
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
attribute C_DM_WIDTH : integer;
attribute C_DM_WIDTH of zynq_design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 4;
attribute C_DQS_WIDTH : integer;
attribute C_DQS_WIDTH of zynq_design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 4;
attribute C_DQ_WIDTH : integer;
attribute C_DQ_WIDTH of zynq_design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 32;
attribute C_EMIO_GPIO_WIDTH : integer;
attribute C_EMIO_GPIO_WIDTH of zynq_design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_EN_EMIO_ENET0 : integer;
attribute C_EN_EMIO_ENET0 of zynq_design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_ENET1 : integer;
attribute C_EN_EMIO_ENET1 of zynq_design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_PJTAG : integer;
attribute C_EN_EMIO_PJTAG of zynq_design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of zynq_design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of zynq_design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is "TRUE";
attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of zynq_design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_FCLK_CLK2_BUF : string;
attribute C_FCLK_CLK2_BUF of zynq_design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_FCLK_CLK3_BUF : string;
attribute C_FCLK_CLK3_BUF of zynq_design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_GP0_EN_MODIFIABLE_TXN : integer;
attribute C_GP0_EN_MODIFIABLE_TXN of zynq_design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_GP1_EN_MODIFIABLE_TXN : integer;
attribute C_GP1_EN_MODIFIABLE_TXN of zynq_design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
attribute C_INCLUDE_ACP_TRANS_CHECK of zynq_design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_INCLUDE_TRACE_BUFFER : integer;
attribute C_INCLUDE_TRACE_BUFFER of zynq_design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_IRQ_F2P_MODE : string;
attribute C_IRQ_F2P_MODE of zynq_design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is "DIRECT";
attribute C_MIO_PRIMITIVE : integer;
attribute C_MIO_PRIMITIVE of zynq_design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 54;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of zynq_design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_M_AXI_GP0_ID_WIDTH : integer;
attribute C_M_AXI_GP0_ID_WIDTH of zynq_design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH of zynq_design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of zynq_design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_M_AXI_GP1_ID_WIDTH : integer;
attribute C_M_AXI_GP1_ID_WIDTH of zynq_design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of zynq_design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_NUM_F2P_INTR_INPUTS : integer;
attribute C_NUM_F2P_INTR_INPUTS of zynq_design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_PACKAGE_NAME : string;
attribute C_PACKAGE_NAME of zynq_design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is "clg484";
attribute C_PS7_SI_REV : string;
attribute C_PS7_SI_REV of zynq_design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is "PRODUCTION";
attribute C_S_AXI_ACP_ARUSER_VAL : integer;
attribute C_S_AXI_ACP_ARUSER_VAL of zynq_design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 31;
attribute C_S_AXI_ACP_AWUSER_VAL : integer;
attribute C_S_AXI_ACP_AWUSER_VAL of zynq_design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 31;
attribute C_S_AXI_ACP_ID_WIDTH : integer;
attribute C_S_AXI_ACP_ID_WIDTH of zynq_design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 3;
attribute C_S_AXI_GP0_ID_WIDTH : integer;
attribute C_S_AXI_GP0_ID_WIDTH of zynq_design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_GP1_ID_WIDTH : integer;
attribute C_S_AXI_GP1_ID_WIDTH of zynq_design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP0_DATA_WIDTH : integer;
attribute C_S_AXI_HP0_DATA_WIDTH of zynq_design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP0_ID_WIDTH : integer;
attribute C_S_AXI_HP0_ID_WIDTH of zynq_design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP1_DATA_WIDTH : integer;
attribute C_S_AXI_HP1_DATA_WIDTH of zynq_design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP1_ID_WIDTH : integer;
attribute C_S_AXI_HP1_ID_WIDTH of zynq_design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP2_DATA_WIDTH : integer;
attribute C_S_AXI_HP2_DATA_WIDTH of zynq_design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP2_ID_WIDTH : integer;
attribute C_S_AXI_HP2_ID_WIDTH of zynq_design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP3_DATA_WIDTH : integer;
attribute C_S_AXI_HP3_DATA_WIDTH of zynq_design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP3_ID_WIDTH : integer;
attribute C_S_AXI_HP3_ID_WIDTH of zynq_design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
attribute C_TRACE_BUFFER_CLOCK_DELAY of zynq_design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
attribute C_TRACE_BUFFER_FIFO_SIZE of zynq_design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 128;
attribute C_TRACE_INTERNAL_WIDTH : integer;
attribute C_TRACE_INTERNAL_WIDTH of zynq_design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 2;
attribute C_TRACE_PIPELINE_WIDTH : integer;
attribute C_TRACE_PIPELINE_WIDTH of zynq_design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 8;
attribute C_USE_AXI_NONSECURE : integer;
attribute C_USE_AXI_NONSECURE of zynq_design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
attribute C_USE_DEFAULT_ACP_USER_VAL of zynq_design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_M_AXI_GP0 : integer;
attribute C_USE_M_AXI_GP0 of zynq_design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_USE_M_AXI_GP1 : integer;
attribute C_USE_M_AXI_GP1 of zynq_design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_ACP : integer;
attribute C_USE_S_AXI_ACP of zynq_design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_GP0 : integer;
attribute C_USE_S_AXI_GP0 of zynq_design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_GP1 : integer;
attribute C_USE_S_AXI_GP1 of zynq_design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP0 : integer;
attribute C_USE_S_AXI_HP0 of zynq_design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP1 : integer;
attribute C_USE_S_AXI_HP1 of zynq_design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP2 : integer;
attribute C_USE_S_AXI_HP2 of zynq_design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP3 : integer;
attribute C_USE_S_AXI_HP3 of zynq_design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of zynq_design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is "zynq_design_1_processing_system7_0_2.hwdef";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is "processing_system7_v5_5_processing_system7";
attribute POWER : string;
attribute POWER of zynq_design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of zynq_design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
end zynq_design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7;
architecture STRUCTURE of zynq_design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal ENET0_MDIO_T_n : STD_LOGIC;
signal ENET1_MDIO_T_n : STD_LOGIC;
signal FCLK_CLK_unbuffered : STD_LOGIC_VECTOR ( 0 to 0 );
signal I2C0_SCL_T_n : STD_LOGIC;
signal I2C0_SDA_T_n : STD_LOGIC;
signal I2C1_SCL_T_n : STD_LOGIC;
signal I2C1_SDA_T_n : STD_LOGIC;
signal \^m_axi_gp0_arcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_gp0_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp0_awcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_gp0_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp1_arcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_gp1_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp1_awcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_gp1_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal SDIO0_CMD_T_n : STD_LOGIC;
signal SDIO0_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal SDIO1_CMD_T_n : STD_LOGIC;
signal SDIO1_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal SPI0_MISO_T_n : STD_LOGIC;
signal SPI0_MOSI_T_n : STD_LOGIC;
signal SPI0_SCLK_T_n : STD_LOGIC;
signal SPI0_SS_T_n : STD_LOGIC;
signal SPI1_MISO_T_n : STD_LOGIC;
signal SPI1_MOSI_T_n : STD_LOGIC;
signal SPI1_SCLK_T_n : STD_LOGIC;
signal SPI1_SS_T_n : STD_LOGIC;
signal \TRACE_CTL_PIPE[0]\ : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of \TRACE_CTL_PIPE[0]\ : signal is "true";
signal \TRACE_CTL_PIPE[1]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[1]\ : signal is "true";
signal \TRACE_CTL_PIPE[2]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[2]\ : signal is "true";
signal \TRACE_CTL_PIPE[3]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[3]\ : signal is "true";
signal \TRACE_CTL_PIPE[4]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[4]\ : signal is "true";
signal \TRACE_CTL_PIPE[5]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[5]\ : signal is "true";
signal \TRACE_CTL_PIPE[6]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[6]\ : signal is "true";
signal \TRACE_CTL_PIPE[7]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[7]\ : signal is "true";
signal \TRACE_DATA_PIPE[0]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[0]\ : signal is "true";
signal \TRACE_DATA_PIPE[1]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[1]\ : signal is "true";
signal \TRACE_DATA_PIPE[2]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[2]\ : signal is "true";
signal \TRACE_DATA_PIPE[3]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[3]\ : signal is "true";
signal \TRACE_DATA_PIPE[4]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[4]\ : signal is "true";
signal \TRACE_DATA_PIPE[5]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[5]\ : signal is "true";
signal \TRACE_DATA_PIPE[6]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[6]\ : signal is "true";
signal \TRACE_DATA_PIPE[7]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[7]\ : signal is "true";
signal buffered_DDR_Addr : STD_LOGIC_VECTOR ( 14 downto 0 );
signal buffered_DDR_BankAddr : STD_LOGIC_VECTOR ( 2 downto 0 );
signal buffered_DDR_CAS_n : STD_LOGIC;
signal buffered_DDR_CKE : STD_LOGIC;
signal buffered_DDR_CS_n : STD_LOGIC;
signal buffered_DDR_Clk : STD_LOGIC;
signal buffered_DDR_Clk_n : STD_LOGIC;
signal buffered_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal buffered_DDR_DQS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DQS_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DRSTB : STD_LOGIC;
signal buffered_DDR_ODT : STD_LOGIC;
signal buffered_DDR_RAS_n : STD_LOGIC;
signal buffered_DDR_VRN : STD_LOGIC;
signal buffered_DDR_VRP : STD_LOGIC;
signal buffered_DDR_WEB : STD_LOGIC;
signal buffered_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal buffered_PS_CLK : STD_LOGIC;
signal buffered_PS_PORB : STD_LOGIC;
signal buffered_PS_SRSTB : STD_LOGIC;
signal gpio_out_t_n : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOTRACECTL_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of DDR_CAS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_CKE_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_CS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_Clk_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_Clk_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_DRSTB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_ODT_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_RAS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_VRN_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_VRP_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_WEB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS7_i : label is "PRIMITIVE";
attribute BOX_TYPE of PS_CLK_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS_PORB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS_SRSTB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of \buffer_fclk_clk_0.FCLK_CLK_0_BUFG\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[0].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[10].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[11].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[12].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[13].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[14].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[15].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[16].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[17].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[18].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[19].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[1].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[20].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[21].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[22].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[23].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[24].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[25].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[26].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[27].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[28].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[29].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[2].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[30].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[31].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[32].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[33].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[34].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[35].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[36].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[37].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[38].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[39].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[3].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[40].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[41].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[42].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[43].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[44].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[45].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[46].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[47].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[48].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[49].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[4].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[50].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[51].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[52].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[53].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[5].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[6].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[7].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[8].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[9].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[0].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[1].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[2].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[0].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[10].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[11].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[12].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[13].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[14].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[1].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[2].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[3].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[4].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[5].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[6].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[7].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[8].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[9].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[0].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[1].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[2].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[3].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[0].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[10].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[11].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[12].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[13].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[14].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[15].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[16].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[17].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[18].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[19].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[1].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[20].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[21].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[22].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[23].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[24].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[25].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[26].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[27].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[28].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[29].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[2].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[30].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[31].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[3].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[4].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[5].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[6].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[7].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[8].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[9].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[0].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[1].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[2].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[3].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[0].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[1].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[2].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[3].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
begin
ENET0_GMII_TXD(7) <= \<const0>\;
ENET0_GMII_TXD(6) <= \<const0>\;
ENET0_GMII_TXD(5) <= \<const0>\;
ENET0_GMII_TXD(4) <= \<const0>\;
ENET0_GMII_TXD(3) <= \<const0>\;
ENET0_GMII_TXD(2) <= \<const0>\;
ENET0_GMII_TXD(1) <= \<const0>\;
ENET0_GMII_TXD(0) <= \<const0>\;
ENET0_GMII_TX_EN <= \<const0>\;
ENET0_GMII_TX_ER <= \<const0>\;
ENET1_GMII_TXD(7) <= \<const0>\;
ENET1_GMII_TXD(6) <= \<const0>\;
ENET1_GMII_TXD(5) <= \<const0>\;
ENET1_GMII_TXD(4) <= \<const0>\;
ENET1_GMII_TXD(3) <= \<const0>\;
ENET1_GMII_TXD(2) <= \<const0>\;
ENET1_GMII_TXD(1) <= \<const0>\;
ENET1_GMII_TXD(0) <= \<const0>\;
ENET1_GMII_TX_EN <= \<const0>\;
ENET1_GMII_TX_ER <= \<const0>\;
M_AXI_GP0_ARCACHE(3 downto 2) <= \^m_axi_gp0_arcache\(3 downto 2);
M_AXI_GP0_ARCACHE(1) <= \<const1>\;
M_AXI_GP0_ARCACHE(0) <= \^m_axi_gp0_arcache\(0);
M_AXI_GP0_ARSIZE(2) <= \<const0>\;
M_AXI_GP0_ARSIZE(1 downto 0) <= \^m_axi_gp0_arsize\(1 downto 0);
M_AXI_GP0_AWCACHE(3 downto 2) <= \^m_axi_gp0_awcache\(3 downto 2);
M_AXI_GP0_AWCACHE(1) <= \<const1>\;
M_AXI_GP0_AWCACHE(0) <= \^m_axi_gp0_awcache\(0);
M_AXI_GP0_AWSIZE(2) <= \<const0>\;
M_AXI_GP0_AWSIZE(1 downto 0) <= \^m_axi_gp0_awsize\(1 downto 0);
M_AXI_GP1_ARCACHE(3 downto 2) <= \^m_axi_gp1_arcache\(3 downto 2);
M_AXI_GP1_ARCACHE(1) <= \<const1>\;
M_AXI_GP1_ARCACHE(0) <= \^m_axi_gp1_arcache\(0);
M_AXI_GP1_ARSIZE(2) <= \<const0>\;
M_AXI_GP1_ARSIZE(1 downto 0) <= \^m_axi_gp1_arsize\(1 downto 0);
M_AXI_GP1_AWCACHE(3 downto 2) <= \^m_axi_gp1_awcache\(3 downto 2);
M_AXI_GP1_AWCACHE(1) <= \<const1>\;
M_AXI_GP1_AWCACHE(0) <= \^m_axi_gp1_awcache\(0);
M_AXI_GP1_AWSIZE(2) <= \<const0>\;
M_AXI_GP1_AWSIZE(1 downto 0) <= \^m_axi_gp1_awsize\(1 downto 0);
PJTAG_TDO <= \<const0>\;
TRACE_CLK_OUT <= \<const0>\;
TRACE_CTL <= \TRACE_CTL_PIPE[0]\;
TRACE_DATA(1 downto 0) <= \TRACE_DATA_PIPE[0]\(1 downto 0);
DDR_CAS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CAS_n,
PAD => DDR_CAS_n
);
DDR_CKE_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CKE,
PAD => DDR_CKE
);
DDR_CS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CS_n,
PAD => DDR_CS_n
);
DDR_Clk_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Clk,
PAD => DDR_Clk
);
DDR_Clk_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Clk_n,
PAD => DDR_Clk_n
);
DDR_DRSTB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DRSTB,
PAD => DDR_DRSTB
);
DDR_ODT_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_ODT,
PAD => DDR_ODT
);
DDR_RAS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_RAS_n,
PAD => DDR_RAS_n
);
DDR_VRN_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_VRN,
PAD => DDR_VRN
);
DDR_VRP_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_VRP,
PAD => DDR_VRP
);
DDR_WEB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_WEB,
PAD => DDR_WEB
);
ENET0_MDIO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ENET0_MDIO_T_n,
O => ENET0_MDIO_T
);
ENET1_MDIO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ENET1_MDIO_T_n,
O => ENET1_MDIO_T
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\GPIO_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(0),
O => GPIO_T(0)
);
\GPIO_T[10]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(10),
O => GPIO_T(10)
);
\GPIO_T[11]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(11),
O => GPIO_T(11)
);
\GPIO_T[12]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(12),
O => GPIO_T(12)
);
\GPIO_T[13]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(13),
O => GPIO_T(13)
);
\GPIO_T[14]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(14),
O => GPIO_T(14)
);
\GPIO_T[15]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(15),
O => GPIO_T(15)
);
\GPIO_T[16]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(16),
O => GPIO_T(16)
);
\GPIO_T[17]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(17),
O => GPIO_T(17)
);
\GPIO_T[18]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(18),
O => GPIO_T(18)
);
\GPIO_T[19]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(19),
O => GPIO_T(19)
);
\GPIO_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(1),
O => GPIO_T(1)
);
\GPIO_T[20]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(20),
O => GPIO_T(20)
);
\GPIO_T[21]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(21),
O => GPIO_T(21)
);
\GPIO_T[22]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(22),
O => GPIO_T(22)
);
\GPIO_T[23]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(23),
O => GPIO_T(23)
);
\GPIO_T[24]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(24),
O => GPIO_T(24)
);
\GPIO_T[25]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(25),
O => GPIO_T(25)
);
\GPIO_T[26]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(26),
O => GPIO_T(26)
);
\GPIO_T[27]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(27),
O => GPIO_T(27)
);
\GPIO_T[28]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(28),
O => GPIO_T(28)
);
\GPIO_T[29]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(29),
O => GPIO_T(29)
);
\GPIO_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(2),
O => GPIO_T(2)
);
\GPIO_T[30]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(30),
O => GPIO_T(30)
);
\GPIO_T[31]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(31),
O => GPIO_T(31)
);
\GPIO_T[32]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(32),
O => GPIO_T(32)
);
\GPIO_T[33]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(33),
O => GPIO_T(33)
);
\GPIO_T[34]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(34),
O => GPIO_T(34)
);
\GPIO_T[35]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(35),
O => GPIO_T(35)
);
\GPIO_T[36]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(36),
O => GPIO_T(36)
);
\GPIO_T[37]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(37),
O => GPIO_T(37)
);
\GPIO_T[38]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(38),
O => GPIO_T(38)
);
\GPIO_T[39]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(39),
O => GPIO_T(39)
);
\GPIO_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(3),
O => GPIO_T(3)
);
\GPIO_T[40]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(40),
O => GPIO_T(40)
);
\GPIO_T[41]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(41),
O => GPIO_T(41)
);
\GPIO_T[42]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(42),
O => GPIO_T(42)
);
\GPIO_T[43]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(43),
O => GPIO_T(43)
);
\GPIO_T[44]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(44),
O => GPIO_T(44)
);
\GPIO_T[45]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(45),
O => GPIO_T(45)
);
\GPIO_T[46]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(46),
O => GPIO_T(46)
);
\GPIO_T[47]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(47),
O => GPIO_T(47)
);
\GPIO_T[48]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(48),
O => GPIO_T(48)
);
\GPIO_T[49]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(49),
O => GPIO_T(49)
);
\GPIO_T[4]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(4),
O => GPIO_T(4)
);
\GPIO_T[50]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(50),
O => GPIO_T(50)
);
\GPIO_T[51]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(51),
O => GPIO_T(51)
);
\GPIO_T[52]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(52),
O => GPIO_T(52)
);
\GPIO_T[53]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(53),
O => GPIO_T(53)
);
\GPIO_T[54]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(54),
O => GPIO_T(54)
);
\GPIO_T[55]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(55),
O => GPIO_T(55)
);
\GPIO_T[56]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(56),
O => GPIO_T(56)
);
\GPIO_T[57]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(57),
O => GPIO_T(57)
);
\GPIO_T[58]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(58),
O => GPIO_T(58)
);
\GPIO_T[59]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(59),
O => GPIO_T(59)
);
\GPIO_T[5]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(5),
O => GPIO_T(5)
);
\GPIO_T[60]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(60),
O => GPIO_T(60)
);
\GPIO_T[61]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(61),
O => GPIO_T(61)
);
\GPIO_T[62]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(62),
O => GPIO_T(62)
);
\GPIO_T[63]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(63),
O => GPIO_T(63)
);
\GPIO_T[6]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(6),
O => GPIO_T(6)
);
\GPIO_T[7]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(7),
O => GPIO_T(7)
);
\GPIO_T[8]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(8),
O => GPIO_T(8)
);
\GPIO_T[9]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(9),
O => GPIO_T(9)
);
I2C0_SCL_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C0_SCL_T_n,
O => I2C0_SCL_T
);
I2C0_SDA_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C0_SDA_T_n,
O => I2C0_SDA_T
);
I2C1_SCL_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C1_SCL_T_n,
O => I2C1_SCL_T
);
I2C1_SDA_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C1_SDA_T_n,
O => I2C1_SDA_T
);
PS7_i: unisim.vcomponents.PS7
port map (
DDRA(14 downto 0) => buffered_DDR_Addr(14 downto 0),
DDRARB(3 downto 0) => DDR_ARB(3 downto 0),
DDRBA(2 downto 0) => buffered_DDR_BankAddr(2 downto 0),
DDRCASB => buffered_DDR_CAS_n,
DDRCKE => buffered_DDR_CKE,
DDRCKN => buffered_DDR_Clk_n,
DDRCKP => buffered_DDR_Clk,
DDRCSB => buffered_DDR_CS_n,
DDRDM(3 downto 0) => buffered_DDR_DM(3 downto 0),
DDRDQ(31 downto 0) => buffered_DDR_DQ(31 downto 0),
DDRDQSN(3 downto 0) => buffered_DDR_DQS_n(3 downto 0),
DDRDQSP(3 downto 0) => buffered_DDR_DQS(3 downto 0),
DDRDRSTB => buffered_DDR_DRSTB,
DDRODT => buffered_DDR_ODT,
DDRRASB => buffered_DDR_RAS_n,
DDRVRN => buffered_DDR_VRN,
DDRVRP => buffered_DDR_VRP,
DDRWEB => buffered_DDR_WEB,
DMA0ACLK => DMA0_ACLK,
DMA0DAREADY => DMA0_DAREADY,
DMA0DATYPE(1 downto 0) => DMA0_DATYPE(1 downto 0),
DMA0DAVALID => DMA0_DAVALID,
DMA0DRLAST => DMA0_DRLAST,
DMA0DRREADY => DMA0_DRREADY,
DMA0DRTYPE(1 downto 0) => DMA0_DRTYPE(1 downto 0),
DMA0DRVALID => DMA0_DRVALID,
DMA0RSTN => DMA0_RSTN,
DMA1ACLK => DMA1_ACLK,
DMA1DAREADY => DMA1_DAREADY,
DMA1DATYPE(1 downto 0) => DMA1_DATYPE(1 downto 0),
DMA1DAVALID => DMA1_DAVALID,
DMA1DRLAST => DMA1_DRLAST,
DMA1DRREADY => DMA1_DRREADY,
DMA1DRTYPE(1 downto 0) => DMA1_DRTYPE(1 downto 0),
DMA1DRVALID => DMA1_DRVALID,
DMA1RSTN => DMA1_RSTN,
DMA2ACLK => DMA2_ACLK,
DMA2DAREADY => DMA2_DAREADY,
DMA2DATYPE(1 downto 0) => DMA2_DATYPE(1 downto 0),
DMA2DAVALID => DMA2_DAVALID,
DMA2DRLAST => DMA2_DRLAST,
DMA2DRREADY => DMA2_DRREADY,
DMA2DRTYPE(1 downto 0) => DMA2_DRTYPE(1 downto 0),
DMA2DRVALID => DMA2_DRVALID,
DMA2RSTN => DMA2_RSTN,
DMA3ACLK => DMA3_ACLK,
DMA3DAREADY => DMA3_DAREADY,
DMA3DATYPE(1 downto 0) => DMA3_DATYPE(1 downto 0),
DMA3DAVALID => DMA3_DAVALID,
DMA3DRLAST => DMA3_DRLAST,
DMA3DRREADY => DMA3_DRREADY,
DMA3DRTYPE(1 downto 0) => DMA3_DRTYPE(1 downto 0),
DMA3DRVALID => DMA3_DRVALID,
DMA3RSTN => DMA3_RSTN,
EMIOCAN0PHYRX => CAN0_PHY_RX,
EMIOCAN0PHYTX => CAN0_PHY_TX,
EMIOCAN1PHYRX => CAN1_PHY_RX,
EMIOCAN1PHYTX => CAN1_PHY_TX,
EMIOENET0EXTINTIN => ENET0_EXT_INTIN,
EMIOENET0GMIICOL => '0',
EMIOENET0GMIICRS => '0',
EMIOENET0GMIIRXCLK => ENET0_GMII_RX_CLK,
EMIOENET0GMIIRXD(7 downto 0) => B"00000000",
EMIOENET0GMIIRXDV => '0',
EMIOENET0GMIIRXER => '0',
EMIOENET0GMIITXCLK => ENET0_GMII_TX_CLK,
EMIOENET0GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED(7 downto 0),
EMIOENET0GMIITXEN => NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED,
EMIOENET0GMIITXER => NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED,
EMIOENET0MDIOI => ENET0_MDIO_I,
EMIOENET0MDIOMDC => ENET0_MDIO_MDC,
EMIOENET0MDIOO => ENET0_MDIO_O,
EMIOENET0MDIOTN => ENET0_MDIO_T_n,
EMIOENET0PTPDELAYREQRX => ENET0_PTP_DELAY_REQ_RX,
EMIOENET0PTPDELAYREQTX => ENET0_PTP_DELAY_REQ_TX,
EMIOENET0PTPPDELAYREQRX => ENET0_PTP_PDELAY_REQ_RX,
EMIOENET0PTPPDELAYREQTX => ENET0_PTP_PDELAY_REQ_TX,
EMIOENET0PTPPDELAYRESPRX => ENET0_PTP_PDELAY_RESP_RX,
EMIOENET0PTPPDELAYRESPTX => ENET0_PTP_PDELAY_RESP_TX,
EMIOENET0PTPSYNCFRAMERX => ENET0_PTP_SYNC_FRAME_RX,
EMIOENET0PTPSYNCFRAMETX => ENET0_PTP_SYNC_FRAME_TX,
EMIOENET0SOFRX => ENET0_SOF_RX,
EMIOENET0SOFTX => ENET0_SOF_TX,
EMIOENET1EXTINTIN => ENET1_EXT_INTIN,
EMIOENET1GMIICOL => '0',
EMIOENET1GMIICRS => '0',
EMIOENET1GMIIRXCLK => ENET1_GMII_RX_CLK,
EMIOENET1GMIIRXD(7 downto 0) => B"00000000",
EMIOENET1GMIIRXDV => '0',
EMIOENET1GMIIRXER => '0',
EMIOENET1GMIITXCLK => ENET1_GMII_TX_CLK,
EMIOENET1GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED(7 downto 0),
EMIOENET1GMIITXEN => NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED,
EMIOENET1GMIITXER => NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED,
EMIOENET1MDIOI => ENET1_MDIO_I,
EMIOENET1MDIOMDC => ENET1_MDIO_MDC,
EMIOENET1MDIOO => ENET1_MDIO_O,
EMIOENET1MDIOTN => ENET1_MDIO_T_n,
EMIOENET1PTPDELAYREQRX => ENET1_PTP_DELAY_REQ_RX,
EMIOENET1PTPDELAYREQTX => ENET1_PTP_DELAY_REQ_TX,
EMIOENET1PTPPDELAYREQRX => ENET1_PTP_PDELAY_REQ_RX,
EMIOENET1PTPPDELAYREQTX => ENET1_PTP_PDELAY_REQ_TX,
EMIOENET1PTPPDELAYRESPRX => ENET1_PTP_PDELAY_RESP_RX,
EMIOENET1PTPPDELAYRESPTX => ENET1_PTP_PDELAY_RESP_TX,
EMIOENET1PTPSYNCFRAMERX => ENET1_PTP_SYNC_FRAME_RX,
EMIOENET1PTPSYNCFRAMETX => ENET1_PTP_SYNC_FRAME_TX,
EMIOENET1SOFRX => ENET1_SOF_RX,
EMIOENET1SOFTX => ENET1_SOF_TX,
EMIOGPIOI(63 downto 0) => GPIO_I(63 downto 0),
EMIOGPIOO(63 downto 0) => GPIO_O(63 downto 0),
EMIOGPIOTN(63 downto 0) => gpio_out_t_n(63 downto 0),
EMIOI2C0SCLI => I2C0_SCL_I,
EMIOI2C0SCLO => I2C0_SCL_O,
EMIOI2C0SCLTN => I2C0_SCL_T_n,
EMIOI2C0SDAI => I2C0_SDA_I,
EMIOI2C0SDAO => I2C0_SDA_O,
EMIOI2C0SDATN => I2C0_SDA_T_n,
EMIOI2C1SCLI => I2C1_SCL_I,
EMIOI2C1SCLO => I2C1_SCL_O,
EMIOI2C1SCLTN => I2C1_SCL_T_n,
EMIOI2C1SDAI => I2C1_SDA_I,
EMIOI2C1SDAO => I2C1_SDA_O,
EMIOI2C1SDATN => I2C1_SDA_T_n,
EMIOPJTAGTCK => PJTAG_TCK,
EMIOPJTAGTDI => PJTAG_TDI,
EMIOPJTAGTDO => NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED,
EMIOPJTAGTDTN => NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED,
EMIOPJTAGTMS => PJTAG_TMS,
EMIOSDIO0BUSPOW => SDIO0_BUSPOW,
EMIOSDIO0BUSVOLT(2 downto 0) => SDIO0_BUSVOLT(2 downto 0),
EMIOSDIO0CDN => SDIO0_CDN,
EMIOSDIO0CLK => SDIO0_CLK,
EMIOSDIO0CLKFB => SDIO0_CLK_FB,
EMIOSDIO0CMDI => SDIO0_CMD_I,
EMIOSDIO0CMDO => SDIO0_CMD_O,
EMIOSDIO0CMDTN => SDIO0_CMD_T_n,
EMIOSDIO0DATAI(3 downto 0) => SDIO0_DATA_I(3 downto 0),
EMIOSDIO0DATAO(3 downto 0) => SDIO0_DATA_O(3 downto 0),
EMIOSDIO0DATATN(3 downto 0) => SDIO0_DATA_T_n(3 downto 0),
EMIOSDIO0LED => SDIO0_LED,
EMIOSDIO0WP => SDIO0_WP,
EMIOSDIO1BUSPOW => SDIO1_BUSPOW,
EMIOSDIO1BUSVOLT(2 downto 0) => SDIO1_BUSVOLT(2 downto 0),
EMIOSDIO1CDN => SDIO1_CDN,
EMIOSDIO1CLK => SDIO1_CLK,
EMIOSDIO1CLKFB => SDIO1_CLK_FB,
EMIOSDIO1CMDI => SDIO1_CMD_I,
EMIOSDIO1CMDO => SDIO1_CMD_O,
EMIOSDIO1CMDTN => SDIO1_CMD_T_n,
EMIOSDIO1DATAI(3 downto 0) => SDIO1_DATA_I(3 downto 0),
EMIOSDIO1DATAO(3 downto 0) => SDIO1_DATA_O(3 downto 0),
EMIOSDIO1DATATN(3 downto 0) => SDIO1_DATA_T_n(3 downto 0),
EMIOSDIO1LED => SDIO1_LED,
EMIOSDIO1WP => SDIO1_WP,
EMIOSPI0MI => SPI0_MISO_I,
EMIOSPI0MO => SPI0_MOSI_O,
EMIOSPI0MOTN => SPI0_MOSI_T_n,
EMIOSPI0SCLKI => SPI0_SCLK_I,
EMIOSPI0SCLKO => SPI0_SCLK_O,
EMIOSPI0SCLKTN => SPI0_SCLK_T_n,
EMIOSPI0SI => SPI0_MOSI_I,
EMIOSPI0SO => SPI0_MISO_O,
EMIOSPI0SSIN => SPI0_SS_I,
EMIOSPI0SSNTN => SPI0_SS_T_n,
EMIOSPI0SSON(2) => SPI0_SS2_O,
EMIOSPI0SSON(1) => SPI0_SS1_O,
EMIOSPI0SSON(0) => SPI0_SS_O,
EMIOSPI0STN => SPI0_MISO_T_n,
EMIOSPI1MI => SPI1_MISO_I,
EMIOSPI1MO => SPI1_MOSI_O,
EMIOSPI1MOTN => SPI1_MOSI_T_n,
EMIOSPI1SCLKI => SPI1_SCLK_I,
EMIOSPI1SCLKO => SPI1_SCLK_O,
EMIOSPI1SCLKTN => SPI1_SCLK_T_n,
EMIOSPI1SI => SPI1_MOSI_I,
EMIOSPI1SO => SPI1_MISO_O,
EMIOSPI1SSIN => SPI1_SS_I,
EMIOSPI1SSNTN => SPI1_SS_T_n,
EMIOSPI1SSON(2) => SPI1_SS2_O,
EMIOSPI1SSON(1) => SPI1_SS1_O,
EMIOSPI1SSON(0) => SPI1_SS_O,
EMIOSPI1STN => SPI1_MISO_T_n,
EMIOSRAMINTIN => SRAM_INTIN,
EMIOTRACECLK => TRACE_CLK,
EMIOTRACECTL => NLW_PS7_i_EMIOTRACECTL_UNCONNECTED,
EMIOTRACEDATA(31 downto 0) => NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED(31 downto 0),
EMIOTTC0CLKI(2) => TTC0_CLK2_IN,
EMIOTTC0CLKI(1) => TTC0_CLK1_IN,
EMIOTTC0CLKI(0) => TTC0_CLK0_IN,
EMIOTTC0WAVEO(2) => TTC0_WAVE2_OUT,
EMIOTTC0WAVEO(1) => TTC0_WAVE1_OUT,
EMIOTTC0WAVEO(0) => TTC0_WAVE0_OUT,
EMIOTTC1CLKI(2) => TTC1_CLK2_IN,
EMIOTTC1CLKI(1) => TTC1_CLK1_IN,
EMIOTTC1CLKI(0) => TTC1_CLK0_IN,
EMIOTTC1WAVEO(2) => TTC1_WAVE2_OUT,
EMIOTTC1WAVEO(1) => TTC1_WAVE1_OUT,
EMIOTTC1WAVEO(0) => TTC1_WAVE0_OUT,
EMIOUART0CTSN => UART0_CTSN,
EMIOUART0DCDN => UART0_DCDN,
EMIOUART0DSRN => UART0_DSRN,
EMIOUART0DTRN => UART0_DTRN,
EMIOUART0RIN => UART0_RIN,
EMIOUART0RTSN => UART0_RTSN,
EMIOUART0RX => UART0_RX,
EMIOUART0TX => UART0_TX,
EMIOUART1CTSN => UART1_CTSN,
EMIOUART1DCDN => UART1_DCDN,
EMIOUART1DSRN => UART1_DSRN,
EMIOUART1DTRN => UART1_DTRN,
EMIOUART1RIN => UART1_RIN,
EMIOUART1RTSN => UART1_RTSN,
EMIOUART1RX => UART1_RX,
EMIOUART1TX => UART1_TX,
EMIOUSB0PORTINDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0),
EMIOUSB0VBUSPWRFAULT => USB0_VBUS_PWRFAULT,
EMIOUSB0VBUSPWRSELECT => USB0_VBUS_PWRSELECT,
EMIOUSB1PORTINDCTL(1 downto 0) => USB1_PORT_INDCTL(1 downto 0),
EMIOUSB1VBUSPWRFAULT => USB1_VBUS_PWRFAULT,
EMIOUSB1VBUSPWRSELECT => USB1_VBUS_PWRSELECT,
EMIOWDTCLKI => WDT_CLK_IN,
EMIOWDTRSTO => WDT_RST_OUT,
EVENTEVENTI => EVENT_EVENTI,
EVENTEVENTO => EVENT_EVENTO,
EVENTSTANDBYWFE(1 downto 0) => EVENT_STANDBYWFE(1 downto 0),
EVENTSTANDBYWFI(1 downto 0) => EVENT_STANDBYWFI(1 downto 0),
FCLKCLK(3) => FCLK_CLK3,
FCLKCLK(2) => FCLK_CLK2,
FCLKCLK(1) => FCLK_CLK1,
FCLKCLK(0) => FCLK_CLK_unbuffered(0),
FCLKCLKTRIGN(3 downto 0) => B"0000",
FCLKRESETN(3) => FCLK_RESET3_N,
FCLKRESETN(2) => FCLK_RESET2_N,
FCLKRESETN(1) => FCLK_RESET1_N,
FCLKRESETN(0) => FCLK_RESET0_N,
FPGAIDLEN => FPGA_IDLE_N,
FTMDTRACEINATID(3 downto 0) => B"0000",
FTMDTRACEINCLOCK => FTMD_TRACEIN_CLK,
FTMDTRACEINDATA(31 downto 0) => B"00000000000000000000000000000000",
FTMDTRACEINVALID => '0',
FTMTF2PDEBUG(31 downto 0) => FTMT_F2P_DEBUG(31 downto 0),
FTMTF2PTRIG(3) => FTMT_F2P_TRIG_3,
FTMTF2PTRIG(2) => FTMT_F2P_TRIG_2,
FTMTF2PTRIG(1) => FTMT_F2P_TRIG_1,
FTMTF2PTRIG(0) => FTMT_F2P_TRIG_0,
FTMTF2PTRIGACK(3) => FTMT_F2P_TRIGACK_3,
FTMTF2PTRIGACK(2) => FTMT_F2P_TRIGACK_2,
FTMTF2PTRIGACK(1) => FTMT_F2P_TRIGACK_1,
FTMTF2PTRIGACK(0) => FTMT_F2P_TRIGACK_0,
FTMTP2FDEBUG(31 downto 0) => FTMT_P2F_DEBUG(31 downto 0),
FTMTP2FTRIG(3) => FTMT_P2F_TRIG_3,
FTMTP2FTRIG(2) => FTMT_P2F_TRIG_2,
FTMTP2FTRIG(1) => FTMT_P2F_TRIG_1,
FTMTP2FTRIG(0) => FTMT_P2F_TRIG_0,
FTMTP2FTRIGACK(3) => FTMT_P2F_TRIGACK_3,
FTMTP2FTRIGACK(2) => FTMT_P2F_TRIGACK_2,
FTMTP2FTRIGACK(1) => FTMT_P2F_TRIGACK_1,
FTMTP2FTRIGACK(0) => FTMT_P2F_TRIGACK_0,
IRQF2P(19) => Core1_nFIQ,
IRQF2P(18) => Core0_nFIQ,
IRQF2P(17) => Core1_nIRQ,
IRQF2P(16) => Core0_nIRQ,
IRQF2P(15 downto 1) => B"000000000000000",
IRQF2P(0) => IRQ_F2P(0),
IRQP2F(28) => IRQ_P2F_DMAC_ABORT,
IRQP2F(27) => IRQ_P2F_DMAC7,
IRQP2F(26) => IRQ_P2F_DMAC6,
IRQP2F(25) => IRQ_P2F_DMAC5,
IRQP2F(24) => IRQ_P2F_DMAC4,
IRQP2F(23) => IRQ_P2F_DMAC3,
IRQP2F(22) => IRQ_P2F_DMAC2,
IRQP2F(21) => IRQ_P2F_DMAC1,
IRQP2F(20) => IRQ_P2F_DMAC0,
IRQP2F(19) => IRQ_P2F_SMC,
IRQP2F(18) => IRQ_P2F_QSPI,
IRQP2F(17) => IRQ_P2F_CTI,
IRQP2F(16) => IRQ_P2F_GPIO,
IRQP2F(15) => IRQ_P2F_USB0,
IRQP2F(14) => IRQ_P2F_ENET0,
IRQP2F(13) => IRQ_P2F_ENET_WAKE0,
IRQP2F(12) => IRQ_P2F_SDIO0,
IRQP2F(11) => IRQ_P2F_I2C0,
IRQP2F(10) => IRQ_P2F_SPI0,
IRQP2F(9) => IRQ_P2F_UART0,
IRQP2F(8) => IRQ_P2F_CAN0,
IRQP2F(7) => IRQ_P2F_USB1,
IRQP2F(6) => IRQ_P2F_ENET1,
IRQP2F(5) => IRQ_P2F_ENET_WAKE1,
IRQP2F(4) => IRQ_P2F_SDIO1,
IRQP2F(3) => IRQ_P2F_I2C1,
IRQP2F(2) => IRQ_P2F_SPI1,
IRQP2F(1) => IRQ_P2F_UART1,
IRQP2F(0) => IRQ_P2F_CAN1,
MAXIGP0ACLK => M_AXI_GP0_ACLK,
MAXIGP0ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0),
MAXIGP0ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0),
MAXIGP0ARCACHE(3 downto 2) => \^m_axi_gp0_arcache\(3 downto 2),
MAXIGP0ARCACHE(1) => NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED(1),
MAXIGP0ARCACHE(0) => \^m_axi_gp0_arcache\(0),
MAXIGP0ARESETN => M_AXI_GP0_ARESETN,
MAXIGP0ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0),
MAXIGP0ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0),
MAXIGP0ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0),
MAXIGP0ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0),
MAXIGP0ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0),
MAXIGP0ARREADY => M_AXI_GP0_ARREADY,
MAXIGP0ARSIZE(1 downto 0) => \^m_axi_gp0_arsize\(1 downto 0),
MAXIGP0ARVALID => M_AXI_GP0_ARVALID,
MAXIGP0AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0),
MAXIGP0AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0),
MAXIGP0AWCACHE(3 downto 2) => \^m_axi_gp0_awcache\(3 downto 2),
MAXIGP0AWCACHE(1) => NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED(1),
MAXIGP0AWCACHE(0) => \^m_axi_gp0_awcache\(0),
MAXIGP0AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0),
MAXIGP0AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0),
MAXIGP0AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0),
MAXIGP0AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0),
MAXIGP0AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0),
MAXIGP0AWREADY => M_AXI_GP0_AWREADY,
MAXIGP0AWSIZE(1 downto 0) => \^m_axi_gp0_awsize\(1 downto 0),
MAXIGP0AWVALID => M_AXI_GP0_AWVALID,
MAXIGP0BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0),
MAXIGP0BREADY => M_AXI_GP0_BREADY,
MAXIGP0BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0),
MAXIGP0BVALID => M_AXI_GP0_BVALID,
MAXIGP0RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0),
MAXIGP0RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0),
MAXIGP0RLAST => M_AXI_GP0_RLAST,
MAXIGP0RREADY => M_AXI_GP0_RREADY,
MAXIGP0RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0),
MAXIGP0RVALID => M_AXI_GP0_RVALID,
MAXIGP0WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0),
MAXIGP0WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0),
MAXIGP0WLAST => M_AXI_GP0_WLAST,
MAXIGP0WREADY => M_AXI_GP0_WREADY,
MAXIGP0WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0),
MAXIGP0WVALID => M_AXI_GP0_WVALID,
MAXIGP1ACLK => M_AXI_GP1_ACLK,
MAXIGP1ARADDR(31 downto 0) => M_AXI_GP1_ARADDR(31 downto 0),
MAXIGP1ARBURST(1 downto 0) => M_AXI_GP1_ARBURST(1 downto 0),
MAXIGP1ARCACHE(3 downto 2) => \^m_axi_gp1_arcache\(3 downto 2),
MAXIGP1ARCACHE(1) => NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED(1),
MAXIGP1ARCACHE(0) => \^m_axi_gp1_arcache\(0),
MAXIGP1ARESETN => M_AXI_GP1_ARESETN,
MAXIGP1ARID(11 downto 0) => M_AXI_GP1_ARID(11 downto 0),
MAXIGP1ARLEN(3 downto 0) => M_AXI_GP1_ARLEN(3 downto 0),
MAXIGP1ARLOCK(1 downto 0) => M_AXI_GP1_ARLOCK(1 downto 0),
MAXIGP1ARPROT(2 downto 0) => M_AXI_GP1_ARPROT(2 downto 0),
MAXIGP1ARQOS(3 downto 0) => M_AXI_GP1_ARQOS(3 downto 0),
MAXIGP1ARREADY => M_AXI_GP1_ARREADY,
MAXIGP1ARSIZE(1 downto 0) => \^m_axi_gp1_arsize\(1 downto 0),
MAXIGP1ARVALID => M_AXI_GP1_ARVALID,
MAXIGP1AWADDR(31 downto 0) => M_AXI_GP1_AWADDR(31 downto 0),
MAXIGP1AWBURST(1 downto 0) => M_AXI_GP1_AWBURST(1 downto 0),
MAXIGP1AWCACHE(3 downto 2) => \^m_axi_gp1_awcache\(3 downto 2),
MAXIGP1AWCACHE(1) => NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED(1),
MAXIGP1AWCACHE(0) => \^m_axi_gp1_awcache\(0),
MAXIGP1AWID(11 downto 0) => M_AXI_GP1_AWID(11 downto 0),
MAXIGP1AWLEN(3 downto 0) => M_AXI_GP1_AWLEN(3 downto 0),
MAXIGP1AWLOCK(1 downto 0) => M_AXI_GP1_AWLOCK(1 downto 0),
MAXIGP1AWPROT(2 downto 0) => M_AXI_GP1_AWPROT(2 downto 0),
MAXIGP1AWQOS(3 downto 0) => M_AXI_GP1_AWQOS(3 downto 0),
MAXIGP1AWREADY => M_AXI_GP1_AWREADY,
MAXIGP1AWSIZE(1 downto 0) => \^m_axi_gp1_awsize\(1 downto 0),
MAXIGP1AWVALID => M_AXI_GP1_AWVALID,
MAXIGP1BID(11 downto 0) => M_AXI_GP1_BID(11 downto 0),
MAXIGP1BREADY => M_AXI_GP1_BREADY,
MAXIGP1BRESP(1 downto 0) => M_AXI_GP1_BRESP(1 downto 0),
MAXIGP1BVALID => M_AXI_GP1_BVALID,
MAXIGP1RDATA(31 downto 0) => M_AXI_GP1_RDATA(31 downto 0),
MAXIGP1RID(11 downto 0) => M_AXI_GP1_RID(11 downto 0),
MAXIGP1RLAST => M_AXI_GP1_RLAST,
MAXIGP1RREADY => M_AXI_GP1_RREADY,
MAXIGP1RRESP(1 downto 0) => M_AXI_GP1_RRESP(1 downto 0),
MAXIGP1RVALID => M_AXI_GP1_RVALID,
MAXIGP1WDATA(31 downto 0) => M_AXI_GP1_WDATA(31 downto 0),
MAXIGP1WID(11 downto 0) => M_AXI_GP1_WID(11 downto 0),
MAXIGP1WLAST => M_AXI_GP1_WLAST,
MAXIGP1WREADY => M_AXI_GP1_WREADY,
MAXIGP1WSTRB(3 downto 0) => M_AXI_GP1_WSTRB(3 downto 0),
MAXIGP1WVALID => M_AXI_GP1_WVALID,
MIO(53 downto 0) => buffered_MIO(53 downto 0),
PSCLK => buffered_PS_CLK,
PSPORB => buffered_PS_PORB,
PSSRSTB => buffered_PS_SRSTB,
SAXIACPACLK => S_AXI_ACP_ACLK,
SAXIACPARADDR(31 downto 0) => S_AXI_ACP_ARADDR(31 downto 0),
SAXIACPARBURST(1 downto 0) => S_AXI_ACP_ARBURST(1 downto 0),
SAXIACPARCACHE(3 downto 0) => S_AXI_ACP_ARCACHE(3 downto 0),
SAXIACPARESETN => S_AXI_ACP_ARESETN,
SAXIACPARID(2 downto 0) => S_AXI_ACP_ARID(2 downto 0),
SAXIACPARLEN(3 downto 0) => S_AXI_ACP_ARLEN(3 downto 0),
SAXIACPARLOCK(1 downto 0) => S_AXI_ACP_ARLOCK(1 downto 0),
SAXIACPARPROT(2 downto 0) => S_AXI_ACP_ARPROT(2 downto 0),
SAXIACPARQOS(3 downto 0) => S_AXI_ACP_ARQOS(3 downto 0),
SAXIACPARREADY => S_AXI_ACP_ARREADY,
SAXIACPARSIZE(1 downto 0) => S_AXI_ACP_ARSIZE(1 downto 0),
SAXIACPARUSER(4 downto 0) => S_AXI_ACP_ARUSER(4 downto 0),
SAXIACPARVALID => S_AXI_ACP_ARVALID,
SAXIACPAWADDR(31 downto 0) => S_AXI_ACP_AWADDR(31 downto 0),
SAXIACPAWBURST(1 downto 0) => S_AXI_ACP_AWBURST(1 downto 0),
SAXIACPAWCACHE(3 downto 0) => S_AXI_ACP_AWCACHE(3 downto 0),
SAXIACPAWID(2 downto 0) => S_AXI_ACP_AWID(2 downto 0),
SAXIACPAWLEN(3 downto 0) => S_AXI_ACP_AWLEN(3 downto 0),
SAXIACPAWLOCK(1 downto 0) => S_AXI_ACP_AWLOCK(1 downto 0),
SAXIACPAWPROT(2 downto 0) => S_AXI_ACP_AWPROT(2 downto 0),
SAXIACPAWQOS(3 downto 0) => S_AXI_ACP_AWQOS(3 downto 0),
SAXIACPAWREADY => S_AXI_ACP_AWREADY,
SAXIACPAWSIZE(1 downto 0) => S_AXI_ACP_AWSIZE(1 downto 0),
SAXIACPAWUSER(4 downto 0) => S_AXI_ACP_AWUSER(4 downto 0),
SAXIACPAWVALID => S_AXI_ACP_AWVALID,
SAXIACPBID(2 downto 0) => S_AXI_ACP_BID(2 downto 0),
SAXIACPBREADY => S_AXI_ACP_BREADY,
SAXIACPBRESP(1 downto 0) => S_AXI_ACP_BRESP(1 downto 0),
SAXIACPBVALID => S_AXI_ACP_BVALID,
SAXIACPRDATA(63 downto 0) => S_AXI_ACP_RDATA(63 downto 0),
SAXIACPRID(2 downto 0) => S_AXI_ACP_RID(2 downto 0),
SAXIACPRLAST => S_AXI_ACP_RLAST,
SAXIACPRREADY => S_AXI_ACP_RREADY,
SAXIACPRRESP(1 downto 0) => S_AXI_ACP_RRESP(1 downto 0),
SAXIACPRVALID => S_AXI_ACP_RVALID,
SAXIACPWDATA(63 downto 0) => S_AXI_ACP_WDATA(63 downto 0),
SAXIACPWID(2 downto 0) => S_AXI_ACP_WID(2 downto 0),
SAXIACPWLAST => S_AXI_ACP_WLAST,
SAXIACPWREADY => S_AXI_ACP_WREADY,
SAXIACPWSTRB(7 downto 0) => S_AXI_ACP_WSTRB(7 downto 0),
SAXIACPWVALID => S_AXI_ACP_WVALID,
SAXIGP0ACLK => S_AXI_GP0_ACLK,
SAXIGP0ARADDR(31 downto 0) => S_AXI_GP0_ARADDR(31 downto 0),
SAXIGP0ARBURST(1 downto 0) => S_AXI_GP0_ARBURST(1 downto 0),
SAXIGP0ARCACHE(3 downto 0) => S_AXI_GP0_ARCACHE(3 downto 0),
SAXIGP0ARESETN => S_AXI_GP0_ARESETN,
SAXIGP0ARID(5 downto 0) => S_AXI_GP0_ARID(5 downto 0),
SAXIGP0ARLEN(3 downto 0) => S_AXI_GP0_ARLEN(3 downto 0),
SAXIGP0ARLOCK(1 downto 0) => S_AXI_GP0_ARLOCK(1 downto 0),
SAXIGP0ARPROT(2 downto 0) => S_AXI_GP0_ARPROT(2 downto 0),
SAXIGP0ARQOS(3 downto 0) => S_AXI_GP0_ARQOS(3 downto 0),
SAXIGP0ARREADY => S_AXI_GP0_ARREADY,
SAXIGP0ARSIZE(1 downto 0) => S_AXI_GP0_ARSIZE(1 downto 0),
SAXIGP0ARVALID => S_AXI_GP0_ARVALID,
SAXIGP0AWADDR(31 downto 0) => S_AXI_GP0_AWADDR(31 downto 0),
SAXIGP0AWBURST(1 downto 0) => S_AXI_GP0_AWBURST(1 downto 0),
SAXIGP0AWCACHE(3 downto 0) => S_AXI_GP0_AWCACHE(3 downto 0),
SAXIGP0AWID(5 downto 0) => S_AXI_GP0_AWID(5 downto 0),
SAXIGP0AWLEN(3 downto 0) => S_AXI_GP0_AWLEN(3 downto 0),
SAXIGP0AWLOCK(1 downto 0) => S_AXI_GP0_AWLOCK(1 downto 0),
SAXIGP0AWPROT(2 downto 0) => S_AXI_GP0_AWPROT(2 downto 0),
SAXIGP0AWQOS(3 downto 0) => S_AXI_GP0_AWQOS(3 downto 0),
SAXIGP0AWREADY => S_AXI_GP0_AWREADY,
SAXIGP0AWSIZE(1 downto 0) => S_AXI_GP0_AWSIZE(1 downto 0),
SAXIGP0AWVALID => S_AXI_GP0_AWVALID,
SAXIGP0BID(5 downto 0) => S_AXI_GP0_BID(5 downto 0),
SAXIGP0BREADY => S_AXI_GP0_BREADY,
SAXIGP0BRESP(1 downto 0) => S_AXI_GP0_BRESP(1 downto 0),
SAXIGP0BVALID => S_AXI_GP0_BVALID,
SAXIGP0RDATA(31 downto 0) => S_AXI_GP0_RDATA(31 downto 0),
SAXIGP0RID(5 downto 0) => S_AXI_GP0_RID(5 downto 0),
SAXIGP0RLAST => S_AXI_GP0_RLAST,
SAXIGP0RREADY => S_AXI_GP0_RREADY,
SAXIGP0RRESP(1 downto 0) => S_AXI_GP0_RRESP(1 downto 0),
SAXIGP0RVALID => S_AXI_GP0_RVALID,
SAXIGP0WDATA(31 downto 0) => S_AXI_GP0_WDATA(31 downto 0),
SAXIGP0WID(5 downto 0) => S_AXI_GP0_WID(5 downto 0),
SAXIGP0WLAST => S_AXI_GP0_WLAST,
SAXIGP0WREADY => S_AXI_GP0_WREADY,
SAXIGP0WSTRB(3 downto 0) => S_AXI_GP0_WSTRB(3 downto 0),
SAXIGP0WVALID => S_AXI_GP0_WVALID,
SAXIGP1ACLK => S_AXI_GP1_ACLK,
SAXIGP1ARADDR(31 downto 0) => S_AXI_GP1_ARADDR(31 downto 0),
SAXIGP1ARBURST(1 downto 0) => S_AXI_GP1_ARBURST(1 downto 0),
SAXIGP1ARCACHE(3 downto 0) => S_AXI_GP1_ARCACHE(3 downto 0),
SAXIGP1ARESETN => S_AXI_GP1_ARESETN,
SAXIGP1ARID(5 downto 0) => S_AXI_GP1_ARID(5 downto 0),
SAXIGP1ARLEN(3 downto 0) => S_AXI_GP1_ARLEN(3 downto 0),
SAXIGP1ARLOCK(1 downto 0) => S_AXI_GP1_ARLOCK(1 downto 0),
SAXIGP1ARPROT(2 downto 0) => S_AXI_GP1_ARPROT(2 downto 0),
SAXIGP1ARQOS(3 downto 0) => S_AXI_GP1_ARQOS(3 downto 0),
SAXIGP1ARREADY => S_AXI_GP1_ARREADY,
SAXIGP1ARSIZE(1 downto 0) => S_AXI_GP1_ARSIZE(1 downto 0),
SAXIGP1ARVALID => S_AXI_GP1_ARVALID,
SAXIGP1AWADDR(31 downto 0) => S_AXI_GP1_AWADDR(31 downto 0),
SAXIGP1AWBURST(1 downto 0) => S_AXI_GP1_AWBURST(1 downto 0),
SAXIGP1AWCACHE(3 downto 0) => S_AXI_GP1_AWCACHE(3 downto 0),
SAXIGP1AWID(5 downto 0) => S_AXI_GP1_AWID(5 downto 0),
SAXIGP1AWLEN(3 downto 0) => S_AXI_GP1_AWLEN(3 downto 0),
SAXIGP1AWLOCK(1 downto 0) => S_AXI_GP1_AWLOCK(1 downto 0),
SAXIGP1AWPROT(2 downto 0) => S_AXI_GP1_AWPROT(2 downto 0),
SAXIGP1AWQOS(3 downto 0) => S_AXI_GP1_AWQOS(3 downto 0),
SAXIGP1AWREADY => S_AXI_GP1_AWREADY,
SAXIGP1AWSIZE(1 downto 0) => S_AXI_GP1_AWSIZE(1 downto 0),
SAXIGP1AWVALID => S_AXI_GP1_AWVALID,
SAXIGP1BID(5 downto 0) => S_AXI_GP1_BID(5 downto 0),
SAXIGP1BREADY => S_AXI_GP1_BREADY,
SAXIGP1BRESP(1 downto 0) => S_AXI_GP1_BRESP(1 downto 0),
SAXIGP1BVALID => S_AXI_GP1_BVALID,
SAXIGP1RDATA(31 downto 0) => S_AXI_GP1_RDATA(31 downto 0),
SAXIGP1RID(5 downto 0) => S_AXI_GP1_RID(5 downto 0),
SAXIGP1RLAST => S_AXI_GP1_RLAST,
SAXIGP1RREADY => S_AXI_GP1_RREADY,
SAXIGP1RRESP(1 downto 0) => S_AXI_GP1_RRESP(1 downto 0),
SAXIGP1RVALID => S_AXI_GP1_RVALID,
SAXIGP1WDATA(31 downto 0) => S_AXI_GP1_WDATA(31 downto 0),
SAXIGP1WID(5 downto 0) => S_AXI_GP1_WID(5 downto 0),
SAXIGP1WLAST => S_AXI_GP1_WLAST,
SAXIGP1WREADY => S_AXI_GP1_WREADY,
SAXIGP1WSTRB(3 downto 0) => S_AXI_GP1_WSTRB(3 downto 0),
SAXIGP1WVALID => S_AXI_GP1_WVALID,
SAXIHP0ACLK => S_AXI_HP0_ACLK,
SAXIHP0ARADDR(31 downto 0) => S_AXI_HP0_ARADDR(31 downto 0),
SAXIHP0ARBURST(1 downto 0) => S_AXI_HP0_ARBURST(1 downto 0),
SAXIHP0ARCACHE(3 downto 0) => S_AXI_HP0_ARCACHE(3 downto 0),
SAXIHP0ARESETN => S_AXI_HP0_ARESETN,
SAXIHP0ARID(5 downto 0) => S_AXI_HP0_ARID(5 downto 0),
SAXIHP0ARLEN(3 downto 0) => S_AXI_HP0_ARLEN(3 downto 0),
SAXIHP0ARLOCK(1 downto 0) => S_AXI_HP0_ARLOCK(1 downto 0),
SAXIHP0ARPROT(2 downto 0) => S_AXI_HP0_ARPROT(2 downto 0),
SAXIHP0ARQOS(3 downto 0) => S_AXI_HP0_ARQOS(3 downto 0),
SAXIHP0ARREADY => S_AXI_HP0_ARREADY,
SAXIHP0ARSIZE(1 downto 0) => S_AXI_HP0_ARSIZE(1 downto 0),
SAXIHP0ARVALID => S_AXI_HP0_ARVALID,
SAXIHP0AWADDR(31 downto 0) => S_AXI_HP0_AWADDR(31 downto 0),
SAXIHP0AWBURST(1 downto 0) => S_AXI_HP0_AWBURST(1 downto 0),
SAXIHP0AWCACHE(3 downto 0) => S_AXI_HP0_AWCACHE(3 downto 0),
SAXIHP0AWID(5 downto 0) => S_AXI_HP0_AWID(5 downto 0),
SAXIHP0AWLEN(3 downto 0) => S_AXI_HP0_AWLEN(3 downto 0),
SAXIHP0AWLOCK(1 downto 0) => S_AXI_HP0_AWLOCK(1 downto 0),
SAXIHP0AWPROT(2 downto 0) => S_AXI_HP0_AWPROT(2 downto 0),
SAXIHP0AWQOS(3 downto 0) => S_AXI_HP0_AWQOS(3 downto 0),
SAXIHP0AWREADY => S_AXI_HP0_AWREADY,
SAXIHP0AWSIZE(1 downto 0) => S_AXI_HP0_AWSIZE(1 downto 0),
SAXIHP0AWVALID => S_AXI_HP0_AWVALID,
SAXIHP0BID(5 downto 0) => S_AXI_HP0_BID(5 downto 0),
SAXIHP0BREADY => S_AXI_HP0_BREADY,
SAXIHP0BRESP(1 downto 0) => S_AXI_HP0_BRESP(1 downto 0),
SAXIHP0BVALID => S_AXI_HP0_BVALID,
SAXIHP0RACOUNT(2 downto 0) => S_AXI_HP0_RACOUNT(2 downto 0),
SAXIHP0RCOUNT(7 downto 0) => S_AXI_HP0_RCOUNT(7 downto 0),
SAXIHP0RDATA(63 downto 0) => S_AXI_HP0_RDATA(63 downto 0),
SAXIHP0RDISSUECAP1EN => S_AXI_HP0_RDISSUECAP1_EN,
SAXIHP0RID(5 downto 0) => S_AXI_HP0_RID(5 downto 0),
SAXIHP0RLAST => S_AXI_HP0_RLAST,
SAXIHP0RREADY => S_AXI_HP0_RREADY,
SAXIHP0RRESP(1 downto 0) => S_AXI_HP0_RRESP(1 downto 0),
SAXIHP0RVALID => S_AXI_HP0_RVALID,
SAXIHP0WACOUNT(5 downto 0) => S_AXI_HP0_WACOUNT(5 downto 0),
SAXIHP0WCOUNT(7 downto 0) => S_AXI_HP0_WCOUNT(7 downto 0),
SAXIHP0WDATA(63 downto 0) => S_AXI_HP0_WDATA(63 downto 0),
SAXIHP0WID(5 downto 0) => S_AXI_HP0_WID(5 downto 0),
SAXIHP0WLAST => S_AXI_HP0_WLAST,
SAXIHP0WREADY => S_AXI_HP0_WREADY,
SAXIHP0WRISSUECAP1EN => S_AXI_HP0_WRISSUECAP1_EN,
SAXIHP0WSTRB(7 downto 0) => S_AXI_HP0_WSTRB(7 downto 0),
SAXIHP0WVALID => S_AXI_HP0_WVALID,
SAXIHP1ACLK => S_AXI_HP1_ACLK,
SAXIHP1ARADDR(31 downto 0) => S_AXI_HP1_ARADDR(31 downto 0),
SAXIHP1ARBURST(1 downto 0) => S_AXI_HP1_ARBURST(1 downto 0),
SAXIHP1ARCACHE(3 downto 0) => S_AXI_HP1_ARCACHE(3 downto 0),
SAXIHP1ARESETN => S_AXI_HP1_ARESETN,
SAXIHP1ARID(5 downto 0) => S_AXI_HP1_ARID(5 downto 0),
SAXIHP1ARLEN(3 downto 0) => S_AXI_HP1_ARLEN(3 downto 0),
SAXIHP1ARLOCK(1 downto 0) => S_AXI_HP1_ARLOCK(1 downto 0),
SAXIHP1ARPROT(2 downto 0) => S_AXI_HP1_ARPROT(2 downto 0),
SAXIHP1ARQOS(3 downto 0) => S_AXI_HP1_ARQOS(3 downto 0),
SAXIHP1ARREADY => S_AXI_HP1_ARREADY,
SAXIHP1ARSIZE(1 downto 0) => S_AXI_HP1_ARSIZE(1 downto 0),
SAXIHP1ARVALID => S_AXI_HP1_ARVALID,
SAXIHP1AWADDR(31 downto 0) => S_AXI_HP1_AWADDR(31 downto 0),
SAXIHP1AWBURST(1 downto 0) => S_AXI_HP1_AWBURST(1 downto 0),
SAXIHP1AWCACHE(3 downto 0) => S_AXI_HP1_AWCACHE(3 downto 0),
SAXIHP1AWID(5 downto 0) => S_AXI_HP1_AWID(5 downto 0),
SAXIHP1AWLEN(3 downto 0) => S_AXI_HP1_AWLEN(3 downto 0),
SAXIHP1AWLOCK(1 downto 0) => S_AXI_HP1_AWLOCK(1 downto 0),
SAXIHP1AWPROT(2 downto 0) => S_AXI_HP1_AWPROT(2 downto 0),
SAXIHP1AWQOS(3 downto 0) => S_AXI_HP1_AWQOS(3 downto 0),
SAXIHP1AWREADY => S_AXI_HP1_AWREADY,
SAXIHP1AWSIZE(1 downto 0) => S_AXI_HP1_AWSIZE(1 downto 0),
SAXIHP1AWVALID => S_AXI_HP1_AWVALID,
SAXIHP1BID(5 downto 0) => S_AXI_HP1_BID(5 downto 0),
SAXIHP1BREADY => S_AXI_HP1_BREADY,
SAXIHP1BRESP(1 downto 0) => S_AXI_HP1_BRESP(1 downto 0),
SAXIHP1BVALID => S_AXI_HP1_BVALID,
SAXIHP1RACOUNT(2 downto 0) => S_AXI_HP1_RACOUNT(2 downto 0),
SAXIHP1RCOUNT(7 downto 0) => S_AXI_HP1_RCOUNT(7 downto 0),
SAXIHP1RDATA(63 downto 0) => S_AXI_HP1_RDATA(63 downto 0),
SAXIHP1RDISSUECAP1EN => S_AXI_HP1_RDISSUECAP1_EN,
SAXIHP1RID(5 downto 0) => S_AXI_HP1_RID(5 downto 0),
SAXIHP1RLAST => S_AXI_HP1_RLAST,
SAXIHP1RREADY => S_AXI_HP1_RREADY,
SAXIHP1RRESP(1 downto 0) => S_AXI_HP1_RRESP(1 downto 0),
SAXIHP1RVALID => S_AXI_HP1_RVALID,
SAXIHP1WACOUNT(5 downto 0) => S_AXI_HP1_WACOUNT(5 downto 0),
SAXIHP1WCOUNT(7 downto 0) => S_AXI_HP1_WCOUNT(7 downto 0),
SAXIHP1WDATA(63 downto 0) => S_AXI_HP1_WDATA(63 downto 0),
SAXIHP1WID(5 downto 0) => S_AXI_HP1_WID(5 downto 0),
SAXIHP1WLAST => S_AXI_HP1_WLAST,
SAXIHP1WREADY => S_AXI_HP1_WREADY,
SAXIHP1WRISSUECAP1EN => S_AXI_HP1_WRISSUECAP1_EN,
SAXIHP1WSTRB(7 downto 0) => S_AXI_HP1_WSTRB(7 downto 0),
SAXIHP1WVALID => S_AXI_HP1_WVALID,
SAXIHP2ACLK => S_AXI_HP2_ACLK,
SAXIHP2ARADDR(31 downto 0) => S_AXI_HP2_ARADDR(31 downto 0),
SAXIHP2ARBURST(1 downto 0) => S_AXI_HP2_ARBURST(1 downto 0),
SAXIHP2ARCACHE(3 downto 0) => S_AXI_HP2_ARCACHE(3 downto 0),
SAXIHP2ARESETN => S_AXI_HP2_ARESETN,
SAXIHP2ARID(5 downto 0) => S_AXI_HP2_ARID(5 downto 0),
SAXIHP2ARLEN(3 downto 0) => S_AXI_HP2_ARLEN(3 downto 0),
SAXIHP2ARLOCK(1 downto 0) => S_AXI_HP2_ARLOCK(1 downto 0),
SAXIHP2ARPROT(2 downto 0) => S_AXI_HP2_ARPROT(2 downto 0),
SAXIHP2ARQOS(3 downto 0) => S_AXI_HP2_ARQOS(3 downto 0),
SAXIHP2ARREADY => S_AXI_HP2_ARREADY,
SAXIHP2ARSIZE(1 downto 0) => S_AXI_HP2_ARSIZE(1 downto 0),
SAXIHP2ARVALID => S_AXI_HP2_ARVALID,
SAXIHP2AWADDR(31 downto 0) => S_AXI_HP2_AWADDR(31 downto 0),
SAXIHP2AWBURST(1 downto 0) => S_AXI_HP2_AWBURST(1 downto 0),
SAXIHP2AWCACHE(3 downto 0) => S_AXI_HP2_AWCACHE(3 downto 0),
SAXIHP2AWID(5 downto 0) => S_AXI_HP2_AWID(5 downto 0),
SAXIHP2AWLEN(3 downto 0) => S_AXI_HP2_AWLEN(3 downto 0),
SAXIHP2AWLOCK(1 downto 0) => S_AXI_HP2_AWLOCK(1 downto 0),
SAXIHP2AWPROT(2 downto 0) => S_AXI_HP2_AWPROT(2 downto 0),
SAXIHP2AWQOS(3 downto 0) => S_AXI_HP2_AWQOS(3 downto 0),
SAXIHP2AWREADY => S_AXI_HP2_AWREADY,
SAXIHP2AWSIZE(1 downto 0) => S_AXI_HP2_AWSIZE(1 downto 0),
SAXIHP2AWVALID => S_AXI_HP2_AWVALID,
SAXIHP2BID(5 downto 0) => S_AXI_HP2_BID(5 downto 0),
SAXIHP2BREADY => S_AXI_HP2_BREADY,
SAXIHP2BRESP(1 downto 0) => S_AXI_HP2_BRESP(1 downto 0),
SAXIHP2BVALID => S_AXI_HP2_BVALID,
SAXIHP2RACOUNT(2 downto 0) => S_AXI_HP2_RACOUNT(2 downto 0),
SAXIHP2RCOUNT(7 downto 0) => S_AXI_HP2_RCOUNT(7 downto 0),
SAXIHP2RDATA(63 downto 0) => S_AXI_HP2_RDATA(63 downto 0),
SAXIHP2RDISSUECAP1EN => S_AXI_HP2_RDISSUECAP1_EN,
SAXIHP2RID(5 downto 0) => S_AXI_HP2_RID(5 downto 0),
SAXIHP2RLAST => S_AXI_HP2_RLAST,
SAXIHP2RREADY => S_AXI_HP2_RREADY,
SAXIHP2RRESP(1 downto 0) => S_AXI_HP2_RRESP(1 downto 0),
SAXIHP2RVALID => S_AXI_HP2_RVALID,
SAXIHP2WACOUNT(5 downto 0) => S_AXI_HP2_WACOUNT(5 downto 0),
SAXIHP2WCOUNT(7 downto 0) => S_AXI_HP2_WCOUNT(7 downto 0),
SAXIHP2WDATA(63 downto 0) => S_AXI_HP2_WDATA(63 downto 0),
SAXIHP2WID(5 downto 0) => S_AXI_HP2_WID(5 downto 0),
SAXIHP2WLAST => S_AXI_HP2_WLAST,
SAXIHP2WREADY => S_AXI_HP2_WREADY,
SAXIHP2WRISSUECAP1EN => S_AXI_HP2_WRISSUECAP1_EN,
SAXIHP2WSTRB(7 downto 0) => S_AXI_HP2_WSTRB(7 downto 0),
SAXIHP2WVALID => S_AXI_HP2_WVALID,
SAXIHP3ACLK => S_AXI_HP3_ACLK,
SAXIHP3ARADDR(31 downto 0) => S_AXI_HP3_ARADDR(31 downto 0),
SAXIHP3ARBURST(1 downto 0) => S_AXI_HP3_ARBURST(1 downto 0),
SAXIHP3ARCACHE(3 downto 0) => S_AXI_HP3_ARCACHE(3 downto 0),
SAXIHP3ARESETN => S_AXI_HP3_ARESETN,
SAXIHP3ARID(5 downto 0) => S_AXI_HP3_ARID(5 downto 0),
SAXIHP3ARLEN(3 downto 0) => S_AXI_HP3_ARLEN(3 downto 0),
SAXIHP3ARLOCK(1 downto 0) => S_AXI_HP3_ARLOCK(1 downto 0),
SAXIHP3ARPROT(2 downto 0) => S_AXI_HP3_ARPROT(2 downto 0),
SAXIHP3ARQOS(3 downto 0) => S_AXI_HP3_ARQOS(3 downto 0),
SAXIHP3ARREADY => S_AXI_HP3_ARREADY,
SAXIHP3ARSIZE(1 downto 0) => S_AXI_HP3_ARSIZE(1 downto 0),
SAXIHP3ARVALID => S_AXI_HP3_ARVALID,
SAXIHP3AWADDR(31 downto 0) => S_AXI_HP3_AWADDR(31 downto 0),
SAXIHP3AWBURST(1 downto 0) => S_AXI_HP3_AWBURST(1 downto 0),
SAXIHP3AWCACHE(3 downto 0) => S_AXI_HP3_AWCACHE(3 downto 0),
SAXIHP3AWID(5 downto 0) => S_AXI_HP3_AWID(5 downto 0),
SAXIHP3AWLEN(3 downto 0) => S_AXI_HP3_AWLEN(3 downto 0),
SAXIHP3AWLOCK(1 downto 0) => S_AXI_HP3_AWLOCK(1 downto 0),
SAXIHP3AWPROT(2 downto 0) => S_AXI_HP3_AWPROT(2 downto 0),
SAXIHP3AWQOS(3 downto 0) => S_AXI_HP3_AWQOS(3 downto 0),
SAXIHP3AWREADY => S_AXI_HP3_AWREADY,
SAXIHP3AWSIZE(1 downto 0) => S_AXI_HP3_AWSIZE(1 downto 0),
SAXIHP3AWVALID => S_AXI_HP3_AWVALID,
SAXIHP3BID(5 downto 0) => S_AXI_HP3_BID(5 downto 0),
SAXIHP3BREADY => S_AXI_HP3_BREADY,
SAXIHP3BRESP(1 downto 0) => S_AXI_HP3_BRESP(1 downto 0),
SAXIHP3BVALID => S_AXI_HP3_BVALID,
SAXIHP3RACOUNT(2 downto 0) => S_AXI_HP3_RACOUNT(2 downto 0),
SAXIHP3RCOUNT(7 downto 0) => S_AXI_HP3_RCOUNT(7 downto 0),
SAXIHP3RDATA(63 downto 0) => S_AXI_HP3_RDATA(63 downto 0),
SAXIHP3RDISSUECAP1EN => S_AXI_HP3_RDISSUECAP1_EN,
SAXIHP3RID(5 downto 0) => S_AXI_HP3_RID(5 downto 0),
SAXIHP3RLAST => S_AXI_HP3_RLAST,
SAXIHP3RREADY => S_AXI_HP3_RREADY,
SAXIHP3RRESP(1 downto 0) => S_AXI_HP3_RRESP(1 downto 0),
SAXIHP3RVALID => S_AXI_HP3_RVALID,
SAXIHP3WACOUNT(5 downto 0) => S_AXI_HP3_WACOUNT(5 downto 0),
SAXIHP3WCOUNT(7 downto 0) => S_AXI_HP3_WCOUNT(7 downto 0),
SAXIHP3WDATA(63 downto 0) => S_AXI_HP3_WDATA(63 downto 0),
SAXIHP3WID(5 downto 0) => S_AXI_HP3_WID(5 downto 0),
SAXIHP3WLAST => S_AXI_HP3_WLAST,
SAXIHP3WREADY => S_AXI_HP3_WREADY,
SAXIHP3WRISSUECAP1EN => S_AXI_HP3_WRISSUECAP1_EN,
SAXIHP3WSTRB(7 downto 0) => S_AXI_HP3_WSTRB(7 downto 0),
SAXIHP3WVALID => S_AXI_HP3_WVALID
);
PS_CLK_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_CLK,
PAD => PS_CLK
);
PS_PORB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_PORB,
PAD => PS_PORB
);
PS_SRSTB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_SRSTB,
PAD => PS_SRSTB
);
SDIO0_CMD_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_CMD_T_n,
O => SDIO0_CMD_T
);
\SDIO0_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(0),
O => SDIO0_DATA_T(0)
);
\SDIO0_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(1),
O => SDIO0_DATA_T(1)
);
\SDIO0_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(2),
O => SDIO0_DATA_T(2)
);
\SDIO0_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(3),
O => SDIO0_DATA_T(3)
);
SDIO1_CMD_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_CMD_T_n,
O => SDIO1_CMD_T
);
\SDIO1_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(0),
O => SDIO1_DATA_T(0)
);
\SDIO1_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(1),
O => SDIO1_DATA_T(1)
);
\SDIO1_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(2),
O => SDIO1_DATA_T(2)
);
\SDIO1_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(3),
O => SDIO1_DATA_T(3)
);
SPI0_MISO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_MISO_T_n,
O => SPI0_MISO_T
);
SPI0_MOSI_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_MOSI_T_n,
O => SPI0_MOSI_T
);
SPI0_SCLK_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_SCLK_T_n,
O => SPI0_SCLK_T
);
SPI0_SS_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_SS_T_n,
O => SPI0_SS_T
);
SPI1_MISO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_MISO_T_n,
O => SPI1_MISO_T
);
SPI1_MOSI_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_MOSI_T_n,
O => SPI1_MOSI_T
);
SPI1_SCLK_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_SCLK_T_n,
O => SPI1_SCLK_T
);
SPI1_SS_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_SS_T_n,
O => SPI1_SS_T
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
\buffer_fclk_clk_0.FCLK_CLK_0_BUFG\: unisim.vcomponents.BUFG
port map (
I => FCLK_CLK_unbuffered(0),
O => FCLK_CLK0
);
\genblk13[0].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(0),
PAD => MIO(0)
);
\genblk13[10].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(10),
PAD => MIO(10)
);
\genblk13[11].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(11),
PAD => MIO(11)
);
\genblk13[12].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(12),
PAD => MIO(12)
);
\genblk13[13].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(13),
PAD => MIO(13)
);
\genblk13[14].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(14),
PAD => MIO(14)
);
\genblk13[15].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(15),
PAD => MIO(15)
);
\genblk13[16].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(16),
PAD => MIO(16)
);
\genblk13[17].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(17),
PAD => MIO(17)
);
\genblk13[18].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(18),
PAD => MIO(18)
);
\genblk13[19].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(19),
PAD => MIO(19)
);
\genblk13[1].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(1),
PAD => MIO(1)
);
\genblk13[20].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(20),
PAD => MIO(20)
);
\genblk13[21].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(21),
PAD => MIO(21)
);
\genblk13[22].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(22),
PAD => MIO(22)
);
\genblk13[23].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(23),
PAD => MIO(23)
);
\genblk13[24].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(24),
PAD => MIO(24)
);
\genblk13[25].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(25),
PAD => MIO(25)
);
\genblk13[26].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(26),
PAD => MIO(26)
);
\genblk13[27].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(27),
PAD => MIO(27)
);
\genblk13[28].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(28),
PAD => MIO(28)
);
\genblk13[29].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(29),
PAD => MIO(29)
);
\genblk13[2].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(2),
PAD => MIO(2)
);
\genblk13[30].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(30),
PAD => MIO(30)
);
\genblk13[31].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(31),
PAD => MIO(31)
);
\genblk13[32].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(32),
PAD => MIO(32)
);
\genblk13[33].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(33),
PAD => MIO(33)
);
\genblk13[34].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(34),
PAD => MIO(34)
);
\genblk13[35].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(35),
PAD => MIO(35)
);
\genblk13[36].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(36),
PAD => MIO(36)
);
\genblk13[37].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(37),
PAD => MIO(37)
);
\genblk13[38].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(38),
PAD => MIO(38)
);
\genblk13[39].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(39),
PAD => MIO(39)
);
\genblk13[3].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(3),
PAD => MIO(3)
);
\genblk13[40].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(40),
PAD => MIO(40)
);
\genblk13[41].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(41),
PAD => MIO(41)
);
\genblk13[42].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(42),
PAD => MIO(42)
);
\genblk13[43].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(43),
PAD => MIO(43)
);
\genblk13[44].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(44),
PAD => MIO(44)
);
\genblk13[45].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(45),
PAD => MIO(45)
);
\genblk13[46].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(46),
PAD => MIO(46)
);
\genblk13[47].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(47),
PAD => MIO(47)
);
\genblk13[48].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(48),
PAD => MIO(48)
);
\genblk13[49].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(49),
PAD => MIO(49)
);
\genblk13[4].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(4),
PAD => MIO(4)
);
\genblk13[50].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(50),
PAD => MIO(50)
);
\genblk13[51].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(51),
PAD => MIO(51)
);
\genblk13[52].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(52),
PAD => MIO(52)
);
\genblk13[53].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(53),
PAD => MIO(53)
);
\genblk13[5].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(5),
PAD => MIO(5)
);
\genblk13[6].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(6),
PAD => MIO(6)
);
\genblk13[7].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(7),
PAD => MIO(7)
);
\genblk13[8].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(8),
PAD => MIO(8)
);
\genblk13[9].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(9),
PAD => MIO(9)
);
\genblk14[0].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(0),
PAD => DDR_BankAddr(0)
);
\genblk14[1].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(1),
PAD => DDR_BankAddr(1)
);
\genblk14[2].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(2),
PAD => DDR_BankAddr(2)
);
\genblk15[0].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(0),
PAD => DDR_Addr(0)
);
\genblk15[10].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(10),
PAD => DDR_Addr(10)
);
\genblk15[11].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(11),
PAD => DDR_Addr(11)
);
\genblk15[12].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(12),
PAD => DDR_Addr(12)
);
\genblk15[13].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(13),
PAD => DDR_Addr(13)
);
\genblk15[14].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(14),
PAD => DDR_Addr(14)
);
\genblk15[1].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(1),
PAD => DDR_Addr(1)
);
\genblk15[2].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(2),
PAD => DDR_Addr(2)
);
\genblk15[3].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(3),
PAD => DDR_Addr(3)
);
\genblk15[4].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(4),
PAD => DDR_Addr(4)
);
\genblk15[5].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(5),
PAD => DDR_Addr(5)
);
\genblk15[6].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(6),
PAD => DDR_Addr(6)
);
\genblk15[7].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(7),
PAD => DDR_Addr(7)
);
\genblk15[8].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(8),
PAD => DDR_Addr(8)
);
\genblk15[9].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(9),
PAD => DDR_Addr(9)
);
\genblk16[0].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(0),
PAD => DDR_DM(0)
);
\genblk16[1].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(1),
PAD => DDR_DM(1)
);
\genblk16[2].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(2),
PAD => DDR_DM(2)
);
\genblk16[3].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(3),
PAD => DDR_DM(3)
);
\genblk17[0].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(0),
PAD => DDR_DQ(0)
);
\genblk17[10].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(10),
PAD => DDR_DQ(10)
);
\genblk17[11].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(11),
PAD => DDR_DQ(11)
);
\genblk17[12].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(12),
PAD => DDR_DQ(12)
);
\genblk17[13].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(13),
PAD => DDR_DQ(13)
);
\genblk17[14].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(14),
PAD => DDR_DQ(14)
);
\genblk17[15].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(15),
PAD => DDR_DQ(15)
);
\genblk17[16].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(16),
PAD => DDR_DQ(16)
);
\genblk17[17].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(17),
PAD => DDR_DQ(17)
);
\genblk17[18].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(18),
PAD => DDR_DQ(18)
);
\genblk17[19].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(19),
PAD => DDR_DQ(19)
);
\genblk17[1].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(1),
PAD => DDR_DQ(1)
);
\genblk17[20].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(20),
PAD => DDR_DQ(20)
);
\genblk17[21].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(21),
PAD => DDR_DQ(21)
);
\genblk17[22].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(22),
PAD => DDR_DQ(22)
);
\genblk17[23].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(23),
PAD => DDR_DQ(23)
);
\genblk17[24].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(24),
PAD => DDR_DQ(24)
);
\genblk17[25].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(25),
PAD => DDR_DQ(25)
);
\genblk17[26].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(26),
PAD => DDR_DQ(26)
);
\genblk17[27].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(27),
PAD => DDR_DQ(27)
);
\genblk17[28].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(28),
PAD => DDR_DQ(28)
);
\genblk17[29].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(29),
PAD => DDR_DQ(29)
);
\genblk17[2].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(2),
PAD => DDR_DQ(2)
);
\genblk17[30].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(30),
PAD => DDR_DQ(30)
);
\genblk17[31].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(31),
PAD => DDR_DQ(31)
);
\genblk17[3].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(3),
PAD => DDR_DQ(3)
);
\genblk17[4].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(4),
PAD => DDR_DQ(4)
);
\genblk17[5].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(5),
PAD => DDR_DQ(5)
);
\genblk17[6].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(6),
PAD => DDR_DQ(6)
);
\genblk17[7].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(7),
PAD => DDR_DQ(7)
);
\genblk17[8].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(8),
PAD => DDR_DQ(8)
);
\genblk17[9].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(9),
PAD => DDR_DQ(9)
);
\genblk18[0].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(0),
PAD => DDR_DQS_n(0)
);
\genblk18[1].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(1),
PAD => DDR_DQS_n(1)
);
\genblk18[2].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(2),
PAD => DDR_DQS_n(2)
);
\genblk18[3].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(3),
PAD => DDR_DQS_n(3)
);
\genblk19[0].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(0),
PAD => DDR_DQS(0)
);
\genblk19[1].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(1),
PAD => DDR_DQS(1)
);
\genblk19[2].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(2),
PAD => DDR_DQS(2)
);
\genblk19[3].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(3),
PAD => DDR_DQS(3)
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[0]\
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[0]\(1)
);
i_10: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[7]\(1)
);
i_11: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[7]\(0)
);
i_12: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[6]\(1)
);
i_13: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[6]\(0)
);
i_14: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[5]\(1)
);
i_15: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[5]\(0)
);
i_16: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[4]\(1)
);
i_17: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[4]\(0)
);
i_18: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[3]\(1)
);
i_19: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[3]\(0)
);
i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[0]\(0)
);
i_20: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[2]\(1)
);
i_21: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[2]\(0)
);
i_22: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[1]\(1)
);
i_23: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[1]\(0)
);
i_3: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[7]\
);
i_4: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[6]\
);
i_5: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[5]\
);
i_6: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[4]\
);
i_7: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[3]\
);
i_8: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[2]\
);
i_9: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[1]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_processing_system7_0_2 is
port (
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of zynq_design_1_processing_system7_0_2 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of zynq_design_1_processing_system7_0_2 : entity is "zynq_design_1_processing_system7_0_2,processing_system7_v5_5_processing_system7,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of zynq_design_1_processing_system7_0_2 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of zynq_design_1_processing_system7_0_2 : entity is "processing_system7_v5_5_processing_system7,Vivado 2017.2";
end zynq_design_1_processing_system7_0_2;
architecture STRUCTURE of zynq_design_1_processing_system7_0_2 is
signal NLW_inst_CAN0_PHY_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_CAN1_PHY_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_MDC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_MDC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_EVENT_EVENTO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET1_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET2_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET3_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SCL_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SCL_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SDA_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SDA_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SCL_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SCL_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SDA_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SDA_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CAN0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CAN1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CTI_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_GPIO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_I2C0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_I2C1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_QSPI_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SMC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SPI0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SPI1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_UART0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_UART1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_USB0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_USB1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_PJTAG_TDO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_BUSPOW_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CLK_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CMD_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CMD_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_LED_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_BUSPOW_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CLK_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CMD_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CMD_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_LED_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MISO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MISO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MOSI_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MOSI_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SCLK_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SCLK_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS1_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS2_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MISO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MISO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MOSI_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MOSI_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SCLK_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SCLK_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS1_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS2_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TRACE_CLK_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TRACE_CTL_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_DTRN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_RTSN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_DTRN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_RTSN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_WDT_RST_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA1_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA2_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA3_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_ENET0_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_ENET1_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_EVENT_STANDBYWFE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_EVENT_STANDBYWFI_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_GPIO_O_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_GPIO_T_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO0_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_SDIO0_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO0_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO1_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_SDIO1_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO1_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_S_AXI_ACP_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_ACP_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_GP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_GP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP2_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP2_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP3_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP3_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_TRACE_DATA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_USB1_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_DM_WIDTH : integer;
attribute C_DM_WIDTH of inst : label is 4;
attribute C_DQS_WIDTH : integer;
attribute C_DQS_WIDTH of inst : label is 4;
attribute C_DQ_WIDTH : integer;
attribute C_DQ_WIDTH of inst : label is 32;
attribute C_EMIO_GPIO_WIDTH : integer;
attribute C_EMIO_GPIO_WIDTH of inst : label is 64;
attribute C_EN_EMIO_ENET0 : integer;
attribute C_EN_EMIO_ENET0 of inst : label is 0;
attribute C_EN_EMIO_ENET1 : integer;
attribute C_EN_EMIO_ENET1 of inst : label is 0;
attribute C_EN_EMIO_PJTAG : integer;
attribute C_EN_EMIO_PJTAG of inst : label is 0;
attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of inst : label is 0;
attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of inst : label is "TRUE";
attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of inst : label is "FALSE";
attribute C_FCLK_CLK2_BUF : string;
attribute C_FCLK_CLK2_BUF of inst : label is "FALSE";
attribute C_FCLK_CLK3_BUF : string;
attribute C_FCLK_CLK3_BUF of inst : label is "FALSE";
attribute C_GP0_EN_MODIFIABLE_TXN : integer;
attribute C_GP0_EN_MODIFIABLE_TXN of inst : label is 1;
attribute C_GP1_EN_MODIFIABLE_TXN : integer;
attribute C_GP1_EN_MODIFIABLE_TXN of inst : label is 1;
attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
attribute C_INCLUDE_ACP_TRANS_CHECK of inst : label is 0;
attribute C_INCLUDE_TRACE_BUFFER : integer;
attribute C_INCLUDE_TRACE_BUFFER of inst : label is 0;
attribute C_IRQ_F2P_MODE : string;
attribute C_IRQ_F2P_MODE of inst : label is "DIRECT";
attribute C_MIO_PRIMITIVE : integer;
attribute C_MIO_PRIMITIVE of inst : label is 54;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of inst : label is 0;
attribute C_M_AXI_GP0_ID_WIDTH : integer;
attribute C_M_AXI_GP0_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of inst : label is 0;
attribute C_M_AXI_GP1_ID_WIDTH : integer;
attribute C_M_AXI_GP1_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of inst : label is 12;
attribute C_NUM_F2P_INTR_INPUTS : integer;
attribute C_NUM_F2P_INTR_INPUTS of inst : label is 1;
attribute C_PACKAGE_NAME : string;
attribute C_PACKAGE_NAME of inst : label is "clg484";
attribute C_PS7_SI_REV : string;
attribute C_PS7_SI_REV of inst : label is "PRODUCTION";
attribute C_S_AXI_ACP_ARUSER_VAL : integer;
attribute C_S_AXI_ACP_ARUSER_VAL of inst : label is 31;
attribute C_S_AXI_ACP_AWUSER_VAL : integer;
attribute C_S_AXI_ACP_AWUSER_VAL of inst : label is 31;
attribute C_S_AXI_ACP_ID_WIDTH : integer;
attribute C_S_AXI_ACP_ID_WIDTH of inst : label is 3;
attribute C_S_AXI_GP0_ID_WIDTH : integer;
attribute C_S_AXI_GP0_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_GP1_ID_WIDTH : integer;
attribute C_S_AXI_GP1_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP0_DATA_WIDTH : integer;
attribute C_S_AXI_HP0_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP0_ID_WIDTH : integer;
attribute C_S_AXI_HP0_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP1_DATA_WIDTH : integer;
attribute C_S_AXI_HP1_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP1_ID_WIDTH : integer;
attribute C_S_AXI_HP1_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP2_DATA_WIDTH : integer;
attribute C_S_AXI_HP2_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP2_ID_WIDTH : integer;
attribute C_S_AXI_HP2_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP3_DATA_WIDTH : integer;
attribute C_S_AXI_HP3_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP3_ID_WIDTH : integer;
attribute C_S_AXI_HP3_ID_WIDTH of inst : label is 6;
attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
attribute C_TRACE_BUFFER_CLOCK_DELAY of inst : label is 12;
attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
attribute C_TRACE_BUFFER_FIFO_SIZE of inst : label is 128;
attribute C_TRACE_INTERNAL_WIDTH : integer;
attribute C_TRACE_INTERNAL_WIDTH of inst : label is 2;
attribute C_TRACE_PIPELINE_WIDTH : integer;
attribute C_TRACE_PIPELINE_WIDTH of inst : label is 8;
attribute C_USE_AXI_NONSECURE : integer;
attribute C_USE_AXI_NONSECURE of inst : label is 0;
attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
attribute C_USE_DEFAULT_ACP_USER_VAL of inst : label is 0;
attribute C_USE_M_AXI_GP0 : integer;
attribute C_USE_M_AXI_GP0 of inst : label is 1;
attribute C_USE_M_AXI_GP1 : integer;
attribute C_USE_M_AXI_GP1 of inst : label is 0;
attribute C_USE_S_AXI_ACP : integer;
attribute C_USE_S_AXI_ACP of inst : label is 0;
attribute C_USE_S_AXI_GP0 : integer;
attribute C_USE_S_AXI_GP0 of inst : label is 0;
attribute C_USE_S_AXI_GP1 : integer;
attribute C_USE_S_AXI_GP1 of inst : label is 0;
attribute C_USE_S_AXI_HP0 : integer;
attribute C_USE_S_AXI_HP0 of inst : label is 0;
attribute C_USE_S_AXI_HP1 : integer;
attribute C_USE_S_AXI_HP1 of inst : label is 0;
attribute C_USE_S_AXI_HP2 : integer;
attribute C_USE_S_AXI_HP2 of inst : label is 0;
attribute C_USE_S_AXI_HP3 : integer;
attribute C_USE_S_AXI_HP3 of inst : label is 0;
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of inst : label is "zynq_design_1_processing_system7_0_2.hwdef";
attribute POWER : string;
attribute POWER of inst : label is "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of inst : label is 0;
begin
inst: entity work.zynq_design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7
port map (
CAN0_PHY_RX => '0',
CAN0_PHY_TX => NLW_inst_CAN0_PHY_TX_UNCONNECTED,
CAN1_PHY_RX => '0',
CAN1_PHY_TX => NLW_inst_CAN1_PHY_TX_UNCONNECTED,
Core0_nFIQ => '0',
Core0_nIRQ => '0',
Core1_nFIQ => '0',
Core1_nIRQ => '0',
DDR_ARB(3 downto 0) => B"0000",
DDR_Addr(14 downto 0) => DDR_Addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_BankAddr(2 downto 0),
DDR_CAS_n => DDR_CAS_n,
DDR_CKE => DDR_CKE,
DDR_CS_n => DDR_CS_n,
DDR_Clk => DDR_Clk,
DDR_Clk_n => DDR_Clk_n,
DDR_DM(3 downto 0) => DDR_DM(3 downto 0),
DDR_DQ(31 downto 0) => DDR_DQ(31 downto 0),
DDR_DQS(3 downto 0) => DDR_DQS(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_DQS_n(3 downto 0),
DDR_DRSTB => DDR_DRSTB,
DDR_ODT => DDR_ODT,
DDR_RAS_n => DDR_RAS_n,
DDR_VRN => DDR_VRN,
DDR_VRP => DDR_VRP,
DDR_WEB => DDR_WEB,
DMA0_ACLK => '0',
DMA0_DAREADY => '0',
DMA0_DATYPE(1 downto 0) => NLW_inst_DMA0_DATYPE_UNCONNECTED(1 downto 0),
DMA0_DAVALID => NLW_inst_DMA0_DAVALID_UNCONNECTED,
DMA0_DRLAST => '0',
DMA0_DRREADY => NLW_inst_DMA0_DRREADY_UNCONNECTED,
DMA0_DRTYPE(1 downto 0) => B"00",
DMA0_DRVALID => '0',
DMA0_RSTN => NLW_inst_DMA0_RSTN_UNCONNECTED,
DMA1_ACLK => '0',
DMA1_DAREADY => '0',
DMA1_DATYPE(1 downto 0) => NLW_inst_DMA1_DATYPE_UNCONNECTED(1 downto 0),
DMA1_DAVALID => NLW_inst_DMA1_DAVALID_UNCONNECTED,
DMA1_DRLAST => '0',
DMA1_DRREADY => NLW_inst_DMA1_DRREADY_UNCONNECTED,
DMA1_DRTYPE(1 downto 0) => B"00",
DMA1_DRVALID => '0',
DMA1_RSTN => NLW_inst_DMA1_RSTN_UNCONNECTED,
DMA2_ACLK => '0',
DMA2_DAREADY => '0',
DMA2_DATYPE(1 downto 0) => NLW_inst_DMA2_DATYPE_UNCONNECTED(1 downto 0),
DMA2_DAVALID => NLW_inst_DMA2_DAVALID_UNCONNECTED,
DMA2_DRLAST => '0',
DMA2_DRREADY => NLW_inst_DMA2_DRREADY_UNCONNECTED,
DMA2_DRTYPE(1 downto 0) => B"00",
DMA2_DRVALID => '0',
DMA2_RSTN => NLW_inst_DMA2_RSTN_UNCONNECTED,
DMA3_ACLK => '0',
DMA3_DAREADY => '0',
DMA3_DATYPE(1 downto 0) => NLW_inst_DMA3_DATYPE_UNCONNECTED(1 downto 0),
DMA3_DAVALID => NLW_inst_DMA3_DAVALID_UNCONNECTED,
DMA3_DRLAST => '0',
DMA3_DRREADY => NLW_inst_DMA3_DRREADY_UNCONNECTED,
DMA3_DRTYPE(1 downto 0) => B"00",
DMA3_DRVALID => '0',
DMA3_RSTN => NLW_inst_DMA3_RSTN_UNCONNECTED,
ENET0_EXT_INTIN => '0',
ENET0_GMII_COL => '0',
ENET0_GMII_CRS => '0',
ENET0_GMII_RXD(7 downto 0) => B"00000000",
ENET0_GMII_RX_CLK => '0',
ENET0_GMII_RX_DV => '0',
ENET0_GMII_RX_ER => '0',
ENET0_GMII_TXD(7 downto 0) => NLW_inst_ENET0_GMII_TXD_UNCONNECTED(7 downto 0),
ENET0_GMII_TX_CLK => '0',
ENET0_GMII_TX_EN => NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED,
ENET0_GMII_TX_ER => NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED,
ENET0_MDIO_I => '0',
ENET0_MDIO_MDC => NLW_inst_ENET0_MDIO_MDC_UNCONNECTED,
ENET0_MDIO_O => NLW_inst_ENET0_MDIO_O_UNCONNECTED,
ENET0_MDIO_T => NLW_inst_ENET0_MDIO_T_UNCONNECTED,
ENET0_PTP_DELAY_REQ_RX => NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_DELAY_REQ_TX => NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_RX => NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_TX => NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_RX => NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_TX => NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_RX => NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_TX => NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET0_SOF_RX => NLW_inst_ENET0_SOF_RX_UNCONNECTED,
ENET0_SOF_TX => NLW_inst_ENET0_SOF_TX_UNCONNECTED,
ENET1_EXT_INTIN => '0',
ENET1_GMII_COL => '0',
ENET1_GMII_CRS => '0',
ENET1_GMII_RXD(7 downto 0) => B"00000000",
ENET1_GMII_RX_CLK => '0',
ENET1_GMII_RX_DV => '0',
ENET1_GMII_RX_ER => '0',
ENET1_GMII_TXD(7 downto 0) => NLW_inst_ENET1_GMII_TXD_UNCONNECTED(7 downto 0),
ENET1_GMII_TX_CLK => '0',
ENET1_GMII_TX_EN => NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED,
ENET1_GMII_TX_ER => NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED,
ENET1_MDIO_I => '0',
ENET1_MDIO_MDC => NLW_inst_ENET1_MDIO_MDC_UNCONNECTED,
ENET1_MDIO_O => NLW_inst_ENET1_MDIO_O_UNCONNECTED,
ENET1_MDIO_T => NLW_inst_ENET1_MDIO_T_UNCONNECTED,
ENET1_PTP_DELAY_REQ_RX => NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET1_PTP_DELAY_REQ_TX => NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET1_PTP_PDELAY_REQ_RX => NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET1_PTP_PDELAY_REQ_TX => NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET1_PTP_PDELAY_RESP_RX => NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET1_PTP_PDELAY_RESP_TX => NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET1_PTP_SYNC_FRAME_RX => NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET1_PTP_SYNC_FRAME_TX => NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET1_SOF_RX => NLW_inst_ENET1_SOF_RX_UNCONNECTED,
ENET1_SOF_TX => NLW_inst_ENET1_SOF_TX_UNCONNECTED,
EVENT_EVENTI => '0',
EVENT_EVENTO => NLW_inst_EVENT_EVENTO_UNCONNECTED,
EVENT_STANDBYWFE(1 downto 0) => NLW_inst_EVENT_STANDBYWFE_UNCONNECTED(1 downto 0),
EVENT_STANDBYWFI(1 downto 0) => NLW_inst_EVENT_STANDBYWFI_UNCONNECTED(1 downto 0),
FCLK_CLK0 => FCLK_CLK0,
FCLK_CLK1 => NLW_inst_FCLK_CLK1_UNCONNECTED,
FCLK_CLK2 => NLW_inst_FCLK_CLK2_UNCONNECTED,
FCLK_CLK3 => NLW_inst_FCLK_CLK3_UNCONNECTED,
FCLK_CLKTRIG0_N => '0',
FCLK_CLKTRIG1_N => '0',
FCLK_CLKTRIG2_N => '0',
FCLK_CLKTRIG3_N => '0',
FCLK_RESET0_N => FCLK_RESET0_N,
FCLK_RESET1_N => NLW_inst_FCLK_RESET1_N_UNCONNECTED,
FCLK_RESET2_N => NLW_inst_FCLK_RESET2_N_UNCONNECTED,
FCLK_RESET3_N => NLW_inst_FCLK_RESET3_N_UNCONNECTED,
FPGA_IDLE_N => '0',
FTMD_TRACEIN_ATID(3 downto 0) => B"0000",
FTMD_TRACEIN_CLK => '0',
FTMD_TRACEIN_DATA(31 downto 0) => B"00000000000000000000000000000000",
FTMD_TRACEIN_VALID => '0',
FTMT_F2P_DEBUG(31 downto 0) => B"00000000000000000000000000000000",
FTMT_F2P_TRIGACK_0 => NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED,
FTMT_F2P_TRIGACK_1 => NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED,
FTMT_F2P_TRIGACK_2 => NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED,
FTMT_F2P_TRIGACK_3 => NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED,
FTMT_F2P_TRIG_0 => '0',
FTMT_F2P_TRIG_1 => '0',
FTMT_F2P_TRIG_2 => '0',
FTMT_F2P_TRIG_3 => '0',
FTMT_P2F_DEBUG(31 downto 0) => NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED(31 downto 0),
FTMT_P2F_TRIGACK_0 => '0',
FTMT_P2F_TRIGACK_1 => '0',
FTMT_P2F_TRIGACK_2 => '0',
FTMT_P2F_TRIGACK_3 => '0',
FTMT_P2F_TRIG_0 => NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED,
FTMT_P2F_TRIG_1 => NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED,
FTMT_P2F_TRIG_2 => NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED,
FTMT_P2F_TRIG_3 => NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED,
GPIO_I(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
GPIO_O(63 downto 0) => NLW_inst_GPIO_O_UNCONNECTED(63 downto 0),
GPIO_T(63 downto 0) => NLW_inst_GPIO_T_UNCONNECTED(63 downto 0),
I2C0_SCL_I => '0',
I2C0_SCL_O => NLW_inst_I2C0_SCL_O_UNCONNECTED,
I2C0_SCL_T => NLW_inst_I2C0_SCL_T_UNCONNECTED,
I2C0_SDA_I => '0',
I2C0_SDA_O => NLW_inst_I2C0_SDA_O_UNCONNECTED,
I2C0_SDA_T => NLW_inst_I2C0_SDA_T_UNCONNECTED,
I2C1_SCL_I => '0',
I2C1_SCL_O => NLW_inst_I2C1_SCL_O_UNCONNECTED,
I2C1_SCL_T => NLW_inst_I2C1_SCL_T_UNCONNECTED,
I2C1_SDA_I => '0',
I2C1_SDA_O => NLW_inst_I2C1_SDA_O_UNCONNECTED,
I2C1_SDA_T => NLW_inst_I2C1_SDA_T_UNCONNECTED,
IRQ_F2P(0) => '0',
IRQ_P2F_CAN0 => NLW_inst_IRQ_P2F_CAN0_UNCONNECTED,
IRQ_P2F_CAN1 => NLW_inst_IRQ_P2F_CAN1_UNCONNECTED,
IRQ_P2F_CTI => NLW_inst_IRQ_P2F_CTI_UNCONNECTED,
IRQ_P2F_DMAC0 => NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED,
IRQ_P2F_DMAC1 => NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED,
IRQ_P2F_DMAC2 => NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED,
IRQ_P2F_DMAC3 => NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED,
IRQ_P2F_DMAC4 => NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED,
IRQ_P2F_DMAC5 => NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED,
IRQ_P2F_DMAC6 => NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED,
IRQ_P2F_DMAC7 => NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED,
IRQ_P2F_DMAC_ABORT => NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED,
IRQ_P2F_ENET0 => NLW_inst_IRQ_P2F_ENET0_UNCONNECTED,
IRQ_P2F_ENET1 => NLW_inst_IRQ_P2F_ENET1_UNCONNECTED,
IRQ_P2F_ENET_WAKE0 => NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED,
IRQ_P2F_ENET_WAKE1 => NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED,
IRQ_P2F_GPIO => NLW_inst_IRQ_P2F_GPIO_UNCONNECTED,
IRQ_P2F_I2C0 => NLW_inst_IRQ_P2F_I2C0_UNCONNECTED,
IRQ_P2F_I2C1 => NLW_inst_IRQ_P2F_I2C1_UNCONNECTED,
IRQ_P2F_QSPI => NLW_inst_IRQ_P2F_QSPI_UNCONNECTED,
IRQ_P2F_SDIO0 => NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED,
IRQ_P2F_SDIO1 => NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED,
IRQ_P2F_SMC => NLW_inst_IRQ_P2F_SMC_UNCONNECTED,
IRQ_P2F_SPI0 => NLW_inst_IRQ_P2F_SPI0_UNCONNECTED,
IRQ_P2F_SPI1 => NLW_inst_IRQ_P2F_SPI1_UNCONNECTED,
IRQ_P2F_UART0 => NLW_inst_IRQ_P2F_UART0_UNCONNECTED,
IRQ_P2F_UART1 => NLW_inst_IRQ_P2F_UART1_UNCONNECTED,
IRQ_P2F_USB0 => NLW_inst_IRQ_P2F_USB0_UNCONNECTED,
IRQ_P2F_USB1 => NLW_inst_IRQ_P2F_USB1_UNCONNECTED,
MIO(53 downto 0) => MIO(53 downto 0),
M_AXI_GP0_ACLK => M_AXI_GP0_ACLK,
M_AXI_GP0_ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => M_AXI_GP0_ARCACHE(3 downto 0),
M_AXI_GP0_ARESETN => NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED,
M_AXI_GP0_ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0),
M_AXI_GP0_ARREADY => M_AXI_GP0_ARREADY,
M_AXI_GP0_ARSIZE(2 downto 0) => M_AXI_GP0_ARSIZE(2 downto 0),
M_AXI_GP0_ARVALID => M_AXI_GP0_ARVALID,
M_AXI_GP0_AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => M_AXI_GP0_AWCACHE(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0),
M_AXI_GP0_AWREADY => M_AXI_GP0_AWREADY,
M_AXI_GP0_AWSIZE(2 downto 0) => M_AXI_GP0_AWSIZE(2 downto 0),
M_AXI_GP0_AWVALID => M_AXI_GP0_AWVALID,
M_AXI_GP0_BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0),
M_AXI_GP0_BREADY => M_AXI_GP0_BREADY,
M_AXI_GP0_BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0),
M_AXI_GP0_BVALID => M_AXI_GP0_BVALID,
M_AXI_GP0_RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0),
M_AXI_GP0_RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0),
M_AXI_GP0_RLAST => M_AXI_GP0_RLAST,
M_AXI_GP0_RREADY => M_AXI_GP0_RREADY,
M_AXI_GP0_RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0),
M_AXI_GP0_RVALID => M_AXI_GP0_RVALID,
M_AXI_GP0_WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0),
M_AXI_GP0_WLAST => M_AXI_GP0_WLAST,
M_AXI_GP0_WREADY => M_AXI_GP0_WREADY,
M_AXI_GP0_WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0),
M_AXI_GP0_WVALID => M_AXI_GP0_WVALID,
M_AXI_GP1_ACLK => '0',
M_AXI_GP1_ARADDR(31 downto 0) => NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED(31 downto 0),
M_AXI_GP1_ARBURST(1 downto 0) => NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED(1 downto 0),
M_AXI_GP1_ARCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARESETN => NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED,
M_AXI_GP1_ARID(11 downto 0) => NLW_inst_M_AXI_GP1_ARID_UNCONNECTED(11 downto 0),
M_AXI_GP1_ARLEN(3 downto 0) => NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP1_ARPROT(2 downto 0) => NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED(2 downto 0),
M_AXI_GP1_ARQOS(3 downto 0) => NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARREADY => '0',
M_AXI_GP1_ARSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP1_ARVALID => NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED,
M_AXI_GP1_AWADDR(31 downto 0) => NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED(31 downto 0),
M_AXI_GP1_AWBURST(1 downto 0) => NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED(1 downto 0),
M_AXI_GP1_AWCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWID(11 downto 0) => NLW_inst_M_AXI_GP1_AWID_UNCONNECTED(11 downto 0),
M_AXI_GP1_AWLEN(3 downto 0) => NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP1_AWPROT(2 downto 0) => NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED(2 downto 0),
M_AXI_GP1_AWQOS(3 downto 0) => NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWREADY => '0',
M_AXI_GP1_AWSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP1_AWVALID => NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED,
M_AXI_GP1_BID(11 downto 0) => B"000000000000",
M_AXI_GP1_BREADY => NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED,
M_AXI_GP1_BRESP(1 downto 0) => B"00",
M_AXI_GP1_BVALID => '0',
M_AXI_GP1_RDATA(31 downto 0) => B"00000000000000000000000000000000",
M_AXI_GP1_RID(11 downto 0) => B"000000000000",
M_AXI_GP1_RLAST => '0',
M_AXI_GP1_RREADY => NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED,
M_AXI_GP1_RRESP(1 downto 0) => B"00",
M_AXI_GP1_RVALID => '0',
M_AXI_GP1_WDATA(31 downto 0) => NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED(31 downto 0),
M_AXI_GP1_WID(11 downto 0) => NLW_inst_M_AXI_GP1_WID_UNCONNECTED(11 downto 0),
M_AXI_GP1_WLAST => NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED,
M_AXI_GP1_WREADY => '0',
M_AXI_GP1_WSTRB(3 downto 0) => NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED(3 downto 0),
M_AXI_GP1_WVALID => NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED,
PJTAG_TCK => '0',
PJTAG_TDI => '0',
PJTAG_TDO => NLW_inst_PJTAG_TDO_UNCONNECTED,
PJTAG_TMS => '0',
PS_CLK => PS_CLK,
PS_PORB => PS_PORB,
PS_SRSTB => PS_SRSTB,
SDIO0_BUSPOW => NLW_inst_SDIO0_BUSPOW_UNCONNECTED,
SDIO0_BUSVOLT(2 downto 0) => NLW_inst_SDIO0_BUSVOLT_UNCONNECTED(2 downto 0),
SDIO0_CDN => '0',
SDIO0_CLK => NLW_inst_SDIO0_CLK_UNCONNECTED,
SDIO0_CLK_FB => '0',
SDIO0_CMD_I => '0',
SDIO0_CMD_O => NLW_inst_SDIO0_CMD_O_UNCONNECTED,
SDIO0_CMD_T => NLW_inst_SDIO0_CMD_T_UNCONNECTED,
SDIO0_DATA_I(3 downto 0) => B"0000",
SDIO0_DATA_O(3 downto 0) => NLW_inst_SDIO0_DATA_O_UNCONNECTED(3 downto 0),
SDIO0_DATA_T(3 downto 0) => NLW_inst_SDIO0_DATA_T_UNCONNECTED(3 downto 0),
SDIO0_LED => NLW_inst_SDIO0_LED_UNCONNECTED,
SDIO0_WP => '0',
SDIO1_BUSPOW => NLW_inst_SDIO1_BUSPOW_UNCONNECTED,
SDIO1_BUSVOLT(2 downto 0) => NLW_inst_SDIO1_BUSVOLT_UNCONNECTED(2 downto 0),
SDIO1_CDN => '0',
SDIO1_CLK => NLW_inst_SDIO1_CLK_UNCONNECTED,
SDIO1_CLK_FB => '0',
SDIO1_CMD_I => '0',
SDIO1_CMD_O => NLW_inst_SDIO1_CMD_O_UNCONNECTED,
SDIO1_CMD_T => NLW_inst_SDIO1_CMD_T_UNCONNECTED,
SDIO1_DATA_I(3 downto 0) => B"0000",
SDIO1_DATA_O(3 downto 0) => NLW_inst_SDIO1_DATA_O_UNCONNECTED(3 downto 0),
SDIO1_DATA_T(3 downto 0) => NLW_inst_SDIO1_DATA_T_UNCONNECTED(3 downto 0),
SDIO1_LED => NLW_inst_SDIO1_LED_UNCONNECTED,
SDIO1_WP => '0',
SPI0_MISO_I => '0',
SPI0_MISO_O => NLW_inst_SPI0_MISO_O_UNCONNECTED,
SPI0_MISO_T => NLW_inst_SPI0_MISO_T_UNCONNECTED,
SPI0_MOSI_I => '0',
SPI0_MOSI_O => NLW_inst_SPI0_MOSI_O_UNCONNECTED,
SPI0_MOSI_T => NLW_inst_SPI0_MOSI_T_UNCONNECTED,
SPI0_SCLK_I => '0',
SPI0_SCLK_O => NLW_inst_SPI0_SCLK_O_UNCONNECTED,
SPI0_SCLK_T => NLW_inst_SPI0_SCLK_T_UNCONNECTED,
SPI0_SS1_O => NLW_inst_SPI0_SS1_O_UNCONNECTED,
SPI0_SS2_O => NLW_inst_SPI0_SS2_O_UNCONNECTED,
SPI0_SS_I => '0',
SPI0_SS_O => NLW_inst_SPI0_SS_O_UNCONNECTED,
SPI0_SS_T => NLW_inst_SPI0_SS_T_UNCONNECTED,
SPI1_MISO_I => '0',
SPI1_MISO_O => NLW_inst_SPI1_MISO_O_UNCONNECTED,
SPI1_MISO_T => NLW_inst_SPI1_MISO_T_UNCONNECTED,
SPI1_MOSI_I => '0',
SPI1_MOSI_O => NLW_inst_SPI1_MOSI_O_UNCONNECTED,
SPI1_MOSI_T => NLW_inst_SPI1_MOSI_T_UNCONNECTED,
SPI1_SCLK_I => '0',
SPI1_SCLK_O => NLW_inst_SPI1_SCLK_O_UNCONNECTED,
SPI1_SCLK_T => NLW_inst_SPI1_SCLK_T_UNCONNECTED,
SPI1_SS1_O => NLW_inst_SPI1_SS1_O_UNCONNECTED,
SPI1_SS2_O => NLW_inst_SPI1_SS2_O_UNCONNECTED,
SPI1_SS_I => '0',
SPI1_SS_O => NLW_inst_SPI1_SS_O_UNCONNECTED,
SPI1_SS_T => NLW_inst_SPI1_SS_T_UNCONNECTED,
SRAM_INTIN => '0',
S_AXI_ACP_ACLK => '0',
S_AXI_ACP_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_ACP_ARBURST(1 downto 0) => B"00",
S_AXI_ACP_ARCACHE(3 downto 0) => B"0000",
S_AXI_ACP_ARESETN => NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED,
S_AXI_ACP_ARID(2 downto 0) => B"000",
S_AXI_ACP_ARLEN(3 downto 0) => B"0000",
S_AXI_ACP_ARLOCK(1 downto 0) => B"00",
S_AXI_ACP_ARPROT(2 downto 0) => B"000",
S_AXI_ACP_ARQOS(3 downto 0) => B"0000",
S_AXI_ACP_ARREADY => NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED,
S_AXI_ACP_ARSIZE(2 downto 0) => B"000",
S_AXI_ACP_ARUSER(4 downto 0) => B"00000",
S_AXI_ACP_ARVALID => '0',
S_AXI_ACP_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_ACP_AWBURST(1 downto 0) => B"00",
S_AXI_ACP_AWCACHE(3 downto 0) => B"0000",
S_AXI_ACP_AWID(2 downto 0) => B"000",
S_AXI_ACP_AWLEN(3 downto 0) => B"0000",
S_AXI_ACP_AWLOCK(1 downto 0) => B"00",
S_AXI_ACP_AWPROT(2 downto 0) => B"000",
S_AXI_ACP_AWQOS(3 downto 0) => B"0000",
S_AXI_ACP_AWREADY => NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED,
S_AXI_ACP_AWSIZE(2 downto 0) => B"000",
S_AXI_ACP_AWUSER(4 downto 0) => B"00000",
S_AXI_ACP_AWVALID => '0',
S_AXI_ACP_BID(2 downto 0) => NLW_inst_S_AXI_ACP_BID_UNCONNECTED(2 downto 0),
S_AXI_ACP_BREADY => '0',
S_AXI_ACP_BRESP(1 downto 0) => NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED(1 downto 0),
S_AXI_ACP_BVALID => NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED,
S_AXI_ACP_RDATA(63 downto 0) => NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED(63 downto 0),
S_AXI_ACP_RID(2 downto 0) => NLW_inst_S_AXI_ACP_RID_UNCONNECTED(2 downto 0),
S_AXI_ACP_RLAST => NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED,
S_AXI_ACP_RREADY => '0',
S_AXI_ACP_RRESP(1 downto 0) => NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED(1 downto 0),
S_AXI_ACP_RVALID => NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED,
S_AXI_ACP_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_ACP_WID(2 downto 0) => B"000",
S_AXI_ACP_WLAST => '0',
S_AXI_ACP_WREADY => NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED,
S_AXI_ACP_WSTRB(7 downto 0) => B"00000000",
S_AXI_ACP_WVALID => '0',
S_AXI_GP0_ACLK => '0',
S_AXI_GP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_ARBURST(1 downto 0) => B"00",
S_AXI_GP0_ARCACHE(3 downto 0) => B"0000",
S_AXI_GP0_ARESETN => NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED,
S_AXI_GP0_ARID(5 downto 0) => B"000000",
S_AXI_GP0_ARLEN(3 downto 0) => B"0000",
S_AXI_GP0_ARLOCK(1 downto 0) => B"00",
S_AXI_GP0_ARPROT(2 downto 0) => B"000",
S_AXI_GP0_ARQOS(3 downto 0) => B"0000",
S_AXI_GP0_ARREADY => NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED,
S_AXI_GP0_ARSIZE(2 downto 0) => B"000",
S_AXI_GP0_ARVALID => '0',
S_AXI_GP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_AWBURST(1 downto 0) => B"00",
S_AXI_GP0_AWCACHE(3 downto 0) => B"0000",
S_AXI_GP0_AWID(5 downto 0) => B"000000",
S_AXI_GP0_AWLEN(3 downto 0) => B"0000",
S_AXI_GP0_AWLOCK(1 downto 0) => B"00",
S_AXI_GP0_AWPROT(2 downto 0) => B"000",
S_AXI_GP0_AWQOS(3 downto 0) => B"0000",
S_AXI_GP0_AWREADY => NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED,
S_AXI_GP0_AWSIZE(2 downto 0) => B"000",
S_AXI_GP0_AWVALID => '0',
S_AXI_GP0_BID(5 downto 0) => NLW_inst_S_AXI_GP0_BID_UNCONNECTED(5 downto 0),
S_AXI_GP0_BREADY => '0',
S_AXI_GP0_BRESP(1 downto 0) => NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED(1 downto 0),
S_AXI_GP0_BVALID => NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED,
S_AXI_GP0_RDATA(31 downto 0) => NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED(31 downto 0),
S_AXI_GP0_RID(5 downto 0) => NLW_inst_S_AXI_GP0_RID_UNCONNECTED(5 downto 0),
S_AXI_GP0_RLAST => NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED,
S_AXI_GP0_RREADY => '0',
S_AXI_GP0_RRESP(1 downto 0) => NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED(1 downto 0),
S_AXI_GP0_RVALID => NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED,
S_AXI_GP0_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_WID(5 downto 0) => B"000000",
S_AXI_GP0_WLAST => '0',
S_AXI_GP0_WREADY => NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED,
S_AXI_GP0_WSTRB(3 downto 0) => B"0000",
S_AXI_GP0_WVALID => '0',
S_AXI_GP1_ACLK => '0',
S_AXI_GP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_ARBURST(1 downto 0) => B"00",
S_AXI_GP1_ARCACHE(3 downto 0) => B"0000",
S_AXI_GP1_ARESETN => NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED,
S_AXI_GP1_ARID(5 downto 0) => B"000000",
S_AXI_GP1_ARLEN(3 downto 0) => B"0000",
S_AXI_GP1_ARLOCK(1 downto 0) => B"00",
S_AXI_GP1_ARPROT(2 downto 0) => B"000",
S_AXI_GP1_ARQOS(3 downto 0) => B"0000",
S_AXI_GP1_ARREADY => NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED,
S_AXI_GP1_ARSIZE(2 downto 0) => B"000",
S_AXI_GP1_ARVALID => '0',
S_AXI_GP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_AWBURST(1 downto 0) => B"00",
S_AXI_GP1_AWCACHE(3 downto 0) => B"0000",
S_AXI_GP1_AWID(5 downto 0) => B"000000",
S_AXI_GP1_AWLEN(3 downto 0) => B"0000",
S_AXI_GP1_AWLOCK(1 downto 0) => B"00",
S_AXI_GP1_AWPROT(2 downto 0) => B"000",
S_AXI_GP1_AWQOS(3 downto 0) => B"0000",
S_AXI_GP1_AWREADY => NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED,
S_AXI_GP1_AWSIZE(2 downto 0) => B"000",
S_AXI_GP1_AWVALID => '0',
S_AXI_GP1_BID(5 downto 0) => NLW_inst_S_AXI_GP1_BID_UNCONNECTED(5 downto 0),
S_AXI_GP1_BREADY => '0',
S_AXI_GP1_BRESP(1 downto 0) => NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED(1 downto 0),
S_AXI_GP1_BVALID => NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED,
S_AXI_GP1_RDATA(31 downto 0) => NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED(31 downto 0),
S_AXI_GP1_RID(5 downto 0) => NLW_inst_S_AXI_GP1_RID_UNCONNECTED(5 downto 0),
S_AXI_GP1_RLAST => NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED,
S_AXI_GP1_RREADY => '0',
S_AXI_GP1_RRESP(1 downto 0) => NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED(1 downto 0),
S_AXI_GP1_RVALID => NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED,
S_AXI_GP1_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_WID(5 downto 0) => B"000000",
S_AXI_GP1_WLAST => '0',
S_AXI_GP1_WREADY => NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED,
S_AXI_GP1_WSTRB(3 downto 0) => B"0000",
S_AXI_GP1_WVALID => '0',
S_AXI_HP0_ACLK => '0',
S_AXI_HP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP0_ARBURST(1 downto 0) => B"00",
S_AXI_HP0_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP0_ARESETN => NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED,
S_AXI_HP0_ARID(5 downto 0) => B"000000",
S_AXI_HP0_ARLEN(3 downto 0) => B"0000",
S_AXI_HP0_ARLOCK(1 downto 0) => B"00",
S_AXI_HP0_ARPROT(2 downto 0) => B"000",
S_AXI_HP0_ARQOS(3 downto 0) => B"0000",
S_AXI_HP0_ARREADY => NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED,
S_AXI_HP0_ARSIZE(2 downto 0) => B"000",
S_AXI_HP0_ARVALID => '0',
S_AXI_HP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP0_AWBURST(1 downto 0) => B"00",
S_AXI_HP0_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP0_AWID(5 downto 0) => B"000000",
S_AXI_HP0_AWLEN(3 downto 0) => B"0000",
S_AXI_HP0_AWLOCK(1 downto 0) => B"00",
S_AXI_HP0_AWPROT(2 downto 0) => B"000",
S_AXI_HP0_AWQOS(3 downto 0) => B"0000",
S_AXI_HP0_AWREADY => NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED,
S_AXI_HP0_AWSIZE(2 downto 0) => B"000",
S_AXI_HP0_AWVALID => '0',
S_AXI_HP0_BID(5 downto 0) => NLW_inst_S_AXI_HP0_BID_UNCONNECTED(5 downto 0),
S_AXI_HP0_BREADY => '0',
S_AXI_HP0_BRESP(1 downto 0) => NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP0_BVALID => NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED,
S_AXI_HP0_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP0_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_RDATA(63 downto 0) => NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP0_RDISSUECAP1_EN => '0',
S_AXI_HP0_RID(5 downto 0) => NLW_inst_S_AXI_HP0_RID_UNCONNECTED(5 downto 0),
S_AXI_HP0_RLAST => NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED,
S_AXI_HP0_RREADY => '0',
S_AXI_HP0_RRESP(1 downto 0) => NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP0_RVALID => NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED,
S_AXI_HP0_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP0_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP0_WID(5 downto 0) => B"000000",
S_AXI_HP0_WLAST => '0',
S_AXI_HP0_WREADY => NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED,
S_AXI_HP0_WRISSUECAP1_EN => '0',
S_AXI_HP0_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP0_WVALID => '0',
S_AXI_HP1_ACLK => '0',
S_AXI_HP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP1_ARBURST(1 downto 0) => B"00",
S_AXI_HP1_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP1_ARESETN => NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED,
S_AXI_HP1_ARID(5 downto 0) => B"000000",
S_AXI_HP1_ARLEN(3 downto 0) => B"0000",
S_AXI_HP1_ARLOCK(1 downto 0) => B"00",
S_AXI_HP1_ARPROT(2 downto 0) => B"000",
S_AXI_HP1_ARQOS(3 downto 0) => B"0000",
S_AXI_HP1_ARREADY => NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED,
S_AXI_HP1_ARSIZE(2 downto 0) => B"000",
S_AXI_HP1_ARVALID => '0',
S_AXI_HP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP1_AWBURST(1 downto 0) => B"00",
S_AXI_HP1_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP1_AWID(5 downto 0) => B"000000",
S_AXI_HP1_AWLEN(3 downto 0) => B"0000",
S_AXI_HP1_AWLOCK(1 downto 0) => B"00",
S_AXI_HP1_AWPROT(2 downto 0) => B"000",
S_AXI_HP1_AWQOS(3 downto 0) => B"0000",
S_AXI_HP1_AWREADY => NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED,
S_AXI_HP1_AWSIZE(2 downto 0) => B"000",
S_AXI_HP1_AWVALID => '0',
S_AXI_HP1_BID(5 downto 0) => NLW_inst_S_AXI_HP1_BID_UNCONNECTED(5 downto 0),
S_AXI_HP1_BREADY => '0',
S_AXI_HP1_BRESP(1 downto 0) => NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP1_BVALID => NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED,
S_AXI_HP1_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP1_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP1_RDATA(63 downto 0) => NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP1_RDISSUECAP1_EN => '0',
S_AXI_HP1_RID(5 downto 0) => NLW_inst_S_AXI_HP1_RID_UNCONNECTED(5 downto 0),
S_AXI_HP1_RLAST => NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED,
S_AXI_HP1_RREADY => '0',
S_AXI_HP1_RRESP(1 downto 0) => NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP1_RVALID => NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED,
S_AXI_HP1_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP1_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP1_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP1_WID(5 downto 0) => B"000000",
S_AXI_HP1_WLAST => '0',
S_AXI_HP1_WREADY => NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED,
S_AXI_HP1_WRISSUECAP1_EN => '0',
S_AXI_HP1_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP1_WVALID => '0',
S_AXI_HP2_ACLK => '0',
S_AXI_HP2_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP2_ARBURST(1 downto 0) => B"00",
S_AXI_HP2_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP2_ARESETN => NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED,
S_AXI_HP2_ARID(5 downto 0) => B"000000",
S_AXI_HP2_ARLEN(3 downto 0) => B"0000",
S_AXI_HP2_ARLOCK(1 downto 0) => B"00",
S_AXI_HP2_ARPROT(2 downto 0) => B"000",
S_AXI_HP2_ARQOS(3 downto 0) => B"0000",
S_AXI_HP2_ARREADY => NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED,
S_AXI_HP2_ARSIZE(2 downto 0) => B"000",
S_AXI_HP2_ARVALID => '0',
S_AXI_HP2_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP2_AWBURST(1 downto 0) => B"00",
S_AXI_HP2_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP2_AWID(5 downto 0) => B"000000",
S_AXI_HP2_AWLEN(3 downto 0) => B"0000",
S_AXI_HP2_AWLOCK(1 downto 0) => B"00",
S_AXI_HP2_AWPROT(2 downto 0) => B"000",
S_AXI_HP2_AWQOS(3 downto 0) => B"0000",
S_AXI_HP2_AWREADY => NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED,
S_AXI_HP2_AWSIZE(2 downto 0) => B"000",
S_AXI_HP2_AWVALID => '0',
S_AXI_HP2_BID(5 downto 0) => NLW_inst_S_AXI_HP2_BID_UNCONNECTED(5 downto 0),
S_AXI_HP2_BREADY => '0',
S_AXI_HP2_BRESP(1 downto 0) => NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP2_BVALID => NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED,
S_AXI_HP2_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP2_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP2_RDATA(63 downto 0) => NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP2_RDISSUECAP1_EN => '0',
S_AXI_HP2_RID(5 downto 0) => NLW_inst_S_AXI_HP2_RID_UNCONNECTED(5 downto 0),
S_AXI_HP2_RLAST => NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED,
S_AXI_HP2_RREADY => '0',
S_AXI_HP2_RRESP(1 downto 0) => NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP2_RVALID => NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED,
S_AXI_HP2_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP2_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP2_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP2_WID(5 downto 0) => B"000000",
S_AXI_HP2_WLAST => '0',
S_AXI_HP2_WREADY => NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED,
S_AXI_HP2_WRISSUECAP1_EN => '0',
S_AXI_HP2_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP2_WVALID => '0',
S_AXI_HP3_ACLK => '0',
S_AXI_HP3_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP3_ARBURST(1 downto 0) => B"00",
S_AXI_HP3_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP3_ARESETN => NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED,
S_AXI_HP3_ARID(5 downto 0) => B"000000",
S_AXI_HP3_ARLEN(3 downto 0) => B"0000",
S_AXI_HP3_ARLOCK(1 downto 0) => B"00",
S_AXI_HP3_ARPROT(2 downto 0) => B"000",
S_AXI_HP3_ARQOS(3 downto 0) => B"0000",
S_AXI_HP3_ARREADY => NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED,
S_AXI_HP3_ARSIZE(2 downto 0) => B"000",
S_AXI_HP3_ARVALID => '0',
S_AXI_HP3_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP3_AWBURST(1 downto 0) => B"00",
S_AXI_HP3_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP3_AWID(5 downto 0) => B"000000",
S_AXI_HP3_AWLEN(3 downto 0) => B"0000",
S_AXI_HP3_AWLOCK(1 downto 0) => B"00",
S_AXI_HP3_AWPROT(2 downto 0) => B"000",
S_AXI_HP3_AWQOS(3 downto 0) => B"0000",
S_AXI_HP3_AWREADY => NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED,
S_AXI_HP3_AWSIZE(2 downto 0) => B"000",
S_AXI_HP3_AWVALID => '0',
S_AXI_HP3_BID(5 downto 0) => NLW_inst_S_AXI_HP3_BID_UNCONNECTED(5 downto 0),
S_AXI_HP3_BREADY => '0',
S_AXI_HP3_BRESP(1 downto 0) => NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP3_BVALID => NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED,
S_AXI_HP3_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP3_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP3_RDATA(63 downto 0) => NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP3_RDISSUECAP1_EN => '0',
S_AXI_HP3_RID(5 downto 0) => NLW_inst_S_AXI_HP3_RID_UNCONNECTED(5 downto 0),
S_AXI_HP3_RLAST => NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED,
S_AXI_HP3_RREADY => '0',
S_AXI_HP3_RRESP(1 downto 0) => NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP3_RVALID => NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED,
S_AXI_HP3_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP3_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP3_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP3_WID(5 downto 0) => B"000000",
S_AXI_HP3_WLAST => '0',
S_AXI_HP3_WREADY => NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED,
S_AXI_HP3_WRISSUECAP1_EN => '0',
S_AXI_HP3_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP3_WVALID => '0',
TRACE_CLK => '0',
TRACE_CLK_OUT => NLW_inst_TRACE_CLK_OUT_UNCONNECTED,
TRACE_CTL => NLW_inst_TRACE_CTL_UNCONNECTED,
TRACE_DATA(1 downto 0) => NLW_inst_TRACE_DATA_UNCONNECTED(1 downto 0),
TTC0_CLK0_IN => '0',
TTC0_CLK1_IN => '0',
TTC0_CLK2_IN => '0',
TTC0_WAVE0_OUT => TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT => TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT => TTC0_WAVE2_OUT,
TTC1_CLK0_IN => '0',
TTC1_CLK1_IN => '0',
TTC1_CLK2_IN => '0',
TTC1_WAVE0_OUT => NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED,
TTC1_WAVE1_OUT => NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED,
TTC1_WAVE2_OUT => NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED,
UART0_CTSN => '0',
UART0_DCDN => '0',
UART0_DSRN => '0',
UART0_DTRN => NLW_inst_UART0_DTRN_UNCONNECTED,
UART0_RIN => '0',
UART0_RTSN => NLW_inst_UART0_RTSN_UNCONNECTED,
UART0_RX => '1',
UART0_TX => NLW_inst_UART0_TX_UNCONNECTED,
UART1_CTSN => '0',
UART1_DCDN => '0',
UART1_DSRN => '0',
UART1_DTRN => NLW_inst_UART1_DTRN_UNCONNECTED,
UART1_RIN => '0',
UART1_RTSN => NLW_inst_UART1_RTSN_UNCONNECTED,
UART1_RX => '1',
UART1_TX => NLW_inst_UART1_TX_UNCONNECTED,
USB0_PORT_INDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0),
USB0_VBUS_PWRFAULT => USB0_VBUS_PWRFAULT,
USB0_VBUS_PWRSELECT => USB0_VBUS_PWRSELECT,
USB1_PORT_INDCTL(1 downto 0) => NLW_inst_USB1_PORT_INDCTL_UNCONNECTED(1 downto 0),
USB1_VBUS_PWRFAULT => '0',
USB1_VBUS_PWRSELECT => NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED,
WDT_CLK_IN => '0',
WDT_RST_OUT => NLW_inst_WDT_RST_OUT_UNCONNECTED
);
end STRUCTURE;
| mit | 681b776fba0f197f5eb2c654eff5c078 | 0.634355 | 2.754217 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/tech/atc18/components/atmel_simprims.vhd | 1 | 7,875 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: Various
-- File: atmel_simprims.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: ATMEL ATC18 behavioural models
-- Modelled after IO33/PCILIB data sheets
------------------------------------------------------------------------------
-- pragma translate_off
-- input pad
library ieee;
use ieee.std_logic_1164.all;
entity pc33d00z is port (pad : in std_logic; cin : out std_logic); end;
architecture rtl of pc33d00z is begin cin <= to_x01(pad) after 1 ns; end;
-- input pad with pull-up
library ieee;
use ieee.std_logic_1164.all;
entity pc33d00uz is port (pad : inout std_logic; cin : out std_logic); end;
architecture rtl of pc33d00uz is
begin cin <= to_x01(pad) after 1 ns; pad <= 'H'; end;
-- input schmitt pad
library ieee;
use ieee.std_logic_1164.all;
entity pc33d20z is port (pad : in std_logic; cin : out std_logic); end;
architecture rtl of pc33d20z is begin cin <= to_x01(pad) after 1 ns; end;
-- input schmitt pad with pull-up
library ieee;
use ieee.std_logic_1164.all;
entity pc33d20uz is port (pad : inout std_logic; cin : out std_logic); end;
architecture rtl of pc33d20uz is
begin cin <= to_x01(pad) after 1 ns; pad <= 'H'; end;
-- output pads
library ieee; use ieee.std_logic_1164.all;
entity pt33o01z is port (i : in std_logic; pad : out std_logic); end;
architecture rtl of pt33o01z is begin pad <= to_x01(i) after 2 ns; end;
library ieee; use ieee.std_logic_1164.all;
entity pt33o02z is port (i : in std_logic; pad : out std_logic); end;
architecture rtl of pt33o02z is begin pad <= to_x01(i) after 2 ns; end;
library ieee; use ieee.std_logic_1164.all;
entity pt33o04z is port (i : in std_logic; pad : out std_logic); end;
architecture rtl of pt33o04z is begin pad <= to_x01(i) after 2 ns; end;
library ieee; use ieee.std_logic_1164.all;
entity pt33o08z is port (i : in std_logic; pad : out std_logic); end;
architecture rtl of pt33o08z is begin pad <= to_x01(i) after 2 ns; end;
-- output tri-state pads
library ieee; use ieee.std_logic_1164.all;
entity pt33t01z is port (i, oen : in std_logic; pad : out std_logic); end;
architecture rtl of pt33t01z is
begin pad <= to_x01(i) after 2 ns when oen = '0' else 'H' after 2 ns; end;
library ieee; use ieee.std_logic_1164.all;
entity pt33t02z is port (i, oen : in std_logic; pad : out std_logic); end;
architecture rtl of pt33t02z is
begin pad <= to_x01(i) after 2 ns when oen = '0' else 'H' after 2 ns; end;
library ieee; use ieee.std_logic_1164.all;
entity pt33t04z is port (i, oen : in std_logic; pad : out std_logic); end;
architecture rtl of pt33t04z is
begin pad <= to_x01(i) after 2 ns when oen = '0' else 'H' after 2 ns; end;
library ieee; use ieee.std_logic_1164.all;
entity pt33t08z is port (i, oen : in std_logic; pad : out std_logic); end;
architecture rtl of pt33t08z is
begin pad <= to_x01(i) after 2 ns when oen = '0' else 'H' after 2 ns; end;
-- output tri-state pads with pull-up
library ieee; use ieee.std_logic_1164.all;
entity pt33t01uz is port (i, oen : in std_logic; pad : out std_logic); end;
architecture rtl of pt33t01uz is
begin pad <= to_x01(i) after 2 ns when oen = '0' else 'H' after 2 ns; end;
library ieee; use ieee.std_logic_1164.all;
entity pt33t02uz is port (i, oen : in std_logic; pad : out std_logic); end;
architecture rtl of pt33t02uz is
begin pad <= to_x01(i) after 2 ns when oen = '0' else 'H' after 2 ns; end;
library ieee; use ieee.std_logic_1164.all;
entity pt33t04uz is port (i, oen : in std_logic; pad : out std_logic); end;
architecture rtl of pt33t04uz is
begin pad <= to_x01(i) after 2 ns when oen = '0' else 'H' after 2 ns; end;
-- bidirectional pad
library ieee; use ieee.std_logic_1164.all;
entity pt33b01z is
port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end;
architecture rtl of pt33b01z is
begin
pad <= to_x01(i) after 2 ns when oen = '0' else 'Z' after 2 ns;
cin <= to_x01(pad) after 1 ns;
end;
library ieee; use ieee.std_logic_1164.all;
entity pt33b02z is
port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end;
architecture rtl of pt33b02z is
begin
pad <= to_x01(i) after 2 ns when oen = '0' else 'Z' after 2 ns;
cin <= to_x01(pad) after 1 ns;
end;
library ieee; use ieee.std_logic_1164.all;
entity pt33b08z is
port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end;
architecture rtl of pt33b08z is
begin
pad <= to_x01(i) after 2 ns when oen = '0' else 'Z' after 2 ns;
cin <= to_x01(pad) after 1 ns;
end;
library ieee; use ieee.std_logic_1164.all;
entity pt33b04z is
port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end;
architecture rtl of pt33b04z is
begin
pad <= to_x01(i) after 2 ns when oen = '0' else 'Z' after 2 ns;
cin <= to_x01(pad) after 1 ns;
end;
-- bidirectional pads with pull-up
library ieee;
use ieee.std_logic_1164.all;
entity pt33b01uz is
port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end;
architecture rtl of pt33b01uz is
begin
pad <= to_x01(i) after 2 ns when oen = '0' else 'H' after 2 ns;
cin <= to_x01(pad) after 1 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity pt33b02uz is
port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end;
architecture rtl of pt33b02uz is
begin
pad <= to_x01(i) after 2 ns when oen = '0' else 'H' after 2 ns;
cin <= to_x01(pad) after 1 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity pt33b08uz is
port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end;
architecture rtl of pt33b08uz is
begin
pad <= to_x01(i) after 2 ns when oen = '0' else 'H' after 2 ns;
cin <= to_x01(pad) after 1 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity pt33b04uz is
port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end;
architecture rtl of pt33b04uz is
begin
pad <= to_x01(i) after 2 ns when oen = '0' else 'H' after 2 ns;
cin <= to_x01(pad) after 1 ns;
end;
-- PCI output pad
library ieee; use ieee.std_logic_1164.all;
entity pp33o01z is port (i : in std_logic; pad : out std_logic); end;
architecture rtl of pp33o01z is begin pad <= to_x01(i) after 2 ns; end;
-- PCI bidirectional pad
library ieee; use ieee.std_logic_1164.all;
entity pp33b01z is
port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end;
architecture rtl of pp33b01z is
begin
pad <= to_x01(i) after 2 ns when oen = '0' else 'Z' after 2 ns;
cin <= to_x01(pad) after 1 ns;
end;
-- PCI output tri-state pad
library ieee; use ieee.std_logic_1164.all;
entity pp33t01z is port (i, oen : in std_logic; pad : out std_logic); end;
architecture rtl of pp33t01z is
begin pad <= to_x01(i) after 2 ns when oen = '0' else 'Z' after 2 ns; end;
-- pragma translate_on
| gpl-2.0 | 657226ffe010378a99808357624929bf | 0.667683 | 2.871991 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/techmap/saed32/pads_saed32.vhd | 1 | 12,034 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: saed32pads
-- File: pads_saed32.vhd
-- Author: Fredrik Ringhage - Aeroflex Gaisler AB
-- Description: SAED32 pad wrappers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package saed32pads is
-- input pad
component I1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; VDDIO : inout std_logic; VDD : inout std_logic; R_EN : in std_logic; VSSIO : inout std_logic;DOUT : out std_logic); end component;
-- input pad with pull-up and pull-down
component B4I1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; PULL_UP : in std_logic; VDDIO : inout std_logic; EN : in std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DOUT: out std_logic; DIN : in std_logic; PULL_DOWN : in std_logic; R_EN : in std_logic); end component;
-- schmitt input pad
component ISH1025_EW port(PADIO : inout std_logic; VSS : inout std_logic; VDDIO : inout std_logic; VDD : inout std_logic; R_EN : in std_logic; VSSIO : inout std_logic; DOUT : out std_logic); end component;
-- output pads
component D4I1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; EN : in std_logic; VDDIO : inout std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DIN : in std_logic); end component;
component D12I1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; EN : in std_logic; VDDIO : inout std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DIN : in std_logic); end component;
component D16I1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; EN : in std_logic; VDDIO : inout std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DIN : in std_logic); end component;
-- bidirectional pads (and tri-state output pads)
component B4ISH1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; PULL_UP : in std_logic; VDDIO : inout std_logic; EN : in std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DOUT : out std_logic; DIN : in std_logic; PULL_DOWN : in std_logic; R_EN : in std_logic); end component;
component B12ISH1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; PULL_UP : in std_logic; VDDIO : inout std_logic; EN : in std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DOUT : out std_logic; DIN : in std_logic; PULL_DOWN : in std_logic; R_EN : in std_logic); end component;
component B16ISH1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; PULL_UP : in std_logic; VDDIO : inout std_logic; EN : in std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DOUT : out std_logic; DIN : in std_logic; PULL_DOWN : in std_logic; R_EN : in std_logic); end component;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library work;
use work.all;
-- pragma translate_off
library saed32;
use saed32.I1025_NS;
use saed32.B4I1025_NS;
use saed32.ISH1025_EW;
-- pragma translate_on
entity saed32_inpad is
generic (level : integer := 0; voltage : integer := 0; filter : integer := 0);
port (pad : in std_logic; o : out std_logic);
end;
architecture rtl of saed32_inpad is
component I1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; VDDIO : inout std_logic; VDD : inout std_logic; R_EN : in std_logic; VSSIO : inout std_logic; DOUT : out std_logic); end component;
component B4I1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; PULL_UP : in std_logic; VDDIO : inout std_logic; EN : in std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DOUT: out std_logic; DIN : in std_logic; PULL_DOWN : in std_logic; R_EN : in std_logic); end component;
component ISH1025_EW port(PADIO : inout std_logic; VSS : inout std_logic; VDDIO : inout std_logic; VDD : inout std_logic; R_EN : in std_logic; VSSIO : inout std_logic; DOUT : out std_logic); end component;
signal localout,localpad : std_logic;
begin
norm : if filter = 0 generate
ip : I1025_NS port map (PADIO => localpad, DOUT => localout, VSS => OPEN, R_EN => '1', VDDIO => OPEN, VDD => OPEN, VSSIO => OPEN);
end generate;
pu : if filter = pullup generate
ip : B4I1025_NS port map (PADIO => localpad, PULL_UP => '1', PULL_DOWN => '0', DOUT => localout, DIN => '0', VSS => OPEN, R_EN => '1', EN => '0', VDDIO => OPEN, VDD => OPEN, VSSIO => OPEN);
end generate;
pd : if filter = pulldown generate
ip : B4I1025_NS port map (PADIO => localpad, PULL_UP => '0', PULL_DOWN => '1', DOUT => localout, DIN => '0', VSS => OPEN, R_EN => '1', EN => '0', VDDIO => OPEN, VDD => OPEN, VSSIO => OPEN);
end generate;
sch : if filter = schmitt generate
ip : ISH1025_EW port map (PADIO => localpad, DOUT => localout, VSS => OPEN, R_EN => '1', VDDIO => OPEN, VDD => OPEN, VSSIO => OPEN);
end generate;
o <= localout;
localpad <= pad;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library work;
use work.all;
-- pragma translate_off
library saed32;
use saed32.B4ISH1025_NS;
use saed32.B12ISH1025_NS;
use saed32.B16ISH1025_NS;
-- pragma translate_on
entity saed32_iopad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);
end ;
architecture rtl of saed32_iopad is
component B4ISH1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; PULL_UP : in std_logic; VDDIO : inout std_logic; EN : in std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DOUT : out std_logic; DIN : in std_logic; PULL_DOWN : in std_logic; R_EN : in std_logic); end component;
component B12ISH1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; PULL_UP : in std_logic; VDDIO : inout std_logic; EN : in std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DOUT : out std_logic; DIN : in std_logic; PULL_DOWN : in std_logic; R_EN : in std_logic); end component;
component B16ISH1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; PULL_UP : in std_logic; VDDIO : inout std_logic; EN : in std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DOUT : out std_logic; DIN : in std_logic; PULL_DOWN : in std_logic; R_EN : in std_logic); end component;
signal localen : std_logic;
signal localout,localpad : std_logic;
begin
localen <= not en;
f4 : if (strength <= 4) generate
op : B4ISH1025_NS port map (DIN => i,PADIO => pad, DOUT => o, VSS => OPEN, R_EN => localen, EN => en, VDDIO => OPEN, VDD => OPEN, VSSIO => OPEN, PULL_UP => '0', PULL_DOWN => '0');
end generate;
f12 : if (strength > 4) and (strength <= 12) generate
op : B12ISH1025_NS port map (DIN => i, PADIO => pad, DOUT => o, VSS => OPEN, R_EN => localen, EN => en, VDDIO => OPEN, VDD => OPEN, VSSIO => OPEN, PULL_UP => '0', PULL_DOWN => '0');
end generate;
f16 : if (strength > 12) generate
op : B16ISH1025_NS port map (DIN => i, PADIO => pad, DOUT => o, VSS => OPEN, R_EN => localen, EN => en, VDDIO => OPEN, VDD => OPEN, VSSIO => OPEN, PULL_UP => '0', PULL_DOWN => '0');
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library work;
use work.all;
-- pragma translate_off
library saed32;
use saed32.D4I1025_NS;
use saed32.D12I1025_NS;
use saed32.D16I1025_NS;
-- pragma translate_on
entity saed32_outpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i : in std_logic);
end ;
architecture rtl of saed32_outpad is
component D4I1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; EN : in std_logic; VDDIO : inout std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DIN : in std_logic); end component;
component D12I1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; EN : in std_logic; VDDIO : inout std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DIN : in std_logic); end component;
component D16I1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; EN : in std_logic; VDDIO : inout std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DIN : in std_logic); end component;
signal localout,localpad : std_logic;
begin
f4 : if (strength <= 4) generate
op : D4I1025_NS port map (DIN => i, PADIO => localpad, VSS => OPEN, EN => '1', VDDIO => OPEN, VDD => OPEN, VSSIO => OPEN);
end generate;
f12 : if (strength > 4) and (strength <= 12) generate
op : D12I1025_NS port map (DIN => i, PADIO => localpad, VSS => OPEN, EN => '1', VDDIO => OPEN, VDD => OPEN, VSSIO => OPEN);
end generate;
f16 : if (strength > 12) generate
op : D16I1025_NS port map (DIN => i, PADIO => localpad, VSS => OPEN, EN => '1', VDDIO => OPEN, VDD => OPEN, VSSIO => OPEN);
end generate;
pad <= localpad;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library work;
use work.all;
-- pragma translate_off
library saed32;
use saed32.B4ISH1025_NS;
use saed32.B12ISH1025_NS;
use saed32.B16ISH1025_NS;
-- pragma translate_on
entity saed32_toutpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i, en : in std_logic);
end ;
architecture rtl of saed32_toutpad is
component B4ISH1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; PULL_UP : in std_logic; VDDIO : inout std_logic; EN : in std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DOUT : out std_logic; DIN : in std_logic; PULL_DOWN : in std_logic; R_EN : in std_logic); end component;
component B12ISH1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; PULL_UP : in std_logic; VDDIO : inout std_logic; EN : in std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DOUT : out std_logic; DIN : in std_logic; PULL_DOWN : in std_logic; R_EN : in std_logic); end component;
component B16ISH1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; PULL_UP : in std_logic; VDDIO : inout std_logic; EN : in std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DOUT : out std_logic; DIN : in std_logic; PULL_DOWN : in std_logic; R_EN : in std_logic); end component;
signal localpad : std_logic;
begin
f4 : if (strength <= 4) generate
op : B4ISH1025_NS port map (DIN => i,PADIO => localpad, DOUT => OPEN, VSS => OPEN, R_EN => '0', EN => en, VDDIO => OPEN, VDD => OPEN, VSSIO => OPEN, PULL_UP => '0', PULL_DOWN => '0');
end generate;
f12 : if (strength > 4) and (strength <= 12) generate
op : B12ISH1025_NS port map (DIN => i, PADIO => localpad, DOUT => OPEN, VSS => OPEN, R_EN => '0', EN => en, VDDIO => OPEN, VDD => OPEN, VSSIO => OPEN, PULL_UP => '0', PULL_DOWN => '0');
end generate;
f16 : if (strength > 12) generate
op : B16ISH1025_NS port map (DIN => i, PADIO => localpad, DOUT => OPEN, VSS => OPEN, R_EN => '0', EN => en, VDDIO => OPEN, VDD => OPEN, VSSIO => OPEN, PULL_UP => '0', PULL_DOWN => '0');
end generate;
pad <= localpad;
end;
| gpl-2.0 | a5a399031b8df5421584af63d2502672 | 0.655975 | 3.235816 | false | false | false | false |
dawsonjon/FPGA-TX | synthesis/nexys_4/tx/fifo.vhd | 3 | 1,952 | library ieee;
use ieee.std_logic_1164.all;
entity fifo is
generic(
width : integer;
depth : integer
);
port(
clk : in std_logic;
rst : in std_logic;
input : in std_logic_vector(width-1 downto 0);
input_stb : in std_logic;
input_ack : out std_logic;
output : out std_logic_vector(width-1 downto 0);
output_stb : out std_logic;
output_ack : in std_logic
);
end entity fifo;
architecture rtl of fifo is
signal s_output_stb, s_input_ack, full, empty, read, write : std_logic;
signal a_out, a_in : integer range 0 to depth - 1 := 0;
type memory_type is array (0 to depth - 1) of std_logic_vector(width -1 downto 0);
signal memory : memory_type;
begin
process
begin
wait until rising_edge(clk);
if write = '1' then
memory(a_in) <= input;
end if;
if read = '1' then
output <= memory(a_out);
end if;
end process;
process
begin
wait until rising_edge(clk);
s_output_stb <= '0';
if read = '1' then
--data is available on clock following read
s_output_stb <= '1';
if a_out = (depth - 1) then
a_out <= 0;
else
a_out <= a_out + 1;
end if;
end if;
--if data has not been read, extend strobe
if s_output_stb = '1' and output_ack = '0' then
s_output_stb <= '1';
end if;
if write = '1' then
if a_in = (depth - 1) then
a_in <= 0;
else
a_in <= a_in + 1;
end if;
end if;
if rst = '1' then
a_out <= 0;
a_in <= 0;
s_output_stb <= '0';
end if;
end process;
full <= '1' when (a_out-1) = a_in else
'1' when (a_out = 0) and (a_in = depth - 1) else
'0';
empty <= '1' when a_out = a_in else '0';
s_input_ack <= not full;
output_stb <= s_output_stb;
input_ack <= s_input_ack;
write <= s_input_ack and input_stb;
read <= ((not s_output_stb) or output_ack) and (not empty);
end rtl;
| mit | 7d2bbd2d0202d061e7cd6d81c2ef9b16 | 0.553279 | 3.045242 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-digilent-nexys3/leon3mp.vhd | 1 | 19,317 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2013 Aeroflex Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.net.all;
use gaisler.jtag.all;
--pragma translate_off
use gaisler.sim.all;
--pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
clk : in std_ulogic;
-- onBoard Cellular RAM, Numonyx StrataFlash and Numonyx Quad Flash
MemOE : out std_ulogic;
MemWR : out std_ulogic;
RamAdv : out std_ulogic;
RamCS : out std_ulogic;
RamClk : out std_ulogic;
RamCRE : out std_ulogic;
RamLB : out std_ulogic;
RamUB : out std_ulogic;
RamWait : out std_ulogic;
FlashRp : out std_ulogic;
FlashCS : out std_ulogic;
QuadSpiFlashCS : out std_ulogic;
QuadSpiFlashSck : out std_ulogic;
QuadSpiFlashDB : inout std_logic_vector(0 downto 0);
address : out std_logic_vector(25 downto 0);
data : inout std_logic_vector(15 downto 0);
-- 7 segment display
--seg : out std_logic_vector(7 downto 0);
--an : out std_logic_vector(3 downto 0);
-- LEDs
led : out std_logic_vector(7 downto 0);
-- Switches
sw : in std_logic_vector(7 downto 0);
-- Buttons
btn : in std_logic_vector(4 downto 0); -- reset on btn0
-- VGA Connector
--vgaRed : out std_logic_vector(2 downto 0);
--vgaGreen : out std_logic_vector(2 downto 0);
--vgaBlue : out std_logic_vector(2 downto 1);
--Hsync : out std_ulogic;
--Vsync : out std_ulogic;
-- 12 pin connectors
--ja : inout std_logic_vector(7 downto 0);
--jb : inout std_logic_vector(7 downto 0);
--jc : inout std_logic_vector(7 downto 0);
--jd : inout std_logic_vector(7 downto 0);
-- SMSC ethernet PHY
PhyRstn : out std_ulogic;
PhyCrs : in std_ulogic;
PhyCol : in std_ulogic;
PhyClk25Mhz : out std_ulogic;
PhyTxd : out std_logic_vector(3 downto 0);
PhyTxEn : out std_ulogic;
PhyTxClk : in std_ulogic;
PhyTxEr : out std_ulogic;
PhyRxd : in std_logic_vector(3 downto 0);
PhyRxDv : in std_ulogic;
PhyRxEr : in std_ulogic;
PhyRxClk : in std_ulogic;
PhyMdc : out std_ulogic;
PhyMdio : inout std_logic;
-- Pic USB-HID interface
--PS2KeyboardData : inout std_logic;
--PS2KeyboardClk : inout std_logic;
--PS2MouseData : inout std_logic;
--PS2MouseClk : inout std_logic;
--PicGpio : out std_logic_vector(1 downto 0);
-- USB-RS232 interface
RsRx : in std_logic;
RsTx : out std_logic
);
end;
architecture rtl of leon3mp is
signal vcc : std_logic;
signal gnd : std_logic;
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal gpti : gptimer_in_type;
signal spii : spi_in_type;
signal spio : spi_out_type;
signal slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
signal spmi : spimctrl_in_type;
signal spmo : spimctrl_out_type;
signal clkm, rstn, clkml : std_ulogic;
signal tck, tms, tdi, tdo : std_ulogic;
signal rstraw : std_logic;
signal lock : std_logic;
-- RS232 APB Uart
signal rxd1 : std_logic;
signal txd1 : std_logic;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of lock : signal is true;
attribute syn_keep of clkml : signal is true;
attribute syn_keep of clkm : signal is true;
attribute syn_preserve of clkml : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute keep of lock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
constant BOARD_FREQ : integer := 100000; -- CLK input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1';
gnd <= '0';
led(7 downto 4) <= (others =>'0'); -- unused leds off
cgi.pllctrl <= "00";
cgi.pllrst <= rstraw;
rst0 : rstgen generic map (acthigh => 1)
port map (btn(0), clkm, lock, rstn, rstraw);
lock <= cgo.clklock;
-- clock generator
clkgen0 : clkgen
generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (clk, gnd, clkm, open, open, open, open, cgi, cgo, open, open, open);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1,
nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH,
nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
-- LEON3 processor
leon3gen : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR,
CFG_NCPU-1)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
led(3) <= not dbgo(0).error;
led(2) <= not dsuo.active;
-- LEON3 Debug Support Unit
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
-- Debug UART
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart
generic map (hindex => CFG_NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (RsRx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (RsTx, duo.txd);
led(0) <= not dui.rxd;
led(1) <= not duo.txd;
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd);
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 5, pindex => 0, paddr => 0, iomask => 0,
ram8 => CFG_MCTRL_RAM8BIT, ram16 => CFG_MCTRL_RAM16BIT,srbanks=>1)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(5), apbi, apbo(0), wpo, open);
end generate;
memi.brdyn <= '1';
memi.bexcn <= '1';
memi.writen <= '1';
memi.wrn <= "1111";
memi.bwidth <= "01";
mg0 : if (CFG_MCTRL_LEON2 = 0) generate
apbo(0) <= apb_none;
ahbso(5) <= ahbs_none;
memo.bdrive(0) <= '1';
end generate;
mgpads : if (CFG_MCTRL_LEON2 /= 0) generate
addr_pad : outpadv generic map (tech => padtech, width => 26)
port map (address, memo.address(26 downto 1));
oen_pad : outpad generic map (tech => padtech)
port map (MemOE, memo.oen);
cs_pad : outpad generic map (tech => padtech)
port map (RamCS, memo.ramsn(0));
lb_pad : outpad generic map (tech => padtech)
port map (RamLB, memo.mben(0));
ub_pad : outpad generic map (tech => padtech)
port map (RamUB, memo.mben(1));
wri_pad : outpad generic map (tech => padtech)
port map (MemWR, memo.writen);
fce_pad : outpad generic map (tech => padtech)
port map (FlashCS, memo.romsn(0));
frp_pad : outpad generic map (tech => padtech)
port map (FlashRp, memo.writen);
end generate;
bdr : iopadv generic map (tech => padtech, width => 8)
port map (data(7 downto 0), memo.data(23 downto 16),
memo.bdrive(1), memi.data(23 downto 16));
bdr2 : iopadv generic map (tech => padtech, width => 8)
port map (data(15 downto 8), memo.data(31 downto 24),
memo.bdrive(0), memi.data(31 downto 24));
RamCRE <= '0';
RamClk <= '0';
RamAdv <= '0';
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
-- APB Bridge
apb0 : apbctrl
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
-- Interrupt controller
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
-- Time Unit
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW,
ntimers => CFG_GPT_NTIM, nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop;
gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
-- Console UART.
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1;
u1i.ctsn <= '0';
u1i.extclk <= '0';
txd1 <= u1o.txd;
-- The USB UART is curently mapped to ahbuart.
-- serrx_pad : inpad generic map (tech => padtech) port map (RsRx, rxd1);
-- sertx_pad : outpad generic map (tech => padtech) port map (RsTx, txd1);
-- led(0) <= not rxd1;
-- led(1) <= not txd1;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
nospi: if CFG_SPICTRL_ENABLE = 0 and CFG_SPIMCTRL = 0 generate
apbo(7) <= apb_none;
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm
generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 15, paddr => 15, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 7,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G)
port map(rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG),
apbi => apbi, apbo => apbo(15), ethi => ethi, etho => etho);
PhyRstn<=rstn;
end generate;
ethpads : if (CFG_GRETH = 1) generate -- eth pads
emdio_pad : iopad generic map (tech => padtech)
port map (PhyMdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (PhyTxClk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (PhyRxClk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (PhyRxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (PhyRxDv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (PhyRxEr, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (PhyCol, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (PhyCrs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (PhyTxd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map (PhyTxEn, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (PhyTxEr, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (PhyMdc, etho.mdc);
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram
generic map (hindex => 3, haddr => CFG_AHBRADDR, tech => CFG_MEMTECH,
kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate;
-----------------------------------------------------------------------
-- Test report module, only used for simulation ----------------------
-----------------------------------------------------------------------
--pragma translate_off
test0 : ahbrep generic map (hindex => 4, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(4));
--pragma translate_on
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+1) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Demonstration design for Digilent NEXYS 3 board",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end rtl;
| gpl-2.0 | 9443dc7a82960eb1f4ddcfab9064f7c4 | 0.524409 | 3.90716 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-xilinx-sp605/testbench.vhd | 1 | 16,677 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
pcie_target_simulation : integer := 0; -- set to 1 to test pci express, only if pcie_target is enabled
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := 40;
signal address : std_logic_vector(24 downto 0);
signal data : std_logic_vector(15 downto 0);
signal button : std_logic_vector(3 downto 0) := "0000";
signal genio : std_logic_vector(59 downto 0);
signal romsn : std_logic;
signal oen : std_ulogic;
signal writen : std_ulogic;
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal txd1, rxd1 : std_logic;
signal txd2, rxd2 : std_logic;
signal ctsn1, rtsn1 : std_ulogic;
signal ctsn2, rtsn2 : std_ulogic;
signal phy_mii_data: std_logic; -- ethernet PHY interface
signal phy_tx_clk : std_ulogic;
signal phy_rx_clk : std_ulogic;
signal phy_rx_data : std_logic_vector(7 downto 0);
signal phy_dv : std_ulogic;
signal phy_rx_er : std_ulogic;
signal phy_col : std_ulogic;
signal phy_crs : std_ulogic;
signal phy_tx_data : std_logic_vector(7 downto 0);
signal phy_tx_en : std_ulogic;
signal phy_tx_er : std_ulogic;
signal phy_mii_clk : std_ulogic;
signal phy_rst_n : std_ulogic;
signal phy_gtx_clk : std_ulogic;
signal phy_mii_int_n : std_ulogic;
signal clk27 : std_ulogic := '0';
signal clk200p : std_ulogic := '0';
signal clk200n : std_ulogic := '1';
signal clk33 : std_ulogic := '0';
signal iic_scl : std_ulogic;
signal iic_sda : std_ulogic;
signal ddc_scl : std_ulogic;
signal ddc_sda : std_ulogic;
signal dvi_iic_scl : std_logic;
signal dvi_iic_sda : std_logic;
signal tft_lcd_data : std_logic_vector(11 downto 0);
signal tft_lcd_clk_p : std_ulogic;
signal tft_lcd_clk_n : std_ulogic;
signal tft_lcd_hsync : std_ulogic;
signal tft_lcd_vsync : std_ulogic;
signal tft_lcd_de : std_ulogic;
signal tft_lcd_reset_b : std_ulogic;
-- DDR2 memory
signal ddr_clk : std_logic;
signal ddr_clkb : std_logic;
signal ddr_clk_fb : std_logic;
signal ddr_cke : std_logic;
signal ddr_csb : std_logic := '0';
signal ddr_we : std_ulogic; -- write enable
signal ddr_ras : std_ulogic; -- ras
signal ddr_cas : std_ulogic; -- cas
signal ddr_dm : std_logic_vector(1 downto 0); -- dm
signal ddr_dqs : std_logic_vector(1 downto 0); -- dqs
signal ddr_dqsn : std_logic_vector(1 downto 0); -- dqsn
signal ddr3_tdqs_n : std_logic_vector(1 downto 0); -- dqsn
signal ddr_ad : std_logic_vector(12 downto 0); -- address
signal ddr_ba : std_logic_vector(2 downto 0); -- bank address
signal ddr_dq : std_logic_vector(15 downto 0); -- data
signal ddr_dq2 : std_logic_vector(15 downto 0); -- data
signal ddr_odt : std_logic;
signal ddr_reset_n: std_logic;
signal ddr_rzq : std_logic;
signal ddr_zio : std_logic;
-- SPI flash
signal spi_sel_n : std_ulogic;
signal spi_clk : std_ulogic;
signal spi_mosi : std_ulogic;
signal sysace_mpa : std_logic_vector(6 downto 0);
signal sysace_mpce : std_ulogic;
signal sysace_mpirq : std_ulogic;
signal sysace_mpoe : std_ulogic;
signal sysace_mpwe : std_ulogic;
signal sysace_d : std_logic_vector(7 downto 0);
signal dsurst : std_ulogic;
signal errorn : std_logic;
signal switch : std_logic_vector(3 downto 0); -- I/O port
signal led : std_logic_vector(3 downto 0); -- I/O port
constant lresp : boolean := false;
-----------------------------------------------------FOR PCIE---------------
function REF_CLK_HALF_CYCLE(FREQ_SEL : integer) return integer is
begin
case FREQ_SEL is
when 0 => return 5000; -- 100 MHz / 5000 ps half-cycle
when 1 => return 4000; -- 125 MHz / 4000 ps half-cycle
when others => return 1; -- invalid case
end case;
end REF_CLK_HALF_CYCLE;
component xilinx_pcie_2_0_rport_v6 is
generic
(
REF_CLK_FREQ : integer := 0;
ALLOW_X8_GEN2 : boolean := FALSE;
PL_FAST_TRAIN : boolean := FALSE;
LINK_CAP_MAX_LINK_SPEED : bit_vector := X"1";
DEVICE_ID : bit_vector := X"0007";
LINK_CAP_MAX_LINK_WIDTH : bit_vector := X"08";
LTSSM_MAX_LINK_WIDTH : bit_vector := X"08";
LINK_CAP_MAX_LINK_WIDTH_int : integer := 8;
LINK_CTRL2_TARGET_LINK_SPEED : bit_vector := X"2";
DEV_CAP_MAX_PAYLOAD_SUPPORTED : integer := 2;
USER_CLK_FREQ : integer := 3;
VC0_TX_LASTPACKET : integer := 31;
VC0_RX_RAM_LIMIT : bit_vector := X"03FF";
VC0_TOTAL_CREDITS_CD : integer := 154;
VC0_TOTAL_CREDITS_PD : integer := 154
);
port (
sys_clk : in std_logic;
sys_reset_n : in std_logic;
pci_exp_rxn : in std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
pci_exp_rxp : in std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
pci_exp_txn : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
pci_exp_txp : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0)
);
end component xilinx_pcie_2_0_rport_v6;
component sys_clk_gen is
generic
(
HALFCYCLE : integer := 500;
OFFSET : integer := 0
);
port
(
sys_clk : out std_logic
);
end component sys_clk_gen;
component sys_clk_gen_ds is
generic
(
HALFCYCLE : integer := 500;
OFFSET : integer := 0
);
port
(
sys_clk_p : out std_logic;
sys_clk_n : out std_logic
);
end component sys_clk_gen_ds;
--
-- System reset
--
signal sys_reset_n : std_logic;
--
-- System clocks
--
signal rp_sys_clk : std_logic;
signal ep_sys_clk_p : std_logic;
signal ep_sys_clk_n : std_logic;
--
-- PCI-Express Serial Interconnect
--
signal ep_pci_exp_txn : std_logic_vector(0 downto 0);
signal ep_pci_exp_txp : std_logic_vector(0 downto 0);
signal rp_pci_exp_txn : std_logic_vector(0 downto 0);
signal rp_pci_exp_txp : std_logic_vector(0 downto 0);
--
-- Misc. signals
--
signal led_0 : std_logic;
signal led_1 : std_logic;
signal led_2 : std_logic;
-----------------------------------------------pcie end--------------
begin
-- clock and reset
clk27 <= not clk27 after ct * 1 ns;
clk33 <= not clk33 after 15 ns;
clk200p <= not clk200p after 2.5 ns;
clk200n <= not clk200n after 2.5 ns;
rst <= not dsurst;
rxd1 <= 'H'; ctsn1 <= '0';
rxd2 <= 'H'; ctsn2 <= '0';
button <= "0000";
switch <= "0000";
---------------------pcie----------------------------------------------
pcie_sim: if pcie_target_simulation = 1 generate
RP : xilinx_pcie_2_0_rport_v6
generic map (
REF_CLK_FREQ => 1,
PL_FAST_TRAIN => TRUE,
ALLOW_X8_GEN2 => FALSE,
LINK_CAP_MAX_LINK_SPEED => X"1",
DEVICE_ID => X"0007",
LINK_CAP_MAX_LINK_WIDTH => X"01",
LTSSM_MAX_LINK_WIDTH => X"01",
LINK_CAP_MAX_LINK_WIDTH_int => 1,
LINK_CTRL2_TARGET_LINK_SPEED => X"1",
DEV_CAP_MAX_PAYLOAD_SUPPORTED => 2,
USER_CLK_FREQ => 3,
VC0_TX_LASTPACKET => 31,
VC0_RX_RAM_LIMIT => X"03FF",
VC0_TOTAL_CREDITS_CD => 154,
VC0_TOTAL_CREDITS_PD => 154
)
port map (
-- SYS Inteface
sys_clk => rp_sys_clk,
sys_reset_n => sys_reset_n,
-- PCI-Express Interface
pci_exp_txn => rp_pci_exp_txn,
pci_exp_txp => rp_pci_exp_txp,
pci_exp_rxn => ep_pci_exp_txn,
pci_exp_rxp => ep_pci_exp_txp
);
--
-- Generate system clocks and reset
--
CLK_GEN_RP : sys_clk_gen
generic map (
HALFCYCLE => REF_CLK_HALF_CYCLE(1),
OFFSET => 0
)
port map (
sys_clk => rp_sys_clk
);
CLK_GEN_EP : sys_clk_gen_ds
generic map (
HALFCYCLE => REF_CLK_HALF_CYCLE(1),
OFFSET => 0
)
port map (
sys_clk_p => ep_sys_clk_p,
sys_clk_n => ep_sys_clk_n
);
BOARD_INIT : process
begin
report("[" & time'image(now) & "] : System Reset Asserted...");
sys_reset_n <= '0';
for n in 0 to 499 loop
wait until rising_edge(ep_sys_clk_p);
end loop;
report("[" & time'image(now) & "] : System Reset De-asserted...");
sys_reset_n <= '1';
wait until falling_edge(sys_reset_n); -- forever
end process BOARD_INIT;
end generate;
--------------------------------------pcie---------------------------
cpu : entity work.leon3mp
generic map ( fabtech, memtech, padtech, clktech,
disas, dbguart, pclow )
port map (rst, clk27, clk200p, clk200n, clk33, address(24 downto 1),
data, oen, writen, romsn,
ddr_clk, ddr_clkb, ddr_cke, ddr_odt, ddr_reset_n, ddr_we, ddr_ras, ddr_cas, ddr_dm,
ddr_dqs, ddr_dqsn, ddr_ad, ddr_ba, ddr_dq, ddr_rzq, ddr_zio,
txd1, rxd1, ctsn1, rtsn1, button,
switch, led,
phy_gtx_clk, phy_mii_data, phy_tx_clk, phy_rx_clk,
phy_rx_data, phy_dv, phy_rx_er, phy_col, phy_crs, phy_tx_data,
phy_tx_en, phy_tx_er, phy_mii_clk, phy_rst_n, phy_mii_int_n,
iic_scl, iic_sda, ddc_scl, ddc_sda,
dvi_iic_scl, dvi_iic_sda,
tft_lcd_data, tft_lcd_clk_p, tft_lcd_clk_n, tft_lcd_hsync,
tft_lcd_vsync, tft_lcd_de, tft_lcd_reset_b,
spi_sel_n, spi_clk, spi_mosi, ep_pci_exp_txn(0), ep_pci_exp_txp(0), rp_pci_exp_txn(0),
rp_pci_exp_txp(0), ep_sys_clk_p, ep_sys_clk_n, sys_reset_n,
sysace_mpa, sysace_mpce, sysace_mpirq, sysace_mpoe,
sysace_mpwe, sysace_d
);
-- prom0 : sram generic map (index => 6, abits => romdepth, fname => promfile)
-- port map (address(romdepth-1 downto 0), data(31 downto 24), romsn,
-- writen, oen);
prom0 : for i in 0 to 1 generate
sr0 : sram generic map (index => i+4, abits => 24, fname => promfile)
port map (address(24 downto 1), data(15-i*8 downto 8-i*8), romsn,
writen, oen);
end generate;
address(0) <= '0';
u1 : ddr3ram
generic map (
width => 16, abits => 13, fname => sdramfile,
speedbin => 3,
ldguard => 1
)
port map (
ck => ddr_clk, ckn => ddr_clkb, cke => ddr_cke, csn => ddr_csb, odt => ddr_odt,
rasn => ddr_ras, casn => ddr_cas, wen => ddr_we,
dm => ddr_dm, ba => ddr_ba, a => ddr_ad, resetn => ddr_reset_n,
dq => ddr_dq, dqs => ddr_dqs, dqsn => ddr_dqsn,
doload => led(2)
);
errorn <= led(1);
errorn <= 'H'; -- ERROR pull-up
phy0 : if (CFG_GRETH = 1) generate
phy_mii_data <= 'H';
p0: phy
generic map (address => 7)
port map(phy_rst_n, phy_mii_data, phy_tx_clk, phy_rx_clk, phy_rx_data,
phy_dv, phy_rx_er, phy_col, phy_crs, phy_tx_data, phy_tx_en,
phy_tx_er, phy_mii_clk, phy_gtx_clk);
end generate;
sysace_mpirq <= '0';
sysace_d <= (others => 'Z');
iuerr : process
begin
wait for 5000 ns;
if to_x01(errorn) = '1' then wait on errorn; end if;
assert (to_x01(errorn) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
data <= buskeep(data) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 320 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 2500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#2e#, txp);
wait for 25000 ns;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0D#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#70#, 16#11#, 16#78#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#0D#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#00#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
wait;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#aa#, txp);
txa(dsutx, 16#00#, 16#55#, 16#00#, 16#55#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#a0#, txp);
txa(dsutx, 16#01#, 16#02#, 16#09#, 16#33#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#80#, 16#00#, 16#02#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(txd2, rxd2);
wait;
end process;
end ;
| gpl-2.0 | 2a18dbdbc56a6b2cb4119553e90897f0 | 0.557834 | 3.053277 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/tech/virage/simprims/virage_simprims.vhd | 1 | 18,532 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: virage_simprims
-- File: virage_simprims.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: Simple simulation models for VIRAGE RAMs
-----------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
package virage_simprims is
component virage_syncram_sim
generic ( abits : integer := 10; dbits : integer := 8 );
port (
addr : in std_logic_vector((abits -1) downto 0);
clk : in std_logic;
di : in std_logic_vector((dbits -1) downto 0);
do : out std_logic_vector((dbits -1) downto 0);
me : in std_logic;
oe : in std_logic;
we : in std_logic
);
end component;
-- synchronous 2-port ram
component virage_2pram_sim
generic (
abits : integer := 8;
dbits : integer := 32;
words : integer := 256
);
port (
addra, addrb : in std_logic_vector((abits -1) downto 0);
clka, clkb : in std_logic;
dia : in std_logic_vector((dbits -1) downto 0);
dob : out std_logic_vector((dbits -1) downto 0);
mea, wea, meb, oeb : in std_logic
);
end component;
component virage_dpram_sim
generic (
abits : integer := 8;
dbits : integer := 32
);
port (
addra : in std_logic_vector((abits -1) downto 0);
clka : in std_logic;
dia : in std_logic_vector((dbits -1) downto 0);
doa : out std_logic_vector((dbits -1) downto 0);
mea, oea, wea : in std_logic;
addrb : in std_logic_vector((abits -1) downto 0);
clkb : in std_logic;
dib : in std_logic_vector((dbits -1) downto 0);
dob : out std_logic_vector((dbits -1) downto 0);
meb, oeb, web : in std_logic
);
end component;
end;
-- 1-port syncronous ram
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity virage_syncram_sim is
generic (
abits : integer := 10;
dbits : integer := 8
);
port (
addr : in std_logic_vector((abits -1) downto 0);
clk : in std_logic;
di : in std_logic_vector((dbits -1) downto 0);
do : out std_logic_vector((dbits -1) downto 0);
me : in std_logic;
oe : in std_logic;
we : in std_logic
);
end;
architecture behavioral of virage_syncram_sim is
subtype word is std_logic_vector((dbits -1) downto 0);
type mem is array(0 to (2**abits -1)) of word;
begin
main : process(clk, oe, me)
variable memarr : mem;-- := (others => (others => '0'));
variable doint : std_logic_vector((dbits -1) downto 0);
begin
if rising_edge(clk) and (me = '1') and not is_x(addr) then
if (we = '1') then memarr(to_integer(unsigned(addr))) := di; end if;
doint := memarr(to_integer(unsigned(addr)));
end if;
-- if (me and oe) = '1' then do <= doint;
if oe = '1' then do <= doint;
else do <= (others => 'Z'); end if;
end process;
end behavioral;
-- synchronous 2-port ram
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity virage_2pram_sim is
generic (
abits : integer := 10;
dbits : integer := 8;
words : integer := 1024
);
port (
addra, addrb : in std_logic_vector((abits -1) downto 0);
clka, clkb : in std_logic;
dia : in std_logic_vector((dbits -1) downto 0);
dob : out std_logic_vector((dbits -1) downto 0);
mea, wea, meb, oeb : in std_logic
);
end;
architecture behavioral of virage_2pram_sim is
subtype word is std_logic_vector((dbits -1) downto 0);
type mem is array(0 to (words-1)) of word;
begin
main : process(clka, clkb, oeb, mea, meb, wea)
variable memarr : mem;
variable doint : std_logic_vector((dbits -1) downto 0);
begin
if rising_edge(clka) and (mea = '1') and not is_x(addra) then
if (wea = '1') then memarr(to_integer(unsigned(addra)) mod words) := dia; end if;
end if;
if rising_edge(clkb) and (meb = '1') and not is_x(addrb) then
doint := memarr(to_integer(unsigned(addrb)) mod words);
end if;
if oeb = '1' then dob <= doint;
else dob <= (others => 'Z'); end if;
end process;
end behavioral;
-- synchronous dual-port ram
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity virage_dpram_sim is
generic (
abits : integer := 10;
dbits : integer := 8
);
port (
addra : in std_logic_vector((abits -1) downto 0);
clka : in std_logic;
dia : in std_logic_vector((dbits -1) downto 0);
doa : out std_logic_vector((dbits -1) downto 0);
mea, oea, wea : in std_logic;
addrb : in std_logic_vector((abits -1) downto 0);
clkb : in std_logic;
dib : in std_logic_vector((dbits -1) downto 0);
dob : out std_logic_vector((dbits -1) downto 0);
meb, oeb, web : in std_logic
);
end;
architecture behavioral of virage_dpram_sim is
subtype word is std_logic_vector((dbits -1) downto 0);
type mem is array(0 to (2**abits -1)) of word;
begin
main : process(clka, oea, mea, clkb, oeb, meb)
variable memarr : mem;
variable dointa, dointb : std_logic_vector((dbits -1) downto 0);
begin
if rising_edge(clka) and (mea = '1') and not is_x(addra) then
if (wea = '1') then memarr(to_integer(unsigned(addra))) := dia; end if;
dointa := memarr(to_integer(unsigned(addra)));
end if;
if oea = '1' then doa <= dointa;
else doa <= (others => 'Z'); end if;
if rising_edge(clkb) and (meb = '1') and not is_x(addrb) then
if (web = '1') then memarr(to_integer(unsigned(addrb))) := dib; end if;
dointb := memarr(to_integer(unsigned(addrb)));
end if;
if oeb = '1' then dob <= dointb;
else dob <= (others => 'Z'); end if;
end process;
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_128x32cm4sw0ab is
port (
addr, taddr : in std_logic_vector(6 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_128x32cm4sw0ab is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 7, dbits => 32)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_256x32cm4sw0ab is
port (
addr, taddr : in std_logic_vector(7 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_256x32cm4sw0ab is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 8, dbits => 32)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_512x32cm4sw0ab is
port (
addr, taddr : in std_logic_vector(8 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_512x32cm4sw0ab is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 9, dbits => 32)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_512x38cm4sw0ab is
port (
addr, taddr : in std_logic_vector(8 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(37 downto 0);
do : out std_logic_vector(37 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_512x38cm4sw0ab is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 9, dbits => 38)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_1024x32cm4sw0ab is
port (
addr, taddr : in std_logic_vector(9 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_1024x32cm4sw0ab is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 10, dbits => 32)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_2048x32cm8sw0ab is
port (
addr, taddr : in std_logic_vector(10 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_2048x32cm8sw0ab is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 11, dbits => 32)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_4096x36cm8sw0ab is
port (
addr, taddr : in std_logic_vector(11 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(35 downto 0);
do : out std_logic_vector(35 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_4096x36cm8sw0ab is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 12, dbits => 36)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_16384x8cm16sw0 is
port (
addr : in std_logic_vector(13 downto 0);
clk : in std_logic;
di : in std_logic_vector(7 downto 0);
do : out std_logic_vector(7 downto 0);
me, oe, we : in std_logic
);
end;
architecture behavioral of hdss1_16384x8cm16sw0 is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 14, dbits => 8)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
-- 2-port syncronous ram
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity rfss2_136x32cm2sw0ab is
port (
addra, taddra : in std_logic_vector(7 downto 0);
addrb, taddrb : in std_logic_vector(7 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dob : out std_logic_vector(31 downto 0);
mea, wea, tmea, twea, bistea : in std_logic;
meb, oeb, tmeb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of rfss2_136x32cm2sw0ab is
begin
syncram0 : virage_2pram_sim
generic map ( abits => 8, dbits => 32, words => 136)
port map ( addra, addrb, clka, clkb, dia, dob, mea, wea, meb, oeb);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity rfss2_136x40cm2sw0ab is
port (
addra, taddra : in std_logic_vector(7 downto 0);
addrb, taddrb : in std_logic_vector(7 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(39 downto 0);
dob : out std_logic_vector(39 downto 0);
mea, wea, tmea, twea, bistea : in std_logic;
meb, oeb, tmeb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of rfss2_136x40cm2sw0ab is
begin
syncram0 : virage_2pram_sim
generic map ( abits => 8, dbits => 40, words => 136)
port map ( addra, addrb, clka, clkb, dia, dob, mea, wea, meb, oeb);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity rfss2_168x32cm2sw0ab is
port (
addra, taddra : in std_logic_vector(7 downto 0);
addrb, taddrb : in std_logic_vector(7 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dob : out std_logic_vector(31 downto 0);
mea, wea, tmea, twea, bistea : in std_logic;
meb, oeb, tmeb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of rfss2_168x32cm2sw0ab is
begin
syncram0 : virage_2pram_sim
generic map ( abits => 8, dbits => 32, words => 168)
port map ( addra, addrb, clka, clkb, dia, dob, mea, wea, meb, oeb);
end behavioral;
-- dual-port syncronous ram
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss2_64x32cm4sw0ab is
port (
addra, taddra : in std_logic_vector(5 downto 0);
addrb, taddrb : in std_logic_vector(5 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of hdss2_64x32cm4sw0ab is
begin
syncram0 : virage_dpram_sim
generic map ( abits => 6, dbits => 32)
port map ( addra, clka, dia, doa, mea, oea, wea,
addrb, clkb, dib, dob, meb, oeb, web);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss2_128x32cm4sw0ab is
port (
addra, taddra : in std_logic_vector(6 downto 0);
addrb, taddrb : in std_logic_vector(6 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of hdss2_128x32cm4sw0ab is
begin
syncram0 : virage_dpram_sim
generic map ( abits => 7, dbits => 32)
port map ( addra, clka, dia, doa, mea, oea, wea,
addrb, clkb, dib, dob, meb, oeb, web);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss2_256x32cm4sw0ab is
port (
addra, taddra : in std_logic_vector(7 downto 0);
addrb, taddrb : in std_logic_vector(7 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of hdss2_256x32cm4sw0ab is
begin
syncram0 : virage_dpram_sim
generic map ( abits => 8, dbits => 32)
port map ( addra, clka, dia, doa, mea, oea, wea,
addrb, clkb, dib, dob, meb, oeb, web);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss2_512x32cm4sw0ab is
port (
addra, taddra : in std_logic_vector(8 downto 0);
addrb, taddrb : in std_logic_vector(8 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of hdss2_512x32cm4sw0ab is
begin
syncram0 : virage_dpram_sim
generic map ( abits => 9, dbits => 32)
port map ( addra, clka, dia, doa, mea, oea, wea,
addrb, clkb, dib, dob, meb, oeb, web);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss2_512x38cm4sw0ab is
port (
addra, taddra : in std_logic_vector(8 downto 0);
addrb, taddrb : in std_logic_vector(8 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(37 downto 0);
dib, tdib : in std_logic_vector(37 downto 0);
doa, dob : out std_logic_vector(37 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of hdss2_512x38cm4sw0ab is
begin
syncram0 : virage_dpram_sim
generic map ( abits => 9, dbits => 38)
port map ( addra, clka, dia, doa, mea, oea, wea,
addrb, clkb, dib, dob, meb, oeb, web);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss2_8192x8cm16sw0ab is
port (
addra, taddra : in std_logic_vector(12 downto 0);
addrb, taddrb : in std_logic_vector(12 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(7 downto 0);
dib, tdib : in std_logic_vector(7 downto 0);
doa, dob : out std_logic_vector(7 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of hdss2_8192x8cm16sw0ab is
begin
syncram0 : virage_dpram_sim
generic map ( abits => 13, dbits => 8)
port map ( addra, clka, dia, doa, mea, oea, wea,
addrb, clkb, dib, dob, meb, oeb, web);
end behavioral;
-- pragma translate_on
| gpl-2.0 | 64f8dea161b1db3d17848a36a8694ac1 | 0.634092 | 3.167322 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.cache/ip/2017.2.1/841f5df448bf42bc/zqynq_lab_1_design_auto_pc_1_sim_netlist.vhdl | 1 | 533,334 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2.1 (win64) Build 1957588 Wed Aug 9 16:32:24 MDT 2017
-- Date : Fri Sep 22 14:40:47 2017
-- Host : EffulgentTome running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_auto_pc_1_sim_netlist.vhdl
-- Design : zqynq_lab_1_design_auto_pc_1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd is
port (
next_pending_r_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
axaddr_incr_reg : out STD_LOGIC_VECTOR ( 7 downto 0 );
\axaddr_incr_reg[11]_0\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axlen_cnt_reg[7]_0\ : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
\axlen_cnt_reg[4]_0\ : out STD_LOGIC;
\m_axi_awaddr[1]\ : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_reg_0 : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_reg_1 : in STD_LOGIC;
\state_reg[0]\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[51]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\state_reg[0]_rep\ : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr[4]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_5_n_0\ : STD_LOGIC;
signal \^axaddr_incr_reg\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^axaddr_incr_reg[11]_0\ : STD_LOGIC;
signal \^axaddr_incr_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_7\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_4_n_0\ : STD_LOGIC;
signal \^axlen_cnt_reg[7]_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[6]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[7]\ : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 7 downto 2 );
signal \NLW_axaddr_incr_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axlen_cnt[4]_i_2\ : label is "soft_lutpair113";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_3\ : label is "soft_lutpair113";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
axaddr_incr_reg(7 downto 0) <= \^axaddr_incr_reg\(7 downto 0);
\axaddr_incr_reg[11]_0\ <= \^axaddr_incr_reg[11]_0\;
\axaddr_incr_reg[3]_0\(3 downto 0) <= \^axaddr_incr_reg[3]_0\(3 downto 0);
\axlen_cnt_reg[7]_0\ <= \^axlen_cnt_reg[7]_0\;
\axaddr_incr[0]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"559AAAAAAAAAAAAA"
)
port map (
I0 => \m_payload_i_reg[51]\(3),
I1 => \state_reg[1]\(0),
I2 => \state_reg[1]\(1),
I3 => \state_reg[0]_rep\,
I4 => \m_payload_i_reg[51]\(5),
I5 => \m_payload_i_reg[51]\(4),
O => S(3)
);
\axaddr_incr[0]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000AAAA559AAAAA"
)
port map (
I0 => \m_payload_i_reg[51]\(2),
I1 => \state_reg[1]\(0),
I2 => \state_reg[1]\(1),
I3 => \state_reg[0]_rep\,
I4 => \m_payload_i_reg[51]\(5),
I5 => \m_payload_i_reg[51]\(4),
O => S(2)
);
\axaddr_incr[0]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000559AAAAA"
)
port map (
I0 => \m_payload_i_reg[51]\(1),
I1 => \state_reg[1]\(0),
I2 => \state_reg[1]\(1),
I3 => \state_reg[0]_rep\,
I4 => \m_payload_i_reg[51]\(4),
I5 => \m_payload_i_reg[51]\(5),
O => S(1)
);
\axaddr_incr[0]_i_18\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000559A"
)
port map (
I0 => \m_payload_i_reg[51]\(0),
I1 => \state_reg[1]\(0),
I2 => \state_reg[1]\(1),
I3 => \state_reg[0]_rep\,
I4 => \m_payload_i_reg[51]\(5),
I5 => \m_payload_i_reg[51]\(4),
O => S(0)
);
\axaddr_incr[4]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(3),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(3),
O => \axaddr_incr[4]_i_2_n_0\
);
\axaddr_incr[4]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(2),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(2),
O => \axaddr_incr[4]_i_3_n_0\
);
\axaddr_incr[4]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(1),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(1),
O => \axaddr_incr[4]_i_4_n_0\
);
\axaddr_incr[4]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(0),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(0),
O => \axaddr_incr[4]_i_5_n_0\
);
\axaddr_incr[8]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(7),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(7),
O => \axaddr_incr[8]_i_2_n_0\
);
\axaddr_incr[8]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(6),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(6),
O => \axaddr_incr[8]_i_3_n_0\
);
\axaddr_incr[8]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(5),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(5),
O => \axaddr_incr[8]_i_4_n_0\
);
\axaddr_incr[8]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(4),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(4),
O => \axaddr_incr[8]_i_5_n_0\
);
\axaddr_incr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(0),
Q => \^axaddr_incr_reg[3]_0\(0),
R => '0'
);
\axaddr_incr_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1_n_5\,
Q => \^axaddr_incr_reg\(6),
R => '0'
);
\axaddr_incr_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1_n_4\,
Q => \^axaddr_incr_reg\(7),
R => '0'
);
\axaddr_incr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(1),
Q => \^axaddr_incr_reg[3]_0\(1),
R => '0'
);
\axaddr_incr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(2),
Q => \^axaddr_incr_reg[3]_0\(2),
R => '0'
);
\axaddr_incr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(3),
Q => \^axaddr_incr_reg[3]_0\(3),
R => '0'
);
\axaddr_incr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1_n_7\,
Q => \^axaddr_incr_reg\(0),
R => '0'
);
\axaddr_incr_reg[4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => CO(0),
CO(3) => \axaddr_incr_reg[4]_i_1_n_0\,
CO(2) => \axaddr_incr_reg[4]_i_1_n_1\,
CO(1) => \axaddr_incr_reg[4]_i_1_n_2\,
CO(0) => \axaddr_incr_reg[4]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[4]_i_1_n_4\,
O(2) => \axaddr_incr_reg[4]_i_1_n_5\,
O(1) => \axaddr_incr_reg[4]_i_1_n_6\,
O(0) => \axaddr_incr_reg[4]_i_1_n_7\,
S(3) => \axaddr_incr[4]_i_2_n_0\,
S(2) => \axaddr_incr[4]_i_3_n_0\,
S(1) => \axaddr_incr[4]_i_4_n_0\,
S(0) => \axaddr_incr[4]_i_5_n_0\
);
\axaddr_incr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1_n_6\,
Q => \^axaddr_incr_reg\(1),
R => '0'
);
\axaddr_incr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1_n_5\,
Q => \^axaddr_incr_reg\(2),
R => '0'
);
\axaddr_incr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1_n_4\,
Q => \^axaddr_incr_reg\(3),
R => '0'
);
\axaddr_incr_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1_n_7\,
Q => \^axaddr_incr_reg\(4),
R => '0'
);
\axaddr_incr_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[4]_i_1_n_0\,
CO(3) => \NLW_axaddr_incr_reg[8]_i_1_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[8]_i_1_n_1\,
CO(1) => \axaddr_incr_reg[8]_i_1_n_2\,
CO(0) => \axaddr_incr_reg[8]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[8]_i_1_n_4\,
O(2) => \axaddr_incr_reg[8]_i_1_n_5\,
O(1) => \axaddr_incr_reg[8]_i_1_n_6\,
O(0) => \axaddr_incr_reg[8]_i_1_n_7\,
S(3) => \axaddr_incr[8]_i_2_n_0\,
S(2) => \axaddr_incr[8]_i_3_n_0\,
S(1) => \axaddr_incr[8]_i_4_n_0\,
S(0) => \axaddr_incr[8]_i_5_n_0\
);
\axaddr_incr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1_n_6\,
Q => \^axaddr_incr_reg\(5),
R => '0'
);
\axlen_cnt[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F8F8F88F88888888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[51]\(7),
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \^q\(0),
I4 => \^q\(1),
I5 => \state_reg[0]\,
O => p_1_in(2)
);
\axlen_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA90000FFFFFFFF"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => \state_reg[0]\,
I5 => \m_payload_i_reg[47]\,
O => \axlen_cnt[3]_i_1_n_0\
);
\axlen_cnt[4]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \axlen_cnt_reg_n_0_[2]\,
O => \axlen_cnt_reg[4]_0\
);
\axlen_cnt[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFA900A900A900"
)
port map (
I0 => \axlen_cnt_reg_n_0_[6]\,
I1 => \^axlen_cnt_reg[7]_0\,
I2 => \^q\(3),
I3 => \state_reg[0]\,
I4 => E(0),
I5 => \m_payload_i_reg[51]\(8),
O => p_1_in(6)
);
\axlen_cnt[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFA900A900A900"
)
port map (
I0 => \axlen_cnt_reg_n_0_[7]\,
I1 => \^axlen_cnt_reg[7]_0\,
I2 => \axlen_cnt[7]_i_4_n_0\,
I3 => \state_reg[0]\,
I4 => E(0),
I5 => \m_payload_i_reg[51]\(9),
O => p_1_in(7)
);
\axlen_cnt[7]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \^q\(2),
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \^q\(0),
I3 => \^q\(1),
I4 => \axlen_cnt_reg_n_0_[3]\,
O => \^axlen_cnt_reg[7]_0\
);
\axlen_cnt[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \axlen_cnt_reg_n_0_[6]\,
I1 => \^q\(3),
O => \axlen_cnt[7]_i_4_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(0),
Q => \^q\(0),
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(1),
Q => \^q\(1),
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => p_1_in(2),
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_1_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\axlen_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(2),
Q => \^q\(2),
R => '0'
);
\axlen_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(3),
Q => \^q\(3),
R => '0'
);
\axlen_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => p_1_in(6),
Q => \axlen_cnt_reg_n_0_[6]\,
R => '0'
);
\axlen_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => p_1_in(7),
Q => \axlen_cnt_reg_n_0_[7]\,
R => '0'
);
\m_axi_awaddr[1]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EF40"
)
port map (
I0 => \^axaddr_incr_reg[11]_0\,
I1 => \^axaddr_incr_reg[3]_0\(1),
I2 => \m_payload_i_reg[51]\(6),
I3 => \m_payload_i_reg[51]\(1),
O => \m_axi_awaddr[1]\
);
next_pending_r_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[7]\,
I2 => \^q\(2),
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => \^q\(1),
I5 => \axlen_cnt[7]_i_4_n_0\,
O => next_pending_r_reg_1
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => incr_next_pending,
Q => next_pending_r_reg_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^axaddr_incr_reg[11]_0\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2 is
port (
next_pending_r_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]_0\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\axaddr_incr_reg[11]_1\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
next_pending_r_reg_1 : out STD_LOGIC;
\m_axi_araddr[5]\ : out STD_LOGIC;
\m_axi_araddr[2]\ : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_reg_0 : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_reg_1 : in STD_LOGIC;
\state_reg[0]\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[51]\ : in STD_LOGIC_VECTOR ( 12 downto 0 );
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 1 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2 : entity is "axi_protocol_converter_v2_1_13_b2s_incr_cmd";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2 is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \axaddr_incr[4]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_5__0_n_0\ : STD_LOGIC;
signal axaddr_incr_reg : STD_LOGIC_VECTOR ( 5 to 5 );
signal \^axaddr_incr_reg[11]_0\ : STD_LOGIC_VECTOR ( 6 downto 0 );
signal \^axaddr_incr_reg[11]_1\ : STD_LOGIC;
signal \^axaddr_incr_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr_reg[4]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_7\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1__1_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1__1_n_0\ : STD_LOGIC;
signal \axlen_cnt[4]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[4]_i_2__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[5]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[5]_i_2_n_0\ : STD_LOGIC;
signal \axlen_cnt[6]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_2__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_3__0_n_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[4]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[5]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[6]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[7]\ : STD_LOGIC;
signal \next_pending_r_i_4__0_n_0\ : STD_LOGIC;
signal \NLW_axaddr_incr_reg[8]_i_1__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axlen_cnt[4]_i_2__0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \axlen_cnt[5]_i_2\ : label is "soft_lutpair4";
begin
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_incr_reg[11]_0\(6 downto 0) <= \^axaddr_incr_reg[11]_0\(6 downto 0);
\axaddr_incr_reg[11]_1\ <= \^axaddr_incr_reg[11]_1\;
\axaddr_incr_reg[3]_0\(3 downto 0) <= \^axaddr_incr_reg[3]_0\(3 downto 0);
\axaddr_incr[0]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA6AAAAAAAAAAAAA"
)
port map (
I0 => \m_payload_i_reg[51]\(3),
I1 => \m_payload_i_reg[51]\(6),
I2 => \m_payload_i_reg[51]\(5),
I3 => \state_reg[1]\(1),
I4 => \state_reg[1]\(0),
I5 => m_axi_arready,
O => S(3)
);
\axaddr_incr[0]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A262A2A2A2A2A2A"
)
port map (
I0 => \m_payload_i_reg[51]\(2),
I1 => \m_payload_i_reg[51]\(6),
I2 => \m_payload_i_reg[51]\(5),
I3 => \state_reg[1]\(1),
I4 => \state_reg[1]\(0),
I5 => m_axi_arready,
O => S(2)
);
\axaddr_incr[0]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A060A0A0A0A0A0A"
)
port map (
I0 => \m_payload_i_reg[51]\(1),
I1 => \m_payload_i_reg[51]\(5),
I2 => \m_payload_i_reg[51]\(6),
I3 => \state_reg[1]\(1),
I4 => \state_reg[1]\(0),
I5 => m_axi_arready,
O => S(1)
);
\axaddr_incr[0]_i_18\: unisim.vcomponents.LUT6
generic map(
INIT => X"0201020202020202"
)
port map (
I0 => \m_payload_i_reg[51]\(0),
I1 => \m_payload_i_reg[51]\(6),
I2 => \m_payload_i_reg[51]\(5),
I3 => \state_reg[1]\(1),
I4 => \state_reg[1]\(0),
I5 => m_axi_arready,
O => S(0)
);
\axaddr_incr[4]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(3),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(2),
O => \axaddr_incr[4]_i_2__0_n_0\
);
\axaddr_incr[4]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(2),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(1),
O => \axaddr_incr[4]_i_3__0_n_0\
);
\axaddr_incr[4]_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(1),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => axaddr_incr_reg(5),
O => \axaddr_incr[4]_i_4__0_n_0\
);
\axaddr_incr[4]_i_5__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(0),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(0),
O => \axaddr_incr[4]_i_5__0_n_0\
);
\axaddr_incr[8]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(3),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(6),
O => \axaddr_incr[8]_i_2__0_n_0\
);
\axaddr_incr[8]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(2),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(5),
O => \axaddr_incr[8]_i_3__0_n_0\
);
\axaddr_incr[8]_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(1),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(4),
O => \axaddr_incr[8]_i_4__0_n_0\
);
\axaddr_incr[8]_i_5__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(0),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(3),
O => \axaddr_incr[8]_i_5__0_n_0\
);
\axaddr_incr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(0),
Q => \^axaddr_incr_reg[3]_0\(0),
R => '0'
);
\axaddr_incr_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1__0_n_5\,
Q => \^axaddr_incr_reg[11]_0\(5),
R => '0'
);
\axaddr_incr_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1__0_n_4\,
Q => \^axaddr_incr_reg[11]_0\(6),
R => '0'
);
\axaddr_incr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(1),
Q => \^axaddr_incr_reg[3]_0\(1),
R => '0'
);
\axaddr_incr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(2),
Q => \^axaddr_incr_reg[3]_0\(2),
R => '0'
);
\axaddr_incr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(3),
Q => \^axaddr_incr_reg[3]_0\(3),
R => '0'
);
\axaddr_incr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1__0_n_7\,
Q => \^axaddr_incr_reg[11]_0\(0),
R => '0'
);
\axaddr_incr_reg[4]_i_1__0\: unisim.vcomponents.CARRY4
port map (
CI => CO(0),
CO(3) => \axaddr_incr_reg[4]_i_1__0_n_0\,
CO(2) => \axaddr_incr_reg[4]_i_1__0_n_1\,
CO(1) => \axaddr_incr_reg[4]_i_1__0_n_2\,
CO(0) => \axaddr_incr_reg[4]_i_1__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[4]_i_1__0_n_4\,
O(2) => \axaddr_incr_reg[4]_i_1__0_n_5\,
O(1) => \axaddr_incr_reg[4]_i_1__0_n_6\,
O(0) => \axaddr_incr_reg[4]_i_1__0_n_7\,
S(3) => \axaddr_incr[4]_i_2__0_n_0\,
S(2) => \axaddr_incr[4]_i_3__0_n_0\,
S(1) => \axaddr_incr[4]_i_4__0_n_0\,
S(0) => \axaddr_incr[4]_i_5__0_n_0\
);
\axaddr_incr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1__0_n_6\,
Q => axaddr_incr_reg(5),
R => '0'
);
\axaddr_incr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1__0_n_5\,
Q => \^axaddr_incr_reg[11]_0\(1),
R => '0'
);
\axaddr_incr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1__0_n_4\,
Q => \^axaddr_incr_reg[11]_0\(2),
R => '0'
);
\axaddr_incr_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1__0_n_7\,
Q => \^axaddr_incr_reg[11]_0\(3),
R => '0'
);
\axaddr_incr_reg[8]_i_1__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[4]_i_1__0_n_0\,
CO(3) => \NLW_axaddr_incr_reg[8]_i_1__0_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[8]_i_1__0_n_1\,
CO(1) => \axaddr_incr_reg[8]_i_1__0_n_2\,
CO(0) => \axaddr_incr_reg[8]_i_1__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[8]_i_1__0_n_4\,
O(2) => \axaddr_incr_reg[8]_i_1__0_n_5\,
O(1) => \axaddr_incr_reg[8]_i_1__0_n_6\,
O(0) => \axaddr_incr_reg[8]_i_1__0_n_7\,
S(3) => \axaddr_incr[8]_i_2__0_n_0\,
S(2) => \axaddr_incr[8]_i_3__0_n_0\,
S(1) => \axaddr_incr[8]_i_4__0_n_0\,
S(0) => \axaddr_incr[8]_i_5__0_n_0\
);
\axaddr_incr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1__0_n_6\,
Q => \^axaddr_incr_reg[11]_0\(4),
R => '0'
);
\axlen_cnt[2]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F8F8F88F88888888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[51]\(8),
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \^q\(0),
I4 => \^q\(1),
I5 => \state_reg[0]\,
O => \axlen_cnt[2]_i_1__1_n_0\
);
\axlen_cnt[3]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA90000FFFFFFFF"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => \state_reg[0]\,
I5 => \m_payload_i_reg[47]\,
O => \axlen_cnt[3]_i_1__1_n_0\
);
\axlen_cnt[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF909090"
)
port map (
I0 => \axlen_cnt_reg_n_0_[4]\,
I1 => \axlen_cnt[4]_i_2__0_n_0\,
I2 => \state_reg[0]\,
I3 => E(0),
I4 => \m_payload_i_reg[51]\(9),
O => \axlen_cnt[4]_i_1__0_n_0\
);
\axlen_cnt[4]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \axlen_cnt_reg_n_0_[2]\,
O => \axlen_cnt[4]_i_2__0_n_0\
);
\axlen_cnt[5]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF909090"
)
port map (
I0 => \axlen_cnt_reg_n_0_[5]\,
I1 => \axlen_cnt[5]_i_2_n_0\,
I2 => \state_reg[0]\,
I3 => E(0),
I4 => \m_payload_i_reg[51]\(10),
O => \axlen_cnt[5]_i_1__0_n_0\
);
\axlen_cnt[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \axlen_cnt_reg_n_0_[4]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \^q\(0),
I3 => \^q\(1),
I4 => \axlen_cnt_reg_n_0_[3]\,
O => \axlen_cnt[5]_i_2_n_0\
);
\axlen_cnt[6]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF909090"
)
port map (
I0 => \axlen_cnt_reg_n_0_[6]\,
I1 => \axlen_cnt[7]_i_3__0_n_0\,
I2 => \state_reg[0]\,
I3 => E(0),
I4 => \m_payload_i_reg[51]\(11),
O => \axlen_cnt[6]_i_1__0_n_0\
);
\axlen_cnt[7]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"F8F8F88F88888888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[51]\(12),
I2 => \axlen_cnt_reg_n_0_[7]\,
I3 => \axlen_cnt[7]_i_3__0_n_0\,
I4 => \axlen_cnt_reg_n_0_[6]\,
I5 => \state_reg[0]\,
O => \axlen_cnt[7]_i_2__0_n_0\
);
\axlen_cnt[7]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \axlen_cnt_reg_n_0_[5]\,
I1 => \axlen_cnt_reg_n_0_[3]\,
I2 => \^q\(1),
I3 => \^q\(0),
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \axlen_cnt_reg_n_0_[4]\,
O => \axlen_cnt[7]_i_3__0_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(0),
Q => \^q\(0),
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(1),
Q => \^q\(1),
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[2]_i_1__1_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_1__1_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\axlen_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[4]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[4]\,
R => '0'
);
\axlen_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[5]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[5]\,
R => '0'
);
\axlen_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[6]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[6]\,
R => '0'
);
\axlen_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[7]_i_2__0_n_0\,
Q => \axlen_cnt_reg_n_0_[7]\,
R => '0'
);
\m_axi_araddr[2]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EF40"
)
port map (
I0 => \^axaddr_incr_reg[11]_1\,
I1 => \^axaddr_incr_reg[3]_0\(2),
I2 => \m_payload_i_reg[51]\(7),
I3 => \m_payload_i_reg[51]\(2),
O => \m_axi_araddr[2]\
);
\m_axi_araddr[5]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EF40"
)
port map (
I0 => \^axaddr_incr_reg[11]_1\,
I1 => axaddr_incr_reg(5),
I2 => \m_payload_i_reg[51]\(7),
I3 => \m_payload_i_reg[51]\(4),
O => \m_axi_araddr[5]\
);
\next_pending_r_i_3__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \axlen_cnt_reg_n_0_[4]\,
I1 => \axlen_cnt_reg_n_0_[5]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
I3 => \next_pending_r_i_4__0_n_0\,
O => next_pending_r_reg_1
);
\next_pending_r_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \^q\(1),
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[6]\,
I3 => \axlen_cnt_reg_n_0_[7]\,
O => \next_pending_r_i_4__0_n_0\
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => incr_next_pending,
Q => next_pending_r_reg_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^axaddr_incr_reg[11]_1\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm is
port (
\axlen_cnt_reg[1]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
wrap_second_len : out STD_LOGIC_VECTOR ( 0 to 0 );
r_push_r_reg : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC;
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
\axlen_cnt_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axburst_eq0_reg : out STD_LOGIC;
sel_first_i : out STD_LOGIC;
incr_next_pending : out STD_LOGIC;
s_axburst_eq1_reg : out STD_LOGIC;
\axaddr_wrap_reg[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
\m_payload_i_reg[0]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
sel_first_reg : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
\axlen_cnt_reg[4]\ : in STD_LOGIC;
\m_payload_i_reg[44]\ : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
s_axburst_eq1_reg_0 : in STD_LOGIC;
\cnt_read_reg[2]_rep__0\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\axlen_cnt_reg[1]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\wrap_second_len_r_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
axaddr_offset : in STD_LOGIC_VECTOR ( 2 downto 0 );
wrap_next_pending : in STD_LOGIC;
\m_payload_i_reg[51]\ : in STD_LOGIC;
next_pending_r_reg : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
sel_first_reg_3 : in STD_LOGIC;
aclk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axlen_cnt_reg[1]\ : STD_LOGIC;
signal \^incr_next_pending\ : STD_LOGIC;
signal \^m_payload_i_reg[0]\ : STD_LOGIC;
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal next_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^r_push_r_reg\ : STD_LOGIC;
signal \^sel_first_i\ : STD_LOGIC;
signal \^wrap_second_len\ : STD_LOGIC_VECTOR ( 0 to 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_incr[0]_i_1__0\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_1__0\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__0\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of r_push_r_i_1 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \s_axburst_eq0_i_1__0\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \s_axburst_eq1_i_1__0\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \state[1]_i_1\ : label is "soft_lutpair0";
attribute KEEP : string;
attribute KEEP of \state_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \state_reg[0]\ : label is "state_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \state_reg[0]_rep\ : label is 1;
attribute KEEP of \state_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[0]_rep\ : label is "state_reg[0]";
attribute KEEP of \state_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]\ : label is "state_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \state_reg[1]_rep\ : label is 1;
attribute KEEP of \state_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]_rep\ : label is "state_reg[1]";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[11]_i_1__0\ : label is "soft_lutpair2";
begin
E(0) <= \^e\(0);
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_offset_r_reg[3]\(0) <= \^axaddr_offset_r_reg[3]\(0);
\axlen_cnt_reg[1]\ <= \^axlen_cnt_reg[1]\;
incr_next_pending <= \^incr_next_pending\;
\m_payload_i_reg[0]\ <= \^m_payload_i_reg[0]\;
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
r_push_r_reg <= \^r_push_r_reg\;
sel_first_i <= \^sel_first_i\;
wrap_second_len(0) <= \^wrap_second_len\(0);
\axaddr_incr[0]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAEA"
)
port map (
I0 => sel_first_reg_2,
I1 => m_axi_arready,
I2 => \^m_payload_i_reg[0]_0\,
I3 => \^m_payload_i_reg[0]\,
O => \axaddr_incr_reg[11]\
);
\axaddr_offset_r[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAACAAAAAAA0AA"
)
port map (
I0 => \axaddr_offset_r_reg[3]_0\(0),
I1 => \m_payload_i_reg[47]\(3),
I2 => \^m_payload_i_reg[0]_0\,
I3 => si_rs_arvalid,
I4 => \^m_payload_i_reg[0]\,
I5 => \m_payload_i_reg[6]\,
O => \^axaddr_offset_r_reg[3]\(0)
);
\axlen_cnt[0]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0400FFFF04000400"
)
port map (
I0 => \^q\(1),
I1 => si_rs_arvalid,
I2 => \^q\(0),
I3 => \m_payload_i_reg[47]\(1),
I4 => \axlen_cnt_reg[1]_1\(0),
I5 => \^axlen_cnt_reg[1]\,
O => \axlen_cnt_reg[1]_0\(0)
);
\axlen_cnt[1]_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => \^e\(0),
I1 => \m_payload_i_reg[47]\(2),
I2 => \axlen_cnt_reg[1]_1\(1),
I3 => \axlen_cnt_reg[1]_1\(0),
I4 => \^axlen_cnt_reg[1]\,
O => \axlen_cnt_reg[1]_0\(1)
);
\axlen_cnt[7]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00CA"
)
port map (
I0 => si_rs_arvalid,
I1 => m_axi_arready,
I2 => \^m_payload_i_reg[0]_0\,
I3 => \^m_payload_i_reg[0]\,
O => \axaddr_wrap_reg[11]\(0)
);
\axlen_cnt[7]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00FB"
)
port map (
I0 => \^q\(0),
I1 => si_rs_arvalid,
I2 => \^q\(1),
I3 => \axlen_cnt_reg[4]\,
O => \^axlen_cnt_reg[1]\
);
m_axi_arvalid_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => \^m_payload_i_reg[0]\,
O => m_axi_arvalid
);
\m_payload_i[31]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"D5"
)
port map (
I0 => si_rs_arvalid,
I1 => \^m_payload_i_reg[0]\,
I2 => \^m_payload_i_reg[0]_0\,
O => \m_payload_i_reg[0]_1\(0)
);
\next_pending_r_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBB8B88"
)
port map (
I0 => \m_payload_i_reg[51]\,
I1 => \^e\(0),
I2 => \axlen_cnt_reg[4]\,
I3 => \^r_push_r_reg\,
I4 => next_pending_r_reg,
O => \^incr_next_pending\
);
r_push_r_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => \^m_payload_i_reg[0]_0\,
I2 => m_axi_arready,
O => \^r_push_r_reg\
);
\s_axburst_eq0_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => wrap_next_pending,
I1 => \m_payload_i_reg[47]\(0),
I2 => \^sel_first_i\,
I3 => \^incr_next_pending\,
O => s_axburst_eq0_reg
);
\s_axburst_eq1_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"ABA8"
)
port map (
I0 => wrap_next_pending,
I1 => \m_payload_i_reg[47]\(0),
I2 => \^sel_first_i\,
I3 => \^incr_next_pending\,
O => s_axburst_eq1_reg
);
\sel_first_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FCFFFFFFCCCECCCE"
)
port map (
I0 => si_rs_arvalid,
I1 => areset_d1,
I2 => \^m_payload_i_reg[0]\,
I3 => \^m_payload_i_reg[0]_0\,
I4 => m_axi_arready,
I5 => sel_first_reg_1,
O => \^sel_first_i\
);
\sel_first_i_1__3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFC4C4CFCC"
)
port map (
I0 => m_axi_arready,
I1 => sel_first_reg_2,
I2 => \^q\(1),
I3 => si_rs_arvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg
);
\sel_first_i_1__4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFC4C4CFCC"
)
port map (
I0 => m_axi_arready,
I1 => sel_first_reg_3,
I2 => \^q\(1),
I3 => si_rs_arvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg_0
);
\state[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"003030303E3E3E3E"
)
port map (
I0 => si_rs_arvalid,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => m_axi_arready,
I4 => s_axburst_eq1_reg_0,
I5 => \cnt_read_reg[2]_rep__0\,
O => next_state(0)
);
\state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00AAB000"
)
port map (
I0 => \cnt_read_reg[2]_rep__0\,
I1 => s_axburst_eq1_reg_0,
I2 => m_axi_arready,
I3 => \^m_payload_i_reg[0]_0\,
I4 => \^m_payload_i_reg[0]\,
O => next_state(1)
);
\state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^q\(0),
R => areset_d1
);
\state_reg[0]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^m_payload_i_reg[0]_0\,
R => areset_d1
);
\state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(1),
Q => \^q\(1),
R => areset_d1
);
\state_reg[1]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(1),
Q => \^m_payload_i_reg[0]\,
R => areset_d1
);
\wrap_boundary_axaddr_r[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => si_rs_arvalid,
I2 => \^m_payload_i_reg[0]_0\,
O => \^e\(0)
);
\wrap_cnt_r[1]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^wrap_second_len\(0),
I1 => \m_payload_i_reg[44]\,
O => D(0)
);
\wrap_second_len_r[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF0000FCAAAAAAAA"
)
port map (
I0 => \wrap_second_len_r_reg[1]\(0),
I1 => axaddr_offset(2),
I2 => \^axaddr_offset_r_reg[3]\(0),
I3 => axaddr_offset(0),
I4 => axaddr_offset(1),
I5 => \^e\(0),
O => \^wrap_second_len\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo is
port (
\cnt_read_reg[0]_rep__0_0\ : out STD_LOGIC;
\cnt_read_reg[1]_rep__1_0\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\cnt_read_reg[0]_0\ : out STD_LOGIC;
sel : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
bvalid_i_reg : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
b_push : in STD_LOGIC;
shandshake_r : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
areset_d1 : in STD_LOGIC;
\bresp_cnt_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
mhandshake_r : in STD_LOGIC;
bvalid_i_reg_0 : in STD_LOGIC;
si_rs_bready : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 19 downto 0 );
aclk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo is
signal bvalid_i_i_2_n_0 : STD_LOGIC;
signal cnt_read : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \cnt_read[0]_i_1__2_n_0\ : STD_LOGIC;
signal \cnt_read[1]_i_1_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[0]_0\ : STD_LOGIC;
signal \^cnt_read_reg[0]_rep__0_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[1]_rep__1_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_3_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_4_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_5_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_6_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][1]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][2]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][3]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][4]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][5]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][6]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][7]_srl4_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \bresp_cnt[7]_i_1\ : label is "soft_lutpair115";
attribute SOFT_HLUTNM of bvalid_i_i_1 : label is "soft_lutpair115";
attribute SOFT_HLUTNM of \cnt_read[0]_i_1\ : label is "soft_lutpair117";
attribute SOFT_HLUTNM of \cnt_read[0]_i_1__2\ : label is "soft_lutpair116";
attribute SOFT_HLUTNM of \cnt_read[1]_i_1\ : label is "soft_lutpair116";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__1\ : label is "cnt_read_reg[1]";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][0]_srl4 ";
attribute SOFT_HLUTNM of \memory_reg[3][0]_srl4_i_1__0\ : label is "soft_lutpair117";
attribute srl_bus_name of \memory_reg[3][10]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][10]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][10]_srl4 ";
attribute srl_bus_name of \memory_reg[3][11]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][11]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][11]_srl4 ";
attribute srl_bus_name of \memory_reg[3][12]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][12]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][12]_srl4 ";
attribute srl_bus_name of \memory_reg[3][13]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][13]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][13]_srl4 ";
attribute srl_bus_name of \memory_reg[3][14]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][14]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][14]_srl4 ";
attribute srl_bus_name of \memory_reg[3][15]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][15]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][15]_srl4 ";
attribute srl_bus_name of \memory_reg[3][16]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][16]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][16]_srl4 ";
attribute srl_bus_name of \memory_reg[3][17]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][17]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][17]_srl4 ";
attribute srl_bus_name of \memory_reg[3][18]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][18]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][18]_srl4 ";
attribute srl_bus_name of \memory_reg[3][19]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][19]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][19]_srl4 ";
attribute srl_bus_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][1]_srl4 ";
attribute srl_bus_name of \memory_reg[3][2]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][2]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][2]_srl4 ";
attribute srl_bus_name of \memory_reg[3][3]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][3]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][3]_srl4 ";
attribute srl_bus_name of \memory_reg[3][4]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][4]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][4]_srl4 ";
attribute srl_bus_name of \memory_reg[3][5]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][5]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][5]_srl4 ";
attribute srl_bus_name of \memory_reg[3][6]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][6]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][6]_srl4 ";
attribute srl_bus_name of \memory_reg[3][7]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][7]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][7]_srl4 ";
attribute srl_bus_name of \memory_reg[3][8]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][8]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][8]_srl4 ";
attribute srl_bus_name of \memory_reg[3][9]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][9]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][9]_srl4 ";
begin
\cnt_read_reg[0]_0\ <= \^cnt_read_reg[0]_0\;
\cnt_read_reg[0]_rep__0_0\ <= \^cnt_read_reg[0]_rep__0_0\;
\cnt_read_reg[1]_rep__1_0\ <= \^cnt_read_reg[1]_rep__1_0\;
\bresp_cnt[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => areset_d1,
I1 => \^cnt_read_reg[0]_0\,
O => SR(0)
);
bvalid_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"002A"
)
port map (
I0 => bvalid_i_i_2_n_0,
I1 => bvalid_i_reg_0,
I2 => si_rs_bready,
I3 => areset_d1,
O => bvalid_i_reg
);
bvalid_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00070707"
)
port map (
I0 => \^cnt_read_reg[1]_rep__1_0\,
I1 => \^cnt_read_reg[0]_rep__0_0\,
I2 => shandshake_r,
I3 => Q(1),
I4 => Q(0),
I5 => bvalid_i_reg_0,
O => bvalid_i_i_2_n_0
);
\cnt_read[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \^cnt_read_reg[0]_0\,
I1 => shandshake_r,
I2 => Q(0),
O => D(0)
);
\cnt_read[0]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^cnt_read_reg[0]_rep__0_0\,
I1 => b_push,
I2 => shandshake_r,
O => \cnt_read[0]_i_1__2_n_0\
);
\cnt_read[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"E718"
)
port map (
I0 => \^cnt_read_reg[0]_rep__0_0\,
I1 => b_push,
I2 => shandshake_r,
I3 => \^cnt_read_reg[1]_rep__1_0\,
O => \cnt_read[1]_i_1_n_0\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__2_n_0\,
Q => cnt_read(0),
S => areset_d1
);
\cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__2_n_0\,
Q => \cnt_read_reg[0]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__2_n_0\,
Q => \^cnt_read_reg[0]_rep__0_0\,
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => cnt_read(1),
S => areset_d1
);
\cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => \cnt_read_reg[1]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => \cnt_read_reg[1]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => \^cnt_read_reg[1]_rep__1_0\,
S => areset_d1
);
\memory_reg[3][0]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(0),
Q => \memory_reg[3][0]_srl4_n_0\
);
\memory_reg[3][0]_srl4_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cnt_read_reg[0]_0\,
O => sel
);
\memory_reg[3][0]_srl4_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFEFFFFFFFFFFFE"
)
port map (
I0 => \memory_reg[3][0]_srl4_i_3_n_0\,
I1 => \memory_reg[3][0]_srl4_i_4_n_0\,
I2 => \memory_reg[3][0]_srl4_i_5_n_0\,
I3 => \memory_reg[3][0]_srl4_i_6_n_0\,
I4 => \bresp_cnt_reg[7]\(3),
I5 => \memory_reg[3][3]_srl4_n_0\,
O => \^cnt_read_reg[0]_0\
);
\memory_reg[3][0]_srl4_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"22F2FFFFFFFF22F2"
)
port map (
I0 => \memory_reg[3][0]_srl4_n_0\,
I1 => \bresp_cnt_reg[7]\(0),
I2 => \memory_reg[3][2]_srl4_n_0\,
I3 => \bresp_cnt_reg[7]\(2),
I4 => \memory_reg[3][1]_srl4_n_0\,
I5 => \bresp_cnt_reg[7]\(1),
O => \memory_reg[3][0]_srl4_i_3_n_0\
);
\memory_reg[3][0]_srl4_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"F222FFFFFFFFF222"
)
port map (
I0 => \bresp_cnt_reg[7]\(5),
I1 => \memory_reg[3][5]_srl4_n_0\,
I2 => \^cnt_read_reg[1]_rep__1_0\,
I3 => \^cnt_read_reg[0]_rep__0_0\,
I4 => \bresp_cnt_reg[7]\(7),
I5 => \memory_reg[3][7]_srl4_n_0\,
O => \memory_reg[3][0]_srl4_i_4_n_0\
);
\memory_reg[3][0]_srl4_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"2FF22FF2FFFF2FF2"
)
port map (
I0 => \bresp_cnt_reg[7]\(2),
I1 => \memory_reg[3][2]_srl4_n_0\,
I2 => \memory_reg[3][4]_srl4_n_0\,
I3 => \bresp_cnt_reg[7]\(4),
I4 => \bresp_cnt_reg[7]\(0),
I5 => \memory_reg[3][0]_srl4_n_0\,
O => \memory_reg[3][0]_srl4_i_5_n_0\
);
\memory_reg[3][0]_srl4_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"6F6FFF6F"
)
port map (
I0 => \memory_reg[3][6]_srl4_n_0\,
I1 => \bresp_cnt_reg[7]\(6),
I2 => mhandshake_r,
I3 => \memory_reg[3][5]_srl4_n_0\,
I4 => \bresp_cnt_reg[7]\(5),
O => \memory_reg[3][0]_srl4_i_6_n_0\
);
\memory_reg[3][10]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(10),
Q => \out\(2)
);
\memory_reg[3][11]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(11),
Q => \out\(3)
);
\memory_reg[3][12]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(12),
Q => \out\(4)
);
\memory_reg[3][13]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(13),
Q => \out\(5)
);
\memory_reg[3][14]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(14),
Q => \out\(6)
);
\memory_reg[3][15]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(15),
Q => \out\(7)
);
\memory_reg[3][16]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(16),
Q => \out\(8)
);
\memory_reg[3][17]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(17),
Q => \out\(9)
);
\memory_reg[3][18]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(18),
Q => \out\(10)
);
\memory_reg[3][19]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(19),
Q => \out\(11)
);
\memory_reg[3][1]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(1),
Q => \memory_reg[3][1]_srl4_n_0\
);
\memory_reg[3][2]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(2),
Q => \memory_reg[3][2]_srl4_n_0\
);
\memory_reg[3][3]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(3),
Q => \memory_reg[3][3]_srl4_n_0\
);
\memory_reg[3][4]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(4),
Q => \memory_reg[3][4]_srl4_n_0\
);
\memory_reg[3][5]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(5),
Q => \memory_reg[3][5]_srl4_n_0\
);
\memory_reg[3][6]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(6),
Q => \memory_reg[3][6]_srl4_n_0\
);
\memory_reg[3][7]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(7),
Q => \memory_reg[3][7]_srl4_n_0\
);
\memory_reg[3][8]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(8),
Q => \out\(0)
);
\memory_reg[3][9]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(9),
Q => \out\(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\ is
port (
mhandshake : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bready : out STD_LOGIC;
\skid_buffer_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
mhandshake_r : in STD_LOGIC;
shandshake_r : in STD_LOGIC;
\bresp_cnt_reg[3]\ : in STD_LOGIC;
sel : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
aclk : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\ : entity is "axi_protocol_converter_v2_1_13_b2s_simple_fifo";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\ is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \cnt_read[1]_i_1__0_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[1]_i_1__0\ : label is "soft_lutpair118";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute SOFT_HLUTNM of m_axi_bready_INST_0 : label is "soft_lutpair118";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][0]_srl4 ";
attribute srl_bus_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][1]_srl4 ";
begin
Q(1 downto 0) <= \^q\(1 downto 0);
\cnt_read[1]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A69A"
)
port map (
I0 => \^q\(1),
I1 => shandshake_r,
I2 => \^q\(0),
I3 => \bresp_cnt_reg[3]\,
O => \cnt_read[1]_i_1__0_n_0\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => D(0),
Q => \^q\(0),
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__0_n_0\,
Q => \^q\(1),
S => areset_d1
);
m_axi_bready_INST_0: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => mhandshake_r,
O => m_axi_bready
);
\memory_reg[3][0]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \^q\(0),
A1 => \^q\(1),
A2 => '0',
A3 => '0',
CE => sel,
CLK => aclk,
D => \in\(0),
Q => \skid_buffer_reg[1]\(0)
);
\memory_reg[3][1]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \^q\(0),
A1 => \^q\(1),
A2 => '0',
A3 => '0',
CE => sel,
CLK => aclk,
D => \in\(1),
Q => \skid_buffer_reg[1]\(1)
);
mhandshake_r_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => m_axi_bvalid,
I1 => mhandshake_r,
I2 => \^q\(0),
I3 => \^q\(1),
O => mhandshake
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\ is
port (
\cnt_read_reg[3]_rep__2_0\ : out STD_LOGIC;
wr_en0 : out STD_LOGIC;
\cnt_read_reg[4]_rep__2_0\ : out STD_LOGIC;
\cnt_read_reg[4]_rep__2_1\ : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
\state_reg[1]_rep\ : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 33 downto 0 );
s_ready_i_reg : in STD_LOGIC;
s_ready_i_reg_0 : in STD_LOGIC;
si_rs_rready : in STD_LOGIC;
\cnt_read_reg[4]_rep__0_0\ : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
aclk : in STD_LOGIC;
areset_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\ : entity is "axi_protocol_converter_v2_1_13_b2s_simple_fifo";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\ is
signal cnt_read : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \cnt_read[0]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[1]_i_1__2_n_0\ : STD_LOGIC;
signal \cnt_read[2]_i_1_n_0\ : STD_LOGIC;
signal \cnt_read[3]_i_1_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_1_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_2_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_3_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__2_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__2_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__2_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep__1_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[3]_rep__2_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep__1_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[4]_rep__2_0\ : STD_LOGIC;
signal \^cnt_read_reg[4]_rep__2_1\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep_n_0\ : STD_LOGIC;
signal \^wr_en0\ : STD_LOGIC;
signal \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[0]_i_1__0\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \cnt_read[1]_i_1__2\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \cnt_read[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \cnt_read[4]_i_2\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \cnt_read[4]_i_3\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \cnt_read[4]_i_5\ : label is "soft_lutpair9";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__1\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__2\ : label is "cnt_read_reg[0]";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__1\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__2\ : label is "cnt_read_reg[1]";
attribute KEEP of \cnt_read_reg[2]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__0\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__1\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__2\ : label is "cnt_read_reg[2]";
attribute KEEP of \cnt_read_reg[3]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__0\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__1\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__2\ : label is "cnt_read_reg[3]";
attribute KEEP of \cnt_read_reg[4]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__0\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__1\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__2\ : label is "cnt_read_reg[4]";
attribute SOFT_HLUTNM of m_axi_rready_INST_0 : label is "soft_lutpair7";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][0]_srl32 ";
attribute srl_bus_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][10]_srl32 ";
attribute srl_bus_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][11]_srl32 ";
attribute srl_bus_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][12]_srl32 ";
attribute srl_bus_name of \memory_reg[31][13]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][13]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][13]_srl32 ";
attribute srl_bus_name of \memory_reg[31][14]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][14]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][14]_srl32 ";
attribute srl_bus_name of \memory_reg[31][15]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][15]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][15]_srl32 ";
attribute srl_bus_name of \memory_reg[31][16]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][16]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][16]_srl32 ";
attribute srl_bus_name of \memory_reg[31][17]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][17]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][17]_srl32 ";
attribute srl_bus_name of \memory_reg[31][18]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][18]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][18]_srl32 ";
attribute srl_bus_name of \memory_reg[31][19]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][19]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][19]_srl32 ";
attribute srl_bus_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][1]_srl32 ";
attribute srl_bus_name of \memory_reg[31][20]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][20]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][20]_srl32 ";
attribute srl_bus_name of \memory_reg[31][21]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][21]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][21]_srl32 ";
attribute srl_bus_name of \memory_reg[31][22]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][22]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][22]_srl32 ";
attribute srl_bus_name of \memory_reg[31][23]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][23]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][23]_srl32 ";
attribute srl_bus_name of \memory_reg[31][24]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][24]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][24]_srl32 ";
attribute srl_bus_name of \memory_reg[31][25]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][25]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][25]_srl32 ";
attribute srl_bus_name of \memory_reg[31][26]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][26]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][26]_srl32 ";
attribute srl_bus_name of \memory_reg[31][27]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][27]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][27]_srl32 ";
attribute srl_bus_name of \memory_reg[31][28]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][28]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][28]_srl32 ";
attribute srl_bus_name of \memory_reg[31][29]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][29]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][29]_srl32 ";
attribute srl_bus_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][2]_srl32 ";
attribute srl_bus_name of \memory_reg[31][30]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][30]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][30]_srl32 ";
attribute srl_bus_name of \memory_reg[31][31]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][31]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][31]_srl32 ";
attribute srl_bus_name of \memory_reg[31][32]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][32]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][32]_srl32 ";
attribute srl_bus_name of \memory_reg[31][33]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][33]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][33]_srl32 ";
attribute srl_bus_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][3]_srl32 ";
attribute srl_bus_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][4]_srl32 ";
attribute srl_bus_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][5]_srl32 ";
attribute srl_bus_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][6]_srl32 ";
attribute srl_bus_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][7]_srl32 ";
attribute srl_bus_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][8]_srl32 ";
attribute srl_bus_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][9]_srl32 ";
attribute SOFT_HLUTNM of \state[1]_i_4\ : label is "soft_lutpair7";
begin
\cnt_read_reg[3]_rep__2_0\ <= \^cnt_read_reg[3]_rep__2_0\;
\cnt_read_reg[4]_rep__2_0\ <= \^cnt_read_reg[4]_rep__2_0\;
\cnt_read_reg[4]_rep__2_1\ <= \^cnt_read_reg[4]_rep__2_1\;
wr_en0 <= \^wr_en0\;
\cnt_read[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => s_ready_i_reg,
I2 => \^wr_en0\,
O => \cnt_read[0]_i_1__0_n_0\
);
\cnt_read[1]_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"A96A"
)
port map (
I0 => \cnt_read_reg[1]_rep__2_n_0\,
I1 => \cnt_read_reg[0]_rep__2_n_0\,
I2 => \^wr_en0\,
I3 => s_ready_i_reg,
O => \cnt_read[1]_i_1__2_n_0\
);
\cnt_read[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"A6AAAA9A"
)
port map (
I0 => \cnt_read_reg[2]_rep__2_n_0\,
I1 => \cnt_read_reg[1]_rep__2_n_0\,
I2 => s_ready_i_reg,
I3 => \^wr_en0\,
I4 => \cnt_read_reg[0]_rep__2_n_0\,
O => \cnt_read[2]_i_1_n_0\
);
\cnt_read[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAA96AAAAAAA"
)
port map (
I0 => \^cnt_read_reg[3]_rep__2_0\,
I1 => \cnt_read_reg[2]_rep__2_n_0\,
I2 => \cnt_read_reg[1]_rep__2_n_0\,
I3 => \cnt_read_reg[0]_rep__2_n_0\,
I4 => \^wr_en0\,
I5 => s_ready_i_reg,
O => \cnt_read[3]_i_1_n_0\
);
\cnt_read[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA55AAA6A6AAA6AA"
)
port map (
I0 => \^cnt_read_reg[4]_rep__2_0\,
I1 => \cnt_read[4]_i_2_n_0\,
I2 => \cnt_read[4]_i_3_n_0\,
I3 => s_ready_i_reg_0,
I4 => \^cnt_read_reg[4]_rep__2_1\,
I5 => \^cnt_read_reg[3]_rep__2_0\,
O => \cnt_read[4]_i_1_n_0\
);
\cnt_read[4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cnt_read_reg[2]_rep__2_n_0\,
I1 => \cnt_read_reg[1]_rep__2_n_0\,
O => \cnt_read[4]_i_2_n_0\
);
\cnt_read[4]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFB"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => si_rs_rready,
I2 => \cnt_read_reg[4]_rep__0_0\,
I3 => \^wr_en0\,
O => \cnt_read[4]_i_3_n_0\
);
\cnt_read[4]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => \cnt_read_reg[1]_rep__2_n_0\,
I2 => \cnt_read_reg[2]_rep__2_n_0\,
O => \^cnt_read_reg[4]_rep__2_1\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => cnt_read(0),
S => areset_d1
);
\cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => \cnt_read_reg[0]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => \cnt_read_reg[0]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => \cnt_read_reg[0]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => \cnt_read_reg[0]_rep__2_n_0\,
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => cnt_read(1),
S => areset_d1
);
\cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep__2_n_0\,
S => areset_d1
);
\cnt_read_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => cnt_read(2),
S => areset_d1
);
\cnt_read_reg[2]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep__2_n_0\,
S => areset_d1
);
\cnt_read_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => cnt_read(3),
S => areset_d1
);
\cnt_read_reg[3]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \cnt_read_reg[3]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \cnt_read_reg[3]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \cnt_read_reg[3]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \^cnt_read_reg[3]_rep__2_0\,
S => areset_d1
);
\cnt_read_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => cnt_read(4),
S => areset_d1
);
\cnt_read_reg[4]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \cnt_read_reg[4]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \cnt_read_reg[4]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \cnt_read_reg[4]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \^cnt_read_reg[4]_rep__2_0\,
S => areset_d1
);
m_axi_rready_INST_0: unisim.vcomponents.LUT5
generic map(
INIT => X"F77F777F"
)
port map (
I0 => \^cnt_read_reg[3]_rep__2_0\,
I1 => \^cnt_read_reg[4]_rep__2_0\,
I2 => \cnt_read_reg[1]_rep__2_n_0\,
I3 => \cnt_read_reg[2]_rep__2_n_0\,
I4 => \cnt_read_reg[0]_rep__2_n_0\,
O => m_axi_rready
);
\memory_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(0),
Q => \out\(0),
Q31 => \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][0]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA2A2AAA2A2A2AAA"
)
port map (
I0 => m_axi_rvalid,
I1 => \^cnt_read_reg[3]_rep__2_0\,
I2 => \^cnt_read_reg[4]_rep__2_0\,
I3 => \cnt_read_reg[1]_rep__2_n_0\,
I4 => \cnt_read_reg[2]_rep__2_n_0\,
I5 => \cnt_read_reg[0]_rep__2_n_0\,
O => \^wr_en0\
);
\memory_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(10),
Q => \out\(10),
Q31 => \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(11),
Q => \out\(11),
Q31 => \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(12),
Q => \out\(12),
Q31 => \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][13]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(13),
Q => \out\(13),
Q31 => \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][14]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(14),
Q => \out\(14),
Q31 => \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][15]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(15),
Q => \out\(15),
Q31 => \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][16]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(16),
Q => \out\(16),
Q31 => \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][17]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(17),
Q => \out\(17),
Q31 => \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][18]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(18),
Q => \out\(18),
Q31 => \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][19]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(19),
Q => \out\(19),
Q31 => \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(1),
Q => \out\(1),
Q31 => \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][20]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(20),
Q => \out\(20),
Q31 => \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][21]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(21),
Q => \out\(21),
Q31 => \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][22]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(22),
Q => \out\(22),
Q31 => \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][23]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(23),
Q => \out\(23),
Q31 => \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][24]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(24),
Q => \out\(24),
Q31 => \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][25]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(25),
Q => \out\(25),
Q31 => \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][26]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(26),
Q => \out\(26),
Q31 => \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][27]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(27),
Q => \out\(27),
Q31 => \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][28]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(28),
Q => \out\(28),
Q31 => \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][29]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(29),
Q => \out\(29),
Q31 => \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(2),
Q => \out\(2),
Q31 => \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][30]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(30),
Q => \out\(30),
Q31 => \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][31]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(31),
Q => \out\(31),
Q31 => \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][32]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(32),
Q => \out\(32),
Q31 => \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][33]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(33),
Q => \out\(33),
Q31 => \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(3),
Q => \out\(3),
Q31 => \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(4),
Q => \out\(4),
Q31 => \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(5),
Q => \out\(5),
Q31 => \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(6),
Q => \out\(6),
Q31 => \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(7),
Q => \out\(7),
Q31 => \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(8),
Q => \out\(8),
Q31 => \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(9),
Q => \out\(9),
Q31 => \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\
);
\state[1]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"7C000000"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => \cnt_read_reg[2]_rep__2_n_0\,
I2 => \cnt_read_reg[1]_rep__2_n_0\,
I3 => \^cnt_read_reg[4]_rep__2_0\,
I4 => \^cnt_read_reg[3]_rep__2_0\,
O => \state_reg[1]_rep\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\ is
port (
\state_reg[1]_rep\ : out STD_LOGIC;
\cnt_read_reg[4]_rep__2\ : out STD_LOGIC;
m_valid_i_reg : out STD_LOGIC;
\skid_buffer_reg[46]\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
r_push_r : in STD_LOGIC;
s_ready_i_reg : in STD_LOGIC;
\cnt_read_reg[0]_rep__2\ : in STD_LOGIC;
si_rs_rready : in STD_LOGIC;
wr_en0 : in STD_LOGIC;
\cnt_read_reg[4]_rep__2_0\ : in STD_LOGIC;
\cnt_read_reg[3]_rep__2\ : in STD_LOGIC;
\cnt_read_reg[0]_rep__2_0\ : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 12 downto 0 );
aclk : in STD_LOGIC;
areset_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\ : entity is "axi_protocol_converter_v2_1_13_b2s_simple_fifo";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\ is
signal cnt_read : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \cnt_read[0]_i_1__1_n_0\ : STD_LOGIC;
signal \cnt_read[1]_i_1__1_n_0\ : STD_LOGIC;
signal \cnt_read[2]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[3]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_2__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_3__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_4__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_5__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep_n_0\ : STD_LOGIC;
signal \^m_valid_i_reg\ : STD_LOGIC;
signal \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[0]_i_1__1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \cnt_read[1]_i_1__1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \cnt_read[2]_i_1__0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \cnt_read[4]_i_2__0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \cnt_read[4]_i_3__0\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \cnt_read[4]_i_4__0\ : label is "soft_lutpair11";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]";
attribute KEEP of \cnt_read_reg[2]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__0\ : label is "cnt_read_reg[2]";
attribute KEEP of \cnt_read_reg[3]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__0\ : label is "cnt_read_reg[3]";
attribute KEEP of \cnt_read_reg[4]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__0\ : label is "cnt_read_reg[4]";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][0]_srl32 ";
attribute srl_bus_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][10]_srl32 ";
attribute srl_bus_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][11]_srl32 ";
attribute srl_bus_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][12]_srl32 ";
attribute srl_bus_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][1]_srl32 ";
attribute srl_bus_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][2]_srl32 ";
attribute srl_bus_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][3]_srl32 ";
attribute srl_bus_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][4]_srl32 ";
attribute srl_bus_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][5]_srl32 ";
attribute srl_bus_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][6]_srl32 ";
attribute srl_bus_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][7]_srl32 ";
attribute srl_bus_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][8]_srl32 ";
attribute srl_bus_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][9]_srl32 ";
begin
m_valid_i_reg <= \^m_valid_i_reg\;
\cnt_read[0]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cnt_read_reg[0]_rep__0_n_0\,
I1 => s_ready_i_reg,
I2 => r_push_r,
O => \cnt_read[0]_i_1__1_n_0\
);
\cnt_read[1]_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A69A"
)
port map (
I0 => \cnt_read_reg[1]_rep__0_n_0\,
I1 => \cnt_read_reg[0]_rep__0_n_0\,
I2 => s_ready_i_reg,
I3 => r_push_r,
O => \cnt_read[1]_i_1__1_n_0\
);
\cnt_read[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AA6AA9AA"
)
port map (
I0 => \cnt_read_reg[2]_rep__0_n_0\,
I1 => \cnt_read_reg[1]_rep__0_n_0\,
I2 => r_push_r,
I3 => s_ready_i_reg,
I4 => \cnt_read_reg[0]_rep__0_n_0\,
O => \cnt_read[2]_i_1__0_n_0\
);
\cnt_read[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA6AAAAAA9AAAA"
)
port map (
I0 => \cnt_read_reg[3]_rep__0_n_0\,
I1 => \cnt_read_reg[2]_rep__0_n_0\,
I2 => \cnt_read_reg[1]_rep__0_n_0\,
I3 => r_push_r,
I4 => s_ready_i_reg,
I5 => \cnt_read_reg[0]_rep__0_n_0\,
O => \cnt_read[3]_i_1__0_n_0\
);
\cnt_read[4]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"6A666A6AAA99AAAA"
)
port map (
I0 => \cnt_read_reg[4]_rep__0_n_0\,
I1 => \cnt_read[4]_i_2__0_n_0\,
I2 => \cnt_read[4]_i_3__0_n_0\,
I3 => \cnt_read[4]_i_4__0_n_0\,
I4 => \cnt_read[4]_i_5__0_n_0\,
I5 => \cnt_read_reg[3]_rep__0_n_0\,
O => \cnt_read[4]_i_1__0_n_0\
);
\cnt_read[4]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"8A"
)
port map (
I0 => r_push_r,
I1 => \^m_valid_i_reg\,
I2 => si_rs_rready,
O => \cnt_read[4]_i_2__0_n_0\
);
\cnt_read[4]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \cnt_read_reg[2]_rep__0_n_0\,
I1 => \cnt_read_reg[1]_rep__0_n_0\,
I2 => \cnt_read_reg[0]_rep__0_n_0\,
O => \cnt_read[4]_i_3__0_n_0\
);
\cnt_read[4]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"4F"
)
port map (
I0 => \^m_valid_i_reg\,
I1 => si_rs_rready,
I2 => wr_en0,
O => \cnt_read_reg[4]_rep__2\
);
\cnt_read[4]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFB"
)
port map (
I0 => \cnt_read_reg[0]_rep__0_n_0\,
I1 => si_rs_rready,
I2 => \^m_valid_i_reg\,
I3 => r_push_r,
O => \cnt_read[4]_i_4__0_n_0\
);
\cnt_read[4]_i_5__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cnt_read_reg[1]_rep__0_n_0\,
I1 => \cnt_read_reg[2]_rep__0_n_0\,
O => \cnt_read[4]_i_5__0_n_0\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => cnt_read(0),
S => areset_d1
);
\cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => \cnt_read_reg[0]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => \cnt_read_reg[0]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => cnt_read(1),
S => areset_d1
);
\cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => \cnt_read_reg[1]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => \cnt_read_reg[1]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1__0_n_0\,
Q => cnt_read(2),
S => areset_d1
);
\cnt_read_reg[2]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1__0_n_0\,
Q => \cnt_read_reg[2]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1__0_n_0\,
Q => \cnt_read_reg[2]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => cnt_read(3),
S => areset_d1
);
\cnt_read_reg[3]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => \cnt_read_reg[3]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => \cnt_read_reg[3]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1__0_n_0\,
Q => cnt_read(4),
S => areset_d1
);
\cnt_read_reg[4]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1__0_n_0\,
Q => \cnt_read_reg[4]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1__0_n_0\,
Q => \cnt_read_reg[4]_rep__0_n_0\,
S => areset_d1
);
m_valid_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FF80808080808080"
)
port map (
I0 => \cnt_read_reg[4]_rep__0_n_0\,
I1 => \cnt_read_reg[3]_rep__0_n_0\,
I2 => \cnt_read[4]_i_3__0_n_0\,
I3 => \cnt_read_reg[4]_rep__2_0\,
I4 => \cnt_read_reg[3]_rep__2\,
I5 => \cnt_read_reg[0]_rep__2_0\,
O => \^m_valid_i_reg\
);
\memory_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(0),
Q => \skid_buffer_reg[46]\(0),
Q31 => \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(10),
Q => \skid_buffer_reg[46]\(10),
Q31 => \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(11),
Q => \skid_buffer_reg[46]\(11),
Q31 => \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(12),
Q => \skid_buffer_reg[46]\(12),
Q31 => \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(1),
Q => \skid_buffer_reg[46]\(1),
Q31 => \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(2),
Q => \skid_buffer_reg[46]\(2),
Q31 => \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(3),
Q => \skid_buffer_reg[46]\(3),
Q31 => \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(4),
Q => \skid_buffer_reg[46]\(4),
Q31 => \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(5),
Q => \skid_buffer_reg[46]\(5),
Q31 => \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(6),
Q => \skid_buffer_reg[46]\(6),
Q31 => \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(7),
Q => \skid_buffer_reg[46]\(7),
Q31 => \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(8),
Q => \skid_buffer_reg[46]\(8),
Q31 => \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(9),
Q => \skid_buffer_reg[46]\(9),
Q31 => \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\
);
\state[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"BEFEAAAAAAAAAAAA"
)
port map (
I0 => \cnt_read_reg[0]_rep__2\,
I1 => \cnt_read_reg[2]_rep__0_n_0\,
I2 => \cnt_read_reg[1]_rep__0_n_0\,
I3 => \cnt_read_reg[0]_rep__0_n_0\,
I4 => \cnt_read_reg[3]_rep__0_n_0\,
I5 => \cnt_read_reg[4]_rep__0_n_0\,
O => \state_reg[1]_rep\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm is
port (
\axlen_cnt_reg[4]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_second_len_r_reg[1]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep_0\ : out STD_LOGIC;
\state_reg[1]_rep_1\ : out STD_LOGIC;
\axlen_cnt_reg[5]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axburst_eq0_reg : out STD_LOGIC;
wrap_next_pending : out STD_LOGIC;
sel_first_i : out STD_LOGIC;
incr_next_pending : out STD_LOGIC;
s_axburst_eq1_reg : out STD_LOGIC;
\next\ : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC;
\axaddr_wrap_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC;
\m_payload_i_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
sel_first_reg : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
si_rs_awvalid : in STD_LOGIC;
\axlen_cnt_reg[3]\ : in STD_LOGIC;
\m_payload_i_reg[44]\ : in STD_LOGIC;
s_axburst_eq1_reg_0 : in STD_LOGIC;
\cnt_read_reg[1]_rep__1\ : in STD_LOGIC;
\cnt_read_reg[0]_rep__0\ : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
\m_payload_i_reg[49]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
\axlen_cnt_reg[5]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\axlen_cnt_reg[3]_0\ : in STD_LOGIC;
\axlen_cnt_reg[4]_0\ : in STD_LOGIC;
\wrap_second_len_r_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[35]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[48]\ : in STD_LOGIC;
next_pending_r_reg : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
\m_payload_i_reg[46]\ : in STD_LOGIC;
\axlen_cnt_reg[2]\ : in STD_LOGIC;
next_pending_r_reg_0 : in STD_LOGIC;
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
\sel_first__0\ : in STD_LOGIC;
aclk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axlen_cnt_reg[4]\ : STD_LOGIC;
signal \^incr_next_pending\ : STD_LOGIC;
signal \^m_payload_i_reg[0]\ : STD_LOGIC;
signal \^next\ : STD_LOGIC;
signal next_state : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^sel_first_i\ : STD_LOGIC;
signal \state[0]_i_2_n_0\ : STD_LOGIC;
signal \state[1]_i_1__0_n_0\ : STD_LOGIC;
signal \^state_reg[1]_rep_0\ : STD_LOGIC;
signal \^state_reg[1]_rep_1\ : STD_LOGIC;
signal \^wrap_next_pending\ : STD_LOGIC;
signal \^wrap_second_len_r_reg[1]\ : STD_LOGIC_VECTOR ( 0 to 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_incr[0]_i_1\ : label is "soft_lutpair110";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_1\ : label is "soft_lutpair110";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_5\ : label is "soft_lutpair111";
attribute SOFT_HLUTNM of m_axi_awvalid_INST_0 : label is "soft_lutpair112";
attribute SOFT_HLUTNM of s_axburst_eq0_i_1 : label is "soft_lutpair109";
attribute SOFT_HLUTNM of s_axburst_eq1_i_1 : label is "soft_lutpair109";
attribute SOFT_HLUTNM of \state[0]_i_1\ : label is "soft_lutpair111";
attribute KEEP : string;
attribute KEEP of \state_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \state_reg[0]\ : label is "state_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \state_reg[0]_rep\ : label is 1;
attribute KEEP of \state_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[0]_rep\ : label is "state_reg[0]";
attribute KEEP of \state_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]\ : label is "state_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \state_reg[1]_rep\ : label is 1;
attribute KEEP of \state_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]_rep\ : label is "state_reg[1]";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[11]_i_1\ : label is "soft_lutpair112";
begin
E(0) <= \^e\(0);
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_offset_r_reg[3]\(0) <= \^axaddr_offset_r_reg[3]\(0);
\axlen_cnt_reg[4]\ <= \^axlen_cnt_reg[4]\;
incr_next_pending <= \^incr_next_pending\;
\m_payload_i_reg[0]\ <= \^m_payload_i_reg[0]\;
\next\ <= \^next\;
sel_first_i <= \^sel_first_i\;
\state_reg[1]_rep_0\ <= \^state_reg[1]_rep_0\;
\state_reg[1]_rep_1\ <= \^state_reg[1]_rep_1\;
wrap_next_pending <= \^wrap_next_pending\;
\wrap_second_len_r_reg[1]\(0) <= \^wrap_second_len_r_reg[1]\(0);
\axaddr_incr[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EEFE"
)
port map (
I0 => sel_first_reg_2,
I1 => \^m_payload_i_reg[0]\,
I2 => \^state_reg[1]_rep_0\,
I3 => \^state_reg[1]_rep_1\,
O => \axaddr_incr_reg[11]\
);
\axaddr_offset_r[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAACAAAAAAA0AA"
)
port map (
I0 => \axaddr_offset_r_reg[3]_0\(0),
I1 => \m_payload_i_reg[49]\(3),
I2 => \^state_reg[1]_rep_1\,
I3 => si_rs_awvalid,
I4 => \^state_reg[1]_rep_0\,
I5 => \m_payload_i_reg[6]\,
O => \^axaddr_offset_r_reg[3]\(0)
);
\axlen_cnt[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0400FFFF04000400"
)
port map (
I0 => \^q\(1),
I1 => si_rs_awvalid,
I2 => \^q\(0),
I3 => \m_payload_i_reg[49]\(1),
I4 => \axlen_cnt_reg[5]_0\(0),
I5 => \^axlen_cnt_reg[4]\,
O => \axlen_cnt_reg[5]\(0)
);
\axlen_cnt[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => \^e\(0),
I1 => \m_payload_i_reg[49]\(2),
I2 => \axlen_cnt_reg[5]_0\(1),
I3 => \axlen_cnt_reg[5]_0\(0),
I4 => \^axlen_cnt_reg[4]\,
O => \axlen_cnt_reg[5]\(1)
);
\axlen_cnt[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => \^e\(0),
I1 => \m_payload_i_reg[49]\(4),
I2 => \axlen_cnt_reg[5]_0\(2),
I3 => \axlen_cnt_reg[3]_0\,
I4 => \^axlen_cnt_reg[4]\,
O => \axlen_cnt_reg[5]\(2)
);
\axlen_cnt[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => \^e\(0),
I1 => \m_payload_i_reg[49]\(5),
I2 => \axlen_cnt_reg[5]_0\(3),
I3 => \axlen_cnt_reg[4]_0\,
I4 => \^axlen_cnt_reg[4]\,
O => \axlen_cnt_reg[5]\(3)
);
\axlen_cnt[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCFE"
)
port map (
I0 => si_rs_awvalid,
I1 => \^m_payload_i_reg[0]\,
I2 => \^state_reg[1]_rep_0\,
I3 => \^state_reg[1]_rep_1\,
O => \axaddr_wrap_reg[0]\(0)
);
\axlen_cnt[7]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"00FB"
)
port map (
I0 => \^q\(0),
I1 => si_rs_awvalid,
I2 => \^q\(1),
I3 => \axlen_cnt_reg[3]\,
O => \^axlen_cnt_reg[4]\
);
m_axi_awvalid_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^state_reg[1]_rep_1\,
I1 => \^state_reg[1]_rep_0\,
O => m_axi_awvalid
);
\m_payload_i[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => si_rs_awvalid,
O => \m_payload_i_reg[0]_0\(0)
);
\memory_reg[3][0]_srl4_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"88008888A800A8A8"
)
port map (
I0 => \^state_reg[1]_rep_1\,
I1 => \^state_reg[1]_rep_0\,
I2 => m_axi_awready,
I3 => \cnt_read_reg[0]_rep__0\,
I4 => \cnt_read_reg[1]_rep__1\,
I5 => s_axburst_eq1_reg_0,
O => \^m_payload_i_reg[0]\
);
next_pending_r_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBB8B88"
)
port map (
I0 => \m_payload_i_reg[48]\,
I1 => \^e\(0),
I2 => \axlen_cnt_reg[3]\,
I3 => \^next\,
I4 => next_pending_r_reg,
O => \^incr_next_pending\
);
\next_pending_r_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBB8B88"
)
port map (
I0 => \m_payload_i_reg[46]\,
I1 => \^e\(0),
I2 => \axlen_cnt_reg[2]\,
I3 => \^next\,
I4 => next_pending_r_reg_0,
O => \^wrap_next_pending\
);
next_pending_r_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"F3F35100FFFF0000"
)
port map (
I0 => s_axburst_eq1_reg_0,
I1 => \cnt_read_reg[1]_rep__1\,
I2 => \cnt_read_reg[0]_rep__0\,
I3 => m_axi_awready,
I4 => \^state_reg[1]_rep_0\,
I5 => \^state_reg[1]_rep_1\,
O => \^next\
);
s_axburst_eq0_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => \^wrap_next_pending\,
I1 => \m_payload_i_reg[49]\(0),
I2 => \^sel_first_i\,
I3 => \^incr_next_pending\,
O => s_axburst_eq0_reg
);
s_axburst_eq1_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"ABA8"
)
port map (
I0 => \^wrap_next_pending\,
I1 => \m_payload_i_reg[49]\(0),
I2 => \^sel_first_i\,
I3 => \^incr_next_pending\,
O => s_axburst_eq1_reg
);
sel_first_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCEFCFFCCCECCCE"
)
port map (
I0 => si_rs_awvalid,
I1 => areset_d1,
I2 => \^state_reg[1]_rep_1\,
I3 => \^state_reg[1]_rep_0\,
I4 => \^m_payload_i_reg[0]\,
I5 => sel_first_reg_1,
O => \^sel_first_i\
);
\sel_first_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF44440F04"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => sel_first_reg_2,
I2 => \^q\(1),
I3 => si_rs_awvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg
);
\sel_first_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF44440F04"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => \sel_first__0\,
I2 => \^q\(1),
I3 => si_rs_awvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg_0
);
\state[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"2F"
)
port map (
I0 => si_rs_awvalid,
I1 => \^q\(0),
I2 => \state[0]_i_2_n_0\,
O => next_state(0)
);
\state[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FA08FAFA0F0F0F0F"
)
port map (
I0 => m_axi_awready,
I1 => s_axburst_eq1_reg_0,
I2 => \^state_reg[1]_rep_0\,
I3 => \cnt_read_reg[0]_rep__0\,
I4 => \cnt_read_reg[1]_rep__1\,
I5 => \^state_reg[1]_rep_1\,
O => \state[0]_i_2_n_0\
);
\state[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C0CAE0000000000"
)
port map (
I0 => s_axburst_eq1_reg_0,
I1 => \cnt_read_reg[1]_rep__1\,
I2 => \cnt_read_reg[0]_rep__0\,
I3 => m_axi_awready,
I4 => \^state_reg[1]_rep_0\,
I5 => \^state_reg[1]_rep_1\,
O => \state[1]_i_1__0_n_0\
);
\state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^q\(0),
R => areset_d1
);
\state_reg[0]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^state_reg[1]_rep_1\,
R => areset_d1
);
\state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \state[1]_i_1__0_n_0\,
Q => \^q\(1),
R => areset_d1
);
\state_reg[1]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \state[1]_i_1__0_n_0\,
Q => \^state_reg[1]_rep_0\,
R => areset_d1
);
\wrap_boundary_axaddr_r[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^state_reg[1]_rep_0\,
I1 => si_rs_awvalid,
I2 => \^state_reg[1]_rep_1\,
O => \^e\(0)
);
\wrap_cnt_r[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^wrap_second_len_r_reg[1]\(0),
I1 => \m_payload_i_reg[44]\,
O => D(0)
);
\wrap_second_len_r[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF0000FCAAAAAAAA"
)
port map (
I0 => \wrap_second_len_r_reg[1]_0\(0),
I1 => \m_payload_i_reg[35]\(2),
I2 => \^axaddr_offset_r_reg[3]\(0),
I3 => \m_payload_i_reg[35]\(0),
I4 => \m_payload_i_reg[35]\(1),
I5 => \^e\(0),
O => \^wrap_second_len_r_reg[1]\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd is
port (
next_pending_r_reg_0 : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
wrap_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC_VECTOR ( 18 downto 0 );
\next\ : in STD_LOGIC;
axaddr_incr_reg : in STD_LOGIC_VECTOR ( 7 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
\axaddr_incr_reg[3]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
sel_first_reg_2 : in STD_LOGIC;
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd is
signal axaddr_wrap : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axaddr_wrap0 : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \axaddr_wrap[0]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[10]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_7_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_8_n_0\ : STD_LOGIC;
signal \axaddr_wrap[1]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[2]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[4]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[5]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[6]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[8]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[9]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_3\ : STD_LOGIC;
signal \axlen_cnt[0]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[1]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \^sel_first_reg_0\ : STD_LOGIC;
signal wrap_boundary_axaddr_r : STD_LOGIC_VECTOR ( 11 downto 0 );
signal wrap_cnt_r : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_wrap[11]_i_2\ : label is "soft_lutpair114";
attribute SOFT_HLUTNM of \next_pending_r_i_3__0\ : label is "soft_lutpair114";
begin
sel_first_reg_0 <= \^sel_first_reg_0\;
\axaddr_offset_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(0),
Q => \axaddr_offset_r_reg[3]_0\(0),
R => '0'
);
\axaddr_offset_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(1),
Q => \axaddr_offset_r_reg[3]_0\(1),
R => '0'
);
\axaddr_offset_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(2),
Q => \axaddr_offset_r_reg[3]_0\(2),
R => '0'
);
\axaddr_offset_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(3),
Q => \axaddr_offset_r_reg[3]_0\(3),
R => '0'
);
\axaddr_wrap[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(0),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(0),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(0),
O => \axaddr_wrap[0]_i_1_n_0\
);
\axaddr_wrap[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(10),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(10),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(10),
O => \axaddr_wrap[10]_i_1_n_0\
);
\axaddr_wrap[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(11),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(11),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(11),
O => \axaddr_wrap[11]_i_1_n_0\
);
\axaddr_wrap[11]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"41"
)
port map (
I0 => \axaddr_wrap[11]_i_4_n_0\,
I1 => wrap_cnt_r(3),
I2 => \axlen_cnt_reg_n_0_[3]\,
O => \axaddr_wrap[11]_i_2_n_0\
);
\axaddr_wrap[11]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => wrap_cnt_r(0),
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => wrap_cnt_r(2),
I4 => \axlen_cnt_reg_n_0_[1]\,
I5 => wrap_cnt_r(1),
O => \axaddr_wrap[11]_i_4_n_0\
);
\axaddr_wrap[11]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(11),
O => \axaddr_wrap[11]_i_5_n_0\
);
\axaddr_wrap[11]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(10),
O => \axaddr_wrap[11]_i_6_n_0\
);
\axaddr_wrap[11]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(9),
O => \axaddr_wrap[11]_i_7_n_0\
);
\axaddr_wrap[11]_i_8\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(8),
O => \axaddr_wrap[11]_i_8_n_0\
);
\axaddr_wrap[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(1),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(1),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(1),
O => \axaddr_wrap[1]_i_1_n_0\
);
\axaddr_wrap[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(2),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(2),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(2),
O => \axaddr_wrap[2]_i_1_n_0\
);
\axaddr_wrap[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(3),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(3),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(3),
O => \axaddr_wrap[3]_i_1_n_0\
);
\axaddr_wrap[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => axaddr_wrap(3),
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_3_n_0\
);
\axaddr_wrap[3]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => axaddr_wrap(2),
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_4_n_0\
);
\axaddr_wrap[3]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => axaddr_wrap(1),
I1 => \m_payload_i_reg[47]\(13),
I2 => \m_payload_i_reg[47]\(12),
O => \axaddr_wrap[3]_i_5_n_0\
);
\axaddr_wrap[3]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"A9"
)
port map (
I0 => axaddr_wrap(0),
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(4),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(4),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(4),
O => \axaddr_wrap[4]_i_1_n_0\
);
\axaddr_wrap[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(5),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(5),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(5),
O => \axaddr_wrap[5]_i_1_n_0\
);
\axaddr_wrap[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(6),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(6),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(6),
O => \axaddr_wrap[6]_i_1_n_0\
);
\axaddr_wrap[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(7),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(7),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(7),
O => \axaddr_wrap[7]_i_1_n_0\
);
\axaddr_wrap[7]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(7),
O => \axaddr_wrap[7]_i_3_n_0\
);
\axaddr_wrap[7]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(6),
O => \axaddr_wrap[7]_i_4_n_0\
);
\axaddr_wrap[7]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(5),
O => \axaddr_wrap[7]_i_5_n_0\
);
\axaddr_wrap[7]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(4),
O => \axaddr_wrap[7]_i_6_n_0\
);
\axaddr_wrap[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(8),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(8),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(8),
O => \axaddr_wrap[8]_i_1_n_0\
);
\axaddr_wrap[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(9),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(9),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(9),
O => \axaddr_wrap[9]_i_1_n_0\
);
\axaddr_wrap_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[0]_i_1_n_0\,
Q => axaddr_wrap(0),
R => '0'
);
\axaddr_wrap_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[10]_i_1_n_0\,
Q => axaddr_wrap(10),
R => '0'
);
\axaddr_wrap_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[11]_i_1_n_0\,
Q => axaddr_wrap(11),
R => '0'
);
\axaddr_wrap_reg[11]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[7]_i_2_n_0\,
CO(3) => \NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED\(3),
CO(2) => \axaddr_wrap_reg[11]_i_3_n_1\,
CO(1) => \axaddr_wrap_reg[11]_i_3_n_2\,
CO(0) => \axaddr_wrap_reg[11]_i_3_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => axaddr_wrap0(11 downto 8),
S(3) => \axaddr_wrap[11]_i_5_n_0\,
S(2) => \axaddr_wrap[11]_i_6_n_0\,
S(1) => \axaddr_wrap[11]_i_7_n_0\,
S(0) => \axaddr_wrap[11]_i_8_n_0\
);
\axaddr_wrap_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[1]_i_1_n_0\,
Q => axaddr_wrap(1),
R => '0'
);
\axaddr_wrap_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[2]_i_1_n_0\,
Q => axaddr_wrap(2),
R => '0'
);
\axaddr_wrap_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[3]_i_1_n_0\,
Q => axaddr_wrap(3),
R => '0'
);
\axaddr_wrap_reg[3]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_wrap_reg[3]_i_2_n_0\,
CO(2) => \axaddr_wrap_reg[3]_i_2_n_1\,
CO(1) => \axaddr_wrap_reg[3]_i_2_n_2\,
CO(0) => \axaddr_wrap_reg[3]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => axaddr_wrap(3 downto 0),
O(3 downto 0) => axaddr_wrap0(3 downto 0),
S(3) => \axaddr_wrap[3]_i_3_n_0\,
S(2) => \axaddr_wrap[3]_i_4_n_0\,
S(1) => \axaddr_wrap[3]_i_5_n_0\,
S(0) => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[4]_i_1_n_0\,
Q => axaddr_wrap(4),
R => '0'
);
\axaddr_wrap_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[5]_i_1_n_0\,
Q => axaddr_wrap(5),
R => '0'
);
\axaddr_wrap_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[6]_i_1_n_0\,
Q => axaddr_wrap(6),
R => '0'
);
\axaddr_wrap_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[7]_i_1_n_0\,
Q => axaddr_wrap(7),
R => '0'
);
\axaddr_wrap_reg[7]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[3]_i_2_n_0\,
CO(3) => \axaddr_wrap_reg[7]_i_2_n_0\,
CO(2) => \axaddr_wrap_reg[7]_i_2_n_1\,
CO(1) => \axaddr_wrap_reg[7]_i_2_n_2\,
CO(0) => \axaddr_wrap_reg[7]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => axaddr_wrap0(7 downto 4),
S(3) => \axaddr_wrap[7]_i_3_n_0\,
S(2) => \axaddr_wrap[7]_i_4_n_0\,
S(1) => \axaddr_wrap[7]_i_5_n_0\,
S(0) => \axaddr_wrap[7]_i_6_n_0\
);
\axaddr_wrap_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[8]_i_1_n_0\,
Q => axaddr_wrap(8),
R => '0'
);
\axaddr_wrap_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[9]_i_1_n_0\,
Q => axaddr_wrap(9),
R => '0'
);
\axlen_cnt[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A3A3A3A3A3A3A3A0"
)
port map (
I0 => \m_payload_i_reg[47]\(15),
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => E(0),
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => \axlen_cnt_reg_n_0_[1]\,
I5 => \axlen_cnt_reg_n_0_[2]\,
O => \axlen_cnt[0]_i_1__0_n_0\
);
\axlen_cnt[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF999800009998"
)
port map (
I0 => \axlen_cnt_reg_n_0_[1]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(16),
O => \axlen_cnt[1]_i_1__0_n_0\
);
\axlen_cnt[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFA9A80000A9A8"
)
port map (
I0 => \axlen_cnt_reg_n_0_[2]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(17),
O => \axlen_cnt[2]_i_1__0_n_0\
);
\axlen_cnt[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFAAA80000AAA8"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(18),
O => \axlen_cnt[3]_i_1__0_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[0]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[0]\,
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[1]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[1]\,
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[2]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\m_axi_awaddr[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(0),
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(0),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(0),
O => m_axi_awaddr(0)
);
\m_axi_awaddr[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(10),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(6),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(10),
O => m_axi_awaddr(10)
);
\m_axi_awaddr[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(11),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(7),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(11),
O => m_axi_awaddr(11)
);
\m_axi_awaddr[1]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \m_payload_i_reg[47]\(1),
I1 => \^sel_first_reg_0\,
I2 => axaddr_wrap(1),
I3 => \m_payload_i_reg[47]\(14),
I4 => sel_first_reg_2,
O => m_axi_awaddr(1)
);
\m_axi_awaddr[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(2),
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(1),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(2),
O => m_axi_awaddr(2)
);
\m_axi_awaddr[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(3),
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(2),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(3),
O => m_axi_awaddr(3)
);
\m_axi_awaddr[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(4),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(0),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(4),
O => m_axi_awaddr(4)
);
\m_axi_awaddr[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(5),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(1),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(5),
O => m_axi_awaddr(5)
);
\m_axi_awaddr[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(6),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(2),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(6),
O => m_axi_awaddr(6)
);
\m_axi_awaddr[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(7),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(3),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(7),
O => m_axi_awaddr(7)
);
\m_axi_awaddr[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(8),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(4),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(8),
O => m_axi_awaddr(8)
);
\m_axi_awaddr[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(9),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(5),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(9),
O => m_axi_awaddr(9)
);
\next_pending_r_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \axlen_cnt_reg_n_0_[2]\,
I1 => \axlen_cnt_reg_n_0_[1]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
O => next_pending_r_reg_1
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => wrap_next_pending,
Q => next_pending_r_reg_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^sel_first_reg_0\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(0),
Q => wrap_boundary_axaddr_r(0),
R => '0'
);
\wrap_boundary_axaddr_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(10),
Q => wrap_boundary_axaddr_r(10),
R => '0'
);
\wrap_boundary_axaddr_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(11),
Q => wrap_boundary_axaddr_r(11),
R => '0'
);
\wrap_boundary_axaddr_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(1),
Q => wrap_boundary_axaddr_r(1),
R => '0'
);
\wrap_boundary_axaddr_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(2),
Q => wrap_boundary_axaddr_r(2),
R => '0'
);
\wrap_boundary_axaddr_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(3),
Q => wrap_boundary_axaddr_r(3),
R => '0'
);
\wrap_boundary_axaddr_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(4),
Q => wrap_boundary_axaddr_r(4),
R => '0'
);
\wrap_boundary_axaddr_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(5),
Q => wrap_boundary_axaddr_r(5),
R => '0'
);
\wrap_boundary_axaddr_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(6),
Q => wrap_boundary_axaddr_r(6),
R => '0'
);
\wrap_boundary_axaddr_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(7),
Q => wrap_boundary_axaddr_r(7),
R => '0'
);
\wrap_boundary_axaddr_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(8),
Q => wrap_boundary_axaddr_r(8),
R => '0'
);
\wrap_boundary_axaddr_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(9),
Q => wrap_boundary_axaddr_r(9),
R => '0'
);
\wrap_cnt_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(0),
Q => wrap_cnt_r(0),
R => '0'
);
\wrap_cnt_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(1),
Q => wrap_cnt_r(1),
R => '0'
);
\wrap_cnt_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(2),
Q => wrap_cnt_r(2),
R => '0'
);
\wrap_cnt_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(3),
Q => wrap_cnt_r(3),
R => '0'
);
\wrap_second_len_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(0),
Q => \wrap_second_len_r_reg[3]_0\(0),
R => '0'
);
\wrap_second_len_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(1),
Q => \wrap_second_len_r_reg[3]_0\(1),
R => '0'
);
\wrap_second_len_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(2),
Q => \wrap_second_len_r_reg[3]_0\(2),
R => '0'
);
\wrap_second_len_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(3),
Q => \wrap_second_len_r_reg[3]_0\(3),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3 is
port (
wrap_next_pending : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC_VECTOR ( 18 downto 0 );
\state_reg[0]_rep\ : in STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
\m_payload_i_reg[46]\ : in STD_LOGIC;
\state_reg[1]_rep_0\ : in STD_LOGIC;
\axaddr_incr_reg[11]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
\axaddr_incr_reg[3]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
sel_first_reg_2 : in STD_LOGIC;
sel_first_reg_3 : in STD_LOGIC;
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3 : entity is "axi_protocol_converter_v2_1_13_b2s_wrap_cmd";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3 is
signal \axaddr_wrap[0]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[10]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_7__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_8__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[1]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[2]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[4]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[5]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[6]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[8]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[9]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_4\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_5\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_6\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_7\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_4\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_5\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_6\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_7\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_4\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_5\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_6\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_7\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[0]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[10]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[11]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[1]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[2]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[3]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[4]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[5]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[6]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[7]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[8]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[9]\ : STD_LOGIC;
signal \axlen_cnt[0]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[1]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \next_pending_r_i_3__2_n_0\ : STD_LOGIC;
signal next_pending_r_reg_n_0 : STD_LOGIC;
signal \^sel_first_reg_0\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[0]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[10]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[11]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[1]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[2]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[3]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[4]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[5]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[6]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[7]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[8]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[0]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[1]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[2]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[3]\ : STD_LOGIC;
signal \^wrap_next_pending\ : STD_LOGIC;
signal \NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
begin
sel_first_reg_0 <= \^sel_first_reg_0\;
wrap_next_pending <= \^wrap_next_pending\;
\axaddr_offset_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(0),
Q => \axaddr_offset_r_reg[3]_0\(0),
R => '0'
);
\axaddr_offset_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(1),
Q => \axaddr_offset_r_reg[3]_0\(1),
R => '0'
);
\axaddr_offset_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(2),
Q => \axaddr_offset_r_reg[3]_0\(2),
R => '0'
);
\axaddr_offset_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(3),
Q => \axaddr_offset_r_reg[3]_0\(3),
R => '0'
);
\axaddr_wrap[0]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[0]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_7\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(0),
O => \axaddr_wrap[0]_i_1__0_n_0\
);
\axaddr_wrap[10]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[10]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_5\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(10),
O => \axaddr_wrap[10]_i_1__0_n_0\
);
\axaddr_wrap[11]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[11]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_4\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(11),
O => \axaddr_wrap[11]_i_1__0_n_0\
);
\axaddr_wrap[11]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"41"
)
port map (
I0 => \axaddr_wrap[11]_i_4__0_n_0\,
I1 => \wrap_cnt_r_reg_n_0_[3]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
O => \axaddr_wrap[11]_i_2__0_n_0\
);
\axaddr_wrap[11]_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => \wrap_cnt_r_reg_n_0_[0]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \wrap_cnt_r_reg_n_0_[1]\,
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \wrap_cnt_r_reg_n_0_[2]\,
O => \axaddr_wrap[11]_i_4__0_n_0\
);
\axaddr_wrap[11]_i_5__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[11]\,
O => \axaddr_wrap[11]_i_5__0_n_0\
);
\axaddr_wrap[11]_i_6__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[10]\,
O => \axaddr_wrap[11]_i_6__0_n_0\
);
\axaddr_wrap[11]_i_7__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[9]\,
O => \axaddr_wrap[11]_i_7__0_n_0\
);
\axaddr_wrap[11]_i_8__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[8]\,
O => \axaddr_wrap[11]_i_8__0_n_0\
);
\axaddr_wrap[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[1]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_6\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(1),
O => \axaddr_wrap[1]_i_1__0_n_0\
);
\axaddr_wrap[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[2]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_5\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(2),
O => \axaddr_wrap[2]_i_1__0_n_0\
);
\axaddr_wrap[3]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[3]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_4\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(3),
O => \axaddr_wrap[3]_i_1__0_n_0\
);
\axaddr_wrap[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[3]\,
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_3_n_0\
);
\axaddr_wrap[3]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[2]\,
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_4_n_0\
);
\axaddr_wrap[3]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[1]\,
I1 => \m_payload_i_reg[47]\(13),
I2 => \m_payload_i_reg[47]\(12),
O => \axaddr_wrap[3]_i_5_n_0\
);
\axaddr_wrap[3]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"A9"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[0]\,
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[4]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_7\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(4),
O => \axaddr_wrap[4]_i_1__0_n_0\
);
\axaddr_wrap[5]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[5]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_6\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(5),
O => \axaddr_wrap[5]_i_1__0_n_0\
);
\axaddr_wrap[6]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[6]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_5\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(6),
O => \axaddr_wrap[6]_i_1__0_n_0\
);
\axaddr_wrap[7]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[7]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_4\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(7),
O => \axaddr_wrap[7]_i_1__0_n_0\
);
\axaddr_wrap[7]_i_3__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[7]\,
O => \axaddr_wrap[7]_i_3__0_n_0\
);
\axaddr_wrap[7]_i_4__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[6]\,
O => \axaddr_wrap[7]_i_4__0_n_0\
);
\axaddr_wrap[7]_i_5__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[5]\,
O => \axaddr_wrap[7]_i_5__0_n_0\
);
\axaddr_wrap[7]_i_6__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[4]\,
O => \axaddr_wrap[7]_i_6__0_n_0\
);
\axaddr_wrap[8]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[8]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_7\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(8),
O => \axaddr_wrap[8]_i_1__0_n_0\
);
\axaddr_wrap[9]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[9]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_6\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(9),
O => \axaddr_wrap[9]_i_1__0_n_0\
);
\axaddr_wrap_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[0]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[0]\,
R => '0'
);
\axaddr_wrap_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[10]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[10]\,
R => '0'
);
\axaddr_wrap_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[11]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[11]\,
R => '0'
);
\axaddr_wrap_reg[11]_i_3__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[7]_i_2__0_n_0\,
CO(3) => \NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED\(3),
CO(2) => \axaddr_wrap_reg[11]_i_3__0_n_1\,
CO(1) => \axaddr_wrap_reg[11]_i_3__0_n_2\,
CO(0) => \axaddr_wrap_reg[11]_i_3__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_wrap_reg[11]_i_3__0_n_4\,
O(2) => \axaddr_wrap_reg[11]_i_3__0_n_5\,
O(1) => \axaddr_wrap_reg[11]_i_3__0_n_6\,
O(0) => \axaddr_wrap_reg[11]_i_3__0_n_7\,
S(3) => \axaddr_wrap[11]_i_5__0_n_0\,
S(2) => \axaddr_wrap[11]_i_6__0_n_0\,
S(1) => \axaddr_wrap[11]_i_7__0_n_0\,
S(0) => \axaddr_wrap[11]_i_8__0_n_0\
);
\axaddr_wrap_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[1]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[1]\,
R => '0'
);
\axaddr_wrap_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[2]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[2]\,
R => '0'
);
\axaddr_wrap_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[3]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[3]\,
R => '0'
);
\axaddr_wrap_reg[3]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_wrap_reg[3]_i_2__0_n_0\,
CO(2) => \axaddr_wrap_reg[3]_i_2__0_n_1\,
CO(1) => \axaddr_wrap_reg[3]_i_2__0_n_2\,
CO(0) => \axaddr_wrap_reg[3]_i_2__0_n_3\,
CYINIT => '0',
DI(3) => \axaddr_wrap_reg_n_0_[3]\,
DI(2) => \axaddr_wrap_reg_n_0_[2]\,
DI(1) => \axaddr_wrap_reg_n_0_[1]\,
DI(0) => \axaddr_wrap_reg_n_0_[0]\,
O(3) => \axaddr_wrap_reg[3]_i_2__0_n_4\,
O(2) => \axaddr_wrap_reg[3]_i_2__0_n_5\,
O(1) => \axaddr_wrap_reg[3]_i_2__0_n_6\,
O(0) => \axaddr_wrap_reg[3]_i_2__0_n_7\,
S(3) => \axaddr_wrap[3]_i_3_n_0\,
S(2) => \axaddr_wrap[3]_i_4_n_0\,
S(1) => \axaddr_wrap[3]_i_5_n_0\,
S(0) => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[4]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[4]\,
R => '0'
);
\axaddr_wrap_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[5]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[5]\,
R => '0'
);
\axaddr_wrap_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[6]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[6]\,
R => '0'
);
\axaddr_wrap_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[7]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[7]\,
R => '0'
);
\axaddr_wrap_reg[7]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[3]_i_2__0_n_0\,
CO(3) => \axaddr_wrap_reg[7]_i_2__0_n_0\,
CO(2) => \axaddr_wrap_reg[7]_i_2__0_n_1\,
CO(1) => \axaddr_wrap_reg[7]_i_2__0_n_2\,
CO(0) => \axaddr_wrap_reg[7]_i_2__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_wrap_reg[7]_i_2__0_n_4\,
O(2) => \axaddr_wrap_reg[7]_i_2__0_n_5\,
O(1) => \axaddr_wrap_reg[7]_i_2__0_n_6\,
O(0) => \axaddr_wrap_reg[7]_i_2__0_n_7\,
S(3) => \axaddr_wrap[7]_i_3__0_n_0\,
S(2) => \axaddr_wrap[7]_i_4__0_n_0\,
S(1) => \axaddr_wrap[7]_i_5__0_n_0\,
S(0) => \axaddr_wrap[7]_i_6__0_n_0\
);
\axaddr_wrap_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[8]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[8]\,
R => '0'
);
\axaddr_wrap_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[9]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[9]\,
R => '0'
);
\axlen_cnt[0]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"A3A3A3A3A3A3A3A0"
)
port map (
I0 => \m_payload_i_reg[47]\(15),
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => E(0),
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \axlen_cnt_reg_n_0_[1]\,
O => \axlen_cnt[0]_i_1__2_n_0\
);
\axlen_cnt[1]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF999800009998"
)
port map (
I0 => \axlen_cnt_reg_n_0_[1]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(16),
O => \axlen_cnt[1]_i_1__2_n_0\
);
\axlen_cnt[2]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFA9A80000A9A8"
)
port map (
I0 => \axlen_cnt_reg_n_0_[2]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(17),
O => \axlen_cnt[2]_i_1__2_n_0\
);
\axlen_cnt[3]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFAAA80000AAA8"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(18),
O => \axlen_cnt[3]_i_1__2_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[0]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[0]\,
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[1]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[1]\,
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[2]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\m_axi_araddr[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[0]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(0),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(0),
O => m_axi_araddr(0)
);
\m_axi_araddr[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[10]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(5),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(10),
O => m_axi_araddr(10)
);
\m_axi_araddr[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[11]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(6),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(11),
O => m_axi_araddr(11)
);
\m_axi_araddr[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[1]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(1),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(1),
O => m_axi_araddr(1)
);
\m_axi_araddr[2]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \m_payload_i_reg[47]\(2),
I1 => \^sel_first_reg_0\,
I2 => \axaddr_wrap_reg_n_0_[2]\,
I3 => \m_payload_i_reg[47]\(14),
I4 => sel_first_reg_3,
O => m_axi_araddr(2)
);
\m_axi_araddr[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[3]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(2),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(3),
O => m_axi_araddr(3)
);
\m_axi_araddr[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[4]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(0),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(4),
O => m_axi_araddr(4)
);
\m_axi_araddr[5]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \m_payload_i_reg[47]\(5),
I1 => \^sel_first_reg_0\,
I2 => \axaddr_wrap_reg_n_0_[5]\,
I3 => \m_payload_i_reg[47]\(14),
I4 => sel_first_reg_2,
O => m_axi_araddr(5)
);
\m_axi_araddr[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[6]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(1),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(6),
O => m_axi_araddr(6)
);
\m_axi_araddr[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[7]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(2),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(7),
O => m_axi_araddr(7)
);
\m_axi_araddr[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[8]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(3),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(8),
O => m_axi_araddr(8)
);
\m_axi_araddr[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[9]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(4),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(9),
O => m_axi_araddr(9)
);
\next_pending_r_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FD55FC0C"
)
port map (
I0 => \m_payload_i_reg[46]\,
I1 => next_pending_r_reg_n_0,
I2 => \state_reg[1]_rep_0\,
I3 => \next_pending_r_i_3__2_n_0\,
I4 => E(0),
O => \^wrap_next_pending\
);
\next_pending_r_i_3__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FBFBFBFBFBFBFB00"
)
port map (
I0 => \state_reg[0]_rep\,
I1 => si_rs_arvalid,
I2 => \state_reg[1]_rep\,
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \axlen_cnt_reg_n_0_[1]\,
O => \next_pending_r_i_3__2_n_0\
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \^wrap_next_pending\,
Q => next_pending_r_reg_n_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^sel_first_reg_0\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(0),
Q => \wrap_boundary_axaddr_r_reg_n_0_[0]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(10),
Q => \wrap_boundary_axaddr_r_reg_n_0_[10]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(11),
Q => \wrap_boundary_axaddr_r_reg_n_0_[11]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(1),
Q => \wrap_boundary_axaddr_r_reg_n_0_[1]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(2),
Q => \wrap_boundary_axaddr_r_reg_n_0_[2]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(3),
Q => \wrap_boundary_axaddr_r_reg_n_0_[3]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(4),
Q => \wrap_boundary_axaddr_r_reg_n_0_[4]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(5),
Q => \wrap_boundary_axaddr_r_reg_n_0_[5]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(6),
Q => \wrap_boundary_axaddr_r_reg_n_0_[6]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(7),
Q => \wrap_boundary_axaddr_r_reg_n_0_[7]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(8),
Q => \wrap_boundary_axaddr_r_reg_n_0_[8]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(9),
Q => \wrap_boundary_axaddr_r_reg_n_0_[9]\,
R => '0'
);
\wrap_cnt_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(0),
Q => \wrap_cnt_r_reg_n_0_[0]\,
R => '0'
);
\wrap_cnt_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(1),
Q => \wrap_cnt_r_reg_n_0_[1]\,
R => '0'
);
\wrap_cnt_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(2),
Q => \wrap_cnt_r_reg_n_0_[2]\,
R => '0'
);
\wrap_cnt_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(3),
Q => \wrap_cnt_r_reg_n_0_[3]\,
R => '0'
);
\wrap_second_len_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(0),
Q => \wrap_second_len_r_reg[3]_0\(0),
R => '0'
);
\wrap_second_len_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(1),
Q => \wrap_second_len_r_reg[3]_0\(1),
R => '0'
);
\wrap_second_len_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(2),
Q => \wrap_second_len_r_reg[3]_0\(2),
R => '0'
);
\wrap_second_len_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(3),
Q => \wrap_second_len_r_reg[3]_0\(3),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice is
port (
s_axi_arready : out STD_LOGIC;
s_ready_i_reg_0 : out STD_LOGIC;
m_valid_i_reg_0 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 58 downto 0 );
\axaddr_incr_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[7]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_cnt_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[3]_0\ : out STD_LOGIC;
\axaddr_offset_r_reg[1]\ : out STD_LOGIC;
\axaddr_offset_r_reg[0]\ : out STD_LOGIC;
\axaddr_offset_r_reg[2]\ : out STD_LOGIC;
\axlen_cnt_reg[3]\ : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
\axaddr_offset_r_reg[3]\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\m_axi_araddr[10]\ : out STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[0]_0\ : in STD_LOGIC;
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_payload_i_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
wrap_second_len_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[0]_rep\ : in STD_LOGIC;
\state_reg[1]_rep_0\ : in STD_LOGIC;
sel_first_2 : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
\axaddr_incr_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice is
signal \^q\ : STD_LOGIC_VECTOR ( 58 downto 0 );
signal \axaddr_incr[0]_i_10__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_12__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_13__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_14__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_7__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_8__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_9__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_10__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_7__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_8__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_9__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_10__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_7__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_8__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_9__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6__0_n_3\ : STD_LOGIC;
signal \axaddr_offset_r[0]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[1]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_3__0_n_0\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[0]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[1]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[2]\ : STD_LOGIC;
signal \^axlen_cnt_reg[3]\ : STD_LOGIC;
signal \m_payload_i[0]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[10]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[14]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[15]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[16]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[17]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[18]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[19]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[20]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[21]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[22]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[23]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[24]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[25]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[26]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[27]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[28]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[29]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[30]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[31]_i_2__0_n_0\ : STD_LOGIC;
signal \m_payload_i[32]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[33]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[34]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[35]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[36]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[38]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[39]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[44]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[45]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[46]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[47]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[48]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[49]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[50]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[51]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[53]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[54]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[55]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[56]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[57]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[58]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[59]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[60]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[61]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[62]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[63]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[64]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_1__0_n_0\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^next_pending_r_reg_0\ : STD_LOGIC;
signal \^s_axi_arready\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[48]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[49]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[54]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[55]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[56]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[57]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[58]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[59]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[60]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[61]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[62]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[63]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[64]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r[3]_i_2__0_n_0\ : STD_LOGIC;
signal \wrap_cnt_r[3]_i_3__0_n_0\ : STD_LOGIC;
signal \^wrap_cnt_r_reg[3]_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_2__0_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_3__0_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_4__0_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[3]_i_2__0_n_0\ : STD_LOGIC;
signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_axaddr_incr_reg[8]_i_6__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_offset_r[1]_i_2__0\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \axaddr_offset_r[2]_i_2__0\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__0\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__0\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__0\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__0\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__0\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__0\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__0\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__0\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__0\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__0\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__0\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__0\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__0\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__0\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__0\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__0\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__0\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__0\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__0\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__0\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_2__0\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__0\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__0\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__0\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__0\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__0\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__0\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__0\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__0\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__0\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__0\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[47]_i_1__0\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[48]_i_1__0\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[49]_i_1__0\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__0\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[50]_i_1__0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[51]_i_1__0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[53]_i_1__0\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[54]_i_1__0\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[55]_i_1__0\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \m_payload_i[56]_i_1__0\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \m_payload_i[57]_i_1__0\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \m_payload_i[58]_i_1__0\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \m_payload_i[59]_i_1__0\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__0\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[60]_i_1__0\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \m_payload_i[61]_i_1__0\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \m_payload_i[62]_i_1__0\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \m_payload_i[63]_i_1__0\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \m_payload_i[64]_i_1__0\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__0\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__0\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__0\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__0\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[3]_i_2__0\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[5]_i_1__0\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \wrap_cnt_r[2]_i_1__0\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_1__0\ : label is "soft_lutpair14";
begin
Q(58 downto 0) <= \^q\(58 downto 0);
\axaddr_offset_r_reg[0]\ <= \^axaddr_offset_r_reg[0]\;
\axaddr_offset_r_reg[1]\ <= \^axaddr_offset_r_reg[1]\;
\axaddr_offset_r_reg[2]\ <= \^axaddr_offset_r_reg[2]\;
\axlen_cnt_reg[3]\ <= \^axlen_cnt_reg[3]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
next_pending_r_reg_0 <= \^next_pending_r_reg_0\;
s_axi_arready <= \^s_axi_arready\;
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
\wrap_cnt_r_reg[3]_0\ <= \^wrap_cnt_r_reg[3]_0\;
\wrap_second_len_r_reg[3]\(2 downto 0) <= \^wrap_second_len_r_reg[3]\(2 downto 0);
\aresetn_d_reg[1]_inv\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \aresetn_d_reg[0]_0\,
Q => \^m_valid_i_reg_0\,
R => '0'
);
\axaddr_incr[0]_i_10__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE100E1"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => \axaddr_incr_reg[3]_0\(0),
I3 => sel_first_2,
I4 => \axaddr_incr_reg[0]_i_11__0_n_7\,
O => \axaddr_incr[0]_i_10__0_n_0\
);
\axaddr_incr[0]_i_12__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"2A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[0]_i_12__0_n_0\
);
\axaddr_incr[0]_i_13__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
O => \axaddr_incr[0]_i_13__0_n_0\
);
\axaddr_incr[0]_i_14__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \^q\(0),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[0]_i_14__0_n_0\
);
\axaddr_incr[0]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first_2,
O => \axaddr_incr[0]_i_3__0_n_0\
);
\axaddr_incr[0]_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first_2,
O => \axaddr_incr[0]_i_4__0_n_0\
);
\axaddr_incr[0]_i_5__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => sel_first_2,
O => \axaddr_incr[0]_i_5__0_n_0\
);
\axaddr_incr[0]_i_6__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first_2,
O => \axaddr_incr[0]_i_6__0_n_0\
);
\axaddr_incr[0]_i_7__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF780078"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => \axaddr_incr_reg[3]_0\(3),
I3 => sel_first_2,
I4 => \axaddr_incr_reg[0]_i_11__0_n_4\,
O => \axaddr_incr[0]_i_7__0_n_0\
);
\axaddr_incr[0]_i_8__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD200D2"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => \axaddr_incr_reg[3]_0\(2),
I3 => sel_first_2,
I4 => \axaddr_incr_reg[0]_i_11__0_n_5\,
O => \axaddr_incr[0]_i_8__0_n_0\
);
\axaddr_incr[0]_i_9__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD200D2"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => \axaddr_incr_reg[3]_0\(1),
I3 => sel_first_2,
I4 => \axaddr_incr_reg[0]_i_11__0_n_6\,
O => \axaddr_incr[0]_i_9__0_n_0\
);
\axaddr_incr[4]_i_10__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(4),
O => \axaddr_incr[4]_i_10__0_n_0\
);
\axaddr_incr[4]_i_7__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(7),
O => \axaddr_incr[4]_i_7__0_n_0\
);
\axaddr_incr[4]_i_8__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(6),
O => \axaddr_incr[4]_i_8__0_n_0\
);
\axaddr_incr[4]_i_9__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(5),
O => \axaddr_incr[4]_i_9__0_n_0\
);
\axaddr_incr[8]_i_10__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(8),
O => \axaddr_incr[8]_i_10__0_n_0\
);
\axaddr_incr[8]_i_7__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(11),
O => \axaddr_incr[8]_i_7__0_n_0\
);
\axaddr_incr[8]_i_8__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(10),
O => \axaddr_incr[8]_i_8__0_n_0\
);
\axaddr_incr[8]_i_9__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(9),
O => \axaddr_incr[8]_i_9__0_n_0\
);
\axaddr_incr_reg[0]_i_11__0\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[0]_i_11__0_n_0\,
CO(2) => \axaddr_incr_reg[0]_i_11__0_n_1\,
CO(1) => \axaddr_incr_reg[0]_i_11__0_n_2\,
CO(0) => \axaddr_incr_reg[0]_i_11__0_n_3\,
CYINIT => '0',
DI(3) => \^q\(3),
DI(2) => \axaddr_incr[0]_i_12__0_n_0\,
DI(1) => \axaddr_incr[0]_i_13__0_n_0\,
DI(0) => \axaddr_incr[0]_i_14__0_n_0\,
O(3) => \axaddr_incr_reg[0]_i_11__0_n_4\,
O(2) => \axaddr_incr_reg[0]_i_11__0_n_5\,
O(1) => \axaddr_incr_reg[0]_i_11__0_n_6\,
O(0) => \axaddr_incr_reg[0]_i_11__0_n_7\,
S(3 downto 0) => \m_payload_i_reg[3]_0\(3 downto 0)
);
\axaddr_incr_reg[0]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[7]_0\(0),
CO(2) => \axaddr_incr_reg[0]_i_2__0_n_1\,
CO(1) => \axaddr_incr_reg[0]_i_2__0_n_2\,
CO(0) => \axaddr_incr_reg[0]_i_2__0_n_3\,
CYINIT => '0',
DI(3) => \axaddr_incr[0]_i_3__0_n_0\,
DI(2) => \axaddr_incr[0]_i_4__0_n_0\,
DI(1) => \axaddr_incr[0]_i_5__0_n_0\,
DI(0) => \axaddr_incr[0]_i_6__0_n_0\,
O(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
S(3) => \axaddr_incr[0]_i_7__0_n_0\,
S(2) => \axaddr_incr[0]_i_8__0_n_0\,
S(1) => \axaddr_incr[0]_i_9__0_n_0\,
S(0) => \axaddr_incr[0]_i_10__0_n_0\
);
\axaddr_incr_reg[4]_i_6__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[0]_i_11__0_n_0\,
CO(3) => \axaddr_incr_reg[4]_i_6__0_n_0\,
CO(2) => \axaddr_incr_reg[4]_i_6__0_n_1\,
CO(1) => \axaddr_incr_reg[4]_i_6__0_n_2\,
CO(0) => \axaddr_incr_reg[4]_i_6__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[7]\(3 downto 0),
S(3) => \axaddr_incr[4]_i_7__0_n_0\,
S(2) => \axaddr_incr[4]_i_8__0_n_0\,
S(1) => \axaddr_incr[4]_i_9__0_n_0\,
S(0) => \axaddr_incr[4]_i_10__0_n_0\
);
\axaddr_incr_reg[8]_i_6__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[4]_i_6__0_n_0\,
CO(3) => \NLW_axaddr_incr_reg[8]_i_6__0_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[8]_i_6__0_n_1\,
CO(1) => \axaddr_incr_reg[8]_i_6__0_n_2\,
CO(0) => \axaddr_incr_reg[8]_i_6__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[11]\(3 downto 0),
S(3) => \axaddr_incr[8]_i_7__0_n_0\,
S(2) => \axaddr_incr[8]_i_8__0_n_0\,
S(1) => \axaddr_incr[8]_i_9__0_n_0\,
S(0) => \axaddr_incr[8]_i_10__0_n_0\
);
\axaddr_offset_r[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0F0F0F0F088F0F0"
)
port map (
I0 => \axaddr_offset_r[0]_i_2__0_n_0\,
I1 => \^q\(39),
I2 => \axaddr_offset_r_reg[3]_1\(0),
I3 => \state_reg[1]\(1),
I4 => \^s_ready_i_reg_0\,
I5 => \state_reg[1]\(0),
O => \^axaddr_offset_r_reg[0]\
);
\axaddr_offset_r[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(35),
I3 => \^q\(2),
I4 => \^q\(36),
I5 => \^q\(0),
O => \axaddr_offset_r[0]_i_2__0_n_0\
);
\axaddr_offset_r[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AC00FFFFAC000000"
)
port map (
I0 => \axaddr_offset_r[2]_i_3__0_n_0\,
I1 => \axaddr_offset_r[1]_i_2__0_n_0\,
I2 => \^q\(35),
I3 => \^q\(40),
I4 => \state_reg[1]_rep\,
I5 => \axaddr_offset_r_reg[3]_1\(1),
O => \^axaddr_offset_r_reg[1]\
);
\axaddr_offset_r[1]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(3),
I1 => \^q\(36),
I2 => \^q\(1),
O => \axaddr_offset_r[1]_i_2__0_n_0\
);
\axaddr_offset_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AC00FFFFAC000000"
)
port map (
I0 => \axaddr_offset_r[2]_i_2__0_n_0\,
I1 => \axaddr_offset_r[2]_i_3__0_n_0\,
I2 => \^q\(35),
I3 => \^q\(41),
I4 => \state_reg[1]_rep\,
I5 => \axaddr_offset_r_reg[3]_1\(2),
O => \^axaddr_offset_r_reg[2]\
);
\axaddr_offset_r[2]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(3),
O => \axaddr_offset_r[2]_i_2__0_n_0\
);
\axaddr_offset_r[2]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(4),
I1 => \^q\(36),
I2 => \^q\(2),
O => \axaddr_offset_r[2]_i_3__0_n_0\
);
\axaddr_offset_r[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(6),
I1 => \^q\(4),
I2 => \^q\(35),
I3 => \^q\(5),
I4 => \^q\(36),
I5 => \^q\(3),
O => \axaddr_offset_r_reg[3]\
);
\axlen_cnt[3]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => \^q\(42),
I1 => \state_reg[0]_rep\,
I2 => \^s_ready_i_reg_0\,
I3 => \state_reg[1]_rep_0\,
O => \^axlen_cnt_reg[3]\
);
\m_axi_araddr[11]_INST_0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(37),
I1 => sel_first_2,
O => \m_axi_araddr[10]\
);
\m_payload_i[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => \m_payload_i[0]_i_1__0_n_0\
);
\m_payload_i[10]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(10),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => \m_payload_i[10]_i_1__0_n_0\
);
\m_payload_i[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(11),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => \m_payload_i[11]_i_1__0_n_0\
);
\m_payload_i[12]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(12),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => \m_payload_i[12]_i_1__0_n_0\
);
\m_payload_i[13]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(13),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => \m_payload_i[13]_i_1__1_n_0\
);
\m_payload_i[14]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(14),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => \m_payload_i[14]_i_1__0_n_0\
);
\m_payload_i[15]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(15),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => \m_payload_i[15]_i_1__0_n_0\
);
\m_payload_i[16]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(16),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => \m_payload_i[16]_i_1__0_n_0\
);
\m_payload_i[17]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(17),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => \m_payload_i[17]_i_1__0_n_0\
);
\m_payload_i[18]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(18),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => \m_payload_i[18]_i_1__0_n_0\
);
\m_payload_i[19]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(19),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => \m_payload_i[19]_i_1__0_n_0\
);
\m_payload_i[1]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => \m_payload_i[1]_i_1__0_n_0\
);
\m_payload_i[20]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(20),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => \m_payload_i[20]_i_1__0_n_0\
);
\m_payload_i[21]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(21),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => \m_payload_i[21]_i_1__0_n_0\
);
\m_payload_i[22]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(22),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => \m_payload_i[22]_i_1__0_n_0\
);
\m_payload_i[23]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(23),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => \m_payload_i[23]_i_1__0_n_0\
);
\m_payload_i[24]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(24),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => \m_payload_i[24]_i_1__0_n_0\
);
\m_payload_i[25]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(25),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => \m_payload_i[25]_i_1__0_n_0\
);
\m_payload_i[26]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(26),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => \m_payload_i[26]_i_1__0_n_0\
);
\m_payload_i[27]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(27),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => \m_payload_i[27]_i_1__0_n_0\
);
\m_payload_i[28]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(28),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => \m_payload_i[28]_i_1__0_n_0\
);
\m_payload_i[29]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(29),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => \m_payload_i[29]_i_1__0_n_0\
);
\m_payload_i[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => \m_payload_i[2]_i_1__0_n_0\
);
\m_payload_i[30]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(30),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => \m_payload_i[30]_i_1__0_n_0\
);
\m_payload_i[31]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(31),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => \m_payload_i[31]_i_2__0_n_0\
);
\m_payload_i[32]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => \m_payload_i[32]_i_1__0_n_0\
);
\m_payload_i[33]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => \m_payload_i[33]_i_1__0_n_0\
);
\m_payload_i[34]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => \m_payload_i[34]_i_1__0_n_0\
);
\m_payload_i[35]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arsize(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => \m_payload_i[35]_i_1__0_n_0\
);
\m_payload_i[36]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arsize(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => \m_payload_i[36]_i_1__0_n_0\
);
\m_payload_i[38]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arburst(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => \m_payload_i[38]_i_1__0_n_0\
);
\m_payload_i[39]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arburst(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => \m_payload_i[39]_i_1__0_n_0\
);
\m_payload_i[3]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(3),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => \m_payload_i[3]_i_1__0_n_0\
);
\m_payload_i[44]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => \m_payload_i[44]_i_1__0_n_0\
);
\m_payload_i[45]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => \m_payload_i[45]_i_1__0_n_0\
);
\m_payload_i[46]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => \m_payload_i[46]_i_1__1_n_0\
);
\m_payload_i[47]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(3),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[47]\,
O => \m_payload_i[47]_i_1__0_n_0\
);
\m_payload_i[48]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(4),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[48]\,
O => \m_payload_i[48]_i_1__0_n_0\
);
\m_payload_i[49]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(5),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[49]\,
O => \m_payload_i[49]_i_1__0_n_0\
);
\m_payload_i[4]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(4),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => \m_payload_i[4]_i_1__0_n_0\
);
\m_payload_i[50]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(6),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[50]\,
O => \m_payload_i[50]_i_1__0_n_0\
);
\m_payload_i[51]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(7),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[51]\,
O => \m_payload_i[51]_i_1__0_n_0\
);
\m_payload_i[53]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[53]\,
O => \m_payload_i[53]_i_1__0_n_0\
);
\m_payload_i[54]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[54]\,
O => \m_payload_i[54]_i_1__0_n_0\
);
\m_payload_i[55]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[55]\,
O => \m_payload_i[55]_i_1__0_n_0\
);
\m_payload_i[56]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(3),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[56]\,
O => \m_payload_i[56]_i_1__0_n_0\
);
\m_payload_i[57]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(4),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[57]\,
O => \m_payload_i[57]_i_1__0_n_0\
);
\m_payload_i[58]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(5),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[58]\,
O => \m_payload_i[58]_i_1__0_n_0\
);
\m_payload_i[59]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(6),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[59]\,
O => \m_payload_i[59]_i_1__0_n_0\
);
\m_payload_i[5]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(5),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => \m_payload_i[5]_i_1__0_n_0\
);
\m_payload_i[60]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(7),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[60]\,
O => \m_payload_i[60]_i_1__0_n_0\
);
\m_payload_i[61]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(8),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[61]\,
O => \m_payload_i[61]_i_1__0_n_0\
);
\m_payload_i[62]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(9),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[62]\,
O => \m_payload_i[62]_i_1__0_n_0\
);
\m_payload_i[63]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(10),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[63]\,
O => \m_payload_i[63]_i_1__0_n_0\
);
\m_payload_i[64]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(11),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[64]\,
O => \m_payload_i[64]_i_1__0_n_0\
);
\m_payload_i[6]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(6),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => \m_payload_i[6]_i_1__0_n_0\
);
\m_payload_i[7]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(7),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => \m_payload_i[7]_i_1__0_n_0\
);
\m_payload_i[8]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(8),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => \m_payload_i[8]_i_1__0_n_0\
);
\m_payload_i[9]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(9),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => \m_payload_i[9]_i_1__0_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[0]_i_1__0_n_0\,
Q => \^q\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[10]_i_1__0_n_0\,
Q => \^q\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[11]_i_1__0_n_0\,
Q => \^q\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[12]_i_1__0_n_0\,
Q => \^q\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[13]_i_1__1_n_0\,
Q => \^q\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[14]_i_1__0_n_0\,
Q => \^q\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[15]_i_1__0_n_0\,
Q => \^q\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[16]_i_1__0_n_0\,
Q => \^q\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[17]_i_1__0_n_0\,
Q => \^q\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[18]_i_1__0_n_0\,
Q => \^q\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[19]_i_1__0_n_0\,
Q => \^q\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[1]_i_1__0_n_0\,
Q => \^q\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[20]_i_1__0_n_0\,
Q => \^q\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[21]_i_1__0_n_0\,
Q => \^q\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[22]_i_1__0_n_0\,
Q => \^q\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[23]_i_1__0_n_0\,
Q => \^q\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[24]_i_1__0_n_0\,
Q => \^q\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[25]_i_1__0_n_0\,
Q => \^q\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[26]_i_1__0_n_0\,
Q => \^q\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[27]_i_1__0_n_0\,
Q => \^q\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[28]_i_1__0_n_0\,
Q => \^q\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[29]_i_1__0_n_0\,
Q => \^q\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[2]_i_1__0_n_0\,
Q => \^q\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[30]_i_1__0_n_0\,
Q => \^q\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[31]_i_2__0_n_0\,
Q => \^q\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[32]_i_1__0_n_0\,
Q => \^q\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[33]_i_1__0_n_0\,
Q => \^q\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[34]_i_1__0_n_0\,
Q => \^q\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[35]_i_1__0_n_0\,
Q => \^q\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[36]_i_1__0_n_0\,
Q => \^q\(36),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[38]_i_1__0_n_0\,
Q => \^q\(37),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[39]_i_1__0_n_0\,
Q => \^q\(38),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[3]_i_1__0_n_0\,
Q => \^q\(3),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[44]_i_1__0_n_0\,
Q => \^q\(39),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[45]_i_1__0_n_0\,
Q => \^q\(40),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[46]_i_1__1_n_0\,
Q => \^q\(41),
R => '0'
);
\m_payload_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[47]_i_1__0_n_0\,
Q => \^q\(42),
R => '0'
);
\m_payload_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[48]_i_1__0_n_0\,
Q => \^q\(43),
R => '0'
);
\m_payload_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[49]_i_1__0_n_0\,
Q => \^q\(44),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[4]_i_1__0_n_0\,
Q => \^q\(4),
R => '0'
);
\m_payload_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[50]_i_1__0_n_0\,
Q => \^q\(45),
R => '0'
);
\m_payload_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[51]_i_1__0_n_0\,
Q => \^q\(46),
R => '0'
);
\m_payload_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[53]_i_1__0_n_0\,
Q => \^q\(47),
R => '0'
);
\m_payload_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[54]_i_1__0_n_0\,
Q => \^q\(48),
R => '0'
);
\m_payload_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[55]_i_1__0_n_0\,
Q => \^q\(49),
R => '0'
);
\m_payload_i_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[56]_i_1__0_n_0\,
Q => \^q\(50),
R => '0'
);
\m_payload_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[57]_i_1__0_n_0\,
Q => \^q\(51),
R => '0'
);
\m_payload_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[58]_i_1__0_n_0\,
Q => \^q\(52),
R => '0'
);
\m_payload_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[59]_i_1__0_n_0\,
Q => \^q\(53),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[5]_i_1__0_n_0\,
Q => \^q\(5),
R => '0'
);
\m_payload_i_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[60]_i_1__0_n_0\,
Q => \^q\(54),
R => '0'
);
\m_payload_i_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[61]_i_1__0_n_0\,
Q => \^q\(55),
R => '0'
);
\m_payload_i_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[62]_i_1__0_n_0\,
Q => \^q\(56),
R => '0'
);
\m_payload_i_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[63]_i_1__0_n_0\,
Q => \^q\(57),
R => '0'
);
\m_payload_i_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[64]_i_1__0_n_0\,
Q => \^q\(58),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[6]_i_1__0_n_0\,
Q => \^q\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[7]_i_1__0_n_0\,
Q => \^q\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[8]_i_1__0_n_0\,
Q => \^q\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[9]_i_1__0_n_0\,
Q => \^q\(9),
R => '0'
);
\m_valid_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFFFBBBB"
)
port map (
I0 => s_axi_arvalid,
I1 => \^s_axi_arready\,
I2 => \state_reg[0]_rep\,
I3 => \state_reg[1]_rep_0\,
I4 => \^s_ready_i_reg_0\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^s_ready_i_reg_0\,
R => \^m_valid_i_reg_0\
);
\next_pending_r_i_2__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFD"
)
port map (
I0 => \^next_pending_r_reg_0\,
I1 => \^q\(46),
I2 => \^q\(44),
I3 => \^q\(45),
I4 => \^q\(43),
O => next_pending_r_reg
);
\next_pending_r_i_2__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \^q\(41),
I1 => \^q\(39),
I2 => \^q\(40),
I3 => \^q\(42),
O => \^next_pending_r_reg_0\
);
\s_ready_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F444FFFF"
)
port map (
I0 => s_axi_arvalid,
I1 => \^s_axi_arready\,
I2 => \state_reg[0]_rep\,
I3 => \state_reg[1]_rep_0\,
I4 => \^s_ready_i_reg_0\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^s_axi_arready\,
R => \aresetn_d_reg[0]\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arprot(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arprot(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arprot(2),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arsize(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arsize(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arburst(0),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arburst(1),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(0),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(1),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(2),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(3),
Q => \skid_buffer_reg_n_0_[47]\,
R => '0'
);
\skid_buffer_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(4),
Q => \skid_buffer_reg_n_0_[48]\,
R => '0'
);
\skid_buffer_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(5),
Q => \skid_buffer_reg_n_0_[49]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(6),
Q => \skid_buffer_reg_n_0_[50]\,
R => '0'
);
\skid_buffer_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(7),
Q => \skid_buffer_reg_n_0_[51]\,
R => '0'
);
\skid_buffer_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(0),
Q => \skid_buffer_reg_n_0_[53]\,
R => '0'
);
\skid_buffer_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(1),
Q => \skid_buffer_reg_n_0_[54]\,
R => '0'
);
\skid_buffer_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(2),
Q => \skid_buffer_reg_n_0_[55]\,
R => '0'
);
\skid_buffer_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(3),
Q => \skid_buffer_reg_n_0_[56]\,
R => '0'
);
\skid_buffer_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(4),
Q => \skid_buffer_reg_n_0_[57]\,
R => '0'
);
\skid_buffer_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(5),
Q => \skid_buffer_reg_n_0_[58]\,
R => '0'
);
\skid_buffer_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(6),
Q => \skid_buffer_reg_n_0_[59]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(7),
Q => \skid_buffer_reg_n_0_[60]\,
R => '0'
);
\skid_buffer_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(8),
Q => \skid_buffer_reg_n_0_[61]\,
R => '0'
);
\skid_buffer_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(9),
Q => \skid_buffer_reg_n_0_[62]\,
R => '0'
);
\skid_buffer_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(10),
Q => \skid_buffer_reg_n_0_[63]\,
R => '0'
);
\skid_buffer_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(11),
Q => \skid_buffer_reg_n_0_[64]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
\wrap_boundary_axaddr_r[0]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA8A"
)
port map (
I0 => \^q\(0),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(0)
);
\wrap_boundary_axaddr_r[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8A888AAA"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
I4 => \^q\(40),
O => \wrap_boundary_axaddr_r_reg[6]\(1)
);
\wrap_boundary_axaddr_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0A0202AAAAA202A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(40),
I2 => \^q\(35),
I3 => \^q\(41),
I4 => \^q\(36),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(2)
);
\wrap_boundary_axaddr_r[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"020202A2A2A202A2"
)
port map (
I0 => \^q\(3),
I1 => \wrap_boundary_axaddr_r[3]_i_2__0_n_0\,
I2 => \^q\(36),
I3 => \^q\(40),
I4 => \^q\(35),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(3)
);
\wrap_boundary_axaddr_r[3]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(41),
I1 => \^q\(35),
I2 => \^q\(42),
O => \wrap_boundary_axaddr_r[3]_i_2__0_n_0\
);
\wrap_boundary_axaddr_r[4]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"002A882A222AAA2A"
)
port map (
I0 => \^q\(4),
I1 => \^q\(35),
I2 => \^q\(42),
I3 => \^q\(36),
I4 => \^q\(40),
I5 => \^q\(41),
O => \wrap_boundary_axaddr_r_reg[6]\(4)
);
\wrap_boundary_axaddr_r[5]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"2A222AAA"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(41),
I3 => \^q\(35),
I4 => \^q\(42),
O => \wrap_boundary_axaddr_r_reg[6]\(5)
);
\wrap_boundary_axaddr_r[6]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"2AAA"
)
port map (
I0 => \^q\(6),
I1 => \^q\(36),
I2 => \^q\(42),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(6)
);
\wrap_cnt_r[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBABBCCCCC0CC"
)
port map (
I0 => \wrap_second_len_r[0]_i_2__0_n_0\,
I1 => \wrap_second_len_r_reg[3]_0\(0),
I2 => \state_reg[1]\(0),
I3 => \^s_ready_i_reg_0\,
I4 => \state_reg[1]\(1),
I5 => \wrap_second_len_r[0]_i_3__0_n_0\,
O => \wrap_cnt_r_reg[3]\(0)
);
\wrap_cnt_r[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(1),
I1 => \^wrap_cnt_r_reg[3]_0\,
I2 => wrap_second_len_1(0),
O => \wrap_cnt_r_reg[3]\(1)
);
\wrap_cnt_r[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A6AA"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(2),
I1 => wrap_second_len_1(0),
I2 => \^wrap_cnt_r_reg[3]_0\,
I3 => \^wrap_second_len_r_reg[3]\(1),
O => \wrap_cnt_r_reg[3]\(2)
);
\wrap_cnt_r[3]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAAB"
)
port map (
I0 => \wrap_cnt_r[3]_i_3__0_n_0\,
I1 => \^axaddr_offset_r_reg[1]\,
I2 => \^axaddr_offset_r_reg[0]\,
I3 => \axaddr_offset_r_reg[3]_0\(0),
I4 => \^axaddr_offset_r_reg[2]\,
O => \^wrap_cnt_r_reg[3]_0\
);
\wrap_cnt_r[3]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0F0F0F0F880F0F"
)
port map (
I0 => \axaddr_offset_r[0]_i_2__0_n_0\,
I1 => \^q\(39),
I2 => \wrap_second_len_r_reg[3]_0\(0),
I3 => \state_reg[1]\(1),
I4 => \^s_ready_i_reg_0\,
I5 => \state_reg[1]\(0),
O => \wrap_cnt_r[3]_i_3__0_n_0\
);
\wrap_second_len_r[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4444454444444044"
)
port map (
I0 => \wrap_second_len_r[0]_i_2__0_n_0\,
I1 => \wrap_second_len_r_reg[3]_0\(0),
I2 => \state_reg[1]\(0),
I3 => \^s_ready_i_reg_0\,
I4 => \state_reg[1]\(1),
I5 => \wrap_second_len_r[0]_i_3__0_n_0\,
O => \^wrap_second_len_r_reg[3]\(0)
);
\wrap_second_len_r[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAA8080000A808"
)
port map (
I0 => \wrap_second_len_r[0]_i_4__0_n_0\,
I1 => \^q\(0),
I2 => \^q\(36),
I3 => \^q\(2),
I4 => \^q\(35),
I5 => \axaddr_offset_r[1]_i_2__0_n_0\,
O => \wrap_second_len_r[0]_i_2__0_n_0\
);
\wrap_second_len_r[0]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFBA"
)
port map (
I0 => \^axaddr_offset_r_reg[2]\,
I1 => \state_reg[1]_rep\,
I2 => \axaddr_offset_r_reg[3]_1\(3),
I3 => \wrap_second_len_r[3]_i_2__0_n_0\,
I4 => \^axaddr_offset_r_reg[0]\,
I5 => \^axaddr_offset_r_reg[1]\,
O => \wrap_second_len_r[0]_i_3__0_n_0\
);
\wrap_second_len_r[0]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => \^q\(39),
I1 => \state_reg[1]\(0),
I2 => \^s_ready_i_reg_0\,
I3 => \state_reg[1]\(1),
O => \wrap_second_len_r[0]_i_4__0_n_0\
);
\wrap_second_len_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EE10FFFFEE100000"
)
port map (
I0 => \^axaddr_offset_r_reg[1]\,
I1 => \^axaddr_offset_r_reg[0]\,
I2 => \axaddr_offset_r_reg[3]_0\(0),
I3 => \^axaddr_offset_r_reg[2]\,
I4 => \state_reg[1]_rep\,
I5 => \wrap_second_len_r_reg[3]_0\(1),
O => \^wrap_second_len_r_reg[3]\(1)
);
\wrap_second_len_r[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFF444444444"
)
port map (
I0 => \state_reg[1]_rep\,
I1 => \wrap_second_len_r_reg[3]_0\(2),
I2 => \^axaddr_offset_r_reg[0]\,
I3 => \^axaddr_offset_r_reg[1]\,
I4 => \^axaddr_offset_r_reg[2]\,
I5 => \wrap_second_len_r[3]_i_2__0_n_0\,
O => \^wrap_second_len_r_reg[3]\(2)
);
\wrap_second_len_r[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EEE222E2"
)
port map (
I0 => \axaddr_offset_r[2]_i_2__0_n_0\,
I1 => \^q\(35),
I2 => \^q\(4),
I3 => \^q\(36),
I4 => \^q\(6),
I5 => \^axlen_cnt_reg[3]\,
O => \wrap_second_len_r[3]_i_2__0_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice_0 is
port (
s_axi_awready : out STD_LOGIC;
s_ready_i_reg_0 : out STD_LOGIC;
m_valid_i_reg_0 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 58 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
CO : out STD_LOGIC_VECTOR ( 0 to 0 );
O : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[3]\ : out STD_LOGIC;
\axaddr_offset_r_reg[1]\ : out STD_LOGIC;
\axaddr_offset_r_reg[0]\ : out STD_LOGIC;
\axaddr_offset_r_reg[2]\ : out STD_LOGIC;
\axlen_cnt_reg[3]\ : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
\axaddr_offset_r_reg[3]\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\m_axi_awaddr[10]\ : out STD_LOGIC;
\aresetn_d_reg[1]_inv\ : out STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[1]_inv_0\ : in STD_LOGIC;
aresetn : in STD_LOGIC;
\state_reg[0]_rep\ : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
b_push : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
S : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
wrap_second_len : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep_0\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
axaddr_incr_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice_0 : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice_0;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice_0 is
signal C : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 58 downto 0 );
signal \aresetn_d_reg_n_0_[0]\ : STD_LOGIC;
signal \axaddr_incr[0]_i_10_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_12_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_13_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_14_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_7_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_8_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_9_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_10_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_7_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_8_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_9_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_10_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_7_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_8_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_9_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6_n_3\ : STD_LOGIC;
signal \axaddr_offset_r[0]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[1]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_3_n_0\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[0]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[1]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[2]\ : STD_LOGIC;
signal \^axlen_cnt_reg[3]\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^next_pending_r_reg_0\ : STD_LOGIC;
signal \^s_axi_awready\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 64 downto 0 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[48]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[49]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[54]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[55]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[56]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[57]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[58]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[59]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[60]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[61]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[62]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[63]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[64]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r[3]_i_2_n_0\ : STD_LOGIC;
signal \wrap_cnt_r[3]_i_3_n_0\ : STD_LOGIC;
signal \^wrap_cnt_r_reg[3]\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_2_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_3_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_4_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[3]_i_2_n_0\ : STD_LOGIC;
signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_axaddr_incr_reg[8]_i_6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_offset_r[2]_i_2\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \axaddr_offset_r[2]_i_3\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \axlen_cnt[3]_i_2\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__0\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_2\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__0\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[47]_i_1\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[48]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[49]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_payload_i[50]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[51]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[53]_i_1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \m_payload_i[54]_i_1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \m_payload_i[55]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[56]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[57]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_payload_i[58]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_payload_i[59]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \m_payload_i[60]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_payload_i[61]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_payload_i[62]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_payload_i[63]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_payload_i[64]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[3]_i_2\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[5]_i_1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \wrap_cnt_r[2]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \wrap_second_len_r[0]_i_4\ : label is "soft_lutpair46";
begin
Q(58 downto 0) <= \^q\(58 downto 0);
\axaddr_offset_r_reg[0]\ <= \^axaddr_offset_r_reg[0]\;
\axaddr_offset_r_reg[1]\ <= \^axaddr_offset_r_reg[1]\;
\axaddr_offset_r_reg[2]\ <= \^axaddr_offset_r_reg[2]\;
\axlen_cnt_reg[3]\ <= \^axlen_cnt_reg[3]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
next_pending_r_reg_0 <= \^next_pending_r_reg_0\;
s_axi_awready <= \^s_axi_awready\;
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
\wrap_cnt_r_reg[3]\ <= \^wrap_cnt_r_reg[3]\;
\wrap_second_len_r_reg[3]\(2 downto 0) <= \^wrap_second_len_r_reg[3]\(2 downto 0);
\aresetn_d[1]_inv_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \aresetn_d_reg_n_0_[0]\,
I1 => aresetn,
O => \aresetn_d_reg[1]_inv\
);
\aresetn_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => aresetn,
Q => \aresetn_d_reg_n_0_[0]\,
R => '0'
);
\axaddr_incr[0]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE100E1"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => axaddr_incr_reg(0),
I3 => sel_first,
I4 => C(0),
O => \axaddr_incr[0]_i_10_n_0\
);
\axaddr_incr[0]_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"2A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[0]_i_12_n_0\
);
\axaddr_incr[0]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
O => \axaddr_incr[0]_i_13_n_0\
);
\axaddr_incr[0]_i_14\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \^q\(0),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[0]_i_14_n_0\
);
\axaddr_incr[0]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first,
O => \axaddr_incr[0]_i_3_n_0\
);
\axaddr_incr[0]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first,
O => \axaddr_incr[0]_i_4_n_0\
);
\axaddr_incr[0]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => sel_first,
O => \axaddr_incr[0]_i_5_n_0\
);
\axaddr_incr[0]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first,
O => \axaddr_incr[0]_i_6_n_0\
);
\axaddr_incr[0]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF780078"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => axaddr_incr_reg(3),
I3 => sel_first,
I4 => C(3),
O => \axaddr_incr[0]_i_7_n_0\
);
\axaddr_incr[0]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD200D2"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => axaddr_incr_reg(2),
I3 => sel_first,
I4 => C(2),
O => \axaddr_incr[0]_i_8_n_0\
);
\axaddr_incr[0]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD200D2"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => axaddr_incr_reg(1),
I3 => sel_first,
I4 => C(1),
O => \axaddr_incr[0]_i_9_n_0\
);
\axaddr_incr[4]_i_10\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(4),
O => \axaddr_incr[4]_i_10_n_0\
);
\axaddr_incr[4]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(7),
O => \axaddr_incr[4]_i_7_n_0\
);
\axaddr_incr[4]_i_8\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(6),
O => \axaddr_incr[4]_i_8_n_0\
);
\axaddr_incr[4]_i_9\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(5),
O => \axaddr_incr[4]_i_9_n_0\
);
\axaddr_incr[8]_i_10\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(8),
O => \axaddr_incr[8]_i_10_n_0\
);
\axaddr_incr[8]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(11),
O => \axaddr_incr[8]_i_7_n_0\
);
\axaddr_incr[8]_i_8\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(10),
O => \axaddr_incr[8]_i_8_n_0\
);
\axaddr_incr[8]_i_9\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(9),
O => \axaddr_incr[8]_i_9_n_0\
);
\axaddr_incr_reg[0]_i_11\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[0]_i_11_n_0\,
CO(2) => \axaddr_incr_reg[0]_i_11_n_1\,
CO(1) => \axaddr_incr_reg[0]_i_11_n_2\,
CO(0) => \axaddr_incr_reg[0]_i_11_n_3\,
CYINIT => '0',
DI(3) => \^q\(3),
DI(2) => \axaddr_incr[0]_i_12_n_0\,
DI(1) => \axaddr_incr[0]_i_13_n_0\,
DI(0) => \axaddr_incr[0]_i_14_n_0\,
O(3 downto 0) => C(3 downto 0),
S(3 downto 0) => S(3 downto 0)
);
\axaddr_incr_reg[0]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => CO(0),
CO(2) => \axaddr_incr_reg[0]_i_2_n_1\,
CO(1) => \axaddr_incr_reg[0]_i_2_n_2\,
CO(0) => \axaddr_incr_reg[0]_i_2_n_3\,
CYINIT => '0',
DI(3) => \axaddr_incr[0]_i_3_n_0\,
DI(2) => \axaddr_incr[0]_i_4_n_0\,
DI(1) => \axaddr_incr[0]_i_5_n_0\,
DI(0) => \axaddr_incr[0]_i_6_n_0\,
O(3 downto 0) => O(3 downto 0),
S(3) => \axaddr_incr[0]_i_7_n_0\,
S(2) => \axaddr_incr[0]_i_8_n_0\,
S(1) => \axaddr_incr[0]_i_9_n_0\,
S(0) => \axaddr_incr[0]_i_10_n_0\
);
\axaddr_incr_reg[4]_i_6\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[0]_i_11_n_0\,
CO(3) => \axaddr_incr_reg[4]_i_6_n_0\,
CO(2) => \axaddr_incr_reg[4]_i_6_n_1\,
CO(1) => \axaddr_incr_reg[4]_i_6_n_2\,
CO(0) => \axaddr_incr_reg[4]_i_6_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[11]\(3 downto 0),
S(3) => \axaddr_incr[4]_i_7_n_0\,
S(2) => \axaddr_incr[4]_i_8_n_0\,
S(1) => \axaddr_incr[4]_i_9_n_0\,
S(0) => \axaddr_incr[4]_i_10_n_0\
);
\axaddr_incr_reg[8]_i_6\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[4]_i_6_n_0\,
CO(3) => \NLW_axaddr_incr_reg[8]_i_6_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[8]_i_6_n_1\,
CO(1) => \axaddr_incr_reg[8]_i_6_n_2\,
CO(0) => \axaddr_incr_reg[8]_i_6_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[11]\(7 downto 4),
S(3) => \axaddr_incr[8]_i_7_n_0\,
S(2) => \axaddr_incr[8]_i_8_n_0\,
S(1) => \axaddr_incr[8]_i_9_n_0\,
S(0) => \axaddr_incr[8]_i_10_n_0\
);
\axaddr_offset_r[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0F0F0F0F088F0F0"
)
port map (
I0 => \axaddr_offset_r[0]_i_2_n_0\,
I1 => \^q\(39),
I2 => \axaddr_offset_r_reg[3]_1\(0),
I3 => \state_reg[1]\(1),
I4 => \^m_valid_i_reg_0\,
I5 => \state_reg[1]\(0),
O => \^axaddr_offset_r_reg[0]\
);
\axaddr_offset_r[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(35),
I3 => \^q\(2),
I4 => \^q\(36),
I5 => \^q\(0),
O => \axaddr_offset_r[0]_i_2_n_0\
);
\axaddr_offset_r[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AC00FFFFAC000000"
)
port map (
I0 => \axaddr_offset_r[2]_i_3_n_0\,
I1 => \axaddr_offset_r[1]_i_2_n_0\,
I2 => \^q\(35),
I3 => \^q\(40),
I4 => \state_reg[1]_rep_0\,
I5 => \axaddr_offset_r_reg[3]_1\(1),
O => \^axaddr_offset_r_reg[1]\
);
\axaddr_offset_r[1]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(3),
I1 => \^q\(36),
I2 => \^q\(1),
O => \axaddr_offset_r[1]_i_2_n_0\
);
\axaddr_offset_r[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AC00FFFFAC000000"
)
port map (
I0 => \axaddr_offset_r[2]_i_2_n_0\,
I1 => \axaddr_offset_r[2]_i_3_n_0\,
I2 => \^q\(35),
I3 => \^q\(41),
I4 => \state_reg[1]_rep_0\,
I5 => \axaddr_offset_r_reg[3]_1\(2),
O => \^axaddr_offset_r_reg[2]\
);
\axaddr_offset_r[2]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(3),
O => \axaddr_offset_r[2]_i_2_n_0\
);
\axaddr_offset_r[2]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(4),
I1 => \^q\(36),
I2 => \^q\(2),
O => \axaddr_offset_r[2]_i_3_n_0\
);
\axaddr_offset_r[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(6),
I1 => \^q\(4),
I2 => \^q\(35),
I3 => \^q\(5),
I4 => \^q\(36),
I5 => \^q\(3),
O => \axaddr_offset_r_reg[3]\
);
\axlen_cnt[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => \^q\(42),
I1 => \state_reg[0]_rep\,
I2 => \^m_valid_i_reg_0\,
I3 => \state_reg[1]_rep\,
O => \^axlen_cnt_reg[3]\
);
\m_axi_awaddr[11]_INST_0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(37),
I1 => sel_first,
O => \m_axi_awaddr[10]\
);
\m_payload_i[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\m_payload_i[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(10),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(11),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(12),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[13]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(13),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(14),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(15),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(16),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(17),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(18),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(19),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => skid_buffer(1)
);
\m_payload_i[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(20),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(21),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(22),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(23),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(24),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(25),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(26),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(27),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(28),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(29),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => skid_buffer(2)
);
\m_payload_i[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(30),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[31]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(31),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[32]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awprot(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[33]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awprot(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[34]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awprot(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awsize(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awsize(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[38]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awburst(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awburst(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(3),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[44]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i[47]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(3),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[47]\,
O => skid_buffer(47)
);
\m_payload_i[48]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(4),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[48]\,
O => skid_buffer(48)
);
\m_payload_i[49]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(5),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[49]\,
O => skid_buffer(49)
);
\m_payload_i[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(4),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[50]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(6),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[50]\,
O => skid_buffer(50)
);
\m_payload_i[51]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(7),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[51]\,
O => skid_buffer(51)
);
\m_payload_i[53]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[53]\,
O => skid_buffer(53)
);
\m_payload_i[54]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[54]\,
O => skid_buffer(54)
);
\m_payload_i[55]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[55]\,
O => skid_buffer(55)
);
\m_payload_i[56]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(3),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[56]\,
O => skid_buffer(56)
);
\m_payload_i[57]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(4),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[57]\,
O => skid_buffer(57)
);
\m_payload_i[58]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(5),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[58]\,
O => skid_buffer(58)
);
\m_payload_i[59]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(6),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[59]\,
O => skid_buffer(59)
);
\m_payload_i[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(5),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[60]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(7),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[60]\,
O => skid_buffer(60)
);
\m_payload_i[61]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(8),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[61]\,
O => skid_buffer(61)
);
\m_payload_i[62]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(9),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[62]\,
O => skid_buffer(62)
);
\m_payload_i[63]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(10),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[63]\,
O => skid_buffer(63)
);
\m_payload_i[64]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(11),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[64]\,
O => skid_buffer(64)
);
\m_payload_i[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(6),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(7),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(8),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(9),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(0),
Q => \^q\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(10),
Q => \^q\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(11),
Q => \^q\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(12),
Q => \^q\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(13),
Q => \^q\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(14),
Q => \^q\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(15),
Q => \^q\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(16),
Q => \^q\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(17),
Q => \^q\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(18),
Q => \^q\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(19),
Q => \^q\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(1),
Q => \^q\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(20),
Q => \^q\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(21),
Q => \^q\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(22),
Q => \^q\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(23),
Q => \^q\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(24),
Q => \^q\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(25),
Q => \^q\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(26),
Q => \^q\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(27),
Q => \^q\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(28),
Q => \^q\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(29),
Q => \^q\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(2),
Q => \^q\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(30),
Q => \^q\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(31),
Q => \^q\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(32),
Q => \^q\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(33),
Q => \^q\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(34),
Q => \^q\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(35),
Q => \^q\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(36),
Q => \^q\(36),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(38),
Q => \^q\(37),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(39),
Q => \^q\(38),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(3),
Q => \^q\(3),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(44),
Q => \^q\(39),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(45),
Q => \^q\(40),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(46),
Q => \^q\(41),
R => '0'
);
\m_payload_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(47),
Q => \^q\(42),
R => '0'
);
\m_payload_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(48),
Q => \^q\(43),
R => '0'
);
\m_payload_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(49),
Q => \^q\(44),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(4),
Q => \^q\(4),
R => '0'
);
\m_payload_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(50),
Q => \^q\(45),
R => '0'
);
\m_payload_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(51),
Q => \^q\(46),
R => '0'
);
\m_payload_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(53),
Q => \^q\(47),
R => '0'
);
\m_payload_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(54),
Q => \^q\(48),
R => '0'
);
\m_payload_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(55),
Q => \^q\(49),
R => '0'
);
\m_payload_i_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(56),
Q => \^q\(50),
R => '0'
);
\m_payload_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(57),
Q => \^q\(51),
R => '0'
);
\m_payload_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(58),
Q => \^q\(52),
R => '0'
);
\m_payload_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(59),
Q => \^q\(53),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(5),
Q => \^q\(5),
R => '0'
);
\m_payload_i_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(60),
Q => \^q\(54),
R => '0'
);
\m_payload_i_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(61),
Q => \^q\(55),
R => '0'
);
\m_payload_i_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(62),
Q => \^q\(56),
R => '0'
);
\m_payload_i_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(63),
Q => \^q\(57),
R => '0'
);
\m_payload_i_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(64),
Q => \^q\(58),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(6),
Q => \^q\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(7),
Q => \^q\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(8),
Q => \^q\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(9),
Q => \^q\(9),
R => '0'
);
\m_valid_i_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => b_push,
I1 => \^m_valid_i_reg_0\,
I2 => s_axi_awvalid,
I3 => \^s_axi_awready\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^m_valid_i_reg_0\,
R => \aresetn_d_reg[1]_inv_0\
);
next_pending_r_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \^next_pending_r_reg_0\,
I1 => \^q\(43),
I2 => \^q\(44),
I3 => \^q\(46),
I4 => \^q\(45),
O => next_pending_r_reg
);
\next_pending_r_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \^q\(41),
I1 => \^q\(39),
I2 => \^q\(40),
I3 => \^q\(42),
O => \^next_pending_r_reg_0\
);
\s_ready_i_i_1__1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \aresetn_d_reg_n_0_[0]\,
O => \^s_ready_i_reg_0\
);
s_ready_i_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"BFBB"
)
port map (
I0 => b_push,
I1 => \^m_valid_i_reg_0\,
I2 => s_axi_awvalid,
I3 => \^s_axi_awready\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^s_axi_awready\,
R => \^s_ready_i_reg_0\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awprot(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awprot(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awprot(2),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awsize(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awsize(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awburst(0),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awburst(1),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(0),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(1),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(2),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(3),
Q => \skid_buffer_reg_n_0_[47]\,
R => '0'
);
\skid_buffer_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(4),
Q => \skid_buffer_reg_n_0_[48]\,
R => '0'
);
\skid_buffer_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(5),
Q => \skid_buffer_reg_n_0_[49]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(6),
Q => \skid_buffer_reg_n_0_[50]\,
R => '0'
);
\skid_buffer_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(7),
Q => \skid_buffer_reg_n_0_[51]\,
R => '0'
);
\skid_buffer_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(0),
Q => \skid_buffer_reg_n_0_[53]\,
R => '0'
);
\skid_buffer_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(1),
Q => \skid_buffer_reg_n_0_[54]\,
R => '0'
);
\skid_buffer_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(2),
Q => \skid_buffer_reg_n_0_[55]\,
R => '0'
);
\skid_buffer_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(3),
Q => \skid_buffer_reg_n_0_[56]\,
R => '0'
);
\skid_buffer_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(4),
Q => \skid_buffer_reg_n_0_[57]\,
R => '0'
);
\skid_buffer_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(5),
Q => \skid_buffer_reg_n_0_[58]\,
R => '0'
);
\skid_buffer_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(6),
Q => \skid_buffer_reg_n_0_[59]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(7),
Q => \skid_buffer_reg_n_0_[60]\,
R => '0'
);
\skid_buffer_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(8),
Q => \skid_buffer_reg_n_0_[61]\,
R => '0'
);
\skid_buffer_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(9),
Q => \skid_buffer_reg_n_0_[62]\,
R => '0'
);
\skid_buffer_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(10),
Q => \skid_buffer_reg_n_0_[63]\,
R => '0'
);
\skid_buffer_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(11),
Q => \skid_buffer_reg_n_0_[64]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
\wrap_boundary_axaddr_r[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA8A"
)
port map (
I0 => \^q\(0),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(0)
);
\wrap_boundary_axaddr_r[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8A888AAA"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
I4 => \^q\(40),
O => \wrap_boundary_axaddr_r_reg[6]\(1)
);
\wrap_boundary_axaddr_r[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0A0202AAAAA202A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(40),
I2 => \^q\(35),
I3 => \^q\(41),
I4 => \^q\(36),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(2)
);
\wrap_boundary_axaddr_r[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"020202A2A2A202A2"
)
port map (
I0 => \^q\(3),
I1 => \wrap_boundary_axaddr_r[3]_i_2_n_0\,
I2 => \^q\(36),
I3 => \^q\(40),
I4 => \^q\(35),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(3)
);
\wrap_boundary_axaddr_r[3]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(41),
I1 => \^q\(35),
I2 => \^q\(42),
O => \wrap_boundary_axaddr_r[3]_i_2_n_0\
);
\wrap_boundary_axaddr_r[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"002A882A222AAA2A"
)
port map (
I0 => \^q\(4),
I1 => \^q\(35),
I2 => \^q\(42),
I3 => \^q\(36),
I4 => \^q\(40),
I5 => \^q\(41),
O => \wrap_boundary_axaddr_r_reg[6]\(4)
);
\wrap_boundary_axaddr_r[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"2A222AAA"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(41),
I3 => \^q\(35),
I4 => \^q\(42),
O => \wrap_boundary_axaddr_r_reg[6]\(5)
);
\wrap_boundary_axaddr_r[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2AAA"
)
port map (
I0 => \^q\(6),
I1 => \^q\(36),
I2 => \^q\(42),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(6)
);
\wrap_cnt_r[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBABBCCCCC0CC"
)
port map (
I0 => \wrap_second_len_r[0]_i_2_n_0\,
I1 => \wrap_second_len_r_reg[3]_0\(0),
I2 => \state_reg[1]\(0),
I3 => \^m_valid_i_reg_0\,
I4 => \state_reg[1]\(1),
I5 => \wrap_second_len_r[0]_i_3_n_0\,
O => D(0)
);
\wrap_cnt_r[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(1),
I1 => \^wrap_cnt_r_reg[3]\,
I2 => wrap_second_len(0),
O => D(1)
);
\wrap_cnt_r[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A6AA"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(2),
I1 => wrap_second_len(0),
I2 => \^wrap_cnt_r_reg[3]\,
I3 => \^wrap_second_len_r_reg[3]\(1),
O => D(2)
);
\wrap_cnt_r[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAAB"
)
port map (
I0 => \wrap_cnt_r[3]_i_3_n_0\,
I1 => \^axaddr_offset_r_reg[1]\,
I2 => \^axaddr_offset_r_reg[0]\,
I3 => \axaddr_offset_r_reg[3]_0\(0),
I4 => \^axaddr_offset_r_reg[2]\,
O => \^wrap_cnt_r_reg[3]\
);
\wrap_cnt_r[3]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0F0F0F0F880F0F"
)
port map (
I0 => \axaddr_offset_r[0]_i_2_n_0\,
I1 => \^q\(39),
I2 => \wrap_second_len_r_reg[3]_0\(0),
I3 => \state_reg[1]\(1),
I4 => \^m_valid_i_reg_0\,
I5 => \state_reg[1]\(0),
O => \wrap_cnt_r[3]_i_3_n_0\
);
\wrap_second_len_r[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4444454444444044"
)
port map (
I0 => \wrap_second_len_r[0]_i_2_n_0\,
I1 => \wrap_second_len_r_reg[3]_0\(0),
I2 => \state_reg[1]\(0),
I3 => \^m_valid_i_reg_0\,
I4 => \state_reg[1]\(1),
I5 => \wrap_second_len_r[0]_i_3_n_0\,
O => \^wrap_second_len_r_reg[3]\(0)
);
\wrap_second_len_r[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAA8080000A808"
)
port map (
I0 => \wrap_second_len_r[0]_i_4_n_0\,
I1 => \^q\(0),
I2 => \^q\(36),
I3 => \^q\(2),
I4 => \^q\(35),
I5 => \axaddr_offset_r[1]_i_2_n_0\,
O => \wrap_second_len_r[0]_i_2_n_0\
);
\wrap_second_len_r[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFBA"
)
port map (
I0 => \^axaddr_offset_r_reg[2]\,
I1 => \state_reg[1]_rep_0\,
I2 => \axaddr_offset_r_reg[3]_1\(3),
I3 => \wrap_second_len_r[3]_i_2_n_0\,
I4 => \^axaddr_offset_r_reg[0]\,
I5 => \^axaddr_offset_r_reg[1]\,
O => \wrap_second_len_r[0]_i_3_n_0\
);
\wrap_second_len_r[0]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => \^q\(39),
I1 => \state_reg[0]_rep\,
I2 => \^m_valid_i_reg_0\,
I3 => \state_reg[1]_rep\,
O => \wrap_second_len_r[0]_i_4_n_0\
);
\wrap_second_len_r[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EE10FFFFEE100000"
)
port map (
I0 => \^axaddr_offset_r_reg[1]\,
I1 => \^axaddr_offset_r_reg[0]\,
I2 => \axaddr_offset_r_reg[3]_0\(0),
I3 => \^axaddr_offset_r_reg[2]\,
I4 => \state_reg[1]_rep_0\,
I5 => \wrap_second_len_r_reg[3]_0\(1),
O => \^wrap_second_len_r_reg[3]\(1)
);
\wrap_second_len_r[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFF444444444"
)
port map (
I0 => \state_reg[1]_rep_0\,
I1 => \wrap_second_len_r_reg[3]_0\(2),
I2 => \^axaddr_offset_r_reg[0]\,
I3 => \^axaddr_offset_r_reg[1]\,
I4 => \^axaddr_offset_r_reg[2]\,
I5 => \wrap_second_len_r[3]_i_2_n_0\,
O => \^wrap_second_len_r_reg[3]\(2)
);
\wrap_second_len_r[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EEE222E2"
)
port map (
I0 => \axaddr_offset_r[2]_i_2_n_0\,
I1 => \^q\(35),
I2 => \^q\(4),
I3 => \^q\(36),
I4 => \^q\(6),
I5 => \^axlen_cnt_reg[3]\,
O => \wrap_second_len_r[3]_i_2_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ is
port (
s_axi_bvalid : out STD_LOGIC;
\skid_buffer_reg[0]_0\ : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]_inv\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
si_rs_bvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\s_bresp_acc_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ is
signal \m_payload_i[0]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[10]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_1__1_n_0\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal \^skid_buffer_reg[0]_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_payload_i[0]_i_1__1\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__1\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__1\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__1\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_2\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__1\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__1\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__1\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__1\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__1\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__1\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__1\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__1\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__1\ : label is "soft_lutpair80";
begin
s_axi_bvalid <= \^s_axi_bvalid\;
\skid_buffer_reg[0]_0\ <= \^skid_buffer_reg[0]_0\;
\m_payload_i[0]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \s_bresp_acc_reg[1]\(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => \m_payload_i[0]_i_1__1_n_0\
);
\m_payload_i[10]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(8),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => \m_payload_i[10]_i_1__1_n_0\
);
\m_payload_i[11]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(9),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => \m_payload_i[11]_i_1__1_n_0\
);
\m_payload_i[12]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(10),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => \m_payload_i[12]_i_1__1_n_0\
);
\m_payload_i[13]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
O => p_1_in
);
\m_payload_i[13]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(11),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => \m_payload_i[13]_i_2_n_0\
);
\m_payload_i[1]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \s_bresp_acc_reg[1]\(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => \m_payload_i[1]_i_1__1_n_0\
);
\m_payload_i[2]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => \m_payload_i[2]_i_1__1_n_0\
);
\m_payload_i[3]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => \m_payload_i[3]_i_1__1_n_0\
);
\m_payload_i[4]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(2),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => \m_payload_i[4]_i_1__1_n_0\
);
\m_payload_i[5]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(3),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => \m_payload_i[5]_i_1__1_n_0\
);
\m_payload_i[6]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(4),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => \m_payload_i[6]_i_1__1_n_0\
);
\m_payload_i[7]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(5),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => \m_payload_i[7]_i_1__1_n_0\
);
\m_payload_i[8]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(6),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => \m_payload_i[8]_i_1__1_n_0\
);
\m_payload_i[9]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(7),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => \m_payload_i[9]_i_1__1_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[0]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[10]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[11]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[12]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[13]_i_2_n_0\,
Q => \s_axi_bid[11]\(13),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[1]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(1),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[2]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(2),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[3]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(3),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[4]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[5]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[6]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[7]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[8]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[9]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(9),
R => '0'
);
m_valid_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
I2 => si_rs_bvalid,
I3 => \^skid_buffer_reg[0]_0\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^s_axi_bvalid\,
R => \aresetn_d_reg[1]_inv\
);
s_ready_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => si_rs_bvalid,
I1 => \^skid_buffer_reg[0]_0\,
I2 => s_axi_bready,
I3 => \^s_axi_bvalid\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^skid_buffer_reg[0]_0\,
R => \aresetn_d_reg[0]\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \s_bresp_acc_reg[1]\(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(8),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(9),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(10),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(11),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \s_bresp_acc_reg[1]\(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(0),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(1),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(2),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(3),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(4),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(5),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(6),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(7),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ is
port (
s_axi_rvalid : out STD_LOGIC;
\skid_buffer_reg[0]_0\ : out STD_LOGIC;
\cnt_read_reg[3]_rep__0\ : out STD_LOGIC;
\s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\aresetn_d_reg[1]_inv\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
\cnt_read_reg[4]_rep__0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
r_push_r_reg : in STD_LOGIC_VECTOR ( 12 downto 0 );
\cnt_read_reg[4]\ : in STD_LOGIC_VECTOR ( 33 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ is
signal \m_payload_i[0]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[10]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[14]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[15]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[16]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[17]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[18]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[19]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[20]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[21]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[22]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[23]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[24]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[25]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[26]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[27]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[28]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[29]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[30]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[31]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[32]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[33]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[34]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[35]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[36]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[37]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[38]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[39]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[40]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[41]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[42]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[43]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[44]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[45]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[46]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_1__2_n_0\ : STD_LOGIC;
signal \m_valid_i_i_1__1_n_0\ : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
signal \s_ready_i_i_1__2_n_0\ : STD_LOGIC;
signal \^skid_buffer_reg[0]_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[3]_i_2\ : label is "soft_lutpair85";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__2\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__2\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__2\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__2\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__1\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__1\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__1\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__1\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__1\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__1\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__2\ : label is "soft_lutpair108";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__1\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__1\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__1\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__1\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__1\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__1\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__1\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__1\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__1\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__1\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__2\ : label is "soft_lutpair108";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__1\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__1\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__1\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__1\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__1\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__1\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__1\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__1\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__1\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__2\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__1\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__1\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_2\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__2\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__2\ : label is "soft_lutpair106";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__2\ : label is "soft_lutpair106";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__2\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__2\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__2\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \m_valid_i_i_1__1\ : label is "soft_lutpair85";
begin
s_axi_rvalid <= \^s_axi_rvalid\;
\skid_buffer_reg[0]_0\ <= \^skid_buffer_reg[0]_0\;
\cnt_read[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^skid_buffer_reg[0]_0\,
I1 => \cnt_read_reg[4]_rep__0\,
O => \cnt_read_reg[3]_rep__0\
);
\m_payload_i[0]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => \m_payload_i[0]_i_1__2_n_0\
);
\m_payload_i[10]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(10),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => \m_payload_i[10]_i_1__2_n_0\
);
\m_payload_i[11]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(11),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => \m_payload_i[11]_i_1__2_n_0\
);
\m_payload_i[12]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(12),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => \m_payload_i[12]_i_1__2_n_0\
);
\m_payload_i[13]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(13),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => \m_payload_i[13]_i_1__2_n_0\
);
\m_payload_i[14]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(14),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => \m_payload_i[14]_i_1__1_n_0\
);
\m_payload_i[15]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(15),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => \m_payload_i[15]_i_1__1_n_0\
);
\m_payload_i[16]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(16),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => \m_payload_i[16]_i_1__1_n_0\
);
\m_payload_i[17]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(17),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => \m_payload_i[17]_i_1__1_n_0\
);
\m_payload_i[18]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(18),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => \m_payload_i[18]_i_1__1_n_0\
);
\m_payload_i[19]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(19),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => \m_payload_i[19]_i_1__1_n_0\
);
\m_payload_i[1]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => \m_payload_i[1]_i_1__2_n_0\
);
\m_payload_i[20]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(20),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => \m_payload_i[20]_i_1__1_n_0\
);
\m_payload_i[21]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(21),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => \m_payload_i[21]_i_1__1_n_0\
);
\m_payload_i[22]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(22),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => \m_payload_i[22]_i_1__1_n_0\
);
\m_payload_i[23]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(23),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => \m_payload_i[23]_i_1__1_n_0\
);
\m_payload_i[24]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(24),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => \m_payload_i[24]_i_1__1_n_0\
);
\m_payload_i[25]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(25),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => \m_payload_i[25]_i_1__1_n_0\
);
\m_payload_i[26]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(26),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => \m_payload_i[26]_i_1__1_n_0\
);
\m_payload_i[27]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(27),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => \m_payload_i[27]_i_1__1_n_0\
);
\m_payload_i[28]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(28),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => \m_payload_i[28]_i_1__1_n_0\
);
\m_payload_i[29]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(29),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => \m_payload_i[29]_i_1__1_n_0\
);
\m_payload_i[2]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(2),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => \m_payload_i[2]_i_1__2_n_0\
);
\m_payload_i[30]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(30),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => \m_payload_i[30]_i_1__1_n_0\
);
\m_payload_i[31]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(31),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => \m_payload_i[31]_i_1__1_n_0\
);
\m_payload_i[32]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(32),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => \m_payload_i[32]_i_1__1_n_0\
);
\m_payload_i[33]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(33),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => \m_payload_i[33]_i_1__1_n_0\
);
\m_payload_i[34]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => \m_payload_i[34]_i_1__1_n_0\
);
\m_payload_i[35]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => \m_payload_i[35]_i_1__1_n_0\
);
\m_payload_i[36]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(2),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => \m_payload_i[36]_i_1__1_n_0\
);
\m_payload_i[37]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(3),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => \m_payload_i[37]_i_1_n_0\
);
\m_payload_i[38]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(4),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => \m_payload_i[38]_i_1__1_n_0\
);
\m_payload_i[39]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(5),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => \m_payload_i[39]_i_1__1_n_0\
);
\m_payload_i[3]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(3),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => \m_payload_i[3]_i_1__2_n_0\
);
\m_payload_i[40]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(6),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => \m_payload_i[40]_i_1_n_0\
);
\m_payload_i[41]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(7),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => \m_payload_i[41]_i_1_n_0\
);
\m_payload_i[42]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(8),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => \m_payload_i[42]_i_1_n_0\
);
\m_payload_i[43]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(9),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => \m_payload_i[43]_i_1_n_0\
);
\m_payload_i[44]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(10),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => \m_payload_i[44]_i_1__1_n_0\
);
\m_payload_i[45]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(11),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => \m_payload_i[45]_i_1__1_n_0\
);
\m_payload_i[46]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
O => p_1_in
);
\m_payload_i[46]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(12),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => \m_payload_i[46]_i_2_n_0\
);
\m_payload_i[4]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(4),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => \m_payload_i[4]_i_1__2_n_0\
);
\m_payload_i[5]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(5),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => \m_payload_i[5]_i_1__2_n_0\
);
\m_payload_i[6]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(6),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => \m_payload_i[6]_i_1__2_n_0\
);
\m_payload_i[7]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(7),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => \m_payload_i[7]_i_1__2_n_0\
);
\m_payload_i[8]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(8),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => \m_payload_i[8]_i_1__2_n_0\
);
\m_payload_i[9]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(9),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => \m_payload_i[9]_i_1__2_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[0]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[10]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[11]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[12]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[13]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[14]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[15]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[16]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[17]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[18]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[19]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[1]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[20]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[21]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[22]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[23]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[24]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[25]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[26]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[27]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[28]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[29]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[2]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[30]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[31]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[32]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[33]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[34]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[35]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[36]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(36),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[37]_i_1_n_0\,
Q => \s_axi_rid[11]\(37),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[38]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(38),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[39]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(39),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[3]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(3),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[40]_i_1_n_0\,
Q => \s_axi_rid[11]\(40),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[41]_i_1_n_0\,
Q => \s_axi_rid[11]\(41),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[42]_i_1_n_0\,
Q => \s_axi_rid[11]\(42),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[43]_i_1_n_0\,
Q => \s_axi_rid[11]\(43),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[44]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(44),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[45]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(45),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[46]_i_2_n_0\,
Q => \s_axi_rid[11]\(46),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[4]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[5]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[6]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[7]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[8]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[9]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(9),
R => '0'
);
\m_valid_i_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4FFF"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
I2 => \cnt_read_reg[4]_rep__0\,
I3 => \^skid_buffer_reg[0]_0\,
O => \m_valid_i_i_1__1_n_0\
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_valid_i_i_1__1_n_0\,
Q => \^s_axi_rvalid\,
R => \aresetn_d_reg[1]_inv\
);
\s_ready_i_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F8FF"
)
port map (
I0 => \cnt_read_reg[4]_rep__0\,
I1 => \^skid_buffer_reg[0]_0\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
O => \s_ready_i_i_1__2_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__2_n_0\,
Q => \^skid_buffer_reg[0]_0\,
R => \aresetn_d_reg[0]\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(32),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(33),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(0),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(1),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(2),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(3),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(4),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(5),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(6),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(7),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(8),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(9),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(10),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(11),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(12),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_b_channel is
port (
si_rs_bvalid : out STD_LOGIC;
\cnt_read_reg[0]_rep__0\ : out STD_LOGIC;
\cnt_read_reg[1]_rep__1\ : out STD_LOGIC;
m_axi_bready : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
\skid_buffer_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
areset_d1 : in STD_LOGIC;
aclk : in STD_LOGIC;
b_push : in STD_LOGIC;
si_rs_bready : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 19 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_b_channel;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_b_channel is
signal bid_fifo_0_n_2 : STD_LOGIC;
signal bid_fifo_0_n_3 : STD_LOGIC;
signal bid_fifo_0_n_6 : STD_LOGIC;
signal \bresp_cnt[7]_i_3_n_0\ : STD_LOGIC;
signal \bresp_cnt_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal bresp_push : STD_LOGIC;
signal cnt_read : STD_LOGIC_VECTOR ( 1 downto 0 );
signal mhandshake : STD_LOGIC;
signal mhandshake_r : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s_bresp_acc0 : STD_LOGIC;
signal \s_bresp_acc[0]_i_1_n_0\ : STD_LOGIC;
signal \s_bresp_acc[1]_i_1_n_0\ : STD_LOGIC;
signal \s_bresp_acc_reg_n_0_[0]\ : STD_LOGIC;
signal \s_bresp_acc_reg_n_0_[1]\ : STD_LOGIC;
signal shandshake : STD_LOGIC;
signal shandshake_r : STD_LOGIC;
signal \^si_rs_bvalid\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \bresp_cnt[1]_i_1\ : label is "soft_lutpair121";
attribute SOFT_HLUTNM of \bresp_cnt[2]_i_1\ : label is "soft_lutpair121";
attribute SOFT_HLUTNM of \bresp_cnt[3]_i_1\ : label is "soft_lutpair119";
attribute SOFT_HLUTNM of \bresp_cnt[4]_i_1\ : label is "soft_lutpair119";
attribute SOFT_HLUTNM of \bresp_cnt[6]_i_1\ : label is "soft_lutpair120";
attribute SOFT_HLUTNM of \bresp_cnt[7]_i_2\ : label is "soft_lutpair120";
begin
si_rs_bvalid <= \^si_rs_bvalid\;
bid_fifo_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo
port map (
D(0) => bid_fifo_0_n_2,
Q(1 downto 0) => cnt_read(1 downto 0),
SR(0) => s_bresp_acc0,
aclk => aclk,
areset_d1 => areset_d1,
b_push => b_push,
\bresp_cnt_reg[7]\(7 downto 0) => \bresp_cnt_reg__0\(7 downto 0),
bvalid_i_reg => bid_fifo_0_n_6,
bvalid_i_reg_0 => \^si_rs_bvalid\,
\cnt_read_reg[0]_0\ => bid_fifo_0_n_3,
\cnt_read_reg[0]_rep__0_0\ => \cnt_read_reg[0]_rep__0\,
\cnt_read_reg[1]_rep__1_0\ => \cnt_read_reg[1]_rep__1\,
\in\(19 downto 0) => \in\(19 downto 0),
mhandshake_r => mhandshake_r,
\out\(11 downto 0) => \out\(11 downto 0),
sel => bresp_push,
shandshake_r => shandshake_r,
si_rs_bready => si_rs_bready
);
\bresp_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \bresp_cnt_reg__0\(0),
O => p_0_in(0)
);
\bresp_cnt[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \bresp_cnt_reg__0\(1),
I1 => \bresp_cnt_reg__0\(0),
O => p_0_in(1)
);
\bresp_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \bresp_cnt_reg__0\(2),
I1 => \bresp_cnt_reg__0\(0),
I2 => \bresp_cnt_reg__0\(1),
O => p_0_in(2)
);
\bresp_cnt[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \bresp_cnt_reg__0\(3),
I1 => \bresp_cnt_reg__0\(1),
I2 => \bresp_cnt_reg__0\(0),
I3 => \bresp_cnt_reg__0\(2),
O => p_0_in(3)
);
\bresp_cnt[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \bresp_cnt_reg__0\(4),
I1 => \bresp_cnt_reg__0\(2),
I2 => \bresp_cnt_reg__0\(0),
I3 => \bresp_cnt_reg__0\(1),
I4 => \bresp_cnt_reg__0\(3),
O => p_0_in(4)
);
\bresp_cnt[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \bresp_cnt_reg__0\(5),
I1 => \bresp_cnt_reg__0\(3),
I2 => \bresp_cnt_reg__0\(1),
I3 => \bresp_cnt_reg__0\(0),
I4 => \bresp_cnt_reg__0\(2),
I5 => \bresp_cnt_reg__0\(4),
O => p_0_in(5)
);
\bresp_cnt[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \bresp_cnt_reg__0\(6),
I1 => \bresp_cnt[7]_i_3_n_0\,
O => p_0_in(6)
);
\bresp_cnt[7]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \bresp_cnt_reg__0\(7),
I1 => \bresp_cnt[7]_i_3_n_0\,
I2 => \bresp_cnt_reg__0\(6),
O => p_0_in(7)
);
\bresp_cnt[7]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \bresp_cnt_reg__0\(5),
I1 => \bresp_cnt_reg__0\(3),
I2 => \bresp_cnt_reg__0\(1),
I3 => \bresp_cnt_reg__0\(0),
I4 => \bresp_cnt_reg__0\(2),
I5 => \bresp_cnt_reg__0\(4),
O => \bresp_cnt[7]_i_3_n_0\
);
\bresp_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(0),
Q => \bresp_cnt_reg__0\(0),
R => s_bresp_acc0
);
\bresp_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(1),
Q => \bresp_cnt_reg__0\(1),
R => s_bresp_acc0
);
\bresp_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(2),
Q => \bresp_cnt_reg__0\(2),
R => s_bresp_acc0
);
\bresp_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(3),
Q => \bresp_cnt_reg__0\(3),
R => s_bresp_acc0
);
\bresp_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(4),
Q => \bresp_cnt_reg__0\(4),
R => s_bresp_acc0
);
\bresp_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(5),
Q => \bresp_cnt_reg__0\(5),
R => s_bresp_acc0
);
\bresp_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(6),
Q => \bresp_cnt_reg__0\(6),
R => s_bresp_acc0
);
\bresp_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(7),
Q => \bresp_cnt_reg__0\(7),
R => s_bresp_acc0
);
bresp_fifo_0: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\
port map (
D(0) => bid_fifo_0_n_2,
Q(1 downto 0) => cnt_read(1 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\bresp_cnt_reg[3]\ => bid_fifo_0_n_3,
\in\(1) => \s_bresp_acc_reg_n_0_[1]\,
\in\(0) => \s_bresp_acc_reg_n_0_[0]\,
m_axi_bready => m_axi_bready,
m_axi_bvalid => m_axi_bvalid,
mhandshake => mhandshake,
mhandshake_r => mhandshake_r,
sel => bresp_push,
shandshake_r => shandshake_r,
\skid_buffer_reg[1]\(1 downto 0) => \skid_buffer_reg[1]\(1 downto 0)
);
bvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => bid_fifo_0_n_6,
Q => \^si_rs_bvalid\,
R => '0'
);
mhandshake_r_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => mhandshake,
Q => mhandshake_r,
R => areset_d1
);
\s_bresp_acc[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EACEAAAA"
)
port map (
I0 => \s_bresp_acc_reg_n_0_[0]\,
I1 => m_axi_bresp(0),
I2 => m_axi_bresp(1),
I3 => \s_bresp_acc_reg_n_0_[1]\,
I4 => mhandshake,
I5 => s_bresp_acc0,
O => \s_bresp_acc[0]_i_1_n_0\
);
\s_bresp_acc[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00EC"
)
port map (
I0 => m_axi_bresp(1),
I1 => \s_bresp_acc_reg_n_0_[1]\,
I2 => mhandshake,
I3 => s_bresp_acc0,
O => \s_bresp_acc[1]_i_1_n_0\
);
\s_bresp_acc_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \s_bresp_acc[0]_i_1_n_0\,
Q => \s_bresp_acc_reg_n_0_[0]\,
R => '0'
);
\s_bresp_acc_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \s_bresp_acc[1]_i_1_n_0\,
Q => \s_bresp_acc_reg_n_0_[1]\,
R => '0'
);
shandshake_r_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^si_rs_bvalid\,
I1 => si_rs_bready,
O => shandshake
);
shandshake_r_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => shandshake,
Q => shandshake_r,
R => areset_d1
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator is
port (
next_pending_r_reg : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC;
\sel_first__0\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axlen_cnt_reg[7]\ : out STD_LOGIC;
\state_reg[1]_rep\ : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
next_pending_r_reg_2 : out STD_LOGIC;
\axlen_cnt_reg[4]\ : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
wrap_next_pending : in STD_LOGIC;
sel_first_i : in STD_LOGIC;
\m_payload_i_reg[39]\ : in STD_LOGIC;
\m_payload_i_reg[39]_0\ : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_reg_2 : in STD_LOGIC;
sel_first_reg_3 : in STD_LOGIC;
\state_reg[0]\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[51]\ : in STD_LOGIC_VECTOR ( 21 downto 0 );
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
\next\ : in STD_LOGIC;
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\state_reg[0]_rep\ : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator is
signal axaddr_incr_reg : STD_LOGIC_VECTOR ( 11 downto 4 );
signal \^axaddr_incr_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr_reg_11__s_net_1\ : STD_LOGIC;
signal incr_cmd_0_n_21 : STD_LOGIC;
signal s_axburst_eq0 : STD_LOGIC;
signal s_axburst_eq1 : STD_LOGIC;
begin
\axaddr_incr_reg[11]\ <= \axaddr_incr_reg_11__s_net_1\;
\axaddr_incr_reg[3]\(3 downto 0) <= \^axaddr_incr_reg[3]\(3 downto 0);
incr_cmd_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd
port map (
CO(0) => CO(0),
D(3 downto 0) => D(3 downto 0),
E(0) => E(0),
O(3 downto 0) => O(3 downto 0),
Q(3 downto 0) => Q(3 downto 0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
axaddr_incr_reg(7 downto 0) => axaddr_incr_reg(11 downto 4),
\axaddr_incr_reg[11]_0\ => \axaddr_incr_reg_11__s_net_1\,
\axaddr_incr_reg[3]_0\(3 downto 0) => \^axaddr_incr_reg[3]\(3 downto 0),
\axlen_cnt_reg[4]_0\ => \axlen_cnt_reg[4]\,
\axlen_cnt_reg[7]_0\ => \axlen_cnt_reg[7]\,
incr_next_pending => incr_next_pending,
\m_axi_awaddr[1]\ => incr_cmd_0_n_21,
\m_payload_i_reg[11]\(7 downto 0) => \m_payload_i_reg[11]\(7 downto 0),
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[51]\(9 downto 8) => \m_payload_i_reg[51]\(21 downto 20),
\m_payload_i_reg[51]\(7) => \m_payload_i_reg[51]\(18),
\m_payload_i_reg[51]\(6 downto 4) => \m_payload_i_reg[51]\(14 downto 12),
\m_payload_i_reg[51]\(3 downto 0) => \m_payload_i_reg[51]\(3 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
next_pending_r_reg_0 => next_pending_r_reg,
next_pending_r_reg_1 => next_pending_r_reg_1,
sel_first_reg_0 => sel_first_reg_1,
sel_first_reg_1 => sel_first_reg_2,
\state_reg[0]\ => \state_reg[0]\,
\state_reg[0]_rep\ => \state_reg[0]_rep\,
\state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0)
);
\memory_reg[3][0]_srl4_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axburst_eq1,
I1 => \m_payload_i_reg[51]\(15),
I2 => s_axburst_eq0,
O => \state_reg[1]_rep\
);
s_axburst_eq0_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]\,
Q => s_axburst_eq0,
R => '0'
);
s_axburst_eq1_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]_0\,
Q => s_axburst_eq1,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_i,
Q => sel_first_reg_0,
R => '0'
);
wrap_cmd_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd
port map (
E(0) => E(0),
aclk => aclk,
axaddr_incr_reg(7 downto 0) => axaddr_incr_reg(11 downto 4),
\axaddr_incr_reg[3]\(2 downto 1) => \^axaddr_incr_reg[3]\(3 downto 2),
\axaddr_incr_reg[3]\(0) => \^axaddr_incr_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]_1\(3 downto 0) => \axaddr_offset_r_reg[3]_0\(3 downto 0),
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
\m_payload_i_reg[38]\ => \m_payload_i_reg[38]\,
\m_payload_i_reg[47]\(18 downto 14) => \m_payload_i_reg[51]\(19 downto 15),
\m_payload_i_reg[47]\(13 downto 0) => \m_payload_i_reg[51]\(13 downto 0),
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
\next\ => \next\,
next_pending_r_reg_0 => next_pending_r_reg_0,
next_pending_r_reg_1 => next_pending_r_reg_2,
sel_first_reg_0 => \sel_first__0\,
sel_first_reg_1 => sel_first_reg_3,
sel_first_reg_2 => incr_cmd_0_n_21,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0),
\wrap_second_len_r_reg[3]_1\(3 downto 0) => \wrap_second_len_r_reg[3]_0\(3 downto 0),
\wrap_second_len_r_reg[3]_2\(3 downto 0) => \wrap_second_len_r_reg[3]_1\(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1 is
port (
next_pending_r_reg : out STD_LOGIC;
wrap_next_pending : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC;
sel_first_reg_1 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
next_pending_r_reg_0 : out STD_LOGIC;
r_rlast : out STD_LOGIC;
\state_reg[0]_rep\ : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_i : in STD_LOGIC;
\m_payload_i_reg[39]\ : in STD_LOGIC;
\m_payload_i_reg[39]_0\ : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_reg_3 : in STD_LOGIC;
sel_first_reg_4 : in STD_LOGIC;
\state_reg[0]\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[51]\ : in STD_LOGIC_VECTOR ( 23 downto 0 );
\state_reg[0]_rep_0\ : in STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[46]\ : in STD_LOGIC;
\state_reg[1]_rep_0\ : in STD_LOGIC;
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 1 downto 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1 : entity is "axi_protocol_converter_v2_1_13_b2s_cmd_translator";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1 is
signal axaddr_incr_reg : STD_LOGIC_VECTOR ( 11 downto 4 );
signal \^axaddr_incr_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr_reg_11__s_net_1\ : STD_LOGIC;
signal incr_cmd_0_n_16 : STD_LOGIC;
signal incr_cmd_0_n_17 : STD_LOGIC;
signal s_axburst_eq0 : STD_LOGIC;
signal s_axburst_eq1 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of r_rlast_r_i_1 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \state[1]_i_3\ : label is "soft_lutpair5";
begin
\axaddr_incr_reg[11]\ <= \axaddr_incr_reg_11__s_net_1\;
\axaddr_incr_reg[3]\(3 downto 0) <= \^axaddr_incr_reg[3]\(3 downto 0);
incr_cmd_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2
port map (
CO(0) => CO(0),
D(1 downto 0) => D(1 downto 0),
E(0) => E(0),
O(3 downto 0) => O(3 downto 0),
Q(1 downto 0) => Q(1 downto 0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
\axaddr_incr_reg[11]_0\(6 downto 1) => axaddr_incr_reg(11 downto 6),
\axaddr_incr_reg[11]_0\(0) => axaddr_incr_reg(4),
\axaddr_incr_reg[11]_1\ => \axaddr_incr_reg_11__s_net_1\,
\axaddr_incr_reg[3]_0\(3 downto 0) => \^axaddr_incr_reg[3]\(3 downto 0),
incr_next_pending => incr_next_pending,
\m_axi_araddr[2]\ => incr_cmd_0_n_17,
\m_axi_araddr[5]\ => incr_cmd_0_n_16,
m_axi_arready => m_axi_arready,
\m_payload_i_reg[11]\(3 downto 0) => \m_payload_i_reg[11]\(3 downto 0),
\m_payload_i_reg[3]\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0),
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[51]\(12 downto 9) => \m_payload_i_reg[51]\(23 downto 20),
\m_payload_i_reg[51]\(8) => \m_payload_i_reg[51]\(18),
\m_payload_i_reg[51]\(7 downto 5) => \m_payload_i_reg[51]\(14 downto 12),
\m_payload_i_reg[51]\(4) => \m_payload_i_reg[51]\(5),
\m_payload_i_reg[51]\(3 downto 0) => \m_payload_i_reg[51]\(3 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
next_pending_r_reg_0 => next_pending_r_reg,
next_pending_r_reg_1 => next_pending_r_reg_0,
sel_first_reg_0 => sel_first_reg_2,
sel_first_reg_1 => sel_first_reg_3,
\state_reg[0]\ => \state_reg[0]\,
\state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0)
);
r_rlast_r_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => s_axburst_eq0,
I1 => \m_payload_i_reg[51]\(15),
I2 => s_axburst_eq1,
O => r_rlast
);
s_axburst_eq0_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]\,
Q => s_axburst_eq0,
R => '0'
);
s_axburst_eq1_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]_0\,
Q => s_axburst_eq1,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_i,
Q => sel_first_reg_0,
R => '0'
);
\state[1]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axburst_eq1,
I1 => \m_payload_i_reg[51]\(15),
I2 => s_axburst_eq0,
O => \state_reg[0]_rep\
);
wrap_cmd_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3
port map (
E(0) => E(0),
aclk => aclk,
\axaddr_incr_reg[11]\(6 downto 1) => axaddr_incr_reg(11 downto 6),
\axaddr_incr_reg[11]\(0) => axaddr_incr_reg(4),
\axaddr_incr_reg[3]\(2) => \^axaddr_incr_reg[3]\(3),
\axaddr_incr_reg[3]\(1 downto 0) => \^axaddr_incr_reg[3]\(1 downto 0),
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]_1\(3 downto 0) => \axaddr_offset_r_reg[3]_0\(3 downto 0),
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
\m_payload_i_reg[38]\ => \m_payload_i_reg[38]\,
\m_payload_i_reg[46]\ => \m_payload_i_reg[46]\,
\m_payload_i_reg[47]\(18 downto 14) => \m_payload_i_reg[51]\(19 downto 15),
\m_payload_i_reg[47]\(13 downto 0) => \m_payload_i_reg[51]\(13 downto 0),
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
sel_first_reg_0 => sel_first_reg_1,
sel_first_reg_1 => sel_first_reg_4,
sel_first_reg_2 => incr_cmd_0_n_16,
sel_first_reg_3 => incr_cmd_0_n_17,
si_rs_arvalid => si_rs_arvalid,
\state_reg[0]_rep\ => \state_reg[0]_rep_0\,
\state_reg[1]_rep\ => \state_reg[1]_rep\,
\state_reg[1]_rep_0\ => \state_reg[1]_rep_0\,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0),
\wrap_second_len_r_reg[3]_1\(3 downto 0) => \wrap_second_len_r_reg[3]_0\(3 downto 0),
\wrap_second_len_r_reg[3]_2\(3 downto 0) => \wrap_second_len_r_reg[3]_1\(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_r_channel is
port (
\state_reg[1]_rep\ : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
m_valid_i_reg : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 33 downto 0 );
\skid_buffer_reg[46]\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
\state_reg[1]_rep_0\ : in STD_LOGIC;
aclk : in STD_LOGIC;
r_rlast : in STD_LOGIC;
s_ready_i_reg : in STD_LOGIC;
si_rs_rready : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
areset_d1 : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_r_channel;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_r_channel is
signal \^m_valid_i_reg\ : STD_LOGIC;
signal r_push_r : STD_LOGIC;
signal rd_data_fifo_0_n_0 : STD_LOGIC;
signal rd_data_fifo_0_n_2 : STD_LOGIC;
signal rd_data_fifo_0_n_3 : STD_LOGIC;
signal rd_data_fifo_0_n_5 : STD_LOGIC;
signal trans_in : STD_LOGIC_VECTOR ( 12 downto 0 );
signal transaction_fifo_0_n_1 : STD_LOGIC;
signal wr_en0 : STD_LOGIC;
begin
m_valid_i_reg <= \^m_valid_i_reg\;
\r_arid_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(0),
Q => trans_in(1),
R => '0'
);
\r_arid_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(10),
Q => trans_in(11),
R => '0'
);
\r_arid_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(11),
Q => trans_in(12),
R => '0'
);
\r_arid_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(1),
Q => trans_in(2),
R => '0'
);
\r_arid_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(2),
Q => trans_in(3),
R => '0'
);
\r_arid_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(3),
Q => trans_in(4),
R => '0'
);
\r_arid_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(4),
Q => trans_in(5),
R => '0'
);
\r_arid_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(5),
Q => trans_in(6),
R => '0'
);
\r_arid_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(6),
Q => trans_in(7),
R => '0'
);
\r_arid_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(7),
Q => trans_in(8),
R => '0'
);
\r_arid_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(8),
Q => trans_in(9),
R => '0'
);
\r_arid_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(9),
Q => trans_in(10),
R => '0'
);
r_push_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \state_reg[1]_rep_0\,
Q => r_push_r,
R => '0'
);
r_rlast_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => r_rlast,
Q => trans_in(0),
R => '0'
);
rd_data_fifo_0: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\
port map (
aclk => aclk,
areset_d1 => areset_d1,
\cnt_read_reg[3]_rep__2_0\ => rd_data_fifo_0_n_0,
\cnt_read_reg[4]_rep__0_0\ => \^m_valid_i_reg\,
\cnt_read_reg[4]_rep__2_0\ => rd_data_fifo_0_n_2,
\cnt_read_reg[4]_rep__2_1\ => rd_data_fifo_0_n_3,
\in\(33 downto 0) => \in\(33 downto 0),
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
\out\(33 downto 0) => \out\(33 downto 0),
s_ready_i_reg => s_ready_i_reg,
s_ready_i_reg_0 => transaction_fifo_0_n_1,
si_rs_rready => si_rs_rready,
\state_reg[1]_rep\ => rd_data_fifo_0_n_5,
wr_en0 => wr_en0
);
transaction_fifo_0: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\
port map (
aclk => aclk,
areset_d1 => areset_d1,
\cnt_read_reg[0]_rep__2\ => rd_data_fifo_0_n_5,
\cnt_read_reg[0]_rep__2_0\ => rd_data_fifo_0_n_3,
\cnt_read_reg[3]_rep__2\ => rd_data_fifo_0_n_0,
\cnt_read_reg[4]_rep__2\ => transaction_fifo_0_n_1,
\cnt_read_reg[4]_rep__2_0\ => rd_data_fifo_0_n_2,
\in\(12 downto 0) => trans_in(12 downto 0),
m_valid_i_reg => \^m_valid_i_reg\,
r_push_r => r_push_r,
s_ready_i_reg => s_ready_i_reg,
si_rs_rready => si_rs_rready,
\skid_buffer_reg[46]\(12 downto 0) => \skid_buffer_reg[46]\(12 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep\,
wr_en0 => wr_en0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice is
port (
s_axi_awready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
si_rs_awvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
si_rs_bready : out STD_LOGIC;
si_rs_arvalid : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
si_rs_rready : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 58 downto 0 );
\s_arid_r_reg[11]\ : out STD_LOGIC_VECTOR ( 58 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
CO : out STD_LOGIC_VECTOR ( 0 to 0 );
O : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[7]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[3]\ : out STD_LOGIC;
axaddr_offset : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axlen_cnt_reg[3]\ : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
\wrap_cnt_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[3]_1\ : out STD_LOGIC;
axaddr_offset_0 : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axlen_cnt_reg[3]_0\ : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
next_pending_r_reg_2 : out STD_LOGIC;
\cnt_read_reg[3]_rep__0\ : out STD_LOGIC;
\axaddr_offset_r_reg[3]\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]_0\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\m_axi_awaddr[10]\ : out STD_LOGIC;
\m_axi_araddr[10]\ : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
\state_reg[0]_rep\ : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\cnt_read_reg[4]_rep__0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
b_push : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
S : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\state_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
wrap_second_len : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep_0\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
wrap_second_len_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep_1\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_4\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[0]_rep_0\ : in STD_LOGIC;
\state_reg[1]_rep_2\ : in STD_LOGIC;
sel_first : in STD_LOGIC;
sel_first_2 : in STD_LOGIC;
si_rs_bvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
\out\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\s_bresp_acc_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
r_push_r_reg : in STD_LOGIC_VECTOR ( 12 downto 0 );
\cnt_read_reg[4]\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
axaddr_incr_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice is
signal ar_pipe_n_2 : STD_LOGIC;
signal aw_pipe_n_1 : STD_LOGIC;
signal aw_pipe_n_97 : STD_LOGIC;
begin
ar_pipe: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice
port map (
Q(58 downto 0) => \s_arid_r_reg[11]\(58 downto 0),
aclk => aclk,
\aresetn_d_reg[0]\ => aw_pipe_n_1,
\aresetn_d_reg[0]_0\ => aw_pipe_n_97,
\axaddr_incr_reg[11]\(3 downto 0) => \axaddr_incr_reg[11]_0\(3 downto 0),
\axaddr_incr_reg[3]\(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
\axaddr_incr_reg[3]_0\(3 downto 0) => \axaddr_incr_reg[3]_0\(3 downto 0),
\axaddr_incr_reg[7]\(3 downto 0) => \axaddr_incr_reg[7]\(3 downto 0),
\axaddr_incr_reg[7]_0\(0) => \axaddr_incr_reg[7]_0\(0),
\axaddr_offset_r_reg[0]\ => axaddr_offset_0(0),
\axaddr_offset_r_reg[1]\ => axaddr_offset_0(1),
\axaddr_offset_r_reg[2]\ => axaddr_offset_0(2),
\axaddr_offset_r_reg[3]\ => \axaddr_offset_r_reg[3]_0\,
\axaddr_offset_r_reg[3]_0\(0) => \axaddr_offset_r_reg[3]_3\(0),
\axaddr_offset_r_reg[3]_1\(3 downto 0) => \axaddr_offset_r_reg[3]_4\(3 downto 0),
\axlen_cnt_reg[3]\ => \axlen_cnt_reg[3]_0\,
\m_axi_araddr[10]\ => \m_axi_araddr[10]\,
\m_payload_i_reg[3]_0\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0),
m_valid_i_reg_0 => ar_pipe_n_2,
m_valid_i_reg_1(0) => m_valid_i_reg(0),
next_pending_r_reg => next_pending_r_reg_1,
next_pending_r_reg_0 => next_pending_r_reg_2,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_ready_i_reg_0 => si_rs_arvalid,
sel_first_2 => sel_first_2,
\state_reg[0]_rep\ => \state_reg[0]_rep_0\,
\state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep_1\,
\state_reg[1]_rep_0\ => \state_reg[1]_rep_2\,
\wrap_boundary_axaddr_r_reg[6]\(6 downto 0) => \wrap_boundary_axaddr_r_reg[6]_0\(6 downto 0),
\wrap_cnt_r_reg[3]\(2 downto 0) => \wrap_cnt_r_reg[3]_0\(2 downto 0),
\wrap_cnt_r_reg[3]_0\ => \wrap_cnt_r_reg[3]_1\,
wrap_second_len_1(0) => wrap_second_len_1(0),
\wrap_second_len_r_reg[3]\(2 downto 0) => \wrap_second_len_r_reg[3]_0\(2 downto 0),
\wrap_second_len_r_reg[3]_0\(2 downto 0) => \wrap_second_len_r_reg[3]_2\(2 downto 0)
);
aw_pipe: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice_0
port map (
CO(0) => CO(0),
D(2 downto 0) => D(2 downto 0),
E(0) => E(0),
O(3 downto 0) => O(3 downto 0),
Q(58 downto 0) => Q(58 downto 0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
aresetn => aresetn,
\aresetn_d_reg[1]_inv\ => aw_pipe_n_97,
\aresetn_d_reg[1]_inv_0\ => ar_pipe_n_2,
axaddr_incr_reg(3 downto 0) => axaddr_incr_reg(3 downto 0),
\axaddr_incr_reg[11]\(7 downto 0) => \axaddr_incr_reg[11]\(7 downto 0),
\axaddr_offset_r_reg[0]\ => axaddr_offset(0),
\axaddr_offset_r_reg[1]\ => axaddr_offset(1),
\axaddr_offset_r_reg[2]\ => axaddr_offset(2),
\axaddr_offset_r_reg[3]\ => \axaddr_offset_r_reg[3]\,
\axaddr_offset_r_reg[3]_0\(0) => \axaddr_offset_r_reg[3]_1\(0),
\axaddr_offset_r_reg[3]_1\(3 downto 0) => \axaddr_offset_r_reg[3]_2\(3 downto 0),
\axlen_cnt_reg[3]\ => \axlen_cnt_reg[3]\,
b_push => b_push,
\m_axi_awaddr[10]\ => \m_axi_awaddr[10]\,
m_valid_i_reg_0 => si_rs_awvalid,
next_pending_r_reg => next_pending_r_reg,
next_pending_r_reg_0 => next_pending_r_reg_0,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_ready_i_reg_0 => aw_pipe_n_1,
sel_first => sel_first,
\state_reg[0]_rep\ => \state_reg[0]_rep\,
\state_reg[1]\(1 downto 0) => \state_reg[1]_0\(1 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep\,
\state_reg[1]_rep_0\ => \state_reg[1]_rep_0\,
\wrap_boundary_axaddr_r_reg[6]\(6 downto 0) => \wrap_boundary_axaddr_r_reg[6]\(6 downto 0),
\wrap_cnt_r_reg[3]\ => \wrap_cnt_r_reg[3]\,
wrap_second_len(0) => wrap_second_len(0),
\wrap_second_len_r_reg[3]\(2 downto 0) => \wrap_second_len_r_reg[3]\(2 downto 0),
\wrap_second_len_r_reg[3]_0\(2 downto 0) => \wrap_second_len_r_reg[3]_1\(2 downto 0)
);
b_pipe: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\
port map (
aclk => aclk,
\aresetn_d_reg[0]\ => aw_pipe_n_1,
\aresetn_d_reg[1]_inv\ => ar_pipe_n_2,
\out\(11 downto 0) => \out\(11 downto 0),
\s_axi_bid[11]\(13 downto 0) => \s_axi_bid[11]\(13 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
\s_bresp_acc_reg[1]\(1 downto 0) => \s_bresp_acc_reg[1]\(1 downto 0),
si_rs_bvalid => si_rs_bvalid,
\skid_buffer_reg[0]_0\ => si_rs_bready
);
r_pipe: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\
port map (
aclk => aclk,
\aresetn_d_reg[0]\ => aw_pipe_n_1,
\aresetn_d_reg[1]_inv\ => ar_pipe_n_2,
\cnt_read_reg[3]_rep__0\ => \cnt_read_reg[3]_rep__0\,
\cnt_read_reg[4]\(33 downto 0) => \cnt_read_reg[4]\(33 downto 0),
\cnt_read_reg[4]_rep__0\ => \cnt_read_reg[4]_rep__0\,
r_push_r_reg(12 downto 0) => r_push_r_reg(12 downto 0),
\s_axi_rid[11]\(46 downto 0) => \s_axi_rid[11]\(46 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
\skid_buffer_reg[0]_0\ => si_rs_rready
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_ar_channel is
port (
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
wrap_second_len : out STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_boundary_axaddr_r_reg[11]\ : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC;
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
r_push_r_reg : out STD_LOGIC;
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
r_rlast : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\r_arid_r_reg[11]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
\m_payload_i_reg[44]\ : in STD_LOGIC;
\m_payload_i_reg[64]\ : in STD_LOGIC_VECTOR ( 35 downto 0 );
m_axi_arready : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
\cnt_read_reg[2]_rep__0\ : in STD_LOGIC;
axaddr_offset : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[46]\ : in STD_LOGIC;
\m_payload_i_reg[51]\ : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
\m_payload_i_reg[6]\ : in STD_LOGIC;
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[6]_0\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_ar_channel;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_ar_channel is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ar_cmd_fsm_0_n_0 : STD_LOGIC;
signal ar_cmd_fsm_0_n_12 : STD_LOGIC;
signal ar_cmd_fsm_0_n_15 : STD_LOGIC;
signal ar_cmd_fsm_0_n_16 : STD_LOGIC;
signal ar_cmd_fsm_0_n_17 : STD_LOGIC;
signal ar_cmd_fsm_0_n_20 : STD_LOGIC;
signal ar_cmd_fsm_0_n_21 : STD_LOGIC;
signal ar_cmd_fsm_0_n_3 : STD_LOGIC;
signal ar_cmd_fsm_0_n_8 : STD_LOGIC;
signal ar_cmd_fsm_0_n_9 : STD_LOGIC;
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axaddr_offset_r_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal cmd_translator_0_n_0 : STD_LOGIC;
signal cmd_translator_0_n_10 : STD_LOGIC;
signal cmd_translator_0_n_11 : STD_LOGIC;
signal cmd_translator_0_n_13 : STD_LOGIC;
signal cmd_translator_0_n_2 : STD_LOGIC;
signal cmd_translator_0_n_8 : STD_LOGIC;
signal cmd_translator_0_n_9 : STD_LOGIC;
signal incr_next_pending : STD_LOGIC;
signal \^m_payload_i_reg[0]\ : STD_LOGIC;
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal \^r_push_r_reg\ : STD_LOGIC;
signal \^sel_first\ : STD_LOGIC;
signal sel_first_i : STD_LOGIC;
signal \^wrap_boundary_axaddr_r_reg[11]\ : STD_LOGIC;
signal \wrap_cmd_0/wrap_second_len_r\ : STD_LOGIC_VECTOR ( 1 to 1 );
signal wrap_next_pending : STD_LOGIC;
signal \^wrap_second_len\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_offset_r_reg[3]\(0) <= \^axaddr_offset_r_reg[3]\(0);
\axaddr_offset_r_reg[3]_0\(3 downto 0) <= \^axaddr_offset_r_reg[3]_0\(3 downto 0);
\m_payload_i_reg[0]\ <= \^m_payload_i_reg[0]\;
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
r_push_r_reg <= \^r_push_r_reg\;
sel_first <= \^sel_first\;
\wrap_boundary_axaddr_r_reg[11]\ <= \^wrap_boundary_axaddr_r_reg[11]\;
wrap_second_len(0) <= \^wrap_second_len\(0);
ar_cmd_fsm_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm
port map (
D(0) => ar_cmd_fsm_0_n_3,
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
Q(1 downto 0) => \^q\(1 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\axaddr_incr_reg[11]\ => ar_cmd_fsm_0_n_17,
axaddr_offset(2 downto 0) => axaddr_offset(2 downto 0),
\axaddr_offset_r_reg[3]\(0) => \^axaddr_offset_r_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(0) => \^axaddr_offset_r_reg[3]_0\(3),
\axaddr_wrap_reg[11]\(0) => ar_cmd_fsm_0_n_16,
\axlen_cnt_reg[1]\ => ar_cmd_fsm_0_n_0,
\axlen_cnt_reg[1]_0\(1) => ar_cmd_fsm_0_n_8,
\axlen_cnt_reg[1]_0\(0) => ar_cmd_fsm_0_n_9,
\axlen_cnt_reg[1]_1\(1) => cmd_translator_0_n_9,
\axlen_cnt_reg[1]_1\(0) => cmd_translator_0_n_10,
\axlen_cnt_reg[4]\ => cmd_translator_0_n_11,
\cnt_read_reg[2]_rep__0\ => \cnt_read_reg[2]_rep__0\,
incr_next_pending => incr_next_pending,
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
\m_payload_i_reg[0]\ => \^m_payload_i_reg[0]_0\,
\m_payload_i_reg[0]_0\ => \^m_payload_i_reg[0]\,
\m_payload_i_reg[0]_1\(0) => E(0),
\m_payload_i_reg[44]\ => \m_payload_i_reg[44]\,
\m_payload_i_reg[47]\(3) => \m_payload_i_reg[64]\(19),
\m_payload_i_reg[47]\(2 downto 0) => \m_payload_i_reg[64]\(17 downto 15),
\m_payload_i_reg[51]\ => \m_payload_i_reg[51]\,
\m_payload_i_reg[6]\ => \m_payload_i_reg[6]\,
next_pending_r_reg => cmd_translator_0_n_0,
r_push_r_reg => \^r_push_r_reg\,
s_axburst_eq0_reg => ar_cmd_fsm_0_n_12,
s_axburst_eq1_reg => ar_cmd_fsm_0_n_15,
s_axburst_eq1_reg_0 => cmd_translator_0_n_13,
sel_first_i => sel_first_i,
sel_first_reg => ar_cmd_fsm_0_n_20,
sel_first_reg_0 => ar_cmd_fsm_0_n_21,
sel_first_reg_1 => cmd_translator_0_n_2,
sel_first_reg_2 => \^sel_first\,
sel_first_reg_3 => cmd_translator_0_n_8,
si_rs_arvalid => si_rs_arvalid,
wrap_next_pending => wrap_next_pending,
wrap_second_len(0) => \^wrap_second_len\(0),
\wrap_second_len_r_reg[1]\(0) => \wrap_cmd_0/wrap_second_len_r\(1)
);
cmd_translator_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1
port map (
CO(0) => CO(0),
D(1) => ar_cmd_fsm_0_n_8,
D(0) => ar_cmd_fsm_0_n_9,
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
O(3 downto 0) => O(3 downto 0),
Q(1) => cmd_translator_0_n_9,
Q(0) => cmd_translator_0_n_10,
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
\axaddr_incr_reg[11]\ => \^sel_first\,
\axaddr_incr_reg[3]\(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]\(3 downto 0) => \^axaddr_offset_r_reg[3]_0\(3 downto 0),
\axaddr_offset_r_reg[3]_0\(3) => \^axaddr_offset_r_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(2 downto 0) => axaddr_offset(2 downto 0),
incr_next_pending => incr_next_pending,
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
m_axi_arready => m_axi_arready,
\m_payload_i_reg[11]\(3 downto 0) => \m_payload_i_reg[11]\(3 downto 0),
\m_payload_i_reg[38]\ => \m_payload_i_reg[38]\,
\m_payload_i_reg[39]\ => ar_cmd_fsm_0_n_12,
\m_payload_i_reg[39]_0\ => ar_cmd_fsm_0_n_15,
\m_payload_i_reg[3]\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0),
\m_payload_i_reg[46]\ => \m_payload_i_reg[46]\,
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[51]\(23 downto 0) => \m_payload_i_reg[64]\(23 downto 0),
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]_0\(6 downto 0),
m_valid_i_reg(0) => ar_cmd_fsm_0_n_16,
next_pending_r_reg => cmd_translator_0_n_0,
next_pending_r_reg_0 => cmd_translator_0_n_11,
r_rlast => r_rlast,
sel_first_i => sel_first_i,
sel_first_reg_0 => cmd_translator_0_n_2,
sel_first_reg_1 => cmd_translator_0_n_8,
sel_first_reg_2 => ar_cmd_fsm_0_n_17,
sel_first_reg_3 => ar_cmd_fsm_0_n_20,
sel_first_reg_4 => ar_cmd_fsm_0_n_21,
si_rs_arvalid => si_rs_arvalid,
\state_reg[0]\ => ar_cmd_fsm_0_n_0,
\state_reg[0]_rep\ => cmd_translator_0_n_13,
\state_reg[0]_rep_0\ => \^m_payload_i_reg[0]\,
\state_reg[1]\(1 downto 0) => \^q\(1 downto 0),
\state_reg[1]_rep\ => \^m_payload_i_reg[0]_0\,
\state_reg[1]_rep_0\ => \^r_push_r_reg\,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]\(3 downto 2) => \wrap_second_len_r_reg[3]\(2 downto 1),
\wrap_second_len_r_reg[3]\(1) => \wrap_cmd_0/wrap_second_len_r\(1),
\wrap_second_len_r_reg[3]\(0) => \wrap_second_len_r_reg[3]\(0),
\wrap_second_len_r_reg[3]_0\(3 downto 2) => D(2 downto 1),
\wrap_second_len_r_reg[3]_0\(1) => \^wrap_second_len\(0),
\wrap_second_len_r_reg[3]_0\(0) => D(0),
\wrap_second_len_r_reg[3]_1\(3 downto 2) => \wrap_second_len_r_reg[3]_0\(2 downto 1),
\wrap_second_len_r_reg[3]_1\(1) => ar_cmd_fsm_0_n_3,
\wrap_second_len_r_reg[3]_1\(0) => \wrap_second_len_r_reg[3]_0\(0)
);
\s_arid_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(24),
Q => \r_arid_r_reg[11]\(0),
R => '0'
);
\s_arid_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(34),
Q => \r_arid_r_reg[11]\(10),
R => '0'
);
\s_arid_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(35),
Q => \r_arid_r_reg[11]\(11),
R => '0'
);
\s_arid_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(25),
Q => \r_arid_r_reg[11]\(1),
R => '0'
);
\s_arid_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(26),
Q => \r_arid_r_reg[11]\(2),
R => '0'
);
\s_arid_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(27),
Q => \r_arid_r_reg[11]\(3),
R => '0'
);
\s_arid_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(28),
Q => \r_arid_r_reg[11]\(4),
R => '0'
);
\s_arid_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(29),
Q => \r_arid_r_reg[11]\(5),
R => '0'
);
\s_arid_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(30),
Q => \r_arid_r_reg[11]\(6),
R => '0'
);
\s_arid_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(31),
Q => \r_arid_r_reg[11]\(7),
R => '0'
);
\s_arid_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(32),
Q => \r_arid_r_reg[11]\(8),
R => '0'
);
\s_arid_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(33),
Q => \r_arid_r_reg[11]\(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_aw_channel is
port (
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
\wrap_boundary_axaddr_r_reg[11]\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep\ : out STD_LOGIC;
\state_reg[1]_rep_0\ : out STD_LOGIC;
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
b_push : out STD_LOGIC;
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\in\ : out STD_LOGIC_VECTOR ( 19 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC;
si_rs_awvalid : in STD_LOGIC;
\m_payload_i_reg[64]\ : in STD_LOGIC_VECTOR ( 35 downto 0 );
\m_payload_i_reg[44]\ : in STD_LOGIC;
\cnt_read_reg[1]_rep__1\ : in STD_LOGIC;
\cnt_read_reg[0]_rep__0\ : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[35]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[48]\ : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
\m_payload_i_reg[46]\ : in STD_LOGIC;
\m_payload_i_reg[6]\ : in STD_LOGIC;
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[6]_0\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_aw_channel;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_aw_channel is
signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal aw_cmd_fsm_0_n_0 : STD_LOGIC;
signal aw_cmd_fsm_0_n_13 : STD_LOGIC;
signal aw_cmd_fsm_0_n_17 : STD_LOGIC;
signal aw_cmd_fsm_0_n_20 : STD_LOGIC;
signal aw_cmd_fsm_0_n_21 : STD_LOGIC;
signal aw_cmd_fsm_0_n_24 : STD_LOGIC;
signal aw_cmd_fsm_0_n_25 : STD_LOGIC;
signal aw_cmd_fsm_0_n_3 : STD_LOGIC;
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axaddr_offset_r_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^b_push\ : STD_LOGIC;
signal cmd_translator_0_n_0 : STD_LOGIC;
signal cmd_translator_0_n_1 : STD_LOGIC;
signal cmd_translator_0_n_10 : STD_LOGIC;
signal cmd_translator_0_n_11 : STD_LOGIC;
signal cmd_translator_0_n_12 : STD_LOGIC;
signal cmd_translator_0_n_13 : STD_LOGIC;
signal cmd_translator_0_n_14 : STD_LOGIC;
signal cmd_translator_0_n_15 : STD_LOGIC;
signal cmd_translator_0_n_16 : STD_LOGIC;
signal cmd_translator_0_n_17 : STD_LOGIC;
signal cmd_translator_0_n_2 : STD_LOGIC;
signal cmd_translator_0_n_9 : STD_LOGIC;
signal incr_next_pending : STD_LOGIC;
signal \next\ : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \^sel_first\ : STD_LOGIC;
signal \sel_first__0\ : STD_LOGIC;
signal sel_first_i : STD_LOGIC;
signal \^wrap_boundary_axaddr_r_reg[11]\ : STD_LOGIC;
signal \wrap_cmd_0/wrap_second_len_r\ : STD_LOGIC_VECTOR ( 1 to 1 );
signal wrap_next_pending : STD_LOGIC;
begin
D(0) <= \^d\(0);
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_offset_r_reg[3]\(0) <= \^axaddr_offset_r_reg[3]\(0);
\axaddr_offset_r_reg[3]_0\(3 downto 0) <= \^axaddr_offset_r_reg[3]_0\(3 downto 0);
b_push <= \^b_push\;
sel_first <= \^sel_first\;
\wrap_boundary_axaddr_r_reg[11]\ <= \^wrap_boundary_axaddr_r_reg[11]\;
aw_cmd_fsm_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm
port map (
D(0) => aw_cmd_fsm_0_n_3,
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
Q(1 downto 0) => \^q\(1 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\axaddr_incr_reg[11]\ => aw_cmd_fsm_0_n_21,
\axaddr_offset_r_reg[3]\(0) => \^axaddr_offset_r_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(0) => \^axaddr_offset_r_reg[3]_0\(3),
\axaddr_wrap_reg[0]\(0) => aw_cmd_fsm_0_n_20,
\axlen_cnt_reg[2]\ => cmd_translator_0_n_16,
\axlen_cnt_reg[3]\ => cmd_translator_0_n_15,
\axlen_cnt_reg[3]_0\ => cmd_translator_0_n_17,
\axlen_cnt_reg[4]\ => aw_cmd_fsm_0_n_0,
\axlen_cnt_reg[4]_0\ => cmd_translator_0_n_13,
\axlen_cnt_reg[5]\(3 downto 2) => p_1_in(5 downto 4),
\axlen_cnt_reg[5]\(1 downto 0) => p_1_in(1 downto 0),
\axlen_cnt_reg[5]_0\(3) => cmd_translator_0_n_9,
\axlen_cnt_reg[5]_0\(2) => cmd_translator_0_n_10,
\axlen_cnt_reg[5]_0\(1) => cmd_translator_0_n_11,
\axlen_cnt_reg[5]_0\(0) => cmd_translator_0_n_12,
\cnt_read_reg[0]_rep__0\ => \cnt_read_reg[0]_rep__0\,
\cnt_read_reg[1]_rep__1\ => \cnt_read_reg[1]_rep__1\,
incr_next_pending => incr_next_pending,
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
\m_payload_i_reg[0]\ => \^b_push\,
\m_payload_i_reg[0]_0\(0) => E(0),
\m_payload_i_reg[35]\(2 downto 0) => \m_payload_i_reg[35]\(2 downto 0),
\m_payload_i_reg[44]\ => \m_payload_i_reg[44]\,
\m_payload_i_reg[46]\ => \m_payload_i_reg[46]\,
\m_payload_i_reg[48]\ => \m_payload_i_reg[48]\,
\m_payload_i_reg[49]\(5 downto 3) => \m_payload_i_reg[64]\(21 downto 19),
\m_payload_i_reg[49]\(2 downto 0) => \m_payload_i_reg[64]\(17 downto 15),
\m_payload_i_reg[6]\ => \m_payload_i_reg[6]\,
\next\ => \next\,
next_pending_r_reg => cmd_translator_0_n_0,
next_pending_r_reg_0 => cmd_translator_0_n_1,
s_axburst_eq0_reg => aw_cmd_fsm_0_n_13,
s_axburst_eq1_reg => aw_cmd_fsm_0_n_17,
s_axburst_eq1_reg_0 => cmd_translator_0_n_14,
\sel_first__0\ => \sel_first__0\,
sel_first_i => sel_first_i,
sel_first_reg => aw_cmd_fsm_0_n_24,
sel_first_reg_0 => aw_cmd_fsm_0_n_25,
sel_first_reg_1 => cmd_translator_0_n_2,
sel_first_reg_2 => \^sel_first\,
si_rs_awvalid => si_rs_awvalid,
\state_reg[1]_rep_0\ => \state_reg[1]_rep\,
\state_reg[1]_rep_1\ => \state_reg[1]_rep_0\,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[1]\(0) => \^d\(0),
\wrap_second_len_r_reg[1]_0\(0) => \wrap_cmd_0/wrap_second_len_r\(1)
);
cmd_translator_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator
port map (
CO(0) => CO(0),
D(3 downto 2) => p_1_in(5 downto 4),
D(1 downto 0) => p_1_in(1 downto 0),
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
O(3 downto 0) => O(3 downto 0),
Q(3) => cmd_translator_0_n_9,
Q(2) => cmd_translator_0_n_10,
Q(1) => cmd_translator_0_n_11,
Q(0) => cmd_translator_0_n_12,
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
\axaddr_incr_reg[11]\ => \^sel_first\,
\axaddr_incr_reg[3]\(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]\(3 downto 0) => \^axaddr_offset_r_reg[3]_0\(3 downto 0),
\axaddr_offset_r_reg[3]_0\(3) => \^axaddr_offset_r_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(2 downto 0) => \m_payload_i_reg[35]\(2 downto 0),
\axlen_cnt_reg[4]\ => cmd_translator_0_n_17,
\axlen_cnt_reg[7]\ => cmd_translator_0_n_13,
incr_next_pending => incr_next_pending,
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
\m_payload_i_reg[11]\(7 downto 0) => \m_payload_i_reg[11]\(7 downto 0),
\m_payload_i_reg[38]\ => \m_payload_i_reg[38]\,
\m_payload_i_reg[39]\ => aw_cmd_fsm_0_n_13,
\m_payload_i_reg[39]_0\ => aw_cmd_fsm_0_n_17,
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[51]\(21 downto 20) => \m_payload_i_reg[64]\(23 downto 22),
\m_payload_i_reg[51]\(19 downto 0) => \m_payload_i_reg[64]\(19 downto 0),
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]_0\(6 downto 0),
m_valid_i_reg(0) => aw_cmd_fsm_0_n_20,
\next\ => \next\,
next_pending_r_reg => cmd_translator_0_n_0,
next_pending_r_reg_0 => cmd_translator_0_n_1,
next_pending_r_reg_1 => cmd_translator_0_n_15,
next_pending_r_reg_2 => cmd_translator_0_n_16,
\sel_first__0\ => \sel_first__0\,
sel_first_i => sel_first_i,
sel_first_reg_0 => cmd_translator_0_n_2,
sel_first_reg_1 => aw_cmd_fsm_0_n_21,
sel_first_reg_2 => aw_cmd_fsm_0_n_24,
sel_first_reg_3 => aw_cmd_fsm_0_n_25,
\state_reg[0]\ => aw_cmd_fsm_0_n_0,
\state_reg[0]_rep\ => \^b_push\,
\state_reg[1]\(1 downto 0) => \^q\(1 downto 0),
\state_reg[1]_rep\ => cmd_translator_0_n_14,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]\(3 downto 2) => \wrap_second_len_r_reg[3]\(2 downto 1),
\wrap_second_len_r_reg[3]\(1) => \wrap_cmd_0/wrap_second_len_r\(1),
\wrap_second_len_r_reg[3]\(0) => \wrap_second_len_r_reg[3]\(0),
\wrap_second_len_r_reg[3]_0\(3 downto 2) => \wrap_second_len_r_reg[3]_0\(2 downto 1),
\wrap_second_len_r_reg[3]_0\(1) => \^d\(0),
\wrap_second_len_r_reg[3]_0\(0) => \wrap_second_len_r_reg[3]_0\(0),
\wrap_second_len_r_reg[3]_1\(3 downto 2) => \wrap_second_len_r_reg[3]_1\(2 downto 1),
\wrap_second_len_r_reg[3]_1\(1) => aw_cmd_fsm_0_n_3,
\wrap_second_len_r_reg[3]_1\(0) => \wrap_second_len_r_reg[3]_1\(0)
);
\s_awid_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(24),
Q => \in\(8),
R => '0'
);
\s_awid_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(34),
Q => \in\(18),
R => '0'
);
\s_awid_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(35),
Q => \in\(19),
R => '0'
);
\s_awid_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(25),
Q => \in\(9),
R => '0'
);
\s_awid_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(26),
Q => \in\(10),
R => '0'
);
\s_awid_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(27),
Q => \in\(11),
R => '0'
);
\s_awid_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(28),
Q => \in\(12),
R => '0'
);
\s_awid_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(29),
Q => \in\(13),
R => '0'
);
\s_awid_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(30),
Q => \in\(14),
R => '0'
);
\s_awid_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(31),
Q => \in\(15),
R => '0'
);
\s_awid_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(32),
Q => \in\(16),
R => '0'
);
\s_awid_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(33),
Q => \in\(17),
R => '0'
);
\s_awlen_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(16),
Q => \in\(0),
R => '0'
);
\s_awlen_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(17),
Q => \in\(1),
R => '0'
);
\s_awlen_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(18),
Q => \in\(2),
R => '0'
);
\s_awlen_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(19),
Q => \in\(3),
R => '0'
);
\s_awlen_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(20),
Q => \in\(4),
R => '0'
);
\s_awlen_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(21),
Q => \in\(5),
R => '0'
);
\s_awlen_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(22),
Q => \in\(6),
R => '0'
);
\s_awlen_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(23),
Q => \in\(7),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s is
port (
s_axi_rvalid : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 22 downto 0 );
s_axi_arready : out STD_LOGIC;
\m_axi_arprot[2]\ : out STD_LOGIC_VECTOR ( 22 downto 0 );
s_axi_bvalid : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awready : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
aclk : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
aresetn : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s is
signal C : STD_LOGIC_VECTOR ( 11 downto 4 );
signal \RD.ar_channel_0_n_10\ : STD_LOGIC;
signal \RD.ar_channel_0_n_11\ : STD_LOGIC;
signal \RD.ar_channel_0_n_47\ : STD_LOGIC;
signal \RD.ar_channel_0_n_48\ : STD_LOGIC;
signal \RD.ar_channel_0_n_49\ : STD_LOGIC;
signal \RD.ar_channel_0_n_50\ : STD_LOGIC;
signal \RD.ar_channel_0_n_8\ : STD_LOGIC;
signal \RD.ar_channel_0_n_9\ : STD_LOGIC;
signal \RD.r_channel_0_n_0\ : STD_LOGIC;
signal \RD.r_channel_0_n_2\ : STD_LOGIC;
signal SI_REG_n_134 : STD_LOGIC;
signal SI_REG_n_135 : STD_LOGIC;
signal SI_REG_n_136 : STD_LOGIC;
signal SI_REG_n_137 : STD_LOGIC;
signal SI_REG_n_138 : STD_LOGIC;
signal SI_REG_n_139 : STD_LOGIC;
signal SI_REG_n_140 : STD_LOGIC;
signal SI_REG_n_141 : STD_LOGIC;
signal SI_REG_n_142 : STD_LOGIC;
signal SI_REG_n_143 : STD_LOGIC;
signal SI_REG_n_144 : STD_LOGIC;
signal SI_REG_n_145 : STD_LOGIC;
signal SI_REG_n_146 : STD_LOGIC;
signal SI_REG_n_147 : STD_LOGIC;
signal SI_REG_n_148 : STD_LOGIC;
signal SI_REG_n_149 : STD_LOGIC;
signal SI_REG_n_150 : STD_LOGIC;
signal SI_REG_n_151 : STD_LOGIC;
signal SI_REG_n_158 : STD_LOGIC;
signal SI_REG_n_162 : STD_LOGIC;
signal SI_REG_n_163 : STD_LOGIC;
signal SI_REG_n_164 : STD_LOGIC;
signal SI_REG_n_165 : STD_LOGIC;
signal SI_REG_n_166 : STD_LOGIC;
signal SI_REG_n_167 : STD_LOGIC;
signal SI_REG_n_171 : STD_LOGIC;
signal SI_REG_n_175 : STD_LOGIC;
signal SI_REG_n_176 : STD_LOGIC;
signal SI_REG_n_177 : STD_LOGIC;
signal SI_REG_n_178 : STD_LOGIC;
signal SI_REG_n_179 : STD_LOGIC;
signal SI_REG_n_180 : STD_LOGIC;
signal SI_REG_n_181 : STD_LOGIC;
signal SI_REG_n_182 : STD_LOGIC;
signal SI_REG_n_183 : STD_LOGIC;
signal SI_REG_n_184 : STD_LOGIC;
signal SI_REG_n_185 : STD_LOGIC;
signal SI_REG_n_186 : STD_LOGIC;
signal SI_REG_n_187 : STD_LOGIC;
signal SI_REG_n_188 : STD_LOGIC;
signal SI_REG_n_189 : STD_LOGIC;
signal SI_REG_n_190 : STD_LOGIC;
signal SI_REG_n_191 : STD_LOGIC;
signal SI_REG_n_192 : STD_LOGIC;
signal SI_REG_n_193 : STD_LOGIC;
signal SI_REG_n_194 : STD_LOGIC;
signal SI_REG_n_195 : STD_LOGIC;
signal SI_REG_n_196 : STD_LOGIC;
signal SI_REG_n_20 : STD_LOGIC;
signal SI_REG_n_21 : STD_LOGIC;
signal SI_REG_n_22 : STD_LOGIC;
signal SI_REG_n_23 : STD_LOGIC;
signal SI_REG_n_29 : STD_LOGIC;
signal SI_REG_n_79 : STD_LOGIC;
signal SI_REG_n_80 : STD_LOGIC;
signal SI_REG_n_81 : STD_LOGIC;
signal SI_REG_n_82 : STD_LOGIC;
signal SI_REG_n_88 : STD_LOGIC;
signal \WR.aw_channel_0_n_10\ : STD_LOGIC;
signal \WR.aw_channel_0_n_54\ : STD_LOGIC;
signal \WR.aw_channel_0_n_55\ : STD_LOGIC;
signal \WR.aw_channel_0_n_56\ : STD_LOGIC;
signal \WR.aw_channel_0_n_57\ : STD_LOGIC;
signal \WR.aw_channel_0_n_7\ : STD_LOGIC;
signal \WR.aw_channel_0_n_9\ : STD_LOGIC;
signal \WR.b_channel_0_n_1\ : STD_LOGIC;
signal \WR.b_channel_0_n_2\ : STD_LOGIC;
signal \ar_cmd_fsm_0/state\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \ar_pipe/p_1_in\ : STD_LOGIC;
signal areset_d1 : STD_LOGIC;
signal areset_d1_i_1_n_0 : STD_LOGIC;
signal \aw_cmd_fsm_0/state\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \aw_pipe/p_1_in\ : STD_LOGIC;
signal b_awid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal b_awlen : STD_LOGIC_VECTOR ( 7 downto 0 );
signal b_push : STD_LOGIC;
signal \cmd_translator_0/incr_cmd_0/axaddr_incr_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/incr_cmd_0/axaddr_incr_reg_5\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/incr_cmd_0/sel_first\ : STD_LOGIC;
signal \cmd_translator_0/incr_cmd_0/sel_first_4\ : STD_LOGIC;
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal r_rlast : STD_LOGIC;
signal s_arid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s_arid_r : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s_awid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_araddr : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_arburst : STD_LOGIC_VECTOR ( 1 to 1 );
signal si_rs_arlen : STD_LOGIC_VECTOR ( 3 downto 0 );
signal si_rs_arsize : STD_LOGIC_VECTOR ( 1 downto 0 );
signal si_rs_arvalid : STD_LOGIC;
signal si_rs_awaddr : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_awburst : STD_LOGIC_VECTOR ( 1 to 1 );
signal si_rs_awlen : STD_LOGIC_VECTOR ( 3 downto 0 );
signal si_rs_awsize : STD_LOGIC_VECTOR ( 1 downto 0 );
signal si_rs_awvalid : STD_LOGIC;
signal si_rs_bid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_bready : STD_LOGIC;
signal si_rs_bresp : STD_LOGIC_VECTOR ( 1 downto 0 );
signal si_rs_bvalid : STD_LOGIC;
signal si_rs_rdata : STD_LOGIC_VECTOR ( 31 downto 0 );
signal si_rs_rid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_rlast : STD_LOGIC;
signal si_rs_rready : STD_LOGIC;
signal si_rs_rresp : STD_LOGIC_VECTOR ( 1 downto 0 );
signal wrap_cnt : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
\RD.ar_channel_0\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_ar_channel
port map (
CO(0) => SI_REG_n_147,
D(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(3 downto 2),
D(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(0),
E(0) => \ar_pipe/p_1_in\,
O(3) => SI_REG_n_148,
O(2) => SI_REG_n_149,
O(1) => SI_REG_n_150,
O(0) => SI_REG_n_151,
Q(1 downto 0) => \ar_cmd_fsm_0/state\(1 downto 0),
S(3) => \RD.ar_channel_0_n_47\,
S(2) => \RD.ar_channel_0_n_48\,
S(1) => \RD.ar_channel_0_n_49\,
S(0) => \RD.ar_channel_0_n_50\,
aclk => aclk,
areset_d1 => areset_d1,
\axaddr_incr_reg[3]\(3 downto 0) => \cmd_translator_0/incr_cmd_0/axaddr_incr_reg\(3 downto 0),
axaddr_offset(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(2 downto 0),
\axaddr_offset_r_reg[3]\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(3),
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(3 downto 0),
\cnt_read_reg[2]_rep__0\ => \RD.r_channel_0_n_0\,
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
\m_payload_i_reg[0]\ => \RD.ar_channel_0_n_9\,
\m_payload_i_reg[0]_0\ => \RD.ar_channel_0_n_10\,
\m_payload_i_reg[11]\(3) => SI_REG_n_143,
\m_payload_i_reg[11]\(2) => SI_REG_n_144,
\m_payload_i_reg[11]\(1) => SI_REG_n_145,
\m_payload_i_reg[11]\(0) => SI_REG_n_146,
\m_payload_i_reg[38]\ => SI_REG_n_196,
\m_payload_i_reg[3]\(3) => SI_REG_n_139,
\m_payload_i_reg[3]\(2) => SI_REG_n_140,
\m_payload_i_reg[3]\(1) => SI_REG_n_141,
\m_payload_i_reg[3]\(0) => SI_REG_n_142,
\m_payload_i_reg[44]\ => SI_REG_n_171,
\m_payload_i_reg[46]\ => SI_REG_n_177,
\m_payload_i_reg[47]\ => SI_REG_n_175,
\m_payload_i_reg[51]\ => SI_REG_n_176,
\m_payload_i_reg[64]\(35 downto 24) => s_arid(11 downto 0),
\m_payload_i_reg[64]\(23) => SI_REG_n_79,
\m_payload_i_reg[64]\(22) => SI_REG_n_80,
\m_payload_i_reg[64]\(21) => SI_REG_n_81,
\m_payload_i_reg[64]\(20) => SI_REG_n_82,
\m_payload_i_reg[64]\(19 downto 16) => si_rs_arlen(3 downto 0),
\m_payload_i_reg[64]\(15) => si_rs_arburst(1),
\m_payload_i_reg[64]\(14) => SI_REG_n_88,
\m_payload_i_reg[64]\(13 downto 12) => si_rs_arsize(1 downto 0),
\m_payload_i_reg[64]\(11 downto 0) => si_rs_araddr(11 downto 0),
\m_payload_i_reg[6]\ => SI_REG_n_187,
\m_payload_i_reg[6]_0\(6) => SI_REG_n_188,
\m_payload_i_reg[6]_0\(5) => SI_REG_n_189,
\m_payload_i_reg[6]_0\(4) => SI_REG_n_190,
\m_payload_i_reg[6]_0\(3) => SI_REG_n_191,
\m_payload_i_reg[6]_0\(2) => SI_REG_n_192,
\m_payload_i_reg[6]_0\(1) => SI_REG_n_193,
\m_payload_i_reg[6]_0\(0) => SI_REG_n_194,
\r_arid_r_reg[11]\(11 downto 0) => s_arid_r(11 downto 0),
r_push_r_reg => \RD.ar_channel_0_n_11\,
r_rlast => r_rlast,
sel_first => \cmd_translator_0/incr_cmd_0/sel_first\,
si_rs_arvalid => si_rs_arvalid,
\wrap_boundary_axaddr_r_reg[11]\ => \RD.ar_channel_0_n_8\,
wrap_second_len(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(1),
\wrap_second_len_r_reg[3]\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(3 downto 2),
\wrap_second_len_r_reg[3]\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(0),
\wrap_second_len_r_reg[3]_0\(2) => SI_REG_n_165,
\wrap_second_len_r_reg[3]_0\(1) => SI_REG_n_166,
\wrap_second_len_r_reg[3]_0\(0) => SI_REG_n_167
);
\RD.r_channel_0\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_r_channel
port map (
D(11 downto 0) => s_arid_r(11 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\in\(33 downto 0) => \in\(33 downto 0),
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
m_valid_i_reg => \RD.r_channel_0_n_2\,
\out\(33 downto 32) => si_rs_rresp(1 downto 0),
\out\(31 downto 0) => si_rs_rdata(31 downto 0),
r_rlast => r_rlast,
s_ready_i_reg => SI_REG_n_178,
si_rs_rready => si_rs_rready,
\skid_buffer_reg[46]\(12 downto 1) => si_rs_rid(11 downto 0),
\skid_buffer_reg[46]\(0) => si_rs_rlast,
\state_reg[1]_rep\ => \RD.r_channel_0_n_0\,
\state_reg[1]_rep_0\ => \RD.ar_channel_0_n_11\
);
SI_REG: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice
port map (
CO(0) => SI_REG_n_134,
D(2 downto 1) => wrap_cnt(3 downto 2),
D(0) => wrap_cnt(0),
E(0) => \aw_pipe/p_1_in\,
O(3) => SI_REG_n_135,
O(2) => SI_REG_n_136,
O(1) => SI_REG_n_137,
O(0) => SI_REG_n_138,
Q(58 downto 47) => s_awid(11 downto 0),
Q(46) => SI_REG_n_20,
Q(45) => SI_REG_n_21,
Q(44) => SI_REG_n_22,
Q(43) => SI_REG_n_23,
Q(42 downto 39) => si_rs_awlen(3 downto 0),
Q(38) => si_rs_awburst(1),
Q(37) => SI_REG_n_29,
Q(36 downto 35) => si_rs_awsize(1 downto 0),
Q(34 downto 12) => Q(22 downto 0),
Q(11 downto 0) => si_rs_awaddr(11 downto 0),
S(3) => \WR.aw_channel_0_n_54\,
S(2) => \WR.aw_channel_0_n_55\,
S(1) => \WR.aw_channel_0_n_56\,
S(0) => \WR.aw_channel_0_n_57\,
aclk => aclk,
aresetn => aresetn,
axaddr_incr_reg(3 downto 0) => \cmd_translator_0/incr_cmd_0/axaddr_incr_reg_5\(3 downto 0),
\axaddr_incr_reg[11]\(7 downto 0) => C(11 downto 4),
\axaddr_incr_reg[11]_0\(3) => SI_REG_n_143,
\axaddr_incr_reg[11]_0\(2) => SI_REG_n_144,
\axaddr_incr_reg[11]_0\(1) => SI_REG_n_145,
\axaddr_incr_reg[11]_0\(0) => SI_REG_n_146,
\axaddr_incr_reg[3]\(3) => SI_REG_n_148,
\axaddr_incr_reg[3]\(2) => SI_REG_n_149,
\axaddr_incr_reg[3]\(1) => SI_REG_n_150,
\axaddr_incr_reg[3]\(0) => SI_REG_n_151,
\axaddr_incr_reg[3]_0\(3 downto 0) => \cmd_translator_0/incr_cmd_0/axaddr_incr_reg\(3 downto 0),
\axaddr_incr_reg[7]\(3) => SI_REG_n_139,
\axaddr_incr_reg[7]\(2) => SI_REG_n_140,
\axaddr_incr_reg[7]\(1) => SI_REG_n_141,
\axaddr_incr_reg[7]\(0) => SI_REG_n_142,
\axaddr_incr_reg[7]_0\(0) => SI_REG_n_147,
axaddr_offset(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(2 downto 0),
axaddr_offset_0(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(2 downto 0),
\axaddr_offset_r_reg[3]\ => SI_REG_n_179,
\axaddr_offset_r_reg[3]_0\ => SI_REG_n_187,
\axaddr_offset_r_reg[3]_1\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(3),
\axaddr_offset_r_reg[3]_2\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\(3 downto 0),
\axaddr_offset_r_reg[3]_3\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(3),
\axaddr_offset_r_reg[3]_4\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(3 downto 0),
\axlen_cnt_reg[3]\ => SI_REG_n_162,
\axlen_cnt_reg[3]_0\ => SI_REG_n_175,
b_push => b_push,
\cnt_read_reg[3]_rep__0\ => SI_REG_n_178,
\cnt_read_reg[4]\(33 downto 32) => si_rs_rresp(1 downto 0),
\cnt_read_reg[4]\(31 downto 0) => si_rs_rdata(31 downto 0),
\cnt_read_reg[4]_rep__0\ => \RD.r_channel_0_n_2\,
\m_axi_araddr[10]\ => SI_REG_n_196,
\m_axi_awaddr[10]\ => SI_REG_n_195,
\m_payload_i_reg[3]\(3) => \RD.ar_channel_0_n_47\,
\m_payload_i_reg[3]\(2) => \RD.ar_channel_0_n_48\,
\m_payload_i_reg[3]\(1) => \RD.ar_channel_0_n_49\,
\m_payload_i_reg[3]\(0) => \RD.ar_channel_0_n_50\,
m_valid_i_reg(0) => \ar_pipe/p_1_in\,
next_pending_r_reg => SI_REG_n_163,
next_pending_r_reg_0 => SI_REG_n_164,
next_pending_r_reg_1 => SI_REG_n_176,
next_pending_r_reg_2 => SI_REG_n_177,
\out\(11 downto 0) => si_rs_bid(11 downto 0),
r_push_r_reg(12 downto 1) => si_rs_rid(11 downto 0),
r_push_r_reg(0) => si_rs_rlast,
\s_arid_r_reg[11]\(58 downto 47) => s_arid(11 downto 0),
\s_arid_r_reg[11]\(46) => SI_REG_n_79,
\s_arid_r_reg[11]\(45) => SI_REG_n_80,
\s_arid_r_reg[11]\(44) => SI_REG_n_81,
\s_arid_r_reg[11]\(43) => SI_REG_n_82,
\s_arid_r_reg[11]\(42 downto 39) => si_rs_arlen(3 downto 0),
\s_arid_r_reg[11]\(38) => si_rs_arburst(1),
\s_arid_r_reg[11]\(37) => SI_REG_n_88,
\s_arid_r_reg[11]\(36 downto 35) => si_rs_arsize(1 downto 0),
\s_arid_r_reg[11]\(34 downto 12) => \m_axi_arprot[2]\(22 downto 0),
\s_arid_r_reg[11]\(11 downto 0) => si_rs_araddr(11 downto 0),
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0),
s_axi_awvalid => s_axi_awvalid,
\s_axi_bid[11]\(13 downto 0) => \s_axi_bid[11]\(13 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
\s_axi_rid[11]\(46 downto 0) => \s_axi_rid[11]\(46 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
\s_bresp_acc_reg[1]\(1 downto 0) => si_rs_bresp(1 downto 0),
sel_first => \cmd_translator_0/incr_cmd_0/sel_first_4\,
sel_first_2 => \cmd_translator_0/incr_cmd_0/sel_first\,
si_rs_arvalid => si_rs_arvalid,
si_rs_awvalid => si_rs_awvalid,
si_rs_bready => si_rs_bready,
si_rs_bvalid => si_rs_bvalid,
si_rs_rready => si_rs_rready,
\state_reg[0]_rep\ => \WR.aw_channel_0_n_10\,
\state_reg[0]_rep_0\ => \RD.ar_channel_0_n_9\,
\state_reg[1]\(1 downto 0) => \ar_cmd_fsm_0/state\(1 downto 0),
\state_reg[1]_0\(1 downto 0) => \aw_cmd_fsm_0/state\(1 downto 0),
\state_reg[1]_rep\ => \WR.aw_channel_0_n_9\,
\state_reg[1]_rep_0\ => \WR.aw_channel_0_n_7\,
\state_reg[1]_rep_1\ => \RD.ar_channel_0_n_8\,
\state_reg[1]_rep_2\ => \RD.ar_channel_0_n_10\,
\wrap_boundary_axaddr_r_reg[6]\(6) => SI_REG_n_180,
\wrap_boundary_axaddr_r_reg[6]\(5) => SI_REG_n_181,
\wrap_boundary_axaddr_r_reg[6]\(4) => SI_REG_n_182,
\wrap_boundary_axaddr_r_reg[6]\(3) => SI_REG_n_183,
\wrap_boundary_axaddr_r_reg[6]\(2) => SI_REG_n_184,
\wrap_boundary_axaddr_r_reg[6]\(1) => SI_REG_n_185,
\wrap_boundary_axaddr_r_reg[6]\(0) => SI_REG_n_186,
\wrap_boundary_axaddr_r_reg[6]_0\(6) => SI_REG_n_188,
\wrap_boundary_axaddr_r_reg[6]_0\(5) => SI_REG_n_189,
\wrap_boundary_axaddr_r_reg[6]_0\(4) => SI_REG_n_190,
\wrap_boundary_axaddr_r_reg[6]_0\(3) => SI_REG_n_191,
\wrap_boundary_axaddr_r_reg[6]_0\(2) => SI_REG_n_192,
\wrap_boundary_axaddr_r_reg[6]_0\(1) => SI_REG_n_193,
\wrap_boundary_axaddr_r_reg[6]_0\(0) => SI_REG_n_194,
\wrap_cnt_r_reg[3]\ => SI_REG_n_158,
\wrap_cnt_r_reg[3]_0\(2) => SI_REG_n_165,
\wrap_cnt_r_reg[3]_0\(1) => SI_REG_n_166,
\wrap_cnt_r_reg[3]_0\(0) => SI_REG_n_167,
\wrap_cnt_r_reg[3]_1\ => SI_REG_n_171,
wrap_second_len(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(1),
wrap_second_len_1(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(1),
\wrap_second_len_r_reg[3]\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(3 downto 2),
\wrap_second_len_r_reg[3]\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(0),
\wrap_second_len_r_reg[3]_0\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(3 downto 2),
\wrap_second_len_r_reg[3]_0\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(0),
\wrap_second_len_r_reg[3]_1\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(3 downto 2),
\wrap_second_len_r_reg[3]_1\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(0),
\wrap_second_len_r_reg[3]_2\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(3 downto 2),
\wrap_second_len_r_reg[3]_2\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(0)
);
\WR.aw_channel_0\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_aw_channel
port map (
CO(0) => SI_REG_n_134,
D(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(1),
E(0) => \aw_pipe/p_1_in\,
O(3) => SI_REG_n_135,
O(2) => SI_REG_n_136,
O(1) => SI_REG_n_137,
O(0) => SI_REG_n_138,
Q(1 downto 0) => \aw_cmd_fsm_0/state\(1 downto 0),
S(3) => \WR.aw_channel_0_n_54\,
S(2) => \WR.aw_channel_0_n_55\,
S(1) => \WR.aw_channel_0_n_56\,
S(0) => \WR.aw_channel_0_n_57\,
aclk => aclk,
areset_d1 => areset_d1,
\axaddr_incr_reg[3]\(3 downto 0) => \cmd_translator_0/incr_cmd_0/axaddr_incr_reg_5\(3 downto 0),
\axaddr_offset_r_reg[3]\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(3),
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\(3 downto 0),
b_push => b_push,
\cnt_read_reg[0]_rep__0\ => \WR.b_channel_0_n_1\,
\cnt_read_reg[1]_rep__1\ => \WR.b_channel_0_n_2\,
\in\(19 downto 8) => b_awid(11 downto 0),
\in\(7 downto 0) => b_awlen(7 downto 0),
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
\m_payload_i_reg[11]\(7 downto 0) => C(11 downto 4),
\m_payload_i_reg[35]\(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(2 downto 0),
\m_payload_i_reg[38]\ => SI_REG_n_195,
\m_payload_i_reg[44]\ => SI_REG_n_158,
\m_payload_i_reg[46]\ => SI_REG_n_164,
\m_payload_i_reg[47]\ => SI_REG_n_162,
\m_payload_i_reg[48]\ => SI_REG_n_163,
\m_payload_i_reg[64]\(35 downto 24) => s_awid(11 downto 0),
\m_payload_i_reg[64]\(23) => SI_REG_n_20,
\m_payload_i_reg[64]\(22) => SI_REG_n_21,
\m_payload_i_reg[64]\(21) => SI_REG_n_22,
\m_payload_i_reg[64]\(20) => SI_REG_n_23,
\m_payload_i_reg[64]\(19 downto 16) => si_rs_awlen(3 downto 0),
\m_payload_i_reg[64]\(15) => si_rs_awburst(1),
\m_payload_i_reg[64]\(14) => SI_REG_n_29,
\m_payload_i_reg[64]\(13 downto 12) => si_rs_awsize(1 downto 0),
\m_payload_i_reg[64]\(11 downto 0) => si_rs_awaddr(11 downto 0),
\m_payload_i_reg[6]\ => SI_REG_n_179,
\m_payload_i_reg[6]_0\(6) => SI_REG_n_180,
\m_payload_i_reg[6]_0\(5) => SI_REG_n_181,
\m_payload_i_reg[6]_0\(4) => SI_REG_n_182,
\m_payload_i_reg[6]_0\(3) => SI_REG_n_183,
\m_payload_i_reg[6]_0\(2) => SI_REG_n_184,
\m_payload_i_reg[6]_0\(1) => SI_REG_n_185,
\m_payload_i_reg[6]_0\(0) => SI_REG_n_186,
sel_first => \cmd_translator_0/incr_cmd_0/sel_first_4\,
si_rs_awvalid => si_rs_awvalid,
\state_reg[1]_rep\ => \WR.aw_channel_0_n_9\,
\state_reg[1]_rep_0\ => \WR.aw_channel_0_n_10\,
\wrap_boundary_axaddr_r_reg[11]\ => \WR.aw_channel_0_n_7\,
\wrap_second_len_r_reg[3]\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(3 downto 2),
\wrap_second_len_r_reg[3]\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(0),
\wrap_second_len_r_reg[3]_0\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(3 downto 2),
\wrap_second_len_r_reg[3]_0\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(0),
\wrap_second_len_r_reg[3]_1\(2 downto 1) => wrap_cnt(3 downto 2),
\wrap_second_len_r_reg[3]_1\(0) => wrap_cnt(0)
);
\WR.b_channel_0\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_b_channel
port map (
aclk => aclk,
areset_d1 => areset_d1,
b_push => b_push,
\cnt_read_reg[0]_rep__0\ => \WR.b_channel_0_n_1\,
\cnt_read_reg[1]_rep__1\ => \WR.b_channel_0_n_2\,
\in\(19 downto 8) => b_awid(11 downto 0),
\in\(7 downto 0) => b_awlen(7 downto 0),
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
\out\(11 downto 0) => si_rs_bid(11 downto 0),
si_rs_bready => si_rs_bready,
si_rs_bvalid => si_rs_bvalid,
\skid_buffer_reg[1]\(1 downto 0) => si_rs_bresp(1 downto 0)
);
areset_d1_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aresetn,
O => areset_d1_i_1_n_0
);
areset_d1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => areset_d1_i_1_n_0,
Q => areset_d1,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 12;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "zynq";
attribute C_IGNORE_ID : integer;
attribute C_IGNORE_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_M_AXI_PROTOCOL : integer;
attribute C_M_AXI_PROTOCOL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute C_S_AXI_PROTOCOL : integer;
attribute C_S_AXI_PROTOCOL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_TRANSLATION_MODE : integer;
attribute C_TRANSLATION_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "yes";
attribute P_AXI3 : integer;
attribute P_AXI3 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "3'b010";
attribute P_CONVERSION : integer;
attribute P_CONVERSION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute P_DECERR : string;
attribute P_DECERR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b11";
attribute P_INCR : string;
attribute P_INCR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b01";
attribute P_PROTECTION : integer;
attribute P_PROTECTION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute P_SLVERR : string;
attribute P_SLVERR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b10";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal \^m_axi_wready\ : STD_LOGIC;
signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_wstrb\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_wvalid\ : STD_LOGIC;
begin
\^m_axi_wready\ <= m_axi_wready;
\^s_axi_wdata\(31 downto 0) <= s_axi_wdata(31 downto 0);
\^s_axi_wstrb\(3 downto 0) <= s_axi_wstrb(3 downto 0);
\^s_axi_wvalid\ <= s_axi_wvalid;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const1>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(11) <= \<const0>\;
m_axi_arid(10) <= \<const0>\;
m_axi_arid(9) <= \<const0>\;
m_axi_arid(8) <= \<const0>\;
m_axi_arid(7) <= \<const0>\;
m_axi_arid(6) <= \<const0>\;
m_axi_arid(5) <= \<const0>\;
m_axi_arid(4) <= \<const0>\;
m_axi_arid(3) <= \<const0>\;
m_axi_arid(2) <= \<const0>\;
m_axi_arid(1) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const1>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const1>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(11) <= \<const0>\;
m_axi_awid(10) <= \<const0>\;
m_axi_awid(9) <= \<const0>\;
m_axi_awid(8) <= \<const0>\;
m_axi_awid(7) <= \<const0>\;
m_axi_awid(6) <= \<const0>\;
m_axi_awid(5) <= \<const0>\;
m_axi_awid(4) <= \<const0>\;
m_axi_awid(3) <= \<const0>\;
m_axi_awid(2) <= \<const0>\;
m_axi_awid(1) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const1>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_wdata(31 downto 0) <= \^s_axi_wdata\(31 downto 0);
m_axi_wid(11) <= \<const0>\;
m_axi_wid(10) <= \<const0>\;
m_axi_wid(9) <= \<const0>\;
m_axi_wid(8) <= \<const0>\;
m_axi_wid(7) <= \<const0>\;
m_axi_wid(6) <= \<const0>\;
m_axi_wid(5) <= \<const0>\;
m_axi_wid(4) <= \<const0>\;
m_axi_wid(3) <= \<const0>\;
m_axi_wid(2) <= \<const0>\;
m_axi_wid(1) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const1>\;
m_axi_wstrb(3 downto 0) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \^s_axi_wvalid\;
s_axi_buser(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_wready <= \^m_axi_wready\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
\gen_axilite.gen_b2s_conv.axilite_b2s\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s
port map (
Q(22 downto 20) => m_axi_awprot(2 downto 0),
Q(19 downto 0) => m_axi_awaddr(31 downto 12),
aclk => aclk,
aresetn => aresetn,
\in\(33 downto 32) => m_axi_rresp(1 downto 0),
\in\(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
\m_axi_arprot[2]\(22 downto 20) => m_axi_arprot(2 downto 0),
\m_axi_arprot[2]\(19 downto 0) => m_axi_araddr(31 downto 12),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0),
s_axi_awvalid => s_axi_awvalid,
\s_axi_bid[11]\(13 downto 2) => s_axi_bid(11 downto 0),
\s_axi_bid[11]\(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
\s_axi_rid[11]\(46 downto 35) => s_axi_rid(11 downto 0),
\s_axi_rid[11]\(34) => s_axi_rlast,
\s_axi_rid[11]\(33 downto 32) => s_axi_rresp(1 downto 0),
\s_axi_rid[11]\(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "zqynq_lab_1_design_auto_pc_1,axi_protocol_converter_v2_1_13_axi_protocol_converter,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "axi_protocol_converter_v2_1_13_axi_protocol_converter,Vivado 2017.2.1";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_inst_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_inst_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of inst : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of inst : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of inst : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of inst : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of inst : label is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of inst : label is 12;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of inst : label is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of inst : label is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of inst : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of inst : label is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "zynq";
attribute C_IGNORE_ID : integer;
attribute C_IGNORE_ID of inst : label is 0;
attribute C_M_AXI_PROTOCOL : integer;
attribute C_M_AXI_PROTOCOL of inst : label is 2;
attribute C_S_AXI_PROTOCOL : integer;
attribute C_S_AXI_PROTOCOL of inst : label is 0;
attribute C_TRANSLATION_MODE : integer;
attribute C_TRANSLATION_MODE of inst : label is 2;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute P_AXI3 : integer;
attribute P_AXI3 of inst : label is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of inst : label is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of inst : label is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of inst : label is "3'b010";
attribute P_CONVERSION : integer;
attribute P_CONVERSION of inst : label is 2;
attribute P_DECERR : string;
attribute P_DECERR of inst : label is "2'b11";
attribute P_INCR : string;
attribute P_INCR of inst : label is "2'b01";
attribute P_PROTECTION : integer;
attribute P_PROTECTION of inst : label is 1;
attribute P_SLVERR : string;
attribute P_SLVERR of inst : label is "2'b10";
begin
inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter
port map (
aclk => aclk,
aresetn => aresetn,
m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_inst_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_inst_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(11 downto 0) => NLW_inst_m_axi_arid_UNCONNECTED(11 downto 0),
m_axi_arlen(7 downto 0) => NLW_inst_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_inst_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_inst_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arregion(3 downto 0) => NLW_inst_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_inst_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_inst_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_inst_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_inst_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(11 downto 0) => NLW_inst_m_axi_awid_UNCONNECTED(11 downto 0),
m_axi_awlen(7 downto 0) => NLW_inst_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_inst_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_inst_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awregion(3 downto 0) => NLW_inst_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_inst_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_inst_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => m_axi_awvalid,
m_axi_bid(11 downto 0) => B"000000000000",
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_buser(0) => '0',
m_axi_bvalid => m_axi_bvalid,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => B"000000000000",
m_axi_rlast => '1',
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_ruser(0) => '0',
m_axi_rvalid => m_axi_rvalid,
m_axi_wdata(31 downto 0) => m_axi_wdata(31 downto 0),
m_axi_wid(11 downto 0) => NLW_inst_m_axi_wid_UNCONNECTED(11 downto 0),
m_axi_wlast => NLW_inst_m_axi_wlast_UNCONNECTED,
m_axi_wready => m_axi_wready,
m_axi_wstrb(3 downto 0) => m_axi_wstrb(3 downto 0),
m_axi_wuser(0) => NLW_inst_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => m_axi_wvalid,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock(0) => s_axi_arlock(0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arregion(3 downto 0) => s_axi_arregion(3 downto 0),
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_aruser(0) => '0',
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awlock(0) => s_axi_awlock(0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awregion(3 downto 0) => s_axi_awregion(3 downto 0),
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awuser(0) => '0',
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wid(11 downto 0) => B"000000000000",
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wuser(0) => '0',
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
| mit | 6ec825f7dff64c909d51479a21bf55c9 | 0.532044 | 2.542907 | false | false | false | false |
khaledhassan/vhdl-examples | multiplexer/mux_2x1.vhd | 1 | 1,798 | -- Copyright (c) 2012 Brian Nezvadovitz <http://nezzen.net>
-- This software is distributed under the terms of the MIT License shown below.
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to
-- deal in the Software without restriction, including without limitation the
-- rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
-- sell copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
-- IN THE SOFTWARE.
-- Multiplexer 2:1
-- Implements a 2-to-1 multiplexer of a given width.
library ieee;
use ieee.std_logic_1164.all;
entity mux_2x1 is
generic (
WIDTH : positive := 1
);
port (
output : out std_logic_vector(WIDTH-1 downto 0);
sel : in std_logic;
in0 : in std_logic_vector(WIDTH-1 downto 0);
in1 : in std_logic_vector(WIDTH-1 downto 0)
);
end mux_2x1;
architecture BHV of mux_2x1 is
begin
output <=
in0 when sel = '0' else
in1 when sel = '1' else
(others => '0');
end BHV;
| mit | c0997aa7a1287213293cf807454ef3a5 | 0.69911 | 3.942982 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-altera-c5ekit/ddr3if.vhd | 1 | 9,531 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
library gaisler;
use gaisler.ddrpkg.all;
entity ddr3if is
generic (
hindex: integer;
haddr: integer := 16#400#;
hmask: integer := 16#000#;
burstlen: integer := 8
);
port (
pll_ref_clk: in std_ulogic;
global_reset_n: in std_ulogic;
mem_a: out std_logic_vector(13 downto 0);
mem_ba: out std_logic_vector(2 downto 0);
mem_ck: out std_ulogic;
mem_ck_n: out std_ulogic;
mem_cke: out std_ulogic;
mem_reset_n: out std_ulogic;
mem_cs_n: out std_ulogic;
mem_dm: out std_logic_vector(3 downto 0);
mem_ras_n: out std_ulogic;
mem_cas_n: out std_ulogic;
mem_we_n: out std_ulogic;
mem_dq: inout std_logic_vector(31 downto 0);
mem_dqs: inout std_logic_vector(3 downto 0);
mem_dqs_n: inout std_logic_vector(3 downto 0);
mem_odt: out std_ulogic;
oct_rzqin: in std_logic;
ahb_clk: in std_ulogic;
ahb_rst: in std_ulogic;
ahbsi: in ahb_slv_in_type;
ahbso: out ahb_slv_out_type
);
end;
architecture rtl of ddr3if is
component ddr3ctrl1 is
port (
pll_ref_clk : in std_logic := 'X'; -- clk
global_reset_n : in std_logic := 'X'; -- reset_n
soft_reset_n : in std_logic := 'X'; -- reset_n
afi_clk : out std_logic; -- clk
afi_half_clk : out std_logic; -- clk
afi_reset_n : out std_logic; -- reset_n
afi_reset_export_n : out std_logic; -- reset_n
mem_a : out std_logic_vector(13 downto 0); -- mem_a
mem_ba : out std_logic_vector(2 downto 0); -- mem_ba
mem_ck : out std_logic_vector(0 downto 0); -- mem_ck
mem_ck_n : out std_logic_vector(0 downto 0); -- mem_ck_n
mem_cke : out std_logic_vector(0 downto 0); -- mem_cke
mem_cs_n : out std_logic_vector(0 downto 0); -- mem_cs_n
mem_dm : out std_logic_vector(3 downto 0); -- mem_dm
mem_ras_n : out std_logic_vector(0 downto 0); -- mem_ras_n
mem_cas_n : out std_logic_vector(0 downto 0); -- mem_cas_n
mem_we_n : out std_logic_vector(0 downto 0); -- mem_we_n
mem_reset_n : out std_logic; -- mem_reset_n
mem_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- mem_dq
mem_dqs : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs
mem_dqs_n : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_n
mem_odt : out std_logic_vector(0 downto 0); -- mem_odt
avl_ready : out std_logic; -- waitrequest_n
avl_burstbegin : in std_logic := 'X'; -- beginbursttransfer
avl_addr : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
avl_rdata_valid : out std_logic; -- readdatavalid
avl_rdata : out std_logic_vector(127 downto 0); -- readdata
avl_wdata : in std_logic_vector(127 downto 0) := (others => 'X'); -- writedata
avl_be : in std_logic_vector(15 downto 0) := (others => 'X'); -- byteenable
avl_read_req : in std_logic := 'X'; -- read
avl_write_req : in std_logic := 'X'; -- write
avl_size : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
local_init_done : out std_logic; -- local_init_done
local_cal_success : out std_logic; -- local_cal_success
local_cal_fail : out std_logic; -- local_cal_fail
oct_rzqin : in std_logic := 'X'; -- rzqin
pll_mem_clk : out std_logic; -- pll_mem_clk
pll_write_clk : out std_logic; -- pll_write_clk
pll_write_clk_pre_phy_clk : out std_logic; -- pll_write_clk_pre_phy_clk
pll_addr_cmd_clk : out std_logic; -- pll_addr_cmd_clk
pll_locked : out std_logic; -- pll_locked
pll_avl_clk : out std_logic; -- pll_avl_clk
pll_config_clk : out std_logic; -- pll_config_clk
pll_mem_phy_clk : out std_logic; -- pll_mem_phy_clk
afi_phy_clk : out std_logic; -- afi_phy_clk
pll_avl_phy_clk : out std_logic -- pll_avl_phy_clk
);
end component ddr3ctrl1;
signal vcc: std_ulogic;
signal afi_clk, afi_half_clk, afi_reset_n: std_ulogic;
signal local_init_done, local_cal_success, local_cal_fail: std_ulogic;
signal ck_p_arr, ck_n_arr, cke_arr, cs_arr: std_logic_vector(0 downto 0);
signal rasn_arr, casn_arr, wen_arr, odt_arr: std_logic_vector(0 downto 0);
signal avlsi: ddravl_slv_in_type;
signal avlso: ddravl_slv_out_type;
begin
vcc <= '1';
mem_ck <= ck_p_arr(0);
mem_ck_n <= ck_n_arr(0);
mem_cke <= cke_arr(0);
mem_cs_n <= cs_arr(0);
mem_ras_n <= rasn_arr(0);
mem_cas_n <= casn_arr(0);
mem_we_n <= wen_arr(0);
mem_odt <= odt_arr(0);
ctrl0: ddr3ctrl1
port map (
pll_ref_clk => pll_ref_clk,
global_reset_n => global_reset_n,
soft_reset_n => vcc,
afi_clk => afi_clk,
afi_half_clk => afi_half_clk,
afi_reset_n => afi_reset_n,
afi_reset_export_n => open,
mem_a => mem_a,
mem_ba => mem_ba,
mem_ck => ck_p_arr,
mem_ck_n => ck_n_arr,
mem_cke => cke_arr,
mem_cs_n => cs_arr,
mem_dm => mem_dm,
mem_ras_n => rasn_arr,
mem_cas_n => casn_arr,
mem_we_n => wen_arr,
mem_reset_n => mem_reset_n,
mem_dq => mem_dq,
mem_dqs => mem_dqs,
mem_dqs_n => mem_dqs_n,
mem_odt => odt_arr,
avl_ready => avlso.ready,
avl_burstbegin => avlsi.burstbegin,
avl_addr => avlsi.addr(24 downto 0),
avl_rdata_valid => avlso.rdata_valid,
avl_rdata => avlso.rdata(127 downto 0),
avl_wdata => avlsi.wdata(127 downto 0),
avl_be => avlsi.be(15 downto 0),
avl_read_req => avlsi.read_req,
avl_write_req => avlsi.write_req,
avl_size => avlsi.size(2 downto 0),
local_init_done => local_init_done,
local_cal_success => local_cal_success,
local_cal_fail => local_cal_fail,
oct_rzqin => oct_rzqin,
pll_mem_clk => open,
pll_write_clk => open,
pll_write_clk_pre_phy_clk => open,
pll_addr_cmd_clk => open,
pll_locked => open,
pll_avl_clk => open,
pll_config_clk => open,
pll_mem_phy_clk => open,
afi_phy_clk => open,
pll_avl_phy_clk => open
);
avlso.rdata(avlso.rdata'high downto 128) <= (others => '0');
ahb2avl0: ahb2avl_async
generic map (
hindex => hindex,
haddr => haddr,
hmask => hmask,
burstlen => burstlen,
nosync => 0,
avldbits => 128,
avlabits => 25
)
port map (
rst_ahb => ahb_rst,
clk_ahb => ahb_clk,
ahbsi => ahbsi,
ahbso => ahbso,
rst_avl => afi_reset_n,
clk_avl => afi_clk,
avlsi => avlsi,
avlso => avlso
);
end;
| gpl-2.0 | db8cd8f4f752a8b201d833489fd903e8 | 0.47078 | 3.595247 | false | false | false | false |
eamadio/fpgaMSP430 | fmsp430/per/fmsp_clock_module.vhd | 1 | 18,851 | ------------------------------------------------------------------------------
--! Copyright (C) 2009 , Olivier Girard
--
--! Redistribution and use in source and binary forms, with or without
--! modification, are permitted provided that the following conditions
--! are met:
--! * Redistributions of source code must retain the above copyright
--! notice, this list of conditions and the following disclaimer.
--! * Redistributions in binary form must reproduce the above copyright
--! notice, this list of conditions and the following disclaimer in the
--! documentation and/or other materials provided with the distribution.
--! * Neither the name of the authors nor the names of its contributors
--! may be used to endorse or promote products derived from this software
--! without specific prior written permission.
--
--! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
--! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
--! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
--! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
--! OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
--! THE POSSIBILITY OF SUCH DAMAGE
--
------------------------------------------------------------------------------
--
--! @file fmsp_clock_module.vhd
--!
--! @brief fpgaMSP430 Basic clock module implementation.
--
--! @author Olivier Girard, [email protected]
--! @author Emmanuel Amadio, [email protected] (VHDL Rewrite)
--
------------------------------------------------------------------------------
--! @version 1
--! @date: 2017-04-21
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all; --! standard unresolved logic UX01ZWLH-
use ieee.numeric_std.all; --! for the signed, unsigned types and arithmetic ops
use ieee.math_real.all;
use work.fmsp_misc_package.all;
use work.fmsp_per_package.all;
use work.fmsp_functions.all;
entity fmsp_clock_module is
generic (
INST_NR : integer := 0; --! Current fmsp instance number (for multicore systems)
TOTAL_NR : integer := 0; --! Total number of fmsp instances-1 (for multicore systems)
PMEM_SIZE : integer := 32768; --! Program Memory Size
DMEM_SIZE : integer := 16384; --! Data Memory Size
PER_SIZE : integer := 16384; --! Peripheral Memory Size
DEBUG_EN : boolean := false; --! Include/Exclude Serial Debug interface
WATCHDOG : boolean := false; --! Include/Exclude Watchdog timer
DMA_IF_EN : boolean := false; --! Include/Exclude DMA interface support
NMI_EN : boolean := false --! Include/Exclude Non-Maskable-Interrupt support
);
port (
mclk : in std_logic; --! Main system clock
--! INPUTs
cpu_en : in std_logic; --! Enable CPU code execution (asynchronous)
cpuoff : in std_logic; --! Turns off the CPU
dbg_cpu_reset : in std_logic; --! Reset CPU from debug interface
dbg_en : in std_logic; --! Debug interface enable (asynchronous)
lfxt_clk : in std_logic; --! Low frequency oscillator (typ 32kHz)
oscoff : in std_logic; --! Turns off LFXT1 clock input
per_addr : in std_logic_vector(13 downto 0); --! Peripheral address
per_din : in std_logic_vector(15 downto 0); --! Peripheral data input
per_en : in std_logic; --! Peripheral enable (high active)
per_we : in std_logic_vector(1 downto 0); --! Peripheral write enable (high active)
reset_n : in std_logic; --! Reset Pin (low active, asynchronous)
scg1 : in std_logic; --! System clock generator 1. Turns off the SMCLK
wdt_reset : in std_logic; --! Watchdog-timer reset
--! OUTPUTs
dbg_rst : out std_logic; --! Debug unit reset
per_dout : out std_logic_vector(15 downto 0); --! Peripheral data output
por : out std_logic; --! Power-on reset
puc_pnd_set : out std_logic; --! PUC pending set for the serial debug interface
puc_rst : out std_logic; --! Main system reset
aclk_en : out std_logic; --! ACLK enable
smclk_en : out std_logic --! SMCLK enable
);
end entity fmsp_clock_module;
architecture RTL of fmsp_clock_module is
--=============================================================================
--! 1) WIRES & PARAMETER DECLARATION
--=============================================================================
--! Register base address (must be aligned to decoder bit width)
constant BASE_ADDR : std_logic_vector(14 downto 0) := "000000000000000";
--! Decoder bit width (defines how many bits are considered for address decoding)
constant DEC_WD : integer := 4;
--! Register addresses offset
constant BCSCTL1 : integer := 7;
constant BCSCTL2 : integer := 8;
--! Register one-hot decoder utilities
constant DEC_SZ : integer := (2**DEC_WD);
type fmsp_clock_module_in_type is record
cpu_en : std_logic; --! Enable CPU code execution (asynchronous)
cpuoff : std_logic; --! Turns off the CPU
dbg_cpu_reset : std_logic; --! Reset CPU from debug interface
dbg_en : std_logic; --! Debug interface enable (asynchronous)
dco_clk : std_logic; --! Fast oscillator (fast clock)
lfxt_clk : std_logic; --! Low frequency oscillator (typ 32kHz)
oscoff : std_logic; --! Turns off LFXT1 clock input
per_addr : std_logic_vector(13 downto 0); --! Peripheral address
per_din : std_logic_vector(15 downto 0); --! Peripheral data input
per_en : std_logic; --! Peripheral enable (high active)
per_we : std_logic_vector(1 downto 0); --! Peripheral write enable (high active)
reset_n : std_logic; --! Reset Pin (low active, asynchronous)
scg1 : std_logic; --! System clock generator 1. Turns off the SMCLK
wdt_reset : std_logic; --! Watchdog-timer reset
puc_rst : std_logic; --! Watchdog-timer reset
por_noscan : std_logic;
puc_noscan_n : std_logic;
puc_s : std_logic;
end record;
type reg_type is record
--! To outside of module
bcsctl1 : std_logic_vector(7 downto 0); --! BCSCTL1 Register
bcsctl2 : std_logic_vector(7 downto 0); --! BCSCTL2 Register
lfxt_clk_dly : std_logic;
aclk_en : std_logic; --! ACLK GENERATION
aclk_div : unsigned(2 downto 0);
smclk_en : std_logic;
smclk_div : unsigned(2 downto 0);
dbg_rst : std_logic; --! Reset Generation
end record;
signal d : fmsp_clock_module_in_type;
signal r : reg_type := (
bcsctl1 => (Others => '0'),
bcsctl2 => (Others => '0'),
lfxt_clk_dly => '0',
aclk_en => '0',
aclk_div => (Others => '0'),
smclk_en => '0',
smclk_div => (Others => '0'),
dbg_rst => '1'
);
signal rin : reg_type;
begin
d.cpu_en <= cpu_en;
d.cpuoff <= cpuoff;
d.dbg_cpu_reset <= dbg_cpu_reset;
d.dbg_en <= dbg_en;
d.lfxt_clk <= lfxt_clk;
d.oscoff <= oscoff;
d.per_addr <= per_addr;
d.per_din <= per_din;
d.per_en <= per_en;
d.per_we <= per_we;
d.reset_n <= reset_n;
d.scg1 <= scg1;
d.wdt_reset <= wdt_reset;
COMB : process (d, r)
variable v : reg_type;
--! Local register selection
variable v_reg_sel : std_logic;
--! Register local address
variable v_reg_addr : std_logic_vector(DEC_WD-2 downto 0);
--! Register address decode
variable v_reg_dec : std_logic_vector((DEC_SZ/2)-1 downto 0);
--! Read/Write probes
variable v_reg_lo_write : std_logic;
variable v_reg_hi_write : std_logic;
variable v_reg_read : std_logic;
--! Read/Write vectors
variable v_reg_wr : std_logic_vector(DEC_SZ-1 downto 0);
variable v_reg_rd : std_logic_vector(DEC_SZ-1 downto 0);
--! BCSCTL1 Register
variable v_bcsctl1_wr : std_logic;
variable v_bcsctl1_nxt : std_logic_vector(7 downto 0);
variable v_bcsctl1_mask : std_logic_vector(7 downto 0);
--! BCSCTL2 Register
variable v_bcsctl2_wr : std_logic;
variable v_bcsctl2_nxt : std_logic_vector(7 downto 0);
variable v_bcsctl2_mask : std_logic_vector(7 downto 0);
--! Data output mux
variable v_bcsctl1_rd : std_logic_vector(15 downto 0);
variable v_bcsctl2_rd : std_logic_vector(15 downto 0);
variable v_per_dout : std_logic_vector(15 downto 0);
--! Synchronize LFXT_CLK & edge detection
variable v_lfxt_clk_en : std_logic;
--! Synchronize CPU_EN signal to the ACLK domain
------------------------------------------------
variable v_mclk_div_sel : std_logic;
--! ACLK GENERATION
variable v_aclk_en_nxt : std_logic;
--! Clock MUX
variable v_smclk_in : std_logic;
variable v_smclk_en_nxt : std_logic;
--! Synchronize DBG_EN signal to MCLK domain
variable v_dbg_rst_nxt : std_logic;
--! Asynchronous reset source
--! Scan Reset Mux
-- variable v_dbg_rst : std_logic;
--! Generate main system reset (PUC_RST)
variable v_puc_noscan_n : std_logic;
--! Reset Synchronizer
--! (required because of the asynchronous watchdog reset)
variable v_puc_rst : std_logic;
--! PUC pending set the serial debug interface
variable v_puc_pnd_set : std_logic;
begin
--! default assignment
v := r;
--! overriding assignments
--============================================================================
--! 2) REGISTER DECODER
--============================================================================
--! Local register selection
if ( d.per_addr(13 downto DEC_WD-1) = BASE_ADDR(14 downto DEC_WD) ) then
v_reg_sel := d.per_en;
else
v_reg_sel := '0';
end if;
--! Register local address
v_reg_addr := d.per_addr(DEC_WD-2 downto 0);
--! Register address decode
v_reg_dec := onehot(v_reg_addr);
--! Read/Write probes
v_reg_lo_write := v_reg_sel and d.per_we(0);
v_reg_hi_write := v_reg_sel and d.per_we(1);
v_reg_read := v_reg_sel and not(d.per_we(0) or d.per_we(1));
--! Read/Write vectors
for i in 0 to (DEC_SZ/2)-1 loop
v_reg_wr((i*2)+0) := v_reg_dec(i) and v_reg_lo_write;
v_reg_wr((i*2)+1) := v_reg_dec(i) and v_reg_hi_write;
v_reg_rd((i*2)+0) := v_reg_dec(i) and v_reg_read;
v_reg_rd((i*2)+1) := v_reg_dec(i) and v_reg_read;
end loop;
--============================================================================
--! 3) REGISTERS
--============================================================================
--! BCSCTL1 Register
----------------
v_bcsctl1_wr := v_reg_wr(BCSCTL1);
v_bcsctl1_nxt := byte_per_select_din( BCSCTL1, d.per_din );
if (DMA_IF_EN = true) then
v_bcsctl1_mask := x"3A";
else
v_bcsctl1_mask := x"30";
end if;
if (v_bcsctl1_wr = '1') then
v.bcsctl1 := v_bcsctl1_nxt and v_bcsctl1_mask; --! Mask unused bits
end if;
--! BCSCTL2 Register
----------------
v_bcsctl2_wr := v_reg_wr(BCSCTL2);
v_bcsctl2_nxt := byte_per_select_din( BCSCTL2, d.per_din );
v_bcsctl2_mask := x"0E";
if (v_bcsctl2_wr = '1') then
v.bcsctl2 := v_bcsctl2_nxt and v_bcsctl2_mask; --! Mask unused bits
end if;
--============================================================================
--! 4) DATA OUTPUT GENERATION
--============================================================================
v_bcsctl1_rd := byte_per_select_dout( BCSCTL1, v_reg_rd, r.bcsctl1 );
v_bcsctl2_rd := byte_per_select_dout( BCSCTL2, v_reg_rd, r.bcsctl2 );
--! Data output mux
v_per_dout := v_bcsctl1_rd or v_bcsctl2_rd;
--=============================================================================
--! 5) DCO_CLK / LFXT_CLK INTERFACES (WAKEUP, ENABLE, ...)
--=============================================================================
-------------------------------------------------------------
--! 5.2) LOW FREQUENCY CRYSTAL CLOCK GENERATOR (LFXT_CLK)
-------------------------------------------------------------
--! Synchronize LFXT_CLK & edge detection
v.lfxt_clk_dly := d.lfxt_clk;
v_lfxt_clk_en := d.lfxt_clk and not(r.lfxt_clk_dly) and not(d.oscoff);
--=============================================================================
--! 6) CLOCK GENERATION
--=============================================================================
-------------------------------------------------------------
--! 6.1) GLOBAL CPU ENABLE
------------------------------------------------------------
--! ACLK and SMCLK are directly switched-off
--! with the cpu_en pin (after synchronization).
--! MCLK will be switched off once the CPU reaches
--! its IDLE state (through the mclk_enable signal)
-------------------------------------------------------------
--! 6.3) ACLK GENERATION
-------------------------------------------------------------
v_aclk_en_nxt := '0';
if (v_lfxt_clk_en = '1') then
if (r.bcsctl1(5 downto 4) = "00") then -- Divide mclk by 1
v_aclk_en_nxt := '1';
elsif (r.bcsctl1(5 downto 4) = "01") then -- Divide mclk by 2
v_aclk_en_nxt := r.aclk_div(0);
elsif (r.bcsctl1(5 downto 4) = "10") then -- Divide mclk by 4
v_aclk_en_nxt := r.aclk_div(1) and r.aclk_div(0);
else -- Divide mclk by 8
v_aclk_en_nxt := r.aclk_div(1) and r.aclk_div(1) and r.aclk_div(0);
end if;
end if;
if ( (r.bcsctl1(5 downto 4) /= "00") and (v_lfxt_clk_en = '1') ) then
v.aclk_div := r.aclk_div + 1;
end if;
v.aclk_en := v_aclk_en_nxt and d.cpu_en;
-------------------------------------------------------------
--! 6.4) SMCLK GENERATION
-------------------------------------------------------------
if ( d.scg1 = '1' ) then
v_smclk_in := '0';
elsif (r.bcsctl2(C_SELS) = '1') then
v_smclk_in := v_lfxt_clk_en;
else
v_smclk_in := '1';
end if;
v_smclk_en_nxt := '0';
if (v_smclk_in = '1') then
if (r.bcsctl2(2 downto 1) = "00") then -- Divide mclk by 1
v_smclk_en_nxt := '1';
elsif (r.bcsctl2(2 downto 1) = "01") then -- Divide mclk by 2
v_smclk_en_nxt := r.smclk_div(0);
elsif (r.bcsctl2(2 downto 1) = "10") then -- Divide mclk by 4
v_smclk_en_nxt := r.smclk_div(1) and r.smclk_div(0);
else -- Divide mclk by 8
v_smclk_en_nxt := r.smclk_div(2) and r.smclk_div(1) and r.smclk_div(0);
end if;
end if;
if ( (r.bcsctl2(2 downto 1) /= "00") and (v_smclk_in = '1') ) then
v.smclk_div := r.smclk_div + 1;
end if;
v.smclk_en := v_smclk_en_nxt and d.cpu_en;
--=============================================================================
--! 7) RESET GENERATION
--=============================================================================
--
--! Whenever the reset pin (reset_n) is deasserted, the internal resets of the
--! openMSP430 will be released in the following order:
--! 1- POR
--! 2- DBG_RST (if the sdi interface is enabled, i.e. dbg_en=1)
--! 3- PUC
--
--! Note: releasing the DBG_RST before PUC is particularly important in order
--! to allow the sdi interface to halt the cpu immediately after a PUC.
--
--! Generate synchronized POR to MCLK domain
--------------------------------------------
--! Generate synchronized reset for the SDI
--------------------------------------------
if (DEBUG_EN = true) then
--! Reset Generation
v.dbg_rst := not(d.dbg_en);
else
v.dbg_rst := '1';
end if;
--! Generate main system reset (PUC_RST)
----------------------------------------
--! Asynchronous PUC reset
-- v_puc_a := d.por_noscan or d.wdt_reset;
--! Synchronous PUC reset
-- v_puc_s := d.dbg_cpu_reset or --! With the debug interface command
--! (d.dbg_en and r.dbg_rst and not(d.puc_noscan_n)); --! Sequencing making sure PUC is released
-- --! after DBG_RST if the debug interface is
-- --! enabled at power-on-reset time
--! Scan Reset Mux
-- v_puc_a_scan := v_puc_a;
--! PUC pending set the serial debug interface
v_puc_pnd_set := not(d.puc_noscan_n);
--! drive register inputs
rin <= v;
--! drive module outputs
dbg_rst <= r.dbg_rst; --! Debug unit reset
per_dout <= v_per_dout; --! Peripheral data output
por <= d.por_noscan; --! Power-on reset
puc_pnd_set <= v_puc_pnd_set; --! PUC pending set for the serial debug interface
puc_rst <= d.puc_rst; --! Main system reset
aclk_en <= r.aclk_en; --! ACLK enable
smclk_en <= r.smclk_en; --! SMCLK enable
end process COMB;
-- d.puc_rst <= '0';
d.puc_rst <= not(d.puc_noscan_n);
d.puc_s <= d.dbg_cpu_reset or --! With the debug interface command
(d.dbg_en and r.dbg_rst and not(d.puc_noscan_n)); --! Sequencing making sure PUC is released
--! after DBG_RST if the debug interface is
--! enabled at power-on-reset time
-- d.puc_s <= '0'; --! Sequencing making sure PUC is released
-- --! after DBG_RST if the debug interface is
-- --! enabled at power-on-reset time
REGS_POR : process (mclk,d.por_noscan)
begin
if (d.por_noscan = '1') then
r.dbg_rst <= '1';
elsif rising_edge(mclk) then
r.dbg_rst <= rin.dbg_rst;
end if;
end process REGS_POR;
REGS_PUC : process (mclk,d.puc_rst)
begin
if (d.puc_rst = '1') then
r.bcsctl1 <= (Others => '0');
r.bcsctl2 <= (Others => '0');
r.lfxt_clk_dly <= '1';
r.aclk_en <= '0';
r.aclk_div <= (Others => '0');
r.smclk_en <= '0';
r.smclk_div <= (Others => '0');
elsif rising_edge(mclk) then
r.bcsctl1 <= rin.bcsctl1;
r.bcsctl2 <= rin.bcsctl2;
r.lfxt_clk_dly <= rin.lfxt_clk_dly;
r.aclk_en <= rin.aclk_en;
r.aclk_div <= rin.aclk_div;
r.smclk_en <= rin.smclk_en;
r.smclk_div <= rin.smclk_div;
end if;
end process REGS_PUC;
--! Reset Synchronizer
--! (required because of the asynchronous watchdog reset)
sync_cell_puc : fmsp_sync_cell
port map(
rst => d.por_noscan or wdt_reset,
clk => mclk,
data_in => not(d.puc_s),
data_out => d.puc_noscan_n
);
--! Reset Synchronizer
sync_reset_por : fmsp_sync_reset
port map(
clk => mclk,
rst_a => not(d.reset_n),
rst_s => d.por_noscan
);
end RTL; -- fmsp_clock_module
| bsd-3-clause | 6e15912bc9f952562d01b7a5edbb12ec | 0.544374 | 3.103556 | false | false | false | false |
kloboves/sicxe | vhdl/rs232_in.vhd | 1 | 4,520 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity rs232_in is
Port (
clock_i : in std_logic;
reset_i : in std_logic;
input_i : in std_logic;
data_o : out std_logic_vector(7 downto 0);
receive_o : out std_logic
);
end rs232_in;
architecture behavioral of rs232_in is
-- input sync
signal input_sync : std_logic;
-- delay counter
signal delay_counter : std_logic_vector(8 downto 0);
signal delay_counter_reset : std_logic;
signal delay_counter_half : std_logic;
-- shift register
signal shift_register : std_logic_vector(7 downto 0);
signal shift_register_shift : std_logic;
-- FSM
type state_type is (READY, WAIT_HALF, RECV_START, RECV0, RECV1, RECV2, RECV3,
RECV4, RECV5, RECV6, RECV7, RECV_END);
signal state : state_type;
signal next_state : state_type;
begin
data_o <= shift_register;
-- input sync
input_sync_proc : process(clock_i)
begin
if (rising_edge(clock_i)) then
input_sync <= input_i;
end if;
end process;
-- delay counter (set for 115200 boud)
delay_counter_proc : process(clock_i)
begin
if (rising_edge(clock_i)) then
if (reset_i = '1' or delay_counter_reset = '1') then
delay_counter <= (others => '0');
else
if (delay_counter = "110110010") then
delay_counter <= (others => '0');
else
delay_counter <= delay_counter + 1;
end if;
end if;
end if;
end process;
delay_counter_half_proc : process(delay_counter)
begin
if (delay_counter = "011011001") then
delay_counter_half <= '1';
else
delay_counter_half <= '0';
end if;
end process;
-- shift register
shift_register_proc : process(clock_i)
begin
if (rising_edge(clock_i)) then
if (reset_i = '1') then
shift_register <= (others => '0');
else
if (shift_register_shift = '1') then
shift_register <= input_sync & shift_register(7 downto 1);
else
shift_register <= shift_register;
end if;
end if;
end if;
end process;
-- FSM
sync_proc : process(clock_i)
begin
if (rising_edge(clock_i)) then
if (reset_i = '1') then
state <= READY;
else
state <= next_state;
end if;
end if;
end process;
state_proc : process(state, input_sync, delay_counter_half)
begin
next_state <= state;
case (state) is
when READY =>
if (input_sync = '0') then
next_state <= WAIT_HALF;
end if;
when WAIT_HALF =>
if (delay_counter_half = '1') then
next_state <= RECV_START;
end if;
when RECV_START =>
if (delay_counter_half = '1') then
next_state <= RECV0;
end if;
when RECV0 =>
if (delay_counter_half = '1') then
next_state <= RECV1;
end if;
when RECV1 =>
if (delay_counter_half = '1') then
next_state <= RECV2;
end if;
when RECV2 =>
if (delay_counter_half = '1') then
next_state <= RECV3;
end if;
when RECV3 =>
if (delay_counter_half = '1') then
next_state <= RECV4;
end if;
when RECV4 =>
if (delay_counter_half = '1') then
next_state <= RECV5;
end if;
when RECV5 =>
if (delay_counter_half = '1') then
next_state <= RECV6;
end if;
when RECV6 =>
if (delay_counter_half = '1') then
next_state <= RECV7;
end if;
when RECV7 =>
if (delay_counter_half = '1') then
next_state <= RECV_END;
end if;
when RECV_END =>
if (input_sync = '1') then
next_state <= READY;
end if;
when others =>
end case;
end process;
output_proc : process(state, input_sync, delay_counter_half)
begin
delay_counter_reset <= '0';
shift_register_shift <= '0';
receive_o <= '0';
case (state) is
when READY =>
if (input_sync = '0') then
delay_counter_reset <= '1';
end if;
when WAIT_HALF =>
when RECV_START | RECV0 | RECV1 | RECV2 | RECV3 | RECV4 | RECV5 | RECV6 =>
if (delay_counter_half = '1') then
shift_register_shift <= '1';
end if;
when RECV7 =>
if (delay_counter_half = '1') then
receive_o <= '1';
end if;
when RECV_END =>
when others =>
end case;
end process;
end behavioral;
| mit | 75d0296f7922e6c860d938479d3cc18c | 0.548894 | 3.501162 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_2/embedded_lab_2.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_axi_gpio_0_0/zynq_design_1_axi_gpio_0_0_sim_netlist.vhdl | 1 | 51,912 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Tue Sep 19 09:38:22 2017
-- Host : DarkCube running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/embedded_lab_2/embedded_lab_2.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_axi_gpio_0_0/zynq_design_1_axi_gpio_0_0_sim_netlist.vhdl
-- Design : zynq_design_1_axi_gpio_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_axi_gpio_0_0_GPIO_Core is
port (
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 7 downto 0 );
GPIO_xferAck_i : out STD_LOGIC;
gpio_xferAck_Reg : out STD_LOGIC;
ip2bus_rdack_i : out STD_LOGIC;
ip2bus_wrack_i_D1_reg : out STD_LOGIC;
gpio_io_t : out STD_LOGIC_VECTOR ( 7 downto 0 );
bus2ip_rnw_i_reg : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
SS : in STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_rnw : in STD_LOGIC;
bus2ip_cs : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
rst_reg : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_axi_gpio_0_0_GPIO_Core : entity is "GPIO_Core";
end zynq_design_1_axi_gpio_0_0_GPIO_Core;
architecture STRUCTURE of zynq_design_1_axi_gpio_0_0_GPIO_Core is
signal \^gpio_xferack_i\ : STD_LOGIC;
signal \^gpio_io_o\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^gpio_xferack_reg\ : STD_LOGIC;
signal iGPIO_xferAck : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of iGPIO_xferAck_i_1 : label is "soft_lutpair4";
attribute SOFT_HLUTNM of ip2bus_rdack_i_D1_i_1 : label is "soft_lutpair4";
begin
GPIO_xferAck_i <= \^gpio_xferack_i\;
gpio_io_o(7 downto 0) <= \^gpio_io_o\(7 downto 0);
gpio_xferAck_Reg <= \^gpio_xferack_reg\;
\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_io_o\(7),
Q => D(7),
R => bus2ip_rnw_i_reg
);
\Not_Dual.ALLOUT_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_io_o\(6),
Q => D(6),
R => bus2ip_rnw_i_reg
);
\Not_Dual.ALLOUT_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_io_o\(5),
Q => D(5),
R => bus2ip_rnw_i_reg
);
\Not_Dual.ALLOUT_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_io_o\(4),
Q => D(4),
R => bus2ip_rnw_i_reg
);
\Not_Dual.ALLOUT_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_io_o\(3),
Q => D(3),
R => bus2ip_rnw_i_reg
);
\Not_Dual.ALLOUT_ND.READ_REG_GEN[5].GPIO_DBus_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_io_o\(2),
Q => D(2),
R => bus2ip_rnw_i_reg
);
\Not_Dual.ALLOUT_ND.READ_REG_GEN[6].GPIO_DBus_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_io_o\(1),
Q => D(1),
R => bus2ip_rnw_i_reg
);
\Not_Dual.ALLOUT_ND.READ_REG_GEN[7].GPIO_DBus_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_io_o\(0),
Q => D(0),
R => bus2ip_rnw_i_reg
);
\Not_Dual.gpio_Data_Out_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(7),
Q => \^gpio_io_o\(7),
R => SS(0)
);
\Not_Dual.gpio_Data_Out_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(6),
Q => \^gpio_io_o\(6),
R => SS(0)
);
\Not_Dual.gpio_Data_Out_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(5),
Q => \^gpio_io_o\(5),
R => SS(0)
);
\Not_Dual.gpio_Data_Out_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(4),
Q => \^gpio_io_o\(4),
R => SS(0)
);
\Not_Dual.gpio_Data_Out_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(3),
Q => \^gpio_io_o\(3),
R => SS(0)
);
\Not_Dual.gpio_Data_Out_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(2),
Q => \^gpio_io_o\(2),
R => SS(0)
);
\Not_Dual.gpio_Data_Out_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(1),
Q => \^gpio_io_o\(1),
R => SS(0)
);
\Not_Dual.gpio_Data_Out_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(0),
Q => \^gpio_io_o\(0),
R => SS(0)
);
\Not_Dual.gpio_OE_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => rst_reg(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(7),
Q => gpio_io_t(7),
S => SS(0)
);
\Not_Dual.gpio_OE_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => rst_reg(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(6),
Q => gpio_io_t(6),
S => SS(0)
);
\Not_Dual.gpio_OE_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => rst_reg(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(5),
Q => gpio_io_t(5),
S => SS(0)
);
\Not_Dual.gpio_OE_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => rst_reg(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(4),
Q => gpio_io_t(4),
S => SS(0)
);
\Not_Dual.gpio_OE_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => rst_reg(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(3),
Q => gpio_io_t(3),
S => SS(0)
);
\Not_Dual.gpio_OE_reg[5]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => rst_reg(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(2),
Q => gpio_io_t(2),
S => SS(0)
);
\Not_Dual.gpio_OE_reg[6]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => rst_reg(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(1),
Q => gpio_io_t(1),
S => SS(0)
);
\Not_Dual.gpio_OE_reg[7]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => rst_reg(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(0),
Q => gpio_io_t(0),
S => SS(0)
);
gpio_xferAck_Reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_xferack_i\,
Q => \^gpio_xferack_reg\,
R => SS(0)
);
iGPIO_xferAck_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => bus2ip_cs,
I1 => \^gpio_xferack_reg\,
I2 => \^gpio_xferack_i\,
O => iGPIO_xferAck
);
iGPIO_xferAck_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => iGPIO_xferAck,
Q => \^gpio_xferack_i\,
R => SS(0)
);
ip2bus_rdack_i_D1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^gpio_xferack_i\,
I1 => bus2ip_rnw,
O => ip2bus_rdack_i
);
ip2bus_wrack_i_D1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^gpio_xferack_i\,
I1 => bus2ip_rnw,
O => ip2bus_wrack_i_D1_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_axi_gpio_0_0_address_decoder is
port (
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\Not_Dual.gpio_OE_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\ : out STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
rst_reg : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
bus2ip_rnw_i_reg : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
is_read : in STD_LOGIC;
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
ip2bus_wrack_i_D1 : in STD_LOGIC;
is_write_reg : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
start2_reg : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
gpio_xferAck_Reg : in STD_LOGIC;
GPIO_xferAck_i : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_axi_gpio_0_0_address_decoder : entity is "address_decoder";
end zynq_design_1_axi_gpio_0_0_address_decoder;
architecture STRUCTURE of zynq_design_1_axi_gpio_0_0_address_decoder is
signal \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\ : STD_LOGIC;
signal \^mem_decode_gen[0].cs_out_i_reg[0]_0\ : STD_LOGIC;
signal \^s_axi_arready\ : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
begin
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ <= \^mem_decode_gen[0].cs_out_i_reg[0]_0\;
s_axi_arready <= \^s_axi_arready\;
s_axi_wready <= \^s_axi_wready\;
\MEM_DECODE_GEN[0].cs_out_i[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000000E0"
)
port map (
I0 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I1 => start2_reg,
I2 => s_axi_aresetn,
I3 => \^s_axi_arready\,
I4 => \^s_axi_wready\,
O => \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\
);
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\,
Q => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
R => '0'
);
\Not_Dual.ALLOUT_ND.READ_REG_GEN[7].GPIO_DBus_i[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFF7"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => gpio_xferAck_Reg,
I3 => GPIO_xferAck_i,
O => \Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\
);
\Not_Dual.gpio_Data_Out[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAABAAAA"
)
port map (
I0 => rst_reg,
I1 => Q(1),
I2 => bus2ip_rnw_i_reg,
I3 => Q(0),
I4 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I5 => Q(2),
O => E(0)
);
\Not_Dual.gpio_Data_Out[0]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(7),
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => Q(1),
I3 => s_axi_wdata(15),
O => D(7)
);
\Not_Dual.gpio_Data_Out[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(6),
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => Q(1),
I3 => s_axi_wdata(14),
O => D(6)
);
\Not_Dual.gpio_Data_Out[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(5),
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => Q(1),
I3 => s_axi_wdata(13),
O => D(5)
);
\Not_Dual.gpio_Data_Out[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(4),
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => Q(1),
I3 => s_axi_wdata(12),
O => D(4)
);
\Not_Dual.gpio_Data_Out[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(3),
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => Q(1),
I3 => s_axi_wdata(11),
O => D(3)
);
\Not_Dual.gpio_Data_Out[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(2),
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => Q(1),
I3 => s_axi_wdata(10),
O => D(2)
);
\Not_Dual.gpio_Data_Out[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(1),
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => Q(1),
I3 => s_axi_wdata(9),
O => D(1)
);
\Not_Dual.gpio_Data_Out[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(0),
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => Q(1),
I3 => s_axi_wdata(8),
O => D(0)
);
\Not_Dual.gpio_OE[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAEAAAA"
)
port map (
I0 => rst_reg,
I1 => Q(0),
I2 => Q(1),
I3 => bus2ip_rnw_i_reg,
I4 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I5 => Q(2),
O => \Not_Dual.gpio_OE_reg[0]\(0)
);
s_axi_arready_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAEAAAA"
)
port map (
I0 => ip2bus_rdack_i_D1,
I1 => is_read,
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(2),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(1),
I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(3),
I5 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0),
O => \^s_axi_arready\
);
s_axi_wready_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAEAAAA"
)
port map (
I0 => ip2bus_wrack_i_D1,
I1 => is_write_reg,
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(2),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(1),
I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(3),
I5 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0),
O => \^s_axi_wready\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_axi_gpio_0_0_slave_attachment is
port (
SR : out STD_LOGIC;
\Not_Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC;
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\ : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\Not_Dual.gpio_OE_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\ : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_aresetn : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
ip2bus_wrack_i_D1 : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
gpio_xferAck_Reg : in STD_LOGIC;
GPIO_xferAck_i : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_axi_gpio_0_0_slave_attachment : entity is "slave_attachment";
end zynq_design_1_axi_gpio_0_0_slave_attachment;
architecture STRUCTURE of zynq_design_1_axi_gpio_0_0_slave_attachment is
signal \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^not_dual.gpio_data_out_reg[0]\ : STD_LOGIC;
signal \^sr\ : STD_LOGIC;
signal bus2ip_addr : STD_LOGIC_VECTOR ( 0 to 6 );
signal \bus2ip_addr_i[2]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[3]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[8]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[8]_i_2_n_0\ : STD_LOGIC;
signal bus2ip_rnw_i06_out : STD_LOGIC;
signal clear : STD_LOGIC;
signal is_read : STD_LOGIC;
signal is_read_i_1_n_0 : STD_LOGIC;
signal is_write : STD_LOGIC;
signal is_write_i_1_n_0 : STD_LOGIC;
signal is_write_reg_n_0 : STD_LOGIC;
signal p_0_out : STD_LOGIC_VECTOR ( 1 downto 0 );
signal p_1_in : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_arready\ : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal s_axi_bvalid_i_i_1_n_0 : STD_LOGIC;
signal \s_axi_rdata_i[7]_i_1_n_0\ : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
signal s_axi_rvalid_i_i_1_n_0 : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
signal start2 : STD_LOGIC;
signal start2_i_1_n_0 : STD_LOGIC;
signal state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \state1__2\ : STD_LOGIC;
signal \state[1]_i_3_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \bus2ip_addr_i[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of bus2ip_rnw_i_i_1 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of start2_i_1 : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \state[1]_i_3\ : label is "soft_lutpair1";
begin
\Not_Dual.gpio_Data_Out_reg[0]\ <= \^not_dual.gpio_data_out_reg[0]\;
SR <= \^sr\;
s_axi_arready <= \^s_axi_arready\;
s_axi_bvalid <= \^s_axi_bvalid\;
s_axi_rvalid <= \^s_axi_rvalid\;
s_axi_wready <= \^s_axi_wready\;
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
O => plusOp(0)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
O => plusOp(1)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
O => plusOp(2)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => state(0),
I1 => state(1),
O => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
O => plusOp(3)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(0),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(1),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(2),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(3),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
R => clear
);
I_DECODER: entity work.zynq_design_1_axi_gpio_0_0_address_decoder
port map (
D(7 downto 0) => D(7 downto 0),
E(0) => E(0),
GPIO_xferAck_i => GPIO_xferAck_i,
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(3 downto 0) => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3 downto 0),
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\,
\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\ => \Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\,
\Not_Dual.gpio_OE_reg[0]\(0) => \Not_Dual.gpio_OE_reg[0]\(0),
Q(2) => bus2ip_addr(0),
Q(1) => bus2ip_addr(5),
Q(0) => bus2ip_addr(6),
bus2ip_rnw_i_reg => \^not_dual.gpio_data_out_reg[0]\,
gpio_xferAck_Reg => gpio_xferAck_Reg,
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
is_read => is_read,
is_write_reg => is_write_reg_n_0,
rst_reg => \^sr\,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => \^s_axi_arready\,
s_axi_wdata(15 downto 0) => s_axi_wdata(15 downto 0),
s_axi_wready => \^s_axi_wready\,
start2_reg => start2
);
\bus2ip_addr_i[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"CCCACCCC"
)
port map (
I0 => s_axi_araddr(0),
I1 => s_axi_awaddr(0),
I2 => state(0),
I3 => state(1),
I4 => s_axi_arvalid,
O => \bus2ip_addr_i[2]_i_1_n_0\
);
\bus2ip_addr_i[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"CCCACCCC"
)
port map (
I0 => s_axi_araddr(1),
I1 => s_axi_awaddr(1),
I2 => state(0),
I3 => state(1),
I4 => s_axi_arvalid,
O => \bus2ip_addr_i[3]_i_1_n_0\
);
\bus2ip_addr_i[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000000EA"
)
port map (
I0 => s_axi_arvalid,
I1 => s_axi_awvalid,
I2 => s_axi_wvalid,
I3 => state(1),
I4 => state(0),
O => \bus2ip_addr_i[8]_i_1_n_0\
);
\bus2ip_addr_i[8]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"CCCACCCC"
)
port map (
I0 => s_axi_araddr(2),
I1 => s_axi_awaddr(2),
I2 => state(0),
I3 => state(1),
I4 => s_axi_arvalid,
O => \bus2ip_addr_i[8]_i_2_n_0\
);
\bus2ip_addr_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => \bus2ip_addr_i[2]_i_1_n_0\,
Q => bus2ip_addr(6),
R => \^sr\
);
\bus2ip_addr_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => \bus2ip_addr_i[3]_i_1_n_0\,
Q => bus2ip_addr(5),
R => \^sr\
);
\bus2ip_addr_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => \bus2ip_addr_i[8]_i_2_n_0\,
Q => bus2ip_addr(0),
R => \^sr\
);
bus2ip_rnw_i_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"10"
)
port map (
I0 => state(0),
I1 => state(1),
I2 => s_axi_arvalid,
O => bus2ip_rnw_i06_out
);
bus2ip_rnw_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => bus2ip_rnw_i06_out,
Q => \^not_dual.gpio_data_out_reg[0]\,
R => \^sr\
);
is_read_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"3FFA000A"
)
port map (
I0 => s_axi_arvalid,
I1 => \state1__2\,
I2 => state(0),
I3 => state(1),
I4 => is_read,
O => is_read_i_1_n_0
);
is_read_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_read_i_1_n_0,
Q => is_read,
R => \^sr\
);
is_write_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0040FFFF00400000"
)
port map (
I0 => s_axi_arvalid,
I1 => s_axi_awvalid,
I2 => s_axi_wvalid,
I3 => state(1),
I4 => is_write,
I5 => is_write_reg_n_0,
O => is_write_i_1_n_0
);
is_write_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"F88800000000FFFF"
)
port map (
I0 => \^s_axi_rvalid\,
I1 => s_axi_rready,
I2 => \^s_axi_bvalid\,
I3 => s_axi_bready,
I4 => state(0),
I5 => state(1),
O => is_write
);
is_write_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_write_i_1_n_0,
Q => is_write_reg_n_0,
R => \^sr\
);
rst_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_aresetn,
O => p_1_in
);
rst_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_1_in,
Q => \^sr\,
R => '0'
);
s_axi_bvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_wready\,
I1 => state(1),
I2 => state(0),
I3 => s_axi_bready,
I4 => \^s_axi_bvalid\,
O => s_axi_bvalid_i_i_1_n_0
);
s_axi_bvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_bvalid_i_i_1_n_0,
Q => \^s_axi_bvalid\,
R => \^sr\
);
\s_axi_rdata_i[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => state(0),
I1 => state(1),
O => \s_axi_rdata_i[7]_i_1_n_0\
);
\s_axi_rdata_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[7]_i_1_n_0\,
D => Q(0),
Q => s_axi_rdata(0),
R => \^sr\
);
\s_axi_rdata_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[7]_i_1_n_0\,
D => Q(1),
Q => s_axi_rdata(1),
R => \^sr\
);
\s_axi_rdata_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[7]_i_1_n_0\,
D => Q(2),
Q => s_axi_rdata(2),
R => \^sr\
);
\s_axi_rdata_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[7]_i_1_n_0\,
D => Q(3),
Q => s_axi_rdata(3),
R => \^sr\
);
\s_axi_rdata_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[7]_i_1_n_0\,
D => Q(4),
Q => s_axi_rdata(4),
R => \^sr\
);
\s_axi_rdata_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[7]_i_1_n_0\,
D => Q(5),
Q => s_axi_rdata(5),
R => \^sr\
);
\s_axi_rdata_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[7]_i_1_n_0\,
D => Q(6),
Q => s_axi_rdata(6),
R => \^sr\
);
\s_axi_rdata_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[7]_i_1_n_0\,
D => Q(7),
Q => s_axi_rdata(7),
R => \^sr\
);
s_axi_rvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_arready\,
I1 => state(0),
I2 => state(1),
I3 => s_axi_rready,
I4 => \^s_axi_rvalid\,
O => s_axi_rvalid_i_i_1_n_0
);
s_axi_rvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_rvalid_i_i_1_n_0,
Q => \^s_axi_rvalid\,
R => \^sr\
);
start2_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"000000F8"
)
port map (
I0 => s_axi_awvalid,
I1 => s_axi_wvalid,
I2 => s_axi_arvalid,
I3 => state(1),
I4 => state(0),
O => start2_i_1_n_0
);
start2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => start2_i_1_n_0,
Q => start2,
R => \^sr\
);
\state[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"77FC44FC"
)
port map (
I0 => \state1__2\,
I1 => state(0),
I2 => s_axi_arvalid,
I3 => state(1),
I4 => \^s_axi_wready\,
O => p_0_out(0)
);
\state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"5FFC50FC"
)
port map (
I0 => \state1__2\,
I1 => \state[1]_i_3_n_0\,
I2 => state(1),
I3 => state(0),
I4 => \^s_axi_arready\,
O => p_0_out(1)
);
\state[1]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
O => \state1__2\
);
\state[1]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => s_axi_wvalid,
I1 => s_axi_awvalid,
I2 => s_axi_arvalid,
O => \state[1]_i_3_n_0\
);
\state_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_out(0),
Q => state(0),
R => \^sr\
);
\state_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_out(1),
Q => state(1),
R => \^sr\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_axi_gpio_0_0_axi_lite_ipif is
port (
bus2ip_reset : out STD_LOGIC;
bus2ip_rnw : out STD_LOGIC;
bus2ip_cs : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\Not_Dual.gpio_OE_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\ : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_aresetn : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
ip2bus_wrack_i_D1 : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
gpio_xferAck_Reg : in STD_LOGIC;
GPIO_xferAck_i : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_axi_gpio_0_0_axi_lite_ipif : entity is "axi_lite_ipif";
end zynq_design_1_axi_gpio_0_0_axi_lite_ipif;
architecture STRUCTURE of zynq_design_1_axi_gpio_0_0_axi_lite_ipif is
begin
I_SLAVE_ATTACHMENT: entity work.zynq_design_1_axi_gpio_0_0_slave_attachment
port map (
D(7 downto 0) => D(7 downto 0),
E(0) => E(0),
GPIO_xferAck_i => GPIO_xferAck_i,
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\ => bus2ip_cs,
\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\ => \Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\,
\Not_Dual.gpio_Data_Out_reg[0]\ => bus2ip_rnw,
\Not_Dual.gpio_OE_reg[0]\(0) => \Not_Dual.gpio_OE_reg[0]\(0),
Q(7 downto 0) => Q(7 downto 0),
SR => bus2ip_reset,
gpio_xferAck_Reg => gpio_xferAck_Reg,
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(2 downto 0) => s_axi_araddr(2 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(2 downto 0) => s_axi_awaddr(2 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(7 downto 0) => s_axi_rdata(7 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(15 downto 0) => s_axi_wdata(15 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_axi_gpio_0_0_axi_gpio is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 7 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 7 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 7 downto 0 );
gpio2_io_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
gpio2_io_o : out STD_LOGIC_VECTOR ( 31 downto 0 );
gpio2_io_t : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute C_ALL_INPUTS : integer;
attribute C_ALL_INPUTS of zynq_design_1_axi_gpio_0_0_axi_gpio : entity is 0;
attribute C_ALL_INPUTS_2 : integer;
attribute C_ALL_INPUTS_2 of zynq_design_1_axi_gpio_0_0_axi_gpio : entity is 0;
attribute C_ALL_OUTPUTS : integer;
attribute C_ALL_OUTPUTS of zynq_design_1_axi_gpio_0_0_axi_gpio : entity is 1;
attribute C_ALL_OUTPUTS_2 : integer;
attribute C_ALL_OUTPUTS_2 of zynq_design_1_axi_gpio_0_0_axi_gpio : entity is 0;
attribute C_DOUT_DEFAULT : integer;
attribute C_DOUT_DEFAULT of zynq_design_1_axi_gpio_0_0_axi_gpio : entity is 0;
attribute C_DOUT_DEFAULT_2 : integer;
attribute C_DOUT_DEFAULT_2 of zynq_design_1_axi_gpio_0_0_axi_gpio : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of zynq_design_1_axi_gpio_0_0_axi_gpio : entity is "zynq";
attribute C_GPIO2_WIDTH : integer;
attribute C_GPIO2_WIDTH of zynq_design_1_axi_gpio_0_0_axi_gpio : entity is 32;
attribute C_GPIO_WIDTH : integer;
attribute C_GPIO_WIDTH of zynq_design_1_axi_gpio_0_0_axi_gpio : entity is 8;
attribute C_INTERRUPT_PRESENT : integer;
attribute C_INTERRUPT_PRESENT of zynq_design_1_axi_gpio_0_0_axi_gpio : entity is 0;
attribute C_IS_DUAL : integer;
attribute C_IS_DUAL of zynq_design_1_axi_gpio_0_0_axi_gpio : entity is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of zynq_design_1_axi_gpio_0_0_axi_gpio : entity is 9;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of zynq_design_1_axi_gpio_0_0_axi_gpio : entity is 32;
attribute C_TRI_DEFAULT : integer;
attribute C_TRI_DEFAULT of zynq_design_1_axi_gpio_0_0_axi_gpio : entity is -1;
attribute C_TRI_DEFAULT_2 : integer;
attribute C_TRI_DEFAULT_2 of zynq_design_1_axi_gpio_0_0_axi_gpio : entity is -1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_axi_gpio_0_0_axi_gpio : entity is "axi_gpio";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of zynq_design_1_axi_gpio_0_0_axi_gpio : entity is "yes";
attribute ip_group : string;
attribute ip_group of zynq_design_1_axi_gpio_0_0_axi_gpio : entity is "LOGICORE";
end zynq_design_1_axi_gpio_0_0_axi_gpio;
architecture STRUCTURE of zynq_design_1_axi_gpio_0_0_axi_gpio is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_17 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_6 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_7 : STD_LOGIC;
signal DBus_Reg : STD_LOGIC_VECTOR ( 0 to 7 );
signal GPIO_xferAck_i : STD_LOGIC;
signal bus2ip_cs : STD_LOGIC;
signal bus2ip_reset : STD_LOGIC;
signal bus2ip_rnw : STD_LOGIC;
signal gpio_core_1_n_19 : STD_LOGIC;
signal gpio_xferAck_Reg : STD_LOGIC;
signal ip2bus_data : STD_LOGIC_VECTOR ( 24 to 31 );
signal ip2bus_data_i_D1 : STD_LOGIC_VECTOR ( 24 to 31 );
signal ip2bus_rdack_i : STD_LOGIC;
signal ip2bus_rdack_i_D1 : STD_LOGIC;
signal ip2bus_wrack_i_D1 : STD_LOGIC;
signal \^s_axi_rdata\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^s_axi_wready\ : STD_LOGIC;
begin
gpio2_io_o(31) <= \<const0>\;
gpio2_io_o(30) <= \<const0>\;
gpio2_io_o(29) <= \<const0>\;
gpio2_io_o(28) <= \<const0>\;
gpio2_io_o(27) <= \<const0>\;
gpio2_io_o(26) <= \<const0>\;
gpio2_io_o(25) <= \<const0>\;
gpio2_io_o(24) <= \<const0>\;
gpio2_io_o(23) <= \<const0>\;
gpio2_io_o(22) <= \<const0>\;
gpio2_io_o(21) <= \<const0>\;
gpio2_io_o(20) <= \<const0>\;
gpio2_io_o(19) <= \<const0>\;
gpio2_io_o(18) <= \<const0>\;
gpio2_io_o(17) <= \<const0>\;
gpio2_io_o(16) <= \<const0>\;
gpio2_io_o(15) <= \<const0>\;
gpio2_io_o(14) <= \<const0>\;
gpio2_io_o(13) <= \<const0>\;
gpio2_io_o(12) <= \<const0>\;
gpio2_io_o(11) <= \<const0>\;
gpio2_io_o(10) <= \<const0>\;
gpio2_io_o(9) <= \<const0>\;
gpio2_io_o(8) <= \<const0>\;
gpio2_io_o(7) <= \<const0>\;
gpio2_io_o(6) <= \<const0>\;
gpio2_io_o(5) <= \<const0>\;
gpio2_io_o(4) <= \<const0>\;
gpio2_io_o(3) <= \<const0>\;
gpio2_io_o(2) <= \<const0>\;
gpio2_io_o(1) <= \<const0>\;
gpio2_io_o(0) <= \<const0>\;
gpio2_io_t(31) <= \<const1>\;
gpio2_io_t(30) <= \<const1>\;
gpio2_io_t(29) <= \<const1>\;
gpio2_io_t(28) <= \<const1>\;
gpio2_io_t(27) <= \<const1>\;
gpio2_io_t(26) <= \<const1>\;
gpio2_io_t(25) <= \<const1>\;
gpio2_io_t(24) <= \<const1>\;
gpio2_io_t(23) <= \<const1>\;
gpio2_io_t(22) <= \<const1>\;
gpio2_io_t(21) <= \<const1>\;
gpio2_io_t(20) <= \<const1>\;
gpio2_io_t(19) <= \<const1>\;
gpio2_io_t(18) <= \<const1>\;
gpio2_io_t(17) <= \<const1>\;
gpio2_io_t(16) <= \<const1>\;
gpio2_io_t(15) <= \<const1>\;
gpio2_io_t(14) <= \<const1>\;
gpio2_io_t(13) <= \<const1>\;
gpio2_io_t(12) <= \<const1>\;
gpio2_io_t(11) <= \<const1>\;
gpio2_io_t(10) <= \<const1>\;
gpio2_io_t(9) <= \<const1>\;
gpio2_io_t(8) <= \<const1>\;
gpio2_io_t(7) <= \<const1>\;
gpio2_io_t(6) <= \<const1>\;
gpio2_io_t(5) <= \<const1>\;
gpio2_io_t(4) <= \<const1>\;
gpio2_io_t(3) <= \<const1>\;
gpio2_io_t(2) <= \<const1>\;
gpio2_io_t(1) <= \<const1>\;
gpio2_io_t(0) <= \<const1>\;
ip2intc_irpt <= \<const0>\;
s_axi_awready <= \^s_axi_wready\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7 downto 0) <= \^s_axi_rdata\(7 downto 0);
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_wready <= \^s_axi_wready\;
AXI_LITE_IPIF_I: entity work.zynq_design_1_axi_gpio_0_0_axi_lite_ipif
port map (
D(7) => DBus_Reg(0),
D(6) => DBus_Reg(1),
D(5) => DBus_Reg(2),
D(4) => DBus_Reg(3),
D(3) => DBus_Reg(4),
D(2) => DBus_Reg(5),
D(1) => DBus_Reg(6),
D(0) => DBus_Reg(7),
E(0) => AXI_LITE_IPIF_I_n_6,
GPIO_xferAck_i => GPIO_xferAck_i,
\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\ => AXI_LITE_IPIF_I_n_17,
\Not_Dual.gpio_OE_reg[0]\(0) => AXI_LITE_IPIF_I_n_7,
Q(7) => ip2bus_data_i_D1(24),
Q(6) => ip2bus_data_i_D1(25),
Q(5) => ip2bus_data_i_D1(26),
Q(4) => ip2bus_data_i_D1(27),
Q(3) => ip2bus_data_i_D1(28),
Q(2) => ip2bus_data_i_D1(29),
Q(1) => ip2bus_data_i_D1(30),
Q(0) => ip2bus_data_i_D1(31),
bus2ip_cs => bus2ip_cs,
bus2ip_reset => bus2ip_reset,
bus2ip_rnw => bus2ip_rnw,
gpio_xferAck_Reg => gpio_xferAck_Reg,
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(2) => s_axi_araddr(8),
s_axi_araddr(1 downto 0) => s_axi_araddr(3 downto 2),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(2) => s_axi_awaddr(8),
s_axi_awaddr(1 downto 0) => s_axi_awaddr(3 downto 2),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(7 downto 0) => \^s_axi_rdata\(7 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(15 downto 8) => s_axi_wdata(31 downto 24),
s_axi_wdata(7 downto 0) => s_axi_wdata(7 downto 0),
s_axi_wready => \^s_axi_wready\,
s_axi_wvalid => s_axi_wvalid
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
gpio_core_1: entity work.zynq_design_1_axi_gpio_0_0_GPIO_Core
port map (
D(7) => ip2bus_data(24),
D(6) => ip2bus_data(25),
D(5) => ip2bus_data(26),
D(4) => ip2bus_data(27),
D(3) => ip2bus_data(28),
D(2) => ip2bus_data(29),
D(1) => ip2bus_data(30),
D(0) => ip2bus_data(31),
E(0) => AXI_LITE_IPIF_I_n_6,
GPIO_xferAck_i => GPIO_xferAck_i,
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\(7) => DBus_Reg(0),
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\(6) => DBus_Reg(1),
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\(5) => DBus_Reg(2),
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\(4) => DBus_Reg(3),
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\(3) => DBus_Reg(4),
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\(2) => DBus_Reg(5),
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\(1) => DBus_Reg(6),
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\(0) => DBus_Reg(7),
SS(0) => bus2ip_reset,
bus2ip_cs => bus2ip_cs,
bus2ip_rnw => bus2ip_rnw,
bus2ip_rnw_i_reg => AXI_LITE_IPIF_I_n_17,
gpio_io_o(7 downto 0) => gpio_io_o(7 downto 0),
gpio_io_t(7 downto 0) => gpio_io_t(7 downto 0),
gpio_xferAck_Reg => gpio_xferAck_Reg,
ip2bus_rdack_i => ip2bus_rdack_i,
ip2bus_wrack_i_D1_reg => gpio_core_1_n_19,
rst_reg(0) => AXI_LITE_IPIF_I_n_7,
s_axi_aclk => s_axi_aclk
);
\ip2bus_data_i_D1_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(24),
Q => ip2bus_data_i_D1(24),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(25),
Q => ip2bus_data_i_D1(25),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(26),
Q => ip2bus_data_i_D1(26),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(27),
Q => ip2bus_data_i_D1(27),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(28),
Q => ip2bus_data_i_D1(28),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(29),
Q => ip2bus_data_i_D1(29),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(30),
Q => ip2bus_data_i_D1(30),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(31),
Q => ip2bus_data_i_D1(31),
R => bus2ip_reset
);
ip2bus_rdack_i_D1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_rdack_i,
Q => ip2bus_rdack_i_D1,
R => bus2ip_reset
);
ip2bus_wrack_i_D1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_core_1_n_19,
Q => ip2bus_wrack_i_D1,
R => bus2ip_reset
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_axi_gpio_0_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
gpio_io_o : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of zynq_design_1_axi_gpio_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of zynq_design_1_axi_gpio_0_0 : entity is "zynq_design_1_axi_gpio_0_0,axi_gpio,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of zynq_design_1_axi_gpio_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of zynq_design_1_axi_gpio_0_0 : entity is "axi_gpio,Vivado 2017.2";
end zynq_design_1_axi_gpio_0_0;
architecture STRUCTURE of zynq_design_1_axi_gpio_0_0 is
signal NLW_U0_ip2intc_irpt_UNCONNECTED : STD_LOGIC;
signal NLW_U0_gpio2_io_o_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_gpio2_io_t_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_gpio_io_t_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
attribute C_ALL_INPUTS : integer;
attribute C_ALL_INPUTS of U0 : label is 0;
attribute C_ALL_INPUTS_2 : integer;
attribute C_ALL_INPUTS_2 of U0 : label is 0;
attribute C_ALL_OUTPUTS : integer;
attribute C_ALL_OUTPUTS of U0 : label is 1;
attribute C_ALL_OUTPUTS_2 : integer;
attribute C_ALL_OUTPUTS_2 of U0 : label is 0;
attribute C_DOUT_DEFAULT : integer;
attribute C_DOUT_DEFAULT of U0 : label is 0;
attribute C_DOUT_DEFAULT_2 : integer;
attribute C_DOUT_DEFAULT_2 of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_GPIO2_WIDTH : integer;
attribute C_GPIO2_WIDTH of U0 : label is 32;
attribute C_GPIO_WIDTH : integer;
attribute C_GPIO_WIDTH of U0 : label is 8;
attribute C_INTERRUPT_PRESENT : integer;
attribute C_INTERRUPT_PRESENT of U0 : label is 0;
attribute C_IS_DUAL : integer;
attribute C_IS_DUAL of U0 : label is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of U0 : label is 9;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of U0 : label is 32;
attribute C_TRI_DEFAULT : integer;
attribute C_TRI_DEFAULT of U0 : label is -1;
attribute C_TRI_DEFAULT_2 : integer;
attribute C_TRI_DEFAULT_2 of U0 : label is -1;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
attribute ip_group : string;
attribute ip_group of U0 : label is "LOGICORE";
begin
U0: entity work.zynq_design_1_axi_gpio_0_0_axi_gpio
port map (
gpio2_io_i(31 downto 0) => B"00000000000000000000000000000000",
gpio2_io_o(31 downto 0) => NLW_U0_gpio2_io_o_UNCONNECTED(31 downto 0),
gpio2_io_t(31 downto 0) => NLW_U0_gpio2_io_t_UNCONNECTED(31 downto 0),
gpio_io_i(7 downto 0) => B"00000000",
gpio_io_o(7 downto 0) => gpio_io_o(7 downto 0),
gpio_io_t(7 downto 0) => NLW_U0_gpio_io_t_UNCONNECTED(7 downto 0),
ip2intc_irpt => NLW_U0_ip2intc_irpt_UNCONNECTED,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(8 downto 0) => s_axi_araddr(8 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(8 downto 0) => s_axi_awaddr(8 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
| mit | 259e6e869bca12d55ed97afc20497108 | 0.551375 | 2.650194 | false | false | false | false |
a4a881d4/ringbus4xilinx | src/example/rbus2.vhd | 1 | 6,829 | ---------------------------------------------------------------------------------------------------
--
-- Title : Two End Point Example for Ring Bus
-- Design : Ring Bus
-- Author : Zhao Ming
-- Company : a4a881d4
--
---------------------------------------------------------------------------------------------------
--
-- File : rbus2.vhd
-- Generated : 2013/9/7
-- From :
-- By :
--
---------------------------------------------------------------------------------------------------
--
-- Description : Ring bus example
-- two end point
--
-- Rev: 3.1
--
---------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.rb_config.all;
use work.dma_config.all;
entity RBUS2 is
port(
-- system
clk : in STD_LOGIC;
rst : in STD_LOGIC;
-- CPU bus
wr : in std_logic;
rd : in std_logic;
addr : in std_logic_vector( 7 downto 0 );
Din : in std_logic_vector( 7 downto 0 );
Dout : out std_logic_vector( 7 downto 0 );
cpuClk : in std_logic;
-- out
viewAout : out std_logic_vector( 9 downto 0 );
viewDout : out std_logic_vector( 127 downto 0 );
viewenout : out std_logic
);
end RBUS2;
architecture behave of RBUS2 is
constant Num : natural := 2;
constant Bwidth : natural := 128;
component blockdram
generic(
depth: integer := 256;
Dwidth: integer := 8;
Awidth: integer := 8
);
port(
addra: IN std_logic_VECTOR(Awidth-1 downto 0);
clka: IN std_logic;
addrb: IN std_logic_VECTOR(Awidth-1 downto 0);
clkb: IN std_logic;
dia: IN std_logic_VECTOR(Dwidth-1 downto 0);
wea: IN std_logic;
reb: IN std_logic;
dob: OUT std_logic_VECTOR(Dwidth-1 downto 0) := (others => '0')
);
end component;
component DUMMYSRC
generic(
Awidth : natural;
Bwidth : natural
);
port(
-- system
clk : in STD_LOGIC;
rst : in STD_LOGIC;
Addr : in std_logic_vector( Awidth-1 downto 0 );
Q : out STD_LOGIC_VECTOR( Bwidth-1 downto 0 );
ren : in STD_LOGIC
);
end component;
signal tx_i : std_logic_vector( Num*Bwidth-1 downto 0 );
signal Req_i : std_logic_vector(Num-1 downto 0):= (others => '0');
signal tx_sop_i : std_logic_vector(Num-1 downto 0):= (others => '0');
signal rx_i : std_logic_vector( Num*Bwidth-1 downto 0 );
signal rx_sop_i : std_logic_vector(Num-1 downto 0):= (others => '0');
signal DMA0H, DMA1H : std_logic_vector( Bwidth-1 downto 0 ) := ( others=>'0' );
signal DMA0A, DMA1A : std_logic_vector( 9 downto 0 ) := ( others=>'0' );
signal DMA0_Req, DMA1_Req : std_logic := '0';
signal DMA0_Busy, DMA1_Busy : std_logic := '0';
signal viewA : std_logic_vector( 9 downto 0 ) := ( others=>'0' );
signal viewD : std_logic_vector( Bwidth-1 downto 0 ) := ( others=>'0' );
signal viewen : std_logic := '0';
signal CS0, CS1 : std_logic := '0';
signal Dout0, Dout1 : std_logic_vector( 7 downto 0 ) := ( others=>'Z' );
signal ramWA, ramRA, dummyA : std_logic_vector( 9 downto 0 ) := ( others=>'0' );
signal ramWD, ramRD, dummyD : std_logic_vector( Bwidth-1 downto 0 ) := ( others=>'0' );
signal ramWen, ramRen, dummyen : std_logic := '0';
begin
bus2:RBUS
generic map(
Bwidth=>128,
Num=>2
)
port map(
-- system
sync =>'0',
clk => clk,
rst => rst,
-- tx
tx => tx_i,
Req => Req_i,
tx_sop => tx_sop_i,
-- rx
rx_sop => rx_sop_i,
rx => rx_i
);
outEP0:EPMEMOUT
generic map (
Awidth => 10,
Bwidth => 128
)
port map(
-- system interface
clk => clk,
rst => rst,
-- bus interface
tx_sop => tx_sop_i(0),
Req => req_i(0),
tx => tx_i((0+1)*Bwidth-1 downto 0*Bwidth),
-- Mem interface
mD => dummyD,
mAddr => dummyA,
mren => dummyen,
-- Local Bus interface
header => DMA0H,
laddr => DMA0A,
Req_in => DMA0_Req,
busy => DMA0_busy
);
outEP1:EPMEMOUT
generic map (
Awidth => 10,
Bwidth => 128
)
port map(
-- system interface
clk => clk,
rst => rst,
-- bus interface
tx_sop => tx_sop_i(1),
Req => req_i(1),
tx => tx_i((1+1)*Bwidth-1 downto 1*Bwidth),
-- Mem interface
mD => ramRD,
mAddr => ramRA,
mren => ramRen,
-- Local Bus interface
header => DMA1H,
laddr => DMA1A,
Req_in => DMA1_Req,
busy => DMA1_busy
);
INEP0:EPMEMIN
generic map(
Awidth => 10,
Bwidth => 128,
CS => "00"
)
port map(
-- system interface
clk => clk,
rst => rst,
-- bus interface
rx_sop => rx_sop_i(0),
rx => rx_i((0+1)*Bwidth-1 downto 0*Bwidth),
-- Mem interface
Addr => viewA,
D => viewD,
wen => viewen
--
);
INEP1:EPMEMIN
generic map(
Awidth => 10,
Bwidth => 128,
CS => "00"
)
port map(
-- system interface
clk => clk,
rst => rst,
-- bus interface
rx_sop => rx_sop_i(1),
rx => rx_i((1+1)*Bwidth-1 downto 1*Bwidth),
-- Mem interface
Addr => ramWA,
D => ramWD,
wen => ramWen
--
);
DMA0:DMANP
generic map(
Bwidth => 128,
SAwidth => 10,
DAwidth => 12,
Lwidth => 10
)
port map(
-- system signal
clk => clk,
rst => rst,
-- Tx interface
header => DMA0H,
Req => DMA0_Req,
laddr => DMA0A,
busy => DMA0_Busy,
tx_sop => tx_sop_i(0),
-- CPU bus
CS => CS0,
wr => wr,
rd => rd,
addr => addr( 3 downto 0 ),
Din => Din,
Dout => Dout0,
cpuClk => cpuClk,
-- Priority
en => '1'
);
DMA1:DMANP
generic map(
Bwidth => 128,
SAwidth => 10,
DAwidth => 12,
Lwidth => 10
)
port map(
-- system signal
clk => clk,
rst => rst,
-- Tx interface
header => DMA1H,
Req => DMA1_Req,
laddr => DMA1A,
busy => DMA1_Busy,
tx_sop => tx_sop_i(1),
-- CPU bus
CS => CS1,
wr => wr,
rd => rd,
addr => addr( 3 downto 0 ),
Din => Din,
Dout => Dout1,
cpuClk => cpuClk,
-- Priority
en => '1'
);
ep1ram : blockdram
generic map(
depth => 1024,
Dwidth => 128,
Awidth => 10
)
port map(
addra => ramWA,
clka => clk,
addrb => ramRA,
clkb => clk,
dia => ramWD,
wea => ramWen,
reb => ramRen,
dob => ramRD
);
ep0src:DUMMYSRC
generic map(
Awidth => 10,
Bwidth => 128
)
port map(
-- system
clk => clk,
rst => rst,
Addr => dummyA,
Q => dummyD,
ren => dummyen
);
viewAout<=viewA;
viewDout<=viewD;
viewenout <= viewen;
cs0<='1' when addr( 7 downto 4 )="0000" else '0';
cs1<='1' when addr( 7 downto 4 )="0001" else '0';
dout<=dout0 when cs0='1' else ( others=>'Z' );
end behave;
| gpl-2.0 | f559ee8b361f6a5abcbb1cfd423d2187 | 0.507981 | 2.865715 | false | false | false | false |
juskojan/Bc.FIT | 2BIT/INP/Projekt 2/cpu.vhd | 1 | 10,838 | -- cpu.vhd: Simple 8-bit CPU (BrainFuck interpreter)
-- Copyright (C) 2014 Brno University of Technology,
-- Faculty of Information Technology
-- Author(s): Ján Jusko xjusko00
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity cpu is
port (
CLK : in std_logic; -- hodinovy signal
RESET : in std_logic; -- asynchronni reset procesoru
EN : in std_logic; -- povoleni cinnosti procesoru
-- synchronni pamet RAM
DATA_ADDR : out std_logic_vector(12 downto 0); -- adresa do pameti
DATA_WDATA : out std_logic_vector(7 downto 0); -- mem[DATA_ADDR] <- DATA_WDATA pokud DATA_EN='1'
DATA_RDATA : in std_logic_vector(7 downto 0); -- DATA_RDATA <- ram[DATA_ADDR] pokud DATA_EN='1'
DATA_RDWR : out std_logic; -- cteni (0) / zapis (1)
DATA_EN : out std_logic; -- povoleni cinnosti
-- vstupni port
IN_DATA : in std_logic_vector(7 downto 0); -- IN_DATA <- stav klavesnice pokud IN_VLD='1' a IN_REQ='1'
IN_VLD : in std_logic; -- data platna
IN_REQ : out std_logic; -- pozadavek na vstup data
-- vystupni port
OUT_DATA : out std_logic_vector(7 downto 0); -- zapisovana data
OUT_BUSY : in std_logic; -- LCD je zaneprazdnen (1), nelze zapisovat
OUT_WE : out std_logic -- LCD <- OUT_DATA pokud OUT_WE='1' a OUT_BUSY='0'
);
end cpu;
-- ----------------------------------------------------------------------------
-- Architecture declaration
-- ----------------------------------------------------------------------------
architecture behavioral of cpu is
-- PROGRAM COUNTER 13b
signal PC_reg : std_logic_vector(12 downto 0);
signal PC_inc : std_logic;
signal PC_dec : std_logic;
-- MEMORY POINTER 13b
signal PTR_reg : std_logic_vector(12 downto 0);
signal PTR_inc : std_logic;
signal PTR_dec : std_logic;
-- LOOP COUNTER 8b
signal CNT_reg : std_logic_vector(7 downto 0);
signal CNT_inc : std_logic;
signal CNT_dec : std_logic;
-- MULTIPLEXORY
signal sel : std_logic := '0';
signal sel2 : std_logic_vector(1 downto 0) := "01";
-- INSTRUKCIE
type inst is (incPTR, decPTR, incVALUE, decVALUE, whileS, whileE, putchar, readchar, halt, skip);
signal decoded_inst : inst;
-- STAVY MOOROVA FSM AUTOMATU
type FSM_state is (SIDLE, SFETCH, SDECODE, SHALT, SSKIP,
SINCPTR, SDECPTR, -- >/<
SINCVALUE, SINCVALUE2, SDECVALUE, SDECVALUE2, -- +/-
SPUTCHAR, SPUTCHAR2, -- .
SREADCHAR, SREADCHAR2, -- ,
SWHILES,SWHILES2,SWHILES3,SWHILES4,SWHILES5, -- [
SWHILEE,SWHILEE1,SWHILEE2,SWHILEE3,SWHILEE4 -- ]
);
signal Present_state: FSM_state;
signal Next_state : FSM_state;
begin
-----------------------Program Counter-----------------------
-------------------------------------------------------------
PC: process (CLK,RESET)
begin
if (RESET = '1') then
PC_reg <= (others => '0');
elsif (CLK'event) and (CLK = '1') then
if (PC_inc = '1') then
PC_reg <= PC_reg + "0000000000001";
end if;
if (PC_dec = '1') then
PC_reg <= PC_reg - "0000000000001";
end if;
end if;
end process PC;
-----------------------Memory pointer------------------------
-------------------------------------------------------------
PTR: process (CLK,RESET)
begin
if (RESET = '1') then
PTR_reg <= "1000000000000";
elsif (CLK'event) and (CLK = '1') then
if (PTR_inc = '1') then
if (PTR_reg = "1111111111111") then -- KRUHOVOST OVERFLOW
PTR_reg <= "1000000000000";
else
PTR_reg <= PTR_reg + "0000000000001";
end if;
end if;
if (PTR_dec = '1') then
if (PTR_reg = "1000000000000") then -- KRUHOVOST UNDERFLOW
PTR_reg <= "1111111111111";
else
PTR_reg <= PTR_reg - "0000000000001";
end if;
end if;
end if;
end process PTR;
-----------------------Loop counter--------------------------
-------------------------------------------------------------
CNT: process (CLK, RESET)
begin
if (RESET = '1') then
CNT_reg <= (others=>'0');
elsif (CLK'event) and (CLK = '1') then
if (CNT_inc = '1') then
CNT_reg <= CNT_reg + "00000001";
end if;
if (CNT_dec = '1') then
CNT_reg <= CNT_reg - "00000001";
end if;
end if;
end process CNT;
--------------------Finite state machine---------------------
-------------------------------------------------------------
FSM_pstate: process (CLK, RESET, EN)
begin
if (RESET = '1') then
Present_state <= SIDLE;
elsif (CLK'event) and (CLK = '1') then
if (EN = '1') then
Present_state <= Next_state;
end if;
end if;
end process FSM_pstate;
-----------------MULTIPLEXOR PC vs. PTR----------------------
-------------------------------------------------------------
MUX1: process (sel, PTR_reg, PC_reg)
begin
case sel is
when '1' =>
DATA_ADDR <= PTR_reg;
when '0' =>
DATA_ADDR <= PC_reg;
when others =>
end case;
end process MUX1;
-----------------MULTIPLEXOR WRITE DATA----------------------
-------------------------------------------------------------
MUX2: process (sel2, DATA_RDATA, IN_DATA)
begin
case sel2 is
when "01" =>
DATA_WDATA <= DATA_RDATA + "00000001";
when "10" =>
DATA_WDATA <= DATA_RDATA - "00000001";
when "11" =>
DATA_WDATA <= IN_DATA;
when others =>
end case;
end process MUX2;
--------------------Instruction decoder----------------------
-------------------------------------------------------------
INST_decoder: process (DATA_RDATA)
begin
case DATA_RDATA is
when X"00" =>
decoded_inst <= halt;
when X"3E" =>
decoded_inst <= incPTR;
when X"3C" =>
decoded_inst <= decPTR;
when X"2B" =>
decoded_inst <= incVALUE;
when X"2D" =>
decoded_inst <= decVALUE;
when X"5B" =>
decoded_inst <= whileS;
when X"5D" =>
decoded_inst <= whileE;
when X"2E" =>
decoded_inst <= putchar;
when X"2C" =>
decoded_inst <= readchar;
when others=>
decoded_inst <= skip;
end case;
end process INST_decoder;
--------------------FSM PROCESSOR----------------------------
-------------------------------------------------------------
FSMPROCESSOR: process (Present_state, decoded_inst, OUT_BUSY, DATA_RDATA, IN_VLD, CNT_reg)
begin
IN_REQ <='0';
OUT_WE<='0';
DATA_RDWR<='0';
DATA_EN<='0';
PC_inc<='0';
PC_dec<='0';
PTR_inc<='0';
PTR_dec<='0';
CNT_inc<='0';
CNT_dec<='0';
sel <= '0';
sel2 <= "01";
OUT_DATA <= (others => '0');
case Present_state is
when SIDLE => -- zaciatok, init, pri resete
Next_state <= SFETCH;
when SHALT => -- koniec programu
Next_state <= SHALT;
when SSKIP => -- preskoc komentare
PC_inc <= '1';
Next_state <= SFETCH;
when SFETCH => -- nacitaj instrukciu
DATA_EN <= '1';
DATA_RDWR <= '0';
sel <= '0';
Next_state <= SDECODE;
when SDECODE => -- dekoduj instrukciu
case decoded_inst is
when halt =>
Next_state <= SHALT;
when incPTR =>
Next_state <= SINCPTR;
when decPTR =>
Next_state <= SDECPTR;
when incVALUE =>
Next_state <= SINCVALUE;
when decVALUE =>
Next_state <= SDECVALUE;
when whileS =>
Next_state <= SWHILES;
when whileE =>
Next_state <= SWHILEE;
when putchar =>
Next_state <= SPUTCHAR;
when readchar =>
Next_state <= SREADCHAR;
when skip =>
Next_state <= SSKIP;
end case;
-- PTR inkrement (>)
when SINCPTR =>
PC_inc <= '1';
PTR_inc <= '1';
Next_state <= SFETCH;
-- PTR dekrement (<)
when SDECPTR =>
PC_inc <= '1';
PTR_dec <= '1';
Next_state <= SFETCH;
-- *PTR inkrement (+)
when SINCVALUE =>
sel <= '1';
DATA_RDWR <= '0';
DATA_EN <= '1';
Next_state <= SINCVALUE2;
when SINCVALUE2 =>
DATA_RDWR <= '1';
DATA_EN <= '1';
sel <= '1';
sel2 <= "01";
PC_inc <= '1';
Next_state <= SFETCH;
-- *PTR dekrement (-)
when SDECVALUE =>
sel <= '1';
DATA_RDWR <= '0';
DATA_EN <= '1';
Next_state <= SDECVALUE2;
when SDECVALUE2 =>
DATA_RDWR <= '1';
DATA_EN <= '1';
sel <= '1';
sel2 <= "10";
PC_inc <= '1';
Next_state <= SFETCH;
-- vypis znak (.)
when SPUTCHAR =>
DATA_RDWR <= '0';
DATA_EN <= '1';
sel <= '1';
Next_state <= SPUTCHAR2;
when SPUTCHAR2 =>
if (OUT_BUSY = '0') then
OUT_WE <= '1';
OUT_DATA <= DATA_RDATA;
PC_inc <= '1';
Next_state <= SFETCH;
else
Next_state <= SPUTCHAR2;
end if;
-- nacitaj znak (,)
when SREADCHAR =>
IN_REQ <= '1';
Next_state <= SREADCHAR2;
when SREADCHAR2 =>
if (IN_VLD = '1') then
sel <= '1';
sel2 <= "11";
DATA_RDWR <= '1';
DATA_EN <= '1';
PC_inc <= '1';
Next_state <= SFETCH;
else
IN_REQ <= '1';
Next_state <= SREADCHAR2;
end if;
-- WHILE ZACIATOK --
when SWHILES =>
DATA_RDWR <= '0';
DATA_EN <= '1';
PC_inc <= '1';
sel <= '1';
Next_state <= SWHILES2;
when SWHILES2 =>
if (DATA_RDATA = "00000000") then
CNT_inc <= '1';
Next_state <= SWHILES3;
else
Next_state <= SFETCH;
end if;
when SWHILES3 =>
DATA_RDWR <= '0';
DATA_EN <= '1';
sel <= '0';
Next_state <= SWHILES4;
when SWHILES4 =>
if (decoded_inst = whileE) then
CNT_dec <= '1';
elsif (decoded_inst = whileS) then
CNT_inc <= '1';
end if;
PC_inc <= '1';
Next_state <= SWHILES5;
when SWHILES5 =>
if (CNT_reg = "00000000") then
Next_state <= SFETCH;
else
Next_state <= SWHILES3;
end if;
-- WHILE KONIEC --
when SWHILEE =>
DATA_RDWR <= '0';
DATA_EN <= '1';
sel <= '1';
Next_state <= SWHILEE1;
when SWHILEE1 =>
if (DATA_RDATA = "00000000") then
PC_inc <= '1';
Next_state <= SFETCH;
else
CNT_inc <= '1';
PC_dec <= '1';
Next_state <= SWHILEE2;
end if;
when SWHILEE2 =>
sel <= '0';
DATA_RDWR <= '0';
DATA_EN <= '1';
Next_state <= SWHILEE3;
when SWHILEE3 =>
if (decoded_inst = whileS) then
CNT_dec <= '1';
elsif (decoded_inst = whileE) then
CNT_inc <= '1';
end if;
Next_state <= SWHILEE4;
when SWHILEE4 =>
if (CNT_reg = "00000000") then
PC_inc <= '1';
Next_state <= SFETCH;
else
PC_dec <= '1';
Next_state <= SWHILEE2;
end if;
end case;
end process FSMPROCESSOR;
end behavioral;
| gpl-3.0 | 9d3f4aa52c696fc6798ae7073ff52fa7 | 0.49391 | 3.370025 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/techmap/maps/allmem.vhd | 1 | 49,127 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: allmem
-- File: allmem.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: All tech specific memories
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package allmem is
-- AX & RTAX family
component axcel_syncram
generic ( abits : integer := 10; dbits : integer := 8);
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic);
end component;
component axcel_syncram_2p
generic ( abits : integer := 8; dbits : integer := 32; sepclk : integer:= 0);
port (
rclk : in std_ulogic;
rena : in std_ulogic;
raddr : in std_logic_vector (abits -1 downto 0);
dout : out std_logic_vector (dbits -1 downto 0);
wclk : in std_ulogic;
waddr : in std_logic_vector (abits -1 downto 0);
din : in std_logic_vector (dbits -1 downto 0);
write : in std_ulogic);
end component;
-- Proasic + Proasicplus family
component proasic_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic);
end component;
component proasic_syncram_2p
generic ( abits : integer := 8; dbits : integer := 32);
port (
rclk : in std_ulogic;
rena : in std_ulogic;
raddr : in std_logic_vector (abits -1 downto 0);
dout : out std_logic_vector (dbits -1 downto 0);
wclk : in std_ulogic;
waddr : in std_logic_vector (abits -1 downto 0);
din : in std_logic_vector (dbits -1 downto 0);
write : in std_ulogic);
end component;
-- Proasic3 family
component proasic3_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic);
end component;
component proasic3_syncram_2p
generic ( abits : integer := 8; dbits : integer := 32; sepclk : integer := 0);
port (
rclk : in std_ulogic;
rena : in std_ulogic;
raddr : in std_logic_vector (abits -1 downto 0);
dout : out std_logic_vector (dbits -1 downto 0);
wclk : in std_ulogic;
waddr : in std_logic_vector (abits -1 downto 0);
din : in std_logic_vector (dbits -1 downto 0);
write : in std_ulogic);
end component;
component proasic3_syncram_dp is
generic ( abits : integer := 6; dbits : integer := 8 );
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end component;
component proasic3e_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic);
end component;
component proasic3e_syncram_2p
generic ( abits : integer := 8; dbits : integer := 32; sepclk : integer := 0);
port (
rclk : in std_ulogic;
rena : in std_ulogic;
raddr : in std_logic_vector (abits -1 downto 0);
dout : out std_logic_vector (dbits -1 downto 0);
wclk : in std_ulogic;
waddr : in std_logic_vector (abits -1 downto 0);
din : in std_logic_vector (dbits -1 downto 0);
write : in std_ulogic);
end component;
component proasic3e_syncram_dp is
generic ( abits : integer := 6; dbits : integer := 8 );
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end component;
component proasic3l_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic);
end component;
component proasic3l_syncram_2p
generic ( abits : integer := 8; dbits : integer := 32; sepclk : integer := 0);
port (
rclk : in std_ulogic;
rena : in std_ulogic;
raddr : in std_logic_vector (abits -1 downto 0);
dout : out std_logic_vector (dbits -1 downto 0);
wclk : in std_ulogic;
waddr : in std_logic_vector (abits -1 downto 0);
din : in std_logic_vector (dbits -1 downto 0);
write : in std_ulogic);
end component;
component saed32_syncram_2p
generic ( abits : integer := 8; dbits : integer := 32; sepclk : integer := 0);
port (
rclk : in std_ulogic;
rena : in std_ulogic;
raddr : in std_logic_vector (abits -1 downto 0);
dout : out std_logic_vector (dbits -1 downto 0);
wclk : in std_ulogic;
waddr : in std_logic_vector (abits -1 downto 0);
din : in std_logic_vector (dbits -1 downto 0);
write : in std_ulogic);
end component;
component dare_syncram_2p
generic ( abits : integer := 8; dbits : integer := 32; sepclk : integer := 0);
port (
rclk : in std_ulogic;
rena : in std_ulogic;
raddr : in std_logic_vector (abits -1 downto 0);
dout : out std_logic_vector (dbits -1 downto 0);
wclk : in std_ulogic;
waddr : in std_logic_vector (abits -1 downto 0);
din : in std_logic_vector (dbits -1 downto 0);
write : in std_ulogic);
end component;
component rhumc_syncram_2p
generic ( abits : integer := 8; dbits : integer := 32; sepclk : integer := 0);
port (
rclk : in std_ulogic;
rena : in std_ulogic;
raddr : in std_logic_vector (abits -1 downto 0);
dout : out std_logic_vector (dbits -1 downto 0);
wclk : in std_ulogic;
waddr : in std_logic_vector (abits -1 downto 0);
din : in std_logic_vector (dbits -1 downto 0);
write : in std_ulogic);
end component;
component proasic3l_syncram_dp is
generic ( abits : integer := 6; dbits : integer := 8 );
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end component;
component proasic3_from
generic (
TimingChecksOn: boolean := True;
InstancePath: string := "*";
Xon: boolean := False;
MsgOn: boolean := True;
DATA_X: integer := 1;
MEMORYFILE: string := "";
ACT_PROGFILE: string := "");
port(
CLK : in std_logic := 'U';
DO0 : out std_logic;
DO1 : out std_logic;
DO2 : out std_logic;
DO3 : out std_logic;
DO4 : out std_logic;
DO5 : out std_logic;
DO6 : out std_logic;
DO7 : out std_logic;
ADDR0 : in std_logic := 'U';
ADDR1 : in std_logic := 'U';
ADDR2 : in std_logic := 'U';
ADDR3 : in std_logic := 'U';
ADDR4 : in std_logic := 'U';
ADDR5 : in std_logic := 'U';
ADDR6 : in std_logic := 'U');
end component;
component proasic3e_from
generic (
TimingChecksOn: boolean := True;
InstancePath: string := "*";
Xon: boolean := False;
MsgOn: boolean := True;
DATA_X: integer := 1;
MEMORYFILE: string := "";
ACT_PROGFILE: string := "");
port(
CLK : in std_logic := 'U';
DO0 : out std_logic;
DO1 : out std_logic;
DO2 : out std_logic;
DO3 : out std_logic;
DO4 : out std_logic;
DO5 : out std_logic;
DO6 : out std_logic;
DO7 : out std_logic;
ADDR0 : in std_logic := 'U';
ADDR1 : in std_logic := 'U';
ADDR2 : in std_logic := 'U';
ADDR3 : in std_logic := 'U';
ADDR4 : in std_logic := 'U';
ADDR5 : in std_logic := 'U';
ADDR6 : in std_logic := 'U');
end component;
component proasic3l_from
generic (
TimingChecksOn: boolean := True;
InstancePath: string := "*";
Xon: boolean := False;
MsgOn: boolean := True;
DATA_X: integer := 1;
MEMORYFILE: string := "";
ACT_PROGFILE: string := "");
port(
CLK : in std_logic := 'U';
DO0 : out std_logic;
DO1 : out std_logic;
DO2 : out std_logic;
DO3 : out std_logic;
DO4 : out std_logic;
DO5 : out std_logic;
DO6 : out std_logic;
DO7 : out std_logic;
ADDR0 : in std_logic := 'U';
ADDR1 : in std_logic := 'U';
ADDR2 : in std_logic := 'U';
ADDR3 : in std_logic := 'U';
ADDR4 : in std_logic := 'U';
ADDR5 : in std_logic := 'U';
ADDR6 : in std_logic := 'U');
end component;
component from is
generic (
tech: integer := 0;
timingcheckson: boolean := True;
instancepath: string := "*";
xon: boolean := False;
msgon: boolean := True;
data_x: integer := 1;
memoryfile: string := "";
progfile: string := "");
port (
clk: in std_ulogic;
addr: in std_logic_vector(6 downto 0);
data: out std_logic_vector(7 downto 0));
end component;
-- Fusion family
component fusion_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic);
end component;
component fusion_syncram_2p
generic ( abits : integer := 8; dbits : integer := 32);
port (
rclk : in std_ulogic;
rena : in std_ulogic;
raddr : in std_logic_vector (abits -1 downto 0);
dout : out std_logic_vector (dbits -1 downto 0);
wclk : in std_ulogic;
waddr : in std_logic_vector (abits -1 downto 0);
din : in std_logic_vector (dbits -1 downto 0);
write : in std_ulogic);
end component;
component fusion_syncram_dp is
generic ( abits : integer := 6; dbits : integer := 8 );
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end component;
component fusion_from
generic (
TimingChecksOn: boolean := True;
InstancePath: string := "*";
Xon: boolean := False;
MsgOn: boolean := True;
DATA_X: integer := 1;
MEMORYFILE: string := "";
ACT_PROGFILE: string := "");
port(
CLK : in std_logic := 'U';
DO0 : out std_logic;
DO1 : out std_logic;
DO2 : out std_logic;
DO3 : out std_logic;
DO4 : out std_logic;
DO5 : out std_logic;
DO6 : out std_logic;
DO7 : out std_logic;
ADDR0 : in std_logic := 'U';
ADDR1 : in std_logic := 'U';
ADDR2 : in std_logic := 'U';
ADDR3 : in std_logic := 'U';
ADDR4 : in std_logic := 'U';
ADDR5 : in std_logic := 'U';
ADDR6 : in std_logic := 'U');
end component;
component altera_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end component;
component altera_syncram_dp
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end component;
component altera_fifo_dp is
generic (tech : integer := 0; abits : integer := 4; dbits : integer := 32);
port (
rdclk : in std_logic;
rdreq : in std_logic;
rdfull : out std_logic;
rdempty : out std_logic;
rdusedw : out std_logic_vector(abits-1 downto 0);
q : out std_logic_vector(dbits-1 downto 0);
wrclk : in std_logic;
wrreq : in std_logic;
wrfull : out std_logic;
wrempty : out std_logic;
wrusedw : out std_logic_vector(abits-1 downto 0);
data : in std_logic_vector(dbits-1 downto 0);
aclr : in std_logic := '0');
end component;
component generic_syncram
generic (abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
write : in std_ulogic
);
end component;
component generic_syncram_2p
generic (abits : integer := 8; dbits : integer := 32; sepclk : integer := 0);
port (
rclk : in std_ulogic;
wclk : in std_ulogic;
rdaddress: in std_logic_vector (abits -1 downto 0);
wraddress: in std_logic_vector (abits -1 downto 0);
data: in std_logic_vector (dbits -1 downto 0);
wren : in std_ulogic;
q: out std_logic_vector (dbits -1 downto 0)
);
end component;
component generic_syncram_reg
generic (abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
write : in std_ulogic
);
end component;
component generic_syncram_2p_reg
generic (abits : integer := 8; dbits : integer := 32; sepclk : integer := 0);
port (
rclk : in std_ulogic;
wclk : in std_ulogic;
rdaddress: in std_logic_vector (abits -1 downto 0);
wraddress: in std_logic_vector (abits -1 downto 0);
data: in std_logic_vector (dbits -1 downto 0);
wren : in std_ulogic;
q: out std_logic_vector (dbits -1 downto 0)
);
end component;
-- synchronous 3-port regfile (2 read, 1 write port)
component generic_regfile_3p
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 32;
wrfst : integer := 0; numregs : integer := 40);
port (
wclk : in std_ulogic;
waddr : in std_logic_vector((abits -1) downto 0);
wdata : in std_logic_vector((dbits -1) downto 0);
we : in std_ulogic;
rclk : in std_ulogic;
raddr1 : in std_logic_vector((abits -1) downto 0);
re1 : in std_ulogic;
rdata1 : out std_logic_vector((dbits -1) downto 0);
raddr2 : in std_logic_vector((abits -1) downto 0);
re2 : in std_ulogic;
rdata2 : out std_logic_vector((dbits -1) downto 0)
);
end component;
component ihp25_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_logic;
address : in std_logic_vector(abits -1 downto 0);
datain : in std_logic_vector(dbits -1 downto 0);
dataout : out std_logic_vector(dbits -1 downto 0);
enable : in std_logic;
write : in std_logic
);
end component;
component ec_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end component;
component ec_syncram_dp
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end component;
component rh_lib18t_syncram_2p
generic (abits : integer := 6; dbits : integer := 8;
sepclk : integer := 0);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
diagin : in std_logic_vector(3 downto 0));
end component;
component rh_lib18t_syncram is
generic (abits : integer := 6; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic;
diagin : in std_logic_vector(1 downto 0) := "00");
end component;
component umc_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector(abits -1 downto 0);
datain : in std_logic_vector(dbits -1 downto 0);
dataout : out std_logic_vector(dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic);
end component;
component rhumc_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector(abits -1 downto 0);
datain : in std_logic_vector(dbits -1 downto 0);
dataout : out std_logic_vector(dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic);
end component;
component saed32_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector(abits -1 downto 0);
datain : in std_logic_vector(dbits -1 downto 0);
dataout : out std_logic_vector(dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic);
end component;
component saed32_syncram_dp is
generic ( abits : integer := 6; dbits : integer := 8 );
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end component;
component dare_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector(abits -1 downto 0);
datain : in std_logic_vector(dbits -1 downto 0);
dataout : out std_logic_vector(dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic);
end component;
component dare_syncram_dp is
generic ( abits : integer := 6; dbits : integer := 8 );
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end component;
component virage_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector(abits -1 downto 0);
datain : in std_logic_vector(dbits -1 downto 0);
dataout : out std_logic_vector(dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic);
end component;
component virage_syncram_dp
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic);
end component;
component virage90_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector(abits -1 downto 0);
datain : in std_logic_vector(dbits -1 downto 0);
dataout : out std_logic_vector(dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic);
end component;
component virtex_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end component;
component virtex_syncram_dp
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end component;
component unisim_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end component;
component unisim_syncram_dp
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end component;
component unisim_syncram64
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (63 downto 0);
dataout : out std_logic_vector (63 downto 0);
enable : in std_logic_vector (1 downto 0);
write : in std_logic_vector (1 downto 0)
);
end component;
component virage90_syncram_dp
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end component;
component ut025crh_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end component;
component ut025crh_syncram_2p
generic ( abits : integer := 8; dbits : integer := 32);
port (
rclk : in std_ulogic;
rena : in std_ulogic;
raddr : in std_logic_vector (abits -1 downto 0);
dout : out std_logic_vector (dbits -1 downto 0);
wclk : in std_ulogic;
waddr : in std_logic_vector (abits -1 downto 0);
din : in std_logic_vector (dbits -1 downto 0);
write : in std_ulogic);
end component;
component ut130hbd_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end component;
component ut130hbd_syncram_2p
generic ( abits : integer := 8; dbits : integer := 32; words : integer := 0);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0));
end component;
component peregrine_regfile_3p
generic (abits : integer := 6; dbits : integer := 32);
port (
wclk : in std_ulogic;
waddr : in std_logic_vector((abits -1) downto 0);
wdata : in std_logic_vector((dbits -1) downto 0);
we : in std_ulogic;
raddr1 : in std_logic_vector((abits -1) downto 0);
re1 : in std_ulogic;
rdata1 : out std_logic_vector((dbits -1) downto 0);
raddr2 : in std_logic_vector((abits -1) downto 0);
re2 : in std_ulogic;
rdata2 : out std_logic_vector((dbits -1) downto 0));
end component;
component eclipse_syncram_2p is
generic ( abits : integer := 8; dbits : integer := 32);
port (
rclk : in std_ulogic;
rena : in std_ulogic;
raddr : in std_logic_vector (abits -1 downto 0);
dout : out std_logic_vector (dbits -1 downto 0);
wclk : in std_ulogic;
waddr : in std_logic_vector (abits -1 downto 0);
din : in std_logic_vector (dbits -1 downto 0);
write : in std_ulogic);
end component;
component nextreme_syncram_2p is
generic (abits : integer := 6; dbits : integer := 8);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0));
end component;
component custom1_syncram_2p is
generic ( abits : integer := 8; dbits : integer := 32);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0));
end component;
component artisan_syncram_2p is
generic ( abits : integer := 8; dbits : integer := 32);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0));
end component;
component smic13_syncram_2p is
generic ( abits : integer := 8; dbits : integer := 32);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0));
end component;
component ihp25rh_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_logic;
address : in std_logic_vector(abits -1 downto 0);
datain : in std_logic_vector(dbits -1 downto 0);
dataout : out std_logic_vector(dbits -1 downto 0);
enable : in std_logic;
write : in std_logic);
end component;
component peregrine_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end component;
component artisan_syncram
generic ( abits : integer := 10; dbits : integer := 32 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end component;
component smic13_syncram
generic ( abits : integer := 10; dbits : integer := 32 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end component;
component custom1_syncram
generic ( abits : integer := 10; dbits : integer := 32 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end component;
component nextreme_syncram
generic (abits : integer := 6; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic);
end component;
component unisim_syncram_2p is
generic (abits : integer := 6; dbits : integer := 8; sepclk : integer := 0;
wrfst : integer := 0);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0));
end component;
component virage_syncram_2p
generic (abits : integer := 6; dbits : integer := 8;
sepclk : integer := 0; wrfst : integer := 0);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0));
end component;
component atc18rha_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector(abits -1 downto 0);
datain : in std_logic_vector(dbits -1 downto 0);
dataout : out std_logic_vector(dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic;
testin : in std_logic_vector(3 downto 0));
end component;
component atc18rha_syncram_dp
generic ( abits : integer := 10; dbits : integer := 8);
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic;
testin : in std_logic_vector(3 downto 0));
end component;
component atc18rha_syncram_2p
generic ( abits : integer := 6; dbits : integer := 8;
sepclk : integer := 0; wrfst : integer := 0);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
testin : in std_logic_vector(3 downto 0));
end component;
component artisan_syncram_dp
generic ( abits : integer := 10; dbits : integer := 32 );
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end component;
component smic13_syncram_dp
generic ( abits : integer := 10; dbits : integer := 32 );
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end component;
component tm65gplus_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector(abits -1 downto 0);
datain : in std_logic_vector(dbits -1 downto 0);
dataout : out std_logic_vector(dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end component;
component tm65gplus_syncram_dp
generic ( abits : integer := 10; dbits : integer := 8);
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end component;
component tm65gplus_syncram_2p
generic ( abits : integer := 6; dbits : integer := 8;
sepclk : integer := 0; wrfst : integer := 0);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0));
end component;
component generic_regfile_4p
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 32;
wrfst : integer := 0; numregs : integer := 40; g0addr: integer := 0);
port (
wclk : in std_ulogic;
waddr : in std_logic_vector((abits -1) downto 0);
wdata : in std_logic_vector((dbits -1) downto 0);
we : in std_ulogic;
rclk : in std_ulogic;
raddr1 : in std_logic_vector((abits -1) downto 0);
re1 : in std_ulogic;
rdata1 : out std_logic_vector((dbits -1) downto 0);
raddr2 : in std_logic_vector((abits -1) downto 0);
re2 : in std_ulogic;
rdata2 : out std_logic_vector((dbits -1) downto 0);
raddr3 : in std_logic_vector((abits -1) downto 0);
re3 : in std_ulogic;
rdata3 : out std_logic_vector((dbits -1) downto 0)
);
end component;
component cmos9sf_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector(abits -1 downto 0);
datain : in std_logic_vector(dbits -1 downto 0);
dataout : out std_logic_vector(dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end component;
component cmos9sf_syncram_2p
generic ( abits : integer := 6; dbits : integer := 8);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0));
end component;
-- eASIC Nextreme2
component n2x_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end component;
component n2x_syncram_dp
generic ( abits : integer := 10; dbits : integer := 8; sepclk : integer := 0 );
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end component;
component n2x_syncram_2p is
generic (abits : integer := 6; dbits : integer := 8; sepclk : integer := 0;
wrfst : integer := 0);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0));
end component;
component n2x_syncram_we -- syncram with 32-bit write strobes
generic (
abits : integer := 6;
dbits : integer := 8);
port (
clk : in std_ulogic;
address : in std_logic_vector((abits-1) downto 0);
datain : in std_logic_vector((dbits-1) downto 0);
dataout : out std_logic_vector((dbits-1) downto 0);
enable : in std_logic_vector((dbits/32)-1 downto 0);
write : in std_logic_vector((dbits/32)-1 downto 0));
end component;
component n2x_syncram_be -- syncram with 8-bit write strobes
generic (
abits : integer := 6;
dbits : integer := 8);
port (
clk : in std_ulogic;
address : in std_logic_vector((abits-1) downto 0);
datain : in std_logic_vector((dbits-1) downto 0);
dataout : out std_logic_vector((dbits-1) downto 0);
enable : in std_logic_vector((dbits/8)-1 downto 0);
write : in std_logic_vector((dbits/8)-1 downto 0)
);
end component;
component n2x_syncram_dp_be
generic (
abits : integer := 6;
dbits : integer := 8;
sepclk : integer := 1
);
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits-1) downto 0);
datain1 : in std_logic_vector((dbits-1) downto 0);
dataout1 : out std_logic_vector((dbits-1) downto 0);
enable1 : in std_logic_vector((dbits/8-1) downto 0);
write1 : in std_logic_vector((dbits/8-1) downto 0);
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits-1) downto 0);
datain2 : in std_logic_vector((dbits-1) downto 0);
dataout2 : out std_logic_vector((dbits-1) downto 0);
enable2 : in std_logic_vector((dbits/8-1) downto 0);
write2 : in std_logic_vector((dbits/8-1) downto 0));
end component;
component n2x_syncram_2p_be
generic (
abits : integer := 6;
dbits : integer := 8;
sepclk : integer := 0;
wrfst : integer := 0);
port (
rclk : in std_ulogic;
renable : in std_logic_vector((dbits/8-1) downto 0);
raddress : in std_logic_vector((abits-1) downto 0);
dataout : out std_logic_vector((dbits-1) downto 0);
wclk : in std_ulogic;
write : in std_logic_vector((dbits/8-1) downto 0);
waddress : in std_logic_vector((abits-1) downto 0);
datain : in std_logic_vector((dbits-1) downto 0));
end component;
component ut90nhbd_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic;
tdbn : in std_ulogic
);
end component;
component ut90nhbd_syncram_2p
generic ( abits : integer := 8; dbits : integer := 32);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
tdbn : in std_ulogic);
end component;
component ut90nhbd_syncram_dp
generic ( abits : integer := 10; dbits : integer := 32 );
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic;
tdbn : in std_ulogic
);
end component;
component rh_lib13t_syncram_2p
generic (abits : integer := 6; dbits : integer := 8;
sepclk : integer := 0);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
diagin : in std_logic_vector(3 downto 0));
end component;
component rh_lib13t_syncram is
generic (abits : integer := 6; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic;
diagin : in std_logic_vector(1 downto 0) := "00");
end component;
end;
| gpl-2.0 | 7a3b3435fdf437bbca325663969dbd67 | 0.588475 | 3.389705 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/gr1553b/simtrans1553.vhd | 1 | 3,690 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: simtrans1553
-- File: simtrans1553.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: 1553 Transceiver simulation model
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.gr1553b_pkg.all;
entity simtrans1553_single is
generic (
txdelay: time := 200 ns;
rxdelay: time := 450 ns
);
port (
buswire: inout wire1553;
rxen: in std_logic;
txin: in std_logic;
txP: in std_logic;
txN: in std_logic;
rxP: out std_logic;
rxN: out std_logic
);
end;
architecture b of simtrans1553_single is
signal bw_rxd, bw_txd: wire1553;
begin
bw_rxd <= transport buswire after rxdelay;
buswire <= bw_txd after txdelay;
rxpr: process(bw_rxd,rxen)
variable p,n: std_ulogic;
begin
p:='U'; n:='U';
case rxen is
when '0' => p:='0'; n:='0';
when '1' =>
case bw_rxd is
when 'U' => null;
when 'X' => p := 'X'; n := 'X';
when '0' => p := '0'; n := '0';
when '+' => p := '1'; n := '0';
when '-' => p := '0'; n := '1';
end case;
when 'X' => p:='X'; n:='X';
when others => null;
end case;
rxP <= p;
rxN <= n;
end process;
txpr: process(txin, txP, txN)
variable w: wire1553;
begin
w := 'U';
if txin='1' or (txP='0' and txN='0') or (txP='1' and txN='1') then
w := '0';
elsif txin='0' and txP='1' and txN='0' then
w := '+';
elsif txin='0' and txP='0' and txN='1' then
w := '-';
elsif txin='X' or txP='X' or txN='X' then
w := 'X';
elsif txin='U' or (txP='U' and txN='U') then
w := 'U';
else
w := 'X';
end if;
bw_txd <= w;
end process;
end;
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.gr1553b_pkg.all;
entity simtrans1553 is
generic (
txdelay: time := 200 ns;
rxdelay: time := 450 ns
);
port (
busA: inout wire1553;
busB: inout wire1553;
rxenA: in std_logic;
txinA: in std_logic;
txAP: in std_logic;
txAN: in std_logic;
rxAP: out std_logic;
rxAN: out std_logic;
rxenB: in std_logic;
txinB: in std_logic;
txBP: in std_logic;
txBN: in std_logic;
rxBP: out std_logic;
rxBN: out std_logic
);
end;
architecture s of simtrans1553 is
begin
at: simtrans1553_single
generic map (txdelay,rxdelay)
port map (busA,rxenA,txinA,txAP,txAN,rxAP,rxAN);
bt: simtrans1553_single
generic map (txdelay,rxdelay)
port map (busB,rxenB,txinB,txBP,txBN,rxBP,rxBN);
end;
| gpl-2.0 | 167693473cbf1c786b1cbf6a716245b5 | 0.561789 | 3.419833 | false | false | false | false |
cesar-avalos3/C8VHDL | sources/vhdl/time_keeper.vhd | 1 | 4,850 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity time_keeper is
Port ( memRead : in STD_LOGIC_VECTOR (7 downto 0);
memWrite : out STD_LOGIC_VECTOR (7 downto 0);
memAddress : out STD_LOGIC_VECTOR (11 downto 0);
mem_valid : out STD_LOGIC;
mem_write : out STD_LOGIC;
mem_hold : out STD_LOGIC;
mem_done : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
heart_beat : out STD_LOGIC;
buzz : out STD_LOGIC );
end time_keeper;
architecture Behavioral of time_keeper is
constant DT_ADDRESS : std_logic_vector(11 downto 0):= "000000000000";
constant ST_ADDRESS : std_logic_vector(11 downto 0):= "000000000001";
type state is ( init, count, update, writeDT, readST, writeST, memA, memB );
signal current_state : state;
signal counter60hz : std_logic_vector( 23 downto 0 );
-- close enough, only lets us know the timer is running about
-- at the correct speed.
signal counter1hz : std_logic_vector( 6 downto 0 );
signal mem_ret_state : state;
signal tmp_mem_write : STD_LOGIC;
signal mem_ret_data : STD_LOGIC_VECTOR (7 downto 0);
begin
heart_beat <= counter1hz(6); -- for chip
-- heart_beat <= counter1hz(0); -- for simulation
mem_write <= tmp_mem_write;
process( clk, reset )
variable tmp_count : std_logic_vector( 23 downto 0 );
variable tmp_8 : std_logic_vector( 7 downto 0 );
begin
if ( reset = '1' ) then
current_state <= init;
memWrite <= ( others => '0' );
memAddress <= ( others => '0' );
mem_valid <= '0';
tmp_mem_write <= '0';
mem_hold <= '0';
buzz <= '0';
counter1hz <= "1000000";
elsif ( rising_edge( clk ) ) then
current_state <= current_state;
case current_state is
when init =>
counter60hz <= ( others => '0' );
current_state <= count;
when count =>
mem_hold <= '0';
tmp_count := counter60hz;
tmp_count := tmp_count + 1;
if( tmp_count = "000000011010101010101010" ) then -- for board divider
--if( tmp_count = "000110101010101010101010" ) then -- for board
--if( tmp_count = "000000000000000010000000" ) then -- for test bench
current_state <= update;
tmp_count := ( others => '0' );
counter1hz <= counter1hz + 1;
end if;
counter60hz <= tmp_count;
when update =>
memAddress <= DT_ADDRESS;
tmp_mem_write <= '0';
mem_hold <= '1';
mem_ret_state <= writeDT;
current_state <= memA;
when writeDT =>
tmp_8 := mem_ret_data;
if ( tmp_8 /= "00000000" ) then
tmp_8 := tmp_8 - "00000001";
end if;
memAddress <= DT_ADDRESS;
tmp_mem_write <= '1';
mem_ret_state <= readST;
memWrite <= tmp_8;
current_state <= memA;
when readST =>
memAddress <= ST_ADDRESS;
tmp_mem_write <= '0';
mem_ret_state <= writeST;
current_state <= memA;
when writeST =>
tmp_8 := mem_ret_data;
if ( tmp_8 /= "00000000" ) then
tmp_8 := tmp_8 - "00000001";
buzz <= '1';
else
buzz <= '0';
end if;
memAddress <= ST_ADDRESS;
tmp_mem_write <= '1';
mem_ret_state <= count;
memWrite <= tmp_8;
current_state <= memA;
when memA =>
if ( mem_done = '0' ) then
mem_valid <= '1';
current_state <= memB;
end if;
when memB =>
if( mem_done = '1' ) then
if ( tmp_mem_write = '0' ) then
mem_ret_data <= memRead;
end if;
mem_valid <= '0';
current_state <= mem_ret_state;
end if;
end case;
end if;
end process;
end Behavioral;
| mit | b40e98c057d7fb0a9f8fbe9915d42a77 | 0.430103 | 4.520037 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/techmap/maps/syncrambw.vhd | 1 | 5,257 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: syncrambw
-- File: syncrambw.vhd
-- Author: Jan Andersson - Aeroflex Gaisler
-- Description: Synchronous 1-port ram with 8-bit write strobes
-- and tech selection
------------------------------------------------------------------------------
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allmem.all;
library grlib;
use grlib.config.all;
use grlib.config_types.all;
use grlib.stdlib.all;
entity syncrambw is
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
testen : integer := 0; custombits: integer := 1);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits-1 downto 0);
datain : in std_logic_vector (dbits-1 downto 0);
dataout : out std_logic_vector (dbits-1 downto 0);
enable : in std_logic_vector (dbits/8-1 downto 0);
write : in std_logic_vector (dbits/8-1 downto 0);
testin : in std_logic_vector (TESTIN_WIDTH-1 downto 0) := testin_none;
customclk: in std_ulogic := '0';
customin : in std_logic_vector((dbits/8)*custombits-1 downto 0) := (others => '0');
customout:out std_logic_vector((dbits/8)*custombits-1 downto 0));
end;
architecture rtl of syncrambw is
constant nctrl : integer := abits + (TESTIN_WIDTH-2) + 2*dbits/8;
signal dataoutx, databp, testdata : std_logic_vector((dbits -1) downto 0);
constant SCANTESTBP : boolean := (testen = 1) and (tech /= 0) and (tech /= ut90);
signal xenable, xwrite : std_logic_vector(dbits/8-1 downto 0);
signal custominx,customoutx: std_logic_vector(syncram_customif_maxwidth downto 0);
begin
xenable <= enable when testen=0 or testin(TESTIN_WIDTH-2)='0' else (others => '0');
xwrite <= write when testen=0 or testin(TESTIN_WIDTH-2)='0' else (others => '0');
sbw : if has_srambw(tech) = 1 generate
-- RAM bypass for scan
scanbp : if SCANTESTBP generate
comb : process (address, datain, enable, write, testin)
variable tmp : std_logic_vector((dbits -1) downto 0);
variable ctrlsigs : std_logic_vector((nctrl -1) downto 0);
begin
ctrlsigs := testin(TESTIN_WIDTH-3 downto 0) & write & enable & address;
tmp := datain;
for i in 0 to nctrl-1 loop
tmp(i mod dbits) := tmp(i mod dbits) xor ctrlsigs(i);
end loop;
testdata <= tmp;
end process;
reg : process (clk)
begin
if rising_edge(clk) then
databp <= testdata;
end if;
end process;
dmuxout : for i in 0 to dbits-1 generate
x0: grmux2 generic map (tech)
port map (dataoutx(i), databp(i), testin(TESTIN_WIDTH-1), dataout(i));
end generate;
end generate;
noscanbp : if not SCANTESTBP generate dataout <= dataoutx; end generate;
n2x : if tech = easic45 generate
x0 : n2x_syncram_be generic map (abits, dbits)
port map (clk, address, datain, dataout, xenable, xwrite);
end generate;
customout(customout'high downto custombits) <= (others => '0');
customout(custombits-1 downto 0) <= customoutx(custombits-1 downto 0);
-- pragma translate_off
dmsg : if GRLIB_CONFIG_ARRAY(grlib_debug_level) >= 2 generate
x : process
begin
assert false report "syncrambw: " & tost(2**abits) & "x" & tost(dbits) &
" (" & tech_table(tech) & ")"
severity note;
wait;
end process;
end generate;
-- pragma translate_on
end generate;
nosbw : if has_srambw(tech) = 0 generate
rx : for i in 0 to dbits/8-1 generate
x0 : syncram generic map (tech, abits, 8, testen, custombits)
port map (clk, address, datain(i*8+7 downto i*8),
dataoutx(i*8+7 downto i*8), enable(i), write(i), testin,
customclk, customin((i+1)*custombits-1 downto i*custombits),
customout((i+1)*custombits-1 downto i*custombits));
end generate;
dataout <= dataoutx;
end generate;
custominx(custominx'high downto (dbits/8)*custombits) <= (others => '0');
custominx((dbits/8)*custombits-1 downto 0) <= customin;
nocust: if has_srambw(tech)=0 or syncram_has_customif(tech)=0 generate
customoutx <= (others => '0');
end generate;
end;
| gpl-2.0 | be822d21c8eba852c45c8ed6b00dfd9e | 0.623359 | 3.782014 | false | true | false | false |
khaledhassan/vhdl-examples | adders_1bit/full_adder_tb.vhd | 1 | 2,406 | -- Copyright (c) 2012 Brian Nezvadovitz <http://nezzen.net>
-- This software is distributed under the terms of the MIT License shown below.
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to
-- deal in the Software without restriction, including without limitation the
-- rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
-- sell copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
-- IN THE SOFTWARE.
-- Testbench for the full adder.
library ieee;
use ieee.std_logic_1164.all;
entity full_adder_tb is
end full_adder_tb;
architecture TB of full_adder_tb is
signal a, b, sum, c_in, c_out : std_logic;
begin
-- Instantiate the unit under test (UUT)
UUT : entity work.full_adder
port map (
a => a,
b => b,
c_in => c_in,
sum => sum,
c_out => c_out
);
-- Stimulus process
process
begin
a <= '0';
b <= '0';
c_in <= '0';
wait for 10 ns;
a <= '1';
b <= '0';
c_in <= '0';
wait for 10 ns;
a <= '0';
b <= '1';
c_in <= '0';
wait for 10 ns;
a <= '1';
b <= '1';
c_in <= '0';
wait for 10 ns;
a <= '0';
b <= '0';
c_in <= '1';
wait for 10 ns;
a <= '1';
b <= '0';
c_in <= '1';
wait for 10 ns;
a <= '0';
b <= '1';
c_in <= '1';
wait for 10 ns;
a <= '1';
b <= '1';
c_in <= '1';
wait;
end process;
end TB;
| mit | 01d5bb11dc0b942a8f1204b403e51c22 | 0.561929 | 3.8496 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-altera-ep3sl150/testbench.vhd | 1 | 12,987 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
-- Altera Stratix-III LEON3 Demonstration design test bench
-- Copyright (C) 2007 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
library cypress;
use cypress.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 23; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 20; -- ram address depth
srambanks : integer := 1; -- number of ram banks
dbits : integer := CFG_DDR2SP_DATAWIDTH
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
constant ct : integer := clkperiod/2;
constant lresp : boolean := false;
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal Rst : std_logic := '0'; -- Reset
signal clk : std_logic := '0';
signal clk125 : std_logic := '0';
signal address : std_logic_vector(25 downto 0);
signal data : std_logic_vector(31 downto 0);
signal romsn : std_ulogic;
signal iosn : std_ulogic;
signal oen : std_ulogic;
signal writen : std_ulogic;
signal dsuen, dsutx, dsurx, dsubren, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal error : std_logic;
signal gpio : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal txd1, rxd1 : std_ulogic;
-- PSRAM and FLASH control
signal sram_advn : std_logic;
signal sram_csn : std_logic;
signal sram_wen : std_logic;
signal sram_ben : std_logic_vector (0 to 3);
signal sram_oen : std_ulogic;
signal sram_clk : std_ulogic;
signal sram_adscn : std_ulogic;
signal sram_psn : std_ulogic;
signal sram_adv_n : std_ulogic;
signal sram_wait : std_logic_vector(1 downto 0);
signal flash_clk, flash_cen, max_csn : std_logic;
signal flash_advn, flash_oen, flash_resetn, flash_wen : std_logic;
-- DDR2 memory
signal ddr_clk : std_logic_vector(2 downto 0);
signal ddr_clkb : std_logic_vector(2 downto 0);
signal ddr_cke : std_logic_vector(1 downto 0);
signal ddr_csb : std_logic_vector(1 downto 0);
signal ddr_odt : std_logic_vector(1 downto 0);
signal ddr_web : std_ulogic; -- ddr write enable
signal ddr_rasb : std_ulogic; -- ddr ras
signal ddr_casb : std_ulogic; -- ddr cas
signal ddr_dm : std_logic_vector (8 downto 0); -- ddr dm
signal ddr_dqsp : std_logic_vector (8 downto 0); -- ddr dqs
signal ddr_dqsn : std_logic_vector (8 downto 0); -- ddr dqs
signal ddr_rdqs : std_logic_vector (8 downto 0); -- ddr dqs
signal ddr_ad : std_logic_vector (15 downto 0); -- ddr address
signal ddr_ba : std_logic_vector (2 downto 0); -- ddr bank address
signal ddr_dq : std_logic_vector (71 downto 0); -- ddr data
signal ddr_dq2 : std_logic_vector (71 downto 0); -- ddr data
--signal ddra_cke : std_logic;
--signal ddra_csb : std_logic;
--signal ddra_web : std_ulogic; -- ddr write enable
--signal ddra_rasb : std_ulogic; -- ddr ras
--signal ddra_casb : std_ulogic; -- ddr cas
--signal ddra_ad : std_logic_vector (15 downto 0); -- ddr address
--signal ddra_ba : std_logic_vector (2 downto 0); -- ddr bank address
--signal ddrb_cke : std_logic;
--signal ddrb_csb : std_logic;
--signal ddrb_web : std_ulogic; -- ddr write enable
--signal ddrb_rasb : std_ulogic; -- ddr ras
--signal ddrb_casb : std_ulogic; -- ddr cas
--signal ddrb_ad : std_logic_vector (15 downto 0); -- ddr address
--signal ddrb_ba : std_logic_vector (2 downto 0); -- ddr bank address
--signal ddrab_clk : std_logic_vector(1 downto 0);
--signal ddrab_clkb : std_logic_vector(1 downto 0);
--signal ddrab_odt : std_logic_vector(1 downto 0);
--signal ddrab_dqsp : std_logic_vector(1 downto 0); -- ddr dqs
--signal ddrab_dqsn : std_logic_vector(1 downto 0); -- ddr dqs
--signal ddrab_dm : std_logic_vector(1 downto 0); -- ddr dm
--signal ddrab_dq : std_logic_vector (15 downto 0);-- ddr data
-- Ethernet
signal phy_mii_data: std_logic; -- ethernet PHY interface
signal phy_tx_clk : std_ulogic;
signal phy_rx_clk : std_ulogic;
signal phy_rx_data : std_logic_vector(7 downto 0);
signal phy_dv : std_ulogic;
signal phy_rx_er : std_ulogic;
signal phy_col : std_ulogic;
signal phy_crs : std_ulogic;
signal phy_tx_data : std_logic_vector(7 downto 0);
signal phy_tx_en : std_ulogic;
signal phy_tx_er : std_ulogic;
signal phy_mii_clk : std_ulogic;
signal phy_rst_n : std_ulogic;
signal phy_gtx_clk : std_ulogic;
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
clk125 <= not clk125 after 4 * 1 ns;
rst <= dsurst;
dsubren <= '1'; rxd1 <= '1';
address(0) <= '0';
ddr_dq(71 downto dbits) <= (others => 'H');
ddr_dq2(71 downto dbits) <= (others => 'H');
ddr_dqsp(8 downto dbits/8) <= (others => 'H');
ddr_dqsn(8 downto dbits/8) <= (others => 'H');
ddr_rdqs(8 downto dbits/8) <= (others => 'H');
ddr_dm(8 downto dbits/8) <= (others => 'H');
d3 : entity work.leon3mp
generic map (fabtech, memtech, padtech, clktech,
ncpu, disas, dbguart, pclow, 50000, dbits)
port map (rst, clk, clk125, error, dsubren, dsuact,
-- rxd1, txd1,
gpio, address(25 downto 1), data, open,
sram_advn, sram_csn, sram_wen, sram_ben, sram_oen, sram_clk, sram_psn, sram_wait,
flash_clk, flash_advn, flash_cen, flash_oen, flash_resetn, flash_wen,
max_csn, iosn,
ddr_clk, ddr_clkb, ddr_cke, ddr_csb, ddr_odt, ddr_web,
ddr_rasb, ddr_casb, ddr_dm, ddr_dqsp, ddr_dqsn, ddr_ad, ddr_ba, ddr_dq,
open, open,
-- ddra_cke, ddra_csb, ddra_web, ddra_rasb, ddra_casb, ddra_ad(14 downto 0), ddra_ba, ddrb_cke,
-- ddrb_csb, ddrb_web, ddrb_rasb, ddrb_casb, ddrb_ad(14 downto 0), ddrb_ba, ddrab_clk, ddrab_clkb,
-- ddrab_odt, ddrab_dqsp, ddrab_dqsn, ddrab_dm, ddrab_dq,
phy_gtx_clk, phy_mii_data, phy_tx_clk, phy_rx_clk,
phy_rx_data, phy_dv, phy_rx_er, phy_col, phy_crs,
phy_tx_data, phy_tx_en, phy_tx_er, phy_mii_clk, phy_rst_n
);
ddr2delay : delay_wire
generic map(data_width => dbits, delay_atob => 0.0, delay_btoa => 5.5)
port map(a => ddr_dq(dbits-1 downto 0), b => ddr_dq2(dbits-1 downto 0));
ddr0 : ddr2ram
generic map(width => dbits, abits => 13, babits =>2, colbits => 10, rowbits => 13,
implbanks => 1, fname => sdramfile, speedbin=>1, density => 2)
port map (ck => ddr_clk(0), ckn => ddr_clkb(0), cke => ddr_cke(0), csn => ddr_csb(0),
odt => ddr_odt(0), rasn => ddr_rasb, casn => ddr_casb, wen => ddr_web,
dm => ddr_dm(dbits/8-1 downto 0), ba => ddr_ba(1 downto 0),
a => ddr_ad(12 downto 0), dq => ddr_dq2(dbits-1 downto 0),
dqs => ddr_dqsp(dbits/8-1 downto 0), dqsn =>ddr_dqsn(dbits/8-1 downto 0));
-- 16 bit prom
prom0 : sram16 generic map (index => 4, abits => romdepth, fname => promfile)
port map (address(romdepth downto 1), data(31 downto 16),
gnd, gnd, flash_cen, flash_wen, flash_oen);
-- -- 32 bit prom
-- prom0 : for i in 0 to 3 generate
-- sr0 : sram generic map (index => i, abits => romdepth, fname => promfile)
-- port map (address(romdepth+1 downto 2), data(31-i*8 downto 24-i*8), flash_cen,
-- flash_wen, flash_oen);
-- end generate;
sram0 : for i in 0 to (sramwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
port map (address(sramdepth+1 downto 2), data(31-i*8 downto 24-i*8), sram_csn,
sram_wen, sram_oen);
end generate;
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
data <= buskeep(data), (others => 'H') after 250 ns;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data,
iosn, sram_oen, sram_wen, open);
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
| gpl-2.0 | 0992c14a3ddd64db60bb1d095c4c2c81 | 0.591746 | 3.037895 | false | false | false | false |
kloboves/sicxe | vhdl/debouncer.vhd | 1 | 3,491 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity debouncer is
Port (
clock_i : in std_logic;
reset_i : in std_logic;
input_i : in std_logic;
output_o : out std_logic;
change_on_o : out std_logic;
change_off_o : out std_logic
);
end debouncer;
architecture behavioral of debouncer is
-- input sync
signal input_sync : std_logic;
-- delay counter
signal delay_counter : std_logic_vector(15 downto 0);
signal delay_counter_reset : std_logic;
signal delay_counter_done : std_logic;
-- FSM
type state_type is (OFF_READY, OFF_WAIT, ON_READY, ON_WAIT);
signal state : state_type;
signal next_state : state_type;
begin
-- input sync
input_sync_proc : process(clock_i)
begin
if (rising_edge(clock_i)) then
input_sync <= input_i;
end if;
end process;
-- delay counter
delay_counter_proc : process(clock_i)
begin
if (rising_edge(clock_i)) then
if (reset_i = '1' or delay_counter_reset = '1') then
delay_counter <= (others => '0');
else
if (delay_counter = "1100001101010000") then
delay_counter <= (others => '0');
else
delay_counter <= delay_counter + 1;
end if;
end if;
end if;
end process;
delay_counter_done_proc : process(delay_counter)
begin
if (delay_counter = "1100001101010000") then
delay_counter_done <= '1';
else
delay_counter_done <= '0';
end if;
end process;
-- FSM
sync_proc : process(clock_i)
begin
if (rising_edge(clock_i)) then
if (reset_i = '1') then
if (input_sync = '1') then
state <= ON_READY;
else
state <= OFF_READY;
end if;
else
state <= next_state;
end if;
end if;
end process;
state_proc : process(state, input_sync, delay_counter_done)
begin
next_state <= state;
case (state) is
when OFF_READY =>
if (input_sync = '1') then
next_state <= OFF_WAIT;
end if;
when OFF_WAIT =>
if (delay_counter_done = '1') then
if (input_sync = '1') then
next_state <= ON_READY;
else
next_state <= OFF_READY;
end if;
end if;
when ON_READY =>
if (input_sync = '0') then
next_state <= ON_WAIT;
end if;
when ON_WAIT =>
if (delay_counter_done = '1') then
if (input_sync = '0') then
next_state <= OFF_READY;
else
next_state <= ON_READY;
end if;
end if;
when others =>
end case;
end process;
output_proc : process(state, input_sync, delay_counter_done)
begin
output_o <= '0';
change_on_o <= '0';
change_off_o <= '0';
delay_counter_reset <= '0';
case (state) is
when OFF_READY =>
output_o <= '0';
if (input_sync = '1') then
delay_counter_reset <= '1';
end if;
when OFF_WAIT =>
output_o <= '0';
if (delay_counter_done = '1' and input_sync = '1') then
change_on_o <= '1';
end if;
when ON_READY =>
output_o <= '1';
if (input_sync = '0') then
delay_counter_reset <= '1';
end if;
when ON_WAIT =>
output_o <= '1';
if (delay_counter_done = '1' and input_sync = '0') then
change_off_o <= '1';
end if;
when others =>
end case;
end process;
end behavioral;
| mit | 1b6fb14d259ab94694c779f1585c29c0 | 0.538528 | 3.449605 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-xilinx-sp601/testbench.vhd | 1 | 10,547 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.debug.all;
use work.config.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 37 -- system clock period
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sdramfile : string := "ram.srec"; -- sdram contents
constant lresp : boolean := false;
constant ct : integer := clkperiod/2;
signal clk : std_logic := '0';
signal clk200p : std_logic := '1';
signal clk200n : std_logic := '0';
signal rst : std_logic := '0';
signal rstn1 : std_logic;
signal rstn2 : std_logic;
signal error : std_logic;
-- PROM flash
signal address : std_logic_vector(23 downto 0);
signal data : std_logic_vector(31 downto 0);
signal romsn : std_logic;
signal oen : std_ulogic;
signal writen : std_ulogic;
signal iosn : std_ulogic;
-- DDR2 memory
signal ddr_clk : std_logic;
signal ddr_clkb : std_logic;
signal ddr_clk_fb : std_logic;
signal ddr_cke : std_logic;
signal ddr_csb : std_logic := '0';
signal ddr_we : std_ulogic; -- write enable
signal ddr_ras : std_ulogic; -- ras
signal ddr_cas : std_ulogic; -- cas
signal ddr_dm : std_logic_vector(1 downto 0); -- dm
signal ddr_dqs : std_logic_vector(1 downto 0); -- dqs
signal ddr_dqsn : std_logic_vector(1 downto 0); -- dqsn
signal ddr_ad : std_logic_vector(12 downto 0); -- address
signal ddr_ba : std_logic_vector(2 downto 0); -- bank address
signal ddr_dq : std_logic_vector(15 downto 0); -- data
signal ddr_dq2 : std_logic_vector(15 downto 0); -- data
signal ddr_odt : std_logic;
signal ddr_rzq : std_logic;
signal ddr_zio : std_logic;
-- Debug support unit
signal dsubre : std_ulogic;
-- AHB Uart
signal dsurx : std_ulogic;
signal dsutx : std_ulogic;
-- APB Uart
signal urxd : std_ulogic;
signal utxd : std_ulogic;
-- Ethernet signals
signal etx_clk : std_ulogic;
signal erx_clk : std_ulogic;
signal erxdt : std_logic_vector(7 downto 0);
signal erx_dv : std_ulogic;
signal erx_er : std_ulogic;
signal erx_col : std_ulogic;
signal erx_crs : std_ulogic;
signal etxdt : std_logic_vector(7 downto 0);
signal etx_en : std_ulogic;
signal etx_er : std_ulogic;
signal emdc : std_ulogic;
signal emdio : std_logic;
-- SVGA signals
signal vid_hsync : std_ulogic;
signal vid_vsync : std_ulogic;
signal vid_r : std_logic_vector(3 downto 0);
signal vid_g : std_logic_vector(3 downto 0);
signal vid_b : std_logic_vector(3 downto 0);
-- Select signal for SPI flash
signal spi_sel_n : std_logic;
signal spi_clk : std_logic;
signal spi_mosi : std_logic;
-- Output signals for LEDs
signal led : std_logic_vector(2 downto 0);
signal brdyn : std_ulogic;
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
clk200p <= not clk200p after 2.5 ns;
clk200n <= not clk200n after 2.5 ns;
rst <= '1', '0' after 100 ns;
dsubre <= '0';
urxd <= 'H';
spi_sel_n <= 'H';
spi_clk <= 'L';
d3 : entity work.leon3mp
generic map (fabtech, memtech, padtech, clktech, disas, dbguart, pclow)
port map (
reset => rst,
reset_o1 => rstn1,
reset_o2 => rstn2,
clk27 => clk,
clk200_p => clk200p,
clk200_n => clk200n,
errorn => error,
-- PROM
address => address(23 downto 0),
data => data(31 downto 24),
romsn => romsn,
oen => oen,
writen => writen,
iosn => iosn,
testdata => data(23 downto 0),
-- DDR2
ddr_clk => ddr_clk,
ddr_clkb => ddr_clkb,
ddr_cke => ddr_cke,
ddr_we => ddr_we,
ddr_ras => ddr_ras,
ddr_cas => ddr_cas,
ddr_dm => ddr_dm,
ddr_dqs => ddr_dqs,
ddr_dqsn => ddr_dqsn,
ddr_ad => ddr_ad,
ddr_ba => ddr_ba,
ddr_dq => ddr_dq,
ddr_odt => ddr_odt,
ddr_rzq => ddr_rzq,
ddr_zio => ddr_zio,
-- Debug Unit
dsubre => dsubre,
-- AHB Uart
dsutx => dsutx,
dsurx => dsurx,
-- PHY
etx_clk => etx_clk,
erx_clk => erx_clk,
erxd => erxdt(7 downto 0),
erx_dv => erx_dv,
erx_er => erx_er,
erx_col => erx_col,
erx_crs => erx_crs,
etxd => etxdt(7 downto 0),
etx_en => etx_en,
etx_er => etx_er,
emdc => emdc,
emdio => emdio,
-- SPI flash select
-- spi_sel_n => spi_sel_n,
-- spi_clk => spi_clk,
-- spi_mosi => spi_mosi,
-- Output signals for LEDs
led => led
);
migddr2mem : if (CFG_MIG_DDR2 = 1) generate
ddr2mem0: ddr2ram
generic map (width => 16, abits => 13, babits => 3,
colbits => 10, rowbits => 13, implbanks => 1,
fname => sdramfile, lddelay => (220 us),
speedbin => 1)
port map (ck => ddr_clk, ckn => ddr_clkb, cke => ddr_cke, csn => ddr_csb,
odt => ddr_odt, rasn => ddr_ras, casn => ddr_cas, wen => ddr_we,
dm => ddr_dm, ba => ddr_ba, a => ddr_ad,
dq => ddr_dq, dqs => ddr_dqs, dqsn => ddr_dqsn);
end generate;
ddr2mem : if (CFG_DDR2SP /= 0) generate
ddr2mem0: ddr2ram
generic map (width => 16, abits => 13, babits => 3,
colbits => 10, rowbits => 13, implbanks => 1,
fname => sdramfile, lddelay => (0 us),
speedbin => 1)
port map (ck => ddr_clk, ckn => ddr_clkb, cke => ddr_cke, csn => ddr_csb,
odt => ddr_odt, rasn => ddr_ras, casn => ddr_cas, wen => ddr_we,
dm => ddr_dm, ba => ddr_ba, a => ddr_ad,
dq => ddr_dq2, dqs => ddr_dqs, dqsn => ddr_dqsn);
ddr2delay0 : delay_wire
generic map(data_width => ddr_dq'length, delay_atob => 0.0, delay_btoa => 9.0)
port map(a => ddr_dq, b => ddr_dq2);
end generate;
prom0 : sram
generic map (index => 6, abits => 24, fname => promfile)
port map (address(23 downto 0), data(31 downto 24), romsn, writen, oen);
phy0 : if (CFG_GRETH = 1) generate
emdio <= 'H';
p0: phy
generic map (address => 1)
port map(rstn1, emdio, etx_clk, erx_clk, erxdt, erx_dv, erx_er,
erx_col, erx_crs, etxdt, etx_en, etx_er, emdc, '0');
end generate;
spimem0: if CFG_SPIMCTRL = 1 generate
s0 : spi_flash generic map (ftype => 4, debug => 0, fname => promfile,
readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => 0) -- Dual output is not supported in this design
port map (spi_clk, spi_mosi, data(24), spi_sel_n);
end generate spimem0;
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 5 us;
assert (to_X01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure;
end process;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data, iosn, oen, writen, brdyn);
data <= buskeep(data) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#ef#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
--
-- txc(dsutx, 16#80#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end;
| gpl-2.0 | d2b3a519711170275948124132d1b9ef | 0.538352 | 3.454635 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/leon3v3/dsu3.vhd | 1 | 2,465 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: dsu
-- File: dsu.vhd
-- Author: Jiri Gaisler, Edvin Catovic - Gaisler Research
-- Description: Combined LEON3 debug support and AHB trace unit
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.leon3.all;
library techmap;
use techmap.gencomp.all;
entity dsu3 is
generic (
hindex : integer := 0;
haddr : integer := 16#900#;
hmask : integer := 16#f00#;
ncpu : integer := 1;
tbits : integer := 30; -- timer bits (instruction trace time tag)
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 0;
testen : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
dbgi : in l3_debug_out_vector(0 to NCPU-1);
dbgo : out l3_debug_in_vector(0 to NCPU-1);
dsui : in dsu_in_type;
dsuo : out dsu_out_type
);
end;
architecture rtl of dsu3 is
signal gnd, vcc : std_ulogic;
begin
gnd <= '0'; vcc <= '1';
x0 : dsu3x generic map (hindex, haddr, hmask, ncpu, tbits, tech, irq, kbytes, 0, testen)
port map (rst, gnd, clk, ahbmi, ahbsi, ahbso, ahbsi, dbgi, dbgo, dsui, dsuo, vcc);
end;
| gpl-2.0 | 9d7e76e6f5f240bd0edf2d1d815637c6 | 0.59432 | 3.780675 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/adventures_with_ip/adventures_with_ip.cache/ip/2017.3/38a92fb39758d0fa/ip_design_rst_ps7_0_100M_0_sim_netlist.vhdl | 1 | 35,666 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 18:54:12 2017
-- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_rst_ps7_0_100M_0_sim_netlist.vhdl
-- Design : ip_design_rst_ps7_0_100M_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync is
port (
lpf_asr_reg : out STD_LOGIC;
scndry_out : out STD_LOGIC;
lpf_asr : in STD_LOGIC;
asr_lpf : in STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : in STD_LOGIC;
p_2_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync is
signal asr_d1 : STD_LOGIC;
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
signal \^scndry_out\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
begin
scndry_out <= \^scndry_out\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => asr_d1,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aux_reset_in,
O => asr_d1
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d3,
Q => \^scndry_out\,
R => '0'
);
lpf_asr_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EAAAAAA8"
)
port map (
I0 => lpf_asr,
I1 => asr_lpf(0),
I2 => \^scndry_out\,
I3 => p_1_in,
I4 => p_2_in,
O => lpf_asr_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 is
port (
lpf_exr_reg : out STD_LOGIC;
scndry_out : out STD_LOGIC;
lpf_exr : in STD_LOGIC;
p_3_out : in STD_LOGIC_VECTOR ( 2 downto 0 );
mb_debug_sys_rst : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 : entity is "cdc_sync";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 is
signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0\ : STD_LOGIC;
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
signal \^scndry_out\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
begin
scndry_out <= \^scndry_out\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0\,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => mb_debug_sys_rst,
I1 => ext_reset_in,
O => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0\
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d3,
Q => \^scndry_out\,
R => '0'
);
lpf_exr_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EAAAAAA8"
)
port map (
I0 => lpf_exr,
I1 => p_3_out(0),
I2 => \^scndry_out\,
I3 => p_3_out(1),
I4 => p_3_out(2),
O => lpf_exr_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n is
port (
Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
seq_clr : in STD_LOGIC;
seq_cnt_en : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n is
signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal clear : STD_LOGIC;
signal q_int0 : STD_LOGIC_VECTOR ( 5 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \q_int[1]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \q_int[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \q_int[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \q_int[4]_i_1\ : label is "soft_lutpair0";
begin
Q(5 downto 0) <= \^q\(5 downto 0);
\q_int[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => q_int0(0)
);
\q_int[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => q_int0(1)
);
\q_int[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => q_int0(2)
);
\q_int[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => q_int0(3)
);
\q_int[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \^q\(4),
O => q_int0(4)
);
\q_int[5]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => seq_clr,
O => clear
);
\q_int[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(4),
I5 => \^q\(5),
O => q_int0(5)
);
\q_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(0),
Q => \^q\(0),
R => clear
);
\q_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(1),
Q => \^q\(1),
R => clear
);
\q_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(2),
Q => \^q\(2),
R => clear
);
\q_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(3),
Q => \^q\(3),
R => clear
);
\q_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(4),
Q => \^q\(4),
R => clear
);
\q_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(5),
Q => \^q\(5),
R => clear
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf is
port (
lpf_int : out STD_LOGIC;
slowest_sync_clk : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
ext_reset_in : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf is
signal \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\ : STD_LOGIC;
signal \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\ : STD_LOGIC;
signal Q : STD_LOGIC;
signal asr_lpf : STD_LOGIC_VECTOR ( 0 to 0 );
signal lpf_asr : STD_LOGIC;
signal lpf_exr : STD_LOGIC;
signal \lpf_int0__0\ : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal p_2_in : STD_LOGIC;
signal p_3_in1_in : STD_LOGIC;
signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of POR_SRL_I : label is "SRL16";
attribute box_type : string;
attribute box_type of POR_SRL_I : label is "PRIMITIVE";
attribute srl_name : string;
attribute srl_name of POR_SRL_I : label is "U0/\EXT_LPF/POR_SRL_I ";
begin
\ACTIVE_LOW_AUX.ACT_LO_AUX\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync
port map (
asr_lpf(0) => asr_lpf(0),
aux_reset_in => aux_reset_in,
lpf_asr => lpf_asr,
lpf_asr_reg => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\,
p_1_in => p_1_in,
p_2_in => p_2_in,
scndry_out => p_3_in1_in,
slowest_sync_clk => slowest_sync_clk
);
\ACTIVE_LOW_EXT.ACT_LO_EXT\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0
port map (
ext_reset_in => ext_reset_in,
lpf_exr => lpf_exr,
lpf_exr_reg => \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\,
mb_debug_sys_rst => mb_debug_sys_rst,
p_3_out(2 downto 0) => p_3_out(2 downto 0),
scndry_out => p_3_out(3),
slowest_sync_clk => slowest_sync_clk
);
\AUX_LPF[1].asr_lpf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_in1_in,
Q => p_2_in,
R => '0'
);
\AUX_LPF[2].asr_lpf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_2_in,
Q => p_1_in,
R => '0'
);
\AUX_LPF[3].asr_lpf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_1_in,
Q => asr_lpf(0),
R => '0'
);
\EXT_LPF[1].exr_lpf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(3),
Q => p_3_out(2),
R => '0'
);
\EXT_LPF[2].exr_lpf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(2),
Q => p_3_out(1),
R => '0'
);
\EXT_LPF[3].exr_lpf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(1),
Q => p_3_out(0),
R => '0'
);
POR_SRL_I: unisim.vcomponents.SRL16E
generic map(
INIT => X"FFFF"
)
port map (
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
CE => '1',
CLK => slowest_sync_clk,
D => '0',
Q => Q
);
lpf_asr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\,
Q => lpf_asr,
R => '0'
);
lpf_exr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\,
Q => lpf_exr,
R => '0'
);
lpf_int0: unisim.vcomponents.LUT4
generic map(
INIT => X"FFEF"
)
port map (
I0 => Q,
I1 => lpf_asr,
I2 => dcm_locked,
I3 => lpf_exr,
O => \lpf_int0__0\
);
lpf_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \lpf_int0__0\,
Q => lpf_int,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr is
port (
MB_out : out STD_LOGIC;
Bsr_out : out STD_LOGIC;
Pr_out : out STD_LOGIC;
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ : out STD_LOGIC;
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ : out STD_LOGIC;
lpf_int : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr is
signal \^bsr_out\ : STD_LOGIC;
signal Core_i_1_n_0 : STD_LOGIC;
signal \^mb_out\ : STD_LOGIC;
signal \^pr_out\ : STD_LOGIC;
signal \bsr_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \bsr_dec_reg_n_0_[2]\ : STD_LOGIC;
signal bsr_i_1_n_0 : STD_LOGIC;
signal \core_dec[0]_i_1_n_0\ : STD_LOGIC;
signal \core_dec[2]_i_1_n_0\ : STD_LOGIC;
signal \core_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \core_dec_reg_n_0_[1]\ : STD_LOGIC;
signal from_sys_i_1_n_0 : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal p_3_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_5_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \pr_dec0__0\ : STD_LOGIC;
signal \pr_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \pr_dec_reg_n_0_[2]\ : STD_LOGIC;
signal pr_i_1_n_0 : STD_LOGIC;
signal seq_clr : STD_LOGIC;
signal seq_cnt : STD_LOGIC_VECTOR ( 5 downto 0 );
signal seq_cnt_en : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of Core_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \bsr_dec[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of bsr_i_1 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \core_dec[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \core_dec[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of from_sys_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \pr_dec[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of pr_i_1 : label is "soft_lutpair4";
begin
Bsr_out <= \^bsr_out\;
MB_out <= \^mb_out\;
Pr_out <= \^pr_out\;
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^bsr_out\,
O => \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\
);
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^pr_out\,
O => \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\
);
Core_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^mb_out\,
I1 => p_0_in,
O => Core_i_1_n_0
);
Core_reg: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Core_i_1_n_0,
Q => \^mb_out\,
S => lpf_int
);
SEQ_COUNTER: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n
port map (
Q(5 downto 0) => seq_cnt(5 downto 0),
seq_clr => seq_clr,
seq_cnt_en => seq_cnt_en,
slowest_sync_clk => slowest_sync_clk
);
\bsr_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0804"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(3),
I2 => seq_cnt(5),
I3 => seq_cnt(4),
O => p_5_out(0)
);
\bsr_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \bsr_dec_reg_n_0_[0]\,
O => p_5_out(2)
);
\bsr_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_5_out(0),
Q => \bsr_dec_reg_n_0_[0]\,
R => '0'
);
\bsr_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_5_out(2),
Q => \bsr_dec_reg_n_0_[2]\,
R => '0'
);
bsr_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^bsr_out\,
I1 => \bsr_dec_reg_n_0_[2]\,
O => bsr_i_1_n_0
);
bsr_reg: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => bsr_i_1_n_0,
Q => \^bsr_out\,
S => lpf_int
);
\core_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8040"
)
port map (
I0 => seq_cnt(4),
I1 => seq_cnt(3),
I2 => seq_cnt(5),
I3 => seq_cnt_en,
O => \core_dec[0]_i_1_n_0\
);
\core_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \core_dec_reg_n_0_[0]\,
O => \core_dec[2]_i_1_n_0\
);
\core_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \core_dec[0]_i_1_n_0\,
Q => \core_dec_reg_n_0_[0]\,
R => '0'
);
\core_dec_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \pr_dec0__0\,
Q => \core_dec_reg_n_0_[1]\,
R => '0'
);
\core_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \core_dec[2]_i_1_n_0\,
Q => p_0_in,
R => '0'
);
from_sys_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^mb_out\,
I1 => seq_cnt_en,
O => from_sys_i_1_n_0
);
from_sys_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => from_sys_i_1_n_0,
Q => seq_cnt_en,
S => lpf_int
);
pr_dec0: unisim.vcomponents.LUT4
generic map(
INIT => X"0210"
)
port map (
I0 => seq_cnt(0),
I1 => seq_cnt(1),
I2 => seq_cnt(2),
I3 => seq_cnt_en,
O => \pr_dec0__0\
);
\pr_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"1080"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(5),
I2 => seq_cnt(3),
I3 => seq_cnt(4),
O => p_3_out(0)
);
\pr_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \pr_dec_reg_n_0_[0]\,
O => p_3_out(2)
);
\pr_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(0),
Q => \pr_dec_reg_n_0_[0]\,
R => '0'
);
\pr_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(2),
Q => \pr_dec_reg_n_0_[2]\,
R => '0'
);
pr_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^pr_out\,
I1 => \pr_dec_reg_n_0_[2]\,
O => pr_i_1_n_0
);
pr_reg: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => pr_i_1_n_0,
Q => \^pr_out\,
S => lpf_int
);
seq_clr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => '1',
Q => seq_clr,
R => lpf_int
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute C_AUX_RESET_HIGH : string;
attribute C_AUX_RESET_HIGH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is "1'b0";
attribute C_AUX_RST_WIDTH : integer;
attribute C_AUX_RST_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 4;
attribute C_EXT_RESET_HIGH : string;
attribute C_EXT_RESET_HIGH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is "1'b0";
attribute C_EXT_RST_WIDTH : integer;
attribute C_EXT_RST_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 4;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is "zynq";
attribute C_NUM_BUS_RST : integer;
attribute C_NUM_BUS_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1;
attribute C_NUM_INTERCONNECT_ARESETN : integer;
attribute C_NUM_INTERCONNECT_ARESETN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1;
attribute C_NUM_PERP_ARESETN : integer;
attribute C_NUM_PERP_ARESETN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1;
attribute C_NUM_PERP_RST : integer;
attribute C_NUM_PERP_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1;
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset is
signal Bsr_out : STD_LOGIC;
signal MB_out : STD_LOGIC;
signal Pr_out : STD_LOGIC;
signal SEQ_n_3 : STD_LOGIC;
signal SEQ_n_4 : STD_LOGIC;
signal lpf_int : STD_LOGIC;
attribute box_type : string;
attribute box_type of \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ : label is "PRIMITIVE";
attribute box_type of \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ : label is "PRIMITIVE";
attribute box_type of \BSR_OUT_DFF[0].FDRE_BSR\ : label is "PRIMITIVE";
attribute box_type of FDRE_inst : label is "PRIMITIVE";
attribute box_type of \PR_OUT_DFF[0].FDRE_PER\ : label is "PRIMITIVE";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of bus_struct_reset : signal is "no";
attribute equivalent_register_removal of interconnect_aresetn : signal is "no";
attribute equivalent_register_removal of peripheral_aresetn : signal is "no";
attribute equivalent_register_removal of peripheral_reset : signal is "no";
begin
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => SEQ_n_3,
Q => interconnect_aresetn(0),
R => '0'
);
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => SEQ_n_4,
Q => peripheral_aresetn(0),
R => '0'
);
\BSR_OUT_DFF[0].FDRE_BSR\: unisim.vcomponents.FDRE
generic map(
INIT => '1',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Bsr_out,
Q => bus_struct_reset(0),
R => '0'
);
EXT_LPF: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf
port map (
aux_reset_in => aux_reset_in,
dcm_locked => dcm_locked,
ext_reset_in => ext_reset_in,
lpf_int => lpf_int,
mb_debug_sys_rst => mb_debug_sys_rst,
slowest_sync_clk => slowest_sync_clk
);
FDRE_inst: unisim.vcomponents.FDRE
generic map(
INIT => '1',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => MB_out,
Q => mb_reset,
R => '0'
);
\PR_OUT_DFF[0].FDRE_PER\: unisim.vcomponents.FDRE
generic map(
INIT => '1',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Pr_out,
Q => peripheral_reset(0),
R => '0'
);
SEQ: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr
port map (
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ => SEQ_n_3,
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ => SEQ_n_4,
Bsr_out => Bsr_out,
MB_out => MB_out,
Pr_out => Pr_out,
lpf_int => lpf_int,
slowest_sync_clk => slowest_sync_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "ip_design_rst_ps7_0_100M_0,proc_sys_reset,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "proc_sys_reset,Vivado 2017.3";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute C_AUX_RESET_HIGH : string;
attribute C_AUX_RESET_HIGH of U0 : label is "1'b0";
attribute C_AUX_RST_WIDTH : integer;
attribute C_AUX_RST_WIDTH of U0 : label is 4;
attribute C_EXT_RESET_HIGH : string;
attribute C_EXT_RESET_HIGH of U0 : label is "1'b0";
attribute C_EXT_RST_WIDTH : integer;
attribute C_EXT_RST_WIDTH of U0 : label is 4;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_NUM_BUS_RST : integer;
attribute C_NUM_BUS_RST of U0 : label is 1;
attribute C_NUM_INTERCONNECT_ARESETN : integer;
attribute C_NUM_INTERCONNECT_ARESETN of U0 : label is 1;
attribute C_NUM_PERP_ARESETN : integer;
attribute C_NUM_PERP_ARESETN of U0 : label is 1;
attribute C_NUM_PERP_RST : integer;
attribute C_NUM_PERP_RST of U0 : label is 1;
attribute x_interface_info : string;
attribute x_interface_info of aux_reset_in : signal is "xilinx.com:signal:reset:1.0 aux_reset RST";
attribute x_interface_parameter : string;
attribute x_interface_parameter of aux_reset_in : signal is "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW";
attribute x_interface_info of ext_reset_in : signal is "xilinx.com:signal:reset:1.0 ext_reset RST";
attribute x_interface_parameter of ext_reset_in : signal is "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW";
attribute x_interface_info of mb_debug_sys_rst : signal is "xilinx.com:signal:reset:1.0 dbg_reset RST";
attribute x_interface_parameter of mb_debug_sys_rst : signal is "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH";
attribute x_interface_info of mb_reset : signal is "xilinx.com:signal:reset:1.0 mb_rst RST";
attribute x_interface_parameter of mb_reset : signal is "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR";
attribute x_interface_info of slowest_sync_clk : signal is "xilinx.com:signal:clock:1.0 clock CLK";
attribute x_interface_parameter of slowest_sync_clk : signal is "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0";
attribute x_interface_info of bus_struct_reset : signal is "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
attribute x_interface_parameter of bus_struct_reset : signal is "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT";
attribute x_interface_info of interconnect_aresetn : signal is "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
attribute x_interface_parameter of interconnect_aresetn : signal is "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT";
attribute x_interface_info of peripheral_aresetn : signal is "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
attribute x_interface_parameter of peripheral_aresetn : signal is "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL";
attribute x_interface_info of peripheral_reset : signal is "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
attribute x_interface_parameter of peripheral_reset : signal is "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL";
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset
port map (
aux_reset_in => aux_reset_in,
bus_struct_reset(0) => bus_struct_reset(0),
dcm_locked => dcm_locked,
ext_reset_in => ext_reset_in,
interconnect_aresetn(0) => interconnect_aresetn(0),
mb_debug_sys_rst => mb_debug_sys_rst,
mb_reset => mb_reset,
peripheral_aresetn(0) => peripheral_aresetn(0),
peripheral_reset(0) => peripheral_reset(0),
slowest_sync_clk => slowest_sync_clk
);
end STRUCTURE;
| mit | 2851ca0e375433d19aa2665c425ad957 | 0.589637 | 2.911748 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/adventures_with_ip/adventures_with_ip.srcs/sources_1/bd/ip_design/ip/ip_design_rst_ps7_0_100M_0/synth/ip_design_rst_ps7_0_100M_0.vhd | 1 | 8,103 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 12
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0_12;
USE proc_sys_reset_v5_0_12.proc_sys_reset;
ENTITY ip_design_rst_ps7_0_100M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END ip_design_rst_ps7_0_100M_0;
ARCHITECTURE ip_design_rst_ps7_0_100M_0_arch OF ip_design_rst_ps7_0_100M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ip_design_rst_ps7_0_100M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF ip_design_rst_ps7_0_100M_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2017.3";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF ip_design_rst_ps7_0_100M_0_arch : ARCHITECTURE IS "ip_design_rst_ps7_0_100M_0,proc_sys_reset,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF ip_design_rst_ps7_0_100M_0_arch: ARCHITECTURE IS "ip_design_rst_ps7_0_100M_0,proc_sys_reset,{x_ipProduct=Vivado 2017.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=12,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_aresetn: SIGNAL IS "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF interconnect_aresetn: SIGNAL IS "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_reset: SIGNAL IS "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF bus_struct_reset: SIGNAL IS "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF mb_reset: SIGNAL IS "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF mb_debug_sys_rst: SIGNAL IS "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF aux_reset_in: SIGNAL IS "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF ext_reset_in: SIGNAL IS "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF slowest_sync_clk: SIGNAL IS "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0";
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END ip_design_rst_ps7_0_100M_0_arch;
| mit | f07d6225bdaf9c97ef23d91d2afe88ee | 0.728866 | 3.495686 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/grlib/stdlib/stdio_tb.vhd | 1 | 4,719 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--------------------------------------------------------------------------------
-- Package: StdIO
-- File: stdio.vhd
-- Author: Gaisler Research
-- Description: Package for common I/O functions
--------------------------------------------------------------------------------
library Std;
use Std.Standard.all;
use Std.TextIO.all;
library IEEE;
use IEEE.Std_Logic_1164.all;
library GRLIB;
use GRLIB.StdIO.all;
entity StdIO_TB is
end entity StdIO_TB;
architecture Behavioural of StdIO_TB is
begin
process
variable LW: Line;
variable LR: Line;
file WFile: Text;
file RFile: Text;
constant SUL: Std_ULogic := 'H';
constant SL: Std_Logic := 'L';
constant SULV1: Std_ULogic_Vector := "1";
constant SULV2: Std_ULogic_Vector := "10";
constant SULV3: Std_ULogic_Vector := "011";
constant SULV4: Std_ULogic_Vector := "0100";
constant SULV5: Std_ULogic_Vector := "00101";
constant SULV6: Std_ULogic_Vector := "000110";
constant SULV7: Std_ULogic_Vector := "0000111";
constant SULV8: Std_ULogic_Vector := "00001000";
constant SULV9: Std_ULogic_Vector := "000001001";
constant SULVA: Std_ULogic_Vector := "00000001001000110100010101100111";
constant SULVB: Std_ULogic_Vector := "10001001101010111100110111101111";
variable SULVC: Std_ULogic_Vector(0 to 3);
variable SULVD: Std_ULogic_Vector(0 to 7);
variable SULVE: Std_ULogic_Vector(0 to 15);
variable SULVF: Std_ULogic_Vector(0 to 16);
constant SLVA: Std_Logic_Vector := "00000001001000110100010101100111";
constant SLVB: Std_Logic_Vector := "10001001101010111100110111101111";
variable SLVC: Std_Logic_Vector(0 to 7);
variable SLVD: Std_Logic_Vector(0 to 15);
begin
Write(LW, SUL);
WriteLine(Output, LW);
Write(LW, SL);
WriteLine(Output, LW);
HWrite(LW, SULV1);
WriteLine(Output, LW);
HWrite(LW, SULV2);
WriteLine(Output, LW);
HWrite(LW, SULV3);
WriteLine(Output, LW);
HWrite(LW, SULV4);
WriteLine(Output, LW);
HWrite(LW, SULV5);
WriteLine(Output, LW);
HWrite(LW, SULV6);
WriteLine(Output, LW);
HWrite(LW, SULV7);
WriteLine(Output, LW);
HWrite(LW, SULV8);
WriteLine(Output, LW);
HWrite(LW, SULV9);
WriteLine(Output, LW);
HWrite(LW, SULVA);
WriteLine(Output, LW);
HWrite(LW, SULVB);
WriteLine(Output, LW);
File_Open(WFile, "file.txt", Write_Mode);
HWrite(LW, SULVA);
WriteLine(WFile, LW);
HWrite(LW, SULVB);
WriteLine(WFile, LW);
HWrite(LW, SULVA);
WriteLine(WFile, LW);
HWrite(LW, SULVB);
WriteLine(WFile, LW);
HWrite(LW, SLVA);
WriteLine(WFile, LW);
HWrite(LW, SLVB);
WriteLine(WFile, LW);
File_Close(WFile);
File_Open(RFile, "file.txt", Read_Mode);
ReadLine(RFile, LR);
HRead(LR, SULVC);
HWrite(LW, SULVC);
WriteLine(Output, LW);
ReadLine(RFile, LR);
HRead(LR, SULVD);
HWrite(LW, SULVD);
WriteLine(Output, LW);
ReadLine(RFile, LR);
HRead(LR, SULVE);
HWrite(LW, SULVE);
WriteLine(Output, LW);
ReadLine(RFile, LR);
HRead(LR, SULVF);
HWrite(LW, SULVF);
WriteLine(Output, LW);
ReadLine(RFile, LR);
HRead(LR, SLVC);
HWrite(LW, SLVC);
WriteLine(Output, LW);
ReadLine(RFile, LR);
HRead(LR, SLVD);
HWrite(LW, SLVD);
WriteLine(Output, LW);
File_Close(RFile);
wait;
end process;
end architecture Behavioural;
| gpl-2.0 | f0a9b685611b9d612957845b66df06d4 | 0.581903 | 3.845966 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/ddr/ddr2buf.vhd | 1 | 6,717 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddr2buf
-- File: ddr2buf.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Convenience wrapper for syncram2p with data width conversion
--------------------------------------------------------------------------------
-- 2^rabits x rdbits determines amount of RAM.
--
-- If 2^wabits x wdbits is larger than this, the lowest bits of waddress are
-- used for sub-size writes. writebig ignores these lower bits and writes the
-- full data vector at once.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
entity ddr2buf is
generic (tech : integer := 0; wabits : integer := 6; wdbits : integer := 8;
rabits : integer := 6; rdbits : integer := 8;
sepclk : integer := 0; wrfst : integer := 0; testen : integer := 0);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((rabits-1) downto 0);
dataout : out std_logic_vector((rdbits-1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
writebig : in std_ulogic;
waddress : in std_logic_vector((wabits-1) downto 0);
datain : in std_logic_vector((wdbits-1) downto 0);
testin : in std_logic_vector(3 downto 0) := "0000");
end;
architecture rtl of ddr2buf is
function xlog2(x: integer) return integer is
variable q,r: integer;
begin
r := 0; q := 1;
while x > q loop
q := q+q; r := r+1;
end loop;
return r;
end xlog2;
function xmax(a,b: integer) return integer is
begin
if a>b then return a; else return b; end if;
end xmax;
function xmin(a,b: integer) return integer is
begin
if a<b then return a; else return b; end if;
end xmin;
constant membits : integer := (2**rabits) * rdbits;
constant wabitsbig : integer := xlog2(membits/wdbits);
constant wdbitsbig : integer := wdbits;
constant wabitssml : integer := wabits;
constant wdbitssml : integer := membits / (2**wabits);
constant totdwidth: integer := xmax(wdbitsbig,rdbits);
constant partdwidth: integer := wdbitssml;
constant nrams : integer := totdwidth/partdwidth;
constant dbits : integer := wdbitssml;
constant abits : integer := xlog2(membits/(dbits*nrams));
constant rdratio : integer := rdbits/dbits;
constant wdratio : integer := wdbitsbig/dbits;
type dv_type is array (0 to nrams-1) of std_logic_vector(dbits-1 downto 0);
signal do: dv_type;
signal di: dv_type;
signal we: std_logic_vector(0 to nrams-1);
signal prev_raddress: std_logic_vector(rabits-1 downto 0);
begin
regs: process(rclk)
begin
if rising_edge(rclk) then
prev_raddress <= raddress;
end if;
end process;
comb: process(prev_raddress,write,writebig,waddress,datain,do)
type rdvx_type is array (0 to totdwidth/rdbits-1) of std_logic_vector(rdbits-1 downto 0);
variable rdvx: rdvx_type;
variable vdo: std_logic_vector((rdbits-1) downto 0);
variable vdi: dv_type;
variable vwe: std_logic_vector(0 to nrams-1);
variable we1: std_logic_vector(0 to wdbitsbig/wdbitssml-1);
variable we2: std_logic_vector(0 to wdratio-1);
begin
vdi := (others => (others => '0'));
vwe := (others => '0');
-- Generate rdvx from do
for x in 0 to nrams-1 loop
if rdbits > dbits then
rdvx(x/rdratio)(rdbits-1-(x mod rdratio)*dbits downto rdbits-dbits-(x mod rdratio)*dbits) := do(x);
else
for y in 0 to dbits/rdbits-1 loop
rdvx(x*dbits/rdbits + y) := do(x)(dbits-1-y*rdbits downto dbits-rdbits-y*rdbits);
end loop;
end if;
end loop;
-- Generate dataout from rdvx and prev_address
vdo := rdvx(totdwidth/rdbits-1);
if totdwidth > rdbits then
for x in 0 to totdwidth/rdbits-2 loop
if prev_raddress(log2(totdwidth/rdbits)-1 downto 0) =
std_logic_vector(to_unsigned(x,log2(totdwidth/rdbits))) then
vdo := rdvx(x);
end if;
end loop;
end if;
-- Generate vdi from datain
for x in 0 to nrams-1 loop
vdi(x) := datain(wdbits-(x mod wdratio)*dbits-1 downto wdbits-(x mod wdratio)*dbits-dbits);
end loop;
-- Generate we2 from write/writebig
we2 := (others => writebig);
if wdbitsbig > wdbitssml then
for x in 0 to wdbitsbig/wdbitssml-1 loop
if write='1' and waddress(log2(wdbitsbig/wdbitssml)-1 downto 0) =
std_logic_vector(to_unsigned(x,log2(wdbitsbig/wdbitssml))) then
we2(x*wdbitssml/dbits to (x+1)*wdbitssml/dbits-1) := (others => '1');
end if;
end loop;
else
if write='1' then we2:=(others => '1'); end if;
end if;
-- Generate write-enable from we2
vwe := (others => '0');
if totdwidth > wdbitsbig then
for x in 0 to totdwidth/wdbitsbig-1 loop
if waddress(log2(totdwidth/wdbitssml)-1 downto log2(wdbitsbig/wdbitssml))=
std_logic_vector(to_unsigned(x,log2(totdwidth/wdbitsbig))) then
vwe(x*wdratio to (x+1)*wdratio-1) := we2;
end if;
end loop;
else
vwe := we2;
end if;
dataout <= vdo;
di <= vdi;
we <= vwe;
end process;
ramgen: for x in 0 to nrams-1 generate
r: syncram_2p generic map (tech,abits,dbits,sepclk,wrfst,testen)
port map (rclk => rclk,renable => renable,
raddress => raddress((rabits-1) downto (rabits-abits)),
dataout => do(x),wclk => wclk,write => we(x),
waddress => waddress((wabits-1) downto (wabits-abits)),
datain => di(x), testin => testin);
end generate;
end;
| gpl-2.0 | 97edd82b6cdb98fa56a15e03e04d73da | 0.619026 | 3.674508 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/leon3v3/mmu_dcache.vhd | 1 | 66,870 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: mmu_dcache
-- File: mmu_dcache.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Modified: Edvin Catovic - Gaisler Research
-- Description: This unit implements the data cache controller.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.sparc.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.libmmu.all;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
entity mmu_dcache is
generic (
dsu : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 0;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
ilram : integer range 0 to 1 := 0;
ilramstart : integer range 0 to 255 := 16#8e#;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
memtech : integer range 0 to NTECH := 0;
cached : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
smp : integer := 0;
mmuen : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
dci : in dcache_in_type;
dco : out dcache_out_type;
ico : in icache_out_type;
mcdi : out memory_dc_in_type;
mcdo : in memory_dc_out_type;
ahbsi : in ahb_slv_in_type;
dcrami : out dcram_in_type;
dcramo : in dcram_out_type;
fpuholdn : in std_ulogic;
mmudci : out mmudc_in_type;
mmudco : in mmudc_out_type;
sclk : in std_ulogic;
ahbso : in ahb_slv_out_vector
);
end;
architecture rtl of mmu_dcache is
constant M_EN : boolean := (mmuen = 1);
constant DSNOOP2 : integer := dsnoop mod 4;
constant DSNOOPSEP : boolean := (dsnoop > 3);
constant M_TLB_TYPE : integer range 0 to 1 := -- either split or combined
conv_integer(conv_std_logic_vector(tlb_type, 2) and conv_std_logic_vector(1, 2));
constant M_TLB_FASTWRITE : integer range 0 to 3 := -- fast writebuffer
conv_integer(conv_std_logic_vector(tlb_type, 2) and conv_std_logic_vector(2, 2));
constant M_ENT_I : integer range 2 to 64 := itlbnum; -- icache tlb entries: number
constant M_ENT_ILOG : integer := log2(M_ENT_I); -- icache tlb entries: address bits
constant M_ENT_D : integer range 2 to 64 := dtlbnum; -- dcache tlb entries: number
constant M_ENT_DLOG : integer := log2(M_ENT_D); -- dcache tlb entries: address bits
constant M_ENT_C : integer range 2 to 64 := M_ENT_I; -- i/dcache tlb entries: number
constant M_ENT_CLOG : integer := M_ENT_ILOG; -- i/dcache tlb entries: address bits
constant DLINE_BITS : integer := log2(dlinesize);
constant DOFFSET_BITS : integer := 8 +log2(dsetsize) - DLINE_BITS;
constant LRR_BIT : integer := TAG_HIGH + 1;
constant TAG_LOW : integer := DOFFSET_BITS + DLINE_BITS + 2;
constant OFFSET_HIGH : integer := TAG_LOW - 1;
constant OFFSET_LOW : integer := DLINE_BITS + 2;
constant LINE_HIGH : integer := OFFSET_LOW - 1;
constant LINE_LOW : integer := 2;
constant LINE_ZERO : std_logic_vector(DLINE_BITS-1 downto 0) := (others => '0');
constant SETBITS : integer := log2x(DSETS);
constant DLRUBITS : integer := lru_table(DSETS);
constant LOCAL_RAM_START : std_logic_vector(7 downto 0) :=
conv_std_logic_vector(dlramstart, 8);
constant ILRAM_START : std_logic_vector(7 downto 0) :=
conv_std_logic_vector(ilramstart, 8);
constant DIR_BITS : integer := log2x(DSETS);
constant bend : std_logic_vector(4 downto 2) := "101";
type rdatatype is (dtag, ddata, dddata, dctx, icache, memory,
sysr , misc, mmusnoop_dtag); -- sources during cache read
type vmasktype is (clearone, clearall, merge, tnew); -- valid bits operation
type valid_type is array (0 to DSETS-1) of std_logic_vector(dlinesize - 1 downto 0);
type write_buffer_type is record -- write buffer
addr, data1, data2 : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
asi : std_logic_vector(3 downto 0);
read : std_ulogic;
lock : std_ulogic;
smask : std_logic_vector(DSETS-1 downto 0);-- snoop mask
end record;
type dstatetype is (idle, wread, rtrans, wwrite, wtrans, wflush,
asi_idtag, dblwrite, loadpend);
type dcache_control_type is record -- all registers
read : std_ulogic; -- access direction
size : std_logic_vector(1 downto 0); -- access size
req, burst, rburst, holdn, nomds, stpend : std_ulogic;
xaddress : std_logic_vector(31 downto 0); -- common address buffer
paddress : std_logic_vector(31 downto 0); -- physical address buffer
faddr : std_logic_vector(DOFFSET_BITS - 1 downto 0); -- flush address
efaddr : std_logic_vector(DOFFSET_BITS - 1 downto 0); -- error flush address
dstate : dstatetype; -- FSM vector
hit, valid : std_ulogic;
flush : std_ulogic; -- flush in progress
flush2 : std_ulogic; -- flush in progress
mexc : std_ulogic; -- latched mexc
bmexc : std_ulogic; -- latched mexc from burst read
wb : write_buffer_type; -- write buffer
asi : std_logic_vector(4 downto 0);
icenable : std_ulogic; -- icache diag access
rndcnt : std_logic_vector(log2x(DSETS)-1 downto 0); -- replace counter
setrepl : std_logic_vector(log2x(DSETS)-1 downto 0); -- set to replace
lrr : std_ulogic;
dsuset : std_logic_vector(log2x(DSETS)-1 downto 0);
lock : std_ulogic;
lramrd : std_ulogic;
ilramen : std_ulogic;
cctrl : cctrltype;
cctrlwr : std_ulogic;
flushl2 : std_ulogic;
tadj, dadj, sadj : std_logic_vector(1 downto 0);
mmctrl1 : mmctrl_type1;
mmctrl1wr : std_ulogic;
pflush : std_logic;
pflushr : std_logic;
pflushaddr : std_logic_vector(VA_I_U downto VA_I_D);
pflushtyp : std_logic;
vaddr : std_logic_vector(31 downto 0);
ready : std_logic;
wbinit : std_logic;
cache : std_logic;
dlock : std_logic;
su : std_logic;
trans_op : std_logic;
flush_op : std_logic;
diag_op : std_logic;
reqst : std_logic;
set : integer range 0 to DSETS-1;
noflush : std_logic;
end record;
type snoop_reg_type is record -- snoop control registers
snoop : std_ulogic; -- snoop access to tags
addr : std_logic_vector(TAG_HIGH downto OFFSET_LOW);-- snoop tag address
mask : std_logic_vector(DSETS-1 downto 0);-- snoop mask
snhit : std_logic_vector(0 to MAXSETS-1);
end record;
subtype lru_type is std_logic_vector(DLRUBITS-1 downto 0);
type lru_array is array (0 to 2**DOFFSET_BITS-1) of lru_type; -- lru registers
type lru_reg_type is record
write : std_ulogic;
waddr : std_logic_vector(DOFFSET_BITS-1 downto 0);
set : std_logic_vector(SETBITS-1 downto 0);
lru : lru_array;
end record;
subtype lock_type is std_logic_vector(0 to DSETS-1);
function lru_set (lru : lru_type; lock : lock_type) return std_logic_vector is
variable xlru : std_logic_vector(4 downto 0);
variable set : std_logic_vector(SETBITS-1 downto 0);
variable xset : std_logic_vector(1 downto 0);
variable unlocked : integer range 0 to DSETS-1;
begin
set := (others => '0'); xlru := (others => '0'); xset := (others => '0');
xlru(DLRUBITS-1 downto 0) := lru;
if dsetlock = 1 then
unlocked := DSETS-1;
for i in DSETS-1 downto 0 loop
if lock(i) = '0' then unlocked := i; end if;
end loop;
end if;
case DSETS is
when 2 =>
if dsetlock = 1 then
if lock(0) = '1' then xset(0) := '1'; else xset(0) := xlru(0); end if;
else
xset(0) := xlru(0);
end if;
when 3 =>
if dsetlock = 1 then
xset := conv_std_logic_vector(lru3_repl_table(conv_integer(xlru)) (unlocked), 2);
else
-- xset := conv_std_logic_vector(lru3_repl_table(conv_integer(xlru)) (0), 2);
xset := xlru(2) & (xlru(1) and not xlru(2));
end if;
when 4 =>
if dsetlock = 1 then
xset := conv_std_logic_vector(lru4_repl_table(conv_integer(xlru)) (unlocked), 2);
else
-- xset := conv_std_logic_vector(lru4_repl_table(conv_integer(xlru)) (0), 2);
xset := xlru(4 downto 3);
end if;
when others =>
end case;
set := xset(SETBITS-1 downto 0);
return(set);
end;
function lru_calc (lru : lru_type; xset : std_logic_vector) return lru_type is
variable new_lru : lru_type;
variable xnew_lru: std_logic_vector(4 downto 0);
variable xlru : std_logic_vector(4 downto 0);
variable vset: std_logic_vector(SETBITS-1 downto 0);
variable set: integer;
begin
vset := xset; set := conv_integer(vset);
new_lru := (others => '0'); xnew_lru := (others => '0');
xlru := (others => '0'); xlru(DLRUBITS-1 downto 0) := lru;
case DSETS is
when 2 =>
if set = 0 then xnew_lru(0) := '1'; else xnew_lru(0) := '0'; end if;
when 3 =>
xnew_lru(2 downto 0) := lru_3set_table(conv_integer(lru))(set);
when 4 =>
xnew_lru(4 downto 0) := lru_4set_table(conv_integer(lru))(set);
xnew_lru(SETBITS-1 downto 0) := vset;
when others =>
end case;
new_lru := xnew_lru(DLRUBITS-1 downto 0);
return(new_lru);
end;
subtype word is std_logic_vector(31 downto 0);
constant write_buffer_none : write_buffer_type := (
addr => (others => '0'),
data1 => (others => '0'),
data2 => (others => '0'),
size => (others => '0'),
asi => (others => '0'),
read => '0',
lock => '0',
smask => (others => '0')
);
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RRES : dcache_control_type := (
read => '0',
size => (others => '0'),
req => '0',
burst => '0',
rburst => '0',
holdn => '1',
nomds => '0',
stpend => '0',
xaddress => (others => '0'),
paddress => (others => '0'),
faddr => (others => '0'),
efaddr => (others => '0'),
dstate => idle,
hit => '0',
valid => '0',
flush => '0',
flush2 => '1',
mexc => '0',
bmexc => '0',
wb => write_buffer_none,
asi => (others => '0'),
icenable => '0',
rndcnt => (others => '0'),
setrepl => (others => '0'),
lrr => '0',
dsuset => (others => '0'),
lock => '0',
lramrd => '0',
ilramen => '0',
cctrl => cctrl_none,
cctrlwr => '0',
flushl2 => '0',
tadj => (others => '0'),
dadj => (others => '0'),
sadj => (others => '0'),
mmctrl1 => mmctrl_type1_none,
mmctrl1wr => '0',
pflush => '0',
pflushr => '0',
pflushaddr => (others => '0'),
pflushtyp => '0',
vaddr => (others => '0'),
ready => '0',
wbinit => '0',
cache => '0',
dlock => '0',
su => '0',
trans_op => '0',
flush_op => '0',
diag_op => '0',
reqst => '0',
set => 0,
noflush => '0'
);
constant SRES : snoop_reg_type := (
snoop => '0',
addr => (others => '0'),
mask => (others => '0'),
snhit => (others => '0')
);
constant LRES : lru_reg_type := (
write => '0',
waddr => (others => '0'),
set => (others => '0'),
lru => (others => (others => '0'))
);
signal r, c : dcache_control_type; -- r is registers, c is combinational
signal rs, cs : snoop_reg_type; -- rs is registers, cs is combinational
signal rl, cl : lru_reg_type; -- rl is registers, cl is combinational
constant ctbl : std_logic_vector(15 downto 0) := conv_std_logic_vector(cached, 16);
begin
dctrl : process(rst, r, rs, rl, dci, mcdo, ico, dcramo, ahbsi, fpuholdn, mmudco, ahbso)
variable dcramov : dcram_out_type;
variable rdatasel : rdatatype;
variable maddress : std_logic_vector(31 downto 0);
variable maddrlow : std_logic_vector(1 downto 0);
variable edata : std_logic_vector(31 downto 0);
variable size : std_logic_vector(1 downto 0);
variable read : std_ulogic;
variable twrite, tpwrite, tdiagwrite, ddiagwrite, dwrite : std_ulogic;
variable taddr : std_logic_vector(OFFSET_HIGH downto LINE_LOW); -- tag address
variable newtag : std_logic_vector(TAG_HIGH downto TAG_LOW); -- new tag
variable newptag : std_logic_vector(TAG_HIGH downto TAG_LOW); -- new tag
variable align_data : std_logic_vector(31 downto 0); -- aligned data
variable ddatainv, rdatav, align_datav : cdatatype;
variable rdata : std_logic_vector(31 downto 0);
variable vmask : valid_type; --std_logic_vector((dlinesize -1) downto 0);
variable enable, senable, scanen : std_logic_vector(0 to 3);
variable mds : std_ulogic;
variable mexc : std_ulogic;
variable hit, valid, forcemiss : std_ulogic;
variable flush : std_ulogic;
variable iflush : std_ulogic;
variable v : dcache_control_type;
variable eholdn : std_ulogic; -- external hold
variable snoopwe : std_ulogic;
variable hcache : std_ulogic;
variable lramcs, lramen, lramrd, lramwr, ilramen : std_ulogic;
variable snoopaddr : std_logic_vector(OFFSET_HIGH downto OFFSET_LOW);
variable flushaddr : std_logic_vector(OFFSET_HIGH downto OFFSET_LOW);
variable vs : snoop_reg_type;
variable dsudata : std_logic_vector(31 downto 0);
variable set, eset : integer range 0 to DSETS-1;
variable ddset : integer range 0 to MAXSETS-1;
variable snoopset : integer range 0 to DSETS-1;
variable validraw : std_logic_vector(0 to DSETS-1);
variable validv, hitv : std_logic_vector(0 to MAXSETS-1);
variable csnoopwe, snhit : std_logic_vector(0 to MAXSETS-1);
variable ctwrite, ctpwrite, cdwrite : std_logic_vector(0 to MAXSETS-1);
variable setrepl : std_logic_vector(log2x(DSETS)-1 downto 0);
variable lrusetval: std_logic_vector(SETBITS-1 downto 0);
variable wlrr : std_logic_vector(0 to 3);
variable vl : lru_reg_type;
variable diagset : std_logic_vector(TAG_LOW + SETBITS -1 downto TAG_LOW);
variable lock : std_logic_vector(0 to DSETS-1);
variable wlock : std_logic_vector(0 to MAXSETS-1);
variable laddr : std_logic_vector(31 downto 0); -- local ram addr
variable tag : cdatatype; --std_logic_vector(31 downto 0);
variable ptag : cdatatype; --std_logic_vector(31 downto 0);
variable rlramrd : std_ulogic;
variable cache : std_ulogic;
variable ctx : ctxdatatype;
variable flushl : std_ulogic;
variable miscdata : std_logic_vector(31 downto 0);
variable pflush : std_logic;
variable pflushaddr : std_logic_vector(VA_I_U downto VA_I_D);
variable pflushtyp : std_logic;
variable pftag : std_logic_vector(31 downto 2);
variable mmudci_fsread, tagclear : std_logic;
variable mmudci_trans_op : std_logic;
variable mmudci_flush_op : std_logic;
variable mmudci_wb_op : std_logic;
variable mmudci_diag_op : std_logic;
variable mmudci_su : std_logic;
variable mmudci_read : std_logic;
variable su : std_logic;
variable mmuisdis : std_logic;
variable mmudci_transdata_data : std_logic_vector(31 downto 0);
variable paddress : std_logic_vector(31 downto 0); -- physical address buffer
variable pagesize : integer range 0 to 3;
begin
-- init local variables
v := r; vs := rs; dcramov := dcramo; vl := rl;
vl.write := '0'; lramen := '0'; lramrd := '0'; lramwr := '0';
lramcs := '0'; laddr := (others => '0'); v.cctrlwr := '0';
ilramen := '0'; v.flush2 := r.flush;
snhit := (others => '0');
pagesize := MMU_getpagesize(mmupgsz,r.mmctrl1);
if ((dci.eenaddr or dci.enaddr) = '1') or (r.dstate /= idle) or
((dsu = 1) and (dci.dsuen = '1')) or (r.flush = '1') or
(is_fpga(memtech) = 1)
then
enable := (others => '1');
else enable := (others => '0'); end if;
v.mmctrl1wr := '0';
tagclear := '0'; mmuisdis := '0';
if (not M_EN) or ((r.asi(4 downto 0) = ASI_MMU_BP) or (r.mmctrl1.e = '0')) then
mmuisdis := '1';
end if;
if (mmuisdis = '1') then paddress := r.xaddress;
else paddress := r.paddress; end if;
mds := '1'; dwrite := '0'; twrite := '0'; tpwrite := '0';
ddiagwrite := '0'; tdiagwrite := '0'; v.holdn := '1'; mexc := '0';
flush := '0'; v.icenable := '0'; iflush := '0';
eholdn := ico.hold and fpuholdn; ddset := 0;
vs.snoop := '0'; snoopwe := '0';
snoopaddr := ahbsi.haddr(OFFSET_HIGH downto OFFSET_LOW);
flushaddr := r.xaddress(OFFSET_HIGH downto OFFSET_LOW);
hcache := '0';
validv := (others => '0'); hitv := (others => '0'); cache := '0';
if (dlram = 1) then rlramrd := r.lramrd; else rlramrd := '0'; end if;
miscdata := (others => '0'); pflush := '0';
pflushaddr := dci.maddress(VA_I_U downto VA_I_D); pflushtyp := PFLUSH_PAGE;
pftag := (others => '0');
ctx := (others => (others => '0'));
mmudci_fsread := '0';
ddatainv := (others => (others => '0')); tag := (others => (others => '0')); ptag := (others => (others => '0'));
v.flushl2 := dci.flushl and not r.flush;
newptag := (others => '0');
v.trans_op := r.trans_op and (not mmudco.grant);
v.flush_op := r.flush_op and (not mmudco.grant);
v.diag_op := r.diag_op and (not mmudco.grant);
mmudci_trans_op := r.trans_op;
mmudci_flush_op := r.flush_op;
mmudci_diag_op := r.diag_op;
mmudci_wb_op := '0';
mmudci_transdata_data := r.vaddr;
mmudci_su := '0'; mmudci_read := '0'; su := '0';
rdatasel := ddata; -- read data from cache as default
senable := (others => '0'); scanen := (others => mcdo.scanen);
set := 0; snoopset := 0; csnoopwe := (others => '0');
ctwrite := (others => '0'); ctpwrite := (others => '0'); cdwrite := (others => '0');
wlock := (others => '0');
for i in 0 to DSETS-1 loop wlock(i) := dcramov.tag(i)(CTAG_LOCKPOS); end loop;
wlrr := (others => '0');
for i in 0 to 3 loop wlrr(i) := dcramov.tag(i)(CTAG_LRRPOS); end loop;
if (DSETS > 1) then setrepl := r.setrepl; else setrepl := (others => '0'); end if;
-- random replacement counter
if DSETS > 1 then
if conv_integer(r.rndcnt) = (DSETS - 1) then v.rndcnt := (others => '0');
else v.rndcnt := r.rndcnt + 1; end if;
end if;
-- generate lock bits
lock := (others => '0');
if dsetlock = 1 then
for i in 0 to DSETS-1 loop lock(i) := dcramov.tag(i)(CTAG_LOCKPOS); end loop;
end if;
-- AHB snoop handling
if (DSNOOP2 /= 0) then
-- snoop on NONSEQ or SEQ and first word in cache line
-- do not snoop during own transfers or during cache flush
if (ahbsi.hready and ahbsi.hwrite and (not mcdo.bg or r.mmctrl1.e)) = '1' and
((ahbsi.htrans = HTRANS_NONSEQ) or
((ahbsi.htrans = HTRANS_SEQ) and
(ahbsi.haddr(LINE_HIGH downto LINE_LOW) = LINE_ZERO)))
then
vs.snoop := r.cctrl.dsnoop;
vs.addr := ahbsi.haddr(TAG_HIGH downto OFFSET_LOW);
if (r.mmctrl1.e = '1') and (mcdo.bg = '1') then vs.mask := r.wb.smask;
else vs.mask := (others => '1'); end if;
end if;
if DSNOOP /= 0 then
for i in 0 to DSETS-1 loop senable(i) := vs.snoop or rs.snoop; end loop;
end if;
for i in DSETS-1 downto 0 loop
if ((rs.snoop and not (r.flush or r.flush2)) = '1') then
if (DSNOOP2 /= 0) and (rs.mask(i) = '1') and
((dcramov.stag(i)(TAG_HIGH downto TAG_LOW) = rs.addr(TAG_HIGH downto TAG_LOW))
)
then
if DSNOOPSEP then flushaddr := rs.addr(OFFSET_HIGH downto OFFSET_LOW);
else snoopaddr := rs.addr(OFFSET_HIGH downto OFFSET_LOW); end if;
snoopwe := '1'; snoopset := i; snhit(i) := '1';
end if;
end if;
end loop;
end if;
vs.snhit := snhit; -- not needed, debug only
-- generate access parameters during pipeline stall
if ((r.holdn) = '0') or ((dsu = 1) and (dci.dsuen = '1')) then
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW);
elsif ((dci.enaddr and not dci.read) = '1') or (eholdn = '0')
then
taddr := dci.maddress(OFFSET_HIGH downto LINE_LOW);
else
taddr := dci.eaddress(OFFSET_HIGH downto LINE_LOW);
end if;
if (dci.write or not r.holdn) = '1' then
maddress := r.xaddress(31 downto 0);
read := r.read; size := r.size; edata := dci.maddress;
mmudci_su := r.su; mmudci_read := r.read and not r.dlock;
else
maddress := dci.maddress(31 downto 0);
read := dci.read; size := dci.size; edata := dci.edata;
mmudci_su := dci.msu; mmudci_read := dci.read and not dci.lock;
end if;
newtag := dci.maddress(TAG_HIGH downto TAG_LOW);
newptag := dci.maddress(TAG_HIGH downto TAG_LOW);
vl.waddr := maddress(OFFSET_HIGH downto OFFSET_LOW); -- lru write address
if (dsnoop = 6) and (r.cctrl.dsnoop = '0') then
snoopaddr := taddr(OFFSET_HIGH downto OFFSET_LOW);
senable := enable;
end if;
lrusetval := lru_set(rl.lru(conv_integer(maddress(OFFSET_HIGH downto OFFSET_LOW))), lock(0 to DSETS-1));
-- generate cache hit and valid bits
if (r.mmctrl1.e = '0') then hcache := ahb_slv_dec_cache(dci.maddress, ahbso, cached);
else hcache := '1'; end if;
forcemiss := (not dci.asi(3)) or dci.lock;
if (M_EN and (dci.asi(4 downto 0) = ASI_MMU_BP)) or (r.cctrl.dcs(0) = '0') or
((r.flush or r.flush2) = '1')
then hcache := '0'; end if;
hit := '0'; set := 0;
for i in DSETS-1 downto 0 loop
if (dcramov.tag(i)(TAG_HIGH downto TAG_LOW) = dci.maddress(TAG_HIGH downto TAG_LOW))
and ((dcramov.ctx(i) = r.mmctrl1.ctx) or (r.mmctrl1.e = '0'))
then hitv(i) := '1'; end if;
validv(i) := hcache and hitv(i) and (not r.flush) and (not r.flush2) and dcramov.tag(i)(dlinesize-1);
validraw(i) := dcramov.tag(i)(dlinesize-1);
end loop;
if drepl = dir then
hit := hitv(conv_integer(dci.maddress(OFFSET_HIGH+DIR_BITS downto OFFSET_HIGH+1))) and not r.flush and (not r.flush2);
valid := validv(conv_integer(dci.maddress(OFFSET_HIGH+DIR_BITS downto OFFSET_HIGH+1)));
else
hit := orv(hitv) and not r.flush and (not r.flush2);
valid := orv(validv);
end if;
-- force cache miss if mmu-enabled but off or BYPASS, or on flush
if ((M_EN) and (dci.asi(4 downto 0) = ASI_MMU_BP)) or (r.cctrl.dcs(0) = '0') or ((r.flush or r.flush2) = '1')
then hit := '0'; end if;
if DSETS > 1 then
if drepl = dir then
set := conv_integer(dci.maddress(OFFSET_HIGH+DIR_BITS downto OFFSET_HIGH+1));
else
for i in DSETS-1 downto 0 loop
if (hitv(i) = '1') then set := i; end if;
end loop;
end if;
if rlramrd = '1' then set := 1; end if;
else set := 0; end if;
if (dci.dsuen = '1') then diagset := r.xaddress(TAG_LOW+SETBITS-1 downto TAG_LOW);
else diagset := maddress(TAG_LOW + SETBITS - 1 downto TAG_LOW); end if;
case DSETS is
when 1 => ddset := 0;
when 3 => if conv_integer(diagset) < 3 then ddset := conv_integer(diagset); end if;
when others => ddset := conv_integer(diagset);
end case;
if ((r.holdn and dci.enaddr) = '1') and (r.dstate = idle) then
v.hit := hit; v.xaddress := dci.maddress;
v.read := dci.read; v.size := dci.size;
v.asi := dci.asi(4 downto 0);
v.su := dci.msu; v.set := set;
v.valid := valid; v.dlock := dci.lock;
end if;
-- Store buffer
if mcdo.ready = '1' then
v.wb.addr(LINE_HIGH downto 2) := r.wb.addr(LINE_HIGH downto 2) + 1;
if r.stpend = '1' then
v.stpend := r.req; v.wb.data1 := r.wb.data2;
v.wb.lock := r.wb.lock and r.req;
end if;
end if;
if mcdo.grant = '1' then v.req := r.burst; v.burst := '0'; end if;
if (mcdo.grant and not r.wb.read and r.req) = '1' then v.wb.lock := '0'; end if;
if (dlram = 1) then
if ((r.holdn) = '0') or ((dsu = 1) and (dci.dsuen = '1')) then
laddr := r.xaddress;
elsif ((dci.enaddr and not dci.read) = '1') or (eholdn = '0') then
laddr := dci.maddress;
else laddr := dci.eaddress; end if;
if (dci.enaddr = '1') and (dci.maddress(31 downto 24) = LOCAL_RAM_START)
then lramen := '1'; end if;
if ((laddr(31 downto 24) = LOCAL_RAM_START)) or ((dci.dsuen = '1') and (dci.asi(4 downto 1) = "0101"))
then lramcs := '1'; end if;
end if;
if (ilram = 1) then
if (dci.enaddr = '1') and (dci.maddress(31 downto 24) = ILRAM_START) then ilramen := '1'; end if;
end if;
-- cache freeze operation
if (r.cctrl.ifrz and dci.intack and r.cctrl.ics(0)) = '1' then
v.cctrl.ics := "01";
end if;
if (r.cctrl.dfrz and dci.intack and r.cctrl.dcs(0)) = '1' then
v.cctrl.dcs := "01";
end if;
if (r.cctrlwr and not dci.nullify) = '1' then
if (r.xaddress(7 downto 2) = "000000") and (dci.read = '0') then
v.noflush := dci.maddress(30);
v.cctrl.dsnoop := dci.maddress(23);
flush := dci.maddress(22);
iflush := dci.maddress(21);
v.cctrl.burst:= dci.maddress(16);
v.cctrl.dfrz := dci.maddress(5);
v.cctrl.ifrz := dci.maddress(4);
v.cctrl.dcs := dci.maddress(3 downto 2);
v.cctrl.ics := dci.maddress(1 downto 0);
end if;
if (memtech = rhlib18t) and (r.xaddress(7 downto 2) = "000001") and (dci.read = '0') then
v.tadj := dci.maddress(5 downto 4);
v.sadj := dci.maddress(3 downto 2);
v.dadj := dci.maddress(1 downto 0);
end if;
end if;
-- main Dcache state machine
case r.dstate is
when idle => -- Idle state
if (M_TLB_FASTWRITE /= 0) then
mmudci_transdata_data := dci.maddress;
end if;
v.nomds := r.nomds and not eholdn; v.bmexc := '0';
if ((r.reqst = '0') and (r.stpend = '0')) or ((mcdo.ready and not r.req)= '1') then -- wait for store queue
v.wb.addr := dci.maddress; v.wb.size := dci.size;
v.wb.read := dci.read; v.wb.data1 := dci.edata; v.wb.lock := dci.lock and not dci.nullify and ico.hold;
v.wb.asi := dci.asi(3 downto 0);
if ((M_EN) and (dci.asi(4 downto 0) /= ASI_MMU_BP) and (r.mmctrl1.e = '1') and
((M_TLB_FASTWRITE /= 0) or ((dci.enaddr and eholdn and dci.lock and not dci.read) = '1')))
then
if (dci.enaddr and eholdn and dci.lock and not dci.read) = '1' then -- skip address translation on store in LDST
v.wb.addr := r.wb.addr(31 downto 8) & dci.maddress(7 downto 0);
newptag := r.wb.addr(TAG_HIGH downto TAG_LOW);
else
v.wb.addr := mmudco.wbtransdata.data;
newptag := mmudco.wbtransdata.data(TAG_HIGH downto TAG_LOW);
end if;
end if;
if (dci.read and hcache and andv(r.cctrl.dcs)) = '1' then v.wb.addr(LINE_HIGH downto 0) := (others => '0'); end if;
end if;
if (eholdn and (not r.nomds)) = '1' then -- avoid false path through nullify
case dci.asi(4 downto 0) is
when ASI_SYSR => rdatasel := sysr;
when ASI_DTAG => rdatasel := dtag;
when ASI_DDATA => rdatasel := dddata;
when ASI_DCTX => if M_EN then rdatasel := dctx; end if;
when ASI_MMUREGS => if M_EN then rdatasel := misc; end if;
when ASI_MMUSNOOP_DTAG => rdatasel := mmusnoop_dtag;
when others =>
end case;
end if;
if (dci.enaddr and eholdn and (not r.nomds) and not dci.nullify) = '1' then
case dci.asi(4 downto 0) is
when ASI_SYSR => -- system registers
v.cctrlwr := not dci.read and not (dci.dsuen and not dci.eenaddr);
when ASI_MMUREGS =>
if M_EN then
if (dsu = 0) or dci.dsuen = '0' then
-- clean fault valid bit
if dci.read = '1' then
case dci.maddress(CNR_U downto CNR_D) is
when CNR_F =>
mmudci_fsread := '1';
when others => null;
end case;
end if;
end if;
v.mmctrl1wr := not dci.read and not (r.mmctrl1wr and dci.dsuen);
end if;
when ASI_ITAG | ASI_IDATA | ASI_ICTX => -- Read/write Icache tags
-- CTX write has to be done through ctxnr & ASI_ITAG
if (ico.flush = '1') or (dci.asi(4) = '1') then mexc := '1';
else v.dstate := asi_idtag; v.holdn := dci.dsuen; end if;
when ASI_UINST | ASI_SINST =>
if (ilram = 1) then v.dstate := asi_idtag; v.ilramen := '1'; end if;
when ASI_DFLUSH => -- flush data cache
if dci.read = '0' then flush := '1'; end if;
when ASI_DDATA => -- Read/write Dcache data
if DSNOOPSEP then flushaddr := taddr(OFFSET_HIGH downto OFFSET_LOW); end if;
if (r.flush = '1') then -- No access on flush
mexc := '1';
elsif (dci.read = '0') then
dwrite := '1'; ddiagwrite := '1';
end if;
when ASI_DTAG => -- Read/write Dcache tags
if DSNOOPSEP then flushaddr := taddr(OFFSET_HIGH downto OFFSET_LOW); end if;
if (dci.size /= "10") or (r.flush = '1') then -- allow only word access
mexc := '1';
elsif (dci.read = '0') then
twrite := '1'; tdiagwrite := '1';
end if;
when ASI_MMUSNOOP_DTAG => -- Read/write MMU physical snoop tags
if DSNOOPSEP then
snoopaddr := taddr(OFFSET_HIGH downto OFFSET_LOW);
if (dci.size /= "10") or (r.flush = '1') then -- allow only word access
mexc := '1';
elsif (dci.read = '0') then
tpwrite := '1'; tdiagwrite := '1';
end if;
end if;
when ASI_DCTX =>
-- write has to be done through ctxnr & ASI_DTAG
if DSNOOPSEP then flushaddr := taddr(OFFSET_HIGH downto OFFSET_LOW); end if;
if (dci.size /= "10") or (r.flush = '1') or (dci.read = '0') then -- allow only word access
mexc := '1';
end if;
when ASI_FLUSH_PAGE => -- i/dcache flush page
if dci.read = '0' then iflush := '1'; end if;
if M_EN then
if dci.read = '0' then
flush := '1'; --pflush := '1'; pflushtyp := PFLUSH_PAGE;
end if;
end if;
when ASI_FLUSH_CTX => -- i/dcache flush ctx
if M_EN then
if dci.read = '0' then
flush := '1'; iflush := '1'; --pflush := '1'; pflushtyp := PFLUSH_CTX;
end if;
end if;
when ASI_MMUFLUSHPROBE =>
if M_EN then
if dci.read = '0' then -- flush
mmudci_flush_op := '1';
v.flush_op := not mmudco.grant;
v.dstate := wflush;
v.vaddr := dci.maddress; v.holdn := '0'; flush := '1'; iflush := '1';
end if;
end if;
when ASI_MMU_DIAG =>
if dci.read = '0' then -- diag access
mmudci_diag_op := '1';
v.diag_op := not mmudco.grant;
v.vaddr := dci.maddress;
end if;
when others =>
if dci.read = '1' then -- read access
v.rburst := hcache and (andv(r.cctrl.dcs) or andv(dci.size)); -- and not forcemiss;
if (dlram = 1) and (lramen = '1') then
lramrd := '1';
elsif (ilram = 1) and (ilramen = '1') then
if (ico.flush = '1') or (dci.size /= "10") then mexc := '1';
else v.dstate := asi_idtag; v.holdn := dci.dsuen; v.ilramen := '1'; end if;
elsif dci.dsuen = '0' then
if not ((hit and valid and not forcemiss) = '1') then -- read miss
v.holdn := '0'; v.dstate := wread; v.ready := '0';
v.cache := hcache and andv(r.cctrl.dcs);
if (not M_EN) or ((dci.asi(4 downto 0) = ASI_MMU_BP) or (r.mmctrl1.e = '0')) then
-- cache disabled if mmu-enabled but off or BYPASS
if ((r.stpend = '0') or ((mcdo.ready and not r.req) = '1')) then
v.req := '1'; v.burst := v.rburst;
end if;
else
-- ## mmu case >
if (r.stpend = '0') or ((mcdo.ready and not r.req)= '1') then
v.wbinit := '1'; -- wb init in idle
v.burst := v.rburst;
else
v.wbinit := '0';
end if;
mmudci_trans_op := '1'; -- start translation
v.trans_op := not mmudco.grant;
v.vaddr := dci.maddress;
v.dstate := rtrans;
-- ## < mmu case
end if;
else -- read hit
if (DSETS > 1) and (drepl = lru) then vl.write := '1'; end if;
cache := '1';
end if;
end if;
else -- write access
if (dlram = 1) and (lramen = '1') then
lramwr := '1';
if (dci.size = "11") then -- double store
v.dstate := dblwrite; v.xaddress(2) := '1';
end if;
elsif (ilram = 1) and (ilramen = '1') then
if (ico.flush = '1') or (dci.size /= "10") then mexc := '1';
else v.dstate := asi_idtag; v.holdn := dci.dsuen; v.ilramen := '1'; end if;
elsif dci.dsuen = '0' then
v.ready := '0';
if (not M_EN) or
((dci.asi(4 downto 0) = ASI_MMU_BP) or (r.mmctrl1.e = '0')) then
if ((r.stpend = '0') or ((mcdo.ready and not r.req)= '1'))
then -- wait for store queue
v.reqst := '1';
v.burst := dci.size(1) and dci.size(0);
if (dci.size = "11") then v.dstate := dblwrite; end if; -- double store
v.wb.smask := (others => '1');
else -- wait for store queue
v.dstate := wwrite; v.holdn := '0'; v.wb.read := r.wb.read;
end if;
else
-- ## mmu case > false and
if ((r.stpend = '0') or ((mcdo.ready and not r.req)= '1')) and
(((mmudco.wbtransdata.accexc = '0') and (M_TLB_FASTWRITE /= 0)) or (dci.lock = '1'))
then
v.reqst := '1';
v.burst := dci.size(1) and dci.size(0);
if (dci.size = "11") then v.dstate := dblwrite; end if; -- double store
v.wb.smask := (others => '1');
if hit = '1' then v.wb.smask(set) := '0'; end if;
else
if (r.stpend = '0') or ((mcdo.ready and not r.req)= '1')
then
v.wbinit := '1'; -- wb init in idle
v.burst := dci.size(1) and dci.size(0);
v.wb.smask := (others => '1');
if hit = '1' then v.wb.smask(set) := '0'; end if;
else
v.wbinit := '0';
end if;
mmudci_trans_op := '1'; -- start translation
v.trans_op := not mmudco.grant;
v.vaddr := dci.maddress; v.holdn := '0';
v.dstate := wtrans;
-- ## < mmu case
end if;
end if;
if (hit and valid) = '1' then -- write hit
dwrite := '1';
if (DSETS > 1) and (drepl = lru) then vl.write := '1'; end if;
setrepl := conv_std_logic_vector(set, SETBITS);
if DSNOOP2 /= 0 then
if ((dci.enaddr and not dci.read) = '1') or (eholdn = '0')
then v.xaddress := dci.maddress; else v.xaddress := dci.eaddress; end if;
end if;
end if;
if (dci.size = "11") then v.xaddress(2) := '1'; end if;
end if;
end if;
eset := set;
if (DSETS > 1) then
vl.set := conv_std_logic_vector(set, SETBITS);
v.setrepl := conv_std_logic_vector(set, SETBITS);
if (andv(validraw) = '0') and (drepl /= dir) and false then
for i in DSETS-1 downto 0 loop
if validraw(i) = '0' then eset := i; end if;
end loop;
v.setrepl := conv_std_logic_vector(eset, SETBITS);
elsif ((not hit) and (not r.flush)) = '1' then
case drepl is
when rnd =>
if dsetlock = 1 then
if lock(conv_integer(r.rndcnt)) = '0' then v.setrepl := r.rndcnt;
else
v.setrepl := conv_std_logic_vector(DSETS-1, SETBITS);
for i in DSETS-1 downto 0 loop
if (lock(i) = '0') and (i>conv_integer(r.rndcnt)) then
v.setrepl := conv_std_logic_vector(i, SETBITS);
end if;
end loop;
end if;
else
v.setrepl := r.rndcnt;
end if;
when dir =>
v.setrepl := dci.maddress(OFFSET_HIGH+log2x(DSETS) downto OFFSET_HIGH+1);
when lru =>
v.setrepl := lrusetval;
when lrr =>
v.setrepl := (others => '0');
if dsetlock = 1 then
if lock(0) = '1' then v.setrepl(0) := '1';
else
v.setrepl(0) := dcramov.tag(0)(CTAG_LRRPOS) xor dcramov.tag(1)(CTAG_LRRPOS);
end if;
else
v.setrepl(0) := dcramov.tag(0)(CTAG_LRRPOS) xor dcramov.tag(1)(CTAG_LRRPOS);
end if;
if v.setrepl(0) = '0' then
v.lrr := not dcramov.tag(0)(CTAG_LRRPOS);
else
v.lrr := dcramov.tag(0)(CTAG_LRRPOS);
end if;
end case;
end if;
if (dsetlock = 1) then
if (hit and lock(set)) = '1' then v.lock := '1';
else v.lock := '0'; end if;
end if;
end if;
end case;
end if;
when rtrans =>
if M_EN then
if r.stpend = '1' then
if ((mcdo.ready and not r.req) = '1') then
v.ready := '1'; -- buffer store finish
end if;
end if;
v.holdn := '0';
if mmudco.transdata.finish = '1' then
-- translation error, i.e. page fault
if (mmudco.transdata.accexc) = '1' then
v.holdn := '1'; v.dstate := idle;
mds := '0'; mexc := not r.mmctrl1.nf;
else
v.dstate := wread;
v.cache := r.cache and mmudco.transdata.cache;
v.paddress := mmudco.transdata.data;
v.rburst := r.rburst and v.cache;
if r.wbinit = '1' then
v.wb.addr := v.paddress; --mmudco.transdata.data;
v.req := '1';
v.burst := v.rburst;
if v.rburst = '1' then
v.wb.addr(LINE_HIGH downto 0) := (others => '0');
end if;
end if;
end if;
end if;
end if;
when wread => -- read miss, wait for memory data
if drepl=lru and mcdo.ready='0' and r.hit='0' then
v.setrepl := lrusetval;
end if;
taddr := r.wb.addr(OFFSET_HIGH downto LINE_LOW);
newtag := r.xaddress(TAG_HIGH downto TAG_LOW);
newptag := paddress(TAG_HIGH downto TAG_LOW);
v.nomds := r.nomds and not eholdn;
v.holdn := v.nomds; rdatasel := memory;
for i in 0 to DSETS-1 loop wlock(i) := r.lock; end loop;
for i in 0 to 3 loop wlrr(i) := r.lrr; end loop;
if (r.stpend = '0') and (r.ready = '0') then
if (r.rburst) = '1' then
if (mcdo.grant = '1') and ((r.cctrl.dcs = "01") or
((r.wb.addr(LINE_HIGH downto LINE_LOW) >= bend(LINE_HIGH downto LINE_LOW)) and not
((r.wb.addr(LINE_HIGH downto LINE_LOW) = bend(LINE_HIGH downto LINE_LOW)) and (mcdo.ready = '0')))) then
v.burst := '0';
else v.burst := r.burst; end if;
end if;
if mcdo.ready = '1' then
if (r.cache or r.hit) = '0' then
mds := r.holdn or r.nomds; v.xaddress(2) := '1'; v.holdn := '1';
else
if r.wb.addr(LINE_HIGH downto LINE_LOW) = r.xaddress(LINE_HIGH downto LINE_LOW) then
mds := '0';
end if;
end if;
dwrite := r.cache; rdatasel := memory;
mexc := mcdo.mexc;
v.bmexc := r.bmexc or mcdo.mexc or dci.flushl;
if r.req = '0' then
twrite := r.cache; tagclear := v.bmexc;
if (((dci.enaddr and not mds) = '1') or (dci.flushl = '1') or ((dci.enaddr and twrite) = '1'))
and ((r.cctrl.dcs(0) = '1') or (dlram = 1))
then v.dstate := loadpend; v.holdn := '0';
else v.dstate := idle; v.holdn := '1'; end if;
else v.nomds := not r.cache; end if;
tpwrite := twrite;
end if;
v.mexc := mcdo.mexc and not r.rburst; v.wb.data2 := mcdo.data;
else
if (r.ready or (mcdo.ready and not r.req)) = '1' then -- wait for store queue
v.wb.addr := paddress;
v.wb.size := r.size;
v.burst := r.rburst;
if r.rburst = '1' then
v.wb.addr(LINE_HIGH downto 0) := (others => '0');
end if;
v.wb.read := r.read; v.wb.data1 := dci.maddress; v.req := '1';
v.wb.lock := dci.lock; v.wb.asi := r.asi(3 downto 0); v.ready := '0';
end if;
end if;
when loadpend => -- return from read miss with load pending
taddr := dci.maddress(OFFSET_HIGH downto LINE_LOW);
if (dlram = 1) then
laddr := dci.maddress;
if laddr(31 downto 24) = LOCAL_RAM_START then lramcs := '1'; end if;
end if;
if (r.flushl2 and dci.enaddr) = '1' then
v.holdn := '0';
else
v.dstate := idle;
end if;
when dblwrite => -- second part of double store cycle
edata := dci.edata; -- needed for STD store hit
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW);
if (dlram = 1) and (rlramrd = '1') then
laddr := r.xaddress; lramwr := '1';
else
if r.hit = '1' then dwrite := r.valid; end if;
v.wb.data2 := dci.edata;
end if;
if (dci.flushl and ico.hold) = '1' then
v.dstate := loadpend; v.holdn := '0';
elsif ico.hold = '0' then v.reqst := '0';
else v.dstate := idle; end if;
when asi_idtag => -- icache diag and inst local ram access
rdatasel := icache; v.icenable := '1'; v.holdn := dci.dsuen;
if ico.diagrdy = '1' then
v.dstate := loadpend; v.icenable := '0'; v.ilramen := '0';
if (dsu = 0) or ((dsu = 1) and (dci.dsuen = '0')) then
mds := not r.read;
end if;
end if;
when wtrans =>
edata := dci.edata; -- needed for STD store hit
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW);
newtag := r.xaddress(TAG_HIGH downto TAG_LOW);
if M_EN then
if r.stpend = '1' then
if ((mcdo.ready and not r.req) = '1') then
v.ready := '1'; -- buffer store finish
end if;
end if;
v.holdn := '0';
if mmudco.transdata.finish = '1' then
if (mmudco.transdata.accexc) = '1' then
v.holdn := '1'; v.dstate := idle;
mds := '0'; mexc := not r.mmctrl1.nf;
tagclear := r.hit;
twrite := tagclear;
if (twrite = '1') and (((dci.enaddr and not mds) = '1') or
((dci.eenaddr and mds and eholdn) = '1')) and (r.cctrl.dcs(0) = '1') then
v.dstate := loadpend; v.holdn := '0';
end if;
else
v.dstate := wwrite;
v.cache := mmudco.transdata.cache;
v.paddress := mmudco.transdata.data;
if (r.wbinit) = '1' then
v.wb.data2 := dci.edata;
v.wb.addr := mmudco.transdata.data;
v.dstate := idle; v.holdn := '1';
if (dci.nullify = '0')
then
v.req := '1'; v.stpend := '1';
else v.reqst := '1'; end if;
v.burst := r.size(1) and r.size(0) and not v.wb.addr(2);
if (r.hit = '1') and (r.size = "11") then -- write hit
dwrite := r.valid;
end if;
end if;
end if;
end if;
end if;
when wwrite => -- wait for store buffer to empty (store access)
edata := dci.edata; -- needed for STD store hit
if (
(dci.lock = '1')) and (dci.nullify = '1') then
v.dstate := idle; v.wb.lock := '0';
elsif ((v.ready or (mcdo.ready and not r.req)) = '1') or (
(dci.lock = '1')) then -- store queue emptied
if (r.hit = '1') and (r.size = "11") then -- write hit
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW); dwrite := r.valid;
end if;
v.dstate := idle;
v.burst := r.size(1) and r.size(0);
if (dci.nullify = '0') then v.reqst := '1'; end if;
v.wb.addr := paddress;
v.wb.size := r.size;
v.wb.read := r.read; v.wb.data1 := dci.maddress;
v.wb.lock := dci.lock; v.wb.data2 := dci.edata;
v.wb.asi := r.asi(3 downto 0);
if r.size = "11" then v.wb.addr(2) := '0'; end if;
v.wb.smask := (others => '1');
if r.hit = '1' then v.wb.smask(r.set) := '0'; end if;
else -- hold cpu until buffer empty
v.holdn := '0';
end if;
when wflush =>
v.holdn := '0';
if mmudco.transdata.finish = '1' then
v.dstate := idle; v.holdn := '1';
end if;
when others => v.dstate := idle;
end case;
v.req := v.req or v.reqst; v.stpend := v.stpend or v.reqst; v.reqst := '0';
if (dlram = 1) then v.lramrd := lramcs; end if; -- read local ram data
-- select data to return on read access
-- align if byte/half word read from cache or memory.
if (dsu = 1) and (dci.dsuen = '1') then
v.dsuset := conv_std_logic_vector(ddset, SETBITS);
case dci.asi(4 downto 0) is
when ASI_ITAG | ASI_IDATA =>
v.icenable := not ico.diagrdy;
rdatasel := icache;
when ASI_DTAG =>
tdiagwrite := not dci.eenaddr and dci.enaddr and dci.write;
twrite := not dci.eenaddr and dci.enaddr and dci.write;
rdatasel := dtag;
when ASI_MMUSNOOP_DTAG =>
if DSNOOPSEP then snoopaddr := taddr(OFFSET_HIGH downto OFFSET_LOW); end if;
tdiagwrite := not dci.eenaddr and dci.enaddr and dci.write;
tpwrite := not dci.eenaddr and dci.enaddr and dci.write;
rdatasel := mmusnoop_dtag; senable := (others => '1');
when ASI_DDATA =>
if M_EN then
ddiagwrite := not dci.eenaddr and dci.enaddr and dci.write;
dwrite := not dci.eenaddr and dci.enaddr and dci.write;
rdatasel := dddata;
end if;
when ASI_UDATA | ASI_SDATA =>
lramwr := not dci.eenaddr and dci.enaddr and dci.write;
when ASI_MMUREGS =>
rdatasel := misc;
when others =>
end case;
end if;
-- read
if M_EN then
case dci.maddress(CNR_U downto CNR_D) is
when CNR_CTRL =>
miscdata(MMCTRL_E) := r.mmctrl1.e;
miscdata(MMCTRL_NF) := r.mmctrl1.nf;
miscdata(MMCTRL_PSO) := r.mmctrl1.pso;
miscdata(MMCTRL_VER_U downto MMCTRL_VER_D) := "0001";
miscdata(MMCTRL_IMPL_U downto MMCTRL_IMPL_D) := "0000";
miscdata(23 downto 21) := conv_std_logic_vector(M_ENT_ILOG,3);
miscdata(20 downto 18) := conv_std_logic_vector(M_ENT_DLOG,3);
if M_TLB_TYPE = 0 then miscdata(MMCTRL_TLBSEP) := '1'; else
miscdata(23 downto 21) := conv_std_logic_vector(M_ENT_CLOG,3);
miscdata(20 downto 18) := (others => '0');
end if;
miscdata(MMCTRL_TLBDIS) := r.mmctrl1.tlbdis;
miscdata(MMCTRL_PGSZ_U downto MMCTRL_PGSZ_D) := conv_std_logic_vector(pagesize,2); -- r.mmctrl1.pagesize;
--custom
when CNR_CTXP =>
miscdata(MMCTXP_U downto MMCTXP_D) := r.mmctrl1.ctxp;
when CNR_CTX =>
miscdata(MMCTXNR_U downto MMCTXNR_D) := r.mmctrl1.ctx;
when CNR_F =>
miscdata(FS_OW) := mmudco.mmctrl2.fs.ow;
miscdata(FS_FAV) := mmudco.mmctrl2.fs.fav;
miscdata(FS_FT_U downto FS_FT_D) := mmudco.mmctrl2.fs.ft;
miscdata(FS_AT_LS) := mmudco.mmctrl2.fs.at_ls;
miscdata(FS_AT_ID) := mmudco.mmctrl2.fs.at_id;
miscdata(FS_AT_SU) := mmudco.mmctrl2.fs.at_su;
miscdata(FS_L_U downto FS_L_D) := mmudco.mmctrl2.fs.l;
miscdata(FS_EBE_U downto FS_EBE_D) := mmudco.mmctrl2.fs.ebe;
when CNR_FADDR =>
miscdata(VA_I_U downto VA_I_D) := mmudco.mmctrl2.fa;
when others => null;
end case;
end if;
rdata := (others => '0'); rdatav := (others => (others => '0'));
align_data := (others => '0'); align_datav := (others => (others => '0'));
maddrlow := maddress(1 downto 0); -- stupid Synopsys VSS bug ...
case rdatasel is
when misc =>
if M_EN then set := 0; rdatav(0) := miscdata; end if;
when dddata =>
rdatav := dcramov.data;
if dci.dsuen = '1' then set := conv_integer(r.dsuset);
else set := ddset; end if;
when dtag =>
rdatav := dcramov.tag;
if dci.dsuen = '1' then set := conv_integer(r.dsuset);
else set := ddset; end if;
when mmusnoop_dtag =>
rdatav := dcramov.stag;
if dci.dsuen = '1' then set := conv_integer(r.dsuset);
else set := ddset; end if;
when dctx =>
--rdata(M_CTX_SZ-1 downto 0) := dcramov.dtramout(ddset).ctx;
when icache =>
rdatav(0) := ico.diagdata; set := 0;
when ddata | memory =>
if rdatasel = memory then
rdatav(0) := mcdo.data; set := 0;
else
for i in 0 to DSETS-1 loop rdatav(i) := dcramov.data(i); end loop;
end if;
when sysr =>
set := 0;
case dci.maddress(3 downto 2) is
when "00" =>
rdatav(0)(30) := r.noflush;
rdatav(0)(23) := r.cctrl.dsnoop;
if dsnoop > 4 then rdatav(0)(17) := '1'; end if;
rdatav(0)(16 downto 14) := r.cctrl.burst & ico.flush & r.flush;
rdatav(0)(5 downto 0) :=
r.cctrl.dfrz & r.cctrl.ifrz & r.cctrl.dcs & r.cctrl.ics;
when "01" =>
rdatav(0)(7 downto 0) := "00" & r.tadj & r.sadj & r.dadj;
when "10" =>
rdatav(0) := ico.cfg;
when others =>
rdatav(0) := cache_cfg(drepl, dsets, dlinesize, dsetsize, dsetlock,
dsnoop, dlram, dlramsize, dlramstart, mmuen);
end case;
end case;
-- select which data to update the data cache with
for i in 0 to DSETS-1 loop
case size is -- merge data during partial write
when "00" =>
case maddrlow is
when "00" =>
ddatainv(i) := edata(7 downto 0) & dcramov.data(i)(23 downto 0);
when "01" =>
ddatainv(i) := dcramov.data(i)(31 downto 24) & edata(7 downto 0) &
dcramov.data(i)(15 downto 0);
when "10" =>
ddatainv(i) := dcramov.data(i)(31 downto 16) & edata(7 downto 0) &
dcramov.data(i)(7 downto 0);
when others =>
ddatainv(i) := dcramov.data(i)(31 downto 8) & edata(7 downto 0);
end case;
when "01" =>
if maddress(1) = '0' then
ddatainv(i) := edata(15 downto 0) & dcramov.data(i)(15 downto 0);
else
ddatainv(i) := dcramov.data(i)(31 downto 16) & edata(15 downto 0);
end if;
when others =>
ddatainv(i) := edata;
end case;
end loop;
-- handle double load with pipeline hold
if (r.dstate = idle) and (r.nomds = '1') then
rdatav(0) := r.wb.data2; mexc := r.mexc; set := 0;
end if;
-- Handle AHB retry. Re-generate bus request and burst
if mcdo.retry = '1' then
v.req := '1';
if r.wb.read = '0' then
v.burst := r.wb.size(0) and r.wb.size(1) and not r.wb.addr(2);
else
v.burst := ((r.rburst) and not andv(r.wb.addr(LINE_HIGH downto LINE_LOW))) or
(not r.rburst and r.wb.size(0) and r.wb.size(1) and not r.wb.addr(2));
end if;
end if;
-- Generate new valid bits
if r.flush = '1' then twrite := '0'; dwrite := '0'; end if;
vmask := (others => (others => '1'));
if twrite = '1' then
if tagclear = '1' then vmask := (others => (others => '0')); end if;
if (DSETS>1) and (drepl = lru) and (tdiagwrite = '0') then
vl.write := '1'; vl.set := setrepl;
end if;
end if;
if (DSETS>1) and (drepl = lru) and (rl.write = '1') then
vl.lru(conv_integer(rl.waddr)) :=
lru_calc(rl.lru(conv_integer(rl.waddr)), rl.set);
end if;
if tdiagwrite = '1' then -- diagnostic tag write
if (dsu = 1) and (dci.dsuen = '1') then
vmask := (others => dci.maddress(dlinesize - 1 downto 0));
else
vmask := (others => dci.edata(dlinesize - 1 downto 0));
newtag(TAG_HIGH downto TAG_LOW) := dci.edata(TAG_HIGH downto TAG_LOW);
newptag(TAG_HIGH downto TAG_LOW) := dci.edata(TAG_HIGH downto TAG_LOW);
for i in 0 to 3 loop wlrr(i) := dci.edata(CTAG_LRRPOS); end loop;
for i in 0 to DSETS-1 loop wlock(i) := dci.edata(CTAG_LOCKPOS); end loop;
end if;
end if;
-- mmureg write
if r.mmctrl1wr = '1' then
case r.xaddress(CNR_U downto CNR_D) is
when CNR_CTRL =>
v.mmctrl1.e := dci.maddress(MMCTRL_E);
v.mmctrl1.nf := dci.maddress(MMCTRL_NF);
v.mmctrl1.pso := dci.maddress(MMCTRL_PSO);
v.mmctrl1.tlbdis := dci.maddress(MMCTRL_TLBDIS);
v.mmctrl1.pagesize := dci.maddress(MMCTRL_PGSZ_U downto MMCTRL_PGSZ_D);
--custom
-- Note: before tlb disable tlb flush is required !!!
when CNR_CTXP =>
v.mmctrl1.ctxp := dci.maddress(MMCTXP_U downto MMCTXP_D);
when CNR_CTX =>
v.mmctrl1.ctx := dci.maddress(MMCTXNR_U downto MMCTXNR_D);
when CNR_F => null;
when CNR_FADDR => null;
when others => null;
end case;
end if;
-- cache flush
if ((dci.flush or dci.flushl or flush) = '1') and (dcen /= 0) then
v.flush := not r.noflush; v.faddr := (others => '0');
if (dci.flushl = '1') then v.flush := '1'; v.faddr := r.efaddr; end if;
end if;
if eholdn = '1' then v.efaddr := v.xaddress(OFFSET_HIGH downto OFFSET_LOW); end if;
if (r.flush = '1') and (dcen /= 0) then
twrite := '1'; vmask := (others => (others => '0'));
v.faddr := r.faddr +1; newtag(TAG_HIGH downto TAG_LOW) := (others => '0');
newptag := (others => '0');
if DSNOOPSEP then flushaddr := r.faddr; end if;
taddr(OFFSET_HIGH downto OFFSET_LOW) := r.faddr;
wlrr := (others => '0');
if ((r.faddr(DOFFSET_BITS -1) and not v.faddr(DOFFSET_BITS -1)) or r.flushl2) = '1' then
v.flush := '0';
end if;
end if;
-- update cache with memory data during read miss
if read = '1' then
for i in 0 to DSETS-1 loop
ddatainv(i) := mcdo.data;
end loop;
end if;
-- cache write signals
if twrite = '1' then
if tdiagwrite = '1' then ctwrite(ddset) := '1';
else ctwrite(conv_integer(setrepl)) := '1'; end if;
end if;
if DSNOOPSEP then
if tpwrite = '1' then
if tdiagwrite = '1' then ctpwrite(ddset) := '1';
else ctpwrite(conv_integer(setrepl)) := '1'; end if;
end if;
end if;
if dwrite = '1' then
if ddiagwrite = '1' then cdwrite(ddset) := '1';
else cdwrite(conv_integer(setrepl)) := '1'; end if;
end if;
if (r.flush and twrite) = '1' then -- flush
ctwrite := (others => '1'); wlrr := (others => '0'); wlock := (others => '0');
if DSNOOPSEP then
ctpwrite := (others => '1');
end if;
end if;
csnoopwe := (others => '0'); flushl := '0';
if ((snoopwe and not mcdo.scanen) = '1') then csnoopwe := snhit; end if;
if DSNOOPSEP then
csnoopwe := csnoopwe or ctwrite;
if orv(snhit) = '1' then flushl := '1'; end if; -- flush tag on snoop hit
end if;
if r.flush2 = '1' then
vl.lru := (others => (others => '0'));
end if;
-- reset
if (not RESET_ALL) and (rst = '0') then
v.dstate := idle; v.stpend := '0'; v.req := '0'; v.burst := '0';
v.read := '0'; v.flush := '0'; v.nomds := '0'; v.holdn := '1';
v.rndcnt := (others => '0'); v.setrepl := (others => '0');
v.dsuset := (others => '0'); v.flush2 := '1';
v.lrr := '0'; v.lock := '0'; v.ilramen := '0';
v.cctrl.dcs := "00"; v.cctrl.ics := "00";
v.cctrl.burst := '0'; v.cctrl.dsnoop := '0';
v.tadj := (others => '0'); v.dadj := (others => '0');
v.sadj := (others => '0');
--if M_EN then
v.mmctrl1.e := '0'; v.mmctrl1.nf := '0'; v.mmctrl1.ctx := (others => '0');
v.mmctrl1.tlbdis := '0';
v.mmctrl1.pso := '0';
v.trans_op := '0';
v.flush_op := '0';
v.diag_op := '0';
v.pflush := '0';
v.pflushr := '0';
v.mmctrl1.pagesize := (others => '0');
--end if;
v.mmctrl1.bar := (others => '0');
v.faddr := (others => '0');
v.reqst := '0';
v.cache := '0'; v.wb.lock := '0';
v.wb.data1 := (others => '0'); v.wb.data2 := (others => '0');
v.noflush := '0'; v.mexc := '0';
end if;
if dsnoop = 0 then v.cctrl.dsnoop := '0'; end if;
if not M_EN then v.mmctrl1 := mmctrl_type1_none; end if; -- kill MMU regs if not enabled
-- Drive signals
c <= v; cs <= vs; -- register inputs
cl <= vl;
-- tag ram inputs
senable := senable and not scanen; enable := enable and not scanen;
if mcdo.scanen = '1' then ctpwrite := (others => '0'); end if;
for i in 0 to DSETS-1 loop
tag(i)(dlinesize-1 downto 0) := vmask(i);
tag(i)(TAG_HIGH downto TAG_LOW) := newtag(TAG_HIGH downto TAG_LOW);
tag(i)(CTAG_LRRPOS) := wlrr(i);
tag(i)(CTAG_LOCKPOS) := wlock(i);
ctx(i) := r.mmctrl1.ctx;
ptag(i)(TAG_HIGH downto TAG_LOW) := newptag(TAG_HIGH downto TAG_LOW);
end loop;
dcrami.tag <= tag; -- virtual tag
dcrami.ptag <= ptag; -- physical tag
dcrami.ctx <= ctx; -- context
dcrami.tenable <= enable; -- virtual tag ram enable
dcrami.twrite <= ctwrite; -- virtual tag ram write (port 1)
dcrami.tpwrite <= ctpwrite; -- virtual tag ram write (port 2)
dcrami.flush <= r.flush or flushl;
dcrami.senable <= senable; -- physical tag ram enable
dcrami.swrite <= csnoopwe; -- physical tag ram write
dcrami.saddress(19 downto (OFFSET_HIGH - OFFSET_LOW +1)) <=
zero32(19 downto (OFFSET_HIGH - OFFSET_LOW +1));
dcrami.saddress(OFFSET_HIGH - OFFSET_LOW downto 0) <= snoopaddr;
dcrami.faddress(19 downto (OFFSET_HIGH - OFFSET_LOW +1)) <=
zero32(19 downto (OFFSET_HIGH - OFFSET_LOW +1));
dcrami.faddress(OFFSET_HIGH - OFFSET_LOW downto 0) <= flushaddr;
-- data ram inputs
dcrami.denable <= enable;
dcrami.address(19 downto (OFFSET_HIGH - LINE_LOW + 1)) <= zero32(19 downto (OFFSET_HIGH - LINE_LOW + 1));
dcrami.address(OFFSET_HIGH - LINE_LOW downto 0) <= taddr;
dcrami.data <= ddatainv;
dcrami.dwrite <= cdwrite;
dcrami.ldramin.address(23 downto 2) <= laddr(23 downto 2);
dcrami.ldramin.enable <= (lramcs or lramwr) and not mcdo.scanen;
dcrami.ldramin.read <= rlramrd;
dcrami.ldramin.write <= lramwr;
dcrami.tdiag <= mcdo.testen & mcdo.scanen & r.tadj;
dcrami.sdiag <= mcdo.testen & mcdo.scanen & r.sadj;
dcrami.ddiag <= mcdo.testen & mcdo.scanen & r.dadj;
-- memory controller inputs
mcdi.address <= r.wb.addr;
mcdi.data <= r.wb.data1;
mcdi.burst <= r.burst;
mcdi.size <= r.wb.size;
mcdi.read <= r.wb.read;
mcdi.asi <= r.wb.asi;
mcdi.lock <= r.wb.lock;
mcdi.req <= r.req;
mcdi.cache <= r.cache;
-- diagnostic instruction cache access
dco.icdiag.flush <= iflush;
dco.icdiag.pflush <= pflush;
dco.icdiag.pflushaddr <= pflushaddr;
dco.icdiag.pflushtyp <= pflushtyp;
dco.icdiag.read <= read;
dco.icdiag.tag <= not r.asi(0);
dco.icdiag.ctx <= r.asi(4); --ASI_ICTX "10101"
dco.icdiag.addr <= r.xaddress;
dco.icdiag.enable <= r.icenable;
dco.icdiag.ilramen <= r.ilramen;
dco.icdiag.cctrl <= r.cctrl;
dco.icdiag.scanen <= mcdo.scanen;
-- IU data cache inputs
dco.data <= rdatav;
dco.mexc <= mexc;
dco.set <= conv_std_logic_vector(set, 2);
dco.hold <= r.holdn;
dco.mds <= mds;
dco.werr <= mcdo.werr;
dco.cache <= cache;
dco.hit <= r.hit;
if r.dstate = idle then dco.idle <= not r.stpend;
else dco.idle <= '0'; end if;
dco.scanen <= mcdo.scanen;
dco.testen <= mcdo.testen;
-- MMU
mmudci.trans_op <= mmudci_trans_op;
mmudci.transdata.data <= mmudci_transdata_data; --r.vaddr;
mmudci.transdata.su <= mmudci_su;
mmudci.transdata.read <= mmudci_read;
mmudci.transdata.isid <= id_dcache;
mmudci.transdata.wb_data <= dci.maddress;
mmudci.flush_op <= mmudci_flush_op;
mmudci.wb_op <= mmudci_wb_op;
mmudci.diag_op <= mmudci_diag_op;
mmudci.fsread <= mmudci_fsread;
mmudci.mmctrl1 <= r.mmctrl1;
mmudci.testin <= ahbsi.testin;
end process;
-- Local registers
reg1 : process(clk)
begin
if rising_edge(clk) then
r <= c;
if RESET_ALL and (rst = '0') then r <= RRES; end if;
end if;
end process;
sn2 : if DSNOOP2 /= 0 generate
reg2 : process(sclk)
begin
if rising_edge(sclk) then
rs <= cs;
if RESET_ALL and (rst = '0') then rs <= SRES; end if;
end if;
end process;
end generate;
nosn2 : if DSNOOP2 = 0 generate
rs.snoop <= '0'; rs.addr <= (others => '0');
rs.snhit <= (others => '0'); rs.mask <= (others => '0');
end generate;
reg2 : if (DSETS>1) and (drepl = lru) generate
reg2 : process(clk)
begin
if rising_edge(clk) then
rl <= cl;
if RESET_ALL and (rst = '0') then rl <= LRES; end if;
end if;
end process;
end generate;
noreg2 : if (DSETS = 1) or (drepl /= lru) generate
rl.write <= '0'; rl.waddr <= (others => '0');
rl.set <= (others => '0'); rl.lru <= (others => (others => '0'));
end generate;
-- pragma translate_off
chk : process
begin
assert not ((DSETS > 2) and (drepl = lrr)) report
"Wrong data cache configuration detected: LRR replacement requires 2 ways"
severity failure;
assert not ((DSETS = 3) and (drepl = dir)) report
"Wrong data cache configuration detected: Direct replacement requires 2 or 4 ways"
severity failure;
wait;
end process;
-- pragma translate_on
end ;
| gpl-2.0 | ed303361164c546974bebdb33a8fd9b9 | 0.525422 | 3.45939 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/techmap/inferred/memory_inferred.vhd | 1 | 10,012 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: mem_gen_gen.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: Behavioural memory generators
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity generic_syncram is
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
write : in std_ulogic
);
end;
architecture behavioral of generic_syncram is
type mem is array(0 to (2**abits -1))
of std_logic_vector((dbits -1) downto 0);
signal memarr : mem;
signal ra : std_logic_vector((abits -1) downto 0);
begin
main : process(clk)
begin
if rising_edge(clk) then
if write = '1' then
memarr(conv_integer(address)) <= datain;
end if;
ra <= address;
end if;
end process;
dataout <= memarr(conv_integer(ra));
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity generic_syncram_reg is
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
write : in std_ulogic
);
end;
architecture behavioral of generic_syncram_reg is
type mem is array(0 to (2**abits -1))
of std_logic_vector((dbits -1) downto 0);
signal memarr : mem;
signal ra : std_logic_vector((abits -1) downto 0);
attribute syn_ramstyle : string;
attribute syn_ramstyle of memarr : signal is "registers";
begin
main : process(clk)
begin
if rising_edge(clk) then
if write = '1' then
memarr(conv_integer(address)) <= datain;
end if;
ra <= address;
end if;
end process;
dataout <= memarr(conv_integer(ra));
end;
-- synchronous 2-port ram, common clock
LIBRARY ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity generic_syncram_2p is
generic (
abits : integer := 8;
dbits : integer := 32;
sepclk: integer := 0
);
port (
rclk : in std_ulogic;
wclk : in std_ulogic;
rdaddress: in std_logic_vector (abits -1 downto 0);
wraddress: in std_logic_vector (abits -1 downto 0);
data: in std_logic_vector (dbits -1 downto 0);
wren : in std_ulogic;
q: out std_logic_vector (dbits -1 downto 0)
);
end;
architecture behav of generic_syncram_2p is
type dregtype is array (0 to 2**abits - 1)
of std_logic_vector(dbits -1 downto 0);
signal rfd : dregtype;
begin
wp : process(wclk)
begin
if rising_edge(wclk) then
if wren = '1' then rfd(conv_integer(wraddress)) <= data; end if;
end if;
end process;
oneclk : if sepclk = 0 generate
rp : process(wclk) begin
if rising_edge(wclk) then q <= rfd(conv_integer(rdaddress)); end if;
end process;
end generate;
twoclk : if sepclk = 1 generate
rp : process(rclk) begin
if rising_edge(rclk) then q <= rfd(conv_integer(rdaddress)); end if;
end process;
end generate;
end;
-- synchronous 2-port ram, common clock, flip-flops
LIBRARY ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity generic_syncram_2p_reg is
generic (
abits : integer := 8;
dbits : integer := 32;
sepclk: integer := 0
);
port (
rclk : in std_ulogic;
wclk : in std_ulogic;
rdaddress: in std_logic_vector (abits -1 downto 0);
wraddress: in std_logic_vector (abits -1 downto 0);
data: in std_logic_vector (dbits -1 downto 0);
wren : in std_ulogic;
q: out std_logic_vector (dbits -1 downto 0)
);
end;
architecture behav of generic_syncram_2p_reg is
type dregtype is array (0 to 2**abits - 1)
of std_logic_vector(dbits -1 downto 0);
signal rfd : dregtype;
signal wa, ra : std_logic_vector (abits -1 downto 0);
attribute syn_ramstyle : string;
attribute syn_ramstyle of rfd : signal is "registers";
begin
wp : process(wclk)
begin
if rising_edge(wclk) then
if wren = '1' then rfd(conv_integer(wraddress)) <= data; end if;
end if;
end process;
oneclk : if sepclk = 0 generate
rp : process(wclk) begin
if rising_edge(wclk) then ra <= rdaddress; end if;
end process;
end generate;
twoclk : if sepclk = 1 generate
rp : process(rclk) begin
if rising_edge(rclk) then ra <= rdaddress; end if;
end process;
end generate;
q <= rfd(conv_integer(ra));
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity generic_regfile_3p is
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 32;
wrfst : integer := 0; numregs : integer := 40);
port (
wclk : in std_ulogic;
waddr : in std_logic_vector((abits -1) downto 0);
wdata : in std_logic_vector((dbits -1) downto 0);
we : in std_ulogic;
rclk : in std_ulogic;
raddr1 : in std_logic_vector((abits -1) downto 0);
re1 : in std_ulogic;
rdata1 : out std_logic_vector((dbits -1) downto 0);
raddr2 : in std_logic_vector((abits -1) downto 0);
re2 : in std_ulogic;
rdata2 : out std_logic_vector((dbits -1) downto 0)
);
end;
architecture rtl of generic_regfile_3p is
type mem is array(0 to numregs-1)
of std_logic_vector((dbits -1) downto 0);
signal memarr : mem;
signal ra1, ra2, wa : std_logic_vector((abits -1) downto 0);
signal din : std_logic_vector((dbits -1) downto 0);
signal wr : std_ulogic;
begin
main : process(wclk)
begin
if rising_edge(wclk) then
din <= wdata; wr <= we;
if (we = '1')
-- pragma translate_off
and (conv_integer(waddr) < numregs)
-- pragma translate_on
then wa <= waddr; end if;
if (re1 = '1')
-- pragma translate_off
and (conv_integer(raddr1) < numregs)
-- pragma translate_on
then ra1 <= raddr1; end if;
if (re2 = '1')
-- pragma translate_off
and (conv_integer(raddr2) < numregs)
-- pragma translate_on
then ra2 <= raddr2; end if;
if wr = '1' then
memarr(conv_integer(wa)) <= din;
end if;
end if;
end process;
rdata1 <= din when (wr = '1') and (wa = ra1) and (wrfst = 1)
else memarr(conv_integer(ra1));
rdata2 <= din when (wr = '1') and (wa = ra2) and (wrfst = 1)
else memarr(conv_integer(ra2));
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity generic_regfile_4p is
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 32;
wrfst : integer := 0; numregs : integer := 40; g0addr: integer := 0);
port (
wclk : in std_ulogic;
waddr : in std_logic_vector((abits -1) downto 0);
wdata : in std_logic_vector((dbits -1) downto 0);
we : in std_ulogic;
rclk : in std_ulogic;
raddr1 : in std_logic_vector((abits -1) downto 0);
re1 : in std_ulogic;
rdata1 : out std_logic_vector((dbits -1) downto 0);
raddr2 : in std_logic_vector((abits -1) downto 0);
re2 : in std_ulogic;
rdata2 : out std_logic_vector((dbits -1) downto 0);
raddr3 : in std_logic_vector((abits -1) downto 0);
re3 : in std_ulogic;
rdata3 : out std_logic_vector((dbits -1) downto 0)
);
end;
architecture rtl of generic_regfile_4p is
type mem is array(0 to numregs-1)
of std_logic_vector((dbits -1) downto 0);
signal memarr : mem;
signal ra1, ra2, ra3, wa : std_logic_vector((abits -1) downto 0);
signal din : std_logic_vector((dbits -1) downto 0);
signal wr : std_ulogic;
begin
main : process(wclk)
begin
if rising_edge(wclk) then
din <= wdata; wr <= we;
if (we = '1')
-- pragma translate_off
and (conv_integer(waddr) < numregs)
-- pragma translate_on
then wa <= waddr; end if;
if (re1 = '1')
-- pragma translate_off
and (conv_integer(raddr1) < numregs)
-- pragma translate_on
then ra1 <= raddr1; end if;
if (re2 = '1')
-- pragma translate_off
and (conv_integer(raddr2) < numregs)
-- pragma translate_on
then ra2 <= raddr2; end if;
if (re3 = '1')
-- pragma translate_off
and (conv_integer(raddr3) < numregs)
-- pragma translate_on
then ra3 <= raddr3; end if;
if wr = '1' then
memarr(conv_integer(wa)) <= din;
end if;
if g0addr > 0 and g0addr < numregs then
memarr(g0addr) <= (others => '0');
end if;
end if;
end process;
rdata1 <= din when (wr = '1') and (wa = ra1) and (wrfst = 1)
else memarr(conv_integer(ra1));
rdata2 <= din when (wr = '1') and (wa = ra2) and (wrfst = 1)
else memarr(conv_integer(ra2));
rdata3 <= din when (wr = '1') and (wa = ra3) and (wrfst = 1)
else memarr(conv_integer(ra3));
end;
| gpl-2.0 | 47be4bc7443f6c38a60778b0a76631f0 | 0.615761 | 3.325141 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/spacewire/spacewire.vhd | 1 | 30,557 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
package spacewire is
type grspw_in_type is record
d : std_logic_vector(3 downto 0);
dv : std_logic_vector(3 downto 0);
s : std_logic_vector(1 downto 0);
dconnect : std_logic_vector(3 downto 0);
tickin : std_ulogic;
tickinraw : std_ulogic;
timein : std_logic_vector(7 downto 0);
clkdiv10 : std_logic_vector(7 downto 0);
rmapen : std_ulogic;
rmapnodeaddr : std_logic_vector(7 downto 0);
dcrstval : std_logic_vector(9 downto 0);
timerrstval : std_logic_vector(11 downto 0);
nd : std_logic_vector(9 downto 0);
intpreload : std_logic_vector(30 downto 0);
inttreload : std_logic_vector(30 downto 0);
intiareload : std_logic_vector(30 downto 0);
intcreload : std_logic_vector(30 downto 0);
irqtxdefault : std_logic_vector(4 downto 0);
pnpen : std_ulogic;
pnpuvendid : std_logic_vector(15 downto 0);
pnpuprodid : std_logic_vector(15 downto 0);
pnpusn : std_logic_vector(31 downto 0);
end record;
type grspw_out_type is record
d : std_logic_vector(3 downto 0);
s : std_logic_vector(3 downto 0);
tickout : std_ulogic;
tickoutraw : std_ulogic;
tickindone : std_ulogic;
timeout : std_logic_vector(7 downto 0);
linkdis : std_ulogic;
rmapact : std_ulogic;
rxdataout : std_logic_vector(8 downto 0);
rxdav : std_ulogic;
loopback : std_ulogic;
rxrst : std_ulogic;
end record;
constant grspw_in_none : grspw_in_type :=
((others => '0'), (others => '0'), (others => '0'),
(others => '0'), '0', '0', (others => '0'), (others => '0'), '0',
(others => '0'), (others => '0'), (others => '0'), (others => '0'),
(others => '0'), (others => '0'), (others => '0'), (others => '0'),
(others => '0'), '0', (others => '0'), (others => '0'),
(others => '0'));
constant grspw_out_none : grspw_out_type :=
((others => '0'), (others => '0'), '0', '0', '0', (others => '0'),
'0', '0', (others => '0'), '0', '0', '0');
type grspw_codec_in_type is record
--spw
d : std_logic_vector(3 downto 0);
dv : std_logic_vector(3 downto 0);
dconnect : std_logic_vector(3 downto 0);
--link fsm
linkdisabled : std_ulogic;
linkstart : std_ulogic;
autostart : std_ulogic;
portsel : std_ulogic;
noportforce : std_ulogic;
rdivisor : std_logic_vector(7 downto 0);
idivisor : std_logic_vector(7 downto 0);
--rx iface
rxiread : std_ulogic;
rxififorst : std_ulogic;
--tx iface
txiwrite : std_ulogic;
txichar : std_logic_vector(8 downto 0);
txififorst : std_ulogic;
--time iface
tickin : std_ulogic;
timein : std_logic_vector(7 downto 0);
-- input timing testing
testd : std_logic_vector(1 downto 0);
tests : std_logic_vector(1 downto 0);
testinput : std_ulogic;
end record;
type grspw_codec_out_type is record
--spw
do : std_logic_vector(3 downto 0);
so : std_logic_vector(3 downto 0);
--link fsm
state : std_logic_vector(2 downto 0);
actport : std_ulogic;
dconnecterr : std_ulogic;
crederr : std_ulogic;
escerr : std_ulogic;
parerr : std_ulogic;
--rx iface
rxicharav : std_ulogic;
rxicharcnt : std_logic_vector(11 downto 0);
rxichar : std_logic_vector(8 downto 0);
--tx iface
txicharcnt : std_logic_vector(11 downto 0);
txifull : std_ulogic;
txiempty : std_ulogic;
txififorst : std_ulogic;
--time iface
tickin_done : std_ulogic;
tickin_busy : std_ulogic;
tickout : std_ulogic;
timeout : std_logic_vector(7 downto 0);
--memory error
merror : std_ulogic;
--credit counters
ocredcnt : std_logic_vector(5 downto 0);
credcnt : std_logic_vector(5 downto 0);
--misc
powerdown : std_ulogic;
powerdownrx : std_ulogic;
end record;
type grspw_dma_in_type is record
--rx iface
rxiread : std_ulogic;
--tx iface
txiwrite : std_ulogic;
txichar : std_logic_vector(8 downto 0);
txififorst : std_ulogic;
--internal time iface
itickin : std_ulogic;
itimein : std_logic_vector(7 downto 0);
--time iface
tickin : std_ulogic;
timein : std_logic_vector(7 downto 0);
--rmap iface
rmapen : std_ulogic;
rmapnodeaddr : std_logic_vector(7 downto 0);
end record;
type grspw_dma_out_type is record
--rx iface
rxicharav : std_ulogic;
rxichar : std_logic_vector(8 downto 0);
--tx iface
txicharcnt : std_logic_vector(11 downto 0);
txifull : std_ulogic;
txififorst : std_ulogic;
--internal time iface
itickout : std_ulogic;
itimeout : std_logic_vector(7 downto 0);
--time iface
tickout : std_ulogic;
timeout : std_logic_vector(7 downto 0);
--memory error
merror : std_ulogic;
end record;
type grspw_fifo_in_type is record
enbridge : std_ulogic;
--rx iface
rxiread : std_ulogic;
--tx iface
txiwrite : std_ulogic;
txichar : std_logic_vector(8 downto 0);
txififorst : std_ulogic;
--internal time iface
itickin : std_ulogic;
itimein : std_logic_vector(7 downto 0);
--time iface
tickin : std_ulogic;
timein : std_logic_vector(7 downto 0);
enexttime : std_ulogic;
rmapen : std_ulogic;
--external interface
etxwrite : std_ulogic;
etxchar : std_logic_vector(8 downto 0);
erxread : std_ulogic;
end record;
type grspw_fifo_out_type is record
--rx iface
rxicharcnt : std_logic_vector(11 downto 0);
rxicharav : std_ulogic;
rxichar : std_logic_vector(8 downto 0);
--tx iface
txicharcnt : std_logic_vector(11 downto 0);
txifull : std_ulogic;
txififorst : std_ulogic;
--internal time iface
itickout : std_ulogic;
itimeout : std_logic_vector(7 downto 0);
ienexttime : std_ulogic;
--time iface
tickout : std_ulogic;
timeout : std_logic_vector(7 downto 0);
--external interface
erxcharav : std_ulogic;
erxaempty : std_ulogic;
etxfull : std_ulogic;
etxafull : std_ulogic;
erxchar : std_logic_vector(8 downto 0);
--memory errors
merror : std_ulogic;
end record;
type grspw_router_fifo_char_type is array (0 to 30) of std_logic_vector(8 downto 0);
type grspw_router_time_type is array (0 to 30) of std_logic_vector(7 downto 0);
type grspw_router_in_type is record
rmapen : std_logic_vector(30 downto 0);
idivisor : std_logic_vector(7 downto 0);
txwrite : std_logic_vector(30 downto 0);
txchar : grspw_router_fifo_char_type;
rxread : std_logic_vector(30 downto 0);
tickin : std_logic_vector(30 downto 0);
timein : grspw_router_time_type;
reload : std_logic_vector(31 downto 0);
reloadn : std_logic_vector(31 downto 0);
timeren : std_ulogic;
timecodeen : std_ulogic;
cfglock : std_ulogic;
selfaddren : std_ulogic;
linkstartreq : std_logic_vector(31 downto 1);
autodconnect : std_logic_vector(31 downto 1);
instanceid : std_logic_vector(7 downto 0);
enbridge : std_logic_vector(30 downto 0);
enexttime : std_logic_vector(30 downto 0);
auxtickin : std_ulogic;
auxtimeinen : std_ulogic;
auxtimein : std_logic_vector(7 downto 0);
irqtimeoutreload : std_logic_vector(31 downto 0);
ahbso : ahb_slv_out_type;
interruptcodeen : std_ulogic;
pnpen : std_ulogic;
timecodefilt : std_ulogic;
interruptfwd : std_ulogic;
spillifnrdy : std_logic_vector(31 downto 1);
timecoderegen : std_ulogic;
gpi : std_logic_vector(127 downto 0);
staticrouteen : std_ulogic;
spwclklock : std_ulogic;
irqgenreload : std_logic_vector(31 downto 0);
-- input timing testing
testd : std_logic_vector(61 downto 0);
tests : std_logic_vector(61 downto 0);
testinput : std_ulogic;
end record;
type grspw_router_out_type is record
rxcharav : std_logic_vector(30 downto 0);
rxaempty : std_logic_vector(30 downto 0);
txfull : std_logic_vector(30 downto 0);
txafull : std_logic_vector(30 downto 0);
rxchar : grspw_router_fifo_char_type;
auxtickout : std_ulogic;
auxtimeout : std_logic_vector(7 downto 0);
tickout : std_logic_vector(30 downto 0);
timeout : grspw_router_time_type;
gerror : std_ulogic;
lerror : std_ulogic;
merror : std_ulogic;
linkrun : std_logic_vector(30 downto 0);
porterr : std_logic_vector(31 downto 0);
spwen : std_logic_vector(30 downto 0);
ahbsi : ahb_slv_in_type;
powerdown : std_logic_vector(30 downto 0);
powerdownrx : std_logic_vector(30 downto 0);
gpo : std_logic_vector(127 downto 0);
end record;
constant grspw_router_in_none : grspw_router_in_type :=
((others => '0'), (others => '0'), (others => '0'), (others => (others => '0')),
(others => '0'), (others => '0'), (others => (others => '0')), (others => '0'),
(others => '0'), '0', '0', '0', '0', (others => '0') , (others => '0'), (others => '0'), (others => '0'),
(others => '0'), '0', '0', (others => '0'), (others => '0'), ahbs_none, '0', '0', '0', '0',
(others => '0'), '0', (others => '0'), '0', '1', (others => '0'), (others => '0'), (others => '0'), '0');
constant grspw_router_out_none : grspw_router_out_type :=
((others => '0'), (others => '0'), (others => '0'), (others => '0'),
(others => (others => '0')), '0', (others => '0'), (others => '0'), (others => (others => '0')), '0',
'0', '0', (others => '0'), (others => '0'), (others => '0'), ahbs_in_none,
(others => '0'), (others => '0'), (others => '0'));
type spw_ahb_mst_out_vector is array (natural range <>) of
ahb_mst_out_type;
type spw_apb_slv_out_vector is array (natural range <>) of
apb_slv_out_type;
component grspw_phy is
generic(
tech : integer := 0;
rxclkbuftype : integer range 0 to 2 := 0;
scantest : integer range 0 to 1 := 0
);
port(
rxrst : in std_ulogic;
di : in std_ulogic;
si : in std_ulogic;
rxclko : out std_ulogic;
do : out std_ulogic;
ndo : out std_logic_vector(4 downto 0);
dconnect : out std_logic_vector(1 downto 0);
testen : in std_ulogic := '0';
testclk : in std_ulogic := '0'
);
end component;
component grspw2_phy is
generic(
scantest : integer;
tech : integer;
input_type : integer;
input_level : integer := 0;
input_voltage : integer := x33v;
rxclkbuftype : integer range 0 to 2 := 0
);
port(
rstn : in std_ulogic;
rxclki : in std_ulogic;
rxclkin : in std_ulogic;
nrxclki : in std_ulogic;
di : in std_ulogic;
si : in std_ulogic; --used as df when input_type=3
do : out std_logic_vector(1 downto 0);
dov : out std_logic_vector(1 downto 0);
dconnect : out std_logic_vector(1 downto 0);
rxclko : out std_ulogic;
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0';
-- input timing testing
testdo : out std_logic_vector(1 downto 0);
testso : out std_logic_vector(1 downto 0)
);
end component;
component grspw2 is
generic(
tech : integer range 0 to NTECH := inferred;
hindex : integer range 0 to NAHBMST-1 := 0;
pindex : integer range 0 to NAPBSLV-1 := 0;
paddr : integer range 0 to 16#FFF# := 0;
pmask : integer range 0 to 16#FFF# := 16#FFF#;
pirq : integer range 0 to NAHBIRQ-1 := 0;
rmap : integer range 0 to 2 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 64 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxclkbuftype : integer range 0 to 2 := 0;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
ft : integer range 0 to 2 := 0;
scantest : integer range 0 to 1 := 0;
techfifo : integer range 0 to 1 := 1;
ports : integer range 1 to 2 := 1;
dmachan : integer range 1 to 4 := 1;
memtech : integer range 0 to NTECH := DEFMEMTECH;
input_type : integer range 0 to 4 := 0;
output_type : integer range 0 to 2 := 0;
rxtx_sameclk : integer range 0 to 1 := 0;
netlist : integer range 0 to 1 := 0;
nodeaddr : integer range 0 to 255 := 254;
destkey : integer range 0 to 255 := 0;
interruptdist : integer range 0 to 32 := 0;
intscalerbits : integer range 0 to 31 := 0;
intisrtimerbits : integer range 0 to 31 := 0;
intiatimerbits : integer range 0 to 31 := 0;
intctimerbits : integer range 0 to 31 := 0;
tickinasync : integer range 0 to 1 := 0;
pnp : integer range 0 to 2 := 0;
pnpvendid : integer range 0 to 16#FFFF# := 0;
pnpprodid : integer range 0 to 16#FFFF# := 0;
pnpmajorver : integer range 0 to 16#FF# := 0;
pnpminorver : integer range 0 to 16#FF# := 0;
pnppatch : integer range 0 to 16#FF# := 0;
num_txdesc : integer range 64 to 512 := 64;
num_rxdesc : integer range 128 to 1024 := 128
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxclk0 : in std_ulogic;
rxclk1 : in std_ulogic;
txclk : in std_ulogic;
txclkn : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
swni : in grspw_in_type;
swno : out grspw_out_type
);
end component;
component grspw is
generic(
tech : integer range 0 to NTECH := DEFFABTECH;
hindex : integer range 0 to NAHBMST-1 := 0;
pindex : integer range 0 to NAPBSLV-1 := 0;
paddr : integer range 0 to 16#FFF# := 0;
pmask : integer range 0 to 16#FFF# := 16#FFF#;
pirq : integer range 0 to NAHBIRQ-1 := 0;
sysfreq : integer := 10000;
usegen : integer range 0 to 1 := 1;
nsync : integer range 1 to 2 := 1;
rmap : integer range 0 to 2 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 32 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxclkbuftype : integer range 0 to 2 := 0;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
ft : integer range 0 to 2 := 0;
scantest : integer range 0 to 1 := 0;
techfifo : integer range 0 to 1 := 1;
netlist : integer range 0 to 1 := 0;
ports : integer range 1 to 2 := 1;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nodeaddr : integer range 0 to 255 := 254;
destkey : integer range 0 to 255 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxclk : in std_logic_vector(1 downto 0);
txclk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
swni : in grspw_in_type;
swno : out grspw_out_type);
end component;
type grspw_in_type_vector is array (natural range <>) of grspw_in_type;
type grspw_out_type_vector is array (natural range <>) of grspw_out_type;
component grspwm is
generic(
tech : integer range 0 to NTECH := DEFFABTECH;
hindex : integer range 0 to NAHBMST-1 := 0;
pindex : integer range 0 to NAPBSLV-1 := 0;
paddr : integer range 0 to 16#FFF# := 0;
pmask : integer range 0 to 16#FFF# := 16#FFF#;
pirq : integer range 0 to NAHBIRQ-1 := 0;
sysfreq : integer := 10000; -- spw1
usegen : integer range 0 to 1 := 1; -- spw1
nsync : integer range 1 to 2 := 1;
rmap : integer range 0 to 2 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 64 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxclkbuftype : integer range 0 to 2 := 0;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
ft : integer range 0 to 2 := 0;
scantest : integer range 0 to 1 := 0;
techfifo : integer range 0 to 1 := 1;
netlist : integer range 0 to 1 := 0; -- spw1
ports : integer range 1 to 2 := 1;
dmachan : integer range 1 to 4 := 1; -- spw2
memtech : integer range 0 to NTECH := DEFMEMTECH;
spwcore : integer range 1 to 2 := 2;
input_type : integer range 0 to 4 := 0;
output_type : integer range 0 to 2 := 0;
rxtx_sameclk : integer range 0 to 1 := 0;
nodeaddr : integer range 0 to 255 := 254;
destkey : integer range 0 to 255 := 0;
interruptdist : integer range 0 to 32 := 0; -- spw2
intscalerbits : integer range 0 to 31 := 0; -- spw2
intisrtimerbits : integer range 0 to 31 := 0; -- spw2
intiatimerbits : integer range 0 to 31 := 0; -- spw2
intctimerbits : integer range 0 to 31 := 0; -- spw2
tickinasync : integer range 0 to 2 := 0; -- spw2
pnp : integer range 0 to 2 := 0; -- spw2
pnpvendid : integer range 0 to 16#FFF# := 0; -- spw2
pnpprodid : integer range 0 to 16#FFF# := 0; -- spw2
pnpmajorver : integer range 0 to 16#FF# := 0; -- spw2
pnpminorver : integer range 0 to 16#FF# := 0; -- spw2
pnppatch : integer range 0 to 16#FF# := 0; -- spw2
num_txdesc : integer range 64 to 512 := 64; -- spw2
num_rxdesc : integer range 128 to 1024 := 128 -- spw2
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxclk0 : in std_ulogic;
rxclk1 : in std_ulogic;
txclk : in std_ulogic;
txclkn : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
swni : in grspw_in_type;
swno : out grspw_out_type
);
end component;
component grspw_codec is
generic(
ports : integer range 1 to 2 := 1;
input_type : integer range 0 to 4 := 0;
output_type : integer range 0 to 2 := 0;
rxtx_sameclk : integer range 0 to 1 := 0;
fifosize : integer range 16 to 2048 := 64;
tech : integer;
scantest : integer range 0 to 1 := 0;
techfifo : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
inputtest : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxclk0 : in std_ulogic;
rxclk1 : in std_ulogic;
txclk : in std_ulogic;
txclkn : in std_ulogic;
testen : in std_ulogic;
testrst : in std_ulogic;
lii : in grspw_codec_in_type;
lio : out grspw_codec_out_type;
testin : in std_logic_vector(testin_width-1 downto 0) := testin_none
);
end component;
component grspw_codec_clockgate is
generic(
tech : integer;
scantest : integer range 0 to 1 := 0;
ports : integer range 1 to 2 := 1;
output_type : integer range 0 to 2 := 0;
clkgate : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxclk0 : in std_ulogic;
rxclk1 : in std_ulogic;
txclk : in std_ulogic;
txclkn : in std_ulogic;
testen : in std_ulogic;
testrst : in std_ulogic;
disableclk : in std_ulogic;
disablerxclk0 : in std_ulogic;
disablerxclk1 : in std_ulogic;
disabletxclk : in std_ulogic;
disabletxclkn : in std_ulogic;
gclk : out std_ulogic;
grxclk0 : out std_ulogic;
grxclk1 : out std_ulogic;
gtxclk : out std_ulogic;
gtxclkn : out std_ulogic;
grst : out std_ulogic
);
end component;
component grspwrouter is
generic(
input_type : integer range 0 to 4 := 0;
output_type : integer range 0 to 2 := 0;
rxtx_sameclk : integer range 0 to 1 := 0;
fifosize : integer range 16 to 2048 := 64;
tech : integer;
scantest : integer range 0 to 1 := 0;
techfifo : integer range 0 to 255 := 0;
ft : integer range 0 to 2 := 0;
spwen : integer range 0 to 1 := 1;
ambaen : integer range 0 to 1 := 0;
fifoen : integer range 0 to 1 := 0;
spwports : integer range 0 to 31 := 2;
ambaports : integer range 0 to 16 := 0;
fifoports : integer range 0 to 31 := 0;
arbitration : integer range 0 to 1 := 0; --0=rrobin, 1=priority
rmap : integer range 0 to 16#FFFF# := 0;
rmapcrc : integer range 0 to 16#FFFF# := 0;
fifosize2 : integer range 4 to 32 := 32;
almostsize : integer range 1 to 32 := 8;
rxunaligned : integer range 0 to 16#FFFF# := 0;
rmapbufs : integer range 2 to 8 := 4;
dmachan : integer range 1 to 4 := 1;
hindex : integer range 0 to NAHBMST-1 := 0;
pindex : integer range 0 to NAPBSLV-1 := 0;
paddr : integer range 0 to 16#FFF# := 0;
pmask : integer range 0 to 16#FFF# := 16#FFF#;
pirq : integer range 0 to NAHBIRQ-1 := 0;
cfghindex : integer range 0 to NAHBSLV-1 := 0;
cfghaddr : integer range 0 to 16#FFF# := 0;
cfghmask : integer range 0 to 16#FFF# := 16#FF0#;
ahbslven : integer range 0 to 1 := 0;
timerbits : integer range 0 to 31 := 0;
pnp : integer range 0 to 2 := 0;
autoscrub : integer range 0 to 1 := 0;
sim : integer range 0 to 1 := 0;
dualport : integer range 0 to 1 := 0;
charcntbits : integer range 0 to 32 := 0;
pktcntbits : integer range 0 to 32 := 0;
prescalermin : integer := 250;
spacewired : integer range 0 to 1 := 0;
interruptdist : integer range 0 to 1 := 0;
apbctrl : integer range 0 to 1 := 0;
rmapmaxsize : integer range 4 to 512 := 4;
gpolbits : integer range 0 to 128 := 0;
gpopbits : integer range 0 to 128 := 0;
gpibits : integer range 0 to 128 := 0;
customport : integer range 0 to 1 := 0;
codecclkgate : integer range 0 to 1 := 0;
inputtest : integer range 0 to 1 := 0;
spwpnpvendid : integer range 0 to 16#FFFF# := 0;
spwpnpprodid : integer range 0 to 16#FFFF# := 0;
porttimerbits : integer range 1 to 32 := 10;
irqtimerbits : integer range 1 to 32 := 10;
auxtimeen : integer range 0 to 1 := 1
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxclk : in std_logic_vector(spwports*(1+dualport)-spwen downto 0);
txclk : in std_ulogic;
txclkn : in std_ulogic;
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic;
di : in std_logic_vector(spwports*(2+2*dualport)-spwen downto 0);
dvi : in std_logic_vector(spwports*(2+2*dualport)-spwen downto 0);
dconnect : in std_logic_vector(spwports*(2+2*dualport)-spwen downto 0);
do : out std_logic_vector(spwports*(2+2*dualport)-spwen downto 0);
so : out std_logic_vector(spwports*(2+2*dualport)-spwen downto 0);
ahbmi : in ahb_mst_in_type;
ahbmo : out spw_ahb_mst_out_vector(0 to ambaports*ambaen-ambaen);
apbi : in apb_slv_in_type;
apbo : out spw_apb_slv_out_vector(0 to ambaports*ambaen-ambaen);
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
ri : in grspw_router_in_type;
ro : out grspw_router_out_type
);
end component grspwrouter;
component grspw2_dma is
generic(
hindex : integer range 0 to NAHBMST-1 := 0;
pindex : integer range 0 to NAPBSLV-1:= 0;
pirq : integer range 0 to NAHBIRQ-1 := 0;
paddr : integer range 0 to 16#FFF# := 0;
pmask : integer range 0 to 16#FFF# := 16#FFF#;
rmap : integer range 0 to 2 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 32 := 32;
fifosize2 : integer range 16 to 2048 := 64;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
scantest : integer range 0 to 1 := 0;
dmachan : integer range 1 to 4 := 1;
tech : integer range 0 to NTECH := inferred;
techfifo : integer range 0 to 7 := 1;
ft : integer range 0 to 2 := 0;
nodeaddr : integer range 0 to 255 := 254
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
--ahb mst
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
--apb
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
--link
lii : in grspw_dma_in_type;
lio : out grspw_dma_out_type;
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0';
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0) := testin_none
);
end component;
component grspw2_fifo is
generic(
fifosize : integer range 16 to 2048 := 64;
almostsize : integer range 1 to 32 := 8;
scantest : integer range 0 to 1 := 0;
tech : integer range 0 to NTECH := inferred;
techfifo : integer range 0 to 1 := 1;
ft : integer range 0 to 2 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
--link
lii : in grspw_fifo_in_type;
lio : out grspw_fifo_out_type;
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0';
testin : in std_logic_vector(testin_width-1 downto 0) := testin_none
);
end component;
type grspw_router_fifo_in_type is record
txwrite : std_ulogic;
txchar : std_logic_vector(8 downto 0);
rxread : std_ulogic;
tickin : std_ulogic;
timein : std_logic_vector(7 downto 0);
enbridge : std_ulogic;
enexttime : std_ulogic;
end record;
type grspw_router_fifo_out_type is record
rxcharav : std_ulogic;
rxaempty : std_ulogic;
txfull : std_ulogic;
txafull : std_ulogic;
rxchar : std_logic_vector(8 downto 0);
tickout : std_ulogic;
timeout : std_logic_vector(7 downto 0);
end record;
component grspw2_sist is
generic(
pindex : integer range 0 to NAPBSLV-1:= 0;
pirq : integer range 0 to NAHBIRQ-1 := 0;
paddr : integer range 0 to 16#FFF# := 0;
pmask : integer range 0 to 16#FFF# := 16#FFF#);
port(
rstn : in std_ulogic;
clk : in std_ulogic;
enable : in std_ulogic;
-- amba apb
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
-- fifo i/f
fifoi : in grspw_router_fifo_out_type;
fifoo : out grspw_router_fifo_in_type);
end component;
end package;
| gpl-2.0 | 83d67aaf42b8a0d96fa45665139f7a3a | 0.531171 | 3.633413 | false | true | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/lab3_project.xpr/project_1/project_1.srcs/sources_1/bd/design_1/ipshared/7b8d/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd | 7 | 95,183 | `protect begin_protected
`protect version = 1
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`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2017_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 67920)
`protect data_block
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`protect end_protected
| mit | a8b1e79f2ad6d57ebee74ede6838d44e | 0.952302 | 1.816088 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/solution_OH/syn/vhdl/convolve_kernel.vhd | 3 | 770,747 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity convolve_kernel is
generic (
C_S_AXI_CONTROL_ADDR_WIDTH : INTEGER := 4;
C_S_AXI_CONTROL_DATA_WIDTH : INTEGER := 32 );
port (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
bufw_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_EN_A : OUT STD_LOGIC;
bufw_WEN_A : OUT STD_LOGIC_VECTOR (63 downto 0);
bufw_Din_A : OUT STD_LOGIC_VECTOR (511 downto 0);
bufw_Dout_A : IN STD_LOGIC_VECTOR (511 downto 0);
bufw_Clk_A : OUT STD_LOGIC;
bufw_Rst_A : OUT STD_LOGIC;
bufi_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_EN_A : OUT STD_LOGIC;
bufi_WEN_A : OUT STD_LOGIC_VECTOR (63 downto 0);
bufi_Din_A : OUT STD_LOGIC_VECTOR (511 downto 0);
bufi_Dout_A : IN STD_LOGIC_VECTOR (511 downto 0);
bufi_Clk_A : OUT STD_LOGIC;
bufi_Rst_A : OUT STD_LOGIC;
bufo_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_EN_A : OUT STD_LOGIC;
bufo_WEN_A : OUT STD_LOGIC_VECTOR (63 downto 0);
bufo_Din_A : OUT STD_LOGIC_VECTOR (511 downto 0);
bufo_Dout_A : IN STD_LOGIC_VECTOR (511 downto 0);
bufo_Clk_A : OUT STD_LOGIC;
bufo_Rst_A : OUT STD_LOGIC;
s_axi_control_AWVALID : IN STD_LOGIC;
s_axi_control_AWREADY : OUT STD_LOGIC;
s_axi_control_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_CONTROL_ADDR_WIDTH-1 downto 0);
s_axi_control_WVALID : IN STD_LOGIC;
s_axi_control_WREADY : OUT STD_LOGIC;
s_axi_control_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_CONTROL_DATA_WIDTH-1 downto 0);
s_axi_control_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_CONTROL_DATA_WIDTH/8-1 downto 0);
s_axi_control_ARVALID : IN STD_LOGIC;
s_axi_control_ARREADY : OUT STD_LOGIC;
s_axi_control_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_CONTROL_ADDR_WIDTH-1 downto 0);
s_axi_control_RVALID : OUT STD_LOGIC;
s_axi_control_RREADY : IN STD_LOGIC;
s_axi_control_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_CONTROL_DATA_WIDTH-1 downto 0);
s_axi_control_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
s_axi_control_BVALID : OUT STD_LOGIC;
s_axi_control_BREADY : IN STD_LOGIC;
s_axi_control_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
interrupt : OUT STD_LOGIC );
end;
architecture behav of convolve_kernel is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"convolve_kernel,hls_ip_2017_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=1,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=5.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=5.305800,HLS_SYN_LAT=102544,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=80,HLS_SYN_FF=43626,HLS_SYN_LUT=24925}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (17 downto 0) := "000000000000000001";
constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (17 downto 0) := "000000000000000010";
constant ap_ST_fsm_pp0_stage1 : STD_LOGIC_VECTOR (17 downto 0) := "000000000000000100";
constant ap_ST_fsm_pp0_stage2 : STD_LOGIC_VECTOR (17 downto 0) := "000000000000001000";
constant ap_ST_fsm_pp0_stage3 : STD_LOGIC_VECTOR (17 downto 0) := "000000000000010000";
constant ap_ST_fsm_pp0_stage4 : STD_LOGIC_VECTOR (17 downto 0) := "000000000000100000";
constant ap_ST_fsm_pp0_stage5 : STD_LOGIC_VECTOR (17 downto 0) := "000000000001000000";
constant ap_ST_fsm_pp0_stage6 : STD_LOGIC_VECTOR (17 downto 0) := "000000000010000000";
constant ap_ST_fsm_pp0_stage7 : STD_LOGIC_VECTOR (17 downto 0) := "000000000100000000";
constant ap_ST_fsm_pp0_stage8 : STD_LOGIC_VECTOR (17 downto 0) := "000000001000000000";
constant ap_ST_fsm_pp0_stage9 : STD_LOGIC_VECTOR (17 downto 0) := "000000010000000000";
constant ap_ST_fsm_pp0_stage10 : STD_LOGIC_VECTOR (17 downto 0) := "000000100000000000";
constant ap_ST_fsm_pp0_stage11 : STD_LOGIC_VECTOR (17 downto 0) := "000001000000000000";
constant ap_ST_fsm_pp0_stage12 : STD_LOGIC_VECTOR (17 downto 0) := "000010000000000000";
constant ap_ST_fsm_pp0_stage13 : STD_LOGIC_VECTOR (17 downto 0) := "000100000000000000";
constant ap_ST_fsm_pp0_stage14 : STD_LOGIC_VECTOR (17 downto 0) := "001000000000000000";
constant ap_ST_fsm_pp0_stage15 : STD_LOGIC_VECTOR (17 downto 0) := "010000000000000000";
constant ap_ST_fsm_state161 : STD_LOGIC_VECTOR (17 downto 0) := "100000000000000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_boolean_1 : BOOLEAN := true;
constant C_S_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_boolean_0 : BOOLEAN := false;
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
constant ap_const_lv32_E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001110";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011";
constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv32_C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001100";
constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
constant ap_const_lv32_D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001101";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv13_0 : STD_LOGIC_VECTOR (12 downto 0) := "0000000000000";
constant ap_const_lv3_0 : STD_LOGIC_VECTOR (2 downto 0) := "000";
constant ap_const_lv12_0 : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
constant ap_const_lv10_0 : STD_LOGIC_VECTOR (9 downto 0) := "0000000000";
constant ap_const_lv5_0 : STD_LOGIC_VECTOR (4 downto 0) := "00000";
constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_lv64_FFFFFFFFFFFFFFFF : STD_LOGIC_VECTOR (63 downto 0) := "1111111111111111111111111111111111111111111111111111111111111111";
constant ap_const_lv32_20 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100000";
constant ap_const_lv32_3F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111111";
constant ap_const_lv32_40 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000000";
constant ap_const_lv32_5F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011111";
constant ap_const_lv32_60 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001100000";
constant ap_const_lv32_7F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111111";
constant ap_const_lv32_80 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010000000";
constant ap_const_lv32_9F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010011111";
constant ap_const_lv32_A0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010100000";
constant ap_const_lv32_BF : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010111111";
constant ap_const_lv32_C0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011000000";
constant ap_const_lv32_DF : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011011111";
constant ap_const_lv32_E0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011100000";
constant ap_const_lv32_FF : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011111111";
constant ap_const_lv32_100 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100000000";
constant ap_const_lv32_11F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100011111";
constant ap_const_lv32_120 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100100000";
constant ap_const_lv32_13F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100111111";
constant ap_const_lv32_140 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101000000";
constant ap_const_lv32_15F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101011111";
constant ap_const_lv32_160 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101100000";
constant ap_const_lv32_17F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101111111";
constant ap_const_lv32_180 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000110000000";
constant ap_const_lv32_19F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000110011111";
constant ap_const_lv32_1A0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000110100000";
constant ap_const_lv32_1BF : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000110111111";
constant ap_const_lv32_1C0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000111000000";
constant ap_const_lv32_1DF : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000111011111";
constant ap_const_lv32_1E0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000111100000";
constant ap_const_lv32_1FF : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000111111111";
constant ap_const_lv5_1 : STD_LOGIC_VECTOR (4 downto 0) := "00001";
constant ap_const_lv13_1900 : STD_LOGIC_VECTOR (12 downto 0) := "1100100000000";
constant ap_const_lv13_1 : STD_LOGIC_VECTOR (12 downto 0) := "0000000000001";
constant ap_const_lv12_500 : STD_LOGIC_VECTOR (11 downto 0) := "010100000000";
constant ap_const_lv5_10 : STD_LOGIC_VECTOR (4 downto 0) := "10000";
constant ap_const_lv10_100 : STD_LOGIC_VECTOR (9 downto 0) := "0100000000";
constant ap_const_lv12_1 : STD_LOGIC_VECTOR (11 downto 0) := "000000000001";
constant ap_const_lv3_1 : STD_LOGIC_VECTOR (2 downto 0) := "001";
constant ap_const_lv10_1 : STD_LOGIC_VECTOR (9 downto 0) := "0000000001";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv7_5 : STD_LOGIC_VECTOR (6 downto 0) := "0000101";
constant ap_const_lv5_5 : STD_LOGIC_VECTOR (4 downto 0) := "00101";
constant ap_const_lv6_19 : STD_LOGIC_VECTOR (5 downto 0) := "011001";
constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
constant ap_const_lv7_32 : STD_LOGIC_VECTOR (6 downto 0) := "0110010";
constant ap_const_lv7_4B : STD_LOGIC_VECTOR (6 downto 0) := "1001011";
constant ap_const_lv8_64 : STD_LOGIC_VECTOR (7 downto 0) := "01100100";
constant ap_const_lv8_7D : STD_LOGIC_VECTOR (7 downto 0) := "01111101";
constant ap_const_lv8_96 : STD_LOGIC_VECTOR (7 downto 0) := "10010110";
constant ap_const_lv8_AF : STD_LOGIC_VECTOR (7 downto 0) := "10101111";
constant ap_const_lv9_E1 : STD_LOGIC_VECTOR (8 downto 0) := "011100001";
constant ap_const_lv9_FA : STD_LOGIC_VECTOR (8 downto 0) := "011111010";
constant ap_const_lv9_113 : STD_LOGIC_VECTOR (8 downto 0) := "100010011";
constant ap_const_lv9_12C : STD_LOGIC_VECTOR (8 downto 0) := "100101100";
constant ap_const_lv9_145 : STD_LOGIC_VECTOR (8 downto 0) := "101000101";
constant ap_const_lv9_15E : STD_LOGIC_VECTOR (8 downto 0) := "101011110";
constant ap_const_lv9_177 : STD_LOGIC_VECTOR (8 downto 0) := "101110111";
constant ap_const_lv32_11 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010001";
constant ap_const_lv512_lc_1 : STD_LOGIC_VECTOR (511 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
signal ap_rst_n_inv : STD_LOGIC;
signal ap_start : STD_LOGIC;
signal ap_done : STD_LOGIC;
signal ap_idle : STD_LOGIC;
signal ap_CS_fsm : STD_LOGIC_VECTOR (17 downto 0) := "000000000000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal ap_ready : STD_LOGIC;
signal indvar_flatten1_reg_351 : STD_LOGIC_VECTOR (12 downto 0);
signal i_reg_362 : STD_LOGIC_VECTOR (2 downto 0);
signal indvar_flatten2_reg_374 : STD_LOGIC_VECTOR (11 downto 0);
signal j_reg_385 : STD_LOGIC_VECTOR (2 downto 0);
signal indvar_flatten_reg_397 : STD_LOGIC_VECTOR (9 downto 0);
signal row_b_reg_409 : STD_LOGIC_VECTOR (4 downto 0);
signal col_b_reg_421 : STD_LOGIC_VECTOR (4 downto 0);
signal reg_711 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_pp0_stage5 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage5 : signal is "none";
signal ap_enable_reg_pp0_iter0 : STD_LOGIC := '0';
signal ap_block_state7_pp0_stage5_iter0 : BOOLEAN;
signal ap_block_state23_pp0_stage5_iter1 : BOOLEAN;
signal ap_block_state39_pp0_stage5_iter2 : BOOLEAN;
signal ap_block_state55_pp0_stage5_iter3 : BOOLEAN;
signal ap_block_state71_pp0_stage5_iter4 : BOOLEAN;
signal ap_block_state87_pp0_stage5_iter5 : BOOLEAN;
signal ap_block_state103_pp0_stage5_iter6 : BOOLEAN;
signal ap_block_state119_pp0_stage5_iter7 : BOOLEAN;
signal ap_block_state135_pp0_stage5_iter8 : BOOLEAN;
signal ap_block_state151_pp0_stage5_iter9 : BOOLEAN;
signal ap_block_pp0_stage5_flag00011001 : BOOLEAN;
signal exitcond_flatten2_reg_3675 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage9 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage9 : signal is "none";
signal ap_block_state11_pp0_stage9_iter0 : BOOLEAN;
signal ap_block_state27_pp0_stage9_iter1 : BOOLEAN;
signal ap_block_state43_pp0_stage9_iter2 : BOOLEAN;
signal ap_block_state59_pp0_stage9_iter3 : BOOLEAN;
signal ap_block_state75_pp0_stage9_iter4 : BOOLEAN;
signal ap_block_state91_pp0_stage9_iter5 : BOOLEAN;
signal ap_block_state107_pp0_stage9_iter6 : BOOLEAN;
signal ap_block_state123_pp0_stage9_iter7 : BOOLEAN;
signal ap_block_state139_pp0_stage9_iter8 : BOOLEAN;
signal ap_block_state155_pp0_stage9_iter9 : BOOLEAN;
signal ap_block_pp0_stage9_flag00011001 : BOOLEAN;
signal ap_CS_fsm_pp0_stage13 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage13 : signal is "none";
signal ap_block_state15_pp0_stage13_iter0 : BOOLEAN;
signal ap_block_state31_pp0_stage13_iter1 : BOOLEAN;
signal ap_block_state47_pp0_stage13_iter2 : BOOLEAN;
signal ap_block_state63_pp0_stage13_iter3 : BOOLEAN;
signal ap_block_state79_pp0_stage13_iter4 : BOOLEAN;
signal ap_block_state95_pp0_stage13_iter5 : BOOLEAN;
signal ap_block_state111_pp0_stage13_iter6 : BOOLEAN;
signal ap_block_state127_pp0_stage13_iter7 : BOOLEAN;
signal ap_block_state143_pp0_stage13_iter8 : BOOLEAN;
signal ap_block_state159_pp0_stage13_iter9 : BOOLEAN;
signal ap_block_pp0_stage13_flag00011001 : BOOLEAN;
signal reg_715 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_719 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_723 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_727 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_731 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_735 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_739 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_743 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_747 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_751 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_755 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_759 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_763 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_767 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_771 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_pp0_stage6 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage6 : signal is "none";
signal ap_block_state8_pp0_stage6_iter0 : BOOLEAN;
signal ap_block_state24_pp0_stage6_iter1 : BOOLEAN;
signal ap_block_state40_pp0_stage6_iter2 : BOOLEAN;
signal ap_block_state56_pp0_stage6_iter3 : BOOLEAN;
signal ap_block_state72_pp0_stage6_iter4 : BOOLEAN;
signal ap_block_state88_pp0_stage6_iter5 : BOOLEAN;
signal ap_block_state104_pp0_stage6_iter6 : BOOLEAN;
signal ap_block_state120_pp0_stage6_iter7 : BOOLEAN;
signal ap_block_state136_pp0_stage6_iter8 : BOOLEAN;
signal ap_block_state152_pp0_stage6_iter9 : BOOLEAN;
signal ap_block_pp0_stage6_flag00011001 : BOOLEAN;
signal ap_CS_fsm_pp0_stage10 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage10 : signal is "none";
signal ap_block_state12_pp0_stage10_iter0 : BOOLEAN;
signal ap_block_state28_pp0_stage10_iter1 : BOOLEAN;
signal ap_block_state44_pp0_stage10_iter2 : BOOLEAN;
signal ap_block_state60_pp0_stage10_iter3 : BOOLEAN;
signal ap_block_state76_pp0_stage10_iter4 : BOOLEAN;
signal ap_block_state92_pp0_stage10_iter5 : BOOLEAN;
signal ap_block_state108_pp0_stage10_iter6 : BOOLEAN;
signal ap_block_state124_pp0_stage10_iter7 : BOOLEAN;
signal ap_block_state140_pp0_stage10_iter8 : BOOLEAN;
signal ap_block_state156_pp0_stage10_iter9 : BOOLEAN;
signal ap_block_pp0_stage10_flag00011001 : BOOLEAN;
signal ap_CS_fsm_pp0_stage14 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage14 : signal is "none";
signal ap_block_state16_pp0_stage14_iter0 : BOOLEAN;
signal ap_block_state32_pp0_stage14_iter1 : BOOLEAN;
signal ap_block_state48_pp0_stage14_iter2 : BOOLEAN;
signal ap_block_state64_pp0_stage14_iter3 : BOOLEAN;
signal ap_block_state80_pp0_stage14_iter4 : BOOLEAN;
signal ap_block_state96_pp0_stage14_iter5 : BOOLEAN;
signal ap_block_state112_pp0_stage14_iter6 : BOOLEAN;
signal ap_block_state128_pp0_stage14_iter7 : BOOLEAN;
signal ap_block_state144_pp0_stage14_iter8 : BOOLEAN;
signal ap_block_state160_pp0_stage14_iter9 : BOOLEAN;
signal ap_block_pp0_stage14_flag00011001 : BOOLEAN;
signal reg_775 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_779 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_783 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_787 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_791 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_795 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_799 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_803 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_807 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_811 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_815 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_819 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_823 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_827 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_831 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_pp0_stage7 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage7 : signal is "none";
signal ap_block_state9_pp0_stage7_iter0 : BOOLEAN;
signal ap_block_state25_pp0_stage7_iter1 : BOOLEAN;
signal ap_block_state41_pp0_stage7_iter2 : BOOLEAN;
signal ap_block_state57_pp0_stage7_iter3 : BOOLEAN;
signal ap_block_state73_pp0_stage7_iter4 : BOOLEAN;
signal ap_block_state89_pp0_stage7_iter5 : BOOLEAN;
signal ap_block_state105_pp0_stage7_iter6 : BOOLEAN;
signal ap_block_state121_pp0_stage7_iter7 : BOOLEAN;
signal ap_block_state137_pp0_stage7_iter8 : BOOLEAN;
signal ap_block_state153_pp0_stage7_iter9 : BOOLEAN;
signal ap_block_pp0_stage7_flag00011001 : BOOLEAN;
signal ap_CS_fsm_pp0_stage11 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage11 : signal is "none";
signal ap_block_state13_pp0_stage11_iter0 : BOOLEAN;
signal ap_block_state29_pp0_stage11_iter1 : BOOLEAN;
signal ap_block_state45_pp0_stage11_iter2 : BOOLEAN;
signal ap_block_state61_pp0_stage11_iter3 : BOOLEAN;
signal ap_block_state77_pp0_stage11_iter4 : BOOLEAN;
signal ap_block_state93_pp0_stage11_iter5 : BOOLEAN;
signal ap_block_state109_pp0_stage11_iter6 : BOOLEAN;
signal ap_block_state125_pp0_stage11_iter7 : BOOLEAN;
signal ap_block_state141_pp0_stage11_iter8 : BOOLEAN;
signal ap_block_state157_pp0_stage11_iter9 : BOOLEAN;
signal ap_block_pp0_stage11_flag00011001 : BOOLEAN;
signal ap_CS_fsm_pp0_stage15 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage15 : signal is "none";
signal ap_block_state17_pp0_stage15_iter0 : BOOLEAN;
signal ap_block_state33_pp0_stage15_iter1 : BOOLEAN;
signal ap_block_state49_pp0_stage15_iter2 : BOOLEAN;
signal ap_block_state65_pp0_stage15_iter3 : BOOLEAN;
signal ap_block_state81_pp0_stage15_iter4 : BOOLEAN;
signal ap_block_state97_pp0_stage15_iter5 : BOOLEAN;
signal ap_block_state113_pp0_stage15_iter6 : BOOLEAN;
signal ap_block_state129_pp0_stage15_iter7 : BOOLEAN;
signal ap_block_state145_pp0_stage15_iter8 : BOOLEAN;
signal ap_block_pp0_stage15_flag00011001 : BOOLEAN;
signal reg_835 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_839 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_843 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_847 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_851 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_855 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_859 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_863 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_867 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_871 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_875 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_879 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_883 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_887 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_891 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_pp0_stage8 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage8 : signal is "none";
signal ap_block_state10_pp0_stage8_iter0 : BOOLEAN;
signal ap_block_state26_pp0_stage8_iter1 : BOOLEAN;
signal ap_block_state42_pp0_stage8_iter2 : BOOLEAN;
signal ap_block_state58_pp0_stage8_iter3 : BOOLEAN;
signal ap_block_state74_pp0_stage8_iter4 : BOOLEAN;
signal ap_block_state90_pp0_stage8_iter5 : BOOLEAN;
signal ap_block_state106_pp0_stage8_iter6 : BOOLEAN;
signal ap_block_state122_pp0_stage8_iter7 : BOOLEAN;
signal ap_block_state138_pp0_stage8_iter8 : BOOLEAN;
signal ap_block_state154_pp0_stage8_iter9 : BOOLEAN;
signal ap_block_pp0_stage8_flag00011001 : BOOLEAN;
signal ap_CS_fsm_pp0_stage12 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage12 : signal is "none";
signal ap_block_state14_pp0_stage12_iter0 : BOOLEAN;
signal ap_block_state30_pp0_stage12_iter1 : BOOLEAN;
signal ap_block_state46_pp0_stage12_iter2 : BOOLEAN;
signal ap_block_state62_pp0_stage12_iter3 : BOOLEAN;
signal ap_block_state78_pp0_stage12_iter4 : BOOLEAN;
signal ap_block_state94_pp0_stage12_iter5 : BOOLEAN;
signal ap_block_state110_pp0_stage12_iter6 : BOOLEAN;
signal ap_block_state126_pp0_stage12_iter7 : BOOLEAN;
signal ap_block_state142_pp0_stage12_iter8 : BOOLEAN;
signal ap_block_state158_pp0_stage12_iter9 : BOOLEAN;
signal ap_block_pp0_stage12_flag00011001 : BOOLEAN;
signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
signal ap_block_state2_pp0_stage0_iter0 : BOOLEAN;
signal ap_block_state18_pp0_stage0_iter1 : BOOLEAN;
signal ap_block_state34_pp0_stage0_iter2 : BOOLEAN;
signal ap_block_state50_pp0_stage0_iter3 : BOOLEAN;
signal ap_block_state66_pp0_stage0_iter4 : BOOLEAN;
signal ap_block_state82_pp0_stage0_iter5 : BOOLEAN;
signal ap_block_state98_pp0_stage0_iter6 : BOOLEAN;
signal ap_block_state114_pp0_stage0_iter7 : BOOLEAN;
signal ap_block_state130_pp0_stage0_iter8 : BOOLEAN;
signal ap_block_state146_pp0_stage0_iter9 : BOOLEAN;
signal ap_block_pp0_stage0_flag00011001 : BOOLEAN;
signal reg_895 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_899 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_903 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_907 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_911 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_915 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_919 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_923 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_927 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_931 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_935 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_939 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_943 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_947 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_433_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_951 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter1_exitcond_flatten2_reg_3675 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_enable_reg_pp0_iter9 : STD_LOGIC := '0';
signal ap_reg_pp0_iter9_exitcond_flatten2_reg_3675 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_fu_437_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_956 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_441_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_961 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_445_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_966 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_449_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_971 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_453_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_976 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_457_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_981 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_461_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_986 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_465_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_991 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_469_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_996 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_473_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_1001 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_477_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_1006 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_481_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_1011 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_485_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_1016 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_489_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_1021 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_493_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_1026 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_8_fu_1045_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_8_reg_3670 : STD_LOGIC_VECTOR (5 downto 0);
signal exitcond_flatten2_fu_1051_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter2_exitcond_flatten2_reg_3675 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter3_exitcond_flatten2_reg_3675 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter4_exitcond_flatten2_reg_3675 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter5_exitcond_flatten2_reg_3675 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter6_exitcond_flatten2_reg_3675 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter7_exitcond_flatten2_reg_3675 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter8_exitcond_flatten2_reg_3675 : STD_LOGIC_VECTOR (0 downto 0);
signal indvar_flatten_next2_fu_1057_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal indvar_flatten_next2_reg_3679 : STD_LOGIC_VECTOR (12 downto 0);
signal exitcond_flatten_fu_1063_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond_flatten_reg_3684 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_35_fu_1069_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_35_reg_3696 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond_flatten1_fu_1075_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond_flatten1_reg_3701 : STD_LOGIC_VECTOR (0 downto 0);
signal indvar_flatten40_op_fu_1081_p2 : STD_LOGIC_VECTOR (11 downto 0);
signal indvar_flatten40_op_reg_3707 : STD_LOGIC_VECTOR (11 downto 0);
signal i_1_fu_1087_p2 : STD_LOGIC_VECTOR (2 downto 0);
signal i_1_reg_3712 : STD_LOGIC_VECTOR (2 downto 0);
signal ap_CS_fsm_pp0_stage1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage1 : signal is "none";
signal ap_block_state3_pp0_stage1_iter0 : BOOLEAN;
signal ap_block_state19_pp0_stage1_iter1 : BOOLEAN;
signal ap_block_state35_pp0_stage1_iter2 : BOOLEAN;
signal ap_block_state51_pp0_stage1_iter3 : BOOLEAN;
signal ap_block_state67_pp0_stage1_iter4 : BOOLEAN;
signal ap_block_state83_pp0_stage1_iter5 : BOOLEAN;
signal ap_block_state99_pp0_stage1_iter6 : BOOLEAN;
signal ap_block_state115_pp0_stage1_iter7 : BOOLEAN;
signal ap_block_state131_pp0_stage1_iter8 : BOOLEAN;
signal ap_block_state147_pp0_stage1_iter9 : BOOLEAN;
signal ap_block_pp0_stage1_flag00011001 : BOOLEAN;
signal j_mid_fu_1093_p3 : STD_LOGIC_VECTOR (2 downto 0);
signal j_mid_reg_3717 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_1_mid2_v_fu_1100_p3 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_1_mid2_v_reg_3722 : STD_LOGIC_VECTOR (2 downto 0);
signal exitcond_flatten_mid_fu_1117_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond_flatten_mid_reg_3731 : STD_LOGIC_VECTOR (0 downto 0);
signal j_1_fu_1122_p2 : STD_LOGIC_VECTOR (2 downto 0);
signal j_1_reg_3739 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_9_mid1_fu_1138_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_9_mid1_reg_3744 : STD_LOGIC_VECTOR (0 downto 0);
signal indvar_flatten_op_fu_1144_p2 : STD_LOGIC_VECTOR (9 downto 0);
signal indvar_flatten_op_reg_3752 : STD_LOGIC_VECTOR (9 downto 0);
signal indvar_flatten_next1_fu_1150_p3 : STD_LOGIC_VECTOR (11 downto 0);
signal indvar_flatten_next1_reg_3757 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_1_mid2_cast_fu_1156_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_1_mid2_cast_reg_3762 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_CS_fsm_pp0_stage2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage2 : signal is "none";
signal ap_block_state4_pp0_stage2_iter0 : BOOLEAN;
signal ap_block_state20_pp0_stage2_iter1 : BOOLEAN;
signal ap_block_state36_pp0_stage2_iter2 : BOOLEAN;
signal ap_block_state52_pp0_stage2_iter3 : BOOLEAN;
signal ap_block_state68_pp0_stage2_iter4 : BOOLEAN;
signal ap_block_state84_pp0_stage2_iter5 : BOOLEAN;
signal ap_block_state100_pp0_stage2_iter6 : BOOLEAN;
signal ap_block_state116_pp0_stage2_iter7 : BOOLEAN;
signal ap_block_state132_pp0_stage2_iter8 : BOOLEAN;
signal ap_block_state148_pp0_stage2_iter9 : BOOLEAN;
signal ap_block_pp0_stage2_flag00011001 : BOOLEAN;
signal tmp_2_fu_1170_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_2_reg_3767 : STD_LOGIC_VECTOR (5 downto 0);
signal row_b_mid_fu_1211_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal row_b_mid_reg_3776 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_4_mid2_fu_1219_p3 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_4_mid2_reg_3783 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_75_fu_1228_p2 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_75_reg_3792 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_8_cast_mid5_fu_1234_p3 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_8_cast_mid5_reg_3797 : STD_LOGIC_VECTOR (5 downto 0);
signal col_b_mid2_fu_1250_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal col_b_mid2_reg_3802 : STD_LOGIC_VECTOR (4 downto 0);
signal indvar_flatten_next_fu_1258_p3 : STD_LOGIC_VECTOR (9 downto 0);
signal indvar_flatten_next_reg_3809 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_5_fu_1265_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_5_reg_3814 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_CS_fsm_pp0_stage3 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage3 : signal is "none";
signal ap_block_state5_pp0_stage3_iter0 : BOOLEAN;
signal ap_block_state21_pp0_stage3_iter1 : BOOLEAN;
signal ap_block_state37_pp0_stage3_iter2 : BOOLEAN;
signal ap_block_state53_pp0_stage3_iter3 : BOOLEAN;
signal ap_block_state69_pp0_stage3_iter4 : BOOLEAN;
signal ap_block_state85_pp0_stage3_iter5 : BOOLEAN;
signal ap_block_state101_pp0_stage3_iter6 : BOOLEAN;
signal ap_block_state117_pp0_stage3_iter7 : BOOLEAN;
signal ap_block_state133_pp0_stage3_iter8 : BOOLEAN;
signal ap_block_state149_pp0_stage3_iter9 : BOOLEAN;
signal ap_block_pp0_stage3_flag00011001 : BOOLEAN;
signal tmp_4_mid2_cast_fu_1270_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_4_mid2_cast_reg_3819 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_43_fu_1273_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_43_reg_3824 : STD_LOGIC_VECTOR (5 downto 0);
signal row_b_1_fu_1282_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal row_b_1_reg_3834 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_4_mid2_cast4_fu_1290_p1 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_4_mid2_cast4_reg_3841 : STD_LOGIC_VECTOR (6 downto 0);
signal ap_CS_fsm_pp0_stage4 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage4 : signal is "none";
signal ap_block_state6_pp0_stage4_iter0 : BOOLEAN;
signal ap_block_state22_pp0_stage4_iter1 : BOOLEAN;
signal ap_block_state38_pp0_stage4_iter2 : BOOLEAN;
signal ap_block_state54_pp0_stage4_iter3 : BOOLEAN;
signal ap_block_state70_pp0_stage4_iter4 : BOOLEAN;
signal ap_block_state86_pp0_stage4_iter5 : BOOLEAN;
signal ap_block_state102_pp0_stage4_iter6 : BOOLEAN;
signal ap_block_state118_pp0_stage4_iter7 : BOOLEAN;
signal ap_block_state134_pp0_stage4_iter8 : BOOLEAN;
signal ap_block_state150_pp0_stage4_iter9 : BOOLEAN;
signal ap_block_pp0_stage4_flag00011001 : BOOLEAN;
signal tmp_47_fu_1297_p2 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_47_reg_3852 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_8_mid1_fu_1329_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_8_mid1_reg_3857 : STD_LOGIC_VECTOR (5 downto 0);
signal row_b_mid2_fu_1334_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal row_b_mid2_reg_3862 : STD_LOGIC_VECTOR (4 downto 0);
signal bufo_addr_reg_3867 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter1_bufo_addr_reg_3867 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter2_bufo_addr_reg_3867 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter3_bufo_addr_reg_3867 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter4_bufo_addr_reg_3867 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter5_bufo_addr_reg_3867 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter6_bufo_addr_reg_3867 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter7_bufo_addr_reg_3867 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter8_bufo_addr_reg_3867 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter9_bufo_addr_reg_3867 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_3_fu_1362_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_3_reg_3872 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_635_fu_1367_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_635_reg_3877 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_98_reg_3882 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_134_reg_3887 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_169_reg_3892 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_204_reg_3897 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_239_reg_3902 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_274_reg_3907 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_309_reg_3912 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_344_reg_3917 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_379_reg_3922 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_414_reg_3927 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_449_reg_3932 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_484_reg_3937 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_519_reg_3942 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_554_reg_3947 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_589_reg_3952 : STD_LOGIC_VECTOR (31 downto 0);
signal col_b_1_fu_1371_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal col_b_1_reg_3957 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_51_fu_1395_p2 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_51_reg_3967 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_55_fu_1400_p2 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_55_reg_3972 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_8_cast_mid2_fu_1405_p3 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_8_cast_mid2_reg_3977 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_625_fu_1410_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_625_reg_3983 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_624_fu_1449_p2 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_624_reg_3993 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_627_fu_1455_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_627_reg_3998 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_628_fu_1459_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_628_reg_4003 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_82_reg_4008 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_118_reg_4013 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_153_reg_4018 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_188_reg_4023 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_223_reg_4028 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_258_reg_4033 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_293_reg_4038 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_328_reg_4043 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_363_reg_4048 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_398_reg_4053 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_433_reg_4058 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_468_reg_4063 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_503_reg_4068 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_538_reg_4073 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_573_reg_4078 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_2_cast2_fu_1613_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_2_cast2_reg_4083 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_4_mid2_cast3_fu_1622_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_4_mid2_cast3_reg_4090 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_59_fu_1629_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_59_reg_4102 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_629_fu_1639_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_629_reg_4112 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_63_fu_1652_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_63_reg_4122 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_626_fu_1657_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_626_reg_4127 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_21_reg_4132 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_25_reg_4137 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_630_fu_1681_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_630_reg_4142 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_29_reg_4147 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_33_reg_4152 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_37_reg_4157 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_41_reg_4162 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_45_reg_4167 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_49_reg_4172 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_53_reg_4177 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_57_reg_4182 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_61_reg_4187 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_65_reg_4192 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_69_reg_4197 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_73_reg_4202 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_77_reg_4207 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_67_fu_1829_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_67_reg_4217 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_71_fu_1834_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_71_reg_4222 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_14_fu_1839_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_16_fu_1843_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_631_fu_1862_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_631_reg_4252 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_81_fu_1866_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_117_fu_1871_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_152_fu_1876_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_187_fu_1881_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_222_fu_1886_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_257_fu_1891_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_292_fu_1896_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_327_fu_1901_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_362_fu_1906_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_397_fu_1911_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_432_fu_1916_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_467_fu_1921_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_502_fu_1926_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_537_fu_1931_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_572_fu_1936_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_fu_1945_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_22_fu_1949_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_632_fu_1968_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_632_reg_4362 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_85_fu_1972_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_121_fu_1977_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_156_fu_1982_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_191_fu_1987_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_226_fu_1992_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_261_fu_1997_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_296_fu_2002_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_331_fu_2007_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_366_fu_2012_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_401_fu_2017_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_436_fu_2022_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_471_fu_2027_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_506_fu_2032_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_541_fu_2037_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_576_fu_2042_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_2_cast1_fu_2047_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_2_cast1_reg_4442 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_4_mid2_cast1_fu_2056_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_4_mid2_cast1_reg_4452 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_608_fu_2063_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_608_reg_4467 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_24_fu_2069_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_26_fu_2073_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_633_fu_2092_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_633_reg_4497 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_87_fu_2096_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_123_fu_2101_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_158_fu_2106_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_193_fu_2111_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_228_fu_2116_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_263_fu_2121_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_298_fu_2126_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_333_fu_2131_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_368_fu_2136_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_403_fu_2141_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_438_fu_2146_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_473_fu_2151_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_508_fu_2156_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_543_fu_2161_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_578_fu_2166_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_609_fu_2180_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_609_reg_4582 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_28_fu_2185_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_30_fu_2189_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_634_fu_2208_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_634_reg_4612 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_89_fu_2212_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_125_fu_2217_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_160_fu_2222_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_195_fu_2227_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_230_fu_2232_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_265_fu_2237_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_300_fu_2242_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_335_fu_2247_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_370_fu_2252_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_405_fu_2257_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_440_fu_2262_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_475_fu_2267_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_510_fu_2272_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_545_fu_2277_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_580_fu_2282_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_610_fu_2296_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_610_reg_4697 : STD_LOGIC_VECTOR (8 downto 0);
signal grp_fu_497_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_116_reg_4702 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_32_fu_2301_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_34_fu_2305_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_636_fu_2324_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_636_reg_4732 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_501_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_1_reg_4737 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_91_fu_2328_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_505_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_2_reg_4747 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_127_fu_2333_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_509_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_3_reg_4757 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_162_fu_2338_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_513_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_4_reg_4767 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_197_fu_2343_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_517_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_5_reg_4777 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_232_fu_2348_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_521_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_6_reg_4787 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_267_fu_2353_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_525_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_7_reg_4797 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_302_fu_2358_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_529_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_8_reg_4807 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_337_fu_2363_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_533_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_9_reg_4817 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_372_fu_2368_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_537_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_s_reg_4827 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_407_fu_2373_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_541_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_10_reg_4837 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_442_fu_2378_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_545_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_11_reg_4847 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_477_fu_2383_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_549_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_12_reg_4857 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_512_fu_2388_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_553_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_13_reg_4867 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_547_fu_2393_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_557_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_14_reg_4877 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_582_fu_2398_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_611_fu_2412_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_611_reg_4892 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_18_fu_2417_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_0_1_reg_4902 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_36_fu_2421_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_38_fu_2425_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_637_fu_2444_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_637_reg_4932 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_83_fu_2448_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_1_1_reg_4942 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_93_fu_2452_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_119_fu_2457_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_2_1_reg_4957 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_129_fu_2461_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_154_fu_2466_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_3_1_reg_4972 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_164_fu_2470_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_189_fu_2475_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_4_1_reg_4987 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_199_fu_2479_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_224_fu_2484_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_5_1_reg_5002 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_234_fu_2488_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_259_fu_2493_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_6_1_reg_5017 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_269_fu_2497_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_294_fu_2502_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_7_1_reg_5032 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_304_fu_2506_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_329_fu_2511_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_8_1_reg_5047 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_339_fu_2515_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_364_fu_2520_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_9_1_reg_5062 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_374_fu_2524_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_399_fu_2529_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_10_1_reg_5077 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_409_fu_2533_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_434_fu_2538_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_11_1_reg_5092 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_444_fu_2542_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_469_fu_2547_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_12_1_reg_5107 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_479_fu_2551_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_504_fu_2556_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_13_1_reg_5122 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_514_fu_2560_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_539_fu_2565_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_14_1_reg_5137 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_549_fu_2569_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_574_fu_2574_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_15_1_reg_5152 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_584_fu_2578_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_612_fu_2592_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_612_reg_5167 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_11_0_2_reg_5172 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter1_tmp_11_0_2_reg_5172 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_40_fu_2597_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_42_fu_2601_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_638_fu_2620_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_638_reg_5202 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_1_2_reg_5207 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter1_tmp_11_1_2_reg_5207 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_95_fu_2624_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_2_2_reg_5217 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter1_tmp_11_2_2_reg_5217 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_131_fu_2629_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_3_2_reg_5227 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter1_tmp_11_3_2_reg_5227 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_166_fu_2634_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_4_2_reg_5237 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter1_tmp_11_4_2_reg_5237 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_201_fu_2639_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_5_2_reg_5247 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter1_tmp_11_5_2_reg_5247 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_236_fu_2644_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_6_2_reg_5257 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter1_tmp_11_6_2_reg_5257 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_271_fu_2649_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_7_2_reg_5267 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter1_tmp_11_7_2_reg_5267 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_306_fu_2654_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_8_2_reg_5277 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter1_tmp_11_8_2_reg_5277 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_341_fu_2659_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_9_2_reg_5287 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter1_tmp_11_9_2_reg_5287 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_376_fu_2664_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_10_2_reg_5297 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter1_tmp_11_10_2_reg_5297 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_411_fu_2669_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_11_2_reg_5307 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter1_tmp_11_11_2_reg_5307 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_446_fu_2674_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_12_2_reg_5317 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter1_tmp_11_12_2_reg_5317 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_481_fu_2679_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_13_2_reg_5327 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter1_tmp_11_13_2_reg_5327 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_516_fu_2684_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_14_2_reg_5337 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter1_tmp_11_14_2_reg_5337 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_551_fu_2689_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_15_2_reg_5347 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter1_tmp_11_15_2_reg_5347 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_586_fu_2694_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_613_fu_2713_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_613_reg_5362 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_614_fu_2718_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_614_reg_5367 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_11_0_3_reg_5372 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_0_3_reg_5372 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_44_fu_2723_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_46_fu_2727_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_639_fu_2746_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_639_reg_5402 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_1_3_reg_5407 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_1_3_reg_5407 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_97_fu_2750_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_2_3_reg_5417 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_2_3_reg_5417 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_133_fu_2755_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_3_3_reg_5427 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_3_3_reg_5427 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_168_fu_2760_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_4_3_reg_5437 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_4_3_reg_5437 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_203_fu_2765_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_5_3_reg_5447 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_5_3_reg_5447 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_238_fu_2770_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_6_3_reg_5457 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_6_3_reg_5457 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_273_fu_2775_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_7_3_reg_5467 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_7_3_reg_5467 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_308_fu_2780_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_8_3_reg_5477 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_8_3_reg_5477 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_343_fu_2785_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_9_3_reg_5487 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_9_3_reg_5487 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_378_fu_2790_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_10_3_reg_5497 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_10_3_reg_5497 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_413_fu_2795_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_11_3_reg_5507 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_11_3_reg_5507 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_448_fu_2800_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_12_3_reg_5517 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_12_3_reg_5517 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_483_fu_2805_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_13_3_reg_5527 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_13_3_reg_5527 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_518_fu_2810_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_14_3_reg_5537 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_14_3_reg_5537 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_553_fu_2815_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_15_3_reg_5547 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_15_3_reg_5547 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_588_fu_2820_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_0_4_reg_5562 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_0_4_reg_5562 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_0_4_reg_5562 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_48_fu_2829_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_50_fu_2833_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_640_fu_2852_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_640_reg_5592 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_1_4_reg_5597 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_1_4_reg_5597 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_1_4_reg_5597 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_99_fu_2856_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_108_reg_5607 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_2_4_reg_5612 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_2_4_reg_5612 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_2_4_reg_5612 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_135_fu_2860_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_144_reg_5622 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_3_4_reg_5627 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_3_4_reg_5627 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_3_4_reg_5627 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_170_fu_2864_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_179_reg_5637 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_4_4_reg_5642 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_4_4_reg_5642 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_4_4_reg_5642 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_205_fu_2868_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_214_reg_5652 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_5_4_reg_5657 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_5_4_reg_5657 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_5_4_reg_5657 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_240_fu_2872_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_249_reg_5667 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_6_4_reg_5672 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_6_4_reg_5672 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_6_4_reg_5672 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_275_fu_2876_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_284_reg_5682 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_7_4_reg_5687 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_7_4_reg_5687 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_7_4_reg_5687 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_310_fu_2880_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_319_reg_5697 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_8_4_reg_5702 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_8_4_reg_5702 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_8_4_reg_5702 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_345_fu_2884_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_354_reg_5712 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_9_4_reg_5717 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_9_4_reg_5717 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_9_4_reg_5717 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_380_fu_2888_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_389_reg_5727 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_10_4_reg_5732 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_10_4_reg_5732 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_10_4_reg_5732 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_415_fu_2892_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_424_reg_5742 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_11_4_reg_5747 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_11_4_reg_5747 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_11_4_reg_5747 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_450_fu_2896_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_459_reg_5757 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_12_4_reg_5762 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_12_4_reg_5762 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_12_4_reg_5762 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_485_fu_2900_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_494_reg_5772 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_13_4_reg_5777 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_13_4_reg_5777 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_13_4_reg_5777 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_520_fu_2904_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_529_reg_5787 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_14_4_reg_5792 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_14_4_reg_5792 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_14_4_reg_5792 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_555_fu_2908_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_564_reg_5802 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_15_4_reg_5807 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_15_4_reg_5807 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_15_4_reg_5807 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_590_fu_2912_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_599_reg_5817 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_0_5_reg_5827 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_0_5_reg_5827 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_0_5_reg_5827 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_52_fu_2920_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_54_fu_2924_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_641_fu_2943_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_641_reg_5857 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_1_5_reg_5862 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_1_5_reg_5862 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_1_5_reg_5862 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_101_fu_2947_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_110_reg_5872 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_2_5_reg_5877 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_2_5_reg_5877 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_2_5_reg_5877 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_137_fu_2952_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_146_reg_5887 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_3_5_reg_5892 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_3_5_reg_5892 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_3_5_reg_5892 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_172_fu_2957_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_181_reg_5902 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_4_5_reg_5907 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_4_5_reg_5907 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_4_5_reg_5907 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_207_fu_2962_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_216_reg_5917 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_5_5_reg_5922 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_5_5_reg_5922 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_5_5_reg_5922 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_242_fu_2967_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_251_reg_5932 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_6_5_reg_5937 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_6_5_reg_5937 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_6_5_reg_5937 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_277_fu_2972_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_286_reg_5947 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_7_5_reg_5952 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_7_5_reg_5952 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_7_5_reg_5952 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_312_fu_2977_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_321_reg_5962 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_8_5_reg_5967 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_8_5_reg_5967 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_8_5_reg_5967 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_347_fu_2982_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_356_reg_5977 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_9_5_reg_5982 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_9_5_reg_5982 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_9_5_reg_5982 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_382_fu_2987_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_391_reg_5992 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_10_5_reg_5997 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_10_5_reg_5997 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_10_5_reg_5997 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_417_fu_2992_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_426_reg_6007 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_11_5_reg_6012 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_11_5_reg_6012 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_11_5_reg_6012 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_452_fu_2997_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_461_reg_6022 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_12_5_reg_6027 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_12_5_reg_6027 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_12_5_reg_6027 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_487_fu_3002_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_496_reg_6037 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_13_5_reg_6042 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_13_5_reg_6042 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_13_5_reg_6042 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_522_fu_3007_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_531_reg_6052 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_14_5_reg_6057 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_14_5_reg_6057 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_14_5_reg_6057 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_557_fu_3012_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_566_reg_6067 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_15_5_reg_6072 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_15_5_reg_6072 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_15_5_reg_6072 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_592_fu_3017_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_601_reg_6082 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_0_6_reg_6087 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_0_6_reg_6087 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_0_6_reg_6087 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_0_6_reg_6087 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_56_fu_3022_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_58_fu_3026_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_642_fu_3045_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_642_reg_6117 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_1_6_reg_6122 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_1_6_reg_6122 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_1_6_reg_6122 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_1_6_reg_6122 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_103_fu_3049_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_112_reg_6132 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_2_6_reg_6137 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_2_6_reg_6137 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_2_6_reg_6137 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_2_6_reg_6137 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_139_fu_3054_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_148_reg_6147 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_3_6_reg_6152 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_3_6_reg_6152 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_3_6_reg_6152 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_3_6_reg_6152 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_174_fu_3059_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_183_reg_6162 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_4_6_reg_6167 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_4_6_reg_6167 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_4_6_reg_6167 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_4_6_reg_6167 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_209_fu_3064_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_218_reg_6177 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_5_6_reg_6182 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_5_6_reg_6182 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_5_6_reg_6182 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_5_6_reg_6182 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_244_fu_3069_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_253_reg_6192 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_6_6_reg_6197 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_6_6_reg_6197 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_6_6_reg_6197 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_6_6_reg_6197 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_279_fu_3074_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_288_reg_6207 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_7_6_reg_6212 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_7_6_reg_6212 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_7_6_reg_6212 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_7_6_reg_6212 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_314_fu_3079_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_323_reg_6222 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_8_6_reg_6227 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_8_6_reg_6227 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_8_6_reg_6227 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_8_6_reg_6227 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_349_fu_3084_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_358_reg_6237 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_9_6_reg_6242 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_9_6_reg_6242 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_9_6_reg_6242 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_9_6_reg_6242 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_384_fu_3089_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_393_reg_6252 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_10_6_reg_6257 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_10_6_reg_6257 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_10_6_reg_6257 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_10_6_reg_6257 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_419_fu_3094_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_428_reg_6267 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_11_6_reg_6272 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_11_6_reg_6272 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_11_6_reg_6272 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_11_6_reg_6272 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_454_fu_3099_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_463_reg_6282 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_12_6_reg_6287 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_12_6_reg_6287 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_12_6_reg_6287 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_12_6_reg_6287 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_489_fu_3104_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_498_reg_6297 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_13_6_reg_6302 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_13_6_reg_6302 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_13_6_reg_6302 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_13_6_reg_6302 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_524_fu_3109_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_533_reg_6312 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_14_6_reg_6317 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_14_6_reg_6317 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_14_6_reg_6317 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_14_6_reg_6317 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_559_fu_3114_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_568_reg_6327 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_15_6_reg_6332 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_15_6_reg_6332 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_15_6_reg_6332 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_15_6_reg_6332 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_594_fu_3119_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_603_reg_6342 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_0_7_reg_6347 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_0_7_reg_6347 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_0_7_reg_6347 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_0_7_reg_6347 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_60_fu_3124_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_62_fu_3128_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_1_7_reg_6377 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_1_7_reg_6377 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_1_7_reg_6377 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_1_7_reg_6377 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_105_fu_3147_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_2_7_reg_6387 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_2_7_reg_6387 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_2_7_reg_6387 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_2_7_reg_6387 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_141_fu_3152_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_3_7_reg_6397 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_3_7_reg_6397 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_3_7_reg_6397 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_3_7_reg_6397 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_176_fu_3157_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_4_7_reg_6407 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_4_7_reg_6407 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_4_7_reg_6407 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_4_7_reg_6407 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_211_fu_3162_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_5_7_reg_6417 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_5_7_reg_6417 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_5_7_reg_6417 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_5_7_reg_6417 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_246_fu_3167_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_6_7_reg_6427 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_6_7_reg_6427 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_6_7_reg_6427 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_6_7_reg_6427 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_281_fu_3172_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_7_7_reg_6437 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_7_7_reg_6437 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_7_7_reg_6437 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_7_7_reg_6437 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_316_fu_3177_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_8_7_reg_6447 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_8_7_reg_6447 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_8_7_reg_6447 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_8_7_reg_6447 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_351_fu_3182_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_9_7_reg_6457 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_9_7_reg_6457 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_9_7_reg_6457 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_9_7_reg_6457 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_386_fu_3187_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_10_7_reg_6467 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_10_7_reg_6467 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_10_7_reg_6467 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_10_7_reg_6467 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_421_fu_3192_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_11_7_reg_6477 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_11_7_reg_6477 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_11_7_reg_6477 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_11_7_reg_6477 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_456_fu_3197_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_12_7_reg_6487 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_12_7_reg_6487 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_12_7_reg_6487 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_12_7_reg_6487 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_491_fu_3202_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_13_7_reg_6497 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_13_7_reg_6497 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_13_7_reg_6497 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_13_7_reg_6497 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_526_fu_3207_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_14_7_reg_6507 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_14_7_reg_6507 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_14_7_reg_6507 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_14_7_reg_6507 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_561_fu_3212_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_15_7_reg_6517 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_15_7_reg_6517 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_15_7_reg_6517 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_15_7_reg_6517 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_596_fu_3217_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_0_8_reg_6527 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_0_8_reg_6527 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_0_8_reg_6527 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_0_8_reg_6527 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_0_8_reg_6527 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_64_fu_3222_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_66_fu_3226_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_1_8_reg_6557 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_1_8_reg_6557 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_1_8_reg_6557 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_1_8_reg_6557 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_1_8_reg_6557 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_107_fu_3245_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_2_8_reg_6567 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_2_8_reg_6567 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_2_8_reg_6567 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_2_8_reg_6567 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_2_8_reg_6567 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_143_fu_3250_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_3_8_reg_6577 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_3_8_reg_6577 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_3_8_reg_6577 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_3_8_reg_6577 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_3_8_reg_6577 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_178_fu_3255_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_4_8_reg_6587 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_4_8_reg_6587 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_4_8_reg_6587 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_4_8_reg_6587 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_4_8_reg_6587 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_213_fu_3260_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_5_8_reg_6597 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_5_8_reg_6597 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_5_8_reg_6597 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_5_8_reg_6597 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_5_8_reg_6597 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_248_fu_3265_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_6_8_reg_6607 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_6_8_reg_6607 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_6_8_reg_6607 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_6_8_reg_6607 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_6_8_reg_6607 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_283_fu_3270_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_7_8_reg_6617 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_7_8_reg_6617 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_7_8_reg_6617 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_7_8_reg_6617 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_7_8_reg_6617 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_318_fu_3275_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_8_8_reg_6627 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_8_8_reg_6627 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_8_8_reg_6627 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_8_8_reg_6627 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_8_8_reg_6627 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_353_fu_3280_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_9_8_reg_6637 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_9_8_reg_6637 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_9_8_reg_6637 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_9_8_reg_6637 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_9_8_reg_6637 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_388_fu_3285_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_10_8_reg_6647 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_10_8_reg_6647 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_10_8_reg_6647 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_10_8_reg_6647 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_10_8_reg_6647 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_423_fu_3290_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_11_8_reg_6657 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_11_8_reg_6657 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_11_8_reg_6657 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_11_8_reg_6657 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_11_8_reg_6657 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_458_fu_3295_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_12_8_reg_6667 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_12_8_reg_6667 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_12_8_reg_6667 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_12_8_reg_6667 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_12_8_reg_6667 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_493_fu_3300_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_13_8_reg_6677 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_13_8_reg_6677 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_13_8_reg_6677 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_13_8_reg_6677 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_13_8_reg_6677 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_528_fu_3305_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_14_8_reg_6687 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_14_8_reg_6687 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_14_8_reg_6687 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_14_8_reg_6687 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_14_8_reg_6687 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_563_fu_3310_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_15_8_reg_6697 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_15_8_reg_6697 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_15_8_reg_6697 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_15_8_reg_6697 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_15_8_reg_6697 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_598_fu_3315_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_607_reg_6707 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_0_9_reg_6712 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_0_9_reg_6712 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_0_9_reg_6712 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_0_9_reg_6712 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_0_9_reg_6712 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_68_fu_3320_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_70_fu_3324_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_1_reg_6742 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_1_9_reg_6747 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_1_9_reg_6747 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_1_9_reg_6747 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_1_9_reg_6747 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_1_9_reg_6747 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_109_fu_3343_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_2_reg_6757 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_2_9_reg_6762 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_2_9_reg_6762 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_2_9_reg_6762 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_2_9_reg_6762 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_2_9_reg_6762 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_145_fu_3347_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_3_reg_6772 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_3_9_reg_6777 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_3_9_reg_6777 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_3_9_reg_6777 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_3_9_reg_6777 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_3_9_reg_6777 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_180_fu_3351_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_4_reg_6787 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_4_9_reg_6792 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_4_9_reg_6792 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_4_9_reg_6792 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_4_9_reg_6792 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_4_9_reg_6792 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_215_fu_3355_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_5_reg_6802 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_5_9_reg_6807 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_5_9_reg_6807 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_5_9_reg_6807 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_5_9_reg_6807 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_5_9_reg_6807 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_250_fu_3359_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_6_reg_6817 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_6_9_reg_6822 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_6_9_reg_6822 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_6_9_reg_6822 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_6_9_reg_6822 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_6_9_reg_6822 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_285_fu_3363_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_7_reg_6832 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_7_9_reg_6837 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_7_9_reg_6837 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_7_9_reg_6837 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_7_9_reg_6837 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_7_9_reg_6837 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_320_fu_3367_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_8_reg_6847 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_8_9_reg_6852 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_8_9_reg_6852 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_8_9_reg_6852 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_8_9_reg_6852 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_8_9_reg_6852 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_355_fu_3371_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_9_reg_6862 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_9_9_reg_6867 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_9_9_reg_6867 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_9_9_reg_6867 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_9_9_reg_6867 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_9_9_reg_6867 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_390_fu_3375_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_s_reg_6877 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_10_9_reg_6882 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_10_9_reg_6882 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_10_9_reg_6882 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_10_9_reg_6882 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_10_9_reg_6882 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_425_fu_3379_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_10_reg_6892 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_11_9_reg_6897 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_11_9_reg_6897 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_11_9_reg_6897 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_11_9_reg_6897 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_11_9_reg_6897 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_460_fu_3383_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_11_reg_6907 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_12_9_reg_6912 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_12_9_reg_6912 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_12_9_reg_6912 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_12_9_reg_6912 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_12_9_reg_6912 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_495_fu_3387_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_12_reg_6922 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_13_9_reg_6927 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_13_9_reg_6927 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_13_9_reg_6927 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_13_9_reg_6927 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_13_9_reg_6927 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_530_fu_3391_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_13_reg_6937 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_14_9_reg_6942 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_14_9_reg_6942 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_14_9_reg_6942 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_14_9_reg_6942 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_14_9_reg_6942 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_565_fu_3395_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_14_reg_6952 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_15_9_reg_6957 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_15_9_reg_6957 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_15_9_reg_6957 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_15_9_reg_6957 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_15_9_reg_6957 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_600_fu_3399_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_0_s_reg_6967 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_0_s_reg_6967 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_0_s_reg_6967 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_0_s_reg_6967 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_0_s_reg_6967 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_0_s_reg_6967 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_72_fu_3403_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_74_fu_3407_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_1_s_reg_6997 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_1_s_reg_6997 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_1_s_reg_6997 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_1_s_reg_6997 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_1_s_reg_6997 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_1_s_reg_6997 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_111_fu_3426_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_2_s_reg_7007 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_2_s_reg_7007 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_2_s_reg_7007 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_2_s_reg_7007 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_2_s_reg_7007 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_2_s_reg_7007 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_147_fu_3430_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_3_s_reg_7017 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_3_s_reg_7017 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_3_s_reg_7017 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_3_s_reg_7017 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_3_s_reg_7017 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_3_s_reg_7017 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_182_fu_3434_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_4_s_reg_7027 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_4_s_reg_7027 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_4_s_reg_7027 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_4_s_reg_7027 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_4_s_reg_7027 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_4_s_reg_7027 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_217_fu_3438_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_5_s_reg_7037 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_5_s_reg_7037 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_5_s_reg_7037 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_5_s_reg_7037 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_5_s_reg_7037 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_5_s_reg_7037 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_252_fu_3442_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_6_s_reg_7047 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_6_s_reg_7047 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_6_s_reg_7047 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_6_s_reg_7047 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_6_s_reg_7047 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_6_s_reg_7047 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_287_fu_3446_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_7_s_reg_7057 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_7_s_reg_7057 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_7_s_reg_7057 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_7_s_reg_7057 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_7_s_reg_7057 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_7_s_reg_7057 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_322_fu_3450_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_8_s_reg_7067 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_8_s_reg_7067 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_8_s_reg_7067 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_8_s_reg_7067 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_8_s_reg_7067 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_8_s_reg_7067 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_357_fu_3454_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_9_s_reg_7077 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_9_s_reg_7077 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_9_s_reg_7077 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_9_s_reg_7077 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_9_s_reg_7077 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_9_s_reg_7077 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_392_fu_3458_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_10_s_reg_7087 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_10_s_reg_7087 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_10_s_reg_7087 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_10_s_reg_7087 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_10_s_reg_7087 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_10_s_reg_7087 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_427_fu_3462_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_11_s_reg_7097 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_11_s_reg_7097 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_11_s_reg_7097 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_11_s_reg_7097 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_11_s_reg_7097 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_11_s_reg_7097 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_462_fu_3466_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_12_s_reg_7107 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_12_s_reg_7107 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_12_s_reg_7107 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_12_s_reg_7107 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_12_s_reg_7107 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_12_s_reg_7107 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_497_fu_3470_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_13_s_reg_7117 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_13_s_reg_7117 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_13_s_reg_7117 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_13_s_reg_7117 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_13_s_reg_7117 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_13_s_reg_7117 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_532_fu_3474_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_14_s_reg_7127 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_14_s_reg_7127 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_14_s_reg_7127 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_14_s_reg_7127 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_14_s_reg_7127 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_14_s_reg_7127 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_567_fu_3478_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_15_s_reg_7137 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_15_s_reg_7137 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_15_s_reg_7137 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_15_s_reg_7137 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_15_s_reg_7137 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_15_s_reg_7137 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_602_fu_3482_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_0_10_reg_7147 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_0_10_reg_7147 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_0_10_reg_7147 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_0_10_reg_7147 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_0_10_reg_7147 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_0_10_reg_7147 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_76_fu_3486_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_78_fu_3490_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_1_10_reg_7177 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_1_10_reg_7177 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_1_10_reg_7177 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_1_10_reg_7177 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_1_10_reg_7177 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_1_10_reg_7177 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_113_fu_3509_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_2_10_reg_7187 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_2_10_reg_7187 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_2_10_reg_7187 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_2_10_reg_7187 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_2_10_reg_7187 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_2_10_reg_7187 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_149_fu_3513_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_3_10_reg_7197 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_3_10_reg_7197 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_3_10_reg_7197 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_3_10_reg_7197 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_3_10_reg_7197 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_3_10_reg_7197 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_184_fu_3517_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_4_10_reg_7207 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_4_10_reg_7207 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_4_10_reg_7207 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_4_10_reg_7207 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_4_10_reg_7207 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_4_10_reg_7207 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_219_fu_3521_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_5_10_reg_7217 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_5_10_reg_7217 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_5_10_reg_7217 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_5_10_reg_7217 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_5_10_reg_7217 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_5_10_reg_7217 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_254_fu_3525_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_6_10_reg_7227 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_6_10_reg_7227 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_6_10_reg_7227 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_6_10_reg_7227 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_6_10_reg_7227 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_6_10_reg_7227 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_289_fu_3529_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_7_10_reg_7237 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_7_10_reg_7237 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_7_10_reg_7237 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_7_10_reg_7237 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_7_10_reg_7237 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_7_10_reg_7237 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_324_fu_3533_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_8_10_reg_7247 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_8_10_reg_7247 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_8_10_reg_7247 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_8_10_reg_7247 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_8_10_reg_7247 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_8_10_reg_7247 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_359_fu_3537_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_9_10_reg_7257 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_9_10_reg_7257 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_9_10_reg_7257 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_9_10_reg_7257 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_9_10_reg_7257 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_9_10_reg_7257 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_394_fu_3541_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_10_10_reg_7267 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_10_10_reg_7267 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_10_10_reg_7267 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_10_10_reg_7267 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_10_10_reg_7267 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_10_10_reg_7267 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_429_fu_3545_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_11_10_reg_7277 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_11_10_reg_7277 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_11_10_reg_7277 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_11_10_reg_7277 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_11_10_reg_7277 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_11_10_reg_7277 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_464_fu_3549_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_12_10_reg_7287 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_12_10_reg_7287 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_12_10_reg_7287 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_12_10_reg_7287 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_12_10_reg_7287 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_12_10_reg_7287 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_499_fu_3553_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_13_10_reg_7297 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_13_10_reg_7297 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_13_10_reg_7297 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_13_10_reg_7297 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_13_10_reg_7297 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_13_10_reg_7297 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_534_fu_3557_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_14_10_reg_7307 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_14_10_reg_7307 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_14_10_reg_7307 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_14_10_reg_7307 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_14_10_reg_7307 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_14_10_reg_7307 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_569_fu_3561_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_15_10_reg_7317 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_15_10_reg_7317 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_15_10_reg_7317 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_15_10_reg_7317 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_15_10_reg_7317 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_15_10_reg_7317 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_604_fu_3565_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_0_11_reg_7327 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_0_11_reg_7327 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_0_11_reg_7327 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_0_11_reg_7327 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_0_11_reg_7327 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_0_11_reg_7327 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_11_0_11_reg_7327 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_1_11_reg_7332 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_1_11_reg_7332 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_1_11_reg_7332 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_1_11_reg_7332 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_1_11_reg_7332 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_1_11_reg_7332 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_11_1_11_reg_7332 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_2_11_reg_7337 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_2_11_reg_7337 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_2_11_reg_7337 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_2_11_reg_7337 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_2_11_reg_7337 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_2_11_reg_7337 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_11_2_11_reg_7337 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_3_11_reg_7342 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_3_11_reg_7342 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_3_11_reg_7342 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_3_11_reg_7342 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_3_11_reg_7342 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_3_11_reg_7342 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_11_3_11_reg_7342 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_4_11_reg_7347 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_4_11_reg_7347 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_4_11_reg_7347 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_4_11_reg_7347 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_4_11_reg_7347 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_4_11_reg_7347 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_11_4_11_reg_7347 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_5_11_reg_7352 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_5_11_reg_7352 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_5_11_reg_7352 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_5_11_reg_7352 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_5_11_reg_7352 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_5_11_reg_7352 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_11_5_11_reg_7352 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_6_11_reg_7357 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_6_11_reg_7357 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_6_11_reg_7357 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_6_11_reg_7357 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_6_11_reg_7357 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_6_11_reg_7357 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_11_6_11_reg_7357 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_7_11_reg_7362 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_7_11_reg_7362 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_7_11_reg_7362 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_7_11_reg_7362 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_7_11_reg_7362 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_7_11_reg_7362 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_11_7_11_reg_7362 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_8_11_reg_7367 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_8_11_reg_7367 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_8_11_reg_7367 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_8_11_reg_7367 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_8_11_reg_7367 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_8_11_reg_7367 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_11_8_11_reg_7367 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_9_11_reg_7372 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_9_11_reg_7372 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_9_11_reg_7372 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_9_11_reg_7372 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_9_11_reg_7372 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_9_11_reg_7372 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_11_9_11_reg_7372 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_10_11_reg_7377 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_10_11_reg_7377 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_10_11_reg_7377 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_10_11_reg_7377 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_10_11_reg_7377 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_10_11_reg_7377 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_11_10_11_reg_7377 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_11_11_reg_7382 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_11_11_reg_7382 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_11_11_reg_7382 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_11_11_reg_7382 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_11_11_reg_7382 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_11_11_reg_7382 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_11_11_11_reg_7382 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_12_11_reg_7387 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_12_11_reg_7387 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_12_11_reg_7387 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_12_11_reg_7387 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_12_11_reg_7387 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_12_11_reg_7387 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_11_12_11_reg_7387 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_13_11_reg_7392 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_13_11_reg_7392 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_13_11_reg_7392 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_13_11_reg_7392 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_13_11_reg_7392 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_13_11_reg_7392 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_11_13_11_reg_7392 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_14_11_reg_7397 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_14_11_reg_7397 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_14_11_reg_7397 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_14_11_reg_7397 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_14_11_reg_7397 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_14_11_reg_7397 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_11_14_11_reg_7397 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_15_11_reg_7402 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_15_11_reg_7402 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_15_11_reg_7402 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_15_11_reg_7402 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_15_11_reg_7402 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_15_11_reg_7402 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_11_15_11_reg_7402 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_0_12_reg_7407 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_0_12_reg_7407 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_0_12_reg_7407 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_0_12_reg_7407 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_0_12_reg_7407 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_0_12_reg_7407 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_11_0_12_reg_7407 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_1_12_reg_7412 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_1_12_reg_7412 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_1_12_reg_7412 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_1_12_reg_7412 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_1_12_reg_7412 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_1_12_reg_7412 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_11_1_12_reg_7412 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_2_12_reg_7417 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_2_12_reg_7417 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_2_12_reg_7417 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_2_12_reg_7417 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_2_12_reg_7417 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_2_12_reg_7417 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_11_2_12_reg_7417 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_3_12_reg_7422 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_3_12_reg_7422 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_3_12_reg_7422 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_3_12_reg_7422 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_3_12_reg_7422 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_3_12_reg_7422 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_11_3_12_reg_7422 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_4_12_reg_7427 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_4_12_reg_7427 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_4_12_reg_7427 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_4_12_reg_7427 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_4_12_reg_7427 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_4_12_reg_7427 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_11_4_12_reg_7427 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_5_12_reg_7432 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_5_12_reg_7432 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_5_12_reg_7432 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_5_12_reg_7432 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_5_12_reg_7432 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_5_12_reg_7432 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_11_5_12_reg_7432 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_6_12_reg_7437 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_6_12_reg_7437 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_6_12_reg_7437 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_6_12_reg_7437 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_6_12_reg_7437 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_6_12_reg_7437 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_11_6_12_reg_7437 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_7_12_reg_7442 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_7_12_reg_7442 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_7_12_reg_7442 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_7_12_reg_7442 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_7_12_reg_7442 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_7_12_reg_7442 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_11_7_12_reg_7442 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_8_12_reg_7447 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_8_12_reg_7447 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_8_12_reg_7447 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_8_12_reg_7447 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_8_12_reg_7447 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_8_12_reg_7447 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_11_8_12_reg_7447 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_9_12_reg_7452 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_9_12_reg_7452 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_9_12_reg_7452 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_9_12_reg_7452 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_9_12_reg_7452 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_9_12_reg_7452 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_11_9_12_reg_7452 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_10_12_reg_7457 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_10_12_reg_7457 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_10_12_reg_7457 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_10_12_reg_7457 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_10_12_reg_7457 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_10_12_reg_7457 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_11_10_12_reg_7457 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_11_12_reg_7462 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_11_12_reg_7462 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_11_12_reg_7462 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_11_12_reg_7462 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_11_12_reg_7462 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_11_12_reg_7462 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_11_11_12_reg_7462 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_12_12_reg_7467 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_12_12_reg_7467 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_12_12_reg_7467 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_12_12_reg_7467 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_12_12_reg_7467 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_12_12_reg_7467 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_11_12_12_reg_7467 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_13_12_reg_7472 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_13_12_reg_7472 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_13_12_reg_7472 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_13_12_reg_7472 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_13_12_reg_7472 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_13_12_reg_7472 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_11_13_12_reg_7472 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_14_12_reg_7477 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_14_12_reg_7477 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_14_12_reg_7477 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_14_12_reg_7477 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_14_12_reg_7477 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_14_12_reg_7477 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_11_14_12_reg_7477 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_15_12_reg_7482 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_15_12_reg_7482 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_15_12_reg_7482 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_15_12_reg_7482 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_15_12_reg_7482 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_15_12_reg_7482 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_11_15_12_reg_7482 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_0_13_reg_7487 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_0_13_reg_7487 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_0_13_reg_7487 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_0_13_reg_7487 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_0_13_reg_7487 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_0_13_reg_7487 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_11_0_13_reg_7487 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_11_0_13_reg_7487 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_1_13_reg_7492 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_1_13_reg_7492 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_1_13_reg_7492 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_1_13_reg_7492 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_1_13_reg_7492 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_1_13_reg_7492 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_11_1_13_reg_7492 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_11_1_13_reg_7492 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_2_13_reg_7497 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_2_13_reg_7497 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_2_13_reg_7497 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_2_13_reg_7497 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_2_13_reg_7497 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_2_13_reg_7497 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_11_2_13_reg_7497 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_11_2_13_reg_7497 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_3_13_reg_7502 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_3_13_reg_7502 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_3_13_reg_7502 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_3_13_reg_7502 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_3_13_reg_7502 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_3_13_reg_7502 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_11_3_13_reg_7502 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_11_3_13_reg_7502 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_4_13_reg_7507 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_4_13_reg_7507 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_4_13_reg_7507 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_4_13_reg_7507 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_4_13_reg_7507 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_4_13_reg_7507 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_11_4_13_reg_7507 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_11_4_13_reg_7507 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_5_13_reg_7512 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_5_13_reg_7512 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_5_13_reg_7512 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_5_13_reg_7512 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_5_13_reg_7512 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_5_13_reg_7512 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_11_5_13_reg_7512 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_11_5_13_reg_7512 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_6_13_reg_7517 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_6_13_reg_7517 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_6_13_reg_7517 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_6_13_reg_7517 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_6_13_reg_7517 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_6_13_reg_7517 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_11_6_13_reg_7517 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_11_6_13_reg_7517 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_7_13_reg_7522 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_7_13_reg_7522 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_7_13_reg_7522 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_7_13_reg_7522 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_7_13_reg_7522 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_7_13_reg_7522 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_11_7_13_reg_7522 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_11_7_13_reg_7522 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_8_13_reg_7527 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_8_13_reg_7527 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_8_13_reg_7527 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_8_13_reg_7527 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_8_13_reg_7527 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_8_13_reg_7527 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_11_8_13_reg_7527 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_11_8_13_reg_7527 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_9_13_reg_7532 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_9_13_reg_7532 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_9_13_reg_7532 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_9_13_reg_7532 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_9_13_reg_7532 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_9_13_reg_7532 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_11_9_13_reg_7532 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_11_9_13_reg_7532 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_10_13_reg_7537 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_10_13_reg_7537 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_10_13_reg_7537 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_10_13_reg_7537 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_10_13_reg_7537 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_10_13_reg_7537 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_11_10_13_reg_7537 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_11_10_13_reg_7537 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_11_13_reg_7542 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_11_13_reg_7542 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_11_13_reg_7542 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_11_13_reg_7542 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_11_13_reg_7542 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_11_13_reg_7542 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_11_11_13_reg_7542 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_11_11_13_reg_7542 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_12_13_reg_7547 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_12_13_reg_7547 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_12_13_reg_7547 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_12_13_reg_7547 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_12_13_reg_7547 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_12_13_reg_7547 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_11_12_13_reg_7547 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_11_12_13_reg_7547 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_13_13_reg_7552 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_13_13_reg_7552 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_13_13_reg_7552 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_13_13_reg_7552 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_13_13_reg_7552 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_13_13_reg_7552 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_11_13_13_reg_7552 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_11_13_13_reg_7552 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_14_13_reg_7557 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_14_13_reg_7557 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_14_13_reg_7557 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_14_13_reg_7557 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_14_13_reg_7557 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_14_13_reg_7557 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_11_14_13_reg_7557 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_11_14_13_reg_7557 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_15_13_reg_7562 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_15_13_reg_7562 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_15_13_reg_7562 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_15_13_reg_7562 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_15_13_reg_7562 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_15_13_reg_7562 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_11_15_13_reg_7562 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_11_15_13_reg_7562 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_0_14_reg_7567 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_0_14_reg_7567 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_0_14_reg_7567 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_0_14_reg_7567 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_0_14_reg_7567 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_0_14_reg_7567 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_11_0_14_reg_7567 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_11_0_14_reg_7567 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_1_14_reg_7572 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_1_14_reg_7572 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_1_14_reg_7572 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_1_14_reg_7572 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_1_14_reg_7572 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_1_14_reg_7572 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_11_1_14_reg_7572 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_11_1_14_reg_7572 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_2_14_reg_7577 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_2_14_reg_7577 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_2_14_reg_7577 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_2_14_reg_7577 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_2_14_reg_7577 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_2_14_reg_7577 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_11_2_14_reg_7577 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_11_2_14_reg_7577 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_3_14_reg_7582 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_3_14_reg_7582 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_3_14_reg_7582 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_3_14_reg_7582 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_3_14_reg_7582 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_3_14_reg_7582 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_11_3_14_reg_7582 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_11_3_14_reg_7582 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_4_14_reg_7587 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_4_14_reg_7587 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_4_14_reg_7587 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_4_14_reg_7587 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_4_14_reg_7587 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_4_14_reg_7587 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_11_4_14_reg_7587 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_11_4_14_reg_7587 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_5_14_reg_7592 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_5_14_reg_7592 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_5_14_reg_7592 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_5_14_reg_7592 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_5_14_reg_7592 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_5_14_reg_7592 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_11_5_14_reg_7592 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_11_5_14_reg_7592 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_6_14_reg_7597 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_6_14_reg_7597 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_6_14_reg_7597 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_6_14_reg_7597 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_6_14_reg_7597 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_6_14_reg_7597 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_11_6_14_reg_7597 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_11_6_14_reg_7597 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_7_14_reg_7602 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_7_14_reg_7602 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_7_14_reg_7602 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_7_14_reg_7602 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_7_14_reg_7602 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_7_14_reg_7602 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_11_7_14_reg_7602 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_11_7_14_reg_7602 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_8_14_reg_7607 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_8_14_reg_7607 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_8_14_reg_7607 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_8_14_reg_7607 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_8_14_reg_7607 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_8_14_reg_7607 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_11_8_14_reg_7607 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_11_8_14_reg_7607 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_9_14_reg_7612 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_9_14_reg_7612 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_9_14_reg_7612 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_9_14_reg_7612 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_9_14_reg_7612 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_9_14_reg_7612 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_11_9_14_reg_7612 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_11_9_14_reg_7612 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_10_14_reg_7617 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_10_14_reg_7617 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_10_14_reg_7617 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_10_14_reg_7617 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_10_14_reg_7617 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_10_14_reg_7617 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_11_10_14_reg_7617 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_11_10_14_reg_7617 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_11_14_reg_7622 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_11_14_reg_7622 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_11_14_reg_7622 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_11_14_reg_7622 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_11_14_reg_7622 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_11_14_reg_7622 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_11_11_14_reg_7622 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_11_11_14_reg_7622 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_12_14_reg_7627 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_12_14_reg_7627 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_12_14_reg_7627 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_12_14_reg_7627 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_12_14_reg_7627 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_12_14_reg_7627 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_11_12_14_reg_7627 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_11_12_14_reg_7627 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_13_14_reg_7632 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_13_14_reg_7632 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_13_14_reg_7632 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_13_14_reg_7632 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_13_14_reg_7632 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_13_14_reg_7632 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_11_13_14_reg_7632 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_11_13_14_reg_7632 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_14_14_reg_7637 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_14_14_reg_7637 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_14_14_reg_7637 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_14_14_reg_7637 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_14_14_reg_7637 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_14_14_reg_7637 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_11_14_14_reg_7637 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_11_14_14_reg_7637 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_15_14_reg_7642 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_11_15_14_reg_7642 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_11_15_14_reg_7642 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_11_15_14_reg_7642 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_11_15_14_reg_7642 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_11_15_14_reg_7642 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_11_15_14_reg_7642 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_11_15_14_reg_7642 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_0_2_reg_7647 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter2 : STD_LOGIC := '0';
signal tmp_12_1_2_reg_7652 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_2_2_reg_7657 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_3_2_reg_7662 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_4_2_reg_7667 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_5_2_reg_7672 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_6_2_reg_7677 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_7_2_reg_7682 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_8_2_reg_7687 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_9_2_reg_7692 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_10_2_reg_7697 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_11_2_reg_7702 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_12_2_reg_7707 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_13_2_reg_7712 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_14_2_reg_7717 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_15_2_reg_7722 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_0_3_reg_7727 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter3 : STD_LOGIC := '0';
signal tmp_12_1_3_reg_7732 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_2_3_reg_7737 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_3_3_reg_7742 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_4_3_reg_7747 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_5_3_reg_7752 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_6_3_reg_7757 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_7_3_reg_7762 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_8_3_reg_7767 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_9_3_reg_7772 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_10_3_reg_7777 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_11_3_reg_7782 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_12_3_reg_7787 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_13_3_reg_7792 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_14_3_reg_7797 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_15_3_reg_7802 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_0_4_reg_7807 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_1_4_reg_7812 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_2_4_reg_7817 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_3_4_reg_7822 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_4_4_reg_7827 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_5_4_reg_7832 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_6_4_reg_7837 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_7_4_reg_7842 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_8_4_reg_7847 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_9_4_reg_7852 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_10_4_reg_7857 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_11_4_reg_7862 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_12_4_reg_7867 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_13_4_reg_7872 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_14_4_reg_7877 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_15_4_reg_7882 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_0_5_reg_7887 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter4 : STD_LOGIC := '0';
signal tmp_12_1_5_reg_7892 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_2_5_reg_7897 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_3_5_reg_7902 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_4_5_reg_7907 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_5_5_reg_7912 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_6_5_reg_7917 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_7_5_reg_7922 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_8_5_reg_7927 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_9_5_reg_7932 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_10_5_reg_7937 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_11_5_reg_7942 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_12_5_reg_7947 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_13_5_reg_7952 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_14_5_reg_7957 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_15_5_reg_7962 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_0_6_reg_7967 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_1_6_reg_7972 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_2_6_reg_7977 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_3_6_reg_7982 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_4_6_reg_7987 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_5_6_reg_7992 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_6_6_reg_7997 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_7_6_reg_8002 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_8_6_reg_8007 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_9_6_reg_8012 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_10_6_reg_8017 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_11_6_reg_8022 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_12_6_reg_8027 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_13_6_reg_8032 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_14_6_reg_8037 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_15_6_reg_8042 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_0_7_reg_8047 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter5 : STD_LOGIC := '0';
signal tmp_12_1_7_reg_8052 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_2_7_reg_8057 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_3_7_reg_8062 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_4_7_reg_8067 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_5_7_reg_8072 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_6_7_reg_8077 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_7_7_reg_8082 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_8_7_reg_8087 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_9_7_reg_8092 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_10_7_reg_8097 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_11_7_reg_8102 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_12_7_reg_8107 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_13_7_reg_8112 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_14_7_reg_8117 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_15_7_reg_8122 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_0_8_reg_8127 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_1_8_reg_8132 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_2_8_reg_8137 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_3_8_reg_8142 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_4_8_reg_8147 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_5_8_reg_8152 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_6_8_reg_8157 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_7_8_reg_8162 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_8_8_reg_8167 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_9_8_reg_8172 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_10_8_reg_8177 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_11_8_reg_8182 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_12_8_reg_8187 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_13_8_reg_8192 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_14_8_reg_8197 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_15_8_reg_8202 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_0_9_reg_8207 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter6 : STD_LOGIC := '0';
signal tmp_12_1_9_reg_8212 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_2_9_reg_8217 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_3_9_reg_8222 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_4_9_reg_8227 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_5_9_reg_8232 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_6_9_reg_8237 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_7_9_reg_8242 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_8_9_reg_8247 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_9_9_reg_8252 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_10_9_reg_8257 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_11_9_reg_8262 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_12_9_reg_8267 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_13_9_reg_8272 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_14_9_reg_8277 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_15_9_reg_8282 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_0_s_reg_8287 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter7 : STD_LOGIC := '0';
signal tmp_12_1_s_reg_8292 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_2_s_reg_8297 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_3_s_reg_8302 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_4_s_reg_8307 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_5_s_reg_8312 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_6_s_reg_8317 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_7_s_reg_8322 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_8_s_reg_8327 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_9_s_reg_8332 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_10_s_reg_8337 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_11_s_reg_8342 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_12_s_reg_8347 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_13_s_reg_8352 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_14_s_reg_8357 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_15_s_reg_8362 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_0_10_reg_8367 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_1_10_reg_8372 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_2_10_reg_8377 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_3_10_reg_8382 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_4_10_reg_8387 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_5_10_reg_8392 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_6_10_reg_8397 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_7_10_reg_8402 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_8_10_reg_8407 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_9_10_reg_8412 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_10_10_reg_8417 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_11_10_reg_8422 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_12_10_reg_8427 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_13_10_reg_8432 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_14_10_reg_8437 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_15_10_reg_8442 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_0_11_reg_8447 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter8 : STD_LOGIC := '0';
signal tmp_12_1_11_reg_8452 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_2_11_reg_8457 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_3_11_reg_8462 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_4_11_reg_8467 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_5_11_reg_8472 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_6_11_reg_8477 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_7_11_reg_8482 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_8_11_reg_8487 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_9_11_reg_8492 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_10_11_reg_8497 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_11_11_reg_8502 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_12_11_reg_8507 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_13_11_reg_8512 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_14_11_reg_8517 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_15_11_reg_8522 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_0_12_reg_8527 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_1_12_reg_8532 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_2_12_reg_8537 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_3_12_reg_8542 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_4_12_reg_8547 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_5_12_reg_8552 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_6_12_reg_8557 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_7_12_reg_8562 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_8_12_reg_8567 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_9_12_reg_8572 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_10_12_reg_8577 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_11_12_reg_8582 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_12_12_reg_8587 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_13_12_reg_8592 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_14_12_reg_8597 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_15_12_reg_8602 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_0_13_reg_8607 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_1_13_reg_8612 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_2_13_reg_8617 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_3_13_reg_8622 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_4_13_reg_8627 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_5_13_reg_8632 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_6_13_reg_8637 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_7_13_reg_8642 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_8_13_reg_8647 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_9_13_reg_8652 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_10_13_reg_8657 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_11_13_reg_8662 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_12_13_reg_8667 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_13_13_reg_8672 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_14_13_reg_8677 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_15_13_reg_8682 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_block_pp0_stage0_flag00011011 : BOOLEAN;
signal ap_condition_pp0_exit_iter0_state2 : STD_LOGIC;
signal ap_block_pp0_stage15_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage14_flag00011011 : BOOLEAN;
signal indvar_flatten1_phi_fu_355_p4 : STD_LOGIC_VECTOR (12 downto 0);
signal ap_block_pp0_stage0_flag00000000 : BOOLEAN;
signal i_phi_fu_366_p4 : STD_LOGIC_VECTOR (2 downto 0);
signal indvar_flatten2_phi_fu_378_p4 : STD_LOGIC_VECTOR (11 downto 0);
signal j_phi_fu_389_p4 : STD_LOGIC_VECTOR (2 downto 0);
signal ap_block_pp0_stage1_flag00000000 : BOOLEAN;
signal indvar_flatten_phi_fu_401_p4 : STD_LOGIC_VECTOR (9 downto 0);
signal row_b_phi_fu_413_p4 : STD_LOGIC_VECTOR (4 downto 0);
signal col_b_phi_fu_425_p4 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_629_cast_fu_1278_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_block_pp0_stage3_flag00000000 : BOOLEAN;
signal tmp_621_cast_fu_1293_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_block_pp0_stage4_flag00000000 : BOOLEAN;
signal tmp_647_cast_fu_1348_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_622_cast_fu_1391_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_block_pp0_stage5_flag00000000 : BOOLEAN;
signal tmp_623_cast_fu_1414_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_block_pp0_stage6_flag00000000 : BOOLEAN;
signal tmp_624_cast_fu_1625_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_block_pp0_stage7_flag00000000 : BOOLEAN;
signal tmp_649_cast_fu_1635_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_625_cast_fu_1648_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_block_pp0_stage8_flag00000000 : BOOLEAN;
signal tmp_626_cast_fu_1825_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_block_pp0_stage9_flag00000000 : BOOLEAN;
signal tmp_627_cast_fu_1941_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_block_pp0_stage10_flag00000000 : BOOLEAN;
signal tmp_628_cast_fu_2059_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_block_pp0_stage11_flag00000000 : BOOLEAN;
signal tmp_630_cast_fu_2176_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_block_pp0_stage12_flag00000000 : BOOLEAN;
signal tmp_631_cast_fu_2292_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_block_pp0_stage13_flag00000000 : BOOLEAN;
signal tmp_632_cast_fu_2408_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_block_pp0_stage14_flag00000000 : BOOLEAN;
signal tmp_633_cast_fu_2588_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_block_pp0_stage15_flag00000000 : BOOLEAN;
signal tmp_634_cast_fu_2709_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_635_cast_fu_2825_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_636_cast_fu_2916_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_block_pp0_stage2_flag00000000 : BOOLEAN;
signal bufw_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_433_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_433_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_437_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_437_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_441_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_441_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_445_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_445_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_449_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_449_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_453_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_453_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_457_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_457_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_461_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_461_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_465_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_465_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_469_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_469_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_473_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_473_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_477_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_477_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_481_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_481_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_485_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_485_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_489_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_489_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_493_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_493_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_497_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_497_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_501_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_501_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_505_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_505_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_509_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_509_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_513_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_513_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_517_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_517_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_521_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_521_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_525_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_525_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_529_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_529_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_533_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_533_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_537_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_537_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_541_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_541_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_545_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_545_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_549_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_549_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_553_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_553_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_557_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_557_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_fu_1035_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_1_cast_fu_1031_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_7_cast_fu_1041_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal not_exitcond_flatten_fu_1107_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond_flatten_not_fu_1128_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_9_mid_fu_1112_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_exitcond_flatten_1_fu_1133_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_1_fu_1159_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal p_shl4_cast_fu_1166_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal p_shl3_cast_fu_1183_p4 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_611_cast_fu_1176_p3 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_8_cast_mid_cast_fu_1198_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_39_fu_1207_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_4_mid2_cast2_fu_1224_p1 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_11_fu_1192_p2 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_8_cast_mid3_fu_1201_p3 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_615_fu_1241_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_616_fu_1245_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_cast_fu_1287_p1 : STD_LOGIC_VECTOR (6 downto 0);
signal p_v_fu_1303_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_617_fu_1308_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_618_fu_1320_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_7_cast_mid1_fu_1325_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal col_b_cast1_cast_fu_1339_p1 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_642_cast_fu_1316_p1 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_622_fu_1342_p2 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_623_fu_1353_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_cast_fu_1358_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_2_cast_fu_1376_p1 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_6_fu_1379_p2 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_s_fu_1385_p2 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_619_fu_1418_p3 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_620_fu_1429_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal p_shl_cast_fu_1425_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal p_shl2_cast_fu_1436_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_3_cast_cast_fu_1446_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_621_fu_1440_p2 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_4_fu_1616_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_7_fu_1643_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_9_fu_1815_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_10_fu_1820_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_13_fu_2050_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_15_fu_2171_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_17_fu_2287_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_19_fu_2403_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_23_fu_2583_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_27_fu_2699_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_31_fu_2704_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_605_fu_3629_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_570_fu_3625_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_535_fu_3621_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_500_fu_3617_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_465_fu_3613_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_430_fu_3609_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_395_fu_3605_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_360_fu_3601_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_325_fu_3597_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_290_fu_3593_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_255_fu_3589_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_220_fu_3585_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_185_fu_3581_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_150_fu_3577_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_114_fu_3573_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_79_fu_3569_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state161 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state161 : signal is "none";
signal ap_NS_fsm : STD_LOGIC_VECTOR (17 downto 0);
signal ap_block_pp0_stage1_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage2_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage3_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage4_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage5_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage6_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage7_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage8_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage9_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage10_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage11_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage12_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage13_flag00011011 : BOOLEAN;
signal ap_idle_pp0 : STD_LOGIC;
signal ap_enable_pp0 : STD_LOGIC;
component convolve_kernel_fbkb IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component convolve_kernel_fcud IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component convolve_kernel_control_s_axi IS
generic (
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER );
port (
AWVALID : IN STD_LOGIC;
AWREADY : OUT STD_LOGIC;
AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
WVALID : IN STD_LOGIC;
WREADY : OUT STD_LOGIC;
WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0);
ARVALID : IN STD_LOGIC;
ARREADY : OUT STD_LOGIC;
ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
RVALID : OUT STD_LOGIC;
RREADY : IN STD_LOGIC;
RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
BVALID : OUT STD_LOGIC;
BREADY : IN STD_LOGIC;
BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
ACLK_EN : IN STD_LOGIC;
ap_start : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
ap_ready : IN STD_LOGIC;
ap_done : IN STD_LOGIC;
ap_idle : IN STD_LOGIC );
end component;
begin
convolve_kernel_control_s_axi_U : component convolve_kernel_control_s_axi
generic map (
C_S_AXI_ADDR_WIDTH => C_S_AXI_CONTROL_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_CONTROL_DATA_WIDTH)
port map (
AWVALID => s_axi_control_AWVALID,
AWREADY => s_axi_control_AWREADY,
AWADDR => s_axi_control_AWADDR,
WVALID => s_axi_control_WVALID,
WREADY => s_axi_control_WREADY,
WDATA => s_axi_control_WDATA,
WSTRB => s_axi_control_WSTRB,
ARVALID => s_axi_control_ARVALID,
ARREADY => s_axi_control_ARREADY,
ARADDR => s_axi_control_ARADDR,
RVALID => s_axi_control_RVALID,
RREADY => s_axi_control_RREADY,
RDATA => s_axi_control_RDATA,
RRESP => s_axi_control_RRESP,
BVALID => s_axi_control_BVALID,
BREADY => s_axi_control_BREADY,
BRESP => s_axi_control_BRESP,
ACLK => ap_clk,
ARESET => ap_rst_n_inv,
ACLK_EN => ap_const_logic_1,
ap_start => ap_start,
interrupt => interrupt,
ap_ready => ap_ready,
ap_done => ap_done,
ap_idle => ap_idle);
convolve_kernel_fbkb_U1 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_433_p0,
din1 => grp_fu_433_p1,
ce => ap_const_logic_1,
dout => grp_fu_433_p2);
convolve_kernel_fbkb_U2 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_437_p0,
din1 => grp_fu_437_p1,
ce => ap_const_logic_1,
dout => grp_fu_437_p2);
convolve_kernel_fbkb_U3 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_441_p0,
din1 => grp_fu_441_p1,
ce => ap_const_logic_1,
dout => grp_fu_441_p2);
convolve_kernel_fbkb_U4 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_445_p0,
din1 => grp_fu_445_p1,
ce => ap_const_logic_1,
dout => grp_fu_445_p2);
convolve_kernel_fbkb_U5 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_449_p0,
din1 => grp_fu_449_p1,
ce => ap_const_logic_1,
dout => grp_fu_449_p2);
convolve_kernel_fbkb_U6 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_453_p0,
din1 => grp_fu_453_p1,
ce => ap_const_logic_1,
dout => grp_fu_453_p2);
convolve_kernel_fbkb_U7 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_457_p0,
din1 => grp_fu_457_p1,
ce => ap_const_logic_1,
dout => grp_fu_457_p2);
convolve_kernel_fbkb_U8 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_461_p0,
din1 => grp_fu_461_p1,
ce => ap_const_logic_1,
dout => grp_fu_461_p2);
convolve_kernel_fbkb_U9 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_465_p0,
din1 => grp_fu_465_p1,
ce => ap_const_logic_1,
dout => grp_fu_465_p2);
convolve_kernel_fbkb_U10 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_469_p0,
din1 => grp_fu_469_p1,
ce => ap_const_logic_1,
dout => grp_fu_469_p2);
convolve_kernel_fbkb_U11 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_473_p0,
din1 => grp_fu_473_p1,
ce => ap_const_logic_1,
dout => grp_fu_473_p2);
convolve_kernel_fbkb_U12 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_477_p0,
din1 => grp_fu_477_p1,
ce => ap_const_logic_1,
dout => grp_fu_477_p2);
convolve_kernel_fbkb_U13 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_481_p0,
din1 => grp_fu_481_p1,
ce => ap_const_logic_1,
dout => grp_fu_481_p2);
convolve_kernel_fbkb_U14 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_485_p0,
din1 => grp_fu_485_p1,
ce => ap_const_logic_1,
dout => grp_fu_485_p2);
convolve_kernel_fbkb_U15 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_489_p0,
din1 => grp_fu_489_p1,
ce => ap_const_logic_1,
dout => grp_fu_489_p2);
convolve_kernel_fbkb_U16 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_493_p0,
din1 => grp_fu_493_p1,
ce => ap_const_logic_1,
dout => grp_fu_493_p2);
convolve_kernel_fcud_U17 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_497_p0,
din1 => grp_fu_497_p1,
ce => ap_const_logic_1,
dout => grp_fu_497_p2);
convolve_kernel_fcud_U18 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_501_p0,
din1 => grp_fu_501_p1,
ce => ap_const_logic_1,
dout => grp_fu_501_p2);
convolve_kernel_fcud_U19 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_505_p0,
din1 => grp_fu_505_p1,
ce => ap_const_logic_1,
dout => grp_fu_505_p2);
convolve_kernel_fcud_U20 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_509_p0,
din1 => grp_fu_509_p1,
ce => ap_const_logic_1,
dout => grp_fu_509_p2);
convolve_kernel_fcud_U21 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_513_p0,
din1 => grp_fu_513_p1,
ce => ap_const_logic_1,
dout => grp_fu_513_p2);
convolve_kernel_fcud_U22 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_517_p0,
din1 => grp_fu_517_p1,
ce => ap_const_logic_1,
dout => grp_fu_517_p2);
convolve_kernel_fcud_U23 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_521_p0,
din1 => grp_fu_521_p1,
ce => ap_const_logic_1,
dout => grp_fu_521_p2);
convolve_kernel_fcud_U24 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_525_p0,
din1 => grp_fu_525_p1,
ce => ap_const_logic_1,
dout => grp_fu_525_p2);
convolve_kernel_fcud_U25 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_529_p0,
din1 => grp_fu_529_p1,
ce => ap_const_logic_1,
dout => grp_fu_529_p2);
convolve_kernel_fcud_U26 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_533_p0,
din1 => grp_fu_533_p1,
ce => ap_const_logic_1,
dout => grp_fu_533_p2);
convolve_kernel_fcud_U27 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_537_p0,
din1 => grp_fu_537_p1,
ce => ap_const_logic_1,
dout => grp_fu_537_p2);
convolve_kernel_fcud_U28 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_541_p0,
din1 => grp_fu_541_p1,
ce => ap_const_logic_1,
dout => grp_fu_541_p2);
convolve_kernel_fcud_U29 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_545_p0,
din1 => grp_fu_545_p1,
ce => ap_const_logic_1,
dout => grp_fu_545_p2);
convolve_kernel_fcud_U30 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_549_p0,
din1 => grp_fu_549_p1,
ce => ap_const_logic_1,
dout => grp_fu_549_p2);
convolve_kernel_fcud_U31 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_553_p0,
din1 => grp_fu_553_p1,
ce => ap_const_logic_1,
dout => grp_fu_553_p2);
convolve_kernel_fcud_U32 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_557_p0,
din1 => grp_fu_557_p1,
ce => ap_const_logic_1,
dout => grp_fu_557_p2);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_enable_reg_pp0_iter0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state2))) then
ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_enable_reg_pp0_iter0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011011 = ap_const_boolean_0))) then
if ((ap_const_logic_1 = ap_condition_pp0_exit_iter0_state2)) then
ap_enable_reg_pp0_iter1 <= (ap_condition_pp0_exit_iter0_state2 xor ap_const_logic_1);
elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then
ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
end if;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_enable_reg_pp0_iter2 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter3_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_enable_reg_pp0_iter3 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter4_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_enable_reg_pp0_iter4 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter5_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_enable_reg_pp0_iter5 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter6_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_enable_reg_pp0_iter6 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter7_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_enable_reg_pp0_iter7 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter8_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_enable_reg_pp0_iter8 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter9_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_enable_reg_pp0_iter9 <= ap_const_logic_0;
else
if ((((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011011 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00011011 = ap_const_boolean_0)))) then
ap_enable_reg_pp0_iter9 <= ap_enable_reg_pp0_iter8;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_enable_reg_pp0_iter9 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
col_b_reg_421_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_flatten2_reg_3675 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
col_b_reg_421 <= col_b_1_reg_3957;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
col_b_reg_421 <= ap_const_lv5_0;
end if;
end if;
end process;
i_reg_362_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_flatten2_reg_3675 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
i_reg_362 <= tmp_1_mid2_v_reg_3722;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
i_reg_362 <= ap_const_lv3_0;
end if;
end if;
end process;
indvar_flatten1_reg_351_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_flatten2_reg_3675 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
indvar_flatten1_reg_351 <= indvar_flatten_next2_reg_3679;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
indvar_flatten1_reg_351 <= ap_const_lv13_0;
end if;
end if;
end process;
indvar_flatten2_reg_374_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_flatten2_reg_3675 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
indvar_flatten2_reg_374 <= indvar_flatten_next1_reg_3757;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
indvar_flatten2_reg_374 <= ap_const_lv12_0;
end if;
end if;
end process;
indvar_flatten_reg_397_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_flatten2_reg_3675 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
indvar_flatten_reg_397 <= indvar_flatten_next_reg_3809;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
indvar_flatten_reg_397 <= ap_const_lv10_0;
end if;
end if;
end process;
j_reg_385_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_lv1_0 = ap_reg_pp0_iter1_exitcond_flatten2_reg_3675) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0))) then
j_reg_385 <= tmp_4_mid2_reg_3783;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
j_reg_385 <= ap_const_lv3_0;
end if;
end if;
end process;
row_b_reg_409_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_flatten2_reg_3675 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
row_b_reg_409 <= row_b_mid2_reg_3862;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
row_b_reg_409 <= ap_const_lv5_0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0))) then
ap_reg_pp0_iter1_bufo_addr_reg_3867 <= bufo_addr_reg_3867;
ap_reg_pp0_iter2_bufo_addr_reg_3867 <= ap_reg_pp0_iter1_bufo_addr_reg_3867;
ap_reg_pp0_iter2_tmp_11_0_7_reg_6347 <= tmp_11_0_7_reg_6347;
ap_reg_pp0_iter2_tmp_11_10_7_reg_6467 <= tmp_11_10_7_reg_6467;
ap_reg_pp0_iter2_tmp_11_11_7_reg_6477 <= tmp_11_11_7_reg_6477;
ap_reg_pp0_iter2_tmp_11_12_7_reg_6487 <= tmp_11_12_7_reg_6487;
ap_reg_pp0_iter2_tmp_11_13_7_reg_6497 <= tmp_11_13_7_reg_6497;
ap_reg_pp0_iter2_tmp_11_14_7_reg_6507 <= tmp_11_14_7_reg_6507;
ap_reg_pp0_iter2_tmp_11_15_7_reg_6517 <= tmp_11_15_7_reg_6517;
ap_reg_pp0_iter2_tmp_11_1_7_reg_6377 <= tmp_11_1_7_reg_6377;
ap_reg_pp0_iter2_tmp_11_2_7_reg_6387 <= tmp_11_2_7_reg_6387;
ap_reg_pp0_iter2_tmp_11_3_7_reg_6397 <= tmp_11_3_7_reg_6397;
ap_reg_pp0_iter2_tmp_11_4_7_reg_6407 <= tmp_11_4_7_reg_6407;
ap_reg_pp0_iter2_tmp_11_5_7_reg_6417 <= tmp_11_5_7_reg_6417;
ap_reg_pp0_iter2_tmp_11_6_7_reg_6427 <= tmp_11_6_7_reg_6427;
ap_reg_pp0_iter2_tmp_11_7_7_reg_6437 <= tmp_11_7_7_reg_6437;
ap_reg_pp0_iter2_tmp_11_8_7_reg_6447 <= tmp_11_8_7_reg_6447;
ap_reg_pp0_iter2_tmp_11_9_7_reg_6457 <= tmp_11_9_7_reg_6457;
ap_reg_pp0_iter3_bufo_addr_reg_3867 <= ap_reg_pp0_iter2_bufo_addr_reg_3867;
ap_reg_pp0_iter3_tmp_11_0_7_reg_6347 <= ap_reg_pp0_iter2_tmp_11_0_7_reg_6347;
ap_reg_pp0_iter3_tmp_11_10_7_reg_6467 <= ap_reg_pp0_iter2_tmp_11_10_7_reg_6467;
ap_reg_pp0_iter3_tmp_11_11_7_reg_6477 <= ap_reg_pp0_iter2_tmp_11_11_7_reg_6477;
ap_reg_pp0_iter3_tmp_11_12_7_reg_6487 <= ap_reg_pp0_iter2_tmp_11_12_7_reg_6487;
ap_reg_pp0_iter3_tmp_11_13_7_reg_6497 <= ap_reg_pp0_iter2_tmp_11_13_7_reg_6497;
ap_reg_pp0_iter3_tmp_11_14_7_reg_6507 <= ap_reg_pp0_iter2_tmp_11_14_7_reg_6507;
ap_reg_pp0_iter3_tmp_11_15_7_reg_6517 <= ap_reg_pp0_iter2_tmp_11_15_7_reg_6517;
ap_reg_pp0_iter3_tmp_11_1_7_reg_6377 <= ap_reg_pp0_iter2_tmp_11_1_7_reg_6377;
ap_reg_pp0_iter3_tmp_11_2_7_reg_6387 <= ap_reg_pp0_iter2_tmp_11_2_7_reg_6387;
ap_reg_pp0_iter3_tmp_11_3_7_reg_6397 <= ap_reg_pp0_iter2_tmp_11_3_7_reg_6397;
ap_reg_pp0_iter3_tmp_11_4_7_reg_6407 <= ap_reg_pp0_iter2_tmp_11_4_7_reg_6407;
ap_reg_pp0_iter3_tmp_11_5_7_reg_6417 <= ap_reg_pp0_iter2_tmp_11_5_7_reg_6417;
ap_reg_pp0_iter3_tmp_11_6_7_reg_6427 <= ap_reg_pp0_iter2_tmp_11_6_7_reg_6427;
ap_reg_pp0_iter3_tmp_11_7_7_reg_6437 <= ap_reg_pp0_iter2_tmp_11_7_7_reg_6437;
ap_reg_pp0_iter3_tmp_11_8_7_reg_6447 <= ap_reg_pp0_iter2_tmp_11_8_7_reg_6447;
ap_reg_pp0_iter3_tmp_11_9_7_reg_6457 <= ap_reg_pp0_iter2_tmp_11_9_7_reg_6457;
ap_reg_pp0_iter4_bufo_addr_reg_3867 <= ap_reg_pp0_iter3_bufo_addr_reg_3867;
ap_reg_pp0_iter4_tmp_11_0_7_reg_6347 <= ap_reg_pp0_iter3_tmp_11_0_7_reg_6347;
ap_reg_pp0_iter4_tmp_11_10_7_reg_6467 <= ap_reg_pp0_iter3_tmp_11_10_7_reg_6467;
ap_reg_pp0_iter4_tmp_11_11_7_reg_6477 <= ap_reg_pp0_iter3_tmp_11_11_7_reg_6477;
ap_reg_pp0_iter4_tmp_11_12_7_reg_6487 <= ap_reg_pp0_iter3_tmp_11_12_7_reg_6487;
ap_reg_pp0_iter4_tmp_11_13_7_reg_6497 <= ap_reg_pp0_iter3_tmp_11_13_7_reg_6497;
ap_reg_pp0_iter4_tmp_11_14_7_reg_6507 <= ap_reg_pp0_iter3_tmp_11_14_7_reg_6507;
ap_reg_pp0_iter4_tmp_11_15_7_reg_6517 <= ap_reg_pp0_iter3_tmp_11_15_7_reg_6517;
ap_reg_pp0_iter4_tmp_11_1_7_reg_6377 <= ap_reg_pp0_iter3_tmp_11_1_7_reg_6377;
ap_reg_pp0_iter4_tmp_11_2_7_reg_6387 <= ap_reg_pp0_iter3_tmp_11_2_7_reg_6387;
ap_reg_pp0_iter4_tmp_11_3_7_reg_6397 <= ap_reg_pp0_iter3_tmp_11_3_7_reg_6397;
ap_reg_pp0_iter4_tmp_11_4_7_reg_6407 <= ap_reg_pp0_iter3_tmp_11_4_7_reg_6407;
ap_reg_pp0_iter4_tmp_11_5_7_reg_6417 <= ap_reg_pp0_iter3_tmp_11_5_7_reg_6417;
ap_reg_pp0_iter4_tmp_11_6_7_reg_6427 <= ap_reg_pp0_iter3_tmp_11_6_7_reg_6427;
ap_reg_pp0_iter4_tmp_11_7_7_reg_6437 <= ap_reg_pp0_iter3_tmp_11_7_7_reg_6437;
ap_reg_pp0_iter4_tmp_11_8_7_reg_6447 <= ap_reg_pp0_iter3_tmp_11_8_7_reg_6447;
ap_reg_pp0_iter4_tmp_11_9_7_reg_6457 <= ap_reg_pp0_iter3_tmp_11_9_7_reg_6457;
ap_reg_pp0_iter5_bufo_addr_reg_3867 <= ap_reg_pp0_iter4_bufo_addr_reg_3867;
ap_reg_pp0_iter6_bufo_addr_reg_3867 <= ap_reg_pp0_iter5_bufo_addr_reg_3867;
ap_reg_pp0_iter7_bufo_addr_reg_3867 <= ap_reg_pp0_iter6_bufo_addr_reg_3867;
ap_reg_pp0_iter8_bufo_addr_reg_3867 <= ap_reg_pp0_iter7_bufo_addr_reg_3867;
ap_reg_pp0_iter9_bufo_addr_reg_3867 <= ap_reg_pp0_iter8_bufo_addr_reg_3867;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
ap_reg_pp0_iter1_exitcond_flatten2_reg_3675 <= exitcond_flatten2_reg_3675;
ap_reg_pp0_iter2_exitcond_flatten2_reg_3675 <= ap_reg_pp0_iter1_exitcond_flatten2_reg_3675;
ap_reg_pp0_iter2_tmp_11_0_3_reg_5372 <= tmp_11_0_3_reg_5372;
ap_reg_pp0_iter2_tmp_11_10_3_reg_5497 <= tmp_11_10_3_reg_5497;
ap_reg_pp0_iter2_tmp_11_11_3_reg_5507 <= tmp_11_11_3_reg_5507;
ap_reg_pp0_iter2_tmp_11_12_3_reg_5517 <= tmp_11_12_3_reg_5517;
ap_reg_pp0_iter2_tmp_11_13_3_reg_5527 <= tmp_11_13_3_reg_5527;
ap_reg_pp0_iter2_tmp_11_14_3_reg_5537 <= tmp_11_14_3_reg_5537;
ap_reg_pp0_iter2_tmp_11_15_3_reg_5547 <= tmp_11_15_3_reg_5547;
ap_reg_pp0_iter2_tmp_11_1_3_reg_5407 <= tmp_11_1_3_reg_5407;
ap_reg_pp0_iter2_tmp_11_2_3_reg_5417 <= tmp_11_2_3_reg_5417;
ap_reg_pp0_iter2_tmp_11_3_3_reg_5427 <= tmp_11_3_3_reg_5427;
ap_reg_pp0_iter2_tmp_11_4_3_reg_5437 <= tmp_11_4_3_reg_5437;
ap_reg_pp0_iter2_tmp_11_5_3_reg_5447 <= tmp_11_5_3_reg_5447;
ap_reg_pp0_iter2_tmp_11_6_3_reg_5457 <= tmp_11_6_3_reg_5457;
ap_reg_pp0_iter2_tmp_11_7_3_reg_5467 <= tmp_11_7_3_reg_5467;
ap_reg_pp0_iter2_tmp_11_8_3_reg_5477 <= tmp_11_8_3_reg_5477;
ap_reg_pp0_iter2_tmp_11_9_3_reg_5487 <= tmp_11_9_3_reg_5487;
ap_reg_pp0_iter3_exitcond_flatten2_reg_3675 <= ap_reg_pp0_iter2_exitcond_flatten2_reg_3675;
ap_reg_pp0_iter4_exitcond_flatten2_reg_3675 <= ap_reg_pp0_iter3_exitcond_flatten2_reg_3675;
ap_reg_pp0_iter5_exitcond_flatten2_reg_3675 <= ap_reg_pp0_iter4_exitcond_flatten2_reg_3675;
ap_reg_pp0_iter6_exitcond_flatten2_reg_3675 <= ap_reg_pp0_iter5_exitcond_flatten2_reg_3675;
ap_reg_pp0_iter7_exitcond_flatten2_reg_3675 <= ap_reg_pp0_iter6_exitcond_flatten2_reg_3675;
ap_reg_pp0_iter8_exitcond_flatten2_reg_3675 <= ap_reg_pp0_iter7_exitcond_flatten2_reg_3675;
ap_reg_pp0_iter9_exitcond_flatten2_reg_3675 <= ap_reg_pp0_iter8_exitcond_flatten2_reg_3675;
exitcond_flatten2_reg_3675 <= exitcond_flatten2_fu_1051_p2;
tmp_8_reg_3670 <= tmp_8_fu_1045_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011001 = ap_const_boolean_0))) then
ap_reg_pp0_iter1_tmp_11_0_2_reg_5172 <= tmp_11_0_2_reg_5172;
ap_reg_pp0_iter1_tmp_11_10_2_reg_5297 <= tmp_11_10_2_reg_5297;
ap_reg_pp0_iter1_tmp_11_11_2_reg_5307 <= tmp_11_11_2_reg_5307;
ap_reg_pp0_iter1_tmp_11_12_2_reg_5317 <= tmp_11_12_2_reg_5317;
ap_reg_pp0_iter1_tmp_11_13_2_reg_5327 <= tmp_11_13_2_reg_5327;
ap_reg_pp0_iter1_tmp_11_14_2_reg_5337 <= tmp_11_14_2_reg_5337;
ap_reg_pp0_iter1_tmp_11_15_2_reg_5347 <= tmp_11_15_2_reg_5347;
ap_reg_pp0_iter1_tmp_11_1_2_reg_5207 <= tmp_11_1_2_reg_5207;
ap_reg_pp0_iter1_tmp_11_2_2_reg_5217 <= tmp_11_2_2_reg_5217;
ap_reg_pp0_iter1_tmp_11_3_2_reg_5227 <= tmp_11_3_2_reg_5227;
ap_reg_pp0_iter1_tmp_11_4_2_reg_5237 <= tmp_11_4_2_reg_5237;
ap_reg_pp0_iter1_tmp_11_5_2_reg_5247 <= tmp_11_5_2_reg_5247;
ap_reg_pp0_iter1_tmp_11_6_2_reg_5257 <= tmp_11_6_2_reg_5257;
ap_reg_pp0_iter1_tmp_11_7_2_reg_5267 <= tmp_11_7_2_reg_5267;
ap_reg_pp0_iter1_tmp_11_8_2_reg_5277 <= tmp_11_8_2_reg_5277;
ap_reg_pp0_iter1_tmp_11_9_2_reg_5287 <= tmp_11_9_2_reg_5287;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0))) then
ap_reg_pp0_iter2_tmp_11_0_10_reg_7147 <= tmp_11_0_10_reg_7147;
ap_reg_pp0_iter2_tmp_11_10_10_reg_7267 <= tmp_11_10_10_reg_7267;
ap_reg_pp0_iter2_tmp_11_11_10_reg_7277 <= tmp_11_11_10_reg_7277;
ap_reg_pp0_iter2_tmp_11_12_10_reg_7287 <= tmp_11_12_10_reg_7287;
ap_reg_pp0_iter2_tmp_11_13_10_reg_7297 <= tmp_11_13_10_reg_7297;
ap_reg_pp0_iter2_tmp_11_14_10_reg_7307 <= tmp_11_14_10_reg_7307;
ap_reg_pp0_iter2_tmp_11_15_10_reg_7317 <= tmp_11_15_10_reg_7317;
ap_reg_pp0_iter2_tmp_11_1_10_reg_7177 <= tmp_11_1_10_reg_7177;
ap_reg_pp0_iter2_tmp_11_2_10_reg_7187 <= tmp_11_2_10_reg_7187;
ap_reg_pp0_iter2_tmp_11_3_10_reg_7197 <= tmp_11_3_10_reg_7197;
ap_reg_pp0_iter2_tmp_11_4_10_reg_7207 <= tmp_11_4_10_reg_7207;
ap_reg_pp0_iter2_tmp_11_5_10_reg_7217 <= tmp_11_5_10_reg_7217;
ap_reg_pp0_iter2_tmp_11_6_10_reg_7227 <= tmp_11_6_10_reg_7227;
ap_reg_pp0_iter2_tmp_11_7_10_reg_7237 <= tmp_11_7_10_reg_7237;
ap_reg_pp0_iter2_tmp_11_8_10_reg_7247 <= tmp_11_8_10_reg_7247;
ap_reg_pp0_iter2_tmp_11_9_10_reg_7257 <= tmp_11_9_10_reg_7257;
ap_reg_pp0_iter3_tmp_11_0_10_reg_7147 <= ap_reg_pp0_iter2_tmp_11_0_10_reg_7147;
ap_reg_pp0_iter3_tmp_11_10_10_reg_7267 <= ap_reg_pp0_iter2_tmp_11_10_10_reg_7267;
ap_reg_pp0_iter3_tmp_11_11_10_reg_7277 <= ap_reg_pp0_iter2_tmp_11_11_10_reg_7277;
ap_reg_pp0_iter3_tmp_11_12_10_reg_7287 <= ap_reg_pp0_iter2_tmp_11_12_10_reg_7287;
ap_reg_pp0_iter3_tmp_11_13_10_reg_7297 <= ap_reg_pp0_iter2_tmp_11_13_10_reg_7297;
ap_reg_pp0_iter3_tmp_11_14_10_reg_7307 <= ap_reg_pp0_iter2_tmp_11_14_10_reg_7307;
ap_reg_pp0_iter3_tmp_11_15_10_reg_7317 <= ap_reg_pp0_iter2_tmp_11_15_10_reg_7317;
ap_reg_pp0_iter3_tmp_11_1_10_reg_7177 <= ap_reg_pp0_iter2_tmp_11_1_10_reg_7177;
ap_reg_pp0_iter3_tmp_11_2_10_reg_7187 <= ap_reg_pp0_iter2_tmp_11_2_10_reg_7187;
ap_reg_pp0_iter3_tmp_11_3_10_reg_7197 <= ap_reg_pp0_iter2_tmp_11_3_10_reg_7197;
ap_reg_pp0_iter3_tmp_11_4_10_reg_7207 <= ap_reg_pp0_iter2_tmp_11_4_10_reg_7207;
ap_reg_pp0_iter3_tmp_11_5_10_reg_7217 <= ap_reg_pp0_iter2_tmp_11_5_10_reg_7217;
ap_reg_pp0_iter3_tmp_11_6_10_reg_7227 <= ap_reg_pp0_iter2_tmp_11_6_10_reg_7227;
ap_reg_pp0_iter3_tmp_11_7_10_reg_7237 <= ap_reg_pp0_iter2_tmp_11_7_10_reg_7237;
ap_reg_pp0_iter3_tmp_11_8_10_reg_7247 <= ap_reg_pp0_iter2_tmp_11_8_10_reg_7247;
ap_reg_pp0_iter3_tmp_11_9_10_reg_7257 <= ap_reg_pp0_iter2_tmp_11_9_10_reg_7257;
ap_reg_pp0_iter4_tmp_11_0_10_reg_7147 <= ap_reg_pp0_iter3_tmp_11_0_10_reg_7147;
ap_reg_pp0_iter4_tmp_11_10_10_reg_7267 <= ap_reg_pp0_iter3_tmp_11_10_10_reg_7267;
ap_reg_pp0_iter4_tmp_11_11_10_reg_7277 <= ap_reg_pp0_iter3_tmp_11_11_10_reg_7277;
ap_reg_pp0_iter4_tmp_11_12_10_reg_7287 <= ap_reg_pp0_iter3_tmp_11_12_10_reg_7287;
ap_reg_pp0_iter4_tmp_11_13_10_reg_7297 <= ap_reg_pp0_iter3_tmp_11_13_10_reg_7297;
ap_reg_pp0_iter4_tmp_11_14_10_reg_7307 <= ap_reg_pp0_iter3_tmp_11_14_10_reg_7307;
ap_reg_pp0_iter4_tmp_11_15_10_reg_7317 <= ap_reg_pp0_iter3_tmp_11_15_10_reg_7317;
ap_reg_pp0_iter4_tmp_11_1_10_reg_7177 <= ap_reg_pp0_iter3_tmp_11_1_10_reg_7177;
ap_reg_pp0_iter4_tmp_11_2_10_reg_7187 <= ap_reg_pp0_iter3_tmp_11_2_10_reg_7187;
ap_reg_pp0_iter4_tmp_11_3_10_reg_7197 <= ap_reg_pp0_iter3_tmp_11_3_10_reg_7197;
ap_reg_pp0_iter4_tmp_11_4_10_reg_7207 <= ap_reg_pp0_iter3_tmp_11_4_10_reg_7207;
ap_reg_pp0_iter4_tmp_11_5_10_reg_7217 <= ap_reg_pp0_iter3_tmp_11_5_10_reg_7217;
ap_reg_pp0_iter4_tmp_11_6_10_reg_7227 <= ap_reg_pp0_iter3_tmp_11_6_10_reg_7227;
ap_reg_pp0_iter4_tmp_11_7_10_reg_7237 <= ap_reg_pp0_iter3_tmp_11_7_10_reg_7237;
ap_reg_pp0_iter4_tmp_11_8_10_reg_7247 <= ap_reg_pp0_iter3_tmp_11_8_10_reg_7247;
ap_reg_pp0_iter4_tmp_11_9_10_reg_7257 <= ap_reg_pp0_iter3_tmp_11_9_10_reg_7257;
ap_reg_pp0_iter5_tmp_11_0_10_reg_7147 <= ap_reg_pp0_iter4_tmp_11_0_10_reg_7147;
ap_reg_pp0_iter5_tmp_11_10_10_reg_7267 <= ap_reg_pp0_iter4_tmp_11_10_10_reg_7267;
ap_reg_pp0_iter5_tmp_11_11_10_reg_7277 <= ap_reg_pp0_iter4_tmp_11_11_10_reg_7277;
ap_reg_pp0_iter5_tmp_11_12_10_reg_7287 <= ap_reg_pp0_iter4_tmp_11_12_10_reg_7287;
ap_reg_pp0_iter5_tmp_11_13_10_reg_7297 <= ap_reg_pp0_iter4_tmp_11_13_10_reg_7297;
ap_reg_pp0_iter5_tmp_11_14_10_reg_7307 <= ap_reg_pp0_iter4_tmp_11_14_10_reg_7307;
ap_reg_pp0_iter5_tmp_11_15_10_reg_7317 <= ap_reg_pp0_iter4_tmp_11_15_10_reg_7317;
ap_reg_pp0_iter5_tmp_11_1_10_reg_7177 <= ap_reg_pp0_iter4_tmp_11_1_10_reg_7177;
ap_reg_pp0_iter5_tmp_11_2_10_reg_7187 <= ap_reg_pp0_iter4_tmp_11_2_10_reg_7187;
ap_reg_pp0_iter5_tmp_11_3_10_reg_7197 <= ap_reg_pp0_iter4_tmp_11_3_10_reg_7197;
ap_reg_pp0_iter5_tmp_11_4_10_reg_7207 <= ap_reg_pp0_iter4_tmp_11_4_10_reg_7207;
ap_reg_pp0_iter5_tmp_11_5_10_reg_7217 <= ap_reg_pp0_iter4_tmp_11_5_10_reg_7217;
ap_reg_pp0_iter5_tmp_11_6_10_reg_7227 <= ap_reg_pp0_iter4_tmp_11_6_10_reg_7227;
ap_reg_pp0_iter5_tmp_11_7_10_reg_7237 <= ap_reg_pp0_iter4_tmp_11_7_10_reg_7237;
ap_reg_pp0_iter5_tmp_11_8_10_reg_7247 <= ap_reg_pp0_iter4_tmp_11_8_10_reg_7247;
ap_reg_pp0_iter5_tmp_11_9_10_reg_7257 <= ap_reg_pp0_iter4_tmp_11_9_10_reg_7257;
ap_reg_pp0_iter6_tmp_11_0_10_reg_7147 <= ap_reg_pp0_iter5_tmp_11_0_10_reg_7147;
ap_reg_pp0_iter6_tmp_11_10_10_reg_7267 <= ap_reg_pp0_iter5_tmp_11_10_10_reg_7267;
ap_reg_pp0_iter6_tmp_11_11_10_reg_7277 <= ap_reg_pp0_iter5_tmp_11_11_10_reg_7277;
ap_reg_pp0_iter6_tmp_11_12_10_reg_7287 <= ap_reg_pp0_iter5_tmp_11_12_10_reg_7287;
ap_reg_pp0_iter6_tmp_11_13_10_reg_7297 <= ap_reg_pp0_iter5_tmp_11_13_10_reg_7297;
ap_reg_pp0_iter6_tmp_11_14_10_reg_7307 <= ap_reg_pp0_iter5_tmp_11_14_10_reg_7307;
ap_reg_pp0_iter6_tmp_11_15_10_reg_7317 <= ap_reg_pp0_iter5_tmp_11_15_10_reg_7317;
ap_reg_pp0_iter6_tmp_11_1_10_reg_7177 <= ap_reg_pp0_iter5_tmp_11_1_10_reg_7177;
ap_reg_pp0_iter6_tmp_11_2_10_reg_7187 <= ap_reg_pp0_iter5_tmp_11_2_10_reg_7187;
ap_reg_pp0_iter6_tmp_11_3_10_reg_7197 <= ap_reg_pp0_iter5_tmp_11_3_10_reg_7197;
ap_reg_pp0_iter6_tmp_11_4_10_reg_7207 <= ap_reg_pp0_iter5_tmp_11_4_10_reg_7207;
ap_reg_pp0_iter6_tmp_11_5_10_reg_7217 <= ap_reg_pp0_iter5_tmp_11_5_10_reg_7217;
ap_reg_pp0_iter6_tmp_11_6_10_reg_7227 <= ap_reg_pp0_iter5_tmp_11_6_10_reg_7227;
ap_reg_pp0_iter6_tmp_11_7_10_reg_7237 <= ap_reg_pp0_iter5_tmp_11_7_10_reg_7237;
ap_reg_pp0_iter6_tmp_11_8_10_reg_7247 <= ap_reg_pp0_iter5_tmp_11_8_10_reg_7247;
ap_reg_pp0_iter6_tmp_11_9_10_reg_7257 <= ap_reg_pp0_iter5_tmp_11_9_10_reg_7257;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0))) then
ap_reg_pp0_iter2_tmp_11_0_11_reg_7327 <= tmp_11_0_11_reg_7327;
ap_reg_pp0_iter2_tmp_11_10_11_reg_7377 <= tmp_11_10_11_reg_7377;
ap_reg_pp0_iter2_tmp_11_11_11_reg_7382 <= tmp_11_11_11_reg_7382;
ap_reg_pp0_iter2_tmp_11_12_11_reg_7387 <= tmp_11_12_11_reg_7387;
ap_reg_pp0_iter2_tmp_11_13_11_reg_7392 <= tmp_11_13_11_reg_7392;
ap_reg_pp0_iter2_tmp_11_14_11_reg_7397 <= tmp_11_14_11_reg_7397;
ap_reg_pp0_iter2_tmp_11_15_11_reg_7402 <= tmp_11_15_11_reg_7402;
ap_reg_pp0_iter2_tmp_11_1_11_reg_7332 <= tmp_11_1_11_reg_7332;
ap_reg_pp0_iter2_tmp_11_2_11_reg_7337 <= tmp_11_2_11_reg_7337;
ap_reg_pp0_iter2_tmp_11_3_11_reg_7342 <= tmp_11_3_11_reg_7342;
ap_reg_pp0_iter2_tmp_11_4_11_reg_7347 <= tmp_11_4_11_reg_7347;
ap_reg_pp0_iter2_tmp_11_5_11_reg_7352 <= tmp_11_5_11_reg_7352;
ap_reg_pp0_iter2_tmp_11_6_11_reg_7357 <= tmp_11_6_11_reg_7357;
ap_reg_pp0_iter2_tmp_11_7_11_reg_7362 <= tmp_11_7_11_reg_7362;
ap_reg_pp0_iter2_tmp_11_8_11_reg_7367 <= tmp_11_8_11_reg_7367;
ap_reg_pp0_iter2_tmp_11_9_11_reg_7372 <= tmp_11_9_11_reg_7372;
ap_reg_pp0_iter3_tmp_11_0_11_reg_7327 <= ap_reg_pp0_iter2_tmp_11_0_11_reg_7327;
ap_reg_pp0_iter3_tmp_11_10_11_reg_7377 <= ap_reg_pp0_iter2_tmp_11_10_11_reg_7377;
ap_reg_pp0_iter3_tmp_11_11_11_reg_7382 <= ap_reg_pp0_iter2_tmp_11_11_11_reg_7382;
ap_reg_pp0_iter3_tmp_11_12_11_reg_7387 <= ap_reg_pp0_iter2_tmp_11_12_11_reg_7387;
ap_reg_pp0_iter3_tmp_11_13_11_reg_7392 <= ap_reg_pp0_iter2_tmp_11_13_11_reg_7392;
ap_reg_pp0_iter3_tmp_11_14_11_reg_7397 <= ap_reg_pp0_iter2_tmp_11_14_11_reg_7397;
ap_reg_pp0_iter3_tmp_11_15_11_reg_7402 <= ap_reg_pp0_iter2_tmp_11_15_11_reg_7402;
ap_reg_pp0_iter3_tmp_11_1_11_reg_7332 <= ap_reg_pp0_iter2_tmp_11_1_11_reg_7332;
ap_reg_pp0_iter3_tmp_11_2_11_reg_7337 <= ap_reg_pp0_iter2_tmp_11_2_11_reg_7337;
ap_reg_pp0_iter3_tmp_11_3_11_reg_7342 <= ap_reg_pp0_iter2_tmp_11_3_11_reg_7342;
ap_reg_pp0_iter3_tmp_11_4_11_reg_7347 <= ap_reg_pp0_iter2_tmp_11_4_11_reg_7347;
ap_reg_pp0_iter3_tmp_11_5_11_reg_7352 <= ap_reg_pp0_iter2_tmp_11_5_11_reg_7352;
ap_reg_pp0_iter3_tmp_11_6_11_reg_7357 <= ap_reg_pp0_iter2_tmp_11_6_11_reg_7357;
ap_reg_pp0_iter3_tmp_11_7_11_reg_7362 <= ap_reg_pp0_iter2_tmp_11_7_11_reg_7362;
ap_reg_pp0_iter3_tmp_11_8_11_reg_7367 <= ap_reg_pp0_iter2_tmp_11_8_11_reg_7367;
ap_reg_pp0_iter3_tmp_11_9_11_reg_7372 <= ap_reg_pp0_iter2_tmp_11_9_11_reg_7372;
ap_reg_pp0_iter4_tmp_11_0_11_reg_7327 <= ap_reg_pp0_iter3_tmp_11_0_11_reg_7327;
ap_reg_pp0_iter4_tmp_11_10_11_reg_7377 <= ap_reg_pp0_iter3_tmp_11_10_11_reg_7377;
ap_reg_pp0_iter4_tmp_11_11_11_reg_7382 <= ap_reg_pp0_iter3_tmp_11_11_11_reg_7382;
ap_reg_pp0_iter4_tmp_11_12_11_reg_7387 <= ap_reg_pp0_iter3_tmp_11_12_11_reg_7387;
ap_reg_pp0_iter4_tmp_11_13_11_reg_7392 <= ap_reg_pp0_iter3_tmp_11_13_11_reg_7392;
ap_reg_pp0_iter4_tmp_11_14_11_reg_7397 <= ap_reg_pp0_iter3_tmp_11_14_11_reg_7397;
ap_reg_pp0_iter4_tmp_11_15_11_reg_7402 <= ap_reg_pp0_iter3_tmp_11_15_11_reg_7402;
ap_reg_pp0_iter4_tmp_11_1_11_reg_7332 <= ap_reg_pp0_iter3_tmp_11_1_11_reg_7332;
ap_reg_pp0_iter4_tmp_11_2_11_reg_7337 <= ap_reg_pp0_iter3_tmp_11_2_11_reg_7337;
ap_reg_pp0_iter4_tmp_11_3_11_reg_7342 <= ap_reg_pp0_iter3_tmp_11_3_11_reg_7342;
ap_reg_pp0_iter4_tmp_11_4_11_reg_7347 <= ap_reg_pp0_iter3_tmp_11_4_11_reg_7347;
ap_reg_pp0_iter4_tmp_11_5_11_reg_7352 <= ap_reg_pp0_iter3_tmp_11_5_11_reg_7352;
ap_reg_pp0_iter4_tmp_11_6_11_reg_7357 <= ap_reg_pp0_iter3_tmp_11_6_11_reg_7357;
ap_reg_pp0_iter4_tmp_11_7_11_reg_7362 <= ap_reg_pp0_iter3_tmp_11_7_11_reg_7362;
ap_reg_pp0_iter4_tmp_11_8_11_reg_7367 <= ap_reg_pp0_iter3_tmp_11_8_11_reg_7367;
ap_reg_pp0_iter4_tmp_11_9_11_reg_7372 <= ap_reg_pp0_iter3_tmp_11_9_11_reg_7372;
ap_reg_pp0_iter5_tmp_11_0_11_reg_7327 <= ap_reg_pp0_iter4_tmp_11_0_11_reg_7327;
ap_reg_pp0_iter5_tmp_11_10_11_reg_7377 <= ap_reg_pp0_iter4_tmp_11_10_11_reg_7377;
ap_reg_pp0_iter5_tmp_11_11_11_reg_7382 <= ap_reg_pp0_iter4_tmp_11_11_11_reg_7382;
ap_reg_pp0_iter5_tmp_11_12_11_reg_7387 <= ap_reg_pp0_iter4_tmp_11_12_11_reg_7387;
ap_reg_pp0_iter5_tmp_11_13_11_reg_7392 <= ap_reg_pp0_iter4_tmp_11_13_11_reg_7392;
ap_reg_pp0_iter5_tmp_11_14_11_reg_7397 <= ap_reg_pp0_iter4_tmp_11_14_11_reg_7397;
ap_reg_pp0_iter5_tmp_11_15_11_reg_7402 <= ap_reg_pp0_iter4_tmp_11_15_11_reg_7402;
ap_reg_pp0_iter5_tmp_11_1_11_reg_7332 <= ap_reg_pp0_iter4_tmp_11_1_11_reg_7332;
ap_reg_pp0_iter5_tmp_11_2_11_reg_7337 <= ap_reg_pp0_iter4_tmp_11_2_11_reg_7337;
ap_reg_pp0_iter5_tmp_11_3_11_reg_7342 <= ap_reg_pp0_iter4_tmp_11_3_11_reg_7342;
ap_reg_pp0_iter5_tmp_11_4_11_reg_7347 <= ap_reg_pp0_iter4_tmp_11_4_11_reg_7347;
ap_reg_pp0_iter5_tmp_11_5_11_reg_7352 <= ap_reg_pp0_iter4_tmp_11_5_11_reg_7352;
ap_reg_pp0_iter5_tmp_11_6_11_reg_7357 <= ap_reg_pp0_iter4_tmp_11_6_11_reg_7357;
ap_reg_pp0_iter5_tmp_11_7_11_reg_7362 <= ap_reg_pp0_iter4_tmp_11_7_11_reg_7362;
ap_reg_pp0_iter5_tmp_11_8_11_reg_7367 <= ap_reg_pp0_iter4_tmp_11_8_11_reg_7367;
ap_reg_pp0_iter5_tmp_11_9_11_reg_7372 <= ap_reg_pp0_iter4_tmp_11_9_11_reg_7372;
ap_reg_pp0_iter6_tmp_11_0_11_reg_7327 <= ap_reg_pp0_iter5_tmp_11_0_11_reg_7327;
ap_reg_pp0_iter6_tmp_11_10_11_reg_7377 <= ap_reg_pp0_iter5_tmp_11_10_11_reg_7377;
ap_reg_pp0_iter6_tmp_11_11_11_reg_7382 <= ap_reg_pp0_iter5_tmp_11_11_11_reg_7382;
ap_reg_pp0_iter6_tmp_11_12_11_reg_7387 <= ap_reg_pp0_iter5_tmp_11_12_11_reg_7387;
ap_reg_pp0_iter6_tmp_11_13_11_reg_7392 <= ap_reg_pp0_iter5_tmp_11_13_11_reg_7392;
ap_reg_pp0_iter6_tmp_11_14_11_reg_7397 <= ap_reg_pp0_iter5_tmp_11_14_11_reg_7397;
ap_reg_pp0_iter6_tmp_11_15_11_reg_7402 <= ap_reg_pp0_iter5_tmp_11_15_11_reg_7402;
ap_reg_pp0_iter6_tmp_11_1_11_reg_7332 <= ap_reg_pp0_iter5_tmp_11_1_11_reg_7332;
ap_reg_pp0_iter6_tmp_11_2_11_reg_7337 <= ap_reg_pp0_iter5_tmp_11_2_11_reg_7337;
ap_reg_pp0_iter6_tmp_11_3_11_reg_7342 <= ap_reg_pp0_iter5_tmp_11_3_11_reg_7342;
ap_reg_pp0_iter6_tmp_11_4_11_reg_7347 <= ap_reg_pp0_iter5_tmp_11_4_11_reg_7347;
ap_reg_pp0_iter6_tmp_11_5_11_reg_7352 <= ap_reg_pp0_iter5_tmp_11_5_11_reg_7352;
ap_reg_pp0_iter6_tmp_11_6_11_reg_7357 <= ap_reg_pp0_iter5_tmp_11_6_11_reg_7357;
ap_reg_pp0_iter6_tmp_11_7_11_reg_7362 <= ap_reg_pp0_iter5_tmp_11_7_11_reg_7362;
ap_reg_pp0_iter6_tmp_11_8_11_reg_7367 <= ap_reg_pp0_iter5_tmp_11_8_11_reg_7367;
ap_reg_pp0_iter6_tmp_11_9_11_reg_7372 <= ap_reg_pp0_iter5_tmp_11_9_11_reg_7372;
ap_reg_pp0_iter7_tmp_11_0_11_reg_7327 <= ap_reg_pp0_iter6_tmp_11_0_11_reg_7327;
ap_reg_pp0_iter7_tmp_11_10_11_reg_7377 <= ap_reg_pp0_iter6_tmp_11_10_11_reg_7377;
ap_reg_pp0_iter7_tmp_11_11_11_reg_7382 <= ap_reg_pp0_iter6_tmp_11_11_11_reg_7382;
ap_reg_pp0_iter7_tmp_11_12_11_reg_7387 <= ap_reg_pp0_iter6_tmp_11_12_11_reg_7387;
ap_reg_pp0_iter7_tmp_11_13_11_reg_7392 <= ap_reg_pp0_iter6_tmp_11_13_11_reg_7392;
ap_reg_pp0_iter7_tmp_11_14_11_reg_7397 <= ap_reg_pp0_iter6_tmp_11_14_11_reg_7397;
ap_reg_pp0_iter7_tmp_11_15_11_reg_7402 <= ap_reg_pp0_iter6_tmp_11_15_11_reg_7402;
ap_reg_pp0_iter7_tmp_11_1_11_reg_7332 <= ap_reg_pp0_iter6_tmp_11_1_11_reg_7332;
ap_reg_pp0_iter7_tmp_11_2_11_reg_7337 <= ap_reg_pp0_iter6_tmp_11_2_11_reg_7337;
ap_reg_pp0_iter7_tmp_11_3_11_reg_7342 <= ap_reg_pp0_iter6_tmp_11_3_11_reg_7342;
ap_reg_pp0_iter7_tmp_11_4_11_reg_7347 <= ap_reg_pp0_iter6_tmp_11_4_11_reg_7347;
ap_reg_pp0_iter7_tmp_11_5_11_reg_7352 <= ap_reg_pp0_iter6_tmp_11_5_11_reg_7352;
ap_reg_pp0_iter7_tmp_11_6_11_reg_7357 <= ap_reg_pp0_iter6_tmp_11_6_11_reg_7357;
ap_reg_pp0_iter7_tmp_11_7_11_reg_7362 <= ap_reg_pp0_iter6_tmp_11_7_11_reg_7362;
ap_reg_pp0_iter7_tmp_11_8_11_reg_7367 <= ap_reg_pp0_iter6_tmp_11_8_11_reg_7367;
ap_reg_pp0_iter7_tmp_11_9_11_reg_7372 <= ap_reg_pp0_iter6_tmp_11_9_11_reg_7372;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0))) then
ap_reg_pp0_iter2_tmp_11_0_12_reg_7407 <= tmp_11_0_12_reg_7407;
ap_reg_pp0_iter2_tmp_11_10_12_reg_7457 <= tmp_11_10_12_reg_7457;
ap_reg_pp0_iter2_tmp_11_11_12_reg_7462 <= tmp_11_11_12_reg_7462;
ap_reg_pp0_iter2_tmp_11_12_12_reg_7467 <= tmp_11_12_12_reg_7467;
ap_reg_pp0_iter2_tmp_11_13_12_reg_7472 <= tmp_11_13_12_reg_7472;
ap_reg_pp0_iter2_tmp_11_14_12_reg_7477 <= tmp_11_14_12_reg_7477;
ap_reg_pp0_iter2_tmp_11_15_12_reg_7482 <= tmp_11_15_12_reg_7482;
ap_reg_pp0_iter2_tmp_11_1_12_reg_7412 <= tmp_11_1_12_reg_7412;
ap_reg_pp0_iter2_tmp_11_2_12_reg_7417 <= tmp_11_2_12_reg_7417;
ap_reg_pp0_iter2_tmp_11_3_12_reg_7422 <= tmp_11_3_12_reg_7422;
ap_reg_pp0_iter2_tmp_11_4_12_reg_7427 <= tmp_11_4_12_reg_7427;
ap_reg_pp0_iter2_tmp_11_5_12_reg_7432 <= tmp_11_5_12_reg_7432;
ap_reg_pp0_iter2_tmp_11_6_12_reg_7437 <= tmp_11_6_12_reg_7437;
ap_reg_pp0_iter2_tmp_11_7_12_reg_7442 <= tmp_11_7_12_reg_7442;
ap_reg_pp0_iter2_tmp_11_8_12_reg_7447 <= tmp_11_8_12_reg_7447;
ap_reg_pp0_iter2_tmp_11_9_12_reg_7452 <= tmp_11_9_12_reg_7452;
ap_reg_pp0_iter3_tmp_11_0_12_reg_7407 <= ap_reg_pp0_iter2_tmp_11_0_12_reg_7407;
ap_reg_pp0_iter3_tmp_11_10_12_reg_7457 <= ap_reg_pp0_iter2_tmp_11_10_12_reg_7457;
ap_reg_pp0_iter3_tmp_11_11_12_reg_7462 <= ap_reg_pp0_iter2_tmp_11_11_12_reg_7462;
ap_reg_pp0_iter3_tmp_11_12_12_reg_7467 <= ap_reg_pp0_iter2_tmp_11_12_12_reg_7467;
ap_reg_pp0_iter3_tmp_11_13_12_reg_7472 <= ap_reg_pp0_iter2_tmp_11_13_12_reg_7472;
ap_reg_pp0_iter3_tmp_11_14_12_reg_7477 <= ap_reg_pp0_iter2_tmp_11_14_12_reg_7477;
ap_reg_pp0_iter3_tmp_11_15_12_reg_7482 <= ap_reg_pp0_iter2_tmp_11_15_12_reg_7482;
ap_reg_pp0_iter3_tmp_11_1_12_reg_7412 <= ap_reg_pp0_iter2_tmp_11_1_12_reg_7412;
ap_reg_pp0_iter3_tmp_11_2_12_reg_7417 <= ap_reg_pp0_iter2_tmp_11_2_12_reg_7417;
ap_reg_pp0_iter3_tmp_11_3_12_reg_7422 <= ap_reg_pp0_iter2_tmp_11_3_12_reg_7422;
ap_reg_pp0_iter3_tmp_11_4_12_reg_7427 <= ap_reg_pp0_iter2_tmp_11_4_12_reg_7427;
ap_reg_pp0_iter3_tmp_11_5_12_reg_7432 <= ap_reg_pp0_iter2_tmp_11_5_12_reg_7432;
ap_reg_pp0_iter3_tmp_11_6_12_reg_7437 <= ap_reg_pp0_iter2_tmp_11_6_12_reg_7437;
ap_reg_pp0_iter3_tmp_11_7_12_reg_7442 <= ap_reg_pp0_iter2_tmp_11_7_12_reg_7442;
ap_reg_pp0_iter3_tmp_11_8_12_reg_7447 <= ap_reg_pp0_iter2_tmp_11_8_12_reg_7447;
ap_reg_pp0_iter3_tmp_11_9_12_reg_7452 <= ap_reg_pp0_iter2_tmp_11_9_12_reg_7452;
ap_reg_pp0_iter4_tmp_11_0_12_reg_7407 <= ap_reg_pp0_iter3_tmp_11_0_12_reg_7407;
ap_reg_pp0_iter4_tmp_11_10_12_reg_7457 <= ap_reg_pp0_iter3_tmp_11_10_12_reg_7457;
ap_reg_pp0_iter4_tmp_11_11_12_reg_7462 <= ap_reg_pp0_iter3_tmp_11_11_12_reg_7462;
ap_reg_pp0_iter4_tmp_11_12_12_reg_7467 <= ap_reg_pp0_iter3_tmp_11_12_12_reg_7467;
ap_reg_pp0_iter4_tmp_11_13_12_reg_7472 <= ap_reg_pp0_iter3_tmp_11_13_12_reg_7472;
ap_reg_pp0_iter4_tmp_11_14_12_reg_7477 <= ap_reg_pp0_iter3_tmp_11_14_12_reg_7477;
ap_reg_pp0_iter4_tmp_11_15_12_reg_7482 <= ap_reg_pp0_iter3_tmp_11_15_12_reg_7482;
ap_reg_pp0_iter4_tmp_11_1_12_reg_7412 <= ap_reg_pp0_iter3_tmp_11_1_12_reg_7412;
ap_reg_pp0_iter4_tmp_11_2_12_reg_7417 <= ap_reg_pp0_iter3_tmp_11_2_12_reg_7417;
ap_reg_pp0_iter4_tmp_11_3_12_reg_7422 <= ap_reg_pp0_iter3_tmp_11_3_12_reg_7422;
ap_reg_pp0_iter4_tmp_11_4_12_reg_7427 <= ap_reg_pp0_iter3_tmp_11_4_12_reg_7427;
ap_reg_pp0_iter4_tmp_11_5_12_reg_7432 <= ap_reg_pp0_iter3_tmp_11_5_12_reg_7432;
ap_reg_pp0_iter4_tmp_11_6_12_reg_7437 <= ap_reg_pp0_iter3_tmp_11_6_12_reg_7437;
ap_reg_pp0_iter4_tmp_11_7_12_reg_7442 <= ap_reg_pp0_iter3_tmp_11_7_12_reg_7442;
ap_reg_pp0_iter4_tmp_11_8_12_reg_7447 <= ap_reg_pp0_iter3_tmp_11_8_12_reg_7447;
ap_reg_pp0_iter4_tmp_11_9_12_reg_7452 <= ap_reg_pp0_iter3_tmp_11_9_12_reg_7452;
ap_reg_pp0_iter5_tmp_11_0_12_reg_7407 <= ap_reg_pp0_iter4_tmp_11_0_12_reg_7407;
ap_reg_pp0_iter5_tmp_11_10_12_reg_7457 <= ap_reg_pp0_iter4_tmp_11_10_12_reg_7457;
ap_reg_pp0_iter5_tmp_11_11_12_reg_7462 <= ap_reg_pp0_iter4_tmp_11_11_12_reg_7462;
ap_reg_pp0_iter5_tmp_11_12_12_reg_7467 <= ap_reg_pp0_iter4_tmp_11_12_12_reg_7467;
ap_reg_pp0_iter5_tmp_11_13_12_reg_7472 <= ap_reg_pp0_iter4_tmp_11_13_12_reg_7472;
ap_reg_pp0_iter5_tmp_11_14_12_reg_7477 <= ap_reg_pp0_iter4_tmp_11_14_12_reg_7477;
ap_reg_pp0_iter5_tmp_11_15_12_reg_7482 <= ap_reg_pp0_iter4_tmp_11_15_12_reg_7482;
ap_reg_pp0_iter5_tmp_11_1_12_reg_7412 <= ap_reg_pp0_iter4_tmp_11_1_12_reg_7412;
ap_reg_pp0_iter5_tmp_11_2_12_reg_7417 <= ap_reg_pp0_iter4_tmp_11_2_12_reg_7417;
ap_reg_pp0_iter5_tmp_11_3_12_reg_7422 <= ap_reg_pp0_iter4_tmp_11_3_12_reg_7422;
ap_reg_pp0_iter5_tmp_11_4_12_reg_7427 <= ap_reg_pp0_iter4_tmp_11_4_12_reg_7427;
ap_reg_pp0_iter5_tmp_11_5_12_reg_7432 <= ap_reg_pp0_iter4_tmp_11_5_12_reg_7432;
ap_reg_pp0_iter5_tmp_11_6_12_reg_7437 <= ap_reg_pp0_iter4_tmp_11_6_12_reg_7437;
ap_reg_pp0_iter5_tmp_11_7_12_reg_7442 <= ap_reg_pp0_iter4_tmp_11_7_12_reg_7442;
ap_reg_pp0_iter5_tmp_11_8_12_reg_7447 <= ap_reg_pp0_iter4_tmp_11_8_12_reg_7447;
ap_reg_pp0_iter5_tmp_11_9_12_reg_7452 <= ap_reg_pp0_iter4_tmp_11_9_12_reg_7452;
ap_reg_pp0_iter6_tmp_11_0_12_reg_7407 <= ap_reg_pp0_iter5_tmp_11_0_12_reg_7407;
ap_reg_pp0_iter6_tmp_11_10_12_reg_7457 <= ap_reg_pp0_iter5_tmp_11_10_12_reg_7457;
ap_reg_pp0_iter6_tmp_11_11_12_reg_7462 <= ap_reg_pp0_iter5_tmp_11_11_12_reg_7462;
ap_reg_pp0_iter6_tmp_11_12_12_reg_7467 <= ap_reg_pp0_iter5_tmp_11_12_12_reg_7467;
ap_reg_pp0_iter6_tmp_11_13_12_reg_7472 <= ap_reg_pp0_iter5_tmp_11_13_12_reg_7472;
ap_reg_pp0_iter6_tmp_11_14_12_reg_7477 <= ap_reg_pp0_iter5_tmp_11_14_12_reg_7477;
ap_reg_pp0_iter6_tmp_11_15_12_reg_7482 <= ap_reg_pp0_iter5_tmp_11_15_12_reg_7482;
ap_reg_pp0_iter6_tmp_11_1_12_reg_7412 <= ap_reg_pp0_iter5_tmp_11_1_12_reg_7412;
ap_reg_pp0_iter6_tmp_11_2_12_reg_7417 <= ap_reg_pp0_iter5_tmp_11_2_12_reg_7417;
ap_reg_pp0_iter6_tmp_11_3_12_reg_7422 <= ap_reg_pp0_iter5_tmp_11_3_12_reg_7422;
ap_reg_pp0_iter6_tmp_11_4_12_reg_7427 <= ap_reg_pp0_iter5_tmp_11_4_12_reg_7427;
ap_reg_pp0_iter6_tmp_11_5_12_reg_7432 <= ap_reg_pp0_iter5_tmp_11_5_12_reg_7432;
ap_reg_pp0_iter6_tmp_11_6_12_reg_7437 <= ap_reg_pp0_iter5_tmp_11_6_12_reg_7437;
ap_reg_pp0_iter6_tmp_11_7_12_reg_7442 <= ap_reg_pp0_iter5_tmp_11_7_12_reg_7442;
ap_reg_pp0_iter6_tmp_11_8_12_reg_7447 <= ap_reg_pp0_iter5_tmp_11_8_12_reg_7447;
ap_reg_pp0_iter6_tmp_11_9_12_reg_7452 <= ap_reg_pp0_iter5_tmp_11_9_12_reg_7452;
ap_reg_pp0_iter7_tmp_11_0_12_reg_7407 <= ap_reg_pp0_iter6_tmp_11_0_12_reg_7407;
ap_reg_pp0_iter7_tmp_11_10_12_reg_7457 <= ap_reg_pp0_iter6_tmp_11_10_12_reg_7457;
ap_reg_pp0_iter7_tmp_11_11_12_reg_7462 <= ap_reg_pp0_iter6_tmp_11_11_12_reg_7462;
ap_reg_pp0_iter7_tmp_11_12_12_reg_7467 <= ap_reg_pp0_iter6_tmp_11_12_12_reg_7467;
ap_reg_pp0_iter7_tmp_11_13_12_reg_7472 <= ap_reg_pp0_iter6_tmp_11_13_12_reg_7472;
ap_reg_pp0_iter7_tmp_11_14_12_reg_7477 <= ap_reg_pp0_iter6_tmp_11_14_12_reg_7477;
ap_reg_pp0_iter7_tmp_11_15_12_reg_7482 <= ap_reg_pp0_iter6_tmp_11_15_12_reg_7482;
ap_reg_pp0_iter7_tmp_11_1_12_reg_7412 <= ap_reg_pp0_iter6_tmp_11_1_12_reg_7412;
ap_reg_pp0_iter7_tmp_11_2_12_reg_7417 <= ap_reg_pp0_iter6_tmp_11_2_12_reg_7417;
ap_reg_pp0_iter7_tmp_11_3_12_reg_7422 <= ap_reg_pp0_iter6_tmp_11_3_12_reg_7422;
ap_reg_pp0_iter7_tmp_11_4_12_reg_7427 <= ap_reg_pp0_iter6_tmp_11_4_12_reg_7427;
ap_reg_pp0_iter7_tmp_11_5_12_reg_7432 <= ap_reg_pp0_iter6_tmp_11_5_12_reg_7432;
ap_reg_pp0_iter7_tmp_11_6_12_reg_7437 <= ap_reg_pp0_iter6_tmp_11_6_12_reg_7437;
ap_reg_pp0_iter7_tmp_11_7_12_reg_7442 <= ap_reg_pp0_iter6_tmp_11_7_12_reg_7442;
ap_reg_pp0_iter7_tmp_11_8_12_reg_7447 <= ap_reg_pp0_iter6_tmp_11_8_12_reg_7447;
ap_reg_pp0_iter7_tmp_11_9_12_reg_7452 <= ap_reg_pp0_iter6_tmp_11_9_12_reg_7452;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0))) then
ap_reg_pp0_iter2_tmp_11_0_13_reg_7487 <= tmp_11_0_13_reg_7487;
ap_reg_pp0_iter2_tmp_11_10_13_reg_7537 <= tmp_11_10_13_reg_7537;
ap_reg_pp0_iter2_tmp_11_11_13_reg_7542 <= tmp_11_11_13_reg_7542;
ap_reg_pp0_iter2_tmp_11_12_13_reg_7547 <= tmp_11_12_13_reg_7547;
ap_reg_pp0_iter2_tmp_11_13_13_reg_7552 <= tmp_11_13_13_reg_7552;
ap_reg_pp0_iter2_tmp_11_14_13_reg_7557 <= tmp_11_14_13_reg_7557;
ap_reg_pp0_iter2_tmp_11_15_13_reg_7562 <= tmp_11_15_13_reg_7562;
ap_reg_pp0_iter2_tmp_11_1_13_reg_7492 <= tmp_11_1_13_reg_7492;
ap_reg_pp0_iter2_tmp_11_2_13_reg_7497 <= tmp_11_2_13_reg_7497;
ap_reg_pp0_iter2_tmp_11_3_13_reg_7502 <= tmp_11_3_13_reg_7502;
ap_reg_pp0_iter2_tmp_11_4_13_reg_7507 <= tmp_11_4_13_reg_7507;
ap_reg_pp0_iter2_tmp_11_5_13_reg_7512 <= tmp_11_5_13_reg_7512;
ap_reg_pp0_iter2_tmp_11_6_13_reg_7517 <= tmp_11_6_13_reg_7517;
ap_reg_pp0_iter2_tmp_11_7_13_reg_7522 <= tmp_11_7_13_reg_7522;
ap_reg_pp0_iter2_tmp_11_8_13_reg_7527 <= tmp_11_8_13_reg_7527;
ap_reg_pp0_iter2_tmp_11_9_13_reg_7532 <= tmp_11_9_13_reg_7532;
ap_reg_pp0_iter3_tmp_11_0_13_reg_7487 <= ap_reg_pp0_iter2_tmp_11_0_13_reg_7487;
ap_reg_pp0_iter3_tmp_11_10_13_reg_7537 <= ap_reg_pp0_iter2_tmp_11_10_13_reg_7537;
ap_reg_pp0_iter3_tmp_11_11_13_reg_7542 <= ap_reg_pp0_iter2_tmp_11_11_13_reg_7542;
ap_reg_pp0_iter3_tmp_11_12_13_reg_7547 <= ap_reg_pp0_iter2_tmp_11_12_13_reg_7547;
ap_reg_pp0_iter3_tmp_11_13_13_reg_7552 <= ap_reg_pp0_iter2_tmp_11_13_13_reg_7552;
ap_reg_pp0_iter3_tmp_11_14_13_reg_7557 <= ap_reg_pp0_iter2_tmp_11_14_13_reg_7557;
ap_reg_pp0_iter3_tmp_11_15_13_reg_7562 <= ap_reg_pp0_iter2_tmp_11_15_13_reg_7562;
ap_reg_pp0_iter3_tmp_11_1_13_reg_7492 <= ap_reg_pp0_iter2_tmp_11_1_13_reg_7492;
ap_reg_pp0_iter3_tmp_11_2_13_reg_7497 <= ap_reg_pp0_iter2_tmp_11_2_13_reg_7497;
ap_reg_pp0_iter3_tmp_11_3_13_reg_7502 <= ap_reg_pp0_iter2_tmp_11_3_13_reg_7502;
ap_reg_pp0_iter3_tmp_11_4_13_reg_7507 <= ap_reg_pp0_iter2_tmp_11_4_13_reg_7507;
ap_reg_pp0_iter3_tmp_11_5_13_reg_7512 <= ap_reg_pp0_iter2_tmp_11_5_13_reg_7512;
ap_reg_pp0_iter3_tmp_11_6_13_reg_7517 <= ap_reg_pp0_iter2_tmp_11_6_13_reg_7517;
ap_reg_pp0_iter3_tmp_11_7_13_reg_7522 <= ap_reg_pp0_iter2_tmp_11_7_13_reg_7522;
ap_reg_pp0_iter3_tmp_11_8_13_reg_7527 <= ap_reg_pp0_iter2_tmp_11_8_13_reg_7527;
ap_reg_pp0_iter3_tmp_11_9_13_reg_7532 <= ap_reg_pp0_iter2_tmp_11_9_13_reg_7532;
ap_reg_pp0_iter4_tmp_11_0_13_reg_7487 <= ap_reg_pp0_iter3_tmp_11_0_13_reg_7487;
ap_reg_pp0_iter4_tmp_11_10_13_reg_7537 <= ap_reg_pp0_iter3_tmp_11_10_13_reg_7537;
ap_reg_pp0_iter4_tmp_11_11_13_reg_7542 <= ap_reg_pp0_iter3_tmp_11_11_13_reg_7542;
ap_reg_pp0_iter4_tmp_11_12_13_reg_7547 <= ap_reg_pp0_iter3_tmp_11_12_13_reg_7547;
ap_reg_pp0_iter4_tmp_11_13_13_reg_7552 <= ap_reg_pp0_iter3_tmp_11_13_13_reg_7552;
ap_reg_pp0_iter4_tmp_11_14_13_reg_7557 <= ap_reg_pp0_iter3_tmp_11_14_13_reg_7557;
ap_reg_pp0_iter4_tmp_11_15_13_reg_7562 <= ap_reg_pp0_iter3_tmp_11_15_13_reg_7562;
ap_reg_pp0_iter4_tmp_11_1_13_reg_7492 <= ap_reg_pp0_iter3_tmp_11_1_13_reg_7492;
ap_reg_pp0_iter4_tmp_11_2_13_reg_7497 <= ap_reg_pp0_iter3_tmp_11_2_13_reg_7497;
ap_reg_pp0_iter4_tmp_11_3_13_reg_7502 <= ap_reg_pp0_iter3_tmp_11_3_13_reg_7502;
ap_reg_pp0_iter4_tmp_11_4_13_reg_7507 <= ap_reg_pp0_iter3_tmp_11_4_13_reg_7507;
ap_reg_pp0_iter4_tmp_11_5_13_reg_7512 <= ap_reg_pp0_iter3_tmp_11_5_13_reg_7512;
ap_reg_pp0_iter4_tmp_11_6_13_reg_7517 <= ap_reg_pp0_iter3_tmp_11_6_13_reg_7517;
ap_reg_pp0_iter4_tmp_11_7_13_reg_7522 <= ap_reg_pp0_iter3_tmp_11_7_13_reg_7522;
ap_reg_pp0_iter4_tmp_11_8_13_reg_7527 <= ap_reg_pp0_iter3_tmp_11_8_13_reg_7527;
ap_reg_pp0_iter4_tmp_11_9_13_reg_7532 <= ap_reg_pp0_iter3_tmp_11_9_13_reg_7532;
ap_reg_pp0_iter5_tmp_11_0_13_reg_7487 <= ap_reg_pp0_iter4_tmp_11_0_13_reg_7487;
ap_reg_pp0_iter5_tmp_11_10_13_reg_7537 <= ap_reg_pp0_iter4_tmp_11_10_13_reg_7537;
ap_reg_pp0_iter5_tmp_11_11_13_reg_7542 <= ap_reg_pp0_iter4_tmp_11_11_13_reg_7542;
ap_reg_pp0_iter5_tmp_11_12_13_reg_7547 <= ap_reg_pp0_iter4_tmp_11_12_13_reg_7547;
ap_reg_pp0_iter5_tmp_11_13_13_reg_7552 <= ap_reg_pp0_iter4_tmp_11_13_13_reg_7552;
ap_reg_pp0_iter5_tmp_11_14_13_reg_7557 <= ap_reg_pp0_iter4_tmp_11_14_13_reg_7557;
ap_reg_pp0_iter5_tmp_11_15_13_reg_7562 <= ap_reg_pp0_iter4_tmp_11_15_13_reg_7562;
ap_reg_pp0_iter5_tmp_11_1_13_reg_7492 <= ap_reg_pp0_iter4_tmp_11_1_13_reg_7492;
ap_reg_pp0_iter5_tmp_11_2_13_reg_7497 <= ap_reg_pp0_iter4_tmp_11_2_13_reg_7497;
ap_reg_pp0_iter5_tmp_11_3_13_reg_7502 <= ap_reg_pp0_iter4_tmp_11_3_13_reg_7502;
ap_reg_pp0_iter5_tmp_11_4_13_reg_7507 <= ap_reg_pp0_iter4_tmp_11_4_13_reg_7507;
ap_reg_pp0_iter5_tmp_11_5_13_reg_7512 <= ap_reg_pp0_iter4_tmp_11_5_13_reg_7512;
ap_reg_pp0_iter5_tmp_11_6_13_reg_7517 <= ap_reg_pp0_iter4_tmp_11_6_13_reg_7517;
ap_reg_pp0_iter5_tmp_11_7_13_reg_7522 <= ap_reg_pp0_iter4_tmp_11_7_13_reg_7522;
ap_reg_pp0_iter5_tmp_11_8_13_reg_7527 <= ap_reg_pp0_iter4_tmp_11_8_13_reg_7527;
ap_reg_pp0_iter5_tmp_11_9_13_reg_7532 <= ap_reg_pp0_iter4_tmp_11_9_13_reg_7532;
ap_reg_pp0_iter6_tmp_11_0_13_reg_7487 <= ap_reg_pp0_iter5_tmp_11_0_13_reg_7487;
ap_reg_pp0_iter6_tmp_11_10_13_reg_7537 <= ap_reg_pp0_iter5_tmp_11_10_13_reg_7537;
ap_reg_pp0_iter6_tmp_11_11_13_reg_7542 <= ap_reg_pp0_iter5_tmp_11_11_13_reg_7542;
ap_reg_pp0_iter6_tmp_11_12_13_reg_7547 <= ap_reg_pp0_iter5_tmp_11_12_13_reg_7547;
ap_reg_pp0_iter6_tmp_11_13_13_reg_7552 <= ap_reg_pp0_iter5_tmp_11_13_13_reg_7552;
ap_reg_pp0_iter6_tmp_11_14_13_reg_7557 <= ap_reg_pp0_iter5_tmp_11_14_13_reg_7557;
ap_reg_pp0_iter6_tmp_11_15_13_reg_7562 <= ap_reg_pp0_iter5_tmp_11_15_13_reg_7562;
ap_reg_pp0_iter6_tmp_11_1_13_reg_7492 <= ap_reg_pp0_iter5_tmp_11_1_13_reg_7492;
ap_reg_pp0_iter6_tmp_11_2_13_reg_7497 <= ap_reg_pp0_iter5_tmp_11_2_13_reg_7497;
ap_reg_pp0_iter6_tmp_11_3_13_reg_7502 <= ap_reg_pp0_iter5_tmp_11_3_13_reg_7502;
ap_reg_pp0_iter6_tmp_11_4_13_reg_7507 <= ap_reg_pp0_iter5_tmp_11_4_13_reg_7507;
ap_reg_pp0_iter6_tmp_11_5_13_reg_7512 <= ap_reg_pp0_iter5_tmp_11_5_13_reg_7512;
ap_reg_pp0_iter6_tmp_11_6_13_reg_7517 <= ap_reg_pp0_iter5_tmp_11_6_13_reg_7517;
ap_reg_pp0_iter6_tmp_11_7_13_reg_7522 <= ap_reg_pp0_iter5_tmp_11_7_13_reg_7522;
ap_reg_pp0_iter6_tmp_11_8_13_reg_7527 <= ap_reg_pp0_iter5_tmp_11_8_13_reg_7527;
ap_reg_pp0_iter6_tmp_11_9_13_reg_7532 <= ap_reg_pp0_iter5_tmp_11_9_13_reg_7532;
ap_reg_pp0_iter7_tmp_11_0_13_reg_7487 <= ap_reg_pp0_iter6_tmp_11_0_13_reg_7487;
ap_reg_pp0_iter7_tmp_11_10_13_reg_7537 <= ap_reg_pp0_iter6_tmp_11_10_13_reg_7537;
ap_reg_pp0_iter7_tmp_11_11_13_reg_7542 <= ap_reg_pp0_iter6_tmp_11_11_13_reg_7542;
ap_reg_pp0_iter7_tmp_11_12_13_reg_7547 <= ap_reg_pp0_iter6_tmp_11_12_13_reg_7547;
ap_reg_pp0_iter7_tmp_11_13_13_reg_7552 <= ap_reg_pp0_iter6_tmp_11_13_13_reg_7552;
ap_reg_pp0_iter7_tmp_11_14_13_reg_7557 <= ap_reg_pp0_iter6_tmp_11_14_13_reg_7557;
ap_reg_pp0_iter7_tmp_11_15_13_reg_7562 <= ap_reg_pp0_iter6_tmp_11_15_13_reg_7562;
ap_reg_pp0_iter7_tmp_11_1_13_reg_7492 <= ap_reg_pp0_iter6_tmp_11_1_13_reg_7492;
ap_reg_pp0_iter7_tmp_11_2_13_reg_7497 <= ap_reg_pp0_iter6_tmp_11_2_13_reg_7497;
ap_reg_pp0_iter7_tmp_11_3_13_reg_7502 <= ap_reg_pp0_iter6_tmp_11_3_13_reg_7502;
ap_reg_pp0_iter7_tmp_11_4_13_reg_7507 <= ap_reg_pp0_iter6_tmp_11_4_13_reg_7507;
ap_reg_pp0_iter7_tmp_11_5_13_reg_7512 <= ap_reg_pp0_iter6_tmp_11_5_13_reg_7512;
ap_reg_pp0_iter7_tmp_11_6_13_reg_7517 <= ap_reg_pp0_iter6_tmp_11_6_13_reg_7517;
ap_reg_pp0_iter7_tmp_11_7_13_reg_7522 <= ap_reg_pp0_iter6_tmp_11_7_13_reg_7522;
ap_reg_pp0_iter7_tmp_11_8_13_reg_7527 <= ap_reg_pp0_iter6_tmp_11_8_13_reg_7527;
ap_reg_pp0_iter7_tmp_11_9_13_reg_7532 <= ap_reg_pp0_iter6_tmp_11_9_13_reg_7532;
ap_reg_pp0_iter8_tmp_11_0_13_reg_7487 <= ap_reg_pp0_iter7_tmp_11_0_13_reg_7487;
ap_reg_pp0_iter8_tmp_11_10_13_reg_7537 <= ap_reg_pp0_iter7_tmp_11_10_13_reg_7537;
ap_reg_pp0_iter8_tmp_11_11_13_reg_7542 <= ap_reg_pp0_iter7_tmp_11_11_13_reg_7542;
ap_reg_pp0_iter8_tmp_11_12_13_reg_7547 <= ap_reg_pp0_iter7_tmp_11_12_13_reg_7547;
ap_reg_pp0_iter8_tmp_11_13_13_reg_7552 <= ap_reg_pp0_iter7_tmp_11_13_13_reg_7552;
ap_reg_pp0_iter8_tmp_11_14_13_reg_7557 <= ap_reg_pp0_iter7_tmp_11_14_13_reg_7557;
ap_reg_pp0_iter8_tmp_11_15_13_reg_7562 <= ap_reg_pp0_iter7_tmp_11_15_13_reg_7562;
ap_reg_pp0_iter8_tmp_11_1_13_reg_7492 <= ap_reg_pp0_iter7_tmp_11_1_13_reg_7492;
ap_reg_pp0_iter8_tmp_11_2_13_reg_7497 <= ap_reg_pp0_iter7_tmp_11_2_13_reg_7497;
ap_reg_pp0_iter8_tmp_11_3_13_reg_7502 <= ap_reg_pp0_iter7_tmp_11_3_13_reg_7502;
ap_reg_pp0_iter8_tmp_11_4_13_reg_7507 <= ap_reg_pp0_iter7_tmp_11_4_13_reg_7507;
ap_reg_pp0_iter8_tmp_11_5_13_reg_7512 <= ap_reg_pp0_iter7_tmp_11_5_13_reg_7512;
ap_reg_pp0_iter8_tmp_11_6_13_reg_7517 <= ap_reg_pp0_iter7_tmp_11_6_13_reg_7517;
ap_reg_pp0_iter8_tmp_11_7_13_reg_7522 <= ap_reg_pp0_iter7_tmp_11_7_13_reg_7522;
ap_reg_pp0_iter8_tmp_11_8_13_reg_7527 <= ap_reg_pp0_iter7_tmp_11_8_13_reg_7527;
ap_reg_pp0_iter8_tmp_11_9_13_reg_7532 <= ap_reg_pp0_iter7_tmp_11_9_13_reg_7532;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00011001 = ap_const_boolean_0))) then
ap_reg_pp0_iter2_tmp_11_0_14_reg_7567 <= tmp_11_0_14_reg_7567;
ap_reg_pp0_iter2_tmp_11_10_14_reg_7617 <= tmp_11_10_14_reg_7617;
ap_reg_pp0_iter2_tmp_11_11_14_reg_7622 <= tmp_11_11_14_reg_7622;
ap_reg_pp0_iter2_tmp_11_12_14_reg_7627 <= tmp_11_12_14_reg_7627;
ap_reg_pp0_iter2_tmp_11_13_14_reg_7632 <= tmp_11_13_14_reg_7632;
ap_reg_pp0_iter2_tmp_11_14_14_reg_7637 <= tmp_11_14_14_reg_7637;
ap_reg_pp0_iter2_tmp_11_15_14_reg_7642 <= tmp_11_15_14_reg_7642;
ap_reg_pp0_iter2_tmp_11_1_14_reg_7572 <= tmp_11_1_14_reg_7572;
ap_reg_pp0_iter2_tmp_11_2_14_reg_7577 <= tmp_11_2_14_reg_7577;
ap_reg_pp0_iter2_tmp_11_3_14_reg_7582 <= tmp_11_3_14_reg_7582;
ap_reg_pp0_iter2_tmp_11_4_14_reg_7587 <= tmp_11_4_14_reg_7587;
ap_reg_pp0_iter2_tmp_11_5_14_reg_7592 <= tmp_11_5_14_reg_7592;
ap_reg_pp0_iter2_tmp_11_6_14_reg_7597 <= tmp_11_6_14_reg_7597;
ap_reg_pp0_iter2_tmp_11_7_14_reg_7602 <= tmp_11_7_14_reg_7602;
ap_reg_pp0_iter2_tmp_11_8_14_reg_7607 <= tmp_11_8_14_reg_7607;
ap_reg_pp0_iter2_tmp_11_9_14_reg_7612 <= tmp_11_9_14_reg_7612;
ap_reg_pp0_iter3_tmp_11_0_14_reg_7567 <= ap_reg_pp0_iter2_tmp_11_0_14_reg_7567;
ap_reg_pp0_iter3_tmp_11_10_14_reg_7617 <= ap_reg_pp0_iter2_tmp_11_10_14_reg_7617;
ap_reg_pp0_iter3_tmp_11_11_14_reg_7622 <= ap_reg_pp0_iter2_tmp_11_11_14_reg_7622;
ap_reg_pp0_iter3_tmp_11_12_14_reg_7627 <= ap_reg_pp0_iter2_tmp_11_12_14_reg_7627;
ap_reg_pp0_iter3_tmp_11_13_14_reg_7632 <= ap_reg_pp0_iter2_tmp_11_13_14_reg_7632;
ap_reg_pp0_iter3_tmp_11_14_14_reg_7637 <= ap_reg_pp0_iter2_tmp_11_14_14_reg_7637;
ap_reg_pp0_iter3_tmp_11_15_14_reg_7642 <= ap_reg_pp0_iter2_tmp_11_15_14_reg_7642;
ap_reg_pp0_iter3_tmp_11_1_14_reg_7572 <= ap_reg_pp0_iter2_tmp_11_1_14_reg_7572;
ap_reg_pp0_iter3_tmp_11_2_14_reg_7577 <= ap_reg_pp0_iter2_tmp_11_2_14_reg_7577;
ap_reg_pp0_iter3_tmp_11_3_14_reg_7582 <= ap_reg_pp0_iter2_tmp_11_3_14_reg_7582;
ap_reg_pp0_iter3_tmp_11_4_14_reg_7587 <= ap_reg_pp0_iter2_tmp_11_4_14_reg_7587;
ap_reg_pp0_iter3_tmp_11_5_14_reg_7592 <= ap_reg_pp0_iter2_tmp_11_5_14_reg_7592;
ap_reg_pp0_iter3_tmp_11_6_14_reg_7597 <= ap_reg_pp0_iter2_tmp_11_6_14_reg_7597;
ap_reg_pp0_iter3_tmp_11_7_14_reg_7602 <= ap_reg_pp0_iter2_tmp_11_7_14_reg_7602;
ap_reg_pp0_iter3_tmp_11_8_14_reg_7607 <= ap_reg_pp0_iter2_tmp_11_8_14_reg_7607;
ap_reg_pp0_iter3_tmp_11_9_14_reg_7612 <= ap_reg_pp0_iter2_tmp_11_9_14_reg_7612;
ap_reg_pp0_iter4_tmp_11_0_14_reg_7567 <= ap_reg_pp0_iter3_tmp_11_0_14_reg_7567;
ap_reg_pp0_iter4_tmp_11_10_14_reg_7617 <= ap_reg_pp0_iter3_tmp_11_10_14_reg_7617;
ap_reg_pp0_iter4_tmp_11_11_14_reg_7622 <= ap_reg_pp0_iter3_tmp_11_11_14_reg_7622;
ap_reg_pp0_iter4_tmp_11_12_14_reg_7627 <= ap_reg_pp0_iter3_tmp_11_12_14_reg_7627;
ap_reg_pp0_iter4_tmp_11_13_14_reg_7632 <= ap_reg_pp0_iter3_tmp_11_13_14_reg_7632;
ap_reg_pp0_iter4_tmp_11_14_14_reg_7637 <= ap_reg_pp0_iter3_tmp_11_14_14_reg_7637;
ap_reg_pp0_iter4_tmp_11_15_14_reg_7642 <= ap_reg_pp0_iter3_tmp_11_15_14_reg_7642;
ap_reg_pp0_iter4_tmp_11_1_14_reg_7572 <= ap_reg_pp0_iter3_tmp_11_1_14_reg_7572;
ap_reg_pp0_iter4_tmp_11_2_14_reg_7577 <= ap_reg_pp0_iter3_tmp_11_2_14_reg_7577;
ap_reg_pp0_iter4_tmp_11_3_14_reg_7582 <= ap_reg_pp0_iter3_tmp_11_3_14_reg_7582;
ap_reg_pp0_iter4_tmp_11_4_14_reg_7587 <= ap_reg_pp0_iter3_tmp_11_4_14_reg_7587;
ap_reg_pp0_iter4_tmp_11_5_14_reg_7592 <= ap_reg_pp0_iter3_tmp_11_5_14_reg_7592;
ap_reg_pp0_iter4_tmp_11_6_14_reg_7597 <= ap_reg_pp0_iter3_tmp_11_6_14_reg_7597;
ap_reg_pp0_iter4_tmp_11_7_14_reg_7602 <= ap_reg_pp0_iter3_tmp_11_7_14_reg_7602;
ap_reg_pp0_iter4_tmp_11_8_14_reg_7607 <= ap_reg_pp0_iter3_tmp_11_8_14_reg_7607;
ap_reg_pp0_iter4_tmp_11_9_14_reg_7612 <= ap_reg_pp0_iter3_tmp_11_9_14_reg_7612;
ap_reg_pp0_iter5_tmp_11_0_14_reg_7567 <= ap_reg_pp0_iter4_tmp_11_0_14_reg_7567;
ap_reg_pp0_iter5_tmp_11_10_14_reg_7617 <= ap_reg_pp0_iter4_tmp_11_10_14_reg_7617;
ap_reg_pp0_iter5_tmp_11_11_14_reg_7622 <= ap_reg_pp0_iter4_tmp_11_11_14_reg_7622;
ap_reg_pp0_iter5_tmp_11_12_14_reg_7627 <= ap_reg_pp0_iter4_tmp_11_12_14_reg_7627;
ap_reg_pp0_iter5_tmp_11_13_14_reg_7632 <= ap_reg_pp0_iter4_tmp_11_13_14_reg_7632;
ap_reg_pp0_iter5_tmp_11_14_14_reg_7637 <= ap_reg_pp0_iter4_tmp_11_14_14_reg_7637;
ap_reg_pp0_iter5_tmp_11_15_14_reg_7642 <= ap_reg_pp0_iter4_tmp_11_15_14_reg_7642;
ap_reg_pp0_iter5_tmp_11_1_14_reg_7572 <= ap_reg_pp0_iter4_tmp_11_1_14_reg_7572;
ap_reg_pp0_iter5_tmp_11_2_14_reg_7577 <= ap_reg_pp0_iter4_tmp_11_2_14_reg_7577;
ap_reg_pp0_iter5_tmp_11_3_14_reg_7582 <= ap_reg_pp0_iter4_tmp_11_3_14_reg_7582;
ap_reg_pp0_iter5_tmp_11_4_14_reg_7587 <= ap_reg_pp0_iter4_tmp_11_4_14_reg_7587;
ap_reg_pp0_iter5_tmp_11_5_14_reg_7592 <= ap_reg_pp0_iter4_tmp_11_5_14_reg_7592;
ap_reg_pp0_iter5_tmp_11_6_14_reg_7597 <= ap_reg_pp0_iter4_tmp_11_6_14_reg_7597;
ap_reg_pp0_iter5_tmp_11_7_14_reg_7602 <= ap_reg_pp0_iter4_tmp_11_7_14_reg_7602;
ap_reg_pp0_iter5_tmp_11_8_14_reg_7607 <= ap_reg_pp0_iter4_tmp_11_8_14_reg_7607;
ap_reg_pp0_iter5_tmp_11_9_14_reg_7612 <= ap_reg_pp0_iter4_tmp_11_9_14_reg_7612;
ap_reg_pp0_iter6_tmp_11_0_14_reg_7567 <= ap_reg_pp0_iter5_tmp_11_0_14_reg_7567;
ap_reg_pp0_iter6_tmp_11_10_14_reg_7617 <= ap_reg_pp0_iter5_tmp_11_10_14_reg_7617;
ap_reg_pp0_iter6_tmp_11_11_14_reg_7622 <= ap_reg_pp0_iter5_tmp_11_11_14_reg_7622;
ap_reg_pp0_iter6_tmp_11_12_14_reg_7627 <= ap_reg_pp0_iter5_tmp_11_12_14_reg_7627;
ap_reg_pp0_iter6_tmp_11_13_14_reg_7632 <= ap_reg_pp0_iter5_tmp_11_13_14_reg_7632;
ap_reg_pp0_iter6_tmp_11_14_14_reg_7637 <= ap_reg_pp0_iter5_tmp_11_14_14_reg_7637;
ap_reg_pp0_iter6_tmp_11_15_14_reg_7642 <= ap_reg_pp0_iter5_tmp_11_15_14_reg_7642;
ap_reg_pp0_iter6_tmp_11_1_14_reg_7572 <= ap_reg_pp0_iter5_tmp_11_1_14_reg_7572;
ap_reg_pp0_iter6_tmp_11_2_14_reg_7577 <= ap_reg_pp0_iter5_tmp_11_2_14_reg_7577;
ap_reg_pp0_iter6_tmp_11_3_14_reg_7582 <= ap_reg_pp0_iter5_tmp_11_3_14_reg_7582;
ap_reg_pp0_iter6_tmp_11_4_14_reg_7587 <= ap_reg_pp0_iter5_tmp_11_4_14_reg_7587;
ap_reg_pp0_iter6_tmp_11_5_14_reg_7592 <= ap_reg_pp0_iter5_tmp_11_5_14_reg_7592;
ap_reg_pp0_iter6_tmp_11_6_14_reg_7597 <= ap_reg_pp0_iter5_tmp_11_6_14_reg_7597;
ap_reg_pp0_iter6_tmp_11_7_14_reg_7602 <= ap_reg_pp0_iter5_tmp_11_7_14_reg_7602;
ap_reg_pp0_iter6_tmp_11_8_14_reg_7607 <= ap_reg_pp0_iter5_tmp_11_8_14_reg_7607;
ap_reg_pp0_iter6_tmp_11_9_14_reg_7612 <= ap_reg_pp0_iter5_tmp_11_9_14_reg_7612;
ap_reg_pp0_iter7_tmp_11_0_14_reg_7567 <= ap_reg_pp0_iter6_tmp_11_0_14_reg_7567;
ap_reg_pp0_iter7_tmp_11_10_14_reg_7617 <= ap_reg_pp0_iter6_tmp_11_10_14_reg_7617;
ap_reg_pp0_iter7_tmp_11_11_14_reg_7622 <= ap_reg_pp0_iter6_tmp_11_11_14_reg_7622;
ap_reg_pp0_iter7_tmp_11_12_14_reg_7627 <= ap_reg_pp0_iter6_tmp_11_12_14_reg_7627;
ap_reg_pp0_iter7_tmp_11_13_14_reg_7632 <= ap_reg_pp0_iter6_tmp_11_13_14_reg_7632;
ap_reg_pp0_iter7_tmp_11_14_14_reg_7637 <= ap_reg_pp0_iter6_tmp_11_14_14_reg_7637;
ap_reg_pp0_iter7_tmp_11_15_14_reg_7642 <= ap_reg_pp0_iter6_tmp_11_15_14_reg_7642;
ap_reg_pp0_iter7_tmp_11_1_14_reg_7572 <= ap_reg_pp0_iter6_tmp_11_1_14_reg_7572;
ap_reg_pp0_iter7_tmp_11_2_14_reg_7577 <= ap_reg_pp0_iter6_tmp_11_2_14_reg_7577;
ap_reg_pp0_iter7_tmp_11_3_14_reg_7582 <= ap_reg_pp0_iter6_tmp_11_3_14_reg_7582;
ap_reg_pp0_iter7_tmp_11_4_14_reg_7587 <= ap_reg_pp0_iter6_tmp_11_4_14_reg_7587;
ap_reg_pp0_iter7_tmp_11_5_14_reg_7592 <= ap_reg_pp0_iter6_tmp_11_5_14_reg_7592;
ap_reg_pp0_iter7_tmp_11_6_14_reg_7597 <= ap_reg_pp0_iter6_tmp_11_6_14_reg_7597;
ap_reg_pp0_iter7_tmp_11_7_14_reg_7602 <= ap_reg_pp0_iter6_tmp_11_7_14_reg_7602;
ap_reg_pp0_iter7_tmp_11_8_14_reg_7607 <= ap_reg_pp0_iter6_tmp_11_8_14_reg_7607;
ap_reg_pp0_iter7_tmp_11_9_14_reg_7612 <= ap_reg_pp0_iter6_tmp_11_9_14_reg_7612;
ap_reg_pp0_iter8_tmp_11_0_14_reg_7567 <= ap_reg_pp0_iter7_tmp_11_0_14_reg_7567;
ap_reg_pp0_iter8_tmp_11_10_14_reg_7617 <= ap_reg_pp0_iter7_tmp_11_10_14_reg_7617;
ap_reg_pp0_iter8_tmp_11_11_14_reg_7622 <= ap_reg_pp0_iter7_tmp_11_11_14_reg_7622;
ap_reg_pp0_iter8_tmp_11_12_14_reg_7627 <= ap_reg_pp0_iter7_tmp_11_12_14_reg_7627;
ap_reg_pp0_iter8_tmp_11_13_14_reg_7632 <= ap_reg_pp0_iter7_tmp_11_13_14_reg_7632;
ap_reg_pp0_iter8_tmp_11_14_14_reg_7637 <= ap_reg_pp0_iter7_tmp_11_14_14_reg_7637;
ap_reg_pp0_iter8_tmp_11_15_14_reg_7642 <= ap_reg_pp0_iter7_tmp_11_15_14_reg_7642;
ap_reg_pp0_iter8_tmp_11_1_14_reg_7572 <= ap_reg_pp0_iter7_tmp_11_1_14_reg_7572;
ap_reg_pp0_iter8_tmp_11_2_14_reg_7577 <= ap_reg_pp0_iter7_tmp_11_2_14_reg_7577;
ap_reg_pp0_iter8_tmp_11_3_14_reg_7582 <= ap_reg_pp0_iter7_tmp_11_3_14_reg_7582;
ap_reg_pp0_iter8_tmp_11_4_14_reg_7587 <= ap_reg_pp0_iter7_tmp_11_4_14_reg_7587;
ap_reg_pp0_iter8_tmp_11_5_14_reg_7592 <= ap_reg_pp0_iter7_tmp_11_5_14_reg_7592;
ap_reg_pp0_iter8_tmp_11_6_14_reg_7597 <= ap_reg_pp0_iter7_tmp_11_6_14_reg_7597;
ap_reg_pp0_iter8_tmp_11_7_14_reg_7602 <= ap_reg_pp0_iter7_tmp_11_7_14_reg_7602;
ap_reg_pp0_iter8_tmp_11_8_14_reg_7607 <= ap_reg_pp0_iter7_tmp_11_8_14_reg_7607;
ap_reg_pp0_iter8_tmp_11_9_14_reg_7612 <= ap_reg_pp0_iter7_tmp_11_9_14_reg_7612;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0))) then
ap_reg_pp0_iter2_tmp_11_0_4_reg_5562 <= tmp_11_0_4_reg_5562;
ap_reg_pp0_iter2_tmp_11_10_4_reg_5732 <= tmp_11_10_4_reg_5732;
ap_reg_pp0_iter2_tmp_11_11_4_reg_5747 <= tmp_11_11_4_reg_5747;
ap_reg_pp0_iter2_tmp_11_12_4_reg_5762 <= tmp_11_12_4_reg_5762;
ap_reg_pp0_iter2_tmp_11_13_4_reg_5777 <= tmp_11_13_4_reg_5777;
ap_reg_pp0_iter2_tmp_11_14_4_reg_5792 <= tmp_11_14_4_reg_5792;
ap_reg_pp0_iter2_tmp_11_15_4_reg_5807 <= tmp_11_15_4_reg_5807;
ap_reg_pp0_iter2_tmp_11_1_4_reg_5597 <= tmp_11_1_4_reg_5597;
ap_reg_pp0_iter2_tmp_11_2_4_reg_5612 <= tmp_11_2_4_reg_5612;
ap_reg_pp0_iter2_tmp_11_3_4_reg_5627 <= tmp_11_3_4_reg_5627;
ap_reg_pp0_iter2_tmp_11_4_4_reg_5642 <= tmp_11_4_4_reg_5642;
ap_reg_pp0_iter2_tmp_11_5_4_reg_5657 <= tmp_11_5_4_reg_5657;
ap_reg_pp0_iter2_tmp_11_6_4_reg_5672 <= tmp_11_6_4_reg_5672;
ap_reg_pp0_iter2_tmp_11_7_4_reg_5687 <= tmp_11_7_4_reg_5687;
ap_reg_pp0_iter2_tmp_11_8_4_reg_5702 <= tmp_11_8_4_reg_5702;
ap_reg_pp0_iter2_tmp_11_9_4_reg_5717 <= tmp_11_9_4_reg_5717;
ap_reg_pp0_iter3_tmp_11_0_4_reg_5562 <= ap_reg_pp0_iter2_tmp_11_0_4_reg_5562;
ap_reg_pp0_iter3_tmp_11_10_4_reg_5732 <= ap_reg_pp0_iter2_tmp_11_10_4_reg_5732;
ap_reg_pp0_iter3_tmp_11_11_4_reg_5747 <= ap_reg_pp0_iter2_tmp_11_11_4_reg_5747;
ap_reg_pp0_iter3_tmp_11_12_4_reg_5762 <= ap_reg_pp0_iter2_tmp_11_12_4_reg_5762;
ap_reg_pp0_iter3_tmp_11_13_4_reg_5777 <= ap_reg_pp0_iter2_tmp_11_13_4_reg_5777;
ap_reg_pp0_iter3_tmp_11_14_4_reg_5792 <= ap_reg_pp0_iter2_tmp_11_14_4_reg_5792;
ap_reg_pp0_iter3_tmp_11_15_4_reg_5807 <= ap_reg_pp0_iter2_tmp_11_15_4_reg_5807;
ap_reg_pp0_iter3_tmp_11_1_4_reg_5597 <= ap_reg_pp0_iter2_tmp_11_1_4_reg_5597;
ap_reg_pp0_iter3_tmp_11_2_4_reg_5612 <= ap_reg_pp0_iter2_tmp_11_2_4_reg_5612;
ap_reg_pp0_iter3_tmp_11_3_4_reg_5627 <= ap_reg_pp0_iter2_tmp_11_3_4_reg_5627;
ap_reg_pp0_iter3_tmp_11_4_4_reg_5642 <= ap_reg_pp0_iter2_tmp_11_4_4_reg_5642;
ap_reg_pp0_iter3_tmp_11_5_4_reg_5657 <= ap_reg_pp0_iter2_tmp_11_5_4_reg_5657;
ap_reg_pp0_iter3_tmp_11_6_4_reg_5672 <= ap_reg_pp0_iter2_tmp_11_6_4_reg_5672;
ap_reg_pp0_iter3_tmp_11_7_4_reg_5687 <= ap_reg_pp0_iter2_tmp_11_7_4_reg_5687;
ap_reg_pp0_iter3_tmp_11_8_4_reg_5702 <= ap_reg_pp0_iter2_tmp_11_8_4_reg_5702;
ap_reg_pp0_iter3_tmp_11_9_4_reg_5717 <= ap_reg_pp0_iter2_tmp_11_9_4_reg_5717;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0))) then
ap_reg_pp0_iter2_tmp_11_0_5_reg_5827 <= tmp_11_0_5_reg_5827;
ap_reg_pp0_iter2_tmp_11_10_5_reg_5997 <= tmp_11_10_5_reg_5997;
ap_reg_pp0_iter2_tmp_11_11_5_reg_6012 <= tmp_11_11_5_reg_6012;
ap_reg_pp0_iter2_tmp_11_12_5_reg_6027 <= tmp_11_12_5_reg_6027;
ap_reg_pp0_iter2_tmp_11_13_5_reg_6042 <= tmp_11_13_5_reg_6042;
ap_reg_pp0_iter2_tmp_11_14_5_reg_6057 <= tmp_11_14_5_reg_6057;
ap_reg_pp0_iter2_tmp_11_15_5_reg_6072 <= tmp_11_15_5_reg_6072;
ap_reg_pp0_iter2_tmp_11_1_5_reg_5862 <= tmp_11_1_5_reg_5862;
ap_reg_pp0_iter2_tmp_11_2_5_reg_5877 <= tmp_11_2_5_reg_5877;
ap_reg_pp0_iter2_tmp_11_3_5_reg_5892 <= tmp_11_3_5_reg_5892;
ap_reg_pp0_iter2_tmp_11_4_5_reg_5907 <= tmp_11_4_5_reg_5907;
ap_reg_pp0_iter2_tmp_11_5_5_reg_5922 <= tmp_11_5_5_reg_5922;
ap_reg_pp0_iter2_tmp_11_6_5_reg_5937 <= tmp_11_6_5_reg_5937;
ap_reg_pp0_iter2_tmp_11_7_5_reg_5952 <= tmp_11_7_5_reg_5952;
ap_reg_pp0_iter2_tmp_11_8_5_reg_5967 <= tmp_11_8_5_reg_5967;
ap_reg_pp0_iter2_tmp_11_9_5_reg_5982 <= tmp_11_9_5_reg_5982;
ap_reg_pp0_iter3_tmp_11_0_5_reg_5827 <= ap_reg_pp0_iter2_tmp_11_0_5_reg_5827;
ap_reg_pp0_iter3_tmp_11_10_5_reg_5997 <= ap_reg_pp0_iter2_tmp_11_10_5_reg_5997;
ap_reg_pp0_iter3_tmp_11_11_5_reg_6012 <= ap_reg_pp0_iter2_tmp_11_11_5_reg_6012;
ap_reg_pp0_iter3_tmp_11_12_5_reg_6027 <= ap_reg_pp0_iter2_tmp_11_12_5_reg_6027;
ap_reg_pp0_iter3_tmp_11_13_5_reg_6042 <= ap_reg_pp0_iter2_tmp_11_13_5_reg_6042;
ap_reg_pp0_iter3_tmp_11_14_5_reg_6057 <= ap_reg_pp0_iter2_tmp_11_14_5_reg_6057;
ap_reg_pp0_iter3_tmp_11_15_5_reg_6072 <= ap_reg_pp0_iter2_tmp_11_15_5_reg_6072;
ap_reg_pp0_iter3_tmp_11_1_5_reg_5862 <= ap_reg_pp0_iter2_tmp_11_1_5_reg_5862;
ap_reg_pp0_iter3_tmp_11_2_5_reg_5877 <= ap_reg_pp0_iter2_tmp_11_2_5_reg_5877;
ap_reg_pp0_iter3_tmp_11_3_5_reg_5892 <= ap_reg_pp0_iter2_tmp_11_3_5_reg_5892;
ap_reg_pp0_iter3_tmp_11_4_5_reg_5907 <= ap_reg_pp0_iter2_tmp_11_4_5_reg_5907;
ap_reg_pp0_iter3_tmp_11_5_5_reg_5922 <= ap_reg_pp0_iter2_tmp_11_5_5_reg_5922;
ap_reg_pp0_iter3_tmp_11_6_5_reg_5937 <= ap_reg_pp0_iter2_tmp_11_6_5_reg_5937;
ap_reg_pp0_iter3_tmp_11_7_5_reg_5952 <= ap_reg_pp0_iter2_tmp_11_7_5_reg_5952;
ap_reg_pp0_iter3_tmp_11_8_5_reg_5967 <= ap_reg_pp0_iter2_tmp_11_8_5_reg_5967;
ap_reg_pp0_iter3_tmp_11_9_5_reg_5982 <= ap_reg_pp0_iter2_tmp_11_9_5_reg_5982;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0))) then
ap_reg_pp0_iter2_tmp_11_0_6_reg_6087 <= tmp_11_0_6_reg_6087;
ap_reg_pp0_iter2_tmp_11_10_6_reg_6257 <= tmp_11_10_6_reg_6257;
ap_reg_pp0_iter2_tmp_11_11_6_reg_6272 <= tmp_11_11_6_reg_6272;
ap_reg_pp0_iter2_tmp_11_12_6_reg_6287 <= tmp_11_12_6_reg_6287;
ap_reg_pp0_iter2_tmp_11_13_6_reg_6302 <= tmp_11_13_6_reg_6302;
ap_reg_pp0_iter2_tmp_11_14_6_reg_6317 <= tmp_11_14_6_reg_6317;
ap_reg_pp0_iter2_tmp_11_15_6_reg_6332 <= tmp_11_15_6_reg_6332;
ap_reg_pp0_iter2_tmp_11_1_6_reg_6122 <= tmp_11_1_6_reg_6122;
ap_reg_pp0_iter2_tmp_11_2_6_reg_6137 <= tmp_11_2_6_reg_6137;
ap_reg_pp0_iter2_tmp_11_3_6_reg_6152 <= tmp_11_3_6_reg_6152;
ap_reg_pp0_iter2_tmp_11_4_6_reg_6167 <= tmp_11_4_6_reg_6167;
ap_reg_pp0_iter2_tmp_11_5_6_reg_6182 <= tmp_11_5_6_reg_6182;
ap_reg_pp0_iter2_tmp_11_6_6_reg_6197 <= tmp_11_6_6_reg_6197;
ap_reg_pp0_iter2_tmp_11_7_6_reg_6212 <= tmp_11_7_6_reg_6212;
ap_reg_pp0_iter2_tmp_11_8_6_reg_6227 <= tmp_11_8_6_reg_6227;
ap_reg_pp0_iter2_tmp_11_9_6_reg_6242 <= tmp_11_9_6_reg_6242;
ap_reg_pp0_iter3_tmp_11_0_6_reg_6087 <= ap_reg_pp0_iter2_tmp_11_0_6_reg_6087;
ap_reg_pp0_iter3_tmp_11_10_6_reg_6257 <= ap_reg_pp0_iter2_tmp_11_10_6_reg_6257;
ap_reg_pp0_iter3_tmp_11_11_6_reg_6272 <= ap_reg_pp0_iter2_tmp_11_11_6_reg_6272;
ap_reg_pp0_iter3_tmp_11_12_6_reg_6287 <= ap_reg_pp0_iter2_tmp_11_12_6_reg_6287;
ap_reg_pp0_iter3_tmp_11_13_6_reg_6302 <= ap_reg_pp0_iter2_tmp_11_13_6_reg_6302;
ap_reg_pp0_iter3_tmp_11_14_6_reg_6317 <= ap_reg_pp0_iter2_tmp_11_14_6_reg_6317;
ap_reg_pp0_iter3_tmp_11_15_6_reg_6332 <= ap_reg_pp0_iter2_tmp_11_15_6_reg_6332;
ap_reg_pp0_iter3_tmp_11_1_6_reg_6122 <= ap_reg_pp0_iter2_tmp_11_1_6_reg_6122;
ap_reg_pp0_iter3_tmp_11_2_6_reg_6137 <= ap_reg_pp0_iter2_tmp_11_2_6_reg_6137;
ap_reg_pp0_iter3_tmp_11_3_6_reg_6152 <= ap_reg_pp0_iter2_tmp_11_3_6_reg_6152;
ap_reg_pp0_iter3_tmp_11_4_6_reg_6167 <= ap_reg_pp0_iter2_tmp_11_4_6_reg_6167;
ap_reg_pp0_iter3_tmp_11_5_6_reg_6182 <= ap_reg_pp0_iter2_tmp_11_5_6_reg_6182;
ap_reg_pp0_iter3_tmp_11_6_6_reg_6197 <= ap_reg_pp0_iter2_tmp_11_6_6_reg_6197;
ap_reg_pp0_iter3_tmp_11_7_6_reg_6212 <= ap_reg_pp0_iter2_tmp_11_7_6_reg_6212;
ap_reg_pp0_iter3_tmp_11_8_6_reg_6227 <= ap_reg_pp0_iter2_tmp_11_8_6_reg_6227;
ap_reg_pp0_iter3_tmp_11_9_6_reg_6242 <= ap_reg_pp0_iter2_tmp_11_9_6_reg_6242;
ap_reg_pp0_iter4_tmp_11_0_6_reg_6087 <= ap_reg_pp0_iter3_tmp_11_0_6_reg_6087;
ap_reg_pp0_iter4_tmp_11_10_6_reg_6257 <= ap_reg_pp0_iter3_tmp_11_10_6_reg_6257;
ap_reg_pp0_iter4_tmp_11_11_6_reg_6272 <= ap_reg_pp0_iter3_tmp_11_11_6_reg_6272;
ap_reg_pp0_iter4_tmp_11_12_6_reg_6287 <= ap_reg_pp0_iter3_tmp_11_12_6_reg_6287;
ap_reg_pp0_iter4_tmp_11_13_6_reg_6302 <= ap_reg_pp0_iter3_tmp_11_13_6_reg_6302;
ap_reg_pp0_iter4_tmp_11_14_6_reg_6317 <= ap_reg_pp0_iter3_tmp_11_14_6_reg_6317;
ap_reg_pp0_iter4_tmp_11_15_6_reg_6332 <= ap_reg_pp0_iter3_tmp_11_15_6_reg_6332;
ap_reg_pp0_iter4_tmp_11_1_6_reg_6122 <= ap_reg_pp0_iter3_tmp_11_1_6_reg_6122;
ap_reg_pp0_iter4_tmp_11_2_6_reg_6137 <= ap_reg_pp0_iter3_tmp_11_2_6_reg_6137;
ap_reg_pp0_iter4_tmp_11_3_6_reg_6152 <= ap_reg_pp0_iter3_tmp_11_3_6_reg_6152;
ap_reg_pp0_iter4_tmp_11_4_6_reg_6167 <= ap_reg_pp0_iter3_tmp_11_4_6_reg_6167;
ap_reg_pp0_iter4_tmp_11_5_6_reg_6182 <= ap_reg_pp0_iter3_tmp_11_5_6_reg_6182;
ap_reg_pp0_iter4_tmp_11_6_6_reg_6197 <= ap_reg_pp0_iter3_tmp_11_6_6_reg_6197;
ap_reg_pp0_iter4_tmp_11_7_6_reg_6212 <= ap_reg_pp0_iter3_tmp_11_7_6_reg_6212;
ap_reg_pp0_iter4_tmp_11_8_6_reg_6227 <= ap_reg_pp0_iter3_tmp_11_8_6_reg_6227;
ap_reg_pp0_iter4_tmp_11_9_6_reg_6242 <= ap_reg_pp0_iter3_tmp_11_9_6_reg_6242;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0))) then
ap_reg_pp0_iter2_tmp_11_0_8_reg_6527 <= tmp_11_0_8_reg_6527;
ap_reg_pp0_iter2_tmp_11_10_8_reg_6647 <= tmp_11_10_8_reg_6647;
ap_reg_pp0_iter2_tmp_11_11_8_reg_6657 <= tmp_11_11_8_reg_6657;
ap_reg_pp0_iter2_tmp_11_12_8_reg_6667 <= tmp_11_12_8_reg_6667;
ap_reg_pp0_iter2_tmp_11_13_8_reg_6677 <= tmp_11_13_8_reg_6677;
ap_reg_pp0_iter2_tmp_11_14_8_reg_6687 <= tmp_11_14_8_reg_6687;
ap_reg_pp0_iter2_tmp_11_15_8_reg_6697 <= tmp_11_15_8_reg_6697;
ap_reg_pp0_iter2_tmp_11_1_8_reg_6557 <= tmp_11_1_8_reg_6557;
ap_reg_pp0_iter2_tmp_11_2_8_reg_6567 <= tmp_11_2_8_reg_6567;
ap_reg_pp0_iter2_tmp_11_3_8_reg_6577 <= tmp_11_3_8_reg_6577;
ap_reg_pp0_iter2_tmp_11_4_8_reg_6587 <= tmp_11_4_8_reg_6587;
ap_reg_pp0_iter2_tmp_11_5_8_reg_6597 <= tmp_11_5_8_reg_6597;
ap_reg_pp0_iter2_tmp_11_6_8_reg_6607 <= tmp_11_6_8_reg_6607;
ap_reg_pp0_iter2_tmp_11_7_8_reg_6617 <= tmp_11_7_8_reg_6617;
ap_reg_pp0_iter2_tmp_11_8_8_reg_6627 <= tmp_11_8_8_reg_6627;
ap_reg_pp0_iter2_tmp_11_9_8_reg_6637 <= tmp_11_9_8_reg_6637;
ap_reg_pp0_iter3_tmp_11_0_8_reg_6527 <= ap_reg_pp0_iter2_tmp_11_0_8_reg_6527;
ap_reg_pp0_iter3_tmp_11_10_8_reg_6647 <= ap_reg_pp0_iter2_tmp_11_10_8_reg_6647;
ap_reg_pp0_iter3_tmp_11_11_8_reg_6657 <= ap_reg_pp0_iter2_tmp_11_11_8_reg_6657;
ap_reg_pp0_iter3_tmp_11_12_8_reg_6667 <= ap_reg_pp0_iter2_tmp_11_12_8_reg_6667;
ap_reg_pp0_iter3_tmp_11_13_8_reg_6677 <= ap_reg_pp0_iter2_tmp_11_13_8_reg_6677;
ap_reg_pp0_iter3_tmp_11_14_8_reg_6687 <= ap_reg_pp0_iter2_tmp_11_14_8_reg_6687;
ap_reg_pp0_iter3_tmp_11_15_8_reg_6697 <= ap_reg_pp0_iter2_tmp_11_15_8_reg_6697;
ap_reg_pp0_iter3_tmp_11_1_8_reg_6557 <= ap_reg_pp0_iter2_tmp_11_1_8_reg_6557;
ap_reg_pp0_iter3_tmp_11_2_8_reg_6567 <= ap_reg_pp0_iter2_tmp_11_2_8_reg_6567;
ap_reg_pp0_iter3_tmp_11_3_8_reg_6577 <= ap_reg_pp0_iter2_tmp_11_3_8_reg_6577;
ap_reg_pp0_iter3_tmp_11_4_8_reg_6587 <= ap_reg_pp0_iter2_tmp_11_4_8_reg_6587;
ap_reg_pp0_iter3_tmp_11_5_8_reg_6597 <= ap_reg_pp0_iter2_tmp_11_5_8_reg_6597;
ap_reg_pp0_iter3_tmp_11_6_8_reg_6607 <= ap_reg_pp0_iter2_tmp_11_6_8_reg_6607;
ap_reg_pp0_iter3_tmp_11_7_8_reg_6617 <= ap_reg_pp0_iter2_tmp_11_7_8_reg_6617;
ap_reg_pp0_iter3_tmp_11_8_8_reg_6627 <= ap_reg_pp0_iter2_tmp_11_8_8_reg_6627;
ap_reg_pp0_iter3_tmp_11_9_8_reg_6637 <= ap_reg_pp0_iter2_tmp_11_9_8_reg_6637;
ap_reg_pp0_iter4_tmp_11_0_8_reg_6527 <= ap_reg_pp0_iter3_tmp_11_0_8_reg_6527;
ap_reg_pp0_iter4_tmp_11_10_8_reg_6647 <= ap_reg_pp0_iter3_tmp_11_10_8_reg_6647;
ap_reg_pp0_iter4_tmp_11_11_8_reg_6657 <= ap_reg_pp0_iter3_tmp_11_11_8_reg_6657;
ap_reg_pp0_iter4_tmp_11_12_8_reg_6667 <= ap_reg_pp0_iter3_tmp_11_12_8_reg_6667;
ap_reg_pp0_iter4_tmp_11_13_8_reg_6677 <= ap_reg_pp0_iter3_tmp_11_13_8_reg_6677;
ap_reg_pp0_iter4_tmp_11_14_8_reg_6687 <= ap_reg_pp0_iter3_tmp_11_14_8_reg_6687;
ap_reg_pp0_iter4_tmp_11_15_8_reg_6697 <= ap_reg_pp0_iter3_tmp_11_15_8_reg_6697;
ap_reg_pp0_iter4_tmp_11_1_8_reg_6557 <= ap_reg_pp0_iter3_tmp_11_1_8_reg_6557;
ap_reg_pp0_iter4_tmp_11_2_8_reg_6567 <= ap_reg_pp0_iter3_tmp_11_2_8_reg_6567;
ap_reg_pp0_iter4_tmp_11_3_8_reg_6577 <= ap_reg_pp0_iter3_tmp_11_3_8_reg_6577;
ap_reg_pp0_iter4_tmp_11_4_8_reg_6587 <= ap_reg_pp0_iter3_tmp_11_4_8_reg_6587;
ap_reg_pp0_iter4_tmp_11_5_8_reg_6597 <= ap_reg_pp0_iter3_tmp_11_5_8_reg_6597;
ap_reg_pp0_iter4_tmp_11_6_8_reg_6607 <= ap_reg_pp0_iter3_tmp_11_6_8_reg_6607;
ap_reg_pp0_iter4_tmp_11_7_8_reg_6617 <= ap_reg_pp0_iter3_tmp_11_7_8_reg_6617;
ap_reg_pp0_iter4_tmp_11_8_8_reg_6627 <= ap_reg_pp0_iter3_tmp_11_8_8_reg_6627;
ap_reg_pp0_iter4_tmp_11_9_8_reg_6637 <= ap_reg_pp0_iter3_tmp_11_9_8_reg_6637;
ap_reg_pp0_iter5_tmp_11_0_8_reg_6527 <= ap_reg_pp0_iter4_tmp_11_0_8_reg_6527;
ap_reg_pp0_iter5_tmp_11_10_8_reg_6647 <= ap_reg_pp0_iter4_tmp_11_10_8_reg_6647;
ap_reg_pp0_iter5_tmp_11_11_8_reg_6657 <= ap_reg_pp0_iter4_tmp_11_11_8_reg_6657;
ap_reg_pp0_iter5_tmp_11_12_8_reg_6667 <= ap_reg_pp0_iter4_tmp_11_12_8_reg_6667;
ap_reg_pp0_iter5_tmp_11_13_8_reg_6677 <= ap_reg_pp0_iter4_tmp_11_13_8_reg_6677;
ap_reg_pp0_iter5_tmp_11_14_8_reg_6687 <= ap_reg_pp0_iter4_tmp_11_14_8_reg_6687;
ap_reg_pp0_iter5_tmp_11_15_8_reg_6697 <= ap_reg_pp0_iter4_tmp_11_15_8_reg_6697;
ap_reg_pp0_iter5_tmp_11_1_8_reg_6557 <= ap_reg_pp0_iter4_tmp_11_1_8_reg_6557;
ap_reg_pp0_iter5_tmp_11_2_8_reg_6567 <= ap_reg_pp0_iter4_tmp_11_2_8_reg_6567;
ap_reg_pp0_iter5_tmp_11_3_8_reg_6577 <= ap_reg_pp0_iter4_tmp_11_3_8_reg_6577;
ap_reg_pp0_iter5_tmp_11_4_8_reg_6587 <= ap_reg_pp0_iter4_tmp_11_4_8_reg_6587;
ap_reg_pp0_iter5_tmp_11_5_8_reg_6597 <= ap_reg_pp0_iter4_tmp_11_5_8_reg_6597;
ap_reg_pp0_iter5_tmp_11_6_8_reg_6607 <= ap_reg_pp0_iter4_tmp_11_6_8_reg_6607;
ap_reg_pp0_iter5_tmp_11_7_8_reg_6617 <= ap_reg_pp0_iter4_tmp_11_7_8_reg_6617;
ap_reg_pp0_iter5_tmp_11_8_8_reg_6627 <= ap_reg_pp0_iter4_tmp_11_8_8_reg_6627;
ap_reg_pp0_iter5_tmp_11_9_8_reg_6637 <= ap_reg_pp0_iter4_tmp_11_9_8_reg_6637;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0))) then
ap_reg_pp0_iter2_tmp_11_0_9_reg_6712 <= tmp_11_0_9_reg_6712;
ap_reg_pp0_iter2_tmp_11_10_9_reg_6882 <= tmp_11_10_9_reg_6882;
ap_reg_pp0_iter2_tmp_11_11_9_reg_6897 <= tmp_11_11_9_reg_6897;
ap_reg_pp0_iter2_tmp_11_12_9_reg_6912 <= tmp_11_12_9_reg_6912;
ap_reg_pp0_iter2_tmp_11_13_9_reg_6927 <= tmp_11_13_9_reg_6927;
ap_reg_pp0_iter2_tmp_11_14_9_reg_6942 <= tmp_11_14_9_reg_6942;
ap_reg_pp0_iter2_tmp_11_15_9_reg_6957 <= tmp_11_15_9_reg_6957;
ap_reg_pp0_iter2_tmp_11_1_9_reg_6747 <= tmp_11_1_9_reg_6747;
ap_reg_pp0_iter2_tmp_11_2_9_reg_6762 <= tmp_11_2_9_reg_6762;
ap_reg_pp0_iter2_tmp_11_3_9_reg_6777 <= tmp_11_3_9_reg_6777;
ap_reg_pp0_iter2_tmp_11_4_9_reg_6792 <= tmp_11_4_9_reg_6792;
ap_reg_pp0_iter2_tmp_11_5_9_reg_6807 <= tmp_11_5_9_reg_6807;
ap_reg_pp0_iter2_tmp_11_6_9_reg_6822 <= tmp_11_6_9_reg_6822;
ap_reg_pp0_iter2_tmp_11_7_9_reg_6837 <= tmp_11_7_9_reg_6837;
ap_reg_pp0_iter2_tmp_11_8_9_reg_6852 <= tmp_11_8_9_reg_6852;
ap_reg_pp0_iter2_tmp_11_9_9_reg_6867 <= tmp_11_9_9_reg_6867;
ap_reg_pp0_iter3_tmp_11_0_9_reg_6712 <= ap_reg_pp0_iter2_tmp_11_0_9_reg_6712;
ap_reg_pp0_iter3_tmp_11_10_9_reg_6882 <= ap_reg_pp0_iter2_tmp_11_10_9_reg_6882;
ap_reg_pp0_iter3_tmp_11_11_9_reg_6897 <= ap_reg_pp0_iter2_tmp_11_11_9_reg_6897;
ap_reg_pp0_iter3_tmp_11_12_9_reg_6912 <= ap_reg_pp0_iter2_tmp_11_12_9_reg_6912;
ap_reg_pp0_iter3_tmp_11_13_9_reg_6927 <= ap_reg_pp0_iter2_tmp_11_13_9_reg_6927;
ap_reg_pp0_iter3_tmp_11_14_9_reg_6942 <= ap_reg_pp0_iter2_tmp_11_14_9_reg_6942;
ap_reg_pp0_iter3_tmp_11_15_9_reg_6957 <= ap_reg_pp0_iter2_tmp_11_15_9_reg_6957;
ap_reg_pp0_iter3_tmp_11_1_9_reg_6747 <= ap_reg_pp0_iter2_tmp_11_1_9_reg_6747;
ap_reg_pp0_iter3_tmp_11_2_9_reg_6762 <= ap_reg_pp0_iter2_tmp_11_2_9_reg_6762;
ap_reg_pp0_iter3_tmp_11_3_9_reg_6777 <= ap_reg_pp0_iter2_tmp_11_3_9_reg_6777;
ap_reg_pp0_iter3_tmp_11_4_9_reg_6792 <= ap_reg_pp0_iter2_tmp_11_4_9_reg_6792;
ap_reg_pp0_iter3_tmp_11_5_9_reg_6807 <= ap_reg_pp0_iter2_tmp_11_5_9_reg_6807;
ap_reg_pp0_iter3_tmp_11_6_9_reg_6822 <= ap_reg_pp0_iter2_tmp_11_6_9_reg_6822;
ap_reg_pp0_iter3_tmp_11_7_9_reg_6837 <= ap_reg_pp0_iter2_tmp_11_7_9_reg_6837;
ap_reg_pp0_iter3_tmp_11_8_9_reg_6852 <= ap_reg_pp0_iter2_tmp_11_8_9_reg_6852;
ap_reg_pp0_iter3_tmp_11_9_9_reg_6867 <= ap_reg_pp0_iter2_tmp_11_9_9_reg_6867;
ap_reg_pp0_iter4_tmp_11_0_9_reg_6712 <= ap_reg_pp0_iter3_tmp_11_0_9_reg_6712;
ap_reg_pp0_iter4_tmp_11_10_9_reg_6882 <= ap_reg_pp0_iter3_tmp_11_10_9_reg_6882;
ap_reg_pp0_iter4_tmp_11_11_9_reg_6897 <= ap_reg_pp0_iter3_tmp_11_11_9_reg_6897;
ap_reg_pp0_iter4_tmp_11_12_9_reg_6912 <= ap_reg_pp0_iter3_tmp_11_12_9_reg_6912;
ap_reg_pp0_iter4_tmp_11_13_9_reg_6927 <= ap_reg_pp0_iter3_tmp_11_13_9_reg_6927;
ap_reg_pp0_iter4_tmp_11_14_9_reg_6942 <= ap_reg_pp0_iter3_tmp_11_14_9_reg_6942;
ap_reg_pp0_iter4_tmp_11_15_9_reg_6957 <= ap_reg_pp0_iter3_tmp_11_15_9_reg_6957;
ap_reg_pp0_iter4_tmp_11_1_9_reg_6747 <= ap_reg_pp0_iter3_tmp_11_1_9_reg_6747;
ap_reg_pp0_iter4_tmp_11_2_9_reg_6762 <= ap_reg_pp0_iter3_tmp_11_2_9_reg_6762;
ap_reg_pp0_iter4_tmp_11_3_9_reg_6777 <= ap_reg_pp0_iter3_tmp_11_3_9_reg_6777;
ap_reg_pp0_iter4_tmp_11_4_9_reg_6792 <= ap_reg_pp0_iter3_tmp_11_4_9_reg_6792;
ap_reg_pp0_iter4_tmp_11_5_9_reg_6807 <= ap_reg_pp0_iter3_tmp_11_5_9_reg_6807;
ap_reg_pp0_iter4_tmp_11_6_9_reg_6822 <= ap_reg_pp0_iter3_tmp_11_6_9_reg_6822;
ap_reg_pp0_iter4_tmp_11_7_9_reg_6837 <= ap_reg_pp0_iter3_tmp_11_7_9_reg_6837;
ap_reg_pp0_iter4_tmp_11_8_9_reg_6852 <= ap_reg_pp0_iter3_tmp_11_8_9_reg_6852;
ap_reg_pp0_iter4_tmp_11_9_9_reg_6867 <= ap_reg_pp0_iter3_tmp_11_9_9_reg_6867;
ap_reg_pp0_iter5_tmp_11_0_9_reg_6712 <= ap_reg_pp0_iter4_tmp_11_0_9_reg_6712;
ap_reg_pp0_iter5_tmp_11_10_9_reg_6882 <= ap_reg_pp0_iter4_tmp_11_10_9_reg_6882;
ap_reg_pp0_iter5_tmp_11_11_9_reg_6897 <= ap_reg_pp0_iter4_tmp_11_11_9_reg_6897;
ap_reg_pp0_iter5_tmp_11_12_9_reg_6912 <= ap_reg_pp0_iter4_tmp_11_12_9_reg_6912;
ap_reg_pp0_iter5_tmp_11_13_9_reg_6927 <= ap_reg_pp0_iter4_tmp_11_13_9_reg_6927;
ap_reg_pp0_iter5_tmp_11_14_9_reg_6942 <= ap_reg_pp0_iter4_tmp_11_14_9_reg_6942;
ap_reg_pp0_iter5_tmp_11_15_9_reg_6957 <= ap_reg_pp0_iter4_tmp_11_15_9_reg_6957;
ap_reg_pp0_iter5_tmp_11_1_9_reg_6747 <= ap_reg_pp0_iter4_tmp_11_1_9_reg_6747;
ap_reg_pp0_iter5_tmp_11_2_9_reg_6762 <= ap_reg_pp0_iter4_tmp_11_2_9_reg_6762;
ap_reg_pp0_iter5_tmp_11_3_9_reg_6777 <= ap_reg_pp0_iter4_tmp_11_3_9_reg_6777;
ap_reg_pp0_iter5_tmp_11_4_9_reg_6792 <= ap_reg_pp0_iter4_tmp_11_4_9_reg_6792;
ap_reg_pp0_iter5_tmp_11_5_9_reg_6807 <= ap_reg_pp0_iter4_tmp_11_5_9_reg_6807;
ap_reg_pp0_iter5_tmp_11_6_9_reg_6822 <= ap_reg_pp0_iter4_tmp_11_6_9_reg_6822;
ap_reg_pp0_iter5_tmp_11_7_9_reg_6837 <= ap_reg_pp0_iter4_tmp_11_7_9_reg_6837;
ap_reg_pp0_iter5_tmp_11_8_9_reg_6852 <= ap_reg_pp0_iter4_tmp_11_8_9_reg_6852;
ap_reg_pp0_iter5_tmp_11_9_9_reg_6867 <= ap_reg_pp0_iter4_tmp_11_9_9_reg_6867;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0))) then
ap_reg_pp0_iter2_tmp_11_0_s_reg_6967 <= tmp_11_0_s_reg_6967;
ap_reg_pp0_iter2_tmp_11_10_s_reg_7087 <= tmp_11_10_s_reg_7087;
ap_reg_pp0_iter2_tmp_11_11_s_reg_7097 <= tmp_11_11_s_reg_7097;
ap_reg_pp0_iter2_tmp_11_12_s_reg_7107 <= tmp_11_12_s_reg_7107;
ap_reg_pp0_iter2_tmp_11_13_s_reg_7117 <= tmp_11_13_s_reg_7117;
ap_reg_pp0_iter2_tmp_11_14_s_reg_7127 <= tmp_11_14_s_reg_7127;
ap_reg_pp0_iter2_tmp_11_15_s_reg_7137 <= tmp_11_15_s_reg_7137;
ap_reg_pp0_iter2_tmp_11_1_s_reg_6997 <= tmp_11_1_s_reg_6997;
ap_reg_pp0_iter2_tmp_11_2_s_reg_7007 <= tmp_11_2_s_reg_7007;
ap_reg_pp0_iter2_tmp_11_3_s_reg_7017 <= tmp_11_3_s_reg_7017;
ap_reg_pp0_iter2_tmp_11_4_s_reg_7027 <= tmp_11_4_s_reg_7027;
ap_reg_pp0_iter2_tmp_11_5_s_reg_7037 <= tmp_11_5_s_reg_7037;
ap_reg_pp0_iter2_tmp_11_6_s_reg_7047 <= tmp_11_6_s_reg_7047;
ap_reg_pp0_iter2_tmp_11_7_s_reg_7057 <= tmp_11_7_s_reg_7057;
ap_reg_pp0_iter2_tmp_11_8_s_reg_7067 <= tmp_11_8_s_reg_7067;
ap_reg_pp0_iter2_tmp_11_9_s_reg_7077 <= tmp_11_9_s_reg_7077;
ap_reg_pp0_iter3_tmp_11_0_s_reg_6967 <= ap_reg_pp0_iter2_tmp_11_0_s_reg_6967;
ap_reg_pp0_iter3_tmp_11_10_s_reg_7087 <= ap_reg_pp0_iter2_tmp_11_10_s_reg_7087;
ap_reg_pp0_iter3_tmp_11_11_s_reg_7097 <= ap_reg_pp0_iter2_tmp_11_11_s_reg_7097;
ap_reg_pp0_iter3_tmp_11_12_s_reg_7107 <= ap_reg_pp0_iter2_tmp_11_12_s_reg_7107;
ap_reg_pp0_iter3_tmp_11_13_s_reg_7117 <= ap_reg_pp0_iter2_tmp_11_13_s_reg_7117;
ap_reg_pp0_iter3_tmp_11_14_s_reg_7127 <= ap_reg_pp0_iter2_tmp_11_14_s_reg_7127;
ap_reg_pp0_iter3_tmp_11_15_s_reg_7137 <= ap_reg_pp0_iter2_tmp_11_15_s_reg_7137;
ap_reg_pp0_iter3_tmp_11_1_s_reg_6997 <= ap_reg_pp0_iter2_tmp_11_1_s_reg_6997;
ap_reg_pp0_iter3_tmp_11_2_s_reg_7007 <= ap_reg_pp0_iter2_tmp_11_2_s_reg_7007;
ap_reg_pp0_iter3_tmp_11_3_s_reg_7017 <= ap_reg_pp0_iter2_tmp_11_3_s_reg_7017;
ap_reg_pp0_iter3_tmp_11_4_s_reg_7027 <= ap_reg_pp0_iter2_tmp_11_4_s_reg_7027;
ap_reg_pp0_iter3_tmp_11_5_s_reg_7037 <= ap_reg_pp0_iter2_tmp_11_5_s_reg_7037;
ap_reg_pp0_iter3_tmp_11_6_s_reg_7047 <= ap_reg_pp0_iter2_tmp_11_6_s_reg_7047;
ap_reg_pp0_iter3_tmp_11_7_s_reg_7057 <= ap_reg_pp0_iter2_tmp_11_7_s_reg_7057;
ap_reg_pp0_iter3_tmp_11_8_s_reg_7067 <= ap_reg_pp0_iter2_tmp_11_8_s_reg_7067;
ap_reg_pp0_iter3_tmp_11_9_s_reg_7077 <= ap_reg_pp0_iter2_tmp_11_9_s_reg_7077;
ap_reg_pp0_iter4_tmp_11_0_s_reg_6967 <= ap_reg_pp0_iter3_tmp_11_0_s_reg_6967;
ap_reg_pp0_iter4_tmp_11_10_s_reg_7087 <= ap_reg_pp0_iter3_tmp_11_10_s_reg_7087;
ap_reg_pp0_iter4_tmp_11_11_s_reg_7097 <= ap_reg_pp0_iter3_tmp_11_11_s_reg_7097;
ap_reg_pp0_iter4_tmp_11_12_s_reg_7107 <= ap_reg_pp0_iter3_tmp_11_12_s_reg_7107;
ap_reg_pp0_iter4_tmp_11_13_s_reg_7117 <= ap_reg_pp0_iter3_tmp_11_13_s_reg_7117;
ap_reg_pp0_iter4_tmp_11_14_s_reg_7127 <= ap_reg_pp0_iter3_tmp_11_14_s_reg_7127;
ap_reg_pp0_iter4_tmp_11_15_s_reg_7137 <= ap_reg_pp0_iter3_tmp_11_15_s_reg_7137;
ap_reg_pp0_iter4_tmp_11_1_s_reg_6997 <= ap_reg_pp0_iter3_tmp_11_1_s_reg_6997;
ap_reg_pp0_iter4_tmp_11_2_s_reg_7007 <= ap_reg_pp0_iter3_tmp_11_2_s_reg_7007;
ap_reg_pp0_iter4_tmp_11_3_s_reg_7017 <= ap_reg_pp0_iter3_tmp_11_3_s_reg_7017;
ap_reg_pp0_iter4_tmp_11_4_s_reg_7027 <= ap_reg_pp0_iter3_tmp_11_4_s_reg_7027;
ap_reg_pp0_iter4_tmp_11_5_s_reg_7037 <= ap_reg_pp0_iter3_tmp_11_5_s_reg_7037;
ap_reg_pp0_iter4_tmp_11_6_s_reg_7047 <= ap_reg_pp0_iter3_tmp_11_6_s_reg_7047;
ap_reg_pp0_iter4_tmp_11_7_s_reg_7057 <= ap_reg_pp0_iter3_tmp_11_7_s_reg_7057;
ap_reg_pp0_iter4_tmp_11_8_s_reg_7067 <= ap_reg_pp0_iter3_tmp_11_8_s_reg_7067;
ap_reg_pp0_iter4_tmp_11_9_s_reg_7077 <= ap_reg_pp0_iter3_tmp_11_9_s_reg_7077;
ap_reg_pp0_iter5_tmp_11_0_s_reg_6967 <= ap_reg_pp0_iter4_tmp_11_0_s_reg_6967;
ap_reg_pp0_iter5_tmp_11_10_s_reg_7087 <= ap_reg_pp0_iter4_tmp_11_10_s_reg_7087;
ap_reg_pp0_iter5_tmp_11_11_s_reg_7097 <= ap_reg_pp0_iter4_tmp_11_11_s_reg_7097;
ap_reg_pp0_iter5_tmp_11_12_s_reg_7107 <= ap_reg_pp0_iter4_tmp_11_12_s_reg_7107;
ap_reg_pp0_iter5_tmp_11_13_s_reg_7117 <= ap_reg_pp0_iter4_tmp_11_13_s_reg_7117;
ap_reg_pp0_iter5_tmp_11_14_s_reg_7127 <= ap_reg_pp0_iter4_tmp_11_14_s_reg_7127;
ap_reg_pp0_iter5_tmp_11_15_s_reg_7137 <= ap_reg_pp0_iter4_tmp_11_15_s_reg_7137;
ap_reg_pp0_iter5_tmp_11_1_s_reg_6997 <= ap_reg_pp0_iter4_tmp_11_1_s_reg_6997;
ap_reg_pp0_iter5_tmp_11_2_s_reg_7007 <= ap_reg_pp0_iter4_tmp_11_2_s_reg_7007;
ap_reg_pp0_iter5_tmp_11_3_s_reg_7017 <= ap_reg_pp0_iter4_tmp_11_3_s_reg_7017;
ap_reg_pp0_iter5_tmp_11_4_s_reg_7027 <= ap_reg_pp0_iter4_tmp_11_4_s_reg_7027;
ap_reg_pp0_iter5_tmp_11_5_s_reg_7037 <= ap_reg_pp0_iter4_tmp_11_5_s_reg_7037;
ap_reg_pp0_iter5_tmp_11_6_s_reg_7047 <= ap_reg_pp0_iter4_tmp_11_6_s_reg_7047;
ap_reg_pp0_iter5_tmp_11_7_s_reg_7057 <= ap_reg_pp0_iter4_tmp_11_7_s_reg_7057;
ap_reg_pp0_iter5_tmp_11_8_s_reg_7067 <= ap_reg_pp0_iter4_tmp_11_8_s_reg_7067;
ap_reg_pp0_iter5_tmp_11_9_s_reg_7077 <= ap_reg_pp0_iter4_tmp_11_9_s_reg_7077;
ap_reg_pp0_iter6_tmp_11_0_s_reg_6967 <= ap_reg_pp0_iter5_tmp_11_0_s_reg_6967;
ap_reg_pp0_iter6_tmp_11_10_s_reg_7087 <= ap_reg_pp0_iter5_tmp_11_10_s_reg_7087;
ap_reg_pp0_iter6_tmp_11_11_s_reg_7097 <= ap_reg_pp0_iter5_tmp_11_11_s_reg_7097;
ap_reg_pp0_iter6_tmp_11_12_s_reg_7107 <= ap_reg_pp0_iter5_tmp_11_12_s_reg_7107;
ap_reg_pp0_iter6_tmp_11_13_s_reg_7117 <= ap_reg_pp0_iter5_tmp_11_13_s_reg_7117;
ap_reg_pp0_iter6_tmp_11_14_s_reg_7127 <= ap_reg_pp0_iter5_tmp_11_14_s_reg_7127;
ap_reg_pp0_iter6_tmp_11_15_s_reg_7137 <= ap_reg_pp0_iter5_tmp_11_15_s_reg_7137;
ap_reg_pp0_iter6_tmp_11_1_s_reg_6997 <= ap_reg_pp0_iter5_tmp_11_1_s_reg_6997;
ap_reg_pp0_iter6_tmp_11_2_s_reg_7007 <= ap_reg_pp0_iter5_tmp_11_2_s_reg_7007;
ap_reg_pp0_iter6_tmp_11_3_s_reg_7017 <= ap_reg_pp0_iter5_tmp_11_3_s_reg_7017;
ap_reg_pp0_iter6_tmp_11_4_s_reg_7027 <= ap_reg_pp0_iter5_tmp_11_4_s_reg_7027;
ap_reg_pp0_iter6_tmp_11_5_s_reg_7037 <= ap_reg_pp0_iter5_tmp_11_5_s_reg_7037;
ap_reg_pp0_iter6_tmp_11_6_s_reg_7047 <= ap_reg_pp0_iter5_tmp_11_6_s_reg_7047;
ap_reg_pp0_iter6_tmp_11_7_s_reg_7057 <= ap_reg_pp0_iter5_tmp_11_7_s_reg_7057;
ap_reg_pp0_iter6_tmp_11_8_s_reg_7067 <= ap_reg_pp0_iter5_tmp_11_8_s_reg_7067;
ap_reg_pp0_iter6_tmp_11_9_s_reg_7077 <= ap_reg_pp0_iter5_tmp_11_9_s_reg_7077;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_flatten2_reg_3675 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0))) then
bufo_addr_reg_3867 <= tmp_647_cast_fu_1348_p1(8 - 1 downto 0);
tmp_3_reg_3872 <= tmp_3_fu_1362_p2;
tmp_47_reg_3852 <= tmp_47_fu_1297_p2;
tmp_4_mid2_cast4_reg_3841(2 downto 0) <= tmp_4_mid2_cast4_fu_1290_p1(2 downto 0);
tmp_635_reg_3877 <= tmp_635_fu_1367_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (exitcond_flatten2_reg_3675 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0))) then
col_b_1_reg_3957 <= col_b_1_fu_1371_p2;
row_b_mid2_reg_3862 <= row_b_mid2_fu_1334_p3;
tmp_134_reg_3887 <= bufw_Dout_A(95 downto 64);
tmp_169_reg_3892 <= bufw_Dout_A(127 downto 96);
tmp_204_reg_3897 <= bufw_Dout_A(159 downto 128);
tmp_239_reg_3902 <= bufw_Dout_A(191 downto 160);
tmp_274_reg_3907 <= bufw_Dout_A(223 downto 192);
tmp_309_reg_3912 <= bufw_Dout_A(255 downto 224);
tmp_344_reg_3917 <= bufw_Dout_A(287 downto 256);
tmp_379_reg_3922 <= bufw_Dout_A(319 downto 288);
tmp_414_reg_3927 <= bufw_Dout_A(351 downto 320);
tmp_449_reg_3932 <= bufw_Dout_A(383 downto 352);
tmp_484_reg_3937 <= bufw_Dout_A(415 downto 384);
tmp_519_reg_3942 <= bufw_Dout_A(447 downto 416);
tmp_554_reg_3947 <= bufw_Dout_A(479 downto 448);
tmp_589_reg_3952 <= bufw_Dout_A(511 downto 480);
tmp_98_reg_3882 <= bufw_Dout_A(63 downto 32);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_flatten2_reg_3675 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0))) then
col_b_mid2_reg_3802 <= col_b_mid2_fu_1250_p3;
row_b_mid_reg_3776 <= row_b_mid_fu_1211_p3;
tmp_1_mid2_cast_reg_3762(2 downto 0) <= tmp_1_mid2_cast_fu_1156_p1(2 downto 0);
tmp_2_reg_3767 <= tmp_2_fu_1170_p2;
tmp_75_reg_3792 <= tmp_75_fu_1228_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_lv1_0 = exitcond_flatten2_fu_1051_p2))) then
exitcond_flatten1_reg_3701 <= exitcond_flatten1_fu_1075_p2;
exitcond_flatten_reg_3684 <= exitcond_flatten_fu_1063_p2;
indvar_flatten40_op_reg_3707 <= indvar_flatten40_op_fu_1081_p2;
tmp_35_reg_3696 <= tmp_35_fu_1069_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_flatten2_reg_3675 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0))) then
exitcond_flatten_mid_reg_3731 <= exitcond_flatten_mid_fu_1117_p2;
i_1_reg_3712 <= i_1_fu_1087_p2;
indvar_flatten_op_reg_3752 <= indvar_flatten_op_fu_1144_p2;
j_1_reg_3739 <= j_1_fu_1122_p2;
j_mid_reg_3717 <= j_mid_fu_1093_p3;
tmp_9_mid1_reg_3744 <= tmp_9_mid1_fu_1138_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (exitcond_flatten2_reg_3675 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0))) then
indvar_flatten_next1_reg_3757 <= indvar_flatten_next1_fu_1150_p3;
tmp_1_mid2_v_reg_3722 <= tmp_1_mid2_v_fu_1100_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
indvar_flatten_next2_reg_3679 <= indvar_flatten_next2_fu_1057_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (exitcond_flatten2_reg_3675 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0))) then
indvar_flatten_next_reg_3809 <= indvar_flatten_next_fu_1258_p3;
tmp_4_mid2_reg_3783 <= tmp_4_mid2_fu_1219_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_lv1_0 = ap_reg_pp0_iter1_exitcond_flatten2_reg_3675)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9) and (ap_const_lv1_0 = ap_reg_pp0_iter9_exitcond_flatten2_reg_3675)))) then
reg_1001 <= grp_fu_473_p2;
reg_1006 <= grp_fu_477_p2;
reg_1011 <= grp_fu_481_p2;
reg_1016 <= grp_fu_485_p2;
reg_1021 <= grp_fu_489_p2;
reg_1026 <= grp_fu_493_p2;
reg_951 <= grp_fu_433_p2;
reg_956 <= grp_fu_437_p2;
reg_961 <= grp_fu_441_p2;
reg_966 <= grp_fu_445_p2;
reg_971 <= grp_fu_449_p2;
reg_976 <= grp_fu_453_p2;
reg_981 <= grp_fu_457_p2;
reg_986 <= grp_fu_461_p2;
reg_991 <= grp_fu_465_p2;
reg_996 <= grp_fu_469_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0) and (exitcond_flatten2_reg_3675 = ap_const_lv1_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (exitcond_flatten2_reg_3675 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (exitcond_flatten2_reg_3675 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00011001 = ap_const_boolean_0)))) then
reg_711 <= bufw_Dout_A(63 downto 32);
reg_715 <= bufw_Dout_A(95 downto 64);
reg_719 <= bufw_Dout_A(127 downto 96);
reg_723 <= bufw_Dout_A(159 downto 128);
reg_727 <= bufw_Dout_A(191 downto 160);
reg_731 <= bufw_Dout_A(223 downto 192);
reg_735 <= bufw_Dout_A(255 downto 224);
reg_739 <= bufw_Dout_A(287 downto 256);
reg_743 <= bufw_Dout_A(319 downto 288);
reg_747 <= bufw_Dout_A(351 downto 320);
reg_751 <= bufw_Dout_A(383 downto 352);
reg_755 <= bufw_Dout_A(415 downto 384);
reg_759 <= bufw_Dout_A(447 downto 416);
reg_763 <= bufw_Dout_A(479 downto 448);
reg_767 <= bufw_Dout_A(511 downto 480);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (exitcond_flatten2_reg_3675 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (exitcond_flatten2_reg_3675 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (exitcond_flatten2_reg_3675 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00011001 = ap_const_boolean_0)))) then
reg_771 <= bufw_Dout_A(63 downto 32);
reg_775 <= bufw_Dout_A(95 downto 64);
reg_779 <= bufw_Dout_A(127 downto 96);
reg_783 <= bufw_Dout_A(159 downto 128);
reg_787 <= bufw_Dout_A(191 downto 160);
reg_791 <= bufw_Dout_A(223 downto 192);
reg_795 <= bufw_Dout_A(255 downto 224);
reg_799 <= bufw_Dout_A(287 downto 256);
reg_803 <= bufw_Dout_A(319 downto 288);
reg_807 <= bufw_Dout_A(351 downto 320);
reg_811 <= bufw_Dout_A(383 downto 352);
reg_815 <= bufw_Dout_A(415 downto 384);
reg_819 <= bufw_Dout_A(447 downto 416);
reg_823 <= bufw_Dout_A(479 downto 448);
reg_827 <= bufw_Dout_A(511 downto 480);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (exitcond_flatten2_reg_3675 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (exitcond_flatten2_reg_3675 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (exitcond_flatten2_reg_3675 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011001 = ap_const_boolean_0)))) then
reg_831 <= bufw_Dout_A(63 downto 32);
reg_835 <= bufw_Dout_A(95 downto 64);
reg_839 <= bufw_Dout_A(127 downto 96);
reg_843 <= bufw_Dout_A(159 downto 128);
reg_847 <= bufw_Dout_A(191 downto 160);
reg_851 <= bufw_Dout_A(223 downto 192);
reg_855 <= bufw_Dout_A(255 downto 224);
reg_859 <= bufw_Dout_A(287 downto 256);
reg_863 <= bufw_Dout_A(319 downto 288);
reg_867 <= bufw_Dout_A(351 downto 320);
reg_871 <= bufw_Dout_A(383 downto 352);
reg_875 <= bufw_Dout_A(415 downto 384);
reg_879 <= bufw_Dout_A(447 downto 416);
reg_883 <= bufw_Dout_A(479 downto 448);
reg_887 <= bufw_Dout_A(511 downto 480);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (exitcond_flatten2_reg_3675 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (exitcond_flatten2_reg_3675 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00011001 = ap_const_boolean_0)) or ((exitcond_flatten2_reg_3675 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0)))) then
reg_891 <= bufw_Dout_A(63 downto 32);
reg_895 <= bufw_Dout_A(95 downto 64);
reg_899 <= bufw_Dout_A(127 downto 96);
reg_903 <= bufw_Dout_A(159 downto 128);
reg_907 <= bufw_Dout_A(191 downto 160);
reg_911 <= bufw_Dout_A(223 downto 192);
reg_915 <= bufw_Dout_A(255 downto 224);
reg_919 <= bufw_Dout_A(287 downto 256);
reg_923 <= bufw_Dout_A(319 downto 288);
reg_927 <= bufw_Dout_A(351 downto 320);
reg_931 <= bufw_Dout_A(383 downto 352);
reg_935 <= bufw_Dout_A(415 downto 384);
reg_939 <= bufw_Dout_A(447 downto 416);
reg_943 <= bufw_Dout_A(479 downto 448);
reg_947 <= bufw_Dout_A(511 downto 480);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_flatten2_reg_3675 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0))) then
row_b_1_reg_3834 <= row_b_1_fu_1282_p2;
tmp_43_reg_3824 <= tmp_43_fu_1273_p2;
tmp_4_mid2_cast_reg_3819(2 downto 0) <= tmp_4_mid2_cast_fu_1270_p1(2 downto 0);
tmp_5_reg_3814 <= tmp_5_fu_1265_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_lv1_0 = ap_reg_pp0_iter1_exitcond_flatten2_reg_3675) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0))) then
tmp_108_reg_5607 <= bufw_Dout_A(63 downto 32);
tmp_11_0_4_reg_5562 <= grp_fu_497_p2;
tmp_11_10_4_reg_5732 <= grp_fu_537_p2;
tmp_11_11_4_reg_5747 <= grp_fu_541_p2;
tmp_11_12_4_reg_5762 <= grp_fu_545_p2;
tmp_11_13_4_reg_5777 <= grp_fu_549_p2;
tmp_11_14_4_reg_5792 <= grp_fu_553_p2;
tmp_11_15_4_reg_5807 <= grp_fu_557_p2;
tmp_11_1_4_reg_5597 <= grp_fu_501_p2;
tmp_11_2_4_reg_5612 <= grp_fu_505_p2;
tmp_11_3_4_reg_5627 <= grp_fu_509_p2;
tmp_11_4_4_reg_5642 <= grp_fu_513_p2;
tmp_11_5_4_reg_5657 <= grp_fu_517_p2;
tmp_11_6_4_reg_5672 <= grp_fu_521_p2;
tmp_11_7_4_reg_5687 <= grp_fu_525_p2;
tmp_11_8_4_reg_5702 <= grp_fu_529_p2;
tmp_11_9_4_reg_5717 <= grp_fu_533_p2;
tmp_144_reg_5622 <= bufw_Dout_A(95 downto 64);
tmp_179_reg_5637 <= bufw_Dout_A(127 downto 96);
tmp_214_reg_5652 <= bufw_Dout_A(159 downto 128);
tmp_249_reg_5667 <= bufw_Dout_A(191 downto 160);
tmp_284_reg_5682 <= bufw_Dout_A(223 downto 192);
tmp_319_reg_5697 <= bufw_Dout_A(255 downto 224);
tmp_354_reg_5712 <= bufw_Dout_A(287 downto 256);
tmp_389_reg_5727 <= bufw_Dout_A(319 downto 288);
tmp_424_reg_5742 <= bufw_Dout_A(351 downto 320);
tmp_459_reg_5757 <= bufw_Dout_A(383 downto 352);
tmp_494_reg_5772 <= bufw_Dout_A(415 downto 384);
tmp_529_reg_5787 <= bufw_Dout_A(447 downto 416);
tmp_564_reg_5802 <= bufw_Dout_A(479 downto 448);
tmp_599_reg_5817 <= bufw_Dout_A(511 downto 480);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_lv1_0 = ap_reg_pp0_iter1_exitcond_flatten2_reg_3675) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0))) then
tmp_110_reg_5872 <= bufw_Dout_A(63 downto 32);
tmp_11_0_5_reg_5827 <= grp_fu_497_p2;
tmp_11_10_5_reg_5997 <= grp_fu_537_p2;
tmp_11_11_5_reg_6012 <= grp_fu_541_p2;
tmp_11_12_5_reg_6027 <= grp_fu_545_p2;
tmp_11_13_5_reg_6042 <= grp_fu_549_p2;
tmp_11_14_5_reg_6057 <= grp_fu_553_p2;
tmp_11_15_5_reg_6072 <= grp_fu_557_p2;
tmp_11_1_5_reg_5862 <= grp_fu_501_p2;
tmp_11_2_5_reg_5877 <= grp_fu_505_p2;
tmp_11_3_5_reg_5892 <= grp_fu_509_p2;
tmp_11_4_5_reg_5907 <= grp_fu_513_p2;
tmp_11_5_5_reg_5922 <= grp_fu_517_p2;
tmp_11_6_5_reg_5937 <= grp_fu_521_p2;
tmp_11_7_5_reg_5952 <= grp_fu_525_p2;
tmp_11_8_5_reg_5967 <= grp_fu_529_p2;
tmp_11_9_5_reg_5982 <= grp_fu_533_p2;
tmp_146_reg_5887 <= bufw_Dout_A(95 downto 64);
tmp_181_reg_5902 <= bufw_Dout_A(127 downto 96);
tmp_216_reg_5917 <= bufw_Dout_A(159 downto 128);
tmp_251_reg_5932 <= bufw_Dout_A(191 downto 160);
tmp_286_reg_5947 <= bufw_Dout_A(223 downto 192);
tmp_321_reg_5962 <= bufw_Dout_A(255 downto 224);
tmp_356_reg_5977 <= bufw_Dout_A(287 downto 256);
tmp_391_reg_5992 <= bufw_Dout_A(319 downto 288);
tmp_426_reg_6007 <= bufw_Dout_A(351 downto 320);
tmp_461_reg_6022 <= bufw_Dout_A(383 downto 352);
tmp_496_reg_6037 <= bufw_Dout_A(415 downto 384);
tmp_531_reg_6052 <= bufw_Dout_A(447 downto 416);
tmp_566_reg_6067 <= bufw_Dout_A(479 downto 448);
tmp_601_reg_6082 <= bufw_Dout_A(511 downto 480);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_lv1_0 = ap_reg_pp0_iter1_exitcond_flatten2_reg_3675) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0))) then
tmp_112_reg_6132 <= bufw_Dout_A(63 downto 32);
tmp_11_0_6_reg_6087 <= grp_fu_497_p2;
tmp_11_10_6_reg_6257 <= grp_fu_537_p2;
tmp_11_11_6_reg_6272 <= grp_fu_541_p2;
tmp_11_12_6_reg_6287 <= grp_fu_545_p2;
tmp_11_13_6_reg_6302 <= grp_fu_549_p2;
tmp_11_14_6_reg_6317 <= grp_fu_553_p2;
tmp_11_15_6_reg_6332 <= grp_fu_557_p2;
tmp_11_1_6_reg_6122 <= grp_fu_501_p2;
tmp_11_2_6_reg_6137 <= grp_fu_505_p2;
tmp_11_3_6_reg_6152 <= grp_fu_509_p2;
tmp_11_4_6_reg_6167 <= grp_fu_513_p2;
tmp_11_5_6_reg_6182 <= grp_fu_517_p2;
tmp_11_6_6_reg_6197 <= grp_fu_521_p2;
tmp_11_7_6_reg_6212 <= grp_fu_525_p2;
tmp_11_8_6_reg_6227 <= grp_fu_529_p2;
tmp_11_9_6_reg_6242 <= grp_fu_533_p2;
tmp_148_reg_6147 <= bufw_Dout_A(95 downto 64);
tmp_183_reg_6162 <= bufw_Dout_A(127 downto 96);
tmp_218_reg_6177 <= bufw_Dout_A(159 downto 128);
tmp_253_reg_6192 <= bufw_Dout_A(191 downto 160);
tmp_288_reg_6207 <= bufw_Dout_A(223 downto 192);
tmp_323_reg_6222 <= bufw_Dout_A(255 downto 224);
tmp_358_reg_6237 <= bufw_Dout_A(287 downto 256);
tmp_393_reg_6252 <= bufw_Dout_A(319 downto 288);
tmp_428_reg_6267 <= bufw_Dout_A(351 downto 320);
tmp_463_reg_6282 <= bufw_Dout_A(383 downto 352);
tmp_498_reg_6297 <= bufw_Dout_A(415 downto 384);
tmp_533_reg_6312 <= bufw_Dout_A(447 downto 416);
tmp_568_reg_6327 <= bufw_Dout_A(479 downto 448);
tmp_603_reg_6342 <= bufw_Dout_A(511 downto 480);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (exitcond_flatten2_reg_3675 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00011001 = ap_const_boolean_0))) then
tmp_116_reg_4702 <= grp_fu_497_p2;
tmp_11_10_reg_4837 <= grp_fu_541_p2;
tmp_11_11_reg_4847 <= grp_fu_545_p2;
tmp_11_12_reg_4857 <= grp_fu_549_p2;
tmp_11_13_reg_4867 <= grp_fu_553_p2;
tmp_11_14_reg_4877 <= grp_fu_557_p2;
tmp_11_1_reg_4737 <= grp_fu_501_p2;
tmp_11_2_reg_4747 <= grp_fu_505_p2;
tmp_11_3_reg_4757 <= grp_fu_509_p2;
tmp_11_4_reg_4767 <= grp_fu_513_p2;
tmp_11_5_reg_4777 <= grp_fu_517_p2;
tmp_11_6_reg_4787 <= grp_fu_521_p2;
tmp_11_7_reg_4797 <= grp_fu_525_p2;
tmp_11_8_reg_4807 <= grp_fu_529_p2;
tmp_11_9_reg_4817 <= grp_fu_533_p2;
tmp_11_s_reg_4827 <= grp_fu_537_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_flatten2_reg_3675 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0))) then
tmp_118_reg_4013 <= bufo_Dout_A(95 downto 64);
tmp_153_reg_4018 <= bufo_Dout_A(127 downto 96);
tmp_188_reg_4023 <= bufo_Dout_A(159 downto 128);
tmp_223_reg_4028 <= bufo_Dout_A(191 downto 160);
tmp_258_reg_4033 <= bufo_Dout_A(223 downto 192);
tmp_293_reg_4038 <= bufo_Dout_A(255 downto 224);
tmp_328_reg_4043 <= bufo_Dout_A(287 downto 256);
tmp_363_reg_4048 <= bufo_Dout_A(319 downto 288);
tmp_398_reg_4053 <= bufo_Dout_A(351 downto 320);
tmp_433_reg_4058 <= bufo_Dout_A(383 downto 352);
tmp_468_reg_4063 <= bufo_Dout_A(415 downto 384);
tmp_503_reg_4068 <= bufo_Dout_A(447 downto 416);
tmp_538_reg_4073 <= bufo_Dout_A(479 downto 448);
tmp_573_reg_4078 <= bufo_Dout_A(511 downto 480);
tmp_624_reg_3993 <= tmp_624_fu_1449_p2;
tmp_627_reg_3998 <= tmp_627_fu_1455_p1;
tmp_628_reg_4003 <= tmp_628_fu_1459_p1;
tmp_82_reg_4008 <= bufo_Dout_A(63 downto 32);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_lv1_0 = ap_reg_pp0_iter1_exitcond_flatten2_reg_3675))) then
tmp_11_0_10_reg_7147 <= grp_fu_497_p2;
tmp_11_10_10_reg_7267 <= grp_fu_537_p2;
tmp_11_11_10_reg_7277 <= grp_fu_541_p2;
tmp_11_12_10_reg_7287 <= grp_fu_545_p2;
tmp_11_13_10_reg_7297 <= grp_fu_549_p2;
tmp_11_14_10_reg_7307 <= grp_fu_553_p2;
tmp_11_15_10_reg_7317 <= grp_fu_557_p2;
tmp_11_1_10_reg_7177 <= grp_fu_501_p2;
tmp_11_2_10_reg_7187 <= grp_fu_505_p2;
tmp_11_3_10_reg_7197 <= grp_fu_509_p2;
tmp_11_4_10_reg_7207 <= grp_fu_513_p2;
tmp_11_5_10_reg_7217 <= grp_fu_517_p2;
tmp_11_6_10_reg_7227 <= grp_fu_521_p2;
tmp_11_7_10_reg_7237 <= grp_fu_525_p2;
tmp_11_8_10_reg_7247 <= grp_fu_529_p2;
tmp_11_9_10_reg_7257 <= grp_fu_533_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_lv1_0 = ap_reg_pp0_iter1_exitcond_flatten2_reg_3675))) then
tmp_11_0_11_reg_7327 <= grp_fu_497_p2;
tmp_11_10_11_reg_7377 <= grp_fu_537_p2;
tmp_11_11_11_reg_7382 <= grp_fu_541_p2;
tmp_11_12_11_reg_7387 <= grp_fu_545_p2;
tmp_11_13_11_reg_7392 <= grp_fu_549_p2;
tmp_11_14_11_reg_7397 <= grp_fu_553_p2;
tmp_11_15_11_reg_7402 <= grp_fu_557_p2;
tmp_11_1_11_reg_7332 <= grp_fu_501_p2;
tmp_11_2_11_reg_7337 <= grp_fu_505_p2;
tmp_11_3_11_reg_7342 <= grp_fu_509_p2;
tmp_11_4_11_reg_7347 <= grp_fu_513_p2;
tmp_11_5_11_reg_7352 <= grp_fu_517_p2;
tmp_11_6_11_reg_7357 <= grp_fu_521_p2;
tmp_11_7_11_reg_7362 <= grp_fu_525_p2;
tmp_11_8_11_reg_7367 <= grp_fu_529_p2;
tmp_11_9_11_reg_7372 <= grp_fu_533_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_lv1_0 = ap_reg_pp0_iter1_exitcond_flatten2_reg_3675))) then
tmp_11_0_12_reg_7407 <= grp_fu_497_p2;
tmp_11_10_12_reg_7457 <= grp_fu_537_p2;
tmp_11_11_12_reg_7462 <= grp_fu_541_p2;
tmp_11_12_12_reg_7467 <= grp_fu_545_p2;
tmp_11_13_12_reg_7472 <= grp_fu_549_p2;
tmp_11_14_12_reg_7477 <= grp_fu_553_p2;
tmp_11_15_12_reg_7482 <= grp_fu_557_p2;
tmp_11_1_12_reg_7412 <= grp_fu_501_p2;
tmp_11_2_12_reg_7417 <= grp_fu_505_p2;
tmp_11_3_12_reg_7422 <= grp_fu_509_p2;
tmp_11_4_12_reg_7427 <= grp_fu_513_p2;
tmp_11_5_12_reg_7432 <= grp_fu_517_p2;
tmp_11_6_12_reg_7437 <= grp_fu_521_p2;
tmp_11_7_12_reg_7442 <= grp_fu_525_p2;
tmp_11_8_12_reg_7447 <= grp_fu_529_p2;
tmp_11_9_12_reg_7452 <= grp_fu_533_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_lv1_0 = ap_reg_pp0_iter1_exitcond_flatten2_reg_3675))) then
tmp_11_0_13_reg_7487 <= grp_fu_497_p2;
tmp_11_10_13_reg_7537 <= grp_fu_537_p2;
tmp_11_11_13_reg_7542 <= grp_fu_541_p2;
tmp_11_12_13_reg_7547 <= grp_fu_545_p2;
tmp_11_13_13_reg_7552 <= grp_fu_549_p2;
tmp_11_14_13_reg_7557 <= grp_fu_553_p2;
tmp_11_15_13_reg_7562 <= grp_fu_557_p2;
tmp_11_1_13_reg_7492 <= grp_fu_501_p2;
tmp_11_2_13_reg_7497 <= grp_fu_505_p2;
tmp_11_3_13_reg_7502 <= grp_fu_509_p2;
tmp_11_4_13_reg_7507 <= grp_fu_513_p2;
tmp_11_5_13_reg_7512 <= grp_fu_517_p2;
tmp_11_6_13_reg_7517 <= grp_fu_521_p2;
tmp_11_7_13_reg_7522 <= grp_fu_525_p2;
tmp_11_8_13_reg_7527 <= grp_fu_529_p2;
tmp_11_9_13_reg_7532 <= grp_fu_533_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_lv1_0 = ap_reg_pp0_iter1_exitcond_flatten2_reg_3675))) then
tmp_11_0_14_reg_7567 <= grp_fu_497_p2;
tmp_11_10_14_reg_7617 <= grp_fu_537_p2;
tmp_11_11_14_reg_7622 <= grp_fu_541_p2;
tmp_11_12_14_reg_7627 <= grp_fu_545_p2;
tmp_11_13_14_reg_7632 <= grp_fu_549_p2;
tmp_11_14_14_reg_7637 <= grp_fu_553_p2;
tmp_11_15_14_reg_7642 <= grp_fu_557_p2;
tmp_11_1_14_reg_7572 <= grp_fu_501_p2;
tmp_11_2_14_reg_7577 <= grp_fu_505_p2;
tmp_11_3_14_reg_7582 <= grp_fu_509_p2;
tmp_11_4_14_reg_7587 <= grp_fu_513_p2;
tmp_11_5_14_reg_7592 <= grp_fu_517_p2;
tmp_11_6_14_reg_7597 <= grp_fu_521_p2;
tmp_11_7_14_reg_7602 <= grp_fu_525_p2;
tmp_11_8_14_reg_7607 <= grp_fu_529_p2;
tmp_11_9_14_reg_7612 <= grp_fu_533_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (exitcond_flatten2_reg_3675 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00011001 = ap_const_boolean_0))) then
tmp_11_0_1_reg_4902 <= grp_fu_497_p2;
tmp_11_10_1_reg_5077 <= grp_fu_537_p2;
tmp_11_11_1_reg_5092 <= grp_fu_541_p2;
tmp_11_12_1_reg_5107 <= grp_fu_545_p2;
tmp_11_13_1_reg_5122 <= grp_fu_549_p2;
tmp_11_14_1_reg_5137 <= grp_fu_553_p2;
tmp_11_15_1_reg_5152 <= grp_fu_557_p2;
tmp_11_1_1_reg_4942 <= grp_fu_501_p2;
tmp_11_2_1_reg_4957 <= grp_fu_505_p2;
tmp_11_3_1_reg_4972 <= grp_fu_509_p2;
tmp_11_4_1_reg_4987 <= grp_fu_513_p2;
tmp_11_5_1_reg_5002 <= grp_fu_517_p2;
tmp_11_6_1_reg_5017 <= grp_fu_521_p2;
tmp_11_7_1_reg_5032 <= grp_fu_525_p2;
tmp_11_8_1_reg_5047 <= grp_fu_529_p2;
tmp_11_9_1_reg_5062 <= grp_fu_533_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (exitcond_flatten2_reg_3675 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011001 = ap_const_boolean_0))) then
tmp_11_0_2_reg_5172 <= grp_fu_497_p2;
tmp_11_10_2_reg_5297 <= grp_fu_537_p2;
tmp_11_11_2_reg_5307 <= grp_fu_541_p2;
tmp_11_12_2_reg_5317 <= grp_fu_545_p2;
tmp_11_13_2_reg_5327 <= grp_fu_549_p2;
tmp_11_14_2_reg_5337 <= grp_fu_553_p2;
tmp_11_15_2_reg_5347 <= grp_fu_557_p2;
tmp_11_1_2_reg_5207 <= grp_fu_501_p2;
tmp_11_2_2_reg_5217 <= grp_fu_505_p2;
tmp_11_3_2_reg_5227 <= grp_fu_509_p2;
tmp_11_4_2_reg_5237 <= grp_fu_513_p2;
tmp_11_5_2_reg_5247 <= grp_fu_517_p2;
tmp_11_6_2_reg_5257 <= grp_fu_521_p2;
tmp_11_7_2_reg_5267 <= grp_fu_525_p2;
tmp_11_8_2_reg_5277 <= grp_fu_529_p2;
tmp_11_9_2_reg_5287 <= grp_fu_533_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_flatten2_reg_3675 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
tmp_11_0_3_reg_5372 <= grp_fu_497_p2;
tmp_11_10_3_reg_5497 <= grp_fu_537_p2;
tmp_11_11_3_reg_5507 <= grp_fu_541_p2;
tmp_11_12_3_reg_5517 <= grp_fu_545_p2;
tmp_11_13_3_reg_5527 <= grp_fu_549_p2;
tmp_11_14_3_reg_5537 <= grp_fu_553_p2;
tmp_11_15_3_reg_5547 <= grp_fu_557_p2;
tmp_11_1_3_reg_5407 <= grp_fu_501_p2;
tmp_11_2_3_reg_5417 <= grp_fu_505_p2;
tmp_11_3_3_reg_5427 <= grp_fu_509_p2;
tmp_11_4_3_reg_5437 <= grp_fu_513_p2;
tmp_11_5_3_reg_5447 <= grp_fu_517_p2;
tmp_11_6_3_reg_5457 <= grp_fu_521_p2;
tmp_11_7_3_reg_5467 <= grp_fu_525_p2;
tmp_11_8_3_reg_5477 <= grp_fu_529_p2;
tmp_11_9_3_reg_5487 <= grp_fu_533_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_lv1_0 = ap_reg_pp0_iter1_exitcond_flatten2_reg_3675) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0))) then
tmp_11_0_7_reg_6347 <= grp_fu_497_p2;
tmp_11_10_7_reg_6467 <= grp_fu_537_p2;
tmp_11_11_7_reg_6477 <= grp_fu_541_p2;
tmp_11_12_7_reg_6487 <= grp_fu_545_p2;
tmp_11_13_7_reg_6497 <= grp_fu_549_p2;
tmp_11_14_7_reg_6507 <= grp_fu_553_p2;
tmp_11_15_7_reg_6517 <= grp_fu_557_p2;
tmp_11_1_7_reg_6377 <= grp_fu_501_p2;
tmp_11_2_7_reg_6387 <= grp_fu_505_p2;
tmp_11_3_7_reg_6397 <= grp_fu_509_p2;
tmp_11_4_7_reg_6407 <= grp_fu_513_p2;
tmp_11_5_7_reg_6417 <= grp_fu_517_p2;
tmp_11_6_7_reg_6427 <= grp_fu_521_p2;
tmp_11_7_7_reg_6437 <= grp_fu_525_p2;
tmp_11_8_7_reg_6447 <= grp_fu_529_p2;
tmp_11_9_7_reg_6457 <= grp_fu_533_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_lv1_0 = ap_reg_pp0_iter1_exitcond_flatten2_reg_3675))) then
tmp_11_0_8_reg_6527 <= grp_fu_497_p2;
tmp_11_10_8_reg_6647 <= grp_fu_537_p2;
tmp_11_11_8_reg_6657 <= grp_fu_541_p2;
tmp_11_12_8_reg_6667 <= grp_fu_545_p2;
tmp_11_13_8_reg_6677 <= grp_fu_549_p2;
tmp_11_14_8_reg_6687 <= grp_fu_553_p2;
tmp_11_15_8_reg_6697 <= grp_fu_557_p2;
tmp_11_1_8_reg_6557 <= grp_fu_501_p2;
tmp_11_2_8_reg_6567 <= grp_fu_505_p2;
tmp_11_3_8_reg_6577 <= grp_fu_509_p2;
tmp_11_4_8_reg_6587 <= grp_fu_513_p2;
tmp_11_5_8_reg_6597 <= grp_fu_517_p2;
tmp_11_6_8_reg_6607 <= grp_fu_521_p2;
tmp_11_7_8_reg_6617 <= grp_fu_525_p2;
tmp_11_8_8_reg_6627 <= grp_fu_529_p2;
tmp_11_9_8_reg_6637 <= grp_fu_533_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_lv1_0 = ap_reg_pp0_iter1_exitcond_flatten2_reg_3675))) then
tmp_11_0_9_reg_6712 <= grp_fu_497_p2;
tmp_11_10_9_reg_6882 <= grp_fu_537_p2;
tmp_11_11_9_reg_6897 <= grp_fu_541_p2;
tmp_11_12_9_reg_6912 <= grp_fu_545_p2;
tmp_11_13_9_reg_6927 <= grp_fu_549_p2;
tmp_11_14_9_reg_6942 <= grp_fu_553_p2;
tmp_11_15_9_reg_6957 <= grp_fu_557_p2;
tmp_11_1_9_reg_6747 <= grp_fu_501_p2;
tmp_11_2_9_reg_6762 <= grp_fu_505_p2;
tmp_11_3_9_reg_6777 <= grp_fu_509_p2;
tmp_11_4_9_reg_6792 <= grp_fu_513_p2;
tmp_11_5_9_reg_6807 <= grp_fu_517_p2;
tmp_11_6_9_reg_6822 <= grp_fu_521_p2;
tmp_11_7_9_reg_6837 <= grp_fu_525_p2;
tmp_11_8_9_reg_6852 <= grp_fu_529_p2;
tmp_11_9_9_reg_6867 <= grp_fu_533_p2;
tmp_12_10_reg_6892 <= grp_fu_477_p2;
tmp_12_11_reg_6907 <= grp_fu_481_p2;
tmp_12_12_reg_6922 <= grp_fu_485_p2;
tmp_12_13_reg_6937 <= grp_fu_489_p2;
tmp_12_14_reg_6952 <= grp_fu_493_p2;
tmp_12_1_reg_6742 <= grp_fu_437_p2;
tmp_12_2_reg_6757 <= grp_fu_441_p2;
tmp_12_3_reg_6772 <= grp_fu_445_p2;
tmp_12_4_reg_6787 <= grp_fu_449_p2;
tmp_12_5_reg_6802 <= grp_fu_453_p2;
tmp_12_6_reg_6817 <= grp_fu_457_p2;
tmp_12_7_reg_6832 <= grp_fu_461_p2;
tmp_12_8_reg_6847 <= grp_fu_465_p2;
tmp_12_9_reg_6862 <= grp_fu_469_p2;
tmp_12_s_reg_6877 <= grp_fu_473_p2;
tmp_607_reg_6707 <= grp_fu_433_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_lv1_0 = ap_reg_pp0_iter1_exitcond_flatten2_reg_3675))) then
tmp_11_0_s_reg_6967 <= grp_fu_497_p2;
tmp_11_10_s_reg_7087 <= grp_fu_537_p2;
tmp_11_11_s_reg_7097 <= grp_fu_541_p2;
tmp_11_12_s_reg_7107 <= grp_fu_545_p2;
tmp_11_13_s_reg_7117 <= grp_fu_549_p2;
tmp_11_14_s_reg_7127 <= grp_fu_553_p2;
tmp_11_15_s_reg_7137 <= grp_fu_557_p2;
tmp_11_1_s_reg_6997 <= grp_fu_501_p2;
tmp_11_2_s_reg_7007 <= grp_fu_505_p2;
tmp_11_3_s_reg_7017 <= grp_fu_509_p2;
tmp_11_4_s_reg_7027 <= grp_fu_513_p2;
tmp_11_5_s_reg_7037 <= grp_fu_517_p2;
tmp_11_6_s_reg_7047 <= grp_fu_521_p2;
tmp_11_7_s_reg_7057 <= grp_fu_525_p2;
tmp_11_8_s_reg_7067 <= grp_fu_529_p2;
tmp_11_9_s_reg_7077 <= grp_fu_533_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_const_lv1_0 = ap_reg_pp0_iter7_exitcond_flatten2_reg_3675))) then
tmp_12_0_10_reg_8367 <= grp_fu_433_p2;
tmp_12_10_10_reg_8417 <= grp_fu_473_p2;
tmp_12_11_10_reg_8422 <= grp_fu_477_p2;
tmp_12_12_10_reg_8427 <= grp_fu_481_p2;
tmp_12_13_10_reg_8432 <= grp_fu_485_p2;
tmp_12_14_10_reg_8437 <= grp_fu_489_p2;
tmp_12_15_10_reg_8442 <= grp_fu_493_p2;
tmp_12_1_10_reg_8372 <= grp_fu_437_p2;
tmp_12_2_10_reg_8377 <= grp_fu_441_p2;
tmp_12_3_10_reg_8382 <= grp_fu_445_p2;
tmp_12_4_10_reg_8387 <= grp_fu_449_p2;
tmp_12_5_10_reg_8392 <= grp_fu_453_p2;
tmp_12_6_10_reg_8397 <= grp_fu_457_p2;
tmp_12_7_10_reg_8402 <= grp_fu_461_p2;
tmp_12_8_10_reg_8407 <= grp_fu_465_p2;
tmp_12_9_10_reg_8412 <= grp_fu_469_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_const_lv1_0 = ap_reg_pp0_iter8_exitcond_flatten2_reg_3675))) then
tmp_12_0_11_reg_8447 <= grp_fu_433_p2;
tmp_12_10_11_reg_8497 <= grp_fu_473_p2;
tmp_12_11_11_reg_8502 <= grp_fu_477_p2;
tmp_12_12_11_reg_8507 <= grp_fu_481_p2;
tmp_12_13_11_reg_8512 <= grp_fu_485_p2;
tmp_12_14_11_reg_8517 <= grp_fu_489_p2;
tmp_12_15_11_reg_8522 <= grp_fu_493_p2;
tmp_12_1_11_reg_8452 <= grp_fu_437_p2;
tmp_12_2_11_reg_8457 <= grp_fu_441_p2;
tmp_12_3_11_reg_8462 <= grp_fu_445_p2;
tmp_12_4_11_reg_8467 <= grp_fu_449_p2;
tmp_12_5_11_reg_8472 <= grp_fu_453_p2;
tmp_12_6_11_reg_8477 <= grp_fu_457_p2;
tmp_12_7_11_reg_8482 <= grp_fu_461_p2;
tmp_12_8_11_reg_8487 <= grp_fu_465_p2;
tmp_12_9_11_reg_8492 <= grp_fu_469_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_const_lv1_0 = ap_reg_pp0_iter8_exitcond_flatten2_reg_3675))) then
tmp_12_0_12_reg_8527 <= grp_fu_433_p2;
tmp_12_10_12_reg_8577 <= grp_fu_473_p2;
tmp_12_11_12_reg_8582 <= grp_fu_477_p2;
tmp_12_12_12_reg_8587 <= grp_fu_481_p2;
tmp_12_13_12_reg_8592 <= grp_fu_485_p2;
tmp_12_14_12_reg_8597 <= grp_fu_489_p2;
tmp_12_15_12_reg_8602 <= grp_fu_493_p2;
tmp_12_1_12_reg_8532 <= grp_fu_437_p2;
tmp_12_2_12_reg_8537 <= grp_fu_441_p2;
tmp_12_3_12_reg_8542 <= grp_fu_445_p2;
tmp_12_4_12_reg_8547 <= grp_fu_449_p2;
tmp_12_5_12_reg_8552 <= grp_fu_453_p2;
tmp_12_6_12_reg_8557 <= grp_fu_457_p2;
tmp_12_7_12_reg_8562 <= grp_fu_461_p2;
tmp_12_8_12_reg_8567 <= grp_fu_465_p2;
tmp_12_9_12_reg_8572 <= grp_fu_469_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter9) and (ap_const_lv1_0 = ap_reg_pp0_iter9_exitcond_flatten2_reg_3675) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0))) then
tmp_12_0_13_reg_8607 <= grp_fu_433_p2;
tmp_12_10_13_reg_8657 <= grp_fu_473_p2;
tmp_12_11_13_reg_8662 <= grp_fu_477_p2;
tmp_12_12_13_reg_8667 <= grp_fu_481_p2;
tmp_12_13_13_reg_8672 <= grp_fu_485_p2;
tmp_12_14_13_reg_8677 <= grp_fu_489_p2;
tmp_12_15_13_reg_8682 <= grp_fu_493_p2;
tmp_12_1_13_reg_8612 <= grp_fu_437_p2;
tmp_12_2_13_reg_8617 <= grp_fu_441_p2;
tmp_12_3_13_reg_8622 <= grp_fu_445_p2;
tmp_12_4_13_reg_8627 <= grp_fu_449_p2;
tmp_12_5_13_reg_8632 <= grp_fu_453_p2;
tmp_12_6_13_reg_8637 <= grp_fu_457_p2;
tmp_12_7_13_reg_8642 <= grp_fu_461_p2;
tmp_12_8_13_reg_8647 <= grp_fu_465_p2;
tmp_12_9_13_reg_8652 <= grp_fu_469_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_const_lv1_0 = ap_reg_pp0_iter2_exitcond_flatten2_reg_3675))) then
tmp_12_0_2_reg_7647 <= grp_fu_433_p2;
tmp_12_10_2_reg_7697 <= grp_fu_473_p2;
tmp_12_11_2_reg_7702 <= grp_fu_477_p2;
tmp_12_12_2_reg_7707 <= grp_fu_481_p2;
tmp_12_13_2_reg_7712 <= grp_fu_485_p2;
tmp_12_14_2_reg_7717 <= grp_fu_489_p2;
tmp_12_15_2_reg_7722 <= grp_fu_493_p2;
tmp_12_1_2_reg_7652 <= grp_fu_437_p2;
tmp_12_2_2_reg_7657 <= grp_fu_441_p2;
tmp_12_3_2_reg_7662 <= grp_fu_445_p2;
tmp_12_4_2_reg_7667 <= grp_fu_449_p2;
tmp_12_5_2_reg_7672 <= grp_fu_453_p2;
tmp_12_6_2_reg_7677 <= grp_fu_457_p2;
tmp_12_7_2_reg_7682 <= grp_fu_461_p2;
tmp_12_8_2_reg_7687 <= grp_fu_465_p2;
tmp_12_9_2_reg_7692 <= grp_fu_469_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_const_lv1_0 = ap_reg_pp0_iter3_exitcond_flatten2_reg_3675))) then
tmp_12_0_3_reg_7727 <= grp_fu_433_p2;
tmp_12_10_3_reg_7777 <= grp_fu_473_p2;
tmp_12_11_3_reg_7782 <= grp_fu_477_p2;
tmp_12_12_3_reg_7787 <= grp_fu_481_p2;
tmp_12_13_3_reg_7792 <= grp_fu_485_p2;
tmp_12_14_3_reg_7797 <= grp_fu_489_p2;
tmp_12_15_3_reg_7802 <= grp_fu_493_p2;
tmp_12_1_3_reg_7732 <= grp_fu_437_p2;
tmp_12_2_3_reg_7737 <= grp_fu_441_p2;
tmp_12_3_3_reg_7742 <= grp_fu_445_p2;
tmp_12_4_3_reg_7747 <= grp_fu_449_p2;
tmp_12_5_3_reg_7752 <= grp_fu_453_p2;
tmp_12_6_3_reg_7757 <= grp_fu_457_p2;
tmp_12_7_3_reg_7762 <= grp_fu_461_p2;
tmp_12_8_3_reg_7767 <= grp_fu_465_p2;
tmp_12_9_3_reg_7772 <= grp_fu_469_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_const_lv1_0 = ap_reg_pp0_iter3_exitcond_flatten2_reg_3675))) then
tmp_12_0_4_reg_7807 <= grp_fu_433_p2;
tmp_12_10_4_reg_7857 <= grp_fu_473_p2;
tmp_12_11_4_reg_7862 <= grp_fu_477_p2;
tmp_12_12_4_reg_7867 <= grp_fu_481_p2;
tmp_12_13_4_reg_7872 <= grp_fu_485_p2;
tmp_12_14_4_reg_7877 <= grp_fu_489_p2;
tmp_12_15_4_reg_7882 <= grp_fu_493_p2;
tmp_12_1_4_reg_7812 <= grp_fu_437_p2;
tmp_12_2_4_reg_7817 <= grp_fu_441_p2;
tmp_12_3_4_reg_7822 <= grp_fu_445_p2;
tmp_12_4_4_reg_7827 <= grp_fu_449_p2;
tmp_12_5_4_reg_7832 <= grp_fu_453_p2;
tmp_12_6_4_reg_7837 <= grp_fu_457_p2;
tmp_12_7_4_reg_7842 <= grp_fu_461_p2;
tmp_12_8_4_reg_7847 <= grp_fu_465_p2;
tmp_12_9_4_reg_7852 <= grp_fu_469_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_const_lv1_0 = ap_reg_pp0_iter4_exitcond_flatten2_reg_3675))) then
tmp_12_0_5_reg_7887 <= grp_fu_433_p2;
tmp_12_10_5_reg_7937 <= grp_fu_473_p2;
tmp_12_11_5_reg_7942 <= grp_fu_477_p2;
tmp_12_12_5_reg_7947 <= grp_fu_481_p2;
tmp_12_13_5_reg_7952 <= grp_fu_485_p2;
tmp_12_14_5_reg_7957 <= grp_fu_489_p2;
tmp_12_15_5_reg_7962 <= grp_fu_493_p2;
tmp_12_1_5_reg_7892 <= grp_fu_437_p2;
tmp_12_2_5_reg_7897 <= grp_fu_441_p2;
tmp_12_3_5_reg_7902 <= grp_fu_445_p2;
tmp_12_4_5_reg_7907 <= grp_fu_449_p2;
tmp_12_5_5_reg_7912 <= grp_fu_453_p2;
tmp_12_6_5_reg_7917 <= grp_fu_457_p2;
tmp_12_7_5_reg_7922 <= grp_fu_461_p2;
tmp_12_8_5_reg_7927 <= grp_fu_465_p2;
tmp_12_9_5_reg_7932 <= grp_fu_469_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_const_lv1_0 = ap_reg_pp0_iter4_exitcond_flatten2_reg_3675))) then
tmp_12_0_6_reg_7967 <= grp_fu_433_p2;
tmp_12_10_6_reg_8017 <= grp_fu_473_p2;
tmp_12_11_6_reg_8022 <= grp_fu_477_p2;
tmp_12_12_6_reg_8027 <= grp_fu_481_p2;
tmp_12_13_6_reg_8032 <= grp_fu_485_p2;
tmp_12_14_6_reg_8037 <= grp_fu_489_p2;
tmp_12_15_6_reg_8042 <= grp_fu_493_p2;
tmp_12_1_6_reg_7972 <= grp_fu_437_p2;
tmp_12_2_6_reg_7977 <= grp_fu_441_p2;
tmp_12_3_6_reg_7982 <= grp_fu_445_p2;
tmp_12_4_6_reg_7987 <= grp_fu_449_p2;
tmp_12_5_6_reg_7992 <= grp_fu_453_p2;
tmp_12_6_6_reg_7997 <= grp_fu_457_p2;
tmp_12_7_6_reg_8002 <= grp_fu_461_p2;
tmp_12_8_6_reg_8007 <= grp_fu_465_p2;
tmp_12_9_6_reg_8012 <= grp_fu_469_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_const_lv1_0 = ap_reg_pp0_iter5_exitcond_flatten2_reg_3675))) then
tmp_12_0_7_reg_8047 <= grp_fu_433_p2;
tmp_12_10_7_reg_8097 <= grp_fu_473_p2;
tmp_12_11_7_reg_8102 <= grp_fu_477_p2;
tmp_12_12_7_reg_8107 <= grp_fu_481_p2;
tmp_12_13_7_reg_8112 <= grp_fu_485_p2;
tmp_12_14_7_reg_8117 <= grp_fu_489_p2;
tmp_12_15_7_reg_8122 <= grp_fu_493_p2;
tmp_12_1_7_reg_8052 <= grp_fu_437_p2;
tmp_12_2_7_reg_8057 <= grp_fu_441_p2;
tmp_12_3_7_reg_8062 <= grp_fu_445_p2;
tmp_12_4_7_reg_8067 <= grp_fu_449_p2;
tmp_12_5_7_reg_8072 <= grp_fu_453_p2;
tmp_12_6_7_reg_8077 <= grp_fu_457_p2;
tmp_12_7_7_reg_8082 <= grp_fu_461_p2;
tmp_12_8_7_reg_8087 <= grp_fu_465_p2;
tmp_12_9_7_reg_8092 <= grp_fu_469_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_const_lv1_0 = ap_reg_pp0_iter5_exitcond_flatten2_reg_3675))) then
tmp_12_0_8_reg_8127 <= grp_fu_433_p2;
tmp_12_10_8_reg_8177 <= grp_fu_473_p2;
tmp_12_11_8_reg_8182 <= grp_fu_477_p2;
tmp_12_12_8_reg_8187 <= grp_fu_481_p2;
tmp_12_13_8_reg_8192 <= grp_fu_485_p2;
tmp_12_14_8_reg_8197 <= grp_fu_489_p2;
tmp_12_15_8_reg_8202 <= grp_fu_493_p2;
tmp_12_1_8_reg_8132 <= grp_fu_437_p2;
tmp_12_2_8_reg_8137 <= grp_fu_441_p2;
tmp_12_3_8_reg_8142 <= grp_fu_445_p2;
tmp_12_4_8_reg_8147 <= grp_fu_449_p2;
tmp_12_5_8_reg_8152 <= grp_fu_453_p2;
tmp_12_6_8_reg_8157 <= grp_fu_457_p2;
tmp_12_7_8_reg_8162 <= grp_fu_461_p2;
tmp_12_8_8_reg_8167 <= grp_fu_465_p2;
tmp_12_9_8_reg_8172 <= grp_fu_469_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6) and (ap_const_lv1_0 = ap_reg_pp0_iter6_exitcond_flatten2_reg_3675))) then
tmp_12_0_9_reg_8207 <= grp_fu_433_p2;
tmp_12_10_9_reg_8257 <= grp_fu_473_p2;
tmp_12_11_9_reg_8262 <= grp_fu_477_p2;
tmp_12_12_9_reg_8267 <= grp_fu_481_p2;
tmp_12_13_9_reg_8272 <= grp_fu_485_p2;
tmp_12_14_9_reg_8277 <= grp_fu_489_p2;
tmp_12_15_9_reg_8282 <= grp_fu_493_p2;
tmp_12_1_9_reg_8212 <= grp_fu_437_p2;
tmp_12_2_9_reg_8217 <= grp_fu_441_p2;
tmp_12_3_9_reg_8222 <= grp_fu_445_p2;
tmp_12_4_9_reg_8227 <= grp_fu_449_p2;
tmp_12_5_9_reg_8232 <= grp_fu_453_p2;
tmp_12_6_9_reg_8237 <= grp_fu_457_p2;
tmp_12_7_9_reg_8242 <= grp_fu_461_p2;
tmp_12_8_9_reg_8247 <= grp_fu_465_p2;
tmp_12_9_9_reg_8252 <= grp_fu_469_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_lv1_0 = ap_reg_pp0_iter6_exitcond_flatten2_reg_3675) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7))) then
tmp_12_0_s_reg_8287 <= grp_fu_433_p2;
tmp_12_10_s_reg_8337 <= grp_fu_473_p2;
tmp_12_11_s_reg_8342 <= grp_fu_477_p2;
tmp_12_12_s_reg_8347 <= grp_fu_481_p2;
tmp_12_13_s_reg_8352 <= grp_fu_485_p2;
tmp_12_14_s_reg_8357 <= grp_fu_489_p2;
tmp_12_15_s_reg_8362 <= grp_fu_493_p2;
tmp_12_1_s_reg_8292 <= grp_fu_437_p2;
tmp_12_2_s_reg_8297 <= grp_fu_441_p2;
tmp_12_3_s_reg_8302 <= grp_fu_445_p2;
tmp_12_4_s_reg_8307 <= grp_fu_449_p2;
tmp_12_5_s_reg_8312 <= grp_fu_453_p2;
tmp_12_6_s_reg_8317 <= grp_fu_457_p2;
tmp_12_7_s_reg_8322 <= grp_fu_461_p2;
tmp_12_8_s_reg_8327 <= grp_fu_465_p2;
tmp_12_9_s_reg_8332 <= grp_fu_469_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_flatten2_reg_3675 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0))) then
tmp_21_reg_4132 <= bufi_Dout_A(63 downto 32);
tmp_25_reg_4137 <= bufi_Dout_A(95 downto 64);
tmp_29_reg_4147 <= bufi_Dout_A(127 downto 96);
tmp_33_reg_4152 <= bufi_Dout_A(159 downto 128);
tmp_37_reg_4157 <= bufi_Dout_A(191 downto 160);
tmp_41_reg_4162 <= bufi_Dout_A(223 downto 192);
tmp_45_reg_4167 <= bufi_Dout_A(255 downto 224);
tmp_49_reg_4172 <= bufi_Dout_A(287 downto 256);
tmp_53_reg_4177 <= bufi_Dout_A(319 downto 288);
tmp_57_reg_4182 <= bufi_Dout_A(351 downto 320);
tmp_61_reg_4187 <= bufi_Dout_A(383 downto 352);
tmp_626_reg_4127 <= tmp_626_fu_1657_p1;
tmp_630_reg_4142 <= tmp_630_fu_1681_p1;
tmp_63_reg_4122 <= tmp_63_fu_1652_p2;
tmp_65_reg_4192 <= bufi_Dout_A(415 downto 384);
tmp_69_reg_4197 <= bufi_Dout_A(447 downto 416);
tmp_73_reg_4202 <= bufi_Dout_A(479 downto 448);
tmp_77_reg_4207 <= bufi_Dout_A(511 downto 480);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_flatten2_reg_3675 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0))) then
tmp_2_cast1_reg_4442(5 downto 0) <= tmp_2_cast1_fu_2047_p1(5 downto 0);
tmp_4_mid2_cast1_reg_4452(2 downto 0) <= tmp_4_mid2_cast1_fu_2056_p1(2 downto 0);
tmp_608_reg_4467 <= tmp_608_fu_2063_p2;
tmp_633_reg_4497 <= tmp_633_fu_2092_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_flatten2_reg_3675 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0))) then
tmp_2_cast2_reg_4083(5 downto 0) <= tmp_2_cast2_fu_1613_p1(5 downto 0);
tmp_4_mid2_cast3_reg_4090(2 downto 0) <= tmp_4_mid2_cast3_fu_1622_p1(2 downto 0);
tmp_59_reg_4102 <= tmp_59_fu_1629_p2;
tmp_629_reg_4112 <= tmp_629_fu_1639_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0) and (exitcond_flatten2_reg_3675 = ap_const_lv1_0))) then
tmp_51_reg_3967 <= tmp_51_fu_1395_p2;
tmp_55_reg_3972 <= tmp_55_fu_1400_p2;
tmp_625_reg_3983 <= tmp_625_fu_1410_p1;
tmp_8_cast_mid2_reg_3977 <= tmp_8_cast_mid2_fu_1405_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_flatten2_reg_3675 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00011001 = ap_const_boolean_0))) then
tmp_609_reg_4582 <= tmp_609_fu_2180_p2;
tmp_634_reg_4612 <= tmp_634_fu_2208_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_flatten2_reg_3675 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00011001 = ap_const_boolean_0))) then
tmp_610_reg_4697 <= tmp_610_fu_2296_p2;
tmp_636_reg_4732 <= tmp_636_fu_2324_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_flatten2_reg_3675 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00011001 = ap_const_boolean_0))) then
tmp_611_reg_4892 <= tmp_611_fu_2412_p2;
tmp_637_reg_4932 <= tmp_637_fu_2444_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_flatten2_reg_3675 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011001 = ap_const_boolean_0))) then
tmp_612_reg_5167 <= tmp_612_fu_2592_p2;
tmp_638_reg_5202 <= tmp_638_fu_2620_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_flatten2_reg_3675 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
tmp_613_reg_5362 <= tmp_613_fu_2713_p2;
tmp_614_reg_5367 <= tmp_614_fu_2718_p2;
tmp_639_reg_5402 <= tmp_639_fu_2746_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_flatten2_reg_3675 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0))) then
tmp_631_reg_4252 <= tmp_631_fu_1862_p1;
tmp_67_reg_4217 <= tmp_67_fu_1829_p2;
tmp_71_reg_4222 <= tmp_71_fu_1834_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_flatten2_reg_3675 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0))) then
tmp_632_reg_4362 <= tmp_632_fu_1968_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_lv1_0 = ap_reg_pp0_iter1_exitcond_flatten2_reg_3675) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0))) then
tmp_640_reg_5592 <= tmp_640_fu_2852_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_lv1_0 = ap_reg_pp0_iter1_exitcond_flatten2_reg_3675) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0))) then
tmp_641_reg_5857 <= tmp_641_fu_2943_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_lv1_0 = ap_reg_pp0_iter1_exitcond_flatten2_reg_3675) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0))) then
tmp_642_reg_6117 <= tmp_642_fu_3045_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_flatten2_reg_3675 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0) and (ap_const_lv1_0 = tmp_9_mid1_reg_3744))) then
tmp_8_cast_mid5_reg_3797 <= tmp_8_cast_mid5_fu_1234_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_flatten2_reg_3675 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0) and (tmp_9_mid1_reg_3744 = ap_const_lv1_1))) then
tmp_8_mid1_reg_3857 <= tmp_8_mid1_fu_1329_p2;
end if;
end if;
end process;
tmp_1_mid2_cast_reg_3762(5 downto 3) <= "000";
tmp_4_mid2_cast_reg_3819(5 downto 3) <= "000";
tmp_4_mid2_cast4_reg_3841(6 downto 3) <= "0000";
tmp_2_cast2_reg_4083(7 downto 6) <= "00";
tmp_4_mid2_cast3_reg_4090(7 downto 3) <= "00000";
tmp_2_cast1_reg_4442(8 downto 6) <= "000";
tmp_4_mid2_cast1_reg_4452(8 downto 3) <= "000000";
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage14, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter9, exitcond_flatten2_fu_1051_p2, ap_enable_reg_pp0_iter8, ap_block_pp0_stage0_flag00011011, ap_block_pp0_stage15_flag00011011, ap_block_pp0_stage14_flag00011011, ap_block_pp0_stage1_flag00011011, ap_block_pp0_stage2_flag00011011, ap_block_pp0_stage3_flag00011011, ap_block_pp0_stage4_flag00011011, ap_block_pp0_stage5_flag00011011, ap_block_pp0_stage6_flag00011011, ap_block_pp0_stage7_flag00011011, ap_block_pp0_stage8_flag00011011, ap_block_pp0_stage9_flag00011011, ap_block_pp0_stage10_flag00011011, ap_block_pp0_stage11_flag00011011, ap_block_pp0_stage12_flag00011011, ap_block_pp0_stage13_flag00011011)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_pp0_stage0 =>
if (((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and not(((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (exitcond_flatten2_fu_1051_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0))))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (exitcond_flatten2_fu_1051_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_fsm_state161;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
end if;
when ap_ST_fsm_pp0_stage1 =>
if ((ap_block_pp0_stage1_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage2;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage1;
end if;
when ap_ST_fsm_pp0_stage2 =>
if ((ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage3;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage2;
end if;
when ap_ST_fsm_pp0_stage3 =>
if ((ap_block_pp0_stage3_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage4;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage3;
end if;
when ap_ST_fsm_pp0_stage4 =>
if ((ap_block_pp0_stage4_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage5;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage4;
end if;
when ap_ST_fsm_pp0_stage5 =>
if ((ap_block_pp0_stage5_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage6;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage5;
end if;
when ap_ST_fsm_pp0_stage6 =>
if ((ap_block_pp0_stage6_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage7;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage6;
end if;
when ap_ST_fsm_pp0_stage7 =>
if ((ap_block_pp0_stage7_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage8;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage7;
end if;
when ap_ST_fsm_pp0_stage8 =>
if ((ap_block_pp0_stage8_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage9;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage8;
end if;
when ap_ST_fsm_pp0_stage9 =>
if ((ap_block_pp0_stage9_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage10;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage9;
end if;
when ap_ST_fsm_pp0_stage10 =>
if ((ap_block_pp0_stage10_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage11;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage10;
end if;
when ap_ST_fsm_pp0_stage11 =>
if ((ap_block_pp0_stage11_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage12;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage11;
end if;
when ap_ST_fsm_pp0_stage12 =>
if ((ap_block_pp0_stage12_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage13;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage12;
end if;
when ap_ST_fsm_pp0_stage13 =>
if ((ap_block_pp0_stage13_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage14;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage13;
end if;
when ap_ST_fsm_pp0_stage14 =>
if (((ap_block_pp0_stage14_flag00011011 = ap_const_boolean_0) and not(((ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9) and (ap_block_pp0_stage14_flag00011011 = ap_const_boolean_0) and (ap_enable_reg_pp0_iter8 = ap_const_logic_0))))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage15;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9) and (ap_block_pp0_stage14_flag00011011 = ap_const_boolean_0) and (ap_enable_reg_pp0_iter8 = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_fsm_state161;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage14;
end if;
when ap_ST_fsm_pp0_stage15 =>
if ((ap_block_pp0_stage15_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage15;
end if;
when ap_ST_fsm_state161 =>
ap_NS_fsm <= ap_ST_fsm_state1;
when others =>
ap_NS_fsm <= "XXXXXXXXXXXXXXXXXX";
end case;
end process;
ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(1);
ap_CS_fsm_pp0_stage1 <= ap_CS_fsm(2);
ap_CS_fsm_pp0_stage10 <= ap_CS_fsm(11);
ap_CS_fsm_pp0_stage11 <= ap_CS_fsm(12);
ap_CS_fsm_pp0_stage12 <= ap_CS_fsm(13);
ap_CS_fsm_pp0_stage13 <= ap_CS_fsm(14);
ap_CS_fsm_pp0_stage14 <= ap_CS_fsm(15);
ap_CS_fsm_pp0_stage15 <= ap_CS_fsm(16);
ap_CS_fsm_pp0_stage2 <= ap_CS_fsm(3);
ap_CS_fsm_pp0_stage3 <= ap_CS_fsm(4);
ap_CS_fsm_pp0_stage4 <= ap_CS_fsm(5);
ap_CS_fsm_pp0_stage5 <= ap_CS_fsm(6);
ap_CS_fsm_pp0_stage6 <= ap_CS_fsm(7);
ap_CS_fsm_pp0_stage7 <= ap_CS_fsm(8);
ap_CS_fsm_pp0_stage8 <= ap_CS_fsm(9);
ap_CS_fsm_pp0_stage9 <= ap_CS_fsm(10);
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state161 <= ap_CS_fsm(17);
ap_block_pp0_stage0_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage0_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage0_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage10_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage10_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage10_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage11_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage11_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage11_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage12_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage12_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage12_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage13_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage13_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage13_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage14_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage14_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage14_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage15_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage15_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage15_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage1_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage1_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage1_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage2_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage2_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage2_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage3_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage3_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage3_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage4_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage4_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage4_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage5_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage5_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage5_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage6_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage6_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage6_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage7_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage7_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage7_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage8_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage8_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage8_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage9_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage9_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage9_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state100_pp0_stage2_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state101_pp0_stage3_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state102_pp0_stage4_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state103_pp0_stage5_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state104_pp0_stage6_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state105_pp0_stage7_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state106_pp0_stage8_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state107_pp0_stage9_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state108_pp0_stage10_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state109_pp0_stage11_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state10_pp0_stage8_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state110_pp0_stage12_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state111_pp0_stage13_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state112_pp0_stage14_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state113_pp0_stage15_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state114_pp0_stage0_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state115_pp0_stage1_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state116_pp0_stage2_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state117_pp0_stage3_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state118_pp0_stage4_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state119_pp0_stage5_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state11_pp0_stage9_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state120_pp0_stage6_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state121_pp0_stage7_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state122_pp0_stage8_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state123_pp0_stage9_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state124_pp0_stage10_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state125_pp0_stage11_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state126_pp0_stage12_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state127_pp0_stage13_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state128_pp0_stage14_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state129_pp0_stage15_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state12_pp0_stage10_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state130_pp0_stage0_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state131_pp0_stage1_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state132_pp0_stage2_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state133_pp0_stage3_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state134_pp0_stage4_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state135_pp0_stage5_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state136_pp0_stage6_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state137_pp0_stage7_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state138_pp0_stage8_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state139_pp0_stage9_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state13_pp0_stage11_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state140_pp0_stage10_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state141_pp0_stage11_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state142_pp0_stage12_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state143_pp0_stage13_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state144_pp0_stage14_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state145_pp0_stage15_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state146_pp0_stage0_iter9 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state147_pp0_stage1_iter9 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state148_pp0_stage2_iter9 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state149_pp0_stage3_iter9 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state14_pp0_stage12_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state150_pp0_stage4_iter9 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state151_pp0_stage5_iter9 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state152_pp0_stage6_iter9 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state153_pp0_stage7_iter9 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state154_pp0_stage8_iter9 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state155_pp0_stage9_iter9 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state156_pp0_stage10_iter9 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state157_pp0_stage11_iter9 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state158_pp0_stage12_iter9 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state159_pp0_stage13_iter9 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state15_pp0_stage13_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state160_pp0_stage14_iter9 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state16_pp0_stage14_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state17_pp0_stage15_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state18_pp0_stage0_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state19_pp0_stage1_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state20_pp0_stage2_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state21_pp0_stage3_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state22_pp0_stage4_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state23_pp0_stage5_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state24_pp0_stage6_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state25_pp0_stage7_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state26_pp0_stage8_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state27_pp0_stage9_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state28_pp0_stage10_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state29_pp0_stage11_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state2_pp0_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state30_pp0_stage12_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state31_pp0_stage13_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state32_pp0_stage14_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state33_pp0_stage15_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state34_pp0_stage0_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state35_pp0_stage1_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state36_pp0_stage2_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state37_pp0_stage3_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state38_pp0_stage4_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state39_pp0_stage5_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state3_pp0_stage1_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state40_pp0_stage6_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state41_pp0_stage7_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state42_pp0_stage8_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state43_pp0_stage9_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state44_pp0_stage10_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state45_pp0_stage11_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state46_pp0_stage12_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state47_pp0_stage13_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state48_pp0_stage14_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state49_pp0_stage15_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state4_pp0_stage2_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state50_pp0_stage0_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state51_pp0_stage1_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state52_pp0_stage2_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state53_pp0_stage3_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state54_pp0_stage4_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state55_pp0_stage5_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state56_pp0_stage6_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state57_pp0_stage7_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state58_pp0_stage8_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state59_pp0_stage9_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state5_pp0_stage3_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state60_pp0_stage10_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state61_pp0_stage11_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state62_pp0_stage12_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state63_pp0_stage13_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state64_pp0_stage14_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state65_pp0_stage15_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state66_pp0_stage0_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state67_pp0_stage1_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state68_pp0_stage2_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state69_pp0_stage3_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state6_pp0_stage4_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state70_pp0_stage4_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state71_pp0_stage5_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state72_pp0_stage6_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state73_pp0_stage7_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state74_pp0_stage8_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state75_pp0_stage9_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state76_pp0_stage10_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state77_pp0_stage11_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state78_pp0_stage12_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state79_pp0_stage13_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state7_pp0_stage5_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state80_pp0_stage14_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state81_pp0_stage15_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state82_pp0_stage0_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state83_pp0_stage1_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state84_pp0_stage2_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state85_pp0_stage3_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state86_pp0_stage4_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state87_pp0_stage5_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state88_pp0_stage6_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state89_pp0_stage7_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state8_pp0_stage6_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state90_pp0_stage8_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state91_pp0_stage9_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state92_pp0_stage10_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state93_pp0_stage11_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state94_pp0_stage12_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state95_pp0_stage13_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state96_pp0_stage14_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state97_pp0_stage15_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state98_pp0_stage0_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state99_pp0_stage1_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state9_pp0_stage7_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_condition_pp0_exit_iter0_state2_assign_proc : process(exitcond_flatten2_fu_1051_p2)
begin
if ((exitcond_flatten2_fu_1051_p2 = ap_const_lv1_1)) then
ap_condition_pp0_exit_iter0_state2 <= ap_const_logic_1;
else
ap_condition_pp0_exit_iter0_state2 <= ap_const_logic_0;
end if;
end process;
ap_done_assign_proc : process(ap_CS_fsm_state161)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state161)) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter9, ap_enable_reg_pp0_iter2, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_enable_reg_pp0_iter7, ap_enable_reg_pp0_iter8)
begin
if (((ap_const_logic_0 = ap_enable_reg_pp0_iter0) and (ap_const_logic_0 = ap_enable_reg_pp0_iter1) and (ap_const_logic_0 = ap_enable_reg_pp0_iter2) and (ap_const_logic_0 = ap_enable_reg_pp0_iter3) and (ap_const_logic_0 = ap_enable_reg_pp0_iter4) and (ap_const_logic_0 = ap_enable_reg_pp0_iter5) and (ap_const_logic_0 = ap_enable_reg_pp0_iter6) and (ap_const_logic_0 = ap_enable_reg_pp0_iter7) and (ap_const_logic_0 = ap_enable_reg_pp0_iter8) and (ap_const_logic_0 = ap_enable_reg_pp0_iter9))) then
ap_idle_pp0 <= ap_const_logic_1;
else
ap_idle_pp0 <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(ap_CS_fsm_state161)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state161)) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
bufi_Addr_A <= std_logic_vector(shift_left(unsigned(bufi_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_6(31-1 downto 0)))));
bufi_Addr_A_orig <= tmp_649_cast_fu_1635_p1(32 - 1 downto 0);
bufi_Clk_A <= ap_clk;
bufi_Din_A <= ap_const_lv512_lc_1;
bufi_EN_A_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_flag00011001)
begin
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0))) then
bufi_EN_A <= ap_const_logic_1;
else
bufi_EN_A <= ap_const_logic_0;
end if;
end process;
bufi_Rst_A <= ap_rst_n_inv;
bufi_WEN_A <= ap_const_lv64_0;
bufo_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_6(31-1 downto 0)))));
bufo_Addr_A_orig_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage14, ap_enable_reg_pp0_iter9, bufo_addr_reg_3867, ap_reg_pp0_iter9_bufo_addr_reg_3867, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage14_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
bufo_Addr_A_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(ap_reg_pp0_iter9_bufo_addr_reg_3867),32));
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
bufo_Addr_A_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(bufo_addr_reg_3867),32));
else
bufo_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufo_Clk_A <= ap_clk;
bufo_Din_A <= (((((((((((((((tmp_605_fu_3629_p1 & tmp_570_fu_3625_p1) & tmp_535_fu_3621_p1) & tmp_500_fu_3617_p1) & tmp_465_fu_3613_p1) & tmp_430_fu_3609_p1) & tmp_395_fu_3605_p1) & tmp_360_fu_3601_p1) & tmp_325_fu_3597_p1) & tmp_290_fu_3593_p1) & tmp_255_fu_3589_p1) & tmp_220_fu_3585_p1) & tmp_185_fu_3581_p1) & tmp_150_fu_3577_p1) & tmp_114_fu_3573_p1) & tmp_79_fu_3569_p1);
bufo_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_block_pp0_stage5_flag00011001, ap_CS_fsm_pp0_stage14, ap_block_pp0_stage14_flag00011001, ap_enable_reg_pp0_iter9)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9)))) then
bufo_EN_A <= ap_const_logic_1;
else
bufo_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_Rst_A <= ap_rst_n_inv;
bufo_WEN_A_assign_proc : process(ap_CS_fsm_pp0_stage14, ap_block_pp0_stage14_flag00011001, ap_enable_reg_pp0_iter9, ap_reg_pp0_iter9_exitcond_flatten2_reg_3675)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9) and (ap_const_lv1_0 = ap_reg_pp0_iter9_exitcond_flatten2_reg_3675))) then
bufo_WEN_A <= ap_const_lv64_FFFFFFFFFFFFFFFF;
else
bufo_WEN_A <= ap_const_lv64_0;
end if;
end process;
bufw_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_6(31-1 downto 0)))));
bufw_Addr_A_orig_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, tmp_629_cast_fu_1278_p1, ap_block_pp0_stage3_flag00000000, tmp_621_cast_fu_1293_p1, ap_block_pp0_stage4_flag00000000, tmp_622_cast_fu_1391_p1, ap_block_pp0_stage5_flag00000000, tmp_623_cast_fu_1414_p1, ap_block_pp0_stage6_flag00000000, tmp_624_cast_fu_1625_p1, ap_block_pp0_stage7_flag00000000, tmp_625_cast_fu_1648_p1, ap_block_pp0_stage8_flag00000000, tmp_626_cast_fu_1825_p1, ap_block_pp0_stage9_flag00000000, tmp_627_cast_fu_1941_p1, ap_block_pp0_stage10_flag00000000, tmp_628_cast_fu_2059_p1, ap_block_pp0_stage11_flag00000000, tmp_630_cast_fu_2176_p1, ap_block_pp0_stage12_flag00000000, tmp_631_cast_fu_2292_p1, ap_block_pp0_stage13_flag00000000, tmp_632_cast_fu_2408_p1, ap_block_pp0_stage14_flag00000000, tmp_633_cast_fu_2588_p1, ap_block_pp0_stage15_flag00000000, tmp_634_cast_fu_2709_p1, tmp_635_cast_fu_2825_p1, tmp_636_cast_fu_2916_p1, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
bufw_Addr_A_orig <= tmp_636_cast_fu_2916_p1(32 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
bufw_Addr_A_orig <= tmp_635_cast_fu_2825_p1(32 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
bufw_Addr_A_orig <= tmp_634_cast_fu_2709_p1(32 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
bufw_Addr_A_orig <= tmp_633_cast_fu_2588_p1(32 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
bufw_Addr_A_orig <= tmp_632_cast_fu_2408_p1(32 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
bufw_Addr_A_orig <= tmp_631_cast_fu_2292_p1(32 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
bufw_Addr_A_orig <= tmp_630_cast_fu_2176_p1(32 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
bufw_Addr_A_orig <= tmp_628_cast_fu_2059_p1(32 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
bufw_Addr_A_orig <= tmp_627_cast_fu_1941_p1(32 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
bufw_Addr_A_orig <= tmp_626_cast_fu_1825_p1(32 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
bufw_Addr_A_orig <= tmp_625_cast_fu_1648_p1(32 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
bufw_Addr_A_orig <= tmp_624_cast_fu_1625_p1(32 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
bufw_Addr_A_orig <= tmp_623_cast_fu_1414_p1(32 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
bufw_Addr_A_orig <= tmp_622_cast_fu_1391_p1(32 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
bufw_Addr_A_orig <= tmp_621_cast_fu_1293_p1(32 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
bufw_Addr_A_orig <= tmp_629_cast_fu_1278_p1(32 - 1 downto 0);
else
bufw_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufw_Clk_A <= ap_clk;
bufw_Din_A <= ap_const_lv512_lc_1;
bufw_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_block_pp0_stage5_flag00011001, ap_CS_fsm_pp0_stage9, ap_block_pp0_stage9_flag00011001, ap_CS_fsm_pp0_stage13, ap_block_pp0_stage13_flag00011001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_flag00011001, ap_CS_fsm_pp0_stage10, ap_block_pp0_stage10_flag00011001, ap_CS_fsm_pp0_stage14, ap_block_pp0_stage14_flag00011001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_flag00011001, ap_CS_fsm_pp0_stage11, ap_block_pp0_stage11_flag00011001, ap_CS_fsm_pp0_stage15, ap_block_pp0_stage15_flag00011001, ap_CS_fsm_pp0_stage8, ap_block_pp0_stage8_flag00011001, ap_CS_fsm_pp0_stage12, ap_block_pp0_stage12_flag00011001, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_flag00011001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00011001, ap_CS_fsm_pp0_stage3, ap_block_pp0_stage3_flag00011001, ap_CS_fsm_pp0_stage4, ap_block_pp0_stage4_flag00011001)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0)))) then
bufw_EN_A <= ap_const_logic_1;
else
bufw_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_Rst_A <= ap_rst_n_inv;
bufw_WEN_A <= ap_const_lv64_0;
col_b_1_fu_1371_p2 <= std_logic_vector(unsigned(ap_const_lv5_1) + unsigned(col_b_mid2_reg_3802));
col_b_cast1_cast_fu_1339_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(col_b_mid2_reg_3802),10));
col_b_mid2_fu_1250_p3 <=
ap_const_lv5_0 when (tmp_616_fu_1245_p2(0) = '1') else
col_b_reg_421;
col_b_phi_fu_425_p4_assign_proc : process(col_b_reg_421, exitcond_flatten2_reg_3675, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, col_b_1_reg_3957, ap_block_pp0_stage0_flag00000000)
begin
if (((exitcond_flatten2_reg_3675 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
col_b_phi_fu_425_p4 <= col_b_1_reg_3957;
else
col_b_phi_fu_425_p4 <= col_b_reg_421;
end if;
end process;
exitcond_flatten1_fu_1075_p2 <= "1" when (indvar_flatten_phi_fu_401_p4 = ap_const_lv10_100) else "0";
exitcond_flatten2_fu_1051_p2 <= "1" when (indvar_flatten1_phi_fu_355_p4 = ap_const_lv13_1900) else "0";
exitcond_flatten_fu_1063_p2 <= "1" when (indvar_flatten2_phi_fu_378_p4 = ap_const_lv12_500) else "0";
exitcond_flatten_mid_fu_1117_p2 <= (exitcond_flatten1_reg_3701 and not_exitcond_flatten_fu_1107_p2);
exitcond_flatten_not_fu_1128_p2 <= (exitcond_flatten1_reg_3701 xor ap_const_lv1_1);
grp_fu_433_p0_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, reg_951, ap_enable_reg_pp0_iter9, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, tmp_18_fu_2417_p1, tmp_607_reg_6707, tmp_12_0_2_reg_7647, ap_enable_reg_pp0_iter2, tmp_12_0_3_reg_7727, ap_enable_reg_pp0_iter3, tmp_12_0_4_reg_7807, tmp_12_0_5_reg_7887, ap_enable_reg_pp0_iter4, tmp_12_0_6_reg_7967, tmp_12_0_7_reg_8047, ap_enable_reg_pp0_iter5, tmp_12_0_8_reg_8127, tmp_12_0_9_reg_8207, ap_enable_reg_pp0_iter6, tmp_12_0_s_reg_8287, ap_enable_reg_pp0_iter7, tmp_12_0_10_reg_8367, tmp_12_0_11_reg_8447, ap_enable_reg_pp0_iter8, tmp_12_0_12_reg_8527, tmp_12_0_13_reg_8607, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_433_p0 <= tmp_12_0_13_reg_8607;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_433_p0 <= tmp_12_0_12_reg_8527;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_433_p0 <= tmp_12_0_11_reg_8447;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_433_p0 <= tmp_12_0_10_reg_8367;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_433_p0 <= tmp_12_0_s_reg_8287;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_433_p0 <= tmp_12_0_9_reg_8207;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_433_p0 <= tmp_12_0_8_reg_8127;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_433_p0 <= tmp_12_0_7_reg_8047;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_433_p0 <= tmp_12_0_6_reg_7967;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_433_p0 <= tmp_12_0_5_reg_7887;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_433_p0 <= tmp_12_0_4_reg_7807;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_433_p0 <= tmp_12_0_3_reg_7727;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_433_p0 <= tmp_12_0_2_reg_7647;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_433_p0 <= reg_951;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_433_p0 <= tmp_607_reg_6707;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_433_p0 <= tmp_18_fu_2417_p1;
else
grp_fu_433_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_433_p1_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter9, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, tmp_116_reg_4702, tmp_11_0_1_reg_4902, ap_reg_pp0_iter1_tmp_11_0_2_reg_5172, ap_reg_pp0_iter2_tmp_11_0_3_reg_5372, ap_reg_pp0_iter3_tmp_11_0_4_reg_5562, ap_reg_pp0_iter3_tmp_11_0_5_reg_5827, ap_reg_pp0_iter4_tmp_11_0_6_reg_6087, ap_reg_pp0_iter4_tmp_11_0_7_reg_6347, ap_reg_pp0_iter5_tmp_11_0_8_reg_6527, ap_reg_pp0_iter5_tmp_11_0_9_reg_6712, ap_reg_pp0_iter6_tmp_11_0_s_reg_6967, ap_reg_pp0_iter6_tmp_11_0_10_reg_7147, ap_reg_pp0_iter7_tmp_11_0_11_reg_7327, ap_reg_pp0_iter7_tmp_11_0_12_reg_7407, ap_reg_pp0_iter8_tmp_11_0_13_reg_7487, ap_reg_pp0_iter8_tmp_11_0_14_reg_7567, ap_enable_reg_pp0_iter2, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_enable_reg_pp0_iter7, ap_enable_reg_pp0_iter8, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_433_p1 <= ap_reg_pp0_iter8_tmp_11_0_14_reg_7567;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_433_p1 <= ap_reg_pp0_iter8_tmp_11_0_13_reg_7487;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_433_p1 <= ap_reg_pp0_iter7_tmp_11_0_12_reg_7407;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_433_p1 <= ap_reg_pp0_iter7_tmp_11_0_11_reg_7327;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_433_p1 <= ap_reg_pp0_iter6_tmp_11_0_10_reg_7147;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_433_p1 <= ap_reg_pp0_iter6_tmp_11_0_s_reg_6967;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_433_p1 <= ap_reg_pp0_iter5_tmp_11_0_9_reg_6712;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_433_p1 <= ap_reg_pp0_iter5_tmp_11_0_8_reg_6527;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_433_p1 <= ap_reg_pp0_iter4_tmp_11_0_7_reg_6347;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_433_p1 <= ap_reg_pp0_iter4_tmp_11_0_6_reg_6087;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_433_p1 <= ap_reg_pp0_iter3_tmp_11_0_5_reg_5827;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_433_p1 <= ap_reg_pp0_iter3_tmp_11_0_4_reg_5562;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_433_p1 <= ap_reg_pp0_iter2_tmp_11_0_3_reg_5372;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_433_p1 <= ap_reg_pp0_iter1_tmp_11_0_2_reg_5172;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_433_p1 <= tmp_11_0_1_reg_4902;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_433_p1 <= tmp_116_reg_4702;
else
grp_fu_433_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_437_p0_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter9, reg_956, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, tmp_83_fu_2448_p1, tmp_12_1_reg_6742, ap_enable_reg_pp0_iter2, tmp_12_1_2_reg_7652, ap_enable_reg_pp0_iter3, tmp_12_1_3_reg_7732, tmp_12_1_4_reg_7812, ap_enable_reg_pp0_iter4, tmp_12_1_5_reg_7892, tmp_12_1_6_reg_7972, ap_enable_reg_pp0_iter5, tmp_12_1_7_reg_8052, tmp_12_1_8_reg_8132, ap_enable_reg_pp0_iter6, tmp_12_1_9_reg_8212, ap_enable_reg_pp0_iter7, tmp_12_1_s_reg_8292, tmp_12_1_10_reg_8372, ap_enable_reg_pp0_iter8, tmp_12_1_11_reg_8452, tmp_12_1_12_reg_8532, tmp_12_1_13_reg_8612, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_437_p0 <= tmp_12_1_13_reg_8612;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_437_p0 <= tmp_12_1_12_reg_8532;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_437_p0 <= tmp_12_1_11_reg_8452;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_437_p0 <= tmp_12_1_10_reg_8372;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_437_p0 <= tmp_12_1_s_reg_8292;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_437_p0 <= tmp_12_1_9_reg_8212;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_437_p0 <= tmp_12_1_8_reg_8132;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_437_p0 <= tmp_12_1_7_reg_8052;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_437_p0 <= tmp_12_1_6_reg_7972;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_437_p0 <= tmp_12_1_5_reg_7892;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_437_p0 <= tmp_12_1_4_reg_7812;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_437_p0 <= tmp_12_1_3_reg_7732;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_437_p0 <= tmp_12_1_2_reg_7652;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_437_p0 <= reg_956;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_437_p0 <= tmp_12_1_reg_6742;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_437_p0 <= tmp_83_fu_2448_p1;
else
grp_fu_437_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_437_p1_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter9, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, tmp_11_1_reg_4737, tmp_11_1_1_reg_4942, ap_reg_pp0_iter1_tmp_11_1_2_reg_5207, ap_reg_pp0_iter2_tmp_11_1_3_reg_5407, ap_reg_pp0_iter3_tmp_11_1_4_reg_5597, ap_reg_pp0_iter3_tmp_11_1_5_reg_5862, ap_reg_pp0_iter4_tmp_11_1_6_reg_6122, ap_reg_pp0_iter4_tmp_11_1_7_reg_6377, ap_reg_pp0_iter5_tmp_11_1_8_reg_6557, ap_reg_pp0_iter5_tmp_11_1_9_reg_6747, ap_reg_pp0_iter6_tmp_11_1_s_reg_6997, ap_reg_pp0_iter6_tmp_11_1_10_reg_7177, ap_reg_pp0_iter7_tmp_11_1_11_reg_7332, ap_reg_pp0_iter7_tmp_11_1_12_reg_7412, ap_reg_pp0_iter8_tmp_11_1_13_reg_7492, ap_reg_pp0_iter8_tmp_11_1_14_reg_7572, ap_enable_reg_pp0_iter2, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_enable_reg_pp0_iter7, ap_enable_reg_pp0_iter8, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_437_p1 <= ap_reg_pp0_iter8_tmp_11_1_14_reg_7572;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_437_p1 <= ap_reg_pp0_iter8_tmp_11_1_13_reg_7492;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_437_p1 <= ap_reg_pp0_iter7_tmp_11_1_12_reg_7412;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_437_p1 <= ap_reg_pp0_iter7_tmp_11_1_11_reg_7332;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_437_p1 <= ap_reg_pp0_iter6_tmp_11_1_10_reg_7177;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_437_p1 <= ap_reg_pp0_iter6_tmp_11_1_s_reg_6997;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_437_p1 <= ap_reg_pp0_iter5_tmp_11_1_9_reg_6747;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_437_p1 <= ap_reg_pp0_iter5_tmp_11_1_8_reg_6557;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_437_p1 <= ap_reg_pp0_iter4_tmp_11_1_7_reg_6377;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_437_p1 <= ap_reg_pp0_iter4_tmp_11_1_6_reg_6122;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_437_p1 <= ap_reg_pp0_iter3_tmp_11_1_5_reg_5862;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_437_p1 <= ap_reg_pp0_iter3_tmp_11_1_4_reg_5597;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_437_p1 <= ap_reg_pp0_iter2_tmp_11_1_3_reg_5407;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_437_p1 <= ap_reg_pp0_iter1_tmp_11_1_2_reg_5207;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_437_p1 <= tmp_11_1_1_reg_4942;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_437_p1 <= tmp_11_1_reg_4737;
else
grp_fu_437_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_441_p0_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter9, reg_961, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, tmp_119_fu_2457_p1, tmp_12_2_reg_6757, ap_enable_reg_pp0_iter2, tmp_12_2_2_reg_7657, ap_enable_reg_pp0_iter3, tmp_12_2_3_reg_7737, tmp_12_2_4_reg_7817, ap_enable_reg_pp0_iter4, tmp_12_2_5_reg_7897, tmp_12_2_6_reg_7977, ap_enable_reg_pp0_iter5, tmp_12_2_7_reg_8057, tmp_12_2_8_reg_8137, ap_enable_reg_pp0_iter6, tmp_12_2_9_reg_8217, ap_enable_reg_pp0_iter7, tmp_12_2_s_reg_8297, tmp_12_2_10_reg_8377, ap_enable_reg_pp0_iter8, tmp_12_2_11_reg_8457, tmp_12_2_12_reg_8537, tmp_12_2_13_reg_8617, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_441_p0 <= tmp_12_2_13_reg_8617;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_441_p0 <= tmp_12_2_12_reg_8537;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_441_p0 <= tmp_12_2_11_reg_8457;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_441_p0 <= tmp_12_2_10_reg_8377;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_441_p0 <= tmp_12_2_s_reg_8297;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_441_p0 <= tmp_12_2_9_reg_8217;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_441_p0 <= tmp_12_2_8_reg_8137;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_441_p0 <= tmp_12_2_7_reg_8057;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_441_p0 <= tmp_12_2_6_reg_7977;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_441_p0 <= tmp_12_2_5_reg_7897;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_441_p0 <= tmp_12_2_4_reg_7817;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_441_p0 <= tmp_12_2_3_reg_7737;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_441_p0 <= tmp_12_2_2_reg_7657;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_441_p0 <= reg_961;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_441_p0 <= tmp_12_2_reg_6757;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_441_p0 <= tmp_119_fu_2457_p1;
else
grp_fu_441_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_441_p1_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter9, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, tmp_11_2_reg_4747, tmp_11_2_1_reg_4957, ap_reg_pp0_iter1_tmp_11_2_2_reg_5217, ap_reg_pp0_iter2_tmp_11_2_3_reg_5417, ap_reg_pp0_iter3_tmp_11_2_4_reg_5612, ap_reg_pp0_iter3_tmp_11_2_5_reg_5877, ap_reg_pp0_iter4_tmp_11_2_6_reg_6137, ap_reg_pp0_iter4_tmp_11_2_7_reg_6387, ap_reg_pp0_iter5_tmp_11_2_8_reg_6567, ap_reg_pp0_iter5_tmp_11_2_9_reg_6762, ap_reg_pp0_iter6_tmp_11_2_s_reg_7007, ap_reg_pp0_iter6_tmp_11_2_10_reg_7187, ap_reg_pp0_iter7_tmp_11_2_11_reg_7337, ap_reg_pp0_iter7_tmp_11_2_12_reg_7417, ap_reg_pp0_iter8_tmp_11_2_13_reg_7497, ap_reg_pp0_iter8_tmp_11_2_14_reg_7577, ap_enable_reg_pp0_iter2, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_enable_reg_pp0_iter7, ap_enable_reg_pp0_iter8, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_441_p1 <= ap_reg_pp0_iter8_tmp_11_2_14_reg_7577;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_441_p1 <= ap_reg_pp0_iter8_tmp_11_2_13_reg_7497;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_441_p1 <= ap_reg_pp0_iter7_tmp_11_2_12_reg_7417;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_441_p1 <= ap_reg_pp0_iter7_tmp_11_2_11_reg_7337;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_441_p1 <= ap_reg_pp0_iter6_tmp_11_2_10_reg_7187;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_441_p1 <= ap_reg_pp0_iter6_tmp_11_2_s_reg_7007;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_441_p1 <= ap_reg_pp0_iter5_tmp_11_2_9_reg_6762;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_441_p1 <= ap_reg_pp0_iter5_tmp_11_2_8_reg_6567;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_441_p1 <= ap_reg_pp0_iter4_tmp_11_2_7_reg_6387;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_441_p1 <= ap_reg_pp0_iter4_tmp_11_2_6_reg_6137;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_441_p1 <= ap_reg_pp0_iter3_tmp_11_2_5_reg_5877;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_441_p1 <= ap_reg_pp0_iter3_tmp_11_2_4_reg_5612;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_441_p1 <= ap_reg_pp0_iter2_tmp_11_2_3_reg_5417;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_441_p1 <= ap_reg_pp0_iter1_tmp_11_2_2_reg_5217;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_441_p1 <= tmp_11_2_1_reg_4957;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_441_p1 <= tmp_11_2_reg_4747;
else
grp_fu_441_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_445_p0_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter9, reg_966, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, tmp_154_fu_2466_p1, tmp_12_3_reg_6772, ap_enable_reg_pp0_iter2, tmp_12_3_2_reg_7662, ap_enable_reg_pp0_iter3, tmp_12_3_3_reg_7742, tmp_12_3_4_reg_7822, ap_enable_reg_pp0_iter4, tmp_12_3_5_reg_7902, tmp_12_3_6_reg_7982, ap_enable_reg_pp0_iter5, tmp_12_3_7_reg_8062, tmp_12_3_8_reg_8142, ap_enable_reg_pp0_iter6, tmp_12_3_9_reg_8222, ap_enable_reg_pp0_iter7, tmp_12_3_s_reg_8302, tmp_12_3_10_reg_8382, ap_enable_reg_pp0_iter8, tmp_12_3_11_reg_8462, tmp_12_3_12_reg_8542, tmp_12_3_13_reg_8622, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_445_p0 <= tmp_12_3_13_reg_8622;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_445_p0 <= tmp_12_3_12_reg_8542;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_445_p0 <= tmp_12_3_11_reg_8462;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_445_p0 <= tmp_12_3_10_reg_8382;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_445_p0 <= tmp_12_3_s_reg_8302;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_445_p0 <= tmp_12_3_9_reg_8222;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_445_p0 <= tmp_12_3_8_reg_8142;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_445_p0 <= tmp_12_3_7_reg_8062;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_445_p0 <= tmp_12_3_6_reg_7982;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_445_p0 <= tmp_12_3_5_reg_7902;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_445_p0 <= tmp_12_3_4_reg_7822;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_445_p0 <= tmp_12_3_3_reg_7742;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_445_p0 <= tmp_12_3_2_reg_7662;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_445_p0 <= reg_966;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_445_p0 <= tmp_12_3_reg_6772;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_445_p0 <= tmp_154_fu_2466_p1;
else
grp_fu_445_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_445_p1_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter9, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, tmp_11_3_reg_4757, tmp_11_3_1_reg_4972, ap_reg_pp0_iter1_tmp_11_3_2_reg_5227, ap_reg_pp0_iter2_tmp_11_3_3_reg_5427, ap_reg_pp0_iter3_tmp_11_3_4_reg_5627, ap_reg_pp0_iter3_tmp_11_3_5_reg_5892, ap_reg_pp0_iter4_tmp_11_3_6_reg_6152, ap_reg_pp0_iter4_tmp_11_3_7_reg_6397, ap_reg_pp0_iter5_tmp_11_3_8_reg_6577, ap_reg_pp0_iter5_tmp_11_3_9_reg_6777, ap_reg_pp0_iter6_tmp_11_3_s_reg_7017, ap_reg_pp0_iter6_tmp_11_3_10_reg_7197, ap_reg_pp0_iter7_tmp_11_3_11_reg_7342, ap_reg_pp0_iter7_tmp_11_3_12_reg_7422, ap_reg_pp0_iter8_tmp_11_3_13_reg_7502, ap_reg_pp0_iter8_tmp_11_3_14_reg_7582, ap_enable_reg_pp0_iter2, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_enable_reg_pp0_iter7, ap_enable_reg_pp0_iter8, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_445_p1 <= ap_reg_pp0_iter8_tmp_11_3_14_reg_7582;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_445_p1 <= ap_reg_pp0_iter8_tmp_11_3_13_reg_7502;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_445_p1 <= ap_reg_pp0_iter7_tmp_11_3_12_reg_7422;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_445_p1 <= ap_reg_pp0_iter7_tmp_11_3_11_reg_7342;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_445_p1 <= ap_reg_pp0_iter6_tmp_11_3_10_reg_7197;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_445_p1 <= ap_reg_pp0_iter6_tmp_11_3_s_reg_7017;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_445_p1 <= ap_reg_pp0_iter5_tmp_11_3_9_reg_6777;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_445_p1 <= ap_reg_pp0_iter5_tmp_11_3_8_reg_6577;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_445_p1 <= ap_reg_pp0_iter4_tmp_11_3_7_reg_6397;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_445_p1 <= ap_reg_pp0_iter4_tmp_11_3_6_reg_6152;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_445_p1 <= ap_reg_pp0_iter3_tmp_11_3_5_reg_5892;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_445_p1 <= ap_reg_pp0_iter3_tmp_11_3_4_reg_5627;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_445_p1 <= ap_reg_pp0_iter2_tmp_11_3_3_reg_5427;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_445_p1 <= ap_reg_pp0_iter1_tmp_11_3_2_reg_5227;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_445_p1 <= tmp_11_3_1_reg_4972;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_445_p1 <= tmp_11_3_reg_4757;
else
grp_fu_445_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_449_p0_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter9, reg_971, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, tmp_189_fu_2475_p1, tmp_12_4_reg_6787, ap_enable_reg_pp0_iter2, tmp_12_4_2_reg_7667, ap_enable_reg_pp0_iter3, tmp_12_4_3_reg_7747, tmp_12_4_4_reg_7827, ap_enable_reg_pp0_iter4, tmp_12_4_5_reg_7907, tmp_12_4_6_reg_7987, ap_enable_reg_pp0_iter5, tmp_12_4_7_reg_8067, tmp_12_4_8_reg_8147, ap_enable_reg_pp0_iter6, tmp_12_4_9_reg_8227, ap_enable_reg_pp0_iter7, tmp_12_4_s_reg_8307, tmp_12_4_10_reg_8387, ap_enable_reg_pp0_iter8, tmp_12_4_11_reg_8467, tmp_12_4_12_reg_8547, tmp_12_4_13_reg_8627, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_449_p0 <= tmp_12_4_13_reg_8627;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_449_p0 <= tmp_12_4_12_reg_8547;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_449_p0 <= tmp_12_4_11_reg_8467;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_449_p0 <= tmp_12_4_10_reg_8387;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_449_p0 <= tmp_12_4_s_reg_8307;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_449_p0 <= tmp_12_4_9_reg_8227;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_449_p0 <= tmp_12_4_8_reg_8147;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_449_p0 <= tmp_12_4_7_reg_8067;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_449_p0 <= tmp_12_4_6_reg_7987;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_449_p0 <= tmp_12_4_5_reg_7907;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_449_p0 <= tmp_12_4_4_reg_7827;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_449_p0 <= tmp_12_4_3_reg_7747;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_449_p0 <= tmp_12_4_2_reg_7667;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_449_p0 <= reg_971;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_449_p0 <= tmp_12_4_reg_6787;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_449_p0 <= tmp_189_fu_2475_p1;
else
grp_fu_449_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_449_p1_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter9, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, tmp_11_4_reg_4767, tmp_11_4_1_reg_4987, ap_reg_pp0_iter1_tmp_11_4_2_reg_5237, ap_reg_pp0_iter2_tmp_11_4_3_reg_5437, ap_reg_pp0_iter3_tmp_11_4_4_reg_5642, ap_reg_pp0_iter3_tmp_11_4_5_reg_5907, ap_reg_pp0_iter4_tmp_11_4_6_reg_6167, ap_reg_pp0_iter4_tmp_11_4_7_reg_6407, ap_reg_pp0_iter5_tmp_11_4_8_reg_6587, ap_reg_pp0_iter5_tmp_11_4_9_reg_6792, ap_reg_pp0_iter6_tmp_11_4_s_reg_7027, ap_reg_pp0_iter6_tmp_11_4_10_reg_7207, ap_reg_pp0_iter7_tmp_11_4_11_reg_7347, ap_reg_pp0_iter7_tmp_11_4_12_reg_7427, ap_reg_pp0_iter8_tmp_11_4_13_reg_7507, ap_reg_pp0_iter8_tmp_11_4_14_reg_7587, ap_enable_reg_pp0_iter2, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_enable_reg_pp0_iter7, ap_enable_reg_pp0_iter8, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_449_p1 <= ap_reg_pp0_iter8_tmp_11_4_14_reg_7587;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_449_p1 <= ap_reg_pp0_iter8_tmp_11_4_13_reg_7507;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_449_p1 <= ap_reg_pp0_iter7_tmp_11_4_12_reg_7427;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_449_p1 <= ap_reg_pp0_iter7_tmp_11_4_11_reg_7347;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_449_p1 <= ap_reg_pp0_iter6_tmp_11_4_10_reg_7207;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_449_p1 <= ap_reg_pp0_iter6_tmp_11_4_s_reg_7027;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_449_p1 <= ap_reg_pp0_iter5_tmp_11_4_9_reg_6792;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_449_p1 <= ap_reg_pp0_iter5_tmp_11_4_8_reg_6587;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_449_p1 <= ap_reg_pp0_iter4_tmp_11_4_7_reg_6407;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_449_p1 <= ap_reg_pp0_iter4_tmp_11_4_6_reg_6167;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_449_p1 <= ap_reg_pp0_iter3_tmp_11_4_5_reg_5907;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_449_p1 <= ap_reg_pp0_iter3_tmp_11_4_4_reg_5642;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_449_p1 <= ap_reg_pp0_iter2_tmp_11_4_3_reg_5437;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_449_p1 <= ap_reg_pp0_iter1_tmp_11_4_2_reg_5237;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_449_p1 <= tmp_11_4_1_reg_4987;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_449_p1 <= tmp_11_4_reg_4767;
else
grp_fu_449_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_453_p0_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter9, reg_976, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, tmp_224_fu_2484_p1, tmp_12_5_reg_6802, ap_enable_reg_pp0_iter2, tmp_12_5_2_reg_7672, ap_enable_reg_pp0_iter3, tmp_12_5_3_reg_7752, tmp_12_5_4_reg_7832, ap_enable_reg_pp0_iter4, tmp_12_5_5_reg_7912, tmp_12_5_6_reg_7992, ap_enable_reg_pp0_iter5, tmp_12_5_7_reg_8072, tmp_12_5_8_reg_8152, ap_enable_reg_pp0_iter6, tmp_12_5_9_reg_8232, ap_enable_reg_pp0_iter7, tmp_12_5_s_reg_8312, tmp_12_5_10_reg_8392, ap_enable_reg_pp0_iter8, tmp_12_5_11_reg_8472, tmp_12_5_12_reg_8552, tmp_12_5_13_reg_8632, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_453_p0 <= tmp_12_5_13_reg_8632;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_453_p0 <= tmp_12_5_12_reg_8552;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_453_p0 <= tmp_12_5_11_reg_8472;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_453_p0 <= tmp_12_5_10_reg_8392;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_453_p0 <= tmp_12_5_s_reg_8312;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_453_p0 <= tmp_12_5_9_reg_8232;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_453_p0 <= tmp_12_5_8_reg_8152;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_453_p0 <= tmp_12_5_7_reg_8072;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_453_p0 <= tmp_12_5_6_reg_7992;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_453_p0 <= tmp_12_5_5_reg_7912;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_453_p0 <= tmp_12_5_4_reg_7832;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_453_p0 <= tmp_12_5_3_reg_7752;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_453_p0 <= tmp_12_5_2_reg_7672;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_453_p0 <= reg_976;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_453_p0 <= tmp_12_5_reg_6802;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_453_p0 <= tmp_224_fu_2484_p1;
else
grp_fu_453_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_453_p1_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter9, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, tmp_11_5_reg_4777, tmp_11_5_1_reg_5002, ap_reg_pp0_iter1_tmp_11_5_2_reg_5247, ap_reg_pp0_iter2_tmp_11_5_3_reg_5447, ap_reg_pp0_iter3_tmp_11_5_4_reg_5657, ap_reg_pp0_iter3_tmp_11_5_5_reg_5922, ap_reg_pp0_iter4_tmp_11_5_6_reg_6182, ap_reg_pp0_iter4_tmp_11_5_7_reg_6417, ap_reg_pp0_iter5_tmp_11_5_8_reg_6597, ap_reg_pp0_iter5_tmp_11_5_9_reg_6807, ap_reg_pp0_iter6_tmp_11_5_s_reg_7037, ap_reg_pp0_iter6_tmp_11_5_10_reg_7217, ap_reg_pp0_iter7_tmp_11_5_11_reg_7352, ap_reg_pp0_iter7_tmp_11_5_12_reg_7432, ap_reg_pp0_iter8_tmp_11_5_13_reg_7512, ap_reg_pp0_iter8_tmp_11_5_14_reg_7592, ap_enable_reg_pp0_iter2, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_enable_reg_pp0_iter7, ap_enable_reg_pp0_iter8, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_453_p1 <= ap_reg_pp0_iter8_tmp_11_5_14_reg_7592;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_453_p1 <= ap_reg_pp0_iter8_tmp_11_5_13_reg_7512;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_453_p1 <= ap_reg_pp0_iter7_tmp_11_5_12_reg_7432;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_453_p1 <= ap_reg_pp0_iter7_tmp_11_5_11_reg_7352;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_453_p1 <= ap_reg_pp0_iter6_tmp_11_5_10_reg_7217;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_453_p1 <= ap_reg_pp0_iter6_tmp_11_5_s_reg_7037;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_453_p1 <= ap_reg_pp0_iter5_tmp_11_5_9_reg_6807;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_453_p1 <= ap_reg_pp0_iter5_tmp_11_5_8_reg_6597;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_453_p1 <= ap_reg_pp0_iter4_tmp_11_5_7_reg_6417;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_453_p1 <= ap_reg_pp0_iter4_tmp_11_5_6_reg_6182;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_453_p1 <= ap_reg_pp0_iter3_tmp_11_5_5_reg_5922;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_453_p1 <= ap_reg_pp0_iter3_tmp_11_5_4_reg_5657;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_453_p1 <= ap_reg_pp0_iter2_tmp_11_5_3_reg_5447;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_453_p1 <= ap_reg_pp0_iter1_tmp_11_5_2_reg_5247;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_453_p1 <= tmp_11_5_1_reg_5002;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_453_p1 <= tmp_11_5_reg_4777;
else
grp_fu_453_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_457_p0_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter9, reg_981, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, tmp_259_fu_2493_p1, tmp_12_6_reg_6817, ap_enable_reg_pp0_iter2, tmp_12_6_2_reg_7677, ap_enable_reg_pp0_iter3, tmp_12_6_3_reg_7757, tmp_12_6_4_reg_7837, ap_enable_reg_pp0_iter4, tmp_12_6_5_reg_7917, tmp_12_6_6_reg_7997, ap_enable_reg_pp0_iter5, tmp_12_6_7_reg_8077, tmp_12_6_8_reg_8157, ap_enable_reg_pp0_iter6, tmp_12_6_9_reg_8237, ap_enable_reg_pp0_iter7, tmp_12_6_s_reg_8317, tmp_12_6_10_reg_8397, ap_enable_reg_pp0_iter8, tmp_12_6_11_reg_8477, tmp_12_6_12_reg_8557, tmp_12_6_13_reg_8637, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_457_p0 <= tmp_12_6_13_reg_8637;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_457_p0 <= tmp_12_6_12_reg_8557;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_457_p0 <= tmp_12_6_11_reg_8477;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_457_p0 <= tmp_12_6_10_reg_8397;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_457_p0 <= tmp_12_6_s_reg_8317;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_457_p0 <= tmp_12_6_9_reg_8237;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_457_p0 <= tmp_12_6_8_reg_8157;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_457_p0 <= tmp_12_6_7_reg_8077;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_457_p0 <= tmp_12_6_6_reg_7997;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_457_p0 <= tmp_12_6_5_reg_7917;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_457_p0 <= tmp_12_6_4_reg_7837;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_457_p0 <= tmp_12_6_3_reg_7757;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_457_p0 <= tmp_12_6_2_reg_7677;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_457_p0 <= reg_981;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_457_p0 <= tmp_12_6_reg_6817;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_457_p0 <= tmp_259_fu_2493_p1;
else
grp_fu_457_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_457_p1_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter9, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, tmp_11_6_reg_4787, tmp_11_6_1_reg_5017, ap_reg_pp0_iter1_tmp_11_6_2_reg_5257, ap_reg_pp0_iter2_tmp_11_6_3_reg_5457, ap_reg_pp0_iter3_tmp_11_6_4_reg_5672, ap_reg_pp0_iter3_tmp_11_6_5_reg_5937, ap_reg_pp0_iter4_tmp_11_6_6_reg_6197, ap_reg_pp0_iter4_tmp_11_6_7_reg_6427, ap_reg_pp0_iter5_tmp_11_6_8_reg_6607, ap_reg_pp0_iter5_tmp_11_6_9_reg_6822, ap_reg_pp0_iter6_tmp_11_6_s_reg_7047, ap_reg_pp0_iter6_tmp_11_6_10_reg_7227, ap_reg_pp0_iter7_tmp_11_6_11_reg_7357, ap_reg_pp0_iter7_tmp_11_6_12_reg_7437, ap_reg_pp0_iter8_tmp_11_6_13_reg_7517, ap_reg_pp0_iter8_tmp_11_6_14_reg_7597, ap_enable_reg_pp0_iter2, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_enable_reg_pp0_iter7, ap_enable_reg_pp0_iter8, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_457_p1 <= ap_reg_pp0_iter8_tmp_11_6_14_reg_7597;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_457_p1 <= ap_reg_pp0_iter8_tmp_11_6_13_reg_7517;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_457_p1 <= ap_reg_pp0_iter7_tmp_11_6_12_reg_7437;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_457_p1 <= ap_reg_pp0_iter7_tmp_11_6_11_reg_7357;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_457_p1 <= ap_reg_pp0_iter6_tmp_11_6_10_reg_7227;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_457_p1 <= ap_reg_pp0_iter6_tmp_11_6_s_reg_7047;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_457_p1 <= ap_reg_pp0_iter5_tmp_11_6_9_reg_6822;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_457_p1 <= ap_reg_pp0_iter5_tmp_11_6_8_reg_6607;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_457_p1 <= ap_reg_pp0_iter4_tmp_11_6_7_reg_6427;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_457_p1 <= ap_reg_pp0_iter4_tmp_11_6_6_reg_6197;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_457_p1 <= ap_reg_pp0_iter3_tmp_11_6_5_reg_5937;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_457_p1 <= ap_reg_pp0_iter3_tmp_11_6_4_reg_5672;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_457_p1 <= ap_reg_pp0_iter2_tmp_11_6_3_reg_5457;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_457_p1 <= ap_reg_pp0_iter1_tmp_11_6_2_reg_5257;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_457_p1 <= tmp_11_6_1_reg_5017;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_457_p1 <= tmp_11_6_reg_4787;
else
grp_fu_457_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_461_p0_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter9, reg_986, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, tmp_294_fu_2502_p1, tmp_12_7_reg_6832, ap_enable_reg_pp0_iter2, tmp_12_7_2_reg_7682, ap_enable_reg_pp0_iter3, tmp_12_7_3_reg_7762, tmp_12_7_4_reg_7842, ap_enable_reg_pp0_iter4, tmp_12_7_5_reg_7922, tmp_12_7_6_reg_8002, ap_enable_reg_pp0_iter5, tmp_12_7_7_reg_8082, tmp_12_7_8_reg_8162, ap_enable_reg_pp0_iter6, tmp_12_7_9_reg_8242, ap_enable_reg_pp0_iter7, tmp_12_7_s_reg_8322, tmp_12_7_10_reg_8402, ap_enable_reg_pp0_iter8, tmp_12_7_11_reg_8482, tmp_12_7_12_reg_8562, tmp_12_7_13_reg_8642, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_461_p0 <= tmp_12_7_13_reg_8642;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_461_p0 <= tmp_12_7_12_reg_8562;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_461_p0 <= tmp_12_7_11_reg_8482;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_461_p0 <= tmp_12_7_10_reg_8402;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_461_p0 <= tmp_12_7_s_reg_8322;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_461_p0 <= tmp_12_7_9_reg_8242;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_461_p0 <= tmp_12_7_8_reg_8162;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_461_p0 <= tmp_12_7_7_reg_8082;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_461_p0 <= tmp_12_7_6_reg_8002;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_461_p0 <= tmp_12_7_5_reg_7922;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_461_p0 <= tmp_12_7_4_reg_7842;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_461_p0 <= tmp_12_7_3_reg_7762;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_461_p0 <= tmp_12_7_2_reg_7682;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_461_p0 <= reg_986;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_461_p0 <= tmp_12_7_reg_6832;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_461_p0 <= tmp_294_fu_2502_p1;
else
grp_fu_461_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_461_p1_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter9, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, tmp_11_7_reg_4797, tmp_11_7_1_reg_5032, ap_reg_pp0_iter1_tmp_11_7_2_reg_5267, ap_reg_pp0_iter2_tmp_11_7_3_reg_5467, ap_reg_pp0_iter3_tmp_11_7_4_reg_5687, ap_reg_pp0_iter3_tmp_11_7_5_reg_5952, ap_reg_pp0_iter4_tmp_11_7_6_reg_6212, ap_reg_pp0_iter4_tmp_11_7_7_reg_6437, ap_reg_pp0_iter5_tmp_11_7_8_reg_6617, ap_reg_pp0_iter5_tmp_11_7_9_reg_6837, ap_reg_pp0_iter6_tmp_11_7_s_reg_7057, ap_reg_pp0_iter6_tmp_11_7_10_reg_7237, ap_reg_pp0_iter7_tmp_11_7_11_reg_7362, ap_reg_pp0_iter7_tmp_11_7_12_reg_7442, ap_reg_pp0_iter8_tmp_11_7_13_reg_7522, ap_reg_pp0_iter8_tmp_11_7_14_reg_7602, ap_enable_reg_pp0_iter2, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_enable_reg_pp0_iter7, ap_enable_reg_pp0_iter8, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_461_p1 <= ap_reg_pp0_iter8_tmp_11_7_14_reg_7602;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_461_p1 <= ap_reg_pp0_iter8_tmp_11_7_13_reg_7522;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_461_p1 <= ap_reg_pp0_iter7_tmp_11_7_12_reg_7442;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_461_p1 <= ap_reg_pp0_iter7_tmp_11_7_11_reg_7362;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_461_p1 <= ap_reg_pp0_iter6_tmp_11_7_10_reg_7237;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_461_p1 <= ap_reg_pp0_iter6_tmp_11_7_s_reg_7057;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_461_p1 <= ap_reg_pp0_iter5_tmp_11_7_9_reg_6837;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_461_p1 <= ap_reg_pp0_iter5_tmp_11_7_8_reg_6617;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_461_p1 <= ap_reg_pp0_iter4_tmp_11_7_7_reg_6437;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_461_p1 <= ap_reg_pp0_iter4_tmp_11_7_6_reg_6212;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_461_p1 <= ap_reg_pp0_iter3_tmp_11_7_5_reg_5952;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_461_p1 <= ap_reg_pp0_iter3_tmp_11_7_4_reg_5687;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_461_p1 <= ap_reg_pp0_iter2_tmp_11_7_3_reg_5467;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_461_p1 <= ap_reg_pp0_iter1_tmp_11_7_2_reg_5267;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_461_p1 <= tmp_11_7_1_reg_5032;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_461_p1 <= tmp_11_7_reg_4797;
else
grp_fu_461_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_465_p0_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter9, reg_991, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, tmp_329_fu_2511_p1, tmp_12_8_reg_6847, ap_enable_reg_pp0_iter2, tmp_12_8_2_reg_7687, ap_enable_reg_pp0_iter3, tmp_12_8_3_reg_7767, tmp_12_8_4_reg_7847, ap_enable_reg_pp0_iter4, tmp_12_8_5_reg_7927, tmp_12_8_6_reg_8007, ap_enable_reg_pp0_iter5, tmp_12_8_7_reg_8087, tmp_12_8_8_reg_8167, ap_enable_reg_pp0_iter6, tmp_12_8_9_reg_8247, ap_enable_reg_pp0_iter7, tmp_12_8_s_reg_8327, tmp_12_8_10_reg_8407, ap_enable_reg_pp0_iter8, tmp_12_8_11_reg_8487, tmp_12_8_12_reg_8567, tmp_12_8_13_reg_8647, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_465_p0 <= tmp_12_8_13_reg_8647;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_465_p0 <= tmp_12_8_12_reg_8567;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_465_p0 <= tmp_12_8_11_reg_8487;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_465_p0 <= tmp_12_8_10_reg_8407;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_465_p0 <= tmp_12_8_s_reg_8327;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_465_p0 <= tmp_12_8_9_reg_8247;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_465_p0 <= tmp_12_8_8_reg_8167;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_465_p0 <= tmp_12_8_7_reg_8087;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_465_p0 <= tmp_12_8_6_reg_8007;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_465_p0 <= tmp_12_8_5_reg_7927;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_465_p0 <= tmp_12_8_4_reg_7847;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_465_p0 <= tmp_12_8_3_reg_7767;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_465_p0 <= tmp_12_8_2_reg_7687;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_465_p0 <= reg_991;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_465_p0 <= tmp_12_8_reg_6847;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_465_p0 <= tmp_329_fu_2511_p1;
else
grp_fu_465_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_465_p1_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter9, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, tmp_11_8_reg_4807, tmp_11_8_1_reg_5047, ap_reg_pp0_iter1_tmp_11_8_2_reg_5277, ap_reg_pp0_iter2_tmp_11_8_3_reg_5477, ap_reg_pp0_iter3_tmp_11_8_4_reg_5702, ap_reg_pp0_iter3_tmp_11_8_5_reg_5967, ap_reg_pp0_iter4_tmp_11_8_6_reg_6227, ap_reg_pp0_iter4_tmp_11_8_7_reg_6447, ap_reg_pp0_iter5_tmp_11_8_8_reg_6627, ap_reg_pp0_iter5_tmp_11_8_9_reg_6852, ap_reg_pp0_iter6_tmp_11_8_s_reg_7067, ap_reg_pp0_iter6_tmp_11_8_10_reg_7247, ap_reg_pp0_iter7_tmp_11_8_11_reg_7367, ap_reg_pp0_iter7_tmp_11_8_12_reg_7447, ap_reg_pp0_iter8_tmp_11_8_13_reg_7527, ap_reg_pp0_iter8_tmp_11_8_14_reg_7607, ap_enable_reg_pp0_iter2, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_enable_reg_pp0_iter7, ap_enable_reg_pp0_iter8, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_465_p1 <= ap_reg_pp0_iter8_tmp_11_8_14_reg_7607;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_465_p1 <= ap_reg_pp0_iter8_tmp_11_8_13_reg_7527;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_465_p1 <= ap_reg_pp0_iter7_tmp_11_8_12_reg_7447;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_465_p1 <= ap_reg_pp0_iter7_tmp_11_8_11_reg_7367;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_465_p1 <= ap_reg_pp0_iter6_tmp_11_8_10_reg_7247;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_465_p1 <= ap_reg_pp0_iter6_tmp_11_8_s_reg_7067;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_465_p1 <= ap_reg_pp0_iter5_tmp_11_8_9_reg_6852;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_465_p1 <= ap_reg_pp0_iter5_tmp_11_8_8_reg_6627;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_465_p1 <= ap_reg_pp0_iter4_tmp_11_8_7_reg_6447;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_465_p1 <= ap_reg_pp0_iter4_tmp_11_8_6_reg_6227;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_465_p1 <= ap_reg_pp0_iter3_tmp_11_8_5_reg_5967;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_465_p1 <= ap_reg_pp0_iter3_tmp_11_8_4_reg_5702;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_465_p1 <= ap_reg_pp0_iter2_tmp_11_8_3_reg_5477;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_465_p1 <= ap_reg_pp0_iter1_tmp_11_8_2_reg_5277;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_465_p1 <= tmp_11_8_1_reg_5047;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_465_p1 <= tmp_11_8_reg_4807;
else
grp_fu_465_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_469_p0_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter9, reg_996, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, tmp_364_fu_2520_p1, tmp_12_9_reg_6862, ap_enable_reg_pp0_iter2, tmp_12_9_2_reg_7692, ap_enable_reg_pp0_iter3, tmp_12_9_3_reg_7772, tmp_12_9_4_reg_7852, ap_enable_reg_pp0_iter4, tmp_12_9_5_reg_7932, tmp_12_9_6_reg_8012, ap_enable_reg_pp0_iter5, tmp_12_9_7_reg_8092, tmp_12_9_8_reg_8172, ap_enable_reg_pp0_iter6, tmp_12_9_9_reg_8252, ap_enable_reg_pp0_iter7, tmp_12_9_s_reg_8332, tmp_12_9_10_reg_8412, ap_enable_reg_pp0_iter8, tmp_12_9_11_reg_8492, tmp_12_9_12_reg_8572, tmp_12_9_13_reg_8652, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_469_p0 <= tmp_12_9_13_reg_8652;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_469_p0 <= tmp_12_9_12_reg_8572;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_469_p0 <= tmp_12_9_11_reg_8492;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_469_p0 <= tmp_12_9_10_reg_8412;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_469_p0 <= tmp_12_9_s_reg_8332;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_469_p0 <= tmp_12_9_9_reg_8252;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_469_p0 <= tmp_12_9_8_reg_8172;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_469_p0 <= tmp_12_9_7_reg_8092;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_469_p0 <= tmp_12_9_6_reg_8012;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_469_p0 <= tmp_12_9_5_reg_7932;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_469_p0 <= tmp_12_9_4_reg_7852;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_469_p0 <= tmp_12_9_3_reg_7772;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_469_p0 <= tmp_12_9_2_reg_7692;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_469_p0 <= reg_996;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_469_p0 <= tmp_12_9_reg_6862;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_469_p0 <= tmp_364_fu_2520_p1;
else
grp_fu_469_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_469_p1_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter9, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, tmp_11_9_reg_4817, tmp_11_9_1_reg_5062, ap_reg_pp0_iter1_tmp_11_9_2_reg_5287, ap_reg_pp0_iter2_tmp_11_9_3_reg_5487, ap_reg_pp0_iter3_tmp_11_9_4_reg_5717, ap_reg_pp0_iter3_tmp_11_9_5_reg_5982, ap_reg_pp0_iter4_tmp_11_9_6_reg_6242, ap_reg_pp0_iter4_tmp_11_9_7_reg_6457, ap_reg_pp0_iter5_tmp_11_9_8_reg_6637, ap_reg_pp0_iter5_tmp_11_9_9_reg_6867, ap_reg_pp0_iter6_tmp_11_9_s_reg_7077, ap_reg_pp0_iter6_tmp_11_9_10_reg_7257, ap_reg_pp0_iter7_tmp_11_9_11_reg_7372, ap_reg_pp0_iter7_tmp_11_9_12_reg_7452, ap_reg_pp0_iter8_tmp_11_9_13_reg_7532, ap_reg_pp0_iter8_tmp_11_9_14_reg_7612, ap_enable_reg_pp0_iter2, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_enable_reg_pp0_iter7, ap_enable_reg_pp0_iter8, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_469_p1 <= ap_reg_pp0_iter8_tmp_11_9_14_reg_7612;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_469_p1 <= ap_reg_pp0_iter8_tmp_11_9_13_reg_7532;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_469_p1 <= ap_reg_pp0_iter7_tmp_11_9_12_reg_7452;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_469_p1 <= ap_reg_pp0_iter7_tmp_11_9_11_reg_7372;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_469_p1 <= ap_reg_pp0_iter6_tmp_11_9_10_reg_7257;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_469_p1 <= ap_reg_pp0_iter6_tmp_11_9_s_reg_7077;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_469_p1 <= ap_reg_pp0_iter5_tmp_11_9_9_reg_6867;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_469_p1 <= ap_reg_pp0_iter5_tmp_11_9_8_reg_6637;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_469_p1 <= ap_reg_pp0_iter4_tmp_11_9_7_reg_6457;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_469_p1 <= ap_reg_pp0_iter4_tmp_11_9_6_reg_6242;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_469_p1 <= ap_reg_pp0_iter3_tmp_11_9_5_reg_5982;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_469_p1 <= ap_reg_pp0_iter3_tmp_11_9_4_reg_5717;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_469_p1 <= ap_reg_pp0_iter2_tmp_11_9_3_reg_5487;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_469_p1 <= ap_reg_pp0_iter1_tmp_11_9_2_reg_5287;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_469_p1 <= tmp_11_9_1_reg_5062;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_469_p1 <= tmp_11_9_reg_4817;
else
grp_fu_469_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_473_p0_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter9, reg_1001, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, tmp_399_fu_2529_p1, tmp_12_s_reg_6877, ap_enable_reg_pp0_iter2, tmp_12_10_2_reg_7697, ap_enable_reg_pp0_iter3, tmp_12_10_3_reg_7777, tmp_12_10_4_reg_7857, ap_enable_reg_pp0_iter4, tmp_12_10_5_reg_7937, tmp_12_10_6_reg_8017, ap_enable_reg_pp0_iter5, tmp_12_10_7_reg_8097, tmp_12_10_8_reg_8177, ap_enable_reg_pp0_iter6, tmp_12_10_9_reg_8257, ap_enable_reg_pp0_iter7, tmp_12_10_s_reg_8337, tmp_12_10_10_reg_8417, ap_enable_reg_pp0_iter8, tmp_12_10_11_reg_8497, tmp_12_10_12_reg_8577, tmp_12_10_13_reg_8657, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_473_p0 <= tmp_12_10_13_reg_8657;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_473_p0 <= tmp_12_10_12_reg_8577;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_473_p0 <= tmp_12_10_11_reg_8497;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_473_p0 <= tmp_12_10_10_reg_8417;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_473_p0 <= tmp_12_10_s_reg_8337;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_473_p0 <= tmp_12_10_9_reg_8257;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_473_p0 <= tmp_12_10_8_reg_8177;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_473_p0 <= tmp_12_10_7_reg_8097;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_473_p0 <= tmp_12_10_6_reg_8017;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_473_p0 <= tmp_12_10_5_reg_7937;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_473_p0 <= tmp_12_10_4_reg_7857;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_473_p0 <= tmp_12_10_3_reg_7777;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_473_p0 <= tmp_12_10_2_reg_7697;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_473_p0 <= reg_1001;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_473_p0 <= tmp_12_s_reg_6877;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_473_p0 <= tmp_399_fu_2529_p1;
else
grp_fu_473_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_473_p1_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter9, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, tmp_11_s_reg_4827, tmp_11_10_1_reg_5077, ap_reg_pp0_iter1_tmp_11_10_2_reg_5297, ap_reg_pp0_iter2_tmp_11_10_3_reg_5497, ap_reg_pp0_iter3_tmp_11_10_4_reg_5732, ap_reg_pp0_iter3_tmp_11_10_5_reg_5997, ap_reg_pp0_iter4_tmp_11_10_6_reg_6257, ap_reg_pp0_iter4_tmp_11_10_7_reg_6467, ap_reg_pp0_iter5_tmp_11_10_8_reg_6647, ap_reg_pp0_iter5_tmp_11_10_9_reg_6882, ap_reg_pp0_iter6_tmp_11_10_s_reg_7087, ap_reg_pp0_iter6_tmp_11_10_10_reg_7267, ap_reg_pp0_iter7_tmp_11_10_11_reg_7377, ap_reg_pp0_iter7_tmp_11_10_12_reg_7457, ap_reg_pp0_iter8_tmp_11_10_13_reg_7537, ap_reg_pp0_iter8_tmp_11_10_14_reg_7617, ap_enable_reg_pp0_iter2, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_enable_reg_pp0_iter7, ap_enable_reg_pp0_iter8, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_473_p1 <= ap_reg_pp0_iter8_tmp_11_10_14_reg_7617;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_473_p1 <= ap_reg_pp0_iter8_tmp_11_10_13_reg_7537;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_473_p1 <= ap_reg_pp0_iter7_tmp_11_10_12_reg_7457;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_473_p1 <= ap_reg_pp0_iter7_tmp_11_10_11_reg_7377;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_473_p1 <= ap_reg_pp0_iter6_tmp_11_10_10_reg_7267;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_473_p1 <= ap_reg_pp0_iter6_tmp_11_10_s_reg_7087;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_473_p1 <= ap_reg_pp0_iter5_tmp_11_10_9_reg_6882;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_473_p1 <= ap_reg_pp0_iter5_tmp_11_10_8_reg_6647;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_473_p1 <= ap_reg_pp0_iter4_tmp_11_10_7_reg_6467;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_473_p1 <= ap_reg_pp0_iter4_tmp_11_10_6_reg_6257;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_473_p1 <= ap_reg_pp0_iter3_tmp_11_10_5_reg_5997;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_473_p1 <= ap_reg_pp0_iter3_tmp_11_10_4_reg_5732;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_473_p1 <= ap_reg_pp0_iter2_tmp_11_10_3_reg_5497;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_473_p1 <= ap_reg_pp0_iter1_tmp_11_10_2_reg_5297;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_473_p1 <= tmp_11_10_1_reg_5077;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_473_p1 <= tmp_11_s_reg_4827;
else
grp_fu_473_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_477_p0_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter9, reg_1006, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, tmp_434_fu_2538_p1, tmp_12_10_reg_6892, ap_enable_reg_pp0_iter2, tmp_12_11_2_reg_7702, ap_enable_reg_pp0_iter3, tmp_12_11_3_reg_7782, tmp_12_11_4_reg_7862, ap_enable_reg_pp0_iter4, tmp_12_11_5_reg_7942, tmp_12_11_6_reg_8022, ap_enable_reg_pp0_iter5, tmp_12_11_7_reg_8102, tmp_12_11_8_reg_8182, ap_enable_reg_pp0_iter6, tmp_12_11_9_reg_8262, ap_enable_reg_pp0_iter7, tmp_12_11_s_reg_8342, tmp_12_11_10_reg_8422, ap_enable_reg_pp0_iter8, tmp_12_11_11_reg_8502, tmp_12_11_12_reg_8582, tmp_12_11_13_reg_8662, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_477_p0 <= tmp_12_11_13_reg_8662;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_477_p0 <= tmp_12_11_12_reg_8582;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_477_p0 <= tmp_12_11_11_reg_8502;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_477_p0 <= tmp_12_11_10_reg_8422;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_477_p0 <= tmp_12_11_s_reg_8342;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_477_p0 <= tmp_12_11_9_reg_8262;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_477_p0 <= tmp_12_11_8_reg_8182;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_477_p0 <= tmp_12_11_7_reg_8102;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_477_p0 <= tmp_12_11_6_reg_8022;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_477_p0 <= tmp_12_11_5_reg_7942;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_477_p0 <= tmp_12_11_4_reg_7862;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_477_p0 <= tmp_12_11_3_reg_7782;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_477_p0 <= tmp_12_11_2_reg_7702;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_477_p0 <= reg_1006;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_477_p0 <= tmp_12_10_reg_6892;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_477_p0 <= tmp_434_fu_2538_p1;
else
grp_fu_477_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_477_p1_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter9, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, tmp_11_10_reg_4837, tmp_11_11_1_reg_5092, ap_reg_pp0_iter1_tmp_11_11_2_reg_5307, ap_reg_pp0_iter2_tmp_11_11_3_reg_5507, ap_reg_pp0_iter3_tmp_11_11_4_reg_5747, ap_reg_pp0_iter3_tmp_11_11_5_reg_6012, ap_reg_pp0_iter4_tmp_11_11_6_reg_6272, ap_reg_pp0_iter4_tmp_11_11_7_reg_6477, ap_reg_pp0_iter5_tmp_11_11_8_reg_6657, ap_reg_pp0_iter5_tmp_11_11_9_reg_6897, ap_reg_pp0_iter6_tmp_11_11_s_reg_7097, ap_reg_pp0_iter6_tmp_11_11_10_reg_7277, ap_reg_pp0_iter7_tmp_11_11_11_reg_7382, ap_reg_pp0_iter7_tmp_11_11_12_reg_7462, ap_reg_pp0_iter8_tmp_11_11_13_reg_7542, ap_reg_pp0_iter8_tmp_11_11_14_reg_7622, ap_enable_reg_pp0_iter2, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_enable_reg_pp0_iter7, ap_enable_reg_pp0_iter8, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_477_p1 <= ap_reg_pp0_iter8_tmp_11_11_14_reg_7622;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_477_p1 <= ap_reg_pp0_iter8_tmp_11_11_13_reg_7542;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_477_p1 <= ap_reg_pp0_iter7_tmp_11_11_12_reg_7462;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_477_p1 <= ap_reg_pp0_iter7_tmp_11_11_11_reg_7382;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_477_p1 <= ap_reg_pp0_iter6_tmp_11_11_10_reg_7277;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_477_p1 <= ap_reg_pp0_iter6_tmp_11_11_s_reg_7097;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_477_p1 <= ap_reg_pp0_iter5_tmp_11_11_9_reg_6897;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_477_p1 <= ap_reg_pp0_iter5_tmp_11_11_8_reg_6657;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_477_p1 <= ap_reg_pp0_iter4_tmp_11_11_7_reg_6477;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_477_p1 <= ap_reg_pp0_iter4_tmp_11_11_6_reg_6272;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_477_p1 <= ap_reg_pp0_iter3_tmp_11_11_5_reg_6012;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_477_p1 <= ap_reg_pp0_iter3_tmp_11_11_4_reg_5747;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_477_p1 <= ap_reg_pp0_iter2_tmp_11_11_3_reg_5507;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_477_p1 <= ap_reg_pp0_iter1_tmp_11_11_2_reg_5307;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_477_p1 <= tmp_11_11_1_reg_5092;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_477_p1 <= tmp_11_10_reg_4837;
else
grp_fu_477_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_481_p0_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter9, reg_1011, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, tmp_469_fu_2547_p1, tmp_12_11_reg_6907, ap_enable_reg_pp0_iter2, tmp_12_12_2_reg_7707, ap_enable_reg_pp0_iter3, tmp_12_12_3_reg_7787, tmp_12_12_4_reg_7867, ap_enable_reg_pp0_iter4, tmp_12_12_5_reg_7947, tmp_12_12_6_reg_8027, ap_enable_reg_pp0_iter5, tmp_12_12_7_reg_8107, tmp_12_12_8_reg_8187, ap_enable_reg_pp0_iter6, tmp_12_12_9_reg_8267, ap_enable_reg_pp0_iter7, tmp_12_12_s_reg_8347, tmp_12_12_10_reg_8427, ap_enable_reg_pp0_iter8, tmp_12_12_11_reg_8507, tmp_12_12_12_reg_8587, tmp_12_12_13_reg_8667, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_481_p0 <= tmp_12_12_13_reg_8667;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_481_p0 <= tmp_12_12_12_reg_8587;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_481_p0 <= tmp_12_12_11_reg_8507;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_481_p0 <= tmp_12_12_10_reg_8427;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_481_p0 <= tmp_12_12_s_reg_8347;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_481_p0 <= tmp_12_12_9_reg_8267;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_481_p0 <= tmp_12_12_8_reg_8187;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_481_p0 <= tmp_12_12_7_reg_8107;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_481_p0 <= tmp_12_12_6_reg_8027;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_481_p0 <= tmp_12_12_5_reg_7947;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_481_p0 <= tmp_12_12_4_reg_7867;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_481_p0 <= tmp_12_12_3_reg_7787;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_481_p0 <= tmp_12_12_2_reg_7707;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_481_p0 <= reg_1011;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_481_p0 <= tmp_12_11_reg_6907;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_481_p0 <= tmp_469_fu_2547_p1;
else
grp_fu_481_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_481_p1_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter9, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, tmp_11_11_reg_4847, tmp_11_12_1_reg_5107, ap_reg_pp0_iter1_tmp_11_12_2_reg_5317, ap_reg_pp0_iter2_tmp_11_12_3_reg_5517, ap_reg_pp0_iter3_tmp_11_12_4_reg_5762, ap_reg_pp0_iter3_tmp_11_12_5_reg_6027, ap_reg_pp0_iter4_tmp_11_12_6_reg_6287, ap_reg_pp0_iter4_tmp_11_12_7_reg_6487, ap_reg_pp0_iter5_tmp_11_12_8_reg_6667, ap_reg_pp0_iter5_tmp_11_12_9_reg_6912, ap_reg_pp0_iter6_tmp_11_12_s_reg_7107, ap_reg_pp0_iter6_tmp_11_12_10_reg_7287, ap_reg_pp0_iter7_tmp_11_12_11_reg_7387, ap_reg_pp0_iter7_tmp_11_12_12_reg_7467, ap_reg_pp0_iter8_tmp_11_12_13_reg_7547, ap_reg_pp0_iter8_tmp_11_12_14_reg_7627, ap_enable_reg_pp0_iter2, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_enable_reg_pp0_iter7, ap_enable_reg_pp0_iter8, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_481_p1 <= ap_reg_pp0_iter8_tmp_11_12_14_reg_7627;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_481_p1 <= ap_reg_pp0_iter8_tmp_11_12_13_reg_7547;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_481_p1 <= ap_reg_pp0_iter7_tmp_11_12_12_reg_7467;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_481_p1 <= ap_reg_pp0_iter7_tmp_11_12_11_reg_7387;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_481_p1 <= ap_reg_pp0_iter6_tmp_11_12_10_reg_7287;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_481_p1 <= ap_reg_pp0_iter6_tmp_11_12_s_reg_7107;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_481_p1 <= ap_reg_pp0_iter5_tmp_11_12_9_reg_6912;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_481_p1 <= ap_reg_pp0_iter5_tmp_11_12_8_reg_6667;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_481_p1 <= ap_reg_pp0_iter4_tmp_11_12_7_reg_6487;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_481_p1 <= ap_reg_pp0_iter4_tmp_11_12_6_reg_6287;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_481_p1 <= ap_reg_pp0_iter3_tmp_11_12_5_reg_6027;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_481_p1 <= ap_reg_pp0_iter3_tmp_11_12_4_reg_5762;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_481_p1 <= ap_reg_pp0_iter2_tmp_11_12_3_reg_5517;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_481_p1 <= ap_reg_pp0_iter1_tmp_11_12_2_reg_5317;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_481_p1 <= tmp_11_12_1_reg_5107;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_481_p1 <= tmp_11_11_reg_4847;
else
grp_fu_481_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_485_p0_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter9, reg_1016, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, tmp_504_fu_2556_p1, tmp_12_12_reg_6922, ap_enable_reg_pp0_iter2, tmp_12_13_2_reg_7712, ap_enable_reg_pp0_iter3, tmp_12_13_3_reg_7792, tmp_12_13_4_reg_7872, ap_enable_reg_pp0_iter4, tmp_12_13_5_reg_7952, tmp_12_13_6_reg_8032, ap_enable_reg_pp0_iter5, tmp_12_13_7_reg_8112, tmp_12_13_8_reg_8192, ap_enable_reg_pp0_iter6, tmp_12_13_9_reg_8272, ap_enable_reg_pp0_iter7, tmp_12_13_s_reg_8352, tmp_12_13_10_reg_8432, ap_enable_reg_pp0_iter8, tmp_12_13_11_reg_8512, tmp_12_13_12_reg_8592, tmp_12_13_13_reg_8672, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_485_p0 <= tmp_12_13_13_reg_8672;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_485_p0 <= tmp_12_13_12_reg_8592;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_485_p0 <= tmp_12_13_11_reg_8512;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_485_p0 <= tmp_12_13_10_reg_8432;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_485_p0 <= tmp_12_13_s_reg_8352;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_485_p0 <= tmp_12_13_9_reg_8272;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_485_p0 <= tmp_12_13_8_reg_8192;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_485_p0 <= tmp_12_13_7_reg_8112;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_485_p0 <= tmp_12_13_6_reg_8032;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_485_p0 <= tmp_12_13_5_reg_7952;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_485_p0 <= tmp_12_13_4_reg_7872;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_485_p0 <= tmp_12_13_3_reg_7792;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_485_p0 <= tmp_12_13_2_reg_7712;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_485_p0 <= reg_1016;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_485_p0 <= tmp_12_12_reg_6922;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_485_p0 <= tmp_504_fu_2556_p1;
else
grp_fu_485_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_485_p1_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter9, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, tmp_11_12_reg_4857, tmp_11_13_1_reg_5122, ap_reg_pp0_iter1_tmp_11_13_2_reg_5327, ap_reg_pp0_iter2_tmp_11_13_3_reg_5527, ap_reg_pp0_iter3_tmp_11_13_4_reg_5777, ap_reg_pp0_iter3_tmp_11_13_5_reg_6042, ap_reg_pp0_iter4_tmp_11_13_6_reg_6302, ap_reg_pp0_iter4_tmp_11_13_7_reg_6497, ap_reg_pp0_iter5_tmp_11_13_8_reg_6677, ap_reg_pp0_iter5_tmp_11_13_9_reg_6927, ap_reg_pp0_iter6_tmp_11_13_s_reg_7117, ap_reg_pp0_iter6_tmp_11_13_10_reg_7297, ap_reg_pp0_iter7_tmp_11_13_11_reg_7392, ap_reg_pp0_iter7_tmp_11_13_12_reg_7472, ap_reg_pp0_iter8_tmp_11_13_13_reg_7552, ap_reg_pp0_iter8_tmp_11_13_14_reg_7632, ap_enable_reg_pp0_iter2, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_enable_reg_pp0_iter7, ap_enable_reg_pp0_iter8, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_485_p1 <= ap_reg_pp0_iter8_tmp_11_13_14_reg_7632;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_485_p1 <= ap_reg_pp0_iter8_tmp_11_13_13_reg_7552;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_485_p1 <= ap_reg_pp0_iter7_tmp_11_13_12_reg_7472;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_485_p1 <= ap_reg_pp0_iter7_tmp_11_13_11_reg_7392;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_485_p1 <= ap_reg_pp0_iter6_tmp_11_13_10_reg_7297;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_485_p1 <= ap_reg_pp0_iter6_tmp_11_13_s_reg_7117;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_485_p1 <= ap_reg_pp0_iter5_tmp_11_13_9_reg_6927;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_485_p1 <= ap_reg_pp0_iter5_tmp_11_13_8_reg_6677;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_485_p1 <= ap_reg_pp0_iter4_tmp_11_13_7_reg_6497;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_485_p1 <= ap_reg_pp0_iter4_tmp_11_13_6_reg_6302;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_485_p1 <= ap_reg_pp0_iter3_tmp_11_13_5_reg_6042;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_485_p1 <= ap_reg_pp0_iter3_tmp_11_13_4_reg_5777;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_485_p1 <= ap_reg_pp0_iter2_tmp_11_13_3_reg_5527;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_485_p1 <= ap_reg_pp0_iter1_tmp_11_13_2_reg_5327;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_485_p1 <= tmp_11_13_1_reg_5122;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_485_p1 <= tmp_11_12_reg_4857;
else
grp_fu_485_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_489_p0_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter9, reg_1021, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, tmp_539_fu_2565_p1, tmp_12_13_reg_6937, ap_enable_reg_pp0_iter2, tmp_12_14_2_reg_7717, ap_enable_reg_pp0_iter3, tmp_12_14_3_reg_7797, tmp_12_14_4_reg_7877, ap_enable_reg_pp0_iter4, tmp_12_14_5_reg_7957, tmp_12_14_6_reg_8037, ap_enable_reg_pp0_iter5, tmp_12_14_7_reg_8117, tmp_12_14_8_reg_8197, ap_enable_reg_pp0_iter6, tmp_12_14_9_reg_8277, ap_enable_reg_pp0_iter7, tmp_12_14_s_reg_8357, tmp_12_14_10_reg_8437, ap_enable_reg_pp0_iter8, tmp_12_14_11_reg_8517, tmp_12_14_12_reg_8597, tmp_12_14_13_reg_8677, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_489_p0 <= tmp_12_14_13_reg_8677;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_489_p0 <= tmp_12_14_12_reg_8597;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_489_p0 <= tmp_12_14_11_reg_8517;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_489_p0 <= tmp_12_14_10_reg_8437;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_489_p0 <= tmp_12_14_s_reg_8357;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_489_p0 <= tmp_12_14_9_reg_8277;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_489_p0 <= tmp_12_14_8_reg_8197;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_489_p0 <= tmp_12_14_7_reg_8117;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_489_p0 <= tmp_12_14_6_reg_8037;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_489_p0 <= tmp_12_14_5_reg_7957;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_489_p0 <= tmp_12_14_4_reg_7877;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_489_p0 <= tmp_12_14_3_reg_7797;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_489_p0 <= tmp_12_14_2_reg_7717;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_489_p0 <= reg_1021;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_489_p0 <= tmp_12_13_reg_6937;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_489_p0 <= tmp_539_fu_2565_p1;
else
grp_fu_489_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_489_p1_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter9, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, tmp_11_13_reg_4867, tmp_11_14_1_reg_5137, ap_reg_pp0_iter1_tmp_11_14_2_reg_5337, ap_reg_pp0_iter2_tmp_11_14_3_reg_5537, ap_reg_pp0_iter3_tmp_11_14_4_reg_5792, ap_reg_pp0_iter3_tmp_11_14_5_reg_6057, ap_reg_pp0_iter4_tmp_11_14_6_reg_6317, ap_reg_pp0_iter4_tmp_11_14_7_reg_6507, ap_reg_pp0_iter5_tmp_11_14_8_reg_6687, ap_reg_pp0_iter5_tmp_11_14_9_reg_6942, ap_reg_pp0_iter6_tmp_11_14_s_reg_7127, ap_reg_pp0_iter6_tmp_11_14_10_reg_7307, ap_reg_pp0_iter7_tmp_11_14_11_reg_7397, ap_reg_pp0_iter7_tmp_11_14_12_reg_7477, ap_reg_pp0_iter8_tmp_11_14_13_reg_7557, ap_reg_pp0_iter8_tmp_11_14_14_reg_7637, ap_enable_reg_pp0_iter2, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_enable_reg_pp0_iter7, ap_enable_reg_pp0_iter8, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_489_p1 <= ap_reg_pp0_iter8_tmp_11_14_14_reg_7637;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_489_p1 <= ap_reg_pp0_iter8_tmp_11_14_13_reg_7557;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_489_p1 <= ap_reg_pp0_iter7_tmp_11_14_12_reg_7477;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_489_p1 <= ap_reg_pp0_iter7_tmp_11_14_11_reg_7397;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_489_p1 <= ap_reg_pp0_iter6_tmp_11_14_10_reg_7307;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_489_p1 <= ap_reg_pp0_iter6_tmp_11_14_s_reg_7127;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_489_p1 <= ap_reg_pp0_iter5_tmp_11_14_9_reg_6942;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_489_p1 <= ap_reg_pp0_iter5_tmp_11_14_8_reg_6687;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_489_p1 <= ap_reg_pp0_iter4_tmp_11_14_7_reg_6507;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_489_p1 <= ap_reg_pp0_iter4_tmp_11_14_6_reg_6317;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_489_p1 <= ap_reg_pp0_iter3_tmp_11_14_5_reg_6057;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_489_p1 <= ap_reg_pp0_iter3_tmp_11_14_4_reg_5792;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_489_p1 <= ap_reg_pp0_iter2_tmp_11_14_3_reg_5537;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_489_p1 <= ap_reg_pp0_iter1_tmp_11_14_2_reg_5337;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_489_p1 <= tmp_11_14_1_reg_5137;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_489_p1 <= tmp_11_13_reg_4867;
else
grp_fu_489_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_493_p0_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter9, reg_1026, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, tmp_574_fu_2574_p1, tmp_12_14_reg_6952, ap_enable_reg_pp0_iter2, tmp_12_15_2_reg_7722, ap_enable_reg_pp0_iter3, tmp_12_15_3_reg_7802, tmp_12_15_4_reg_7882, ap_enable_reg_pp0_iter4, tmp_12_15_5_reg_7962, tmp_12_15_6_reg_8042, ap_enable_reg_pp0_iter5, tmp_12_15_7_reg_8122, tmp_12_15_8_reg_8202, ap_enable_reg_pp0_iter6, tmp_12_15_9_reg_8282, ap_enable_reg_pp0_iter7, tmp_12_15_s_reg_8362, tmp_12_15_10_reg_8442, ap_enable_reg_pp0_iter8, tmp_12_15_11_reg_8522, tmp_12_15_12_reg_8602, tmp_12_15_13_reg_8682, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_493_p0 <= tmp_12_15_13_reg_8682;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_493_p0 <= tmp_12_15_12_reg_8602;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_493_p0 <= tmp_12_15_11_reg_8522;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_493_p0 <= tmp_12_15_10_reg_8442;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_493_p0 <= tmp_12_15_s_reg_8362;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_493_p0 <= tmp_12_15_9_reg_8282;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_493_p0 <= tmp_12_15_8_reg_8202;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_493_p0 <= tmp_12_15_7_reg_8122;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_493_p0 <= tmp_12_15_6_reg_8042;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_493_p0 <= tmp_12_15_5_reg_7962;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_493_p0 <= tmp_12_15_4_reg_7882;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_493_p0 <= tmp_12_15_3_reg_7802;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_493_p0 <= tmp_12_15_2_reg_7722;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_493_p0 <= reg_1026;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_493_p0 <= tmp_12_14_reg_6952;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_493_p0 <= tmp_574_fu_2574_p1;
else
grp_fu_493_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_493_p1_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter9, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, tmp_11_14_reg_4877, tmp_11_15_1_reg_5152, ap_reg_pp0_iter1_tmp_11_15_2_reg_5347, ap_reg_pp0_iter2_tmp_11_15_3_reg_5547, ap_reg_pp0_iter3_tmp_11_15_4_reg_5807, ap_reg_pp0_iter3_tmp_11_15_5_reg_6072, ap_reg_pp0_iter4_tmp_11_15_6_reg_6332, ap_reg_pp0_iter4_tmp_11_15_7_reg_6517, ap_reg_pp0_iter5_tmp_11_15_8_reg_6697, ap_reg_pp0_iter5_tmp_11_15_9_reg_6957, ap_reg_pp0_iter6_tmp_11_15_s_reg_7137, ap_reg_pp0_iter6_tmp_11_15_10_reg_7317, ap_reg_pp0_iter7_tmp_11_15_11_reg_7402, ap_reg_pp0_iter7_tmp_11_15_12_reg_7482, ap_reg_pp0_iter8_tmp_11_15_13_reg_7562, ap_reg_pp0_iter8_tmp_11_15_14_reg_7642, ap_enable_reg_pp0_iter2, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_enable_reg_pp0_iter7, ap_enable_reg_pp0_iter8, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_493_p1 <= ap_reg_pp0_iter8_tmp_11_15_14_reg_7642;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_493_p1 <= ap_reg_pp0_iter8_tmp_11_15_13_reg_7562;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_493_p1 <= ap_reg_pp0_iter7_tmp_11_15_12_reg_7482;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_493_p1 <= ap_reg_pp0_iter7_tmp_11_15_11_reg_7402;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_493_p1 <= ap_reg_pp0_iter6_tmp_11_15_10_reg_7317;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_493_p1 <= ap_reg_pp0_iter6_tmp_11_15_s_reg_7137;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_493_p1 <= ap_reg_pp0_iter5_tmp_11_15_9_reg_6957;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_493_p1 <= ap_reg_pp0_iter5_tmp_11_15_8_reg_6697;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_493_p1 <= ap_reg_pp0_iter4_tmp_11_15_7_reg_6517;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_493_p1 <= ap_reg_pp0_iter4_tmp_11_15_6_reg_6332;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_493_p1 <= ap_reg_pp0_iter3_tmp_11_15_5_reg_6072;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_493_p1 <= ap_reg_pp0_iter3_tmp_11_15_4_reg_5807;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_493_p1 <= ap_reg_pp0_iter2_tmp_11_15_3_reg_5547;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_493_p1 <= ap_reg_pp0_iter1_tmp_11_15_2_reg_5347;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_493_p1 <= tmp_11_15_1_reg_5152;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_493_p1 <= tmp_11_14_reg_4877;
else
grp_fu_493_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_497_p0_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, tmp_14_fu_1839_p1, tmp_20_fu_1945_p1, tmp_24_fu_2069_p1, tmp_28_fu_2185_p1, tmp_32_fu_2301_p1, tmp_36_fu_2421_p1, tmp_40_fu_2597_p1, tmp_44_fu_2723_p1, tmp_48_fu_2829_p1, tmp_52_fu_2920_p1, tmp_56_fu_3022_p1, tmp_60_fu_3124_p1, tmp_64_fu_3222_p1, tmp_68_fu_3320_p1, tmp_72_fu_3403_p1, tmp_76_fu_3486_p1, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_497_p0 <= tmp_76_fu_3486_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_497_p0 <= tmp_72_fu_3403_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_497_p0 <= tmp_68_fu_3320_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_497_p0 <= tmp_64_fu_3222_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_497_p0 <= tmp_60_fu_3124_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_497_p0 <= tmp_56_fu_3022_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_497_p0 <= tmp_52_fu_2920_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_497_p0 <= tmp_48_fu_2829_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_497_p0 <= tmp_44_fu_2723_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_497_p0 <= tmp_40_fu_2597_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_497_p0 <= tmp_36_fu_2421_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_497_p0 <= tmp_32_fu_2301_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_497_p0 <= tmp_28_fu_2185_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_497_p0 <= tmp_24_fu_2069_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_497_p0 <= tmp_20_fu_1945_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_497_p0 <= tmp_14_fu_1839_p1;
else
grp_fu_497_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_497_p1_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, tmp_16_fu_1843_p1, tmp_22_fu_1949_p1, tmp_26_fu_2073_p1, tmp_30_fu_2189_p1, tmp_34_fu_2305_p1, tmp_38_fu_2425_p1, tmp_42_fu_2601_p1, tmp_46_fu_2727_p1, tmp_50_fu_2833_p1, tmp_54_fu_2924_p1, tmp_58_fu_3026_p1, tmp_62_fu_3128_p1, tmp_66_fu_3226_p1, tmp_70_fu_3324_p1, tmp_74_fu_3407_p1, tmp_78_fu_3490_p1, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_497_p1 <= tmp_78_fu_3490_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_497_p1 <= tmp_74_fu_3407_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_497_p1 <= tmp_70_fu_3324_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_497_p1 <= tmp_66_fu_3226_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_497_p1 <= tmp_62_fu_3128_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_497_p1 <= tmp_58_fu_3026_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_497_p1 <= tmp_54_fu_2924_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_497_p1 <= tmp_50_fu_2833_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_497_p1 <= tmp_46_fu_2727_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_497_p1 <= tmp_42_fu_2601_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_497_p1 <= tmp_38_fu_2425_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_497_p1 <= tmp_34_fu_2305_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_497_p1 <= tmp_30_fu_2189_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_497_p1 <= tmp_26_fu_2073_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_497_p1 <= tmp_22_fu_1949_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_497_p1 <= tmp_16_fu_1843_p1;
else
grp_fu_497_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_501_p0_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, tmp_81_fu_1866_p1, tmp_85_fu_1972_p1, tmp_87_fu_2096_p1, tmp_89_fu_2212_p1, tmp_91_fu_2328_p1, tmp_93_fu_2452_p1, tmp_95_fu_2624_p1, tmp_97_fu_2750_p1, tmp_99_fu_2856_p1, tmp_101_fu_2947_p1, tmp_103_fu_3049_p1, tmp_105_fu_3147_p1, tmp_107_fu_3245_p1, tmp_109_fu_3343_p1, tmp_111_fu_3426_p1, tmp_113_fu_3509_p1, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_501_p0 <= tmp_113_fu_3509_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_501_p0 <= tmp_111_fu_3426_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_501_p0 <= tmp_109_fu_3343_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_501_p0 <= tmp_107_fu_3245_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_501_p0 <= tmp_105_fu_3147_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_501_p0 <= tmp_103_fu_3049_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_501_p0 <= tmp_101_fu_2947_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_501_p0 <= tmp_99_fu_2856_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_501_p0 <= tmp_97_fu_2750_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_501_p0 <= tmp_95_fu_2624_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_501_p0 <= tmp_93_fu_2452_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_501_p0 <= tmp_91_fu_2328_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_501_p0 <= tmp_89_fu_2212_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_501_p0 <= tmp_87_fu_2096_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_501_p0 <= tmp_85_fu_1972_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_501_p0 <= tmp_81_fu_1866_p1;
else
grp_fu_501_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_501_p1_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, tmp_16_fu_1843_p1, tmp_22_fu_1949_p1, tmp_26_fu_2073_p1, tmp_30_fu_2189_p1, tmp_34_fu_2305_p1, tmp_38_fu_2425_p1, tmp_42_fu_2601_p1, tmp_46_fu_2727_p1, tmp_50_fu_2833_p1, tmp_54_fu_2924_p1, tmp_58_fu_3026_p1, tmp_62_fu_3128_p1, tmp_66_fu_3226_p1, tmp_70_fu_3324_p1, tmp_74_fu_3407_p1, tmp_78_fu_3490_p1, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_501_p1 <= tmp_78_fu_3490_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_501_p1 <= tmp_74_fu_3407_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_501_p1 <= tmp_70_fu_3324_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_501_p1 <= tmp_66_fu_3226_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_501_p1 <= tmp_62_fu_3128_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_501_p1 <= tmp_58_fu_3026_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_501_p1 <= tmp_54_fu_2924_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_501_p1 <= tmp_50_fu_2833_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_501_p1 <= tmp_46_fu_2727_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_501_p1 <= tmp_42_fu_2601_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_501_p1 <= tmp_38_fu_2425_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_501_p1 <= tmp_34_fu_2305_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_501_p1 <= tmp_30_fu_2189_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_501_p1 <= tmp_26_fu_2073_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_501_p1 <= tmp_22_fu_1949_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_501_p1 <= tmp_16_fu_1843_p1;
else
grp_fu_501_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_505_p0_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, tmp_117_fu_1871_p1, tmp_121_fu_1977_p1, tmp_123_fu_2101_p1, tmp_125_fu_2217_p1, tmp_127_fu_2333_p1, tmp_129_fu_2461_p1, tmp_131_fu_2629_p1, tmp_133_fu_2755_p1, tmp_135_fu_2860_p1, tmp_137_fu_2952_p1, tmp_139_fu_3054_p1, tmp_141_fu_3152_p1, tmp_143_fu_3250_p1, tmp_145_fu_3347_p1, tmp_147_fu_3430_p1, tmp_149_fu_3513_p1, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_505_p0 <= tmp_149_fu_3513_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_505_p0 <= tmp_147_fu_3430_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_505_p0 <= tmp_145_fu_3347_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_505_p0 <= tmp_143_fu_3250_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_505_p0 <= tmp_141_fu_3152_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_505_p0 <= tmp_139_fu_3054_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_505_p0 <= tmp_137_fu_2952_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_505_p0 <= tmp_135_fu_2860_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_505_p0 <= tmp_133_fu_2755_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_505_p0 <= tmp_131_fu_2629_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_505_p0 <= tmp_129_fu_2461_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_505_p0 <= tmp_127_fu_2333_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_505_p0 <= tmp_125_fu_2217_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_505_p0 <= tmp_123_fu_2101_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_505_p0 <= tmp_121_fu_1977_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_505_p0 <= tmp_117_fu_1871_p1;
else
grp_fu_505_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_505_p1_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, tmp_16_fu_1843_p1, tmp_22_fu_1949_p1, tmp_26_fu_2073_p1, tmp_30_fu_2189_p1, tmp_34_fu_2305_p1, tmp_38_fu_2425_p1, tmp_42_fu_2601_p1, tmp_46_fu_2727_p1, tmp_50_fu_2833_p1, tmp_54_fu_2924_p1, tmp_58_fu_3026_p1, tmp_62_fu_3128_p1, tmp_66_fu_3226_p1, tmp_70_fu_3324_p1, tmp_74_fu_3407_p1, tmp_78_fu_3490_p1, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_505_p1 <= tmp_78_fu_3490_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_505_p1 <= tmp_74_fu_3407_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_505_p1 <= tmp_70_fu_3324_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_505_p1 <= tmp_66_fu_3226_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_505_p1 <= tmp_62_fu_3128_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_505_p1 <= tmp_58_fu_3026_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_505_p1 <= tmp_54_fu_2924_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_505_p1 <= tmp_50_fu_2833_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_505_p1 <= tmp_46_fu_2727_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_505_p1 <= tmp_42_fu_2601_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_505_p1 <= tmp_38_fu_2425_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_505_p1 <= tmp_34_fu_2305_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_505_p1 <= tmp_30_fu_2189_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_505_p1 <= tmp_26_fu_2073_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_505_p1 <= tmp_22_fu_1949_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_505_p1 <= tmp_16_fu_1843_p1;
else
grp_fu_505_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_509_p0_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, tmp_152_fu_1876_p1, tmp_156_fu_1982_p1, tmp_158_fu_2106_p1, tmp_160_fu_2222_p1, tmp_162_fu_2338_p1, tmp_164_fu_2470_p1, tmp_166_fu_2634_p1, tmp_168_fu_2760_p1, tmp_170_fu_2864_p1, tmp_172_fu_2957_p1, tmp_174_fu_3059_p1, tmp_176_fu_3157_p1, tmp_178_fu_3255_p1, tmp_180_fu_3351_p1, tmp_182_fu_3434_p1, tmp_184_fu_3517_p1, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_509_p0 <= tmp_184_fu_3517_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_509_p0 <= tmp_182_fu_3434_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_509_p0 <= tmp_180_fu_3351_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_509_p0 <= tmp_178_fu_3255_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_509_p0 <= tmp_176_fu_3157_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_509_p0 <= tmp_174_fu_3059_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_509_p0 <= tmp_172_fu_2957_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_509_p0 <= tmp_170_fu_2864_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_509_p0 <= tmp_168_fu_2760_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_509_p0 <= tmp_166_fu_2634_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_509_p0 <= tmp_164_fu_2470_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_509_p0 <= tmp_162_fu_2338_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_509_p0 <= tmp_160_fu_2222_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_509_p0 <= tmp_158_fu_2106_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_509_p0 <= tmp_156_fu_1982_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_509_p0 <= tmp_152_fu_1876_p1;
else
grp_fu_509_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_509_p1_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, tmp_16_fu_1843_p1, tmp_22_fu_1949_p1, tmp_26_fu_2073_p1, tmp_30_fu_2189_p1, tmp_34_fu_2305_p1, tmp_38_fu_2425_p1, tmp_42_fu_2601_p1, tmp_46_fu_2727_p1, tmp_50_fu_2833_p1, tmp_54_fu_2924_p1, tmp_58_fu_3026_p1, tmp_62_fu_3128_p1, tmp_66_fu_3226_p1, tmp_70_fu_3324_p1, tmp_74_fu_3407_p1, tmp_78_fu_3490_p1, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_509_p1 <= tmp_78_fu_3490_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_509_p1 <= tmp_74_fu_3407_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_509_p1 <= tmp_70_fu_3324_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_509_p1 <= tmp_66_fu_3226_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_509_p1 <= tmp_62_fu_3128_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_509_p1 <= tmp_58_fu_3026_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_509_p1 <= tmp_54_fu_2924_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_509_p1 <= tmp_50_fu_2833_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_509_p1 <= tmp_46_fu_2727_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_509_p1 <= tmp_42_fu_2601_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_509_p1 <= tmp_38_fu_2425_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_509_p1 <= tmp_34_fu_2305_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_509_p1 <= tmp_30_fu_2189_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_509_p1 <= tmp_26_fu_2073_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_509_p1 <= tmp_22_fu_1949_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_509_p1 <= tmp_16_fu_1843_p1;
else
grp_fu_509_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_513_p0_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, tmp_187_fu_1881_p1, tmp_191_fu_1987_p1, tmp_193_fu_2111_p1, tmp_195_fu_2227_p1, tmp_197_fu_2343_p1, tmp_199_fu_2479_p1, tmp_201_fu_2639_p1, tmp_203_fu_2765_p1, tmp_205_fu_2868_p1, tmp_207_fu_2962_p1, tmp_209_fu_3064_p1, tmp_211_fu_3162_p1, tmp_213_fu_3260_p1, tmp_215_fu_3355_p1, tmp_217_fu_3438_p1, tmp_219_fu_3521_p1, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_513_p0 <= tmp_219_fu_3521_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_513_p0 <= tmp_217_fu_3438_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_513_p0 <= tmp_215_fu_3355_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_513_p0 <= tmp_213_fu_3260_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_513_p0 <= tmp_211_fu_3162_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_513_p0 <= tmp_209_fu_3064_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_513_p0 <= tmp_207_fu_2962_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_513_p0 <= tmp_205_fu_2868_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_513_p0 <= tmp_203_fu_2765_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_513_p0 <= tmp_201_fu_2639_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_513_p0 <= tmp_199_fu_2479_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_513_p0 <= tmp_197_fu_2343_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_513_p0 <= tmp_195_fu_2227_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_513_p0 <= tmp_193_fu_2111_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_513_p0 <= tmp_191_fu_1987_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_513_p0 <= tmp_187_fu_1881_p1;
else
grp_fu_513_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_513_p1_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, tmp_16_fu_1843_p1, tmp_22_fu_1949_p1, tmp_26_fu_2073_p1, tmp_30_fu_2189_p1, tmp_34_fu_2305_p1, tmp_38_fu_2425_p1, tmp_42_fu_2601_p1, tmp_46_fu_2727_p1, tmp_50_fu_2833_p1, tmp_54_fu_2924_p1, tmp_58_fu_3026_p1, tmp_62_fu_3128_p1, tmp_66_fu_3226_p1, tmp_70_fu_3324_p1, tmp_74_fu_3407_p1, tmp_78_fu_3490_p1, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_513_p1 <= tmp_78_fu_3490_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_513_p1 <= tmp_74_fu_3407_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_513_p1 <= tmp_70_fu_3324_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_513_p1 <= tmp_66_fu_3226_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_513_p1 <= tmp_62_fu_3128_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_513_p1 <= tmp_58_fu_3026_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_513_p1 <= tmp_54_fu_2924_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_513_p1 <= tmp_50_fu_2833_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_513_p1 <= tmp_46_fu_2727_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_513_p1 <= tmp_42_fu_2601_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_513_p1 <= tmp_38_fu_2425_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_513_p1 <= tmp_34_fu_2305_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_513_p1 <= tmp_30_fu_2189_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_513_p1 <= tmp_26_fu_2073_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_513_p1 <= tmp_22_fu_1949_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_513_p1 <= tmp_16_fu_1843_p1;
else
grp_fu_513_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_517_p0_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, tmp_222_fu_1886_p1, tmp_226_fu_1992_p1, tmp_228_fu_2116_p1, tmp_230_fu_2232_p1, tmp_232_fu_2348_p1, tmp_234_fu_2488_p1, tmp_236_fu_2644_p1, tmp_238_fu_2770_p1, tmp_240_fu_2872_p1, tmp_242_fu_2967_p1, tmp_244_fu_3069_p1, tmp_246_fu_3167_p1, tmp_248_fu_3265_p1, tmp_250_fu_3359_p1, tmp_252_fu_3442_p1, tmp_254_fu_3525_p1, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_517_p0 <= tmp_254_fu_3525_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_517_p0 <= tmp_252_fu_3442_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_517_p0 <= tmp_250_fu_3359_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_517_p0 <= tmp_248_fu_3265_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_517_p0 <= tmp_246_fu_3167_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_517_p0 <= tmp_244_fu_3069_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_517_p0 <= tmp_242_fu_2967_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_517_p0 <= tmp_240_fu_2872_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_517_p0 <= tmp_238_fu_2770_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_517_p0 <= tmp_236_fu_2644_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_517_p0 <= tmp_234_fu_2488_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_517_p0 <= tmp_232_fu_2348_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_517_p0 <= tmp_230_fu_2232_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_517_p0 <= tmp_228_fu_2116_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_517_p0 <= tmp_226_fu_1992_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_517_p0 <= tmp_222_fu_1886_p1;
else
grp_fu_517_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_517_p1_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, tmp_16_fu_1843_p1, tmp_22_fu_1949_p1, tmp_26_fu_2073_p1, tmp_30_fu_2189_p1, tmp_34_fu_2305_p1, tmp_38_fu_2425_p1, tmp_42_fu_2601_p1, tmp_46_fu_2727_p1, tmp_50_fu_2833_p1, tmp_54_fu_2924_p1, tmp_58_fu_3026_p1, tmp_62_fu_3128_p1, tmp_66_fu_3226_p1, tmp_70_fu_3324_p1, tmp_74_fu_3407_p1, tmp_78_fu_3490_p1, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_517_p1 <= tmp_78_fu_3490_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_517_p1 <= tmp_74_fu_3407_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_517_p1 <= tmp_70_fu_3324_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_517_p1 <= tmp_66_fu_3226_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_517_p1 <= tmp_62_fu_3128_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_517_p1 <= tmp_58_fu_3026_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_517_p1 <= tmp_54_fu_2924_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_517_p1 <= tmp_50_fu_2833_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_517_p1 <= tmp_46_fu_2727_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_517_p1 <= tmp_42_fu_2601_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_517_p1 <= tmp_38_fu_2425_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_517_p1 <= tmp_34_fu_2305_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_517_p1 <= tmp_30_fu_2189_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_517_p1 <= tmp_26_fu_2073_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_517_p1 <= tmp_22_fu_1949_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_517_p1 <= tmp_16_fu_1843_p1;
else
grp_fu_517_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_521_p0_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, tmp_257_fu_1891_p1, tmp_261_fu_1997_p1, tmp_263_fu_2121_p1, tmp_265_fu_2237_p1, tmp_267_fu_2353_p1, tmp_269_fu_2497_p1, tmp_271_fu_2649_p1, tmp_273_fu_2775_p1, tmp_275_fu_2876_p1, tmp_277_fu_2972_p1, tmp_279_fu_3074_p1, tmp_281_fu_3172_p1, tmp_283_fu_3270_p1, tmp_285_fu_3363_p1, tmp_287_fu_3446_p1, tmp_289_fu_3529_p1, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_521_p0 <= tmp_289_fu_3529_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_521_p0 <= tmp_287_fu_3446_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_521_p0 <= tmp_285_fu_3363_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_521_p0 <= tmp_283_fu_3270_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_521_p0 <= tmp_281_fu_3172_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_521_p0 <= tmp_279_fu_3074_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_521_p0 <= tmp_277_fu_2972_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_521_p0 <= tmp_275_fu_2876_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_521_p0 <= tmp_273_fu_2775_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_521_p0 <= tmp_271_fu_2649_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_521_p0 <= tmp_269_fu_2497_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_521_p0 <= tmp_267_fu_2353_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_521_p0 <= tmp_265_fu_2237_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_521_p0 <= tmp_263_fu_2121_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_521_p0 <= tmp_261_fu_1997_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_521_p0 <= tmp_257_fu_1891_p1;
else
grp_fu_521_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_521_p1_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, tmp_16_fu_1843_p1, tmp_22_fu_1949_p1, tmp_26_fu_2073_p1, tmp_30_fu_2189_p1, tmp_34_fu_2305_p1, tmp_38_fu_2425_p1, tmp_42_fu_2601_p1, tmp_46_fu_2727_p1, tmp_50_fu_2833_p1, tmp_54_fu_2924_p1, tmp_58_fu_3026_p1, tmp_62_fu_3128_p1, tmp_66_fu_3226_p1, tmp_70_fu_3324_p1, tmp_74_fu_3407_p1, tmp_78_fu_3490_p1, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_521_p1 <= tmp_78_fu_3490_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_521_p1 <= tmp_74_fu_3407_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_521_p1 <= tmp_70_fu_3324_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_521_p1 <= tmp_66_fu_3226_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_521_p1 <= tmp_62_fu_3128_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_521_p1 <= tmp_58_fu_3026_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_521_p1 <= tmp_54_fu_2924_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_521_p1 <= tmp_50_fu_2833_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_521_p1 <= tmp_46_fu_2727_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_521_p1 <= tmp_42_fu_2601_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_521_p1 <= tmp_38_fu_2425_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_521_p1 <= tmp_34_fu_2305_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_521_p1 <= tmp_30_fu_2189_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_521_p1 <= tmp_26_fu_2073_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_521_p1 <= tmp_22_fu_1949_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_521_p1 <= tmp_16_fu_1843_p1;
else
grp_fu_521_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_525_p0_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, tmp_292_fu_1896_p1, tmp_296_fu_2002_p1, tmp_298_fu_2126_p1, tmp_300_fu_2242_p1, tmp_302_fu_2358_p1, tmp_304_fu_2506_p1, tmp_306_fu_2654_p1, tmp_308_fu_2780_p1, tmp_310_fu_2880_p1, tmp_312_fu_2977_p1, tmp_314_fu_3079_p1, tmp_316_fu_3177_p1, tmp_318_fu_3275_p1, tmp_320_fu_3367_p1, tmp_322_fu_3450_p1, tmp_324_fu_3533_p1, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_525_p0 <= tmp_324_fu_3533_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_525_p0 <= tmp_322_fu_3450_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_525_p0 <= tmp_320_fu_3367_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_525_p0 <= tmp_318_fu_3275_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_525_p0 <= tmp_316_fu_3177_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_525_p0 <= tmp_314_fu_3079_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_525_p0 <= tmp_312_fu_2977_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_525_p0 <= tmp_310_fu_2880_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_525_p0 <= tmp_308_fu_2780_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_525_p0 <= tmp_306_fu_2654_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_525_p0 <= tmp_304_fu_2506_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_525_p0 <= tmp_302_fu_2358_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_525_p0 <= tmp_300_fu_2242_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_525_p0 <= tmp_298_fu_2126_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_525_p0 <= tmp_296_fu_2002_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_525_p0 <= tmp_292_fu_1896_p1;
else
grp_fu_525_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_525_p1_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, tmp_16_fu_1843_p1, tmp_22_fu_1949_p1, tmp_26_fu_2073_p1, tmp_30_fu_2189_p1, tmp_34_fu_2305_p1, tmp_38_fu_2425_p1, tmp_42_fu_2601_p1, tmp_46_fu_2727_p1, tmp_50_fu_2833_p1, tmp_54_fu_2924_p1, tmp_58_fu_3026_p1, tmp_62_fu_3128_p1, tmp_66_fu_3226_p1, tmp_70_fu_3324_p1, tmp_74_fu_3407_p1, tmp_78_fu_3490_p1, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_525_p1 <= tmp_78_fu_3490_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_525_p1 <= tmp_74_fu_3407_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_525_p1 <= tmp_70_fu_3324_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_525_p1 <= tmp_66_fu_3226_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_525_p1 <= tmp_62_fu_3128_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_525_p1 <= tmp_58_fu_3026_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_525_p1 <= tmp_54_fu_2924_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_525_p1 <= tmp_50_fu_2833_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_525_p1 <= tmp_46_fu_2727_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_525_p1 <= tmp_42_fu_2601_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_525_p1 <= tmp_38_fu_2425_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_525_p1 <= tmp_34_fu_2305_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_525_p1 <= tmp_30_fu_2189_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_525_p1 <= tmp_26_fu_2073_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_525_p1 <= tmp_22_fu_1949_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_525_p1 <= tmp_16_fu_1843_p1;
else
grp_fu_525_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_529_p0_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, tmp_327_fu_1901_p1, tmp_331_fu_2007_p1, tmp_333_fu_2131_p1, tmp_335_fu_2247_p1, tmp_337_fu_2363_p1, tmp_339_fu_2515_p1, tmp_341_fu_2659_p1, tmp_343_fu_2785_p1, tmp_345_fu_2884_p1, tmp_347_fu_2982_p1, tmp_349_fu_3084_p1, tmp_351_fu_3182_p1, tmp_353_fu_3280_p1, tmp_355_fu_3371_p1, tmp_357_fu_3454_p1, tmp_359_fu_3537_p1, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_529_p0 <= tmp_359_fu_3537_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_529_p0 <= tmp_357_fu_3454_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_529_p0 <= tmp_355_fu_3371_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_529_p0 <= tmp_353_fu_3280_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_529_p0 <= tmp_351_fu_3182_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_529_p0 <= tmp_349_fu_3084_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_529_p0 <= tmp_347_fu_2982_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_529_p0 <= tmp_345_fu_2884_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_529_p0 <= tmp_343_fu_2785_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_529_p0 <= tmp_341_fu_2659_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_529_p0 <= tmp_339_fu_2515_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_529_p0 <= tmp_337_fu_2363_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_529_p0 <= tmp_335_fu_2247_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_529_p0 <= tmp_333_fu_2131_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_529_p0 <= tmp_331_fu_2007_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_529_p0 <= tmp_327_fu_1901_p1;
else
grp_fu_529_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_529_p1_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, tmp_16_fu_1843_p1, tmp_22_fu_1949_p1, tmp_26_fu_2073_p1, tmp_30_fu_2189_p1, tmp_34_fu_2305_p1, tmp_38_fu_2425_p1, tmp_42_fu_2601_p1, tmp_46_fu_2727_p1, tmp_50_fu_2833_p1, tmp_54_fu_2924_p1, tmp_58_fu_3026_p1, tmp_62_fu_3128_p1, tmp_66_fu_3226_p1, tmp_70_fu_3324_p1, tmp_74_fu_3407_p1, tmp_78_fu_3490_p1, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_529_p1 <= tmp_78_fu_3490_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_529_p1 <= tmp_74_fu_3407_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_529_p1 <= tmp_70_fu_3324_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_529_p1 <= tmp_66_fu_3226_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_529_p1 <= tmp_62_fu_3128_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_529_p1 <= tmp_58_fu_3026_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_529_p1 <= tmp_54_fu_2924_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_529_p1 <= tmp_50_fu_2833_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_529_p1 <= tmp_46_fu_2727_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_529_p1 <= tmp_42_fu_2601_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_529_p1 <= tmp_38_fu_2425_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_529_p1 <= tmp_34_fu_2305_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_529_p1 <= tmp_30_fu_2189_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_529_p1 <= tmp_26_fu_2073_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_529_p1 <= tmp_22_fu_1949_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_529_p1 <= tmp_16_fu_1843_p1;
else
grp_fu_529_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_533_p0_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, tmp_362_fu_1906_p1, tmp_366_fu_2012_p1, tmp_368_fu_2136_p1, tmp_370_fu_2252_p1, tmp_372_fu_2368_p1, tmp_374_fu_2524_p1, tmp_376_fu_2664_p1, tmp_378_fu_2790_p1, tmp_380_fu_2888_p1, tmp_382_fu_2987_p1, tmp_384_fu_3089_p1, tmp_386_fu_3187_p1, tmp_388_fu_3285_p1, tmp_390_fu_3375_p1, tmp_392_fu_3458_p1, tmp_394_fu_3541_p1, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_533_p0 <= tmp_394_fu_3541_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_533_p0 <= tmp_392_fu_3458_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_533_p0 <= tmp_390_fu_3375_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_533_p0 <= tmp_388_fu_3285_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_533_p0 <= tmp_386_fu_3187_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_533_p0 <= tmp_384_fu_3089_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_533_p0 <= tmp_382_fu_2987_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_533_p0 <= tmp_380_fu_2888_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_533_p0 <= tmp_378_fu_2790_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_533_p0 <= tmp_376_fu_2664_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_533_p0 <= tmp_374_fu_2524_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_533_p0 <= tmp_372_fu_2368_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_533_p0 <= tmp_370_fu_2252_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_533_p0 <= tmp_368_fu_2136_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_533_p0 <= tmp_366_fu_2012_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_533_p0 <= tmp_362_fu_1906_p1;
else
grp_fu_533_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_533_p1_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, tmp_16_fu_1843_p1, tmp_22_fu_1949_p1, tmp_26_fu_2073_p1, tmp_30_fu_2189_p1, tmp_34_fu_2305_p1, tmp_38_fu_2425_p1, tmp_42_fu_2601_p1, tmp_46_fu_2727_p1, tmp_50_fu_2833_p1, tmp_54_fu_2924_p1, tmp_58_fu_3026_p1, tmp_62_fu_3128_p1, tmp_66_fu_3226_p1, tmp_70_fu_3324_p1, tmp_74_fu_3407_p1, tmp_78_fu_3490_p1, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_533_p1 <= tmp_78_fu_3490_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_533_p1 <= tmp_74_fu_3407_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_533_p1 <= tmp_70_fu_3324_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_533_p1 <= tmp_66_fu_3226_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_533_p1 <= tmp_62_fu_3128_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_533_p1 <= tmp_58_fu_3026_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_533_p1 <= tmp_54_fu_2924_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_533_p1 <= tmp_50_fu_2833_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_533_p1 <= tmp_46_fu_2727_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_533_p1 <= tmp_42_fu_2601_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_533_p1 <= tmp_38_fu_2425_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_533_p1 <= tmp_34_fu_2305_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_533_p1 <= tmp_30_fu_2189_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_533_p1 <= tmp_26_fu_2073_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_533_p1 <= tmp_22_fu_1949_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_533_p1 <= tmp_16_fu_1843_p1;
else
grp_fu_533_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_537_p0_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, tmp_397_fu_1911_p1, tmp_401_fu_2017_p1, tmp_403_fu_2141_p1, tmp_405_fu_2257_p1, tmp_407_fu_2373_p1, tmp_409_fu_2533_p1, tmp_411_fu_2669_p1, tmp_413_fu_2795_p1, tmp_415_fu_2892_p1, tmp_417_fu_2992_p1, tmp_419_fu_3094_p1, tmp_421_fu_3192_p1, tmp_423_fu_3290_p1, tmp_425_fu_3379_p1, tmp_427_fu_3462_p1, tmp_429_fu_3545_p1, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_537_p0 <= tmp_429_fu_3545_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_537_p0 <= tmp_427_fu_3462_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_537_p0 <= tmp_425_fu_3379_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_537_p0 <= tmp_423_fu_3290_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_537_p0 <= tmp_421_fu_3192_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_537_p0 <= tmp_419_fu_3094_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_537_p0 <= tmp_417_fu_2992_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_537_p0 <= tmp_415_fu_2892_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_537_p0 <= tmp_413_fu_2795_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_537_p0 <= tmp_411_fu_2669_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_537_p0 <= tmp_409_fu_2533_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_537_p0 <= tmp_407_fu_2373_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_537_p0 <= tmp_405_fu_2257_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_537_p0 <= tmp_403_fu_2141_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_537_p0 <= tmp_401_fu_2017_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_537_p0 <= tmp_397_fu_1911_p1;
else
grp_fu_537_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_537_p1_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, tmp_16_fu_1843_p1, tmp_22_fu_1949_p1, tmp_26_fu_2073_p1, tmp_30_fu_2189_p1, tmp_34_fu_2305_p1, tmp_38_fu_2425_p1, tmp_42_fu_2601_p1, tmp_46_fu_2727_p1, tmp_50_fu_2833_p1, tmp_54_fu_2924_p1, tmp_58_fu_3026_p1, tmp_62_fu_3128_p1, tmp_66_fu_3226_p1, tmp_70_fu_3324_p1, tmp_74_fu_3407_p1, tmp_78_fu_3490_p1, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_537_p1 <= tmp_78_fu_3490_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_537_p1 <= tmp_74_fu_3407_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_537_p1 <= tmp_70_fu_3324_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_537_p1 <= tmp_66_fu_3226_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_537_p1 <= tmp_62_fu_3128_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_537_p1 <= tmp_58_fu_3026_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_537_p1 <= tmp_54_fu_2924_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_537_p1 <= tmp_50_fu_2833_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_537_p1 <= tmp_46_fu_2727_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_537_p1 <= tmp_42_fu_2601_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_537_p1 <= tmp_38_fu_2425_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_537_p1 <= tmp_34_fu_2305_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_537_p1 <= tmp_30_fu_2189_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_537_p1 <= tmp_26_fu_2073_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_537_p1 <= tmp_22_fu_1949_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_537_p1 <= tmp_16_fu_1843_p1;
else
grp_fu_537_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_541_p0_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, tmp_432_fu_1916_p1, tmp_436_fu_2022_p1, tmp_438_fu_2146_p1, tmp_440_fu_2262_p1, tmp_442_fu_2378_p1, tmp_444_fu_2542_p1, tmp_446_fu_2674_p1, tmp_448_fu_2800_p1, tmp_450_fu_2896_p1, tmp_452_fu_2997_p1, tmp_454_fu_3099_p1, tmp_456_fu_3197_p1, tmp_458_fu_3295_p1, tmp_460_fu_3383_p1, tmp_462_fu_3466_p1, tmp_464_fu_3549_p1, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_541_p0 <= tmp_464_fu_3549_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_541_p0 <= tmp_462_fu_3466_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_541_p0 <= tmp_460_fu_3383_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_541_p0 <= tmp_458_fu_3295_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_541_p0 <= tmp_456_fu_3197_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_541_p0 <= tmp_454_fu_3099_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_541_p0 <= tmp_452_fu_2997_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_541_p0 <= tmp_450_fu_2896_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_541_p0 <= tmp_448_fu_2800_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_541_p0 <= tmp_446_fu_2674_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_541_p0 <= tmp_444_fu_2542_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_541_p0 <= tmp_442_fu_2378_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_541_p0 <= tmp_440_fu_2262_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_541_p0 <= tmp_438_fu_2146_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_541_p0 <= tmp_436_fu_2022_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_541_p0 <= tmp_432_fu_1916_p1;
else
grp_fu_541_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_541_p1_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, tmp_16_fu_1843_p1, tmp_22_fu_1949_p1, tmp_26_fu_2073_p1, tmp_30_fu_2189_p1, tmp_34_fu_2305_p1, tmp_38_fu_2425_p1, tmp_42_fu_2601_p1, tmp_46_fu_2727_p1, tmp_50_fu_2833_p1, tmp_54_fu_2924_p1, tmp_58_fu_3026_p1, tmp_62_fu_3128_p1, tmp_66_fu_3226_p1, tmp_70_fu_3324_p1, tmp_74_fu_3407_p1, tmp_78_fu_3490_p1, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_541_p1 <= tmp_78_fu_3490_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_541_p1 <= tmp_74_fu_3407_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_541_p1 <= tmp_70_fu_3324_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_541_p1 <= tmp_66_fu_3226_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_541_p1 <= tmp_62_fu_3128_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_541_p1 <= tmp_58_fu_3026_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_541_p1 <= tmp_54_fu_2924_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_541_p1 <= tmp_50_fu_2833_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_541_p1 <= tmp_46_fu_2727_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_541_p1 <= tmp_42_fu_2601_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_541_p1 <= tmp_38_fu_2425_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_541_p1 <= tmp_34_fu_2305_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_541_p1 <= tmp_30_fu_2189_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_541_p1 <= tmp_26_fu_2073_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_541_p1 <= tmp_22_fu_1949_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_541_p1 <= tmp_16_fu_1843_p1;
else
grp_fu_541_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_545_p0_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, tmp_467_fu_1921_p1, tmp_471_fu_2027_p1, tmp_473_fu_2151_p1, tmp_475_fu_2267_p1, tmp_477_fu_2383_p1, tmp_479_fu_2551_p1, tmp_481_fu_2679_p1, tmp_483_fu_2805_p1, tmp_485_fu_2900_p1, tmp_487_fu_3002_p1, tmp_489_fu_3104_p1, tmp_491_fu_3202_p1, tmp_493_fu_3300_p1, tmp_495_fu_3387_p1, tmp_497_fu_3470_p1, tmp_499_fu_3553_p1, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_545_p0 <= tmp_499_fu_3553_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_545_p0 <= tmp_497_fu_3470_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_545_p0 <= tmp_495_fu_3387_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_545_p0 <= tmp_493_fu_3300_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_545_p0 <= tmp_491_fu_3202_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_545_p0 <= tmp_489_fu_3104_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_545_p0 <= tmp_487_fu_3002_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_545_p0 <= tmp_485_fu_2900_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_545_p0 <= tmp_483_fu_2805_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_545_p0 <= tmp_481_fu_2679_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_545_p0 <= tmp_479_fu_2551_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_545_p0 <= tmp_477_fu_2383_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_545_p0 <= tmp_475_fu_2267_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_545_p0 <= tmp_473_fu_2151_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_545_p0 <= tmp_471_fu_2027_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_545_p0 <= tmp_467_fu_1921_p1;
else
grp_fu_545_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_545_p1_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, tmp_16_fu_1843_p1, tmp_22_fu_1949_p1, tmp_26_fu_2073_p1, tmp_30_fu_2189_p1, tmp_34_fu_2305_p1, tmp_38_fu_2425_p1, tmp_42_fu_2601_p1, tmp_46_fu_2727_p1, tmp_50_fu_2833_p1, tmp_54_fu_2924_p1, tmp_58_fu_3026_p1, tmp_62_fu_3128_p1, tmp_66_fu_3226_p1, tmp_70_fu_3324_p1, tmp_74_fu_3407_p1, tmp_78_fu_3490_p1, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_545_p1 <= tmp_78_fu_3490_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_545_p1 <= tmp_74_fu_3407_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_545_p1 <= tmp_70_fu_3324_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_545_p1 <= tmp_66_fu_3226_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_545_p1 <= tmp_62_fu_3128_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_545_p1 <= tmp_58_fu_3026_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_545_p1 <= tmp_54_fu_2924_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_545_p1 <= tmp_50_fu_2833_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_545_p1 <= tmp_46_fu_2727_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_545_p1 <= tmp_42_fu_2601_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_545_p1 <= tmp_38_fu_2425_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_545_p1 <= tmp_34_fu_2305_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_545_p1 <= tmp_30_fu_2189_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_545_p1 <= tmp_26_fu_2073_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_545_p1 <= tmp_22_fu_1949_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_545_p1 <= tmp_16_fu_1843_p1;
else
grp_fu_545_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_549_p0_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, tmp_502_fu_1926_p1, tmp_506_fu_2032_p1, tmp_508_fu_2156_p1, tmp_510_fu_2272_p1, tmp_512_fu_2388_p1, tmp_514_fu_2560_p1, tmp_516_fu_2684_p1, tmp_518_fu_2810_p1, tmp_520_fu_2904_p1, tmp_522_fu_3007_p1, tmp_524_fu_3109_p1, tmp_526_fu_3207_p1, tmp_528_fu_3305_p1, tmp_530_fu_3391_p1, tmp_532_fu_3474_p1, tmp_534_fu_3557_p1, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_549_p0 <= tmp_534_fu_3557_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_549_p0 <= tmp_532_fu_3474_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_549_p0 <= tmp_530_fu_3391_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_549_p0 <= tmp_528_fu_3305_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_549_p0 <= tmp_526_fu_3207_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_549_p0 <= tmp_524_fu_3109_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_549_p0 <= tmp_522_fu_3007_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_549_p0 <= tmp_520_fu_2904_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_549_p0 <= tmp_518_fu_2810_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_549_p0 <= tmp_516_fu_2684_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_549_p0 <= tmp_514_fu_2560_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_549_p0 <= tmp_512_fu_2388_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_549_p0 <= tmp_510_fu_2272_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_549_p0 <= tmp_508_fu_2156_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_549_p0 <= tmp_506_fu_2032_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_549_p0 <= tmp_502_fu_1926_p1;
else
grp_fu_549_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_549_p1_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, tmp_16_fu_1843_p1, tmp_22_fu_1949_p1, tmp_26_fu_2073_p1, tmp_30_fu_2189_p1, tmp_34_fu_2305_p1, tmp_38_fu_2425_p1, tmp_42_fu_2601_p1, tmp_46_fu_2727_p1, tmp_50_fu_2833_p1, tmp_54_fu_2924_p1, tmp_58_fu_3026_p1, tmp_62_fu_3128_p1, tmp_66_fu_3226_p1, tmp_70_fu_3324_p1, tmp_74_fu_3407_p1, tmp_78_fu_3490_p1, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_549_p1 <= tmp_78_fu_3490_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_549_p1 <= tmp_74_fu_3407_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_549_p1 <= tmp_70_fu_3324_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_549_p1 <= tmp_66_fu_3226_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_549_p1 <= tmp_62_fu_3128_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_549_p1 <= tmp_58_fu_3026_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_549_p1 <= tmp_54_fu_2924_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_549_p1 <= tmp_50_fu_2833_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_549_p1 <= tmp_46_fu_2727_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_549_p1 <= tmp_42_fu_2601_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_549_p1 <= tmp_38_fu_2425_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_549_p1 <= tmp_34_fu_2305_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_549_p1 <= tmp_30_fu_2189_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_549_p1 <= tmp_26_fu_2073_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_549_p1 <= tmp_22_fu_1949_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_549_p1 <= tmp_16_fu_1843_p1;
else
grp_fu_549_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_553_p0_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, tmp_537_fu_1931_p1, tmp_541_fu_2037_p1, tmp_543_fu_2161_p1, tmp_545_fu_2277_p1, tmp_547_fu_2393_p1, tmp_549_fu_2569_p1, tmp_551_fu_2689_p1, tmp_553_fu_2815_p1, tmp_555_fu_2908_p1, tmp_557_fu_3012_p1, tmp_559_fu_3114_p1, tmp_561_fu_3212_p1, tmp_563_fu_3310_p1, tmp_565_fu_3395_p1, tmp_567_fu_3478_p1, tmp_569_fu_3561_p1, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_553_p0 <= tmp_569_fu_3561_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_553_p0 <= tmp_567_fu_3478_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_553_p0 <= tmp_565_fu_3395_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_553_p0 <= tmp_563_fu_3310_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_553_p0 <= tmp_561_fu_3212_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_553_p0 <= tmp_559_fu_3114_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_553_p0 <= tmp_557_fu_3012_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_553_p0 <= tmp_555_fu_2908_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_553_p0 <= tmp_553_fu_2815_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_553_p0 <= tmp_551_fu_2689_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_553_p0 <= tmp_549_fu_2569_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_553_p0 <= tmp_547_fu_2393_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_553_p0 <= tmp_545_fu_2277_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_553_p0 <= tmp_543_fu_2161_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_553_p0 <= tmp_541_fu_2037_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_553_p0 <= tmp_537_fu_1931_p1;
else
grp_fu_553_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_553_p1_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, tmp_16_fu_1843_p1, tmp_22_fu_1949_p1, tmp_26_fu_2073_p1, tmp_30_fu_2189_p1, tmp_34_fu_2305_p1, tmp_38_fu_2425_p1, tmp_42_fu_2601_p1, tmp_46_fu_2727_p1, tmp_50_fu_2833_p1, tmp_54_fu_2924_p1, tmp_58_fu_3026_p1, tmp_62_fu_3128_p1, tmp_66_fu_3226_p1, tmp_70_fu_3324_p1, tmp_74_fu_3407_p1, tmp_78_fu_3490_p1, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_553_p1 <= tmp_78_fu_3490_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_553_p1 <= tmp_74_fu_3407_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_553_p1 <= tmp_70_fu_3324_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_553_p1 <= tmp_66_fu_3226_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_553_p1 <= tmp_62_fu_3128_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_553_p1 <= tmp_58_fu_3026_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_553_p1 <= tmp_54_fu_2924_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_553_p1 <= tmp_50_fu_2833_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_553_p1 <= tmp_46_fu_2727_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_553_p1 <= tmp_42_fu_2601_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_553_p1 <= tmp_38_fu_2425_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_553_p1 <= tmp_34_fu_2305_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_553_p1 <= tmp_30_fu_2189_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_553_p1 <= tmp_26_fu_2073_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_553_p1 <= tmp_22_fu_1949_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_553_p1 <= tmp_16_fu_1843_p1;
else
grp_fu_553_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_557_p0_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, tmp_572_fu_1936_p1, tmp_576_fu_2042_p1, tmp_578_fu_2166_p1, tmp_580_fu_2282_p1, tmp_582_fu_2398_p1, tmp_584_fu_2578_p1, tmp_586_fu_2694_p1, tmp_588_fu_2820_p1, tmp_590_fu_2912_p1, tmp_592_fu_3017_p1, tmp_594_fu_3119_p1, tmp_596_fu_3217_p1, tmp_598_fu_3315_p1, tmp_600_fu_3399_p1, tmp_602_fu_3482_p1, tmp_604_fu_3565_p1, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_557_p0 <= tmp_604_fu_3565_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_557_p0 <= tmp_602_fu_3482_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_557_p0 <= tmp_600_fu_3399_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_557_p0 <= tmp_598_fu_3315_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_557_p0 <= tmp_596_fu_3217_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_557_p0 <= tmp_594_fu_3119_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_557_p0 <= tmp_592_fu_3017_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_557_p0 <= tmp_590_fu_2912_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_557_p0 <= tmp_588_fu_2820_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_557_p0 <= tmp_586_fu_2694_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_557_p0 <= tmp_584_fu_2578_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_557_p0 <= tmp_582_fu_2398_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_557_p0 <= tmp_580_fu_2282_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_557_p0 <= tmp_578_fu_2166_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_557_p0 <= tmp_576_fu_2042_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_557_p0 <= tmp_572_fu_1936_p1;
else
grp_fu_557_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_557_p1_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, tmp_16_fu_1843_p1, tmp_22_fu_1949_p1, tmp_26_fu_2073_p1, tmp_30_fu_2189_p1, tmp_34_fu_2305_p1, tmp_38_fu_2425_p1, tmp_42_fu_2601_p1, tmp_46_fu_2727_p1, tmp_50_fu_2833_p1, tmp_54_fu_2924_p1, tmp_58_fu_3026_p1, tmp_62_fu_3128_p1, tmp_66_fu_3226_p1, tmp_70_fu_3324_p1, tmp_74_fu_3407_p1, tmp_78_fu_3490_p1, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_557_p1 <= tmp_78_fu_3490_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_557_p1 <= tmp_74_fu_3407_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_557_p1 <= tmp_70_fu_3324_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_557_p1 <= tmp_66_fu_3226_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_557_p1 <= tmp_62_fu_3128_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_557_p1 <= tmp_58_fu_3026_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_557_p1 <= tmp_54_fu_2924_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_557_p1 <= tmp_50_fu_2833_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_557_p1 <= tmp_46_fu_2727_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_557_p1 <= tmp_42_fu_2601_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_557_p1 <= tmp_38_fu_2425_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_557_p1 <= tmp_34_fu_2305_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_557_p1 <= tmp_30_fu_2189_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_557_p1 <= tmp_26_fu_2073_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_557_p1 <= tmp_22_fu_1949_p1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_557_p1 <= tmp_16_fu_1843_p1;
else
grp_fu_557_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
i_1_fu_1087_p2 <= std_logic_vector(unsigned(ap_const_lv3_1) + unsigned(i_reg_362));
i_phi_fu_366_p4_assign_proc : process(i_reg_362, exitcond_flatten2_reg_3675, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, tmp_1_mid2_v_reg_3722, ap_block_pp0_stage0_flag00000000)
begin
if (((exitcond_flatten2_reg_3675 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
i_phi_fu_366_p4 <= tmp_1_mid2_v_reg_3722;
else
i_phi_fu_366_p4 <= i_reg_362;
end if;
end process;
indvar_flatten1_phi_fu_355_p4_assign_proc : process(indvar_flatten1_reg_351, exitcond_flatten2_reg_3675, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, indvar_flatten_next2_reg_3679, ap_block_pp0_stage0_flag00000000)
begin
if (((exitcond_flatten2_reg_3675 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
indvar_flatten1_phi_fu_355_p4 <= indvar_flatten_next2_reg_3679;
else
indvar_flatten1_phi_fu_355_p4 <= indvar_flatten1_reg_351;
end if;
end process;
indvar_flatten2_phi_fu_378_p4_assign_proc : process(indvar_flatten2_reg_374, exitcond_flatten2_reg_3675, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, indvar_flatten_next1_reg_3757, ap_block_pp0_stage0_flag00000000)
begin
if (((exitcond_flatten2_reg_3675 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
indvar_flatten2_phi_fu_378_p4 <= indvar_flatten_next1_reg_3757;
else
indvar_flatten2_phi_fu_378_p4 <= indvar_flatten2_reg_374;
end if;
end process;
indvar_flatten40_op_fu_1081_p2 <= std_logic_vector(unsigned(ap_const_lv12_1) + unsigned(indvar_flatten2_phi_fu_378_p4));
indvar_flatten_next1_fu_1150_p3 <=
ap_const_lv12_1 when (exitcond_flatten_reg_3684(0) = '1') else
indvar_flatten40_op_reg_3707;
indvar_flatten_next2_fu_1057_p2 <= std_logic_vector(unsigned(ap_const_lv13_1) + unsigned(indvar_flatten1_phi_fu_355_p4));
indvar_flatten_next_fu_1258_p3 <=
ap_const_lv10_1 when (tmp_39_fu_1207_p2(0) = '1') else
indvar_flatten_op_reg_3752;
indvar_flatten_op_fu_1144_p2 <= std_logic_vector(unsigned(ap_const_lv10_1) + unsigned(indvar_flatten_reg_397));
indvar_flatten_phi_fu_401_p4_assign_proc : process(indvar_flatten_reg_397, exitcond_flatten2_reg_3675, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, indvar_flatten_next_reg_3809, ap_block_pp0_stage0_flag00000000)
begin
if (((exitcond_flatten2_reg_3675 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
indvar_flatten_phi_fu_401_p4 <= indvar_flatten_next_reg_3809;
else
indvar_flatten_phi_fu_401_p4 <= indvar_flatten_reg_397;
end if;
end process;
j_1_fu_1122_p2 <= std_logic_vector(unsigned(ap_const_lv3_1) + unsigned(j_mid_fu_1093_p3));
j_mid_fu_1093_p3 <=
ap_const_lv3_0 when (exitcond_flatten_reg_3684(0) = '1') else
j_phi_fu_389_p4;
j_phi_fu_389_p4_assign_proc : process(j_reg_385, ap_enable_reg_pp0_iter1, ap_reg_pp0_iter1_exitcond_flatten2_reg_3675, ap_CS_fsm_pp0_stage1, tmp_4_mid2_reg_3783, ap_block_pp0_stage1_flag00000000)
begin
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_lv1_0 = ap_reg_pp0_iter1_exitcond_flatten2_reg_3675) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
j_phi_fu_389_p4 <= tmp_4_mid2_reg_3783;
else
j_phi_fu_389_p4 <= j_reg_385;
end if;
end process;
not_exitcond_flatten_1_fu_1133_p2 <= (exitcond_flatten_reg_3684 or exitcond_flatten_not_fu_1128_p2);
not_exitcond_flatten_fu_1107_p2 <= (exitcond_flatten_reg_3684 xor ap_const_lv1_1);
p_shl2_cast_fu_1436_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_620_fu_1429_p3),12));
p_shl3_cast_fu_1183_p4 <= ((ap_const_lv5_5 & tmp_1_mid2_v_reg_3722) & ap_const_lv2_0);
p_shl4_cast_fu_1166_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_1_fu_1159_p3),6));
p_shl_cast_fu_1425_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_619_fu_1418_p3),12));
p_v_fu_1303_p3 <=
row_b_1_reg_3834 when (tmp_9_mid1_reg_3744(0) = '1') else
row_b_mid_reg_3776;
row_b_1_fu_1282_p2 <= std_logic_vector(unsigned(ap_const_lv5_1) + unsigned(row_b_mid_reg_3776));
row_b_mid2_fu_1334_p3 <=
row_b_1_reg_3834 when (tmp_9_mid1_reg_3744(0) = '1') else
row_b_mid_reg_3776;
row_b_mid_fu_1211_p3 <=
ap_const_lv5_0 when (tmp_39_fu_1207_p2(0) = '1') else
row_b_reg_409;
row_b_phi_fu_413_p4_assign_proc : process(row_b_reg_409, exitcond_flatten2_reg_3675, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, row_b_mid2_reg_3862, ap_block_pp0_stage0_flag00000000)
begin
if (((exitcond_flatten2_reg_3675 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
row_b_phi_fu_413_p4 <= row_b_mid2_reg_3862;
else
row_b_phi_fu_413_p4 <= row_b_reg_409;
end if;
end process;
tmp_101_fu_2947_p1 <= reg_711;
tmp_103_fu_3049_p1 <= reg_771;
tmp_105_fu_3147_p1 <= reg_831;
tmp_107_fu_3245_p1 <= reg_891;
tmp_109_fu_3343_p1 <= tmp_108_reg_5607;
tmp_10_fu_1820_p2 <= std_logic_vector(signed(ap_const_lv8_AF) + signed(tmp_2_cast2_reg_4083));
tmp_111_fu_3426_p1 <= tmp_110_reg_5872;
tmp_113_fu_3509_p1 <= tmp_112_reg_6132;
tmp_114_fu_3573_p1 <= reg_956;
tmp_117_fu_1871_p1 <= reg_715;
tmp_119_fu_2457_p1 <= tmp_118_reg_4013;
tmp_11_fu_1192_p2 <= std_logic_vector(unsigned(p_shl3_cast_fu_1183_p4) + unsigned(tmp_611_cast_fu_1176_p3));
tmp_121_fu_1977_p1 <= reg_775;
tmp_123_fu_2101_p1 <= reg_835;
tmp_125_fu_2217_p1 <= reg_895;
tmp_127_fu_2333_p1 <= reg_715;
tmp_129_fu_2461_p1 <= reg_775;
tmp_131_fu_2629_p1 <= reg_835;
tmp_133_fu_2755_p1 <= reg_895;
tmp_135_fu_2860_p1 <= tmp_134_reg_3887;
tmp_137_fu_2952_p1 <= reg_715;
tmp_139_fu_3054_p1 <= reg_775;
tmp_13_fu_2050_p2 <= std_logic_vector(unsigned(ap_const_lv9_E1) + unsigned(tmp_2_cast1_fu_2047_p1));
tmp_141_fu_3152_p1 <= reg_835;
tmp_143_fu_3250_p1 <= reg_895;
tmp_145_fu_3347_p1 <= tmp_144_reg_5622;
tmp_147_fu_3430_p1 <= tmp_146_reg_5887;
tmp_149_fu_3513_p1 <= tmp_148_reg_6147;
tmp_14_fu_1839_p1 <= tmp_625_reg_3983;
tmp_150_fu_3577_p1 <= reg_961;
tmp_152_fu_1876_p1 <= reg_719;
tmp_154_fu_2466_p1 <= tmp_153_reg_4018;
tmp_156_fu_1982_p1 <= reg_779;
tmp_158_fu_2106_p1 <= reg_839;
tmp_15_fu_2171_p2 <= std_logic_vector(unsigned(ap_const_lv9_FA) + unsigned(tmp_2_cast1_reg_4442));
tmp_160_fu_2222_p1 <= reg_899;
tmp_162_fu_2338_p1 <= reg_719;
tmp_164_fu_2470_p1 <= reg_779;
tmp_166_fu_2634_p1 <= reg_839;
tmp_168_fu_2760_p1 <= reg_899;
tmp_16_fu_1843_p1 <= tmp_626_reg_4127;
tmp_170_fu_2864_p1 <= tmp_169_reg_3892;
tmp_172_fu_2957_p1 <= reg_719;
tmp_174_fu_3059_p1 <= reg_779;
tmp_176_fu_3157_p1 <= reg_839;
tmp_178_fu_3255_p1 <= reg_899;
tmp_17_fu_2287_p2 <= std_logic_vector(signed(ap_const_lv9_113) + signed(tmp_2_cast1_reg_4442));
tmp_180_fu_3351_p1 <= tmp_179_reg_5637;
tmp_182_fu_3434_p1 <= tmp_181_reg_5902;
tmp_184_fu_3517_p1 <= tmp_183_reg_6162;
tmp_185_fu_3581_p1 <= reg_966;
tmp_187_fu_1881_p1 <= reg_723;
tmp_189_fu_2475_p1 <= tmp_188_reg_4023;
tmp_18_fu_2417_p1 <= tmp_627_reg_3998;
tmp_191_fu_1987_p1 <= reg_783;
tmp_193_fu_2111_p1 <= reg_843;
tmp_195_fu_2227_p1 <= reg_903;
tmp_197_fu_2343_p1 <= reg_723;
tmp_199_fu_2479_p1 <= reg_783;
tmp_19_fu_2403_p2 <= std_logic_vector(signed(ap_const_lv9_12C) + signed(tmp_2_cast1_reg_4442));
tmp_1_cast_fu_1031_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_phi_fu_366_p4),6));
tmp_1_fu_1159_p3 <= (tmp_1_mid2_v_reg_3722 & ap_const_lv2_0);
tmp_1_mid2_cast_fu_1156_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_1_mid2_v_reg_3722),6));
tmp_1_mid2_v_fu_1100_p3 <=
i_1_fu_1087_p2 when (exitcond_flatten_reg_3684(0) = '1') else
i_reg_362;
tmp_201_fu_2639_p1 <= reg_843;
tmp_203_fu_2765_p1 <= reg_903;
tmp_205_fu_2868_p1 <= tmp_204_reg_3897;
tmp_207_fu_2962_p1 <= reg_723;
tmp_209_fu_3064_p1 <= reg_783;
tmp_20_fu_1945_p1 <= tmp_628_reg_4003;
tmp_211_fu_3162_p1 <= reg_843;
tmp_213_fu_3260_p1 <= reg_903;
tmp_215_fu_3355_p1 <= tmp_214_reg_5652;
tmp_217_fu_3438_p1 <= tmp_216_reg_5917;
tmp_219_fu_3521_p1 <= tmp_218_reg_6177;
tmp_220_fu_3585_p1 <= reg_971;
tmp_222_fu_1886_p1 <= reg_727;
tmp_224_fu_2484_p1 <= tmp_223_reg_4028;
tmp_226_fu_1992_p1 <= reg_787;
tmp_228_fu_2116_p1 <= reg_847;
tmp_22_fu_1949_p1 <= tmp_21_reg_4132;
tmp_230_fu_2232_p1 <= reg_907;
tmp_232_fu_2348_p1 <= reg_727;
tmp_234_fu_2488_p1 <= reg_787;
tmp_236_fu_2644_p1 <= reg_847;
tmp_238_fu_2770_p1 <= reg_907;
tmp_23_fu_2583_p2 <= std_logic_vector(signed(ap_const_lv9_145) + signed(tmp_2_cast1_reg_4442));
tmp_240_fu_2872_p1 <= tmp_239_reg_3902;
tmp_242_fu_2967_p1 <= reg_727;
tmp_244_fu_3069_p1 <= reg_787;
tmp_246_fu_3167_p1 <= reg_847;
tmp_248_fu_3265_p1 <= reg_907;
tmp_24_fu_2069_p1 <= tmp_629_reg_4112;
tmp_250_fu_3359_p1 <= tmp_249_reg_5667;
tmp_252_fu_3442_p1 <= tmp_251_reg_5932;
tmp_254_fu_3525_p1 <= tmp_253_reg_6192;
tmp_255_fu_3589_p1 <= reg_976;
tmp_257_fu_1891_p1 <= reg_731;
tmp_259_fu_2493_p1 <= tmp_258_reg_4033;
tmp_261_fu_1997_p1 <= reg_791;
tmp_263_fu_2121_p1 <= reg_851;
tmp_265_fu_2237_p1 <= reg_911;
tmp_267_fu_2353_p1 <= reg_731;
tmp_269_fu_2497_p1 <= reg_791;
tmp_26_fu_2073_p1 <= tmp_25_reg_4137;
tmp_271_fu_2649_p1 <= reg_851;
tmp_273_fu_2775_p1 <= reg_911;
tmp_275_fu_2876_p1 <= tmp_274_reg_3907;
tmp_277_fu_2972_p1 <= reg_731;
tmp_279_fu_3074_p1 <= reg_791;
tmp_27_fu_2699_p2 <= std_logic_vector(signed(ap_const_lv9_15E) + signed(tmp_2_cast1_reg_4442));
tmp_281_fu_3172_p1 <= reg_851;
tmp_283_fu_3270_p1 <= reg_911;
tmp_285_fu_3363_p1 <= tmp_284_reg_5682;
tmp_287_fu_3446_p1 <= tmp_286_reg_5947;
tmp_289_fu_3529_p1 <= tmp_288_reg_6207;
tmp_28_fu_2185_p1 <= tmp_630_reg_4142;
tmp_290_fu_3593_p1 <= reg_981;
tmp_292_fu_1896_p1 <= reg_735;
tmp_294_fu_2502_p1 <= tmp_293_reg_4038;
tmp_296_fu_2002_p1 <= reg_795;
tmp_298_fu_2126_p1 <= reg_855;
tmp_2_cast1_fu_2047_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_2_reg_3767),9));
tmp_2_cast2_fu_1613_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_2_reg_3767),8));
tmp_2_cast_fu_1376_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_2_reg_3767),7));
tmp_2_fu_1170_p2 <= std_logic_vector(unsigned(p_shl4_cast_fu_1166_p1) + unsigned(tmp_1_mid2_cast_fu_1156_p1));
tmp_300_fu_2242_p1 <= reg_915;
tmp_302_fu_2358_p1 <= reg_735;
tmp_304_fu_2506_p1 <= reg_795;
tmp_306_fu_2654_p1 <= reg_855;
tmp_308_fu_2780_p1 <= reg_915;
tmp_30_fu_2189_p1 <= tmp_29_reg_4147;
tmp_310_fu_2880_p1 <= tmp_309_reg_3912;
tmp_312_fu_2977_p1 <= reg_735;
tmp_314_fu_3079_p1 <= reg_795;
tmp_316_fu_3177_p1 <= reg_855;
tmp_318_fu_3275_p1 <= reg_915;
tmp_31_fu_2704_p2 <= std_logic_vector(signed(ap_const_lv9_177) + signed(tmp_2_cast1_reg_4442));
tmp_320_fu_3367_p1 <= tmp_319_reg_5697;
tmp_322_fu_3450_p1 <= tmp_321_reg_5962;
tmp_324_fu_3533_p1 <= tmp_323_reg_6222;
tmp_325_fu_3597_p1 <= reg_986;
tmp_327_fu_1901_p1 <= reg_739;
tmp_329_fu_2511_p1 <= tmp_328_reg_4043;
tmp_32_fu_2301_p1 <= tmp_631_reg_4252;
tmp_331_fu_2007_p1 <= reg_799;
tmp_333_fu_2131_p1 <= reg_859;
tmp_335_fu_2247_p1 <= reg_919;
tmp_337_fu_2363_p1 <= reg_739;
tmp_339_fu_2515_p1 <= reg_799;
tmp_341_fu_2659_p1 <= reg_859;
tmp_343_fu_2785_p1 <= reg_919;
tmp_345_fu_2884_p1 <= tmp_344_reg_3917;
tmp_347_fu_2982_p1 <= reg_739;
tmp_349_fu_3084_p1 <= reg_799;
tmp_34_fu_2305_p1 <= tmp_33_reg_4152;
tmp_351_fu_3182_p1 <= reg_859;
tmp_353_fu_3280_p1 <= reg_919;
tmp_355_fu_3371_p1 <= tmp_354_reg_5712;
tmp_357_fu_3454_p1 <= tmp_356_reg_5977;
tmp_359_fu_3537_p1 <= tmp_358_reg_6237;
tmp_35_fu_1069_p2 <= "1" when (col_b_phi_fu_425_p4 = ap_const_lv5_10) else "0";
tmp_360_fu_3601_p1 <= reg_991;
tmp_362_fu_1906_p1 <= reg_743;
tmp_364_fu_2520_p1 <= tmp_363_reg_4048;
tmp_366_fu_2012_p1 <= reg_803;
tmp_368_fu_2136_p1 <= reg_863;
tmp_36_fu_2421_p1 <= tmp_632_reg_4362;
tmp_370_fu_2252_p1 <= reg_923;
tmp_372_fu_2368_p1 <= reg_743;
tmp_374_fu_2524_p1 <= reg_803;
tmp_376_fu_2664_p1 <= reg_863;
tmp_378_fu_2790_p1 <= reg_923;
tmp_380_fu_2888_p1 <= tmp_379_reg_3922;
tmp_382_fu_2987_p1 <= reg_743;
tmp_384_fu_3089_p1 <= reg_803;
tmp_386_fu_3187_p1 <= reg_863;
tmp_388_fu_3285_p1 <= reg_923;
tmp_38_fu_2425_p1 <= tmp_37_reg_4157;
tmp_390_fu_3375_p1 <= tmp_389_reg_5727;
tmp_392_fu_3458_p1 <= tmp_391_reg_5992;
tmp_394_fu_3541_p1 <= tmp_393_reg_6252;
tmp_395_fu_3605_p1 <= reg_996;
tmp_397_fu_1911_p1 <= reg_747;
tmp_399_fu_2529_p1 <= tmp_398_reg_4053;
tmp_39_fu_1207_p2 <= (exitcond_flatten_mid_reg_3731 or exitcond_flatten_reg_3684);
tmp_3_cast_cast_fu_1446_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_3_reg_3872),12));
tmp_3_fu_1362_p2 <= std_logic_vector(unsigned(tmp_cast_fu_1358_p1) + unsigned(tmp_4_mid2_cast_reg_3819));
tmp_401_fu_2017_p1 <= reg_807;
tmp_403_fu_2141_p1 <= reg_867;
tmp_405_fu_2257_p1 <= reg_927;
tmp_407_fu_2373_p1 <= reg_747;
tmp_409_fu_2533_p1 <= reg_807;
tmp_40_fu_2597_p1 <= tmp_633_reg_4497;
tmp_411_fu_2669_p1 <= reg_867;
tmp_413_fu_2795_p1 <= reg_927;
tmp_415_fu_2892_p1 <= tmp_414_reg_3927;
tmp_417_fu_2992_p1 <= reg_747;
tmp_419_fu_3094_p1 <= reg_807;
tmp_421_fu_3192_p1 <= reg_867;
tmp_423_fu_3290_p1 <= reg_927;
tmp_425_fu_3379_p1 <= tmp_424_reg_5742;
tmp_427_fu_3462_p1 <= tmp_426_reg_6007;
tmp_429_fu_3545_p1 <= tmp_428_reg_6267;
tmp_42_fu_2601_p1 <= tmp_41_reg_4162;
tmp_430_fu_3609_p1 <= reg_1001;
tmp_432_fu_1916_p1 <= reg_751;
tmp_434_fu_2538_p1 <= tmp_433_reg_4058;
tmp_436_fu_2022_p1 <= reg_811;
tmp_438_fu_2146_p1 <= reg_871;
tmp_43_fu_1273_p2 <= std_logic_vector(unsigned(tmp_4_mid2_cast_fu_1270_p1) + unsigned(tmp_2_reg_3767));
tmp_440_fu_2262_p1 <= reg_931;
tmp_442_fu_2378_p1 <= reg_751;
tmp_444_fu_2542_p1 <= reg_811;
tmp_446_fu_2674_p1 <= reg_871;
tmp_448_fu_2800_p1 <= reg_931;
tmp_44_fu_2723_p1 <= tmp_634_reg_4612;
tmp_450_fu_2896_p1 <= tmp_449_reg_3932;
tmp_452_fu_2997_p1 <= reg_751;
tmp_454_fu_3099_p1 <= reg_811;
tmp_456_fu_3197_p1 <= reg_871;
tmp_458_fu_3295_p1 <= reg_931;
tmp_460_fu_3383_p1 <= tmp_459_reg_5757;
tmp_462_fu_3466_p1 <= tmp_461_reg_6022;
tmp_464_fu_3549_p1 <= tmp_463_reg_6282;
tmp_465_fu_3613_p1 <= reg_1006;
tmp_467_fu_1921_p1 <= reg_755;
tmp_469_fu_2547_p1 <= tmp_468_reg_4063;
tmp_46_fu_2727_p1 <= tmp_45_reg_4167;
tmp_471_fu_2027_p1 <= reg_815;
tmp_473_fu_2151_p1 <= reg_875;
tmp_475_fu_2267_p1 <= reg_935;
tmp_477_fu_2383_p1 <= reg_755;
tmp_479_fu_2551_p1 <= reg_815;
tmp_47_fu_1297_p2 <= std_logic_vector(unsigned(tmp_4_mid2_cast4_fu_1290_p1) + unsigned(tmp_5_cast_fu_1287_p1));
tmp_481_fu_2679_p1 <= reg_875;
tmp_483_fu_2805_p1 <= reg_935;
tmp_485_fu_2900_p1 <= tmp_484_reg_3937;
tmp_487_fu_3002_p1 <= reg_755;
tmp_489_fu_3104_p1 <= reg_815;
tmp_48_fu_2829_p1 <= tmp_635_reg_3877;
tmp_491_fu_3202_p1 <= reg_875;
tmp_493_fu_3300_p1 <= reg_935;
tmp_495_fu_3387_p1 <= tmp_494_reg_5772;
tmp_497_fu_3470_p1 <= tmp_496_reg_6037;
tmp_499_fu_3553_p1 <= tmp_498_reg_6297;
tmp_4_fu_1616_p2 <= std_logic_vector(unsigned(ap_const_lv8_64) + unsigned(tmp_2_cast2_fu_1613_p1));
tmp_4_mid2_cast1_fu_2056_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_4_mid2_reg_3783),9));
tmp_4_mid2_cast2_fu_1224_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_4_mid2_fu_1219_p3),10));
tmp_4_mid2_cast3_fu_1622_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_4_mid2_reg_3783),8));
tmp_4_mid2_cast4_fu_1290_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_4_mid2_reg_3783),7));
tmp_4_mid2_cast_fu_1270_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_4_mid2_reg_3783),6));
tmp_4_mid2_fu_1219_p3 <=
j_1_reg_3739 when (exitcond_flatten_mid_reg_3731(0) = '1') else
j_mid_reg_3717;
tmp_500_fu_3617_p1 <= reg_1011;
tmp_502_fu_1926_p1 <= reg_759;
tmp_504_fu_2556_p1 <= tmp_503_reg_4068;
tmp_506_fu_2032_p1 <= reg_819;
tmp_508_fu_2156_p1 <= reg_879;
tmp_50_fu_2833_p1 <= tmp_49_reg_4172;
tmp_510_fu_2272_p1 <= reg_939;
tmp_512_fu_2388_p1 <= reg_759;
tmp_514_fu_2560_p1 <= reg_819;
tmp_516_fu_2684_p1 <= reg_879;
tmp_518_fu_2810_p1 <= reg_939;
tmp_51_fu_1395_p2 <= std_logic_vector(unsigned(tmp_4_mid2_cast4_reg_3841) + unsigned(tmp_6_fu_1379_p2));
tmp_520_fu_2904_p1 <= tmp_519_reg_3942;
tmp_522_fu_3007_p1 <= reg_759;
tmp_524_fu_3109_p1 <= reg_819;
tmp_526_fu_3207_p1 <= reg_879;
tmp_528_fu_3305_p1 <= reg_939;
tmp_52_fu_2920_p1 <= tmp_636_reg_4732;
tmp_530_fu_3391_p1 <= tmp_529_reg_5787;
tmp_532_fu_3474_p1 <= tmp_531_reg_6052;
tmp_534_fu_3557_p1 <= tmp_533_reg_6312;
tmp_535_fu_3621_p1 <= reg_1016;
tmp_537_fu_1931_p1 <= reg_763;
tmp_539_fu_2565_p1 <= tmp_538_reg_4073;
tmp_541_fu_2037_p1 <= reg_823;
tmp_543_fu_2161_p1 <= reg_883;
tmp_545_fu_2277_p1 <= reg_943;
tmp_547_fu_2393_p1 <= reg_763;
tmp_549_fu_2569_p1 <= reg_823;
tmp_54_fu_2924_p1 <= tmp_53_reg_4177;
tmp_551_fu_2689_p1 <= reg_883;
tmp_553_fu_2815_p1 <= reg_943;
tmp_555_fu_2908_p1 <= tmp_554_reg_3947;
tmp_557_fu_3012_p1 <= reg_763;
tmp_559_fu_3114_p1 <= reg_823;
tmp_55_fu_1400_p2 <= std_logic_vector(unsigned(tmp_4_mid2_cast4_reg_3841) + unsigned(tmp_s_fu_1385_p2));
tmp_561_fu_3212_p1 <= reg_883;
tmp_563_fu_3310_p1 <= reg_943;
tmp_565_fu_3395_p1 <= tmp_564_reg_5802;
tmp_567_fu_3478_p1 <= tmp_566_reg_6067;
tmp_569_fu_3561_p1 <= tmp_568_reg_6327;
tmp_56_fu_3022_p1 <= tmp_637_reg_4932;
tmp_570_fu_3625_p1 <= reg_1021;
tmp_572_fu_1936_p1 <= reg_767;
tmp_574_fu_2574_p1 <= tmp_573_reg_4078;
tmp_576_fu_2042_p1 <= reg_827;
tmp_578_fu_2166_p1 <= reg_887;
tmp_580_fu_2282_p1 <= reg_947;
tmp_582_fu_2398_p1 <= reg_767;
tmp_584_fu_2578_p1 <= reg_827;
tmp_586_fu_2694_p1 <= reg_887;
tmp_588_fu_2820_p1 <= reg_947;
tmp_58_fu_3026_p1 <= tmp_57_reg_4182;
tmp_590_fu_2912_p1 <= tmp_589_reg_3952;
tmp_592_fu_3017_p1 <= reg_767;
tmp_594_fu_3119_p1 <= reg_827;
tmp_596_fu_3217_p1 <= reg_887;
tmp_598_fu_3315_p1 <= reg_947;
tmp_59_fu_1629_p2 <= std_logic_vector(unsigned(tmp_4_mid2_cast3_fu_1622_p1) + unsigned(tmp_4_fu_1616_p2));
tmp_5_cast_fu_1287_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_reg_3814),7));
tmp_5_fu_1265_p2 <= std_logic_vector(unsigned(ap_const_lv6_19) + unsigned(tmp_2_reg_3767));
tmp_600_fu_3399_p1 <= tmp_599_reg_5817;
tmp_602_fu_3482_p1 <= tmp_601_reg_6082;
tmp_604_fu_3565_p1 <= tmp_603_reg_6342;
tmp_605_fu_3629_p1 <= reg_1026;
tmp_608_fu_2063_p2 <= std_logic_vector(unsigned(tmp_4_mid2_cast1_fu_2056_p1) + unsigned(tmp_13_fu_2050_p2));
tmp_609_fu_2180_p2 <= std_logic_vector(unsigned(tmp_4_mid2_cast1_reg_4452) + unsigned(tmp_15_fu_2171_p2));
tmp_60_fu_3124_p1 <= tmp_638_reg_5202;
tmp_610_fu_2296_p2 <= std_logic_vector(unsigned(tmp_4_mid2_cast1_reg_4452) + unsigned(tmp_17_fu_2287_p2));
tmp_611_cast_fu_1176_p3 <= (ap_const_lv7_5 & tmp_1_mid2_v_reg_3722);
tmp_611_fu_2412_p2 <= std_logic_vector(unsigned(tmp_4_mid2_cast1_reg_4452) + unsigned(tmp_19_fu_2403_p2));
tmp_612_fu_2592_p2 <= std_logic_vector(unsigned(tmp_4_mid2_cast1_reg_4452) + unsigned(tmp_23_fu_2583_p2));
tmp_613_fu_2713_p2 <= std_logic_vector(unsigned(tmp_4_mid2_cast1_reg_4452) + unsigned(tmp_27_fu_2699_p2));
tmp_614_fu_2718_p2 <= std_logic_vector(unsigned(tmp_4_mid2_cast1_reg_4452) + unsigned(tmp_31_fu_2704_p2));
tmp_615_fu_1241_p2 <= (tmp_9_mid1_reg_3744 or exitcond_flatten_mid_reg_3731);
tmp_616_fu_1245_p2 <= (tmp_615_fu_1241_p2 or exitcond_flatten_reg_3684);
tmp_617_fu_1308_p3 <= (p_v_fu_1303_p3 & ap_const_lv4_0);
tmp_618_fu_1320_p2 <= std_logic_vector(shift_left(unsigned(row_b_1_reg_3834),to_integer(unsigned('0' & ap_const_lv5_1(5-1 downto 0)))));
tmp_619_fu_1418_p3 <= (tmp_8_cast_mid2_reg_3977 & ap_const_lv5_0);
tmp_620_fu_1429_p3 <= (tmp_8_cast_mid2_reg_3977 & ap_const_lv2_0);
tmp_621_cast_fu_1293_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_43_reg_3824),64));
tmp_621_fu_1440_p2 <= std_logic_vector(unsigned(p_shl_cast_fu_1425_p1) + unsigned(p_shl2_cast_fu_1436_p1));
tmp_622_cast_fu_1391_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_47_reg_3852),64));
tmp_622_fu_1342_p2 <= std_logic_vector(unsigned(col_b_cast1_cast_fu_1339_p1) + unsigned(tmp_642_cast_fu_1316_p1));
tmp_623_cast_fu_1414_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_51_reg_3967),64));
tmp_623_fu_1353_p2 <= std_logic_vector(shift_left(unsigned(col_b_mid2_reg_3802),to_integer(unsigned('0' & ap_const_lv5_1(5-1 downto 0)))));
tmp_624_cast_fu_1625_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_55_reg_3972),64));
tmp_624_fu_1449_p2 <= std_logic_vector(unsigned(tmp_3_cast_cast_fu_1446_p1) + unsigned(tmp_621_fu_1440_p2));
tmp_625_cast_fu_1648_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_59_reg_4102),64));
tmp_625_fu_1410_p1 <= bufw_Dout_A(32 - 1 downto 0);
tmp_626_cast_fu_1825_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_63_reg_4122),64));
tmp_626_fu_1657_p1 <= bufi_Dout_A(32 - 1 downto 0);
tmp_627_cast_fu_1941_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_67_reg_4217),64));
tmp_627_fu_1455_p1 <= bufo_Dout_A(32 - 1 downto 0);
tmp_628_cast_fu_2059_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_71_reg_4222),64));
tmp_628_fu_1459_p1 <= bufw_Dout_A(32 - 1 downto 0);
tmp_629_cast_fu_1278_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_75_reg_3792),64));
tmp_629_fu_1639_p1 <= bufw_Dout_A(32 - 1 downto 0);
tmp_62_fu_3128_p1 <= tmp_61_reg_4187;
tmp_630_cast_fu_2176_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_608_reg_4467),64));
tmp_630_fu_1681_p1 <= bufw_Dout_A(32 - 1 downto 0);
tmp_631_cast_fu_2292_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_609_reg_4582),64));
tmp_631_fu_1862_p1 <= bufw_Dout_A(32 - 1 downto 0);
tmp_632_cast_fu_2408_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_610_reg_4697),64));
tmp_632_fu_1968_p1 <= bufw_Dout_A(32 - 1 downto 0);
tmp_633_cast_fu_2588_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_611_reg_4892),64));
tmp_633_fu_2092_p1 <= bufw_Dout_A(32 - 1 downto 0);
tmp_634_cast_fu_2709_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_612_reg_5167),64));
tmp_634_fu_2208_p1 <= bufw_Dout_A(32 - 1 downto 0);
tmp_635_cast_fu_2825_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_613_reg_5362),64));
tmp_635_fu_1367_p1 <= bufw_Dout_A(32 - 1 downto 0);
tmp_636_cast_fu_2916_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_614_reg_5367),64));
tmp_636_fu_2324_p1 <= bufw_Dout_A(32 - 1 downto 0);
tmp_637_fu_2444_p1 <= bufw_Dout_A(32 - 1 downto 0);
tmp_638_fu_2620_p1 <= bufw_Dout_A(32 - 1 downto 0);
tmp_639_fu_2746_p1 <= bufw_Dout_A(32 - 1 downto 0);
tmp_63_fu_1652_p2 <= std_logic_vector(unsigned(tmp_4_mid2_cast3_reg_4090) + unsigned(tmp_7_fu_1643_p2));
tmp_640_fu_2852_p1 <= bufw_Dout_A(32 - 1 downto 0);
tmp_641_fu_2943_p1 <= bufw_Dout_A(32 - 1 downto 0);
tmp_642_cast_fu_1316_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_617_fu_1308_p3),10));
tmp_642_fu_3045_p1 <= bufw_Dout_A(32 - 1 downto 0);
tmp_647_cast_fu_1348_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_622_fu_1342_p2),64));
tmp_649_cast_fu_1635_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_624_reg_3993),64));
tmp_64_fu_3222_p1 <= tmp_639_reg_5402;
tmp_66_fu_3226_p1 <= tmp_65_reg_4192;
tmp_67_fu_1829_p2 <= std_logic_vector(unsigned(tmp_4_mid2_cast3_reg_4090) + unsigned(tmp_9_fu_1815_p2));
tmp_68_fu_3320_p1 <= tmp_640_reg_5592;
tmp_6_fu_1379_p2 <= std_logic_vector(unsigned(ap_const_lv7_32) + unsigned(tmp_2_cast_fu_1376_p1));
tmp_70_fu_3324_p1 <= tmp_69_reg_4197;
tmp_71_fu_1834_p2 <= std_logic_vector(unsigned(tmp_4_mid2_cast3_reg_4090) + unsigned(tmp_10_fu_1820_p2));
tmp_72_fu_3403_p1 <= tmp_641_reg_5857;
tmp_74_fu_3407_p1 <= tmp_73_reg_4202;
tmp_75_fu_1228_p2 <= std_logic_vector(unsigned(tmp_4_mid2_cast2_fu_1224_p1) + unsigned(tmp_11_fu_1192_p2));
tmp_76_fu_3486_p1 <= tmp_642_reg_6117;
tmp_78_fu_3490_p1 <= tmp_77_reg_4207;
tmp_79_fu_3569_p1 <= reg_951;
tmp_7_cast_fu_1041_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_fu_1035_p2),6));
tmp_7_cast_mid1_fu_1325_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_618_fu_1320_p2),6));
tmp_7_fu_1643_p2 <= std_logic_vector(unsigned(ap_const_lv8_7D) + unsigned(tmp_2_cast2_reg_4083));
tmp_81_fu_1866_p1 <= reg_711;
tmp_83_fu_2448_p1 <= tmp_82_reg_4008;
tmp_85_fu_1972_p1 <= reg_771;
tmp_87_fu_2096_p1 <= reg_831;
tmp_89_fu_2212_p1 <= reg_891;
tmp_8_cast_mid2_fu_1405_p3 <=
tmp_8_mid1_reg_3857 when (tmp_9_mid1_reg_3744(0) = '1') else
tmp_8_cast_mid5_reg_3797;
tmp_8_cast_mid3_fu_1201_p3 <=
tmp_8_cast_mid_cast_fu_1198_p1 when (exitcond_flatten_reg_3684(0) = '1') else
tmp_8_reg_3670;
tmp_8_cast_mid5_fu_1234_p3 <=
tmp_1_mid2_cast_fu_1156_p1 when (exitcond_flatten_mid_reg_3731(0) = '1') else
tmp_8_cast_mid3_fu_1201_p3;
tmp_8_cast_mid_cast_fu_1198_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_1_reg_3712),6));
tmp_8_fu_1045_p2 <= std_logic_vector(unsigned(tmp_1_cast_fu_1031_p1) + unsigned(tmp_7_cast_fu_1041_p1));
tmp_8_mid1_fu_1329_p2 <= std_logic_vector(unsigned(tmp_7_cast_mid1_fu_1325_p1) + unsigned(tmp_1_mid2_cast_reg_3762));
tmp_91_fu_2328_p1 <= reg_711;
tmp_93_fu_2452_p1 <= reg_771;
tmp_95_fu_2624_p1 <= reg_831;
tmp_97_fu_2750_p1 <= reg_891;
tmp_99_fu_2856_p1 <= tmp_98_reg_3882;
tmp_9_fu_1815_p2 <= std_logic_vector(signed(ap_const_lv8_96) + signed(tmp_2_cast2_reg_4083));
tmp_9_mid1_fu_1138_p2 <= (tmp_9_mid_fu_1112_p2 and not_exitcond_flatten_1_fu_1133_p2);
tmp_9_mid_fu_1112_p2 <= (tmp_35_reg_3696 and not_exitcond_flatten_fu_1107_p2);
tmp_cast_fu_1358_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_623_fu_1353_p2),6));
tmp_fu_1035_p2 <= std_logic_vector(shift_left(unsigned(row_b_phi_fu_413_p4),to_integer(unsigned('0' & ap_const_lv5_1(5-1 downto 0)))));
tmp_s_fu_1385_p2 <= std_logic_vector(signed(ap_const_lv7_4B) + signed(tmp_2_cast_fu_1376_p1));
end behav;
| mit | 84fd656ece3bcc866664bb75aa950a58 | 0.642123 | 2.474213 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/solution1_6/syn/vhdl/convolve_kernel.vhd | 3 | 275,955 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity convolve_kernel is
generic (
C_S_AXI_CONTROL_ADDR_WIDTH : INTEGER := 4;
C_S_AXI_CONTROL_DATA_WIDTH : INTEGER := 32 );
port (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
bufw_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_EN_A : OUT STD_LOGIC;
bufw_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_Clk_A : OUT STD_LOGIC;
bufw_Rst_A : OUT STD_LOGIC;
bufi_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_EN_A : OUT STD_LOGIC;
bufi_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufi_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufi_Clk_A : OUT STD_LOGIC;
bufi_Rst_A : OUT STD_LOGIC;
bufo_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_EN_A : OUT STD_LOGIC;
bufo_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_Clk_A : OUT STD_LOGIC;
bufo_Rst_A : OUT STD_LOGIC;
s_axi_control_AWVALID : IN STD_LOGIC;
s_axi_control_AWREADY : OUT STD_LOGIC;
s_axi_control_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_CONTROL_ADDR_WIDTH-1 downto 0);
s_axi_control_WVALID : IN STD_LOGIC;
s_axi_control_WREADY : OUT STD_LOGIC;
s_axi_control_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_CONTROL_DATA_WIDTH-1 downto 0);
s_axi_control_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_CONTROL_DATA_WIDTH/8-1 downto 0);
s_axi_control_ARVALID : IN STD_LOGIC;
s_axi_control_ARREADY : OUT STD_LOGIC;
s_axi_control_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_CONTROL_ADDR_WIDTH-1 downto 0);
s_axi_control_RVALID : OUT STD_LOGIC;
s_axi_control_RREADY : IN STD_LOGIC;
s_axi_control_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_CONTROL_DATA_WIDTH-1 downto 0);
s_axi_control_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
s_axi_control_BVALID : OUT STD_LOGIC;
s_axi_control_BREADY : IN STD_LOGIC;
s_axi_control_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
interrupt : OUT STD_LOGIC );
end;
architecture behav of convolve_kernel is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"convolve_kernel,hls_ip_2017_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=1,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=3.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=3.384000,HLS_SYN_LAT=1638632,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=3,HLS_SYN_FF=21535,HLS_SYN_LUT=6142}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (17 downto 0) := "000000000000000001";
constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (17 downto 0) := "000000000000000010";
constant ap_ST_fsm_pp0_stage1 : STD_LOGIC_VECTOR (17 downto 0) := "000000000000000100";
constant ap_ST_fsm_pp0_stage2 : STD_LOGIC_VECTOR (17 downto 0) := "000000000000001000";
constant ap_ST_fsm_pp0_stage3 : STD_LOGIC_VECTOR (17 downto 0) := "000000000000010000";
constant ap_ST_fsm_pp0_stage4 : STD_LOGIC_VECTOR (17 downto 0) := "000000000000100000";
constant ap_ST_fsm_pp0_stage5 : STD_LOGIC_VECTOR (17 downto 0) := "000000000001000000";
constant ap_ST_fsm_pp0_stage6 : STD_LOGIC_VECTOR (17 downto 0) := "000000000010000000";
constant ap_ST_fsm_pp0_stage7 : STD_LOGIC_VECTOR (17 downto 0) := "000000000100000000";
constant ap_ST_fsm_pp0_stage8 : STD_LOGIC_VECTOR (17 downto 0) := "000000001000000000";
constant ap_ST_fsm_pp0_stage9 : STD_LOGIC_VECTOR (17 downto 0) := "000000010000000000";
constant ap_ST_fsm_pp0_stage10 : STD_LOGIC_VECTOR (17 downto 0) := "000000100000000000";
constant ap_ST_fsm_pp0_stage11 : STD_LOGIC_VECTOR (17 downto 0) := "000001000000000000";
constant ap_ST_fsm_pp0_stage12 : STD_LOGIC_VECTOR (17 downto 0) := "000010000000000000";
constant ap_ST_fsm_pp0_stage13 : STD_LOGIC_VECTOR (17 downto 0) := "000100000000000000";
constant ap_ST_fsm_pp0_stage14 : STD_LOGIC_VECTOR (17 downto 0) := "001000000000000000";
constant ap_ST_fsm_pp0_stage15 : STD_LOGIC_VECTOR (17 downto 0) := "010000000000000000";
constant ap_ST_fsm_state249 : STD_LOGIC_VECTOR (17 downto 0) := "100000000000000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_boolean_1 : BOOLEAN := true;
constant C_S_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_boolean_0 : BOOLEAN := false;
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011";
constant ap_const_lv32_C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001100";
constant ap_const_lv32_D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001101";
constant ap_const_lv32_E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001110";
constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
constant ap_const_lv17_0 : STD_LOGIC_VECTOR (16 downto 0) := "00000000000000000";
constant ap_const_lv3_0 : STD_LOGIC_VECTOR (2 downto 0) := "000";
constant ap_const_lv16_0 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
constant ap_const_lv14_0 : STD_LOGIC_VECTOR (13 downto 0) := "00000000000000";
constant ap_const_lv5_0 : STD_LOGIC_VECTOR (4 downto 0) := "00000";
constant ap_const_lv10_0 : STD_LOGIC_VECTOR (9 downto 0) := "0000000000";
constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
constant ap_const_lv4_F : STD_LOGIC_VECTOR (3 downto 0) := "1111";
constant ap_const_lv5_1 : STD_LOGIC_VECTOR (4 downto 0) := "00001";
constant ap_const_lv17_19000 : STD_LOGIC_VECTOR (16 downto 0) := "11001000000000000";
constant ap_const_lv17_1 : STD_LOGIC_VECTOR (16 downto 0) := "00000000000000001";
constant ap_const_lv16_5000 : STD_LOGIC_VECTOR (15 downto 0) := "0101000000000000";
constant ap_const_lv14_1000 : STD_LOGIC_VECTOR (13 downto 0) := "01000000000000";
constant ap_const_lv16_1 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000001";
constant ap_const_lv10_100 : STD_LOGIC_VECTOR (9 downto 0) := "0100000000";
constant ap_const_lv5_10 : STD_LOGIC_VECTOR (4 downto 0) := "10000";
constant ap_const_lv10_1 : STD_LOGIC_VECTOR (9 downto 0) := "0000000001";
constant ap_const_lv14_1 : STD_LOGIC_VECTOR (13 downto 0) := "00000000000001";
constant ap_const_lv3_1 : STD_LOGIC_VECTOR (2 downto 0) := "001";
constant ap_const_lv6_0 : STD_LOGIC_VECTOR (5 downto 0) := "000000";
constant ap_const_lv9_1 : STD_LOGIC_VECTOR (8 downto 0) := "000000001";
constant ap_const_lv55_0 : STD_LOGIC_VECTOR (54 downto 0) := "0000000000000000000000000000000000000000000000000000000";
constant ap_const_lv53_0 : STD_LOGIC_VECTOR (52 downto 0) := "00000000000000000000000000000000000000000000000000000";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv9_8 : STD_LOGIC_VECTOR (8 downto 0) := "000001000";
constant ap_const_lv9_2 : STD_LOGIC_VECTOR (8 downto 0) := "000000010";
constant ap_const_lv9_3 : STD_LOGIC_VECTOR (8 downto 0) := "000000011";
constant ap_const_lv9_4 : STD_LOGIC_VECTOR (8 downto 0) := "000000100";
constant ap_const_lv16_510 : STD_LOGIC_VECTOR (15 downto 0) := "0000010100010000";
constant ap_const_lv9_5 : STD_LOGIC_VECTOR (8 downto 0) := "000000101";
constant ap_const_lv16_A20 : STD_LOGIC_VECTOR (15 downto 0) := "0000101000100000";
constant ap_const_lv9_6 : STD_LOGIC_VECTOR (8 downto 0) := "000000110";
constant ap_const_lv16_F30 : STD_LOGIC_VECTOR (15 downto 0) := "0000111100110000";
constant ap_const_lv9_7 : STD_LOGIC_VECTOR (8 downto 0) := "000000111";
constant ap_const_lv16_1440 : STD_LOGIC_VECTOR (15 downto 0) := "0001010001000000";
constant ap_const_lv9_9 : STD_LOGIC_VECTOR (8 downto 0) := "000001001";
constant ap_const_lv9_A : STD_LOGIC_VECTOR (8 downto 0) := "000001010";
constant ap_const_lv9_B : STD_LOGIC_VECTOR (8 downto 0) := "000001011";
constant ap_const_lv9_C : STD_LOGIC_VECTOR (8 downto 0) := "000001100";
constant ap_const_lv9_D : STD_LOGIC_VECTOR (8 downto 0) := "000001101";
constant ap_const_lv9_E : STD_LOGIC_VECTOR (8 downto 0) := "000001110";
constant ap_const_lv9_F : STD_LOGIC_VECTOR (8 downto 0) := "000001111";
constant ap_const_lv16_1950 : STD_LOGIC_VECTOR (15 downto 0) := "0001100101010000";
constant ap_const_lv16_1E60 : STD_LOGIC_VECTOR (15 downto 0) := "0001111001100000";
constant ap_const_lv16_2370 : STD_LOGIC_VECTOR (15 downto 0) := "0010001101110000";
constant ap_const_lv16_2880 : STD_LOGIC_VECTOR (15 downto 0) := "0010100010000000";
constant ap_const_lv16_2D90 : STD_LOGIC_VECTOR (15 downto 0) := "0010110110010000";
constant ap_const_lv16_32A0 : STD_LOGIC_VECTOR (15 downto 0) := "0011001010100000";
constant ap_const_lv16_37B0 : STD_LOGIC_VECTOR (15 downto 0) := "0011011110110000";
constant ap_const_lv16_3CC0 : STD_LOGIC_VECTOR (15 downto 0) := "0011110011000000";
constant ap_const_lv16_41D0 : STD_LOGIC_VECTOR (15 downto 0) := "0100000111010000";
constant ap_const_lv16_46E0 : STD_LOGIC_VECTOR (15 downto 0) := "0100011011100000";
constant ap_const_lv16_4BF0 : STD_LOGIC_VECTOR (15 downto 0) := "0100101111110000";
constant ap_const_lv32_11 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010001";
signal ap_rst_n_inv : STD_LOGIC;
signal ap_start : STD_LOGIC;
signal ap_done : STD_LOGIC;
signal ap_idle : STD_LOGIC;
signal ap_CS_fsm : STD_LOGIC_VECTOR (17 downto 0) := "000000000000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal ap_ready : STD_LOGIC;
signal indvar_flatten1_reg_461 : STD_LOGIC_VECTOR (16 downto 0);
signal i_reg_472 : STD_LOGIC_VECTOR (2 downto 0);
signal indvar_flatten2_reg_484 : STD_LOGIC_VECTOR (15 downto 0);
signal j_reg_495 : STD_LOGIC_VECTOR (2 downto 0);
signal indvar_flatten3_reg_507 : STD_LOGIC_VECTOR (13 downto 0);
signal row_b_reg_519 : STD_LOGIC_VECTOR (4 downto 0);
signal indvar_flatten_reg_531 : STD_LOGIC_VECTOR (9 downto 0);
signal col_b_reg_543 : STD_LOGIC_VECTOR (4 downto 0);
signal to_b_reg_555 : STD_LOGIC_VECTOR (4 downto 0);
signal grp_fu_567_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_575 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_pp0_stage6 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage6 : signal is "none";
signal ap_enable_reg_pp0_iter7 : STD_LOGIC := '0';
signal ap_block_state8_pp0_stage6_iter0 : BOOLEAN;
signal ap_block_state24_pp0_stage6_iter1 : BOOLEAN;
signal ap_block_state40_pp0_stage6_iter2 : BOOLEAN;
signal ap_block_state56_pp0_stage6_iter3 : BOOLEAN;
signal ap_block_state72_pp0_stage6_iter4 : BOOLEAN;
signal ap_block_state88_pp0_stage6_iter5 : BOOLEAN;
signal ap_block_state104_pp0_stage6_iter6 : BOOLEAN;
signal ap_block_state120_pp0_stage6_iter7 : BOOLEAN;
signal ap_block_state136_pp0_stage6_iter8 : BOOLEAN;
signal ap_block_state152_pp0_stage6_iter9 : BOOLEAN;
signal ap_block_state168_pp0_stage6_iter10 : BOOLEAN;
signal ap_block_state184_pp0_stage6_iter11 : BOOLEAN;
signal ap_block_state200_pp0_stage6_iter12 : BOOLEAN;
signal ap_block_state216_pp0_stage6_iter13 : BOOLEAN;
signal ap_block_state232_pp0_stage6_iter14 : BOOLEAN;
signal ap_block_state248_pp0_stage6_iter15 : BOOLEAN;
signal ap_block_pp0_stage6_flag00011001 : BOOLEAN;
signal exitcond_flatten3_reg_2229 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter7_exitcond_flatten3_reg_2229 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage5 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage5 : signal is "none";
signal ap_enable_reg_pp0_iter15 : STD_LOGIC := '0';
signal ap_block_state7_pp0_stage5_iter0 : BOOLEAN;
signal ap_block_state23_pp0_stage5_iter1 : BOOLEAN;
signal ap_block_state39_pp0_stage5_iter2 : BOOLEAN;
signal ap_block_state55_pp0_stage5_iter3 : BOOLEAN;
signal ap_block_state71_pp0_stage5_iter4 : BOOLEAN;
signal ap_block_state87_pp0_stage5_iter5 : BOOLEAN;
signal ap_block_state103_pp0_stage5_iter6 : BOOLEAN;
signal ap_block_state119_pp0_stage5_iter7 : BOOLEAN;
signal ap_block_state135_pp0_stage5_iter8 : BOOLEAN;
signal ap_block_state151_pp0_stage5_iter9 : BOOLEAN;
signal ap_block_state167_pp0_stage5_iter10 : BOOLEAN;
signal ap_block_state183_pp0_stage5_iter11 : BOOLEAN;
signal ap_block_state199_pp0_stage5_iter12 : BOOLEAN;
signal ap_block_state215_pp0_stage5_iter13 : BOOLEAN;
signal ap_block_state231_pp0_stage5_iter14 : BOOLEAN;
signal ap_block_state247_pp0_stage5_iter15 : BOOLEAN;
signal ap_block_pp0_stage5_flag00011001 : BOOLEAN;
signal ap_reg_pp0_iter15_exitcond_flatten3_reg_2229 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_6_fu_599_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_6_reg_2219 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
signal ap_block_state2_pp0_stage0_iter0 : BOOLEAN;
signal ap_block_state18_pp0_stage0_iter1 : BOOLEAN;
signal ap_block_state34_pp0_stage0_iter2 : BOOLEAN;
signal ap_block_state50_pp0_stage0_iter3 : BOOLEAN;
signal ap_block_state66_pp0_stage0_iter4 : BOOLEAN;
signal ap_block_state82_pp0_stage0_iter5 : BOOLEAN;
signal ap_block_state98_pp0_stage0_iter6 : BOOLEAN;
signal ap_block_state114_pp0_stage0_iter7 : BOOLEAN;
signal ap_block_state130_pp0_stage0_iter8 : BOOLEAN;
signal ap_block_state146_pp0_stage0_iter9 : BOOLEAN;
signal ap_block_state162_pp0_stage0_iter10 : BOOLEAN;
signal ap_block_state178_pp0_stage0_iter11 : BOOLEAN;
signal ap_block_state194_pp0_stage0_iter12 : BOOLEAN;
signal ap_block_state210_pp0_stage0_iter13 : BOOLEAN;
signal ap_block_state226_pp0_stage0_iter14 : BOOLEAN;
signal ap_block_state242_pp0_stage0_iter15 : BOOLEAN;
signal ap_block_pp0_stage0_flag00011001 : BOOLEAN;
signal tmp_s_fu_615_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_s_reg_2224 : STD_LOGIC_VECTOR (5 downto 0);
signal exitcond_flatten3_fu_621_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter1_exitcond_flatten3_reg_2229 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter2_exitcond_flatten3_reg_2229 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter3_exitcond_flatten3_reg_2229 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter4_exitcond_flatten3_reg_2229 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter5_exitcond_flatten3_reg_2229 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter6_exitcond_flatten3_reg_2229 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter8_exitcond_flatten3_reg_2229 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter9_exitcond_flatten3_reg_2229 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter10_exitcond_flatten3_reg_2229 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter11_exitcond_flatten3_reg_2229 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter12_exitcond_flatten3_reg_2229 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter13_exitcond_flatten3_reg_2229 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter14_exitcond_flatten3_reg_2229 : STD_LOGIC_VECTOR (0 downto 0);
signal indvar_flatten_next3_fu_627_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal indvar_flatten_next3_reg_2233 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_enable_reg_pp0_iter0 : STD_LOGIC := '0';
signal exitcond_flatten_fu_633_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond_flatten_reg_2238 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond_flatten2_fu_639_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond_flatten2_reg_2251 : STD_LOGIC_VECTOR (0 downto 0);
signal indvar_flatten81_op_fu_645_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal indvar_flatten81_op_reg_2257 : STD_LOGIC_VECTOR (15 downto 0);
signal not_exitcond_flatten_fu_651_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_exitcond_flatten_reg_2262 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage1 : signal is "none";
signal ap_block_state3_pp0_stage1_iter0 : BOOLEAN;
signal ap_block_state19_pp0_stage1_iter1 : BOOLEAN;
signal ap_block_state35_pp0_stage1_iter2 : BOOLEAN;
signal ap_block_state51_pp0_stage1_iter3 : BOOLEAN;
signal ap_block_state67_pp0_stage1_iter4 : BOOLEAN;
signal ap_block_state83_pp0_stage1_iter5 : BOOLEAN;
signal ap_block_state99_pp0_stage1_iter6 : BOOLEAN;
signal ap_block_state115_pp0_stage1_iter7 : BOOLEAN;
signal ap_block_state131_pp0_stage1_iter8 : BOOLEAN;
signal ap_block_state147_pp0_stage1_iter9 : BOOLEAN;
signal ap_block_state163_pp0_stage1_iter10 : BOOLEAN;
signal ap_block_state179_pp0_stage1_iter11 : BOOLEAN;
signal ap_block_state195_pp0_stage1_iter12 : BOOLEAN;
signal ap_block_state211_pp0_stage1_iter13 : BOOLEAN;
signal ap_block_state227_pp0_stage1_iter14 : BOOLEAN;
signal ap_block_state243_pp0_stage1_iter15 : BOOLEAN;
signal ap_block_pp0_stage1_flag00011001 : BOOLEAN;
signal exitcond_flatten1_fu_656_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond_flatten1_reg_2269 : STD_LOGIC_VECTOR (0 downto 0);
signal not_exitcond_flatten_1_fu_667_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_exitcond_flatten_1_reg_2274 : STD_LOGIC_VECTOR (0 downto 0);
signal indvar_flatten_next2_fu_672_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal indvar_flatten_next2_reg_2280 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_fu_678_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_2_reg_2285 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage2 : signal is "none";
signal ap_block_state4_pp0_stage2_iter0 : BOOLEAN;
signal ap_block_state20_pp0_stage2_iter1 : BOOLEAN;
signal ap_block_state36_pp0_stage2_iter2 : BOOLEAN;
signal ap_block_state52_pp0_stage2_iter3 : BOOLEAN;
signal ap_block_state68_pp0_stage2_iter4 : BOOLEAN;
signal ap_block_state84_pp0_stage2_iter5 : BOOLEAN;
signal ap_block_state100_pp0_stage2_iter6 : BOOLEAN;
signal ap_block_state116_pp0_stage2_iter7 : BOOLEAN;
signal ap_block_state132_pp0_stage2_iter8 : BOOLEAN;
signal ap_block_state148_pp0_stage2_iter9 : BOOLEAN;
signal ap_block_state164_pp0_stage2_iter10 : BOOLEAN;
signal ap_block_state180_pp0_stage2_iter11 : BOOLEAN;
signal ap_block_state196_pp0_stage2_iter12 : BOOLEAN;
signal ap_block_state212_pp0_stage2_iter13 : BOOLEAN;
signal ap_block_state228_pp0_stage2_iter14 : BOOLEAN;
signal ap_block_state244_pp0_stage2_iter15 : BOOLEAN;
signal ap_block_pp0_stage2_flag00011001 : BOOLEAN;
signal exitcond_flatten43_m_fu_688_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond_flatten43_m_reg_2290 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond_flatten_mid_2_fu_692_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond_flatten_mid_2_reg_2299 : STD_LOGIC_VECTOR (0 downto 0);
signal j_mid_fu_697_p3 : STD_LOGIC_VECTOR (2 downto 0);
signal j_mid_reg_2309 : STD_LOGIC_VECTOR (2 downto 0);
signal ap_CS_fsm_pp0_stage3 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage3 : signal is "none";
signal ap_block_state5_pp0_stage3_iter0 : BOOLEAN;
signal ap_block_state21_pp0_stage3_iter1 : BOOLEAN;
signal ap_block_state37_pp0_stage3_iter2 : BOOLEAN;
signal ap_block_state53_pp0_stage3_iter3 : BOOLEAN;
signal ap_block_state69_pp0_stage3_iter4 : BOOLEAN;
signal ap_block_state85_pp0_stage3_iter5 : BOOLEAN;
signal ap_block_state101_pp0_stage3_iter6 : BOOLEAN;
signal ap_block_state117_pp0_stage3_iter7 : BOOLEAN;
signal ap_block_state133_pp0_stage3_iter8 : BOOLEAN;
signal ap_block_state149_pp0_stage3_iter9 : BOOLEAN;
signal ap_block_state165_pp0_stage3_iter10 : BOOLEAN;
signal ap_block_state181_pp0_stage3_iter11 : BOOLEAN;
signal ap_block_state197_pp0_stage3_iter12 : BOOLEAN;
signal ap_block_state213_pp0_stage3_iter13 : BOOLEAN;
signal ap_block_state229_pp0_stage3_iter14 : BOOLEAN;
signal ap_block_state245_pp0_stage3_iter15 : BOOLEAN;
signal ap_block_pp0_stage3_flag00011001 : BOOLEAN;
signal tmp_3_fu_708_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_3_reg_2315 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_7_fu_721_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_7_reg_2322 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_2_mid2_fu_731_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_2_mid2_reg_2328 : STD_LOGIC_VECTOR (0 downto 0);
signal indvar_flatten_op_fu_737_p2 : STD_LOGIC_VECTOR (9 downto 0);
signal indvar_flatten_op_reg_2335 : STD_LOGIC_VECTOR (9 downto 0);
signal indvar_flatten41_op_fu_743_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal indvar_flatten41_op_reg_2340 : STD_LOGIC_VECTOR (13 downto 0);
signal i_1_fu_749_p2 : STD_LOGIC_VECTOR (2 downto 0);
signal i_1_reg_2345 : STD_LOGIC_VECTOR (2 downto 0);
signal ap_CS_fsm_pp0_stage4 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage4 : signal is "none";
signal ap_block_state6_pp0_stage4_iter0 : BOOLEAN;
signal ap_block_state22_pp0_stage4_iter1 : BOOLEAN;
signal ap_block_state38_pp0_stage4_iter2 : BOOLEAN;
signal ap_block_state54_pp0_stage4_iter3 : BOOLEAN;
signal ap_block_state70_pp0_stage4_iter4 : BOOLEAN;
signal ap_block_state86_pp0_stage4_iter5 : BOOLEAN;
signal ap_block_state102_pp0_stage4_iter6 : BOOLEAN;
signal ap_block_state118_pp0_stage4_iter7 : BOOLEAN;
signal ap_block_state134_pp0_stage4_iter8 : BOOLEAN;
signal ap_block_state150_pp0_stage4_iter9 : BOOLEAN;
signal ap_block_state166_pp0_stage4_iter10 : BOOLEAN;
signal ap_block_state182_pp0_stage4_iter11 : BOOLEAN;
signal ap_block_state198_pp0_stage4_iter12 : BOOLEAN;
signal ap_block_state214_pp0_stage4_iter13 : BOOLEAN;
signal ap_block_state230_pp0_stage4_iter14 : BOOLEAN;
signal ap_block_state246_pp0_stage4_iter15 : BOOLEAN;
signal ap_block_pp0_stage4_flag00011001 : BOOLEAN;
signal j_1_fu_755_p2 : STD_LOGIC_VECTOR (2 downto 0);
signal j_1_reg_2351 : STD_LOGIC_VECTOR (2 downto 0);
signal row_b_mid_fu_760_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal row_b_mid_reg_2357 : STD_LOGIC_VECTOR (4 downto 0);
signal col_b_mid1_fu_767_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal col_b_mid1_reg_2363 : STD_LOGIC_VECTOR (4 downto 0);
signal to_b_mid2_fu_783_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal to_b_mid2_reg_2369 : STD_LOGIC_VECTOR (4 downto 0);
signal indvar_flatten_next_fu_791_p3 : STD_LOGIC_VECTOR (9 downto 0);
signal indvar_flatten_next_reg_2376 : STD_LOGIC_VECTOR (9 downto 0);
signal indvar_flatten_next1_fu_797_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal indvar_flatten_next1_reg_2381 : STD_LOGIC_VECTOR (13 downto 0);
signal i_cast7_mid2_fu_803_p3 : STD_LOGIC_VECTOR (2 downto 0);
signal i_cast7_mid2_reg_2386 : STD_LOGIC_VECTOR (2 downto 0);
signal j_cast5_mid2_fu_809_p3 : STD_LOGIC_VECTOR (2 downto 0);
signal j_cast5_mid2_reg_2395 : STD_LOGIC_VECTOR (2 downto 0);
signal row_b_1_fu_814_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal row_b_1_reg_2402 : STD_LOGIC_VECTOR (4 downto 0);
signal col_b_1_fu_819_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal col_b_1_reg_2408 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_48_fu_824_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_48_reg_2414 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_51_fu_852_p1 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_51_reg_2432 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_53_reg_2437 : STD_LOGIC_VECTOR (8 downto 0);
signal to_b_1_fu_926_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal to_b_1_reg_2463 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_6_cast_mid5_fu_955_p3 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_6_cast_mid5_reg_2468 : STD_LOGIC_VECTOR (5 downto 0);
signal row_b_cast3_mid2_fu_969_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal row_b_cast3_mid2_reg_2473 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_6_mid1_fu_983_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_6_mid1_reg_2479 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_cast_mid5_fu_989_p3 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_cast_mid5_reg_2484 : STD_LOGIC_VECTOR (5 downto 0);
signal col_b_cast2_mid2_fu_996_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal col_b_cast2_mid2_reg_2489 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_mid1_fu_1010_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_mid1_reg_2495 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_52_fu_1016_p2 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_52_reg_2500 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_6_cast_mid2_fu_1052_p3 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_6_cast_mid2_reg_2516 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_CS_fsm_pp0_stage7 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage7 : signal is "none";
signal ap_block_state9_pp0_stage7_iter0 : BOOLEAN;
signal ap_block_state25_pp0_stage7_iter1 : BOOLEAN;
signal ap_block_state41_pp0_stage7_iter2 : BOOLEAN;
signal ap_block_state57_pp0_stage7_iter3 : BOOLEAN;
signal ap_block_state73_pp0_stage7_iter4 : BOOLEAN;
signal ap_block_state89_pp0_stage7_iter5 : BOOLEAN;
signal ap_block_state105_pp0_stage7_iter6 : BOOLEAN;
signal ap_block_state121_pp0_stage7_iter7 : BOOLEAN;
signal ap_block_state137_pp0_stage7_iter8 : BOOLEAN;
signal ap_block_state153_pp0_stage7_iter9 : BOOLEAN;
signal ap_block_state169_pp0_stage7_iter10 : BOOLEAN;
signal ap_block_state185_pp0_stage7_iter11 : BOOLEAN;
signal ap_block_state201_pp0_stage7_iter12 : BOOLEAN;
signal ap_block_state217_pp0_stage7_iter13 : BOOLEAN;
signal ap_block_state233_pp0_stage7_iter14 : BOOLEAN;
signal ap_block_pp0_stage7_flag00011001 : BOOLEAN;
signal tmp_cast_mid2_fu_1057_p3 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_cast_mid2_reg_2522 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_55_fu_1083_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_55_reg_2527 : STD_LOGIC_VECTOR (13 downto 0);
signal grp_fu_890_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_59_reg_2532 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_117_fu_1118_p1 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_117_reg_2547 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_118_reg_2552 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_119_reg_2557 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_171_fu_1142_p2 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_171_reg_2562 : STD_LOGIC_VECTOR (9 downto 0);
signal i_cast6_mid2_fu_1148_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal i_cast6_mid2_reg_2567 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_CS_fsm_pp0_stage8 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage8 : signal is "none";
signal ap_block_state10_pp0_stage8_iter0 : BOOLEAN;
signal ap_block_state26_pp0_stage8_iter1 : BOOLEAN;
signal ap_block_state42_pp0_stage8_iter2 : BOOLEAN;
signal ap_block_state58_pp0_stage8_iter3 : BOOLEAN;
signal ap_block_state74_pp0_stage8_iter4 : BOOLEAN;
signal ap_block_state90_pp0_stage8_iter5 : BOOLEAN;
signal ap_block_state106_pp0_stage8_iter6 : BOOLEAN;
signal ap_block_state122_pp0_stage8_iter7 : BOOLEAN;
signal ap_block_state138_pp0_stage8_iter8 : BOOLEAN;
signal ap_block_state154_pp0_stage8_iter9 : BOOLEAN;
signal ap_block_state170_pp0_stage8_iter10 : BOOLEAN;
signal ap_block_state186_pp0_stage8_iter11 : BOOLEAN;
signal ap_block_state202_pp0_stage8_iter12 : BOOLEAN;
signal ap_block_state218_pp0_stage8_iter13 : BOOLEAN;
signal ap_block_state234_pp0_stage8_iter14 : BOOLEAN;
signal ap_block_pp0_stage8_flag00011001 : BOOLEAN;
signal j_cast4_mid2_cast_fu_1151_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal j_cast4_mid2_cast_reg_2585 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_13_fu_1176_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_13_reg_2604 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_56_fu_1185_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_56_reg_2624 : STD_LOGIC_VECTOR (13 downto 0);
signal grp_fu_1043_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_67_reg_2629 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_116_fu_1224_p2 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_116_reg_2644 : STD_LOGIC_VECTOR (2 downto 0);
signal bufo_addr_reg_2650 : STD_LOGIC_VECTOR (11 downto 0);
signal ap_reg_pp0_iter1_bufo_addr_reg_2650 : STD_LOGIC_VECTOR (11 downto 0);
signal ap_reg_pp0_iter2_bufo_addr_reg_2650 : STD_LOGIC_VECTOR (11 downto 0);
signal ap_reg_pp0_iter3_bufo_addr_reg_2650 : STD_LOGIC_VECTOR (11 downto 0);
signal ap_reg_pp0_iter4_bufo_addr_reg_2650 : STD_LOGIC_VECTOR (11 downto 0);
signal ap_reg_pp0_iter5_bufo_addr_reg_2650 : STD_LOGIC_VECTOR (11 downto 0);
signal ap_reg_pp0_iter6_bufo_addr_reg_2650 : STD_LOGIC_VECTOR (11 downto 0);
signal ap_reg_pp0_iter7_bufo_addr_reg_2650 : STD_LOGIC_VECTOR (11 downto 0);
signal ap_reg_pp0_iter8_bufo_addr_reg_2650 : STD_LOGIC_VECTOR (11 downto 0);
signal ap_reg_pp0_iter9_bufo_addr_reg_2650 : STD_LOGIC_VECTOR (11 downto 0);
signal ap_reg_pp0_iter10_bufo_addr_reg_2650 : STD_LOGIC_VECTOR (11 downto 0);
signal ap_reg_pp0_iter11_bufo_addr_reg_2650 : STD_LOGIC_VECTOR (11 downto 0);
signal ap_reg_pp0_iter12_bufo_addr_reg_2650 : STD_LOGIC_VECTOR (11 downto 0);
signal ap_reg_pp0_iter13_bufo_addr_reg_2650 : STD_LOGIC_VECTOR (11 downto 0);
signal ap_reg_pp0_iter14_bufo_addr_reg_2650 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_14_fu_1246_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_14_reg_2655 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_CS_fsm_pp0_stage9 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage9 : signal is "none";
signal ap_block_state11_pp0_stage9_iter0 : BOOLEAN;
signal ap_block_state27_pp0_stage9_iter1 : BOOLEAN;
signal ap_block_state43_pp0_stage9_iter2 : BOOLEAN;
signal ap_block_state59_pp0_stage9_iter3 : BOOLEAN;
signal ap_block_state75_pp0_stage9_iter4 : BOOLEAN;
signal ap_block_state91_pp0_stage9_iter5 : BOOLEAN;
signal ap_block_state107_pp0_stage9_iter6 : BOOLEAN;
signal ap_block_state123_pp0_stage9_iter7 : BOOLEAN;
signal ap_block_state139_pp0_stage9_iter8 : BOOLEAN;
signal ap_block_state155_pp0_stage9_iter9 : BOOLEAN;
signal ap_block_state171_pp0_stage9_iter10 : BOOLEAN;
signal ap_block_state187_pp0_stage9_iter11 : BOOLEAN;
signal ap_block_state203_pp0_stage9_iter12 : BOOLEAN;
signal ap_block_state219_pp0_stage9_iter13 : BOOLEAN;
signal ap_block_state235_pp0_stage9_iter14 : BOOLEAN;
signal ap_block_pp0_stage9_flag00011001 : BOOLEAN;
signal tmp_cast_mid2_cast_fu_1251_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_cast_mid2_cast_reg_2660 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_32_fu_1254_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_32_reg_2679 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1112_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_75_reg_2689 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_120_fu_1310_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_120_reg_2704 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_15_fu_1316_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_15_reg_2709 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_CS_fsm_pp0_stage10 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage10 : signal is "none";
signal ap_block_state12_pp0_stage10_iter0 : BOOLEAN;
signal ap_block_state28_pp0_stage10_iter1 : BOOLEAN;
signal ap_block_state44_pp0_stage10_iter2 : BOOLEAN;
signal ap_block_state60_pp0_stage10_iter3 : BOOLEAN;
signal ap_block_state76_pp0_stage10_iter4 : BOOLEAN;
signal ap_block_state92_pp0_stage10_iter5 : BOOLEAN;
signal ap_block_state108_pp0_stage10_iter6 : BOOLEAN;
signal ap_block_state124_pp0_stage10_iter7 : BOOLEAN;
signal ap_block_state140_pp0_stage10_iter8 : BOOLEAN;
signal ap_block_state156_pp0_stage10_iter9 : BOOLEAN;
signal ap_block_state172_pp0_stage10_iter10 : BOOLEAN;
signal ap_block_state188_pp0_stage10_iter11 : BOOLEAN;
signal ap_block_state204_pp0_stage10_iter12 : BOOLEAN;
signal ap_block_state220_pp0_stage10_iter13 : BOOLEAN;
signal ap_block_state236_pp0_stage10_iter14 : BOOLEAN;
signal ap_block_pp0_stage10_flag00011001 : BOOLEAN;
signal tmp_33_fu_1325_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_33_reg_2719 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_61_fu_1329_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_61_reg_2724 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_62_fu_1333_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_62_reg_2729 : STD_LOGIC_VECTOR (11 downto 0);
signal grp_fu_1218_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_83_reg_2734 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_121_fu_1370_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_121_reg_2749 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_16_fu_1374_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_16_reg_2754 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_CS_fsm_pp0_stage11 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage11 : signal is "none";
signal ap_block_state13_pp0_stage11_iter0 : BOOLEAN;
signal ap_block_state29_pp0_stage11_iter1 : BOOLEAN;
signal ap_block_state45_pp0_stage11_iter2 : BOOLEAN;
signal ap_block_state61_pp0_stage11_iter3 : BOOLEAN;
signal ap_block_state77_pp0_stage11_iter4 : BOOLEAN;
signal ap_block_state93_pp0_stage11_iter5 : BOOLEAN;
signal ap_block_state109_pp0_stage11_iter6 : BOOLEAN;
signal ap_block_state125_pp0_stage11_iter7 : BOOLEAN;
signal ap_block_state141_pp0_stage11_iter8 : BOOLEAN;
signal ap_block_state157_pp0_stage11_iter9 : BOOLEAN;
signal ap_block_state173_pp0_stage11_iter10 : BOOLEAN;
signal ap_block_state189_pp0_stage11_iter11 : BOOLEAN;
signal ap_block_state205_pp0_stage11_iter12 : BOOLEAN;
signal ap_block_state221_pp0_stage11_iter13 : BOOLEAN;
signal ap_block_state237_pp0_stage11_iter14 : BOOLEAN;
signal ap_block_pp0_stage11_flag00011001 : BOOLEAN;
signal tmp_34_fu_1383_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_34_reg_2764 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_63_fu_1394_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_63_reg_2769 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_69_fu_1399_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_69_reg_2774 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_70_fu_1403_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_70_reg_2779 : STD_LOGIC_VECTOR (11 downto 0);
signal grp_fu_1290_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_91_reg_2784 : STD_LOGIC_VECTOR (63 downto 0);
signal bufw_load_reg_2804 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_load_reg_2809 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_17_fu_1444_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_17_reg_2814 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_CS_fsm_pp0_stage12 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage12 : signal is "none";
signal ap_block_state14_pp0_stage12_iter0 : BOOLEAN;
signal ap_block_state30_pp0_stage12_iter1 : BOOLEAN;
signal ap_block_state46_pp0_stage12_iter2 : BOOLEAN;
signal ap_block_state62_pp0_stage12_iter3 : BOOLEAN;
signal ap_block_state78_pp0_stage12_iter4 : BOOLEAN;
signal ap_block_state94_pp0_stage12_iter5 : BOOLEAN;
signal ap_block_state110_pp0_stage12_iter6 : BOOLEAN;
signal ap_block_state126_pp0_stage12_iter7 : BOOLEAN;
signal ap_block_state142_pp0_stage12_iter8 : BOOLEAN;
signal ap_block_state158_pp0_stage12_iter9 : BOOLEAN;
signal ap_block_state174_pp0_stage12_iter10 : BOOLEAN;
signal ap_block_state190_pp0_stage12_iter11 : BOOLEAN;
signal ap_block_state206_pp0_stage12_iter12 : BOOLEAN;
signal ap_block_state222_pp0_stage12_iter13 : BOOLEAN;
signal ap_block_state238_pp0_stage12_iter14 : BOOLEAN;
signal ap_block_pp0_stage12_flag00011001 : BOOLEAN;
signal tmp_35_fu_1453_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_35_reg_2824 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_64_fu_1457_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_64_reg_2829 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_71_fu_1468_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_71_reg_2834 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_77_fu_1473_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_77_reg_2839 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_78_fu_1477_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_78_reg_2844 : STD_LOGIC_VECTOR (11 downto 0);
signal grp_fu_1364_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_99_reg_2849 : STD_LOGIC_VECTOR (63 downto 0);
signal bufi_load_reg_2924 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_18_fu_1688_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_18_reg_2929 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_CS_fsm_pp0_stage13 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage13 : signal is "none";
signal ap_block_state15_pp0_stage13_iter0 : BOOLEAN;
signal ap_block_state31_pp0_stage13_iter1 : BOOLEAN;
signal ap_block_state47_pp0_stage13_iter2 : BOOLEAN;
signal ap_block_state63_pp0_stage13_iter3 : BOOLEAN;
signal ap_block_state79_pp0_stage13_iter4 : BOOLEAN;
signal ap_block_state95_pp0_stage13_iter5 : BOOLEAN;
signal ap_block_state111_pp0_stage13_iter6 : BOOLEAN;
signal ap_block_state127_pp0_stage13_iter7 : BOOLEAN;
signal ap_block_state143_pp0_stage13_iter8 : BOOLEAN;
signal ap_block_state159_pp0_stage13_iter9 : BOOLEAN;
signal ap_block_state175_pp0_stage13_iter10 : BOOLEAN;
signal ap_block_state191_pp0_stage13_iter11 : BOOLEAN;
signal ap_block_state207_pp0_stage13_iter12 : BOOLEAN;
signal ap_block_state223_pp0_stage13_iter13 : BOOLEAN;
signal ap_block_state239_pp0_stage13_iter14 : BOOLEAN;
signal ap_block_pp0_stage13_flag00011001 : BOOLEAN;
signal tmp_36_fu_1697_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_36_reg_2939 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_72_fu_1705_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_72_reg_2949 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_79_fu_1716_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_79_reg_2954 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_85_fu_1721_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_85_reg_2959 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_86_fu_1725_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_86_reg_2964 : STD_LOGIC_VECTOR (11 downto 0);
signal grp_fu_1434_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_107_reg_2969 : STD_LOGIC_VECTOR (63 downto 0);
signal bufi_load_1_reg_2974 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_load_8_reg_2979 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_fu_1733_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_19_reg_2984 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_CS_fsm_pp0_stage14 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage14 : signal is "none";
signal ap_block_state16_pp0_stage14_iter0 : BOOLEAN;
signal ap_block_state32_pp0_stage14_iter1 : BOOLEAN;
signal ap_block_state48_pp0_stage14_iter2 : BOOLEAN;
signal ap_block_state64_pp0_stage14_iter3 : BOOLEAN;
signal ap_block_state80_pp0_stage14_iter4 : BOOLEAN;
signal ap_block_state96_pp0_stage14_iter5 : BOOLEAN;
signal ap_block_state112_pp0_stage14_iter6 : BOOLEAN;
signal ap_block_state128_pp0_stage14_iter7 : BOOLEAN;
signal ap_block_state144_pp0_stage14_iter8 : BOOLEAN;
signal ap_block_state160_pp0_stage14_iter9 : BOOLEAN;
signal ap_block_state176_pp0_stage14_iter10 : BOOLEAN;
signal ap_block_state192_pp0_stage14_iter11 : BOOLEAN;
signal ap_block_state208_pp0_stage14_iter12 : BOOLEAN;
signal ap_block_state224_pp0_stage14_iter13 : BOOLEAN;
signal ap_block_state240_pp0_stage14_iter14 : BOOLEAN;
signal ap_block_pp0_stage14_flag00011001 : BOOLEAN;
signal tmp_37_fu_1742_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_37_reg_2994 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_80_fu_1750_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_80_reg_3004 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_87_fu_1761_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_87_reg_3009 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_93_fu_1766_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_93_reg_3014 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_94_fu_1770_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_94_reg_3019 : STD_LOGIC_VECTOR (11 downto 0);
signal grp_fu_1508_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_124_reg_3024 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_1537_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_131_reg_3029 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_1566_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_138_reg_3034 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_1595_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_145_reg_3039 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_1624_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_152_reg_3044 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_1653_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_159_reg_3049 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_1682_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_166_reg_3054 : STD_LOGIC_VECTOR (63 downto 0);
signal bufi_load_2_reg_3059 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_fu_1778_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_20_reg_3064 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_CS_fsm_pp0_stage15 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage15 : signal is "none";
signal ap_block_state17_pp0_stage15_iter0 : BOOLEAN;
signal ap_block_state33_pp0_stage15_iter1 : BOOLEAN;
signal ap_block_state49_pp0_stage15_iter2 : BOOLEAN;
signal ap_block_state65_pp0_stage15_iter3 : BOOLEAN;
signal ap_block_state81_pp0_stage15_iter4 : BOOLEAN;
signal ap_block_state97_pp0_stage15_iter5 : BOOLEAN;
signal ap_block_state113_pp0_stage15_iter6 : BOOLEAN;
signal ap_block_state129_pp0_stage15_iter7 : BOOLEAN;
signal ap_block_state145_pp0_stage15_iter8 : BOOLEAN;
signal ap_block_state161_pp0_stage15_iter9 : BOOLEAN;
signal ap_block_state177_pp0_stage15_iter10 : BOOLEAN;
signal ap_block_state193_pp0_stage15_iter11 : BOOLEAN;
signal ap_block_state209_pp0_stage15_iter12 : BOOLEAN;
signal ap_block_state225_pp0_stage15_iter13 : BOOLEAN;
signal ap_block_state241_pp0_stage15_iter14 : BOOLEAN;
signal ap_block_pp0_stage15_flag00011001 : BOOLEAN;
signal tmp_38_fu_1787_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_38_reg_3074 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_88_fu_1795_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_88_reg_3084 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_95_fu_1806_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_95_reg_3089 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_101_fu_1811_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_101_reg_3094 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_102_fu_1815_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_102_reg_3099 : STD_LOGIC_VECTOR (11 downto 0);
signal bufw_load_1_reg_3104 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_load_3_reg_3109 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_21_fu_1847_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_21_reg_3114 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_39_fu_1856_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_39_reg_3124 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_96_fu_1864_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_96_reg_3134 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_103_fu_1875_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_103_reg_3139 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_109_fu_1880_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_109_reg_3144 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_115_fu_1884_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_115_reg_3149 : STD_LOGIC_VECTOR (11 downto 0);
signal bufw_load_2_reg_3154 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
signal bufi_load_4_reg_3159 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_22_fu_1888_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_22_reg_3164 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_40_fu_1897_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_40_reg_3174 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_104_fu_1905_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_104_reg_3184 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_110_fu_1916_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_110_reg_3189 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_126_fu_1921_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_126_reg_3194 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_133_fu_1925_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_133_reg_3199 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_140_fu_1929_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_140_reg_3204 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_147_fu_1933_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_147_reg_3209 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_154_fu_1937_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_154_reg_3214 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_161_fu_1941_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_161_reg_3219 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_168_fu_1945_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_168_reg_3224 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_172_fu_1949_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_172_reg_3229 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_173_fu_1953_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_173_reg_3234 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_175_fu_1957_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_175_reg_3239 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_176_fu_1961_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_176_reg_3244 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_177_fu_1965_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_177_reg_3249 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_178_fu_1969_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_178_reg_3254 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_179_fu_1973_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_179_reg_3259 : STD_LOGIC_VECTOR (11 downto 0);
signal bufw_load_3_reg_3264 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_load_5_reg_3269 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_23_fu_1977_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_23_reg_3274 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_41_fu_1986_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_41_reg_3284 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_111_fu_1994_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_111_reg_3294 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_127_fu_2005_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_127_reg_3299 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_134_fu_2017_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_134_reg_3304 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_141_fu_2029_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_141_reg_3309 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_148_fu_2041_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_148_reg_3314 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_155_fu_2053_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_155_reg_3319 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_162_fu_2065_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_162_reg_3324 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_169_fu_2077_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_169_reg_3329 : STD_LOGIC_VECTOR (13 downto 0);
signal bufw_load_4_reg_3334 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_load_6_reg_3339 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_24_fu_2082_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_24_reg_3344 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_42_fu_2091_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_42_reg_3354 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_128_fu_2099_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_128_reg_3364 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_135_fu_2103_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_135_reg_3369 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_142_fu_2107_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_142_reg_3374 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_149_fu_2111_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_149_reg_3379 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_156_fu_2115_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_156_reg_3384 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_163_fu_2119_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_163_reg_3389 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_170_fu_2123_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_170_reg_3394 : STD_LOGIC_VECTOR (13 downto 0);
signal bufw_load_5_reg_3399 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_load_7_reg_3404 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_25_fu_2127_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_25_reg_3409 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_43_fu_2136_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_43_reg_3419 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_571_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_8_reg_3429 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_load_6_reg_3434 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_load_8_reg_3439 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_26_fu_2144_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_26_reg_3444 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_44_fu_2153_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_44_reg_3454 : STD_LOGIC_VECTOR (15 downto 0);
signal bufw_load_7_reg_3464 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_load_9_reg_3469 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_27_fu_2161_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_27_reg_3474 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_28_fu_2166_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_28_reg_3479 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_45_fu_2175_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_45_reg_3489 : STD_LOGIC_VECTOR (15 downto 0);
signal bufw_load_9_reg_3499 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_load_10_reg_3504 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_46_fu_2187_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_46_reg_3514 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_47_fu_2191_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_47_reg_3519 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_8_1_reg_3529 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_load_10_reg_3534 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_load_11_reg_3539 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_8_2_reg_3554 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_8_2_reg_3554 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_load_11_reg_3559 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_load_12_reg_3564 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_8_3_reg_3574 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_8_3_reg_3574 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_8_3_reg_3574 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_load_12_reg_3579 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_load_13_reg_3584 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_8_4_reg_3594 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_8_4_reg_3594 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_8_4_reg_3594 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_8_4_reg_3594 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_load_13_reg_3599 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_load_14_reg_3604 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_8_5_reg_3609 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_8_5_reg_3609 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_8_5_reg_3609 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_8_5_reg_3609 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_load_15_reg_3614 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_8_6_reg_3624 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_8_6_reg_3624 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_8_6_reg_3624 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_8_6_reg_3624 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_8_6_reg_3624 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_load_14_reg_3629 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_8_7_reg_3634 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_8_7_reg_3634 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_8_7_reg_3634 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_8_7_reg_3634 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_8_7_reg_3634 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_8_7_reg_3634 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_8_8_reg_3639 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_8_8_reg_3639 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_8_8_reg_3639 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_8_8_reg_3639 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_8_8_reg_3639 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_8_8_reg_3639 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_8_8_reg_3639 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_load_15_reg_3644 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_8_9_reg_3649 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_8_9_reg_3649 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_8_9_reg_3649 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_8_9_reg_3649 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_8_9_reg_3649 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_8_9_reg_3649 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_8_9_reg_3649 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_8_9_reg_3649 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_8_s_reg_3654 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter2 : STD_LOGIC := '0';
signal ap_reg_pp0_iter3_tmp_8_s_reg_3654 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_8_s_reg_3654 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_8_s_reg_3654 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_8_s_reg_3654 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_8_s_reg_3654 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_8_s_reg_3654 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_8_s_reg_3654 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_8_s_reg_3654 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_8_10_reg_3659 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_8_10_reg_3659 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_8_10_reg_3659 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_8_10_reg_3659 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_8_10_reg_3659 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_8_10_reg_3659 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_8_10_reg_3659 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_8_10_reg_3659 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_8_10_reg_3659 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_reg_3664 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_8_11_reg_3669 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_8_11_reg_3669 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_8_11_reg_3669 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_8_11_reg_3669 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_8_11_reg_3669 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_8_11_reg_3669 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_8_11_reg_3669 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_8_11_reg_3669 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_8_11_reg_3669 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_8_11_reg_3669 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_8_12_reg_3674 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_8_12_reg_3674 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_8_12_reg_3674 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_8_12_reg_3674 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_8_12_reg_3674 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_8_12_reg_3674 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_8_12_reg_3674 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_8_12_reg_3674 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_8_12_reg_3674 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_8_12_reg_3674 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter12_tmp_8_12_reg_3674 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_8_13_reg_3679 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_8_13_reg_3679 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_8_13_reg_3679 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_8_13_reg_3679 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_8_13_reg_3679 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_8_13_reg_3679 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_8_13_reg_3679 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_8_13_reg_3679 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_8_13_reg_3679 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_8_13_reg_3679 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter12_tmp_8_13_reg_3679 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter13_tmp_8_13_reg_3679 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_8_14_reg_3684 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_8_14_reg_3684 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_8_14_reg_3684 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_8_14_reg_3684 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_8_14_reg_3684 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_8_14_reg_3684 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_8_14_reg_3684 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_8_14_reg_3684 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_8_14_reg_3684 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_8_14_reg_3684 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter12_tmp_8_14_reg_3684 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter13_tmp_8_14_reg_3684 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter14_tmp_8_14_reg_3684 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_1_reg_3689 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter3 : STD_LOGIC := '0';
signal tmp_10_2_reg_3694 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_3_reg_3699 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter4 : STD_LOGIC := '0';
signal tmp_10_4_reg_3704 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter5 : STD_LOGIC := '0';
signal tmp_10_5_reg_3709 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter6 : STD_LOGIC := '0';
signal tmp_10_7_reg_3714 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter8 : STD_LOGIC := '0';
signal tmp_10_8_reg_3719 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter9 : STD_LOGIC := '0';
signal tmp_10_9_reg_3724 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter10 : STD_LOGIC := '0';
signal tmp_10_s_reg_3729 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_10_reg_3734 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter11 : STD_LOGIC := '0';
signal tmp_10_11_reg_3739 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter12 : STD_LOGIC := '0';
signal tmp_10_12_reg_3744 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter13 : STD_LOGIC := '0';
signal tmp_10_13_reg_3749 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter14 : STD_LOGIC := '0';
signal ap_block_pp0_stage0_flag00011011 : BOOLEAN;
signal ap_condition_pp0_exit_iter0_state2 : STD_LOGIC;
signal ap_block_pp0_stage15_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage6_flag00011011 : BOOLEAN;
signal indvar_flatten1_phi_fu_465_p4 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_block_pp0_stage0_flag00000000 : BOOLEAN;
signal i_phi_fu_476_p4 : STD_LOGIC_VECTOR (2 downto 0);
signal indvar_flatten2_phi_fu_488_p4 : STD_LOGIC_VECTOR (15 downto 0);
signal j_phi_fu_499_p4 : STD_LOGIC_VECTOR (2 downto 0);
signal indvar_flatten3_phi_fu_511_p4 : STD_LOGIC_VECTOR (13 downto 0);
signal row_b_phi_fu_523_p4 : STD_LOGIC_VECTOR (4 downto 0);
signal indvar_flatten_phi_fu_535_p4 : STD_LOGIC_VECTOR (9 downto 0);
signal ap_block_pp0_stage1_flag00000000 : BOOLEAN;
signal col_b_phi_fu_547_p4 : STD_LOGIC_VECTOR (4 downto 0);
signal to_b_phi_fu_559_p4 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_block_pp0_stage2_flag00000000 : BOOLEAN;
signal tmp_174_cast_fu_1241_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_block_pp0_stage8_flag00000000 : BOOLEAN;
signal tmp_62_cast_fu_1259_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_block_pp0_stage9_flag00000000 : BOOLEAN;
signal tmp_35_cast_fu_1321_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_block_pp0_stage10_flag00000000 : BOOLEAN;
signal tmp_36_cast_fu_1379_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_block_pp0_stage11_flag00000000 : BOOLEAN;
signal tmp_121_cast_fu_1440_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_37_cast_fu_1449_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_block_pp0_stage12_flag00000000 : BOOLEAN;
signal tmp_38_cast_fu_1693_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_block_pp0_stage13_flag00000000 : BOOLEAN;
signal tmp_69_cast_fu_1701_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_39_cast_fu_1738_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_block_pp0_stage14_flag00000000 : BOOLEAN;
signal tmp_76_cast_fu_1746_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_40_cast_fu_1783_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_block_pp0_stage15_flag00000000 : BOOLEAN;
signal tmp_83_cast_fu_1791_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_41_cast_fu_1852_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_90_cast_fu_1860_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_42_cast_fu_1893_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_97_cast_fu_1901_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_43_cast_fu_1982_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_104_cast_fu_1990_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_44_cast_fu_2087_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_block_pp0_stage3_flag00000000 : BOOLEAN;
signal tmp_111_cast_fu_2095_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_45_cast_fu_2132_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_block_pp0_stage4_flag00000000 : BOOLEAN;
signal tmp_128_cast_fu_2140_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_46_cast_fu_2149_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_block_pp0_stage5_flag00000000 : BOOLEAN;
signal tmp_135_cast_fu_2157_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_47_cast_fu_2171_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_block_pp0_stage6_flag00000000 : BOOLEAN;
signal tmp_142_cast_fu_2179_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_48_cast_fu_2183_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_block_pp0_stage7_flag00000000 : BOOLEAN;
signal tmp_149_cast_fu_2195_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_49_cast_fu_2199_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_156_cast_fu_2203_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_50_cast_fu_2207_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_163_cast_fu_2211_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_170_cast_fu_2215_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal bufw_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_567_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_567_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_571_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_571_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_fu_589_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal i_cast7_fu_581_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_5_cast_fu_595_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_1_fu_605_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal j_cast5_fu_585_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_9_cast_fu_611_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal exitcond_flatten43_n_fu_662_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond_flatten_mid_fu_684_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_2_mid_fu_704_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_fu_717_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_2_mid1_fu_712_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_exitcond_flatten_2_fu_726_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_29_fu_774_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_30_fu_778_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_49_fu_835_p3 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_52_cast_fu_831_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal p_shl3_cast_fu_842_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_50_fu_846_p2 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_57_fu_866_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal grp_fu_890_p0 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_890_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_112_fu_896_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal grp_fu_920_p0 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_920_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_6_cast_mid_cast_fu_934_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal i_cast7_mid2_cast_fu_931_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_6_cast_mid3_fu_937_p3 : STD_LOGIC_VECTOR (5 downto 0);
signal j_cast4_mid1_cast_fu_952_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_cast_mid_fu_943_p3 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_9_fu_974_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_5_cast_mid1_fu_979_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal j_cast5_mid2_cast_fu_949_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_cast_mid3_fu_962_p3 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_31_fu_1001_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_9_cast_mid1_fu_1006_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_65_fu_1020_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal grp_fu_1043_p0 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_1043_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_54_fu_1065_p3 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_59_cast_fu_1071_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal p_shl34_cast_fu_1075_p4 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_73_fu_1089_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal grp_fu_1112_p0 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_1112_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_920_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_52_cast1_fu_1062_p1 : STD_LOGIC_VECTOR (9 downto 0);
signal row_b_cast3_mid2_cas_fu_1049_p1 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_11_fu_1154_p3 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_12_fu_1165_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal p_shl2_cast_fu_1172_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal p_shl1_cast_fu_1161_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1190_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_81_fu_1195_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal grp_fu_1218_p0 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_1218_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_173_cast_fu_1228_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal col_b_cast2_mid2_cas_fu_1182_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_174_fu_1235_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_89_fu_1267_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal grp_fu_1290_p0 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_1290_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_118_cast_fu_1296_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal p_shl18_cast_fu_1302_p4 : STD_LOGIC_VECTOR (13 downto 0);
signal grp_fu_1190_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_97_fu_1341_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal grp_fu_1364_p0 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_1364_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal p_shl32_cast_fu_1387_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal grp_fu_1263_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_105_fu_1411_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal grp_fu_1434_p0 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_1434_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal p_shl30_cast_fu_1461_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal grp_fu_1337_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_122_fu_1485_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal grp_fu_1508_p0 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_1508_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_129_fu_1514_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal grp_fu_1537_p0 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_1537_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_136_fu_1543_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal grp_fu_1566_p0 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_1566_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_143_fu_1572_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal grp_fu_1595_p0 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_1595_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_150_fu_1601_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal grp_fu_1624_p0 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_1624_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_157_fu_1630_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal grp_fu_1653_p0 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_1653_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_164_fu_1659_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal grp_fu_1682_p0 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_1682_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal p_shl28_cast_fu_1709_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal grp_fu_1407_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal p_shl26_cast_fu_1754_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal grp_fu_1481_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal p_shl24_cast_fu_1799_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal grp_fu_1729_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal p_shl22_cast_fu_1868_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal grp_fu_1774_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal p_shl20_cast_fu_1909_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal grp_fu_1819_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_1823_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_1827_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_1831_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_1835_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_1839_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_1843_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal p_shl16_cast_fu_1998_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal p_shl14_cast_fu_2010_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal p_shl12_cast_fu_2022_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal p_shl10_cast_fu_2034_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal p_shl8_cast_fu_2046_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal p_shl6_cast_fu_2058_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal p_shl_cast_fu_2070_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal ap_CS_fsm_state249 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state249 : signal is "none";
signal ap_NS_fsm : STD_LOGIC_VECTOR (17 downto 0);
signal ap_block_pp0_stage1_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage2_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage3_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage4_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage5_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage7_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage8_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage9_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage10_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage11_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage12_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage13_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage14_flag00011011 : BOOLEAN;
signal ap_idle_pp0 : STD_LOGIC;
signal ap_enable_pp0 : STD_LOGIC;
component convolve_kernel_fbkb IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component convolve_kernel_fcud IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component convolve_kernel_adEe IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component convolve_kernel_control_s_axi IS
generic (
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER );
port (
AWVALID : IN STD_LOGIC;
AWREADY : OUT STD_LOGIC;
AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
WVALID : IN STD_LOGIC;
WREADY : OUT STD_LOGIC;
WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0);
ARVALID : IN STD_LOGIC;
ARREADY : OUT STD_LOGIC;
ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
RVALID : OUT STD_LOGIC;
RREADY : IN STD_LOGIC;
RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
BVALID : OUT STD_LOGIC;
BREADY : IN STD_LOGIC;
BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
ACLK_EN : IN STD_LOGIC;
ap_start : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
ap_ready : IN STD_LOGIC;
ap_done : IN STD_LOGIC;
ap_idle : IN STD_LOGIC );
end component;
begin
convolve_kernel_control_s_axi_U : component convolve_kernel_control_s_axi
generic map (
C_S_AXI_ADDR_WIDTH => C_S_AXI_CONTROL_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_CONTROL_DATA_WIDTH)
port map (
AWVALID => s_axi_control_AWVALID,
AWREADY => s_axi_control_AWREADY,
AWADDR => s_axi_control_AWADDR,
WVALID => s_axi_control_WVALID,
WREADY => s_axi_control_WREADY,
WDATA => s_axi_control_WDATA,
WSTRB => s_axi_control_WSTRB,
ARVALID => s_axi_control_ARVALID,
ARREADY => s_axi_control_ARREADY,
ARADDR => s_axi_control_ARADDR,
RVALID => s_axi_control_RVALID,
RREADY => s_axi_control_RREADY,
RDATA => s_axi_control_RDATA,
RRESP => s_axi_control_RRESP,
BVALID => s_axi_control_BVALID,
BREADY => s_axi_control_BREADY,
BRESP => s_axi_control_BRESP,
ACLK => ap_clk,
ARESET => ap_rst_n_inv,
ACLK_EN => ap_const_logic_1,
ap_start => ap_start,
interrupt => interrupt,
ap_ready => ap_ready,
ap_done => ap_done,
ap_idle => ap_idle);
convolve_kernel_fbkb_U1 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_567_p0,
din1 => grp_fu_567_p1,
ce => ap_const_logic_1,
dout => grp_fu_567_p2);
convolve_kernel_fcud_U2 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_571_p0,
din1 => grp_fu_571_p1,
ce => ap_const_logic_1,
dout => grp_fu_571_p2);
convolve_kernel_adEe_U3 : component convolve_kernel_adEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_890_p0,
din1 => grp_fu_890_p1,
ce => ap_const_logic_1,
dout => grp_fu_890_p2);
convolve_kernel_adEe_U4 : component convolve_kernel_adEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_920_p0,
din1 => grp_fu_920_p1,
ce => ap_const_logic_1,
dout => grp_fu_920_p2);
convolve_kernel_adEe_U5 : component convolve_kernel_adEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1043_p0,
din1 => grp_fu_1043_p1,
ce => ap_const_logic_1,
dout => grp_fu_1043_p2);
convolve_kernel_adEe_U6 : component convolve_kernel_adEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1112_p0,
din1 => grp_fu_1112_p1,
ce => ap_const_logic_1,
dout => grp_fu_1112_p2);
convolve_kernel_adEe_U7 : component convolve_kernel_adEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => tmp_59_reg_2532,
din1 => grp_fu_1190_p1,
ce => ap_const_logic_1,
dout => grp_fu_1190_p2);
convolve_kernel_adEe_U8 : component convolve_kernel_adEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1218_p0,
din1 => grp_fu_1218_p1,
ce => ap_const_logic_1,
dout => grp_fu_1218_p2);
convolve_kernel_adEe_U9 : component convolve_kernel_adEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => tmp_67_reg_2629,
din1 => i_cast6_mid2_reg_2567,
ce => ap_const_logic_1,
dout => grp_fu_1263_p2);
convolve_kernel_adEe_U10 : component convolve_kernel_adEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1290_p0,
din1 => grp_fu_1290_p1,
ce => ap_const_logic_1,
dout => grp_fu_1290_p2);
convolve_kernel_adEe_U11 : component convolve_kernel_adEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => tmp_75_reg_2689,
din1 => i_cast6_mid2_reg_2567,
ce => ap_const_logic_1,
dout => grp_fu_1337_p2);
convolve_kernel_adEe_U12 : component convolve_kernel_adEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1364_p0,
din1 => grp_fu_1364_p1,
ce => ap_const_logic_1,
dout => grp_fu_1364_p2);
convolve_kernel_adEe_U13 : component convolve_kernel_adEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => tmp_83_reg_2734,
din1 => i_cast6_mid2_reg_2567,
ce => ap_const_logic_1,
dout => grp_fu_1407_p2);
convolve_kernel_adEe_U14 : component convolve_kernel_adEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1434_p0,
din1 => grp_fu_1434_p1,
ce => ap_const_logic_1,
dout => grp_fu_1434_p2);
convolve_kernel_adEe_U15 : component convolve_kernel_adEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => tmp_91_reg_2784,
din1 => i_cast6_mid2_reg_2567,
ce => ap_const_logic_1,
dout => grp_fu_1481_p2);
convolve_kernel_adEe_U16 : component convolve_kernel_adEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1508_p0,
din1 => grp_fu_1508_p1,
ce => ap_const_logic_1,
dout => grp_fu_1508_p2);
convolve_kernel_adEe_U17 : component convolve_kernel_adEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1537_p0,
din1 => grp_fu_1537_p1,
ce => ap_const_logic_1,
dout => grp_fu_1537_p2);
convolve_kernel_adEe_U18 : component convolve_kernel_adEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1566_p0,
din1 => grp_fu_1566_p1,
ce => ap_const_logic_1,
dout => grp_fu_1566_p2);
convolve_kernel_adEe_U19 : component convolve_kernel_adEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1595_p0,
din1 => grp_fu_1595_p1,
ce => ap_const_logic_1,
dout => grp_fu_1595_p2);
convolve_kernel_adEe_U20 : component convolve_kernel_adEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1624_p0,
din1 => grp_fu_1624_p1,
ce => ap_const_logic_1,
dout => grp_fu_1624_p2);
convolve_kernel_adEe_U21 : component convolve_kernel_adEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1653_p0,
din1 => grp_fu_1653_p1,
ce => ap_const_logic_1,
dout => grp_fu_1653_p2);
convolve_kernel_adEe_U22 : component convolve_kernel_adEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1682_p0,
din1 => grp_fu_1682_p1,
ce => ap_const_logic_1,
dout => grp_fu_1682_p2);
convolve_kernel_adEe_U23 : component convolve_kernel_adEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => tmp_99_reg_2849,
din1 => i_cast6_mid2_reg_2567,
ce => ap_const_logic_1,
dout => grp_fu_1729_p2);
convolve_kernel_adEe_U24 : component convolve_kernel_adEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => tmp_107_reg_2969,
din1 => i_cast6_mid2_reg_2567,
ce => ap_const_logic_1,
dout => grp_fu_1774_p2);
convolve_kernel_adEe_U25 : component convolve_kernel_adEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => tmp_124_reg_3024,
din1 => i_cast6_mid2_reg_2567,
ce => ap_const_logic_1,
dout => grp_fu_1819_p2);
convolve_kernel_adEe_U26 : component convolve_kernel_adEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => tmp_131_reg_3029,
din1 => i_cast6_mid2_reg_2567,
ce => ap_const_logic_1,
dout => grp_fu_1823_p2);
convolve_kernel_adEe_U27 : component convolve_kernel_adEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => tmp_138_reg_3034,
din1 => i_cast6_mid2_reg_2567,
ce => ap_const_logic_1,
dout => grp_fu_1827_p2);
convolve_kernel_adEe_U28 : component convolve_kernel_adEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => tmp_145_reg_3039,
din1 => i_cast6_mid2_reg_2567,
ce => ap_const_logic_1,
dout => grp_fu_1831_p2);
convolve_kernel_adEe_U29 : component convolve_kernel_adEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => tmp_152_reg_3044,
din1 => i_cast6_mid2_reg_2567,
ce => ap_const_logic_1,
dout => grp_fu_1835_p2);
convolve_kernel_adEe_U30 : component convolve_kernel_adEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => tmp_159_reg_3049,
din1 => i_cast6_mid2_reg_2567,
ce => ap_const_logic_1,
dout => grp_fu_1839_p2);
convolve_kernel_adEe_U31 : component convolve_kernel_adEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => tmp_166_reg_3054,
din1 => i_cast6_mid2_reg_2567,
ce => ap_const_logic_1,
dout => grp_fu_1843_p2);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_enable_reg_pp0_iter0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state2))) then
ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_enable_reg_pp0_iter0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011011 = ap_const_boolean_0))) then
if ((ap_const_logic_1 = ap_condition_pp0_exit_iter0_state2)) then
ap_enable_reg_pp0_iter1 <= (ap_condition_pp0_exit_iter0_state2 xor ap_const_logic_1);
elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then
ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
end if;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter10_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_enable_reg_pp0_iter10 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter10 <= ap_enable_reg_pp0_iter9;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter11_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_enable_reg_pp0_iter11 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter11 <= ap_enable_reg_pp0_iter10;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter12_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_enable_reg_pp0_iter12 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter12 <= ap_enable_reg_pp0_iter11;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter13_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_enable_reg_pp0_iter13 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter13 <= ap_enable_reg_pp0_iter12;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter14_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_enable_reg_pp0_iter14 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter14 <= ap_enable_reg_pp0_iter13;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter15_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_enable_reg_pp0_iter15 <= ap_const_logic_0;
else
if ((((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011011 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011011 = ap_const_boolean_0)))) then
ap_enable_reg_pp0_iter15 <= ap_enable_reg_pp0_iter14;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_enable_reg_pp0_iter15 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_enable_reg_pp0_iter2 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter3_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_enable_reg_pp0_iter3 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter4_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_enable_reg_pp0_iter4 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter5_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_enable_reg_pp0_iter5 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter6_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_enable_reg_pp0_iter6 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter7_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_enable_reg_pp0_iter7 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter8_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_enable_reg_pp0_iter8 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter9_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_enable_reg_pp0_iter9 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter9 <= ap_enable_reg_pp0_iter8;
end if;
end if;
end if;
end process;
col_b_reg_543_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (exitcond_flatten3_reg_2229 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
col_b_reg_543 <= col_b_cast2_mid2_reg_2489;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
col_b_reg_543 <= ap_const_lv5_0;
end if;
end if;
end process;
i_reg_472_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (exitcond_flatten3_reg_2229 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
i_reg_472 <= i_cast7_mid2_reg_2386;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
i_reg_472 <= ap_const_lv3_0;
end if;
end if;
end process;
indvar_flatten1_reg_461_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (exitcond_flatten3_reg_2229 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
indvar_flatten1_reg_461 <= indvar_flatten_next3_reg_2233;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
indvar_flatten1_reg_461 <= ap_const_lv17_0;
end if;
end if;
end process;
indvar_flatten2_reg_484_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (exitcond_flatten3_reg_2229 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
indvar_flatten2_reg_484 <= indvar_flatten_next2_reg_2280;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
indvar_flatten2_reg_484 <= ap_const_lv16_0;
end if;
end if;
end process;
indvar_flatten3_reg_507_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (exitcond_flatten3_reg_2229 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
indvar_flatten3_reg_507 <= indvar_flatten_next1_reg_2381;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
indvar_flatten3_reg_507 <= ap_const_lv14_0;
end if;
end if;
end process;
indvar_flatten_reg_531_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_lv1_0 = ap_reg_pp0_iter1_exitcond_flatten3_reg_2229))) then
indvar_flatten_reg_531 <= indvar_flatten_next_reg_2376;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
indvar_flatten_reg_531 <= ap_const_lv10_0;
end if;
end if;
end process;
j_reg_495_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (exitcond_flatten3_reg_2229 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
j_reg_495 <= j_cast5_mid2_reg_2395;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
j_reg_495 <= ap_const_lv3_0;
end if;
end if;
end process;
row_b_reg_519_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (exitcond_flatten3_reg_2229 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
row_b_reg_519 <= row_b_cast3_mid2_reg_2473;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
row_b_reg_519 <= ap_const_lv5_0;
end if;
end if;
end process;
to_b_reg_555_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_lv1_0 = ap_reg_pp0_iter1_exitcond_flatten3_reg_2229))) then
to_b_reg_555 <= to_b_1_reg_2463;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
to_b_reg_555 <= ap_const_lv5_0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0))) then
ap_reg_pp0_iter10_bufo_addr_reg_2650 <= ap_reg_pp0_iter9_bufo_addr_reg_2650;
ap_reg_pp0_iter11_bufo_addr_reg_2650 <= ap_reg_pp0_iter10_bufo_addr_reg_2650;
ap_reg_pp0_iter12_bufo_addr_reg_2650 <= ap_reg_pp0_iter11_bufo_addr_reg_2650;
ap_reg_pp0_iter13_bufo_addr_reg_2650 <= ap_reg_pp0_iter12_bufo_addr_reg_2650;
ap_reg_pp0_iter14_bufo_addr_reg_2650 <= ap_reg_pp0_iter13_bufo_addr_reg_2650;
ap_reg_pp0_iter1_bufo_addr_reg_2650 <= bufo_addr_reg_2650;
ap_reg_pp0_iter2_bufo_addr_reg_2650 <= ap_reg_pp0_iter1_bufo_addr_reg_2650;
ap_reg_pp0_iter2_tmp_8_2_reg_3554 <= tmp_8_2_reg_3554;
ap_reg_pp0_iter3_bufo_addr_reg_2650 <= ap_reg_pp0_iter2_bufo_addr_reg_2650;
ap_reg_pp0_iter4_bufo_addr_reg_2650 <= ap_reg_pp0_iter3_bufo_addr_reg_2650;
ap_reg_pp0_iter5_bufo_addr_reg_2650 <= ap_reg_pp0_iter4_bufo_addr_reg_2650;
ap_reg_pp0_iter6_bufo_addr_reg_2650 <= ap_reg_pp0_iter5_bufo_addr_reg_2650;
ap_reg_pp0_iter7_bufo_addr_reg_2650 <= ap_reg_pp0_iter6_bufo_addr_reg_2650;
ap_reg_pp0_iter8_bufo_addr_reg_2650 <= ap_reg_pp0_iter7_bufo_addr_reg_2650;
ap_reg_pp0_iter9_bufo_addr_reg_2650 <= ap_reg_pp0_iter8_bufo_addr_reg_2650;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
ap_reg_pp0_iter10_exitcond_flatten3_reg_2229 <= ap_reg_pp0_iter9_exitcond_flatten3_reg_2229;
ap_reg_pp0_iter10_tmp_8_s_reg_3654 <= ap_reg_pp0_iter9_tmp_8_s_reg_3654;
ap_reg_pp0_iter11_exitcond_flatten3_reg_2229 <= ap_reg_pp0_iter10_exitcond_flatten3_reg_2229;
ap_reg_pp0_iter12_exitcond_flatten3_reg_2229 <= ap_reg_pp0_iter11_exitcond_flatten3_reg_2229;
ap_reg_pp0_iter13_exitcond_flatten3_reg_2229 <= ap_reg_pp0_iter12_exitcond_flatten3_reg_2229;
ap_reg_pp0_iter14_exitcond_flatten3_reg_2229 <= ap_reg_pp0_iter13_exitcond_flatten3_reg_2229;
ap_reg_pp0_iter15_exitcond_flatten3_reg_2229 <= ap_reg_pp0_iter14_exitcond_flatten3_reg_2229;
ap_reg_pp0_iter1_exitcond_flatten3_reg_2229 <= exitcond_flatten3_reg_2229;
ap_reg_pp0_iter2_exitcond_flatten3_reg_2229 <= ap_reg_pp0_iter1_exitcond_flatten3_reg_2229;
ap_reg_pp0_iter3_exitcond_flatten3_reg_2229 <= ap_reg_pp0_iter2_exitcond_flatten3_reg_2229;
ap_reg_pp0_iter3_tmp_8_s_reg_3654 <= tmp_8_s_reg_3654;
ap_reg_pp0_iter4_exitcond_flatten3_reg_2229 <= ap_reg_pp0_iter3_exitcond_flatten3_reg_2229;
ap_reg_pp0_iter4_tmp_8_s_reg_3654 <= ap_reg_pp0_iter3_tmp_8_s_reg_3654;
ap_reg_pp0_iter5_exitcond_flatten3_reg_2229 <= ap_reg_pp0_iter4_exitcond_flatten3_reg_2229;
ap_reg_pp0_iter5_tmp_8_s_reg_3654 <= ap_reg_pp0_iter4_tmp_8_s_reg_3654;
ap_reg_pp0_iter6_exitcond_flatten3_reg_2229 <= ap_reg_pp0_iter5_exitcond_flatten3_reg_2229;
ap_reg_pp0_iter6_tmp_8_s_reg_3654 <= ap_reg_pp0_iter5_tmp_8_s_reg_3654;
ap_reg_pp0_iter7_exitcond_flatten3_reg_2229 <= ap_reg_pp0_iter6_exitcond_flatten3_reg_2229;
ap_reg_pp0_iter7_tmp_8_s_reg_3654 <= ap_reg_pp0_iter6_tmp_8_s_reg_3654;
ap_reg_pp0_iter8_exitcond_flatten3_reg_2229 <= ap_reg_pp0_iter7_exitcond_flatten3_reg_2229;
ap_reg_pp0_iter8_tmp_8_s_reg_3654 <= ap_reg_pp0_iter7_tmp_8_s_reg_3654;
ap_reg_pp0_iter9_exitcond_flatten3_reg_2229 <= ap_reg_pp0_iter8_exitcond_flatten3_reg_2229;
ap_reg_pp0_iter9_tmp_8_s_reg_3654 <= ap_reg_pp0_iter8_tmp_8_s_reg_3654;
exitcond_flatten3_reg_2229 <= exitcond_flatten3_fu_621_p2;
tmp_6_reg_2219 <= tmp_6_fu_599_p2;
tmp_s_reg_2224 <= tmp_s_fu_615_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0))) then
ap_reg_pp0_iter10_tmp_8_10_reg_3659 <= ap_reg_pp0_iter9_tmp_8_10_reg_3659;
ap_reg_pp0_iter3_tmp_8_10_reg_3659 <= tmp_8_10_reg_3659;
ap_reg_pp0_iter4_tmp_8_10_reg_3659 <= ap_reg_pp0_iter3_tmp_8_10_reg_3659;
ap_reg_pp0_iter5_tmp_8_10_reg_3659 <= ap_reg_pp0_iter4_tmp_8_10_reg_3659;
ap_reg_pp0_iter6_tmp_8_10_reg_3659 <= ap_reg_pp0_iter5_tmp_8_10_reg_3659;
ap_reg_pp0_iter7_tmp_8_10_reg_3659 <= ap_reg_pp0_iter6_tmp_8_10_reg_3659;
ap_reg_pp0_iter8_tmp_8_10_reg_3659 <= ap_reg_pp0_iter7_tmp_8_10_reg_3659;
ap_reg_pp0_iter9_tmp_8_10_reg_3659 <= ap_reg_pp0_iter8_tmp_8_10_reg_3659;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0))) then
ap_reg_pp0_iter10_tmp_8_11_reg_3669 <= ap_reg_pp0_iter9_tmp_8_11_reg_3669;
ap_reg_pp0_iter11_tmp_8_11_reg_3669 <= ap_reg_pp0_iter10_tmp_8_11_reg_3669;
ap_reg_pp0_iter3_tmp_8_11_reg_3669 <= tmp_8_11_reg_3669;
ap_reg_pp0_iter4_tmp_8_11_reg_3669 <= ap_reg_pp0_iter3_tmp_8_11_reg_3669;
ap_reg_pp0_iter5_tmp_8_11_reg_3669 <= ap_reg_pp0_iter4_tmp_8_11_reg_3669;
ap_reg_pp0_iter6_tmp_8_11_reg_3669 <= ap_reg_pp0_iter5_tmp_8_11_reg_3669;
ap_reg_pp0_iter7_tmp_8_11_reg_3669 <= ap_reg_pp0_iter6_tmp_8_11_reg_3669;
ap_reg_pp0_iter8_tmp_8_11_reg_3669 <= ap_reg_pp0_iter7_tmp_8_11_reg_3669;
ap_reg_pp0_iter9_tmp_8_11_reg_3669 <= ap_reg_pp0_iter8_tmp_8_11_reg_3669;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0))) then
ap_reg_pp0_iter10_tmp_8_12_reg_3674 <= ap_reg_pp0_iter9_tmp_8_12_reg_3674;
ap_reg_pp0_iter11_tmp_8_12_reg_3674 <= ap_reg_pp0_iter10_tmp_8_12_reg_3674;
ap_reg_pp0_iter12_tmp_8_12_reg_3674 <= ap_reg_pp0_iter11_tmp_8_12_reg_3674;
ap_reg_pp0_iter3_tmp_8_12_reg_3674 <= tmp_8_12_reg_3674;
ap_reg_pp0_iter4_tmp_8_12_reg_3674 <= ap_reg_pp0_iter3_tmp_8_12_reg_3674;
ap_reg_pp0_iter5_tmp_8_12_reg_3674 <= ap_reg_pp0_iter4_tmp_8_12_reg_3674;
ap_reg_pp0_iter6_tmp_8_12_reg_3674 <= ap_reg_pp0_iter5_tmp_8_12_reg_3674;
ap_reg_pp0_iter7_tmp_8_12_reg_3674 <= ap_reg_pp0_iter6_tmp_8_12_reg_3674;
ap_reg_pp0_iter8_tmp_8_12_reg_3674 <= ap_reg_pp0_iter7_tmp_8_12_reg_3674;
ap_reg_pp0_iter9_tmp_8_12_reg_3674 <= ap_reg_pp0_iter8_tmp_8_12_reg_3674;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0))) then
ap_reg_pp0_iter10_tmp_8_13_reg_3679 <= ap_reg_pp0_iter9_tmp_8_13_reg_3679;
ap_reg_pp0_iter11_tmp_8_13_reg_3679 <= ap_reg_pp0_iter10_tmp_8_13_reg_3679;
ap_reg_pp0_iter12_tmp_8_13_reg_3679 <= ap_reg_pp0_iter11_tmp_8_13_reg_3679;
ap_reg_pp0_iter13_tmp_8_13_reg_3679 <= ap_reg_pp0_iter12_tmp_8_13_reg_3679;
ap_reg_pp0_iter3_tmp_8_13_reg_3679 <= tmp_8_13_reg_3679;
ap_reg_pp0_iter4_tmp_8_13_reg_3679 <= ap_reg_pp0_iter3_tmp_8_13_reg_3679;
ap_reg_pp0_iter5_tmp_8_13_reg_3679 <= ap_reg_pp0_iter4_tmp_8_13_reg_3679;
ap_reg_pp0_iter6_tmp_8_13_reg_3679 <= ap_reg_pp0_iter5_tmp_8_13_reg_3679;
ap_reg_pp0_iter7_tmp_8_13_reg_3679 <= ap_reg_pp0_iter6_tmp_8_13_reg_3679;
ap_reg_pp0_iter8_tmp_8_13_reg_3679 <= ap_reg_pp0_iter7_tmp_8_13_reg_3679;
ap_reg_pp0_iter9_tmp_8_13_reg_3679 <= ap_reg_pp0_iter8_tmp_8_13_reg_3679;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0))) then
ap_reg_pp0_iter10_tmp_8_14_reg_3684 <= ap_reg_pp0_iter9_tmp_8_14_reg_3684;
ap_reg_pp0_iter11_tmp_8_14_reg_3684 <= ap_reg_pp0_iter10_tmp_8_14_reg_3684;
ap_reg_pp0_iter12_tmp_8_14_reg_3684 <= ap_reg_pp0_iter11_tmp_8_14_reg_3684;
ap_reg_pp0_iter13_tmp_8_14_reg_3684 <= ap_reg_pp0_iter12_tmp_8_14_reg_3684;
ap_reg_pp0_iter14_tmp_8_14_reg_3684 <= ap_reg_pp0_iter13_tmp_8_14_reg_3684;
ap_reg_pp0_iter3_tmp_8_14_reg_3684 <= tmp_8_14_reg_3684;
ap_reg_pp0_iter4_tmp_8_14_reg_3684 <= ap_reg_pp0_iter3_tmp_8_14_reg_3684;
ap_reg_pp0_iter5_tmp_8_14_reg_3684 <= ap_reg_pp0_iter4_tmp_8_14_reg_3684;
ap_reg_pp0_iter6_tmp_8_14_reg_3684 <= ap_reg_pp0_iter5_tmp_8_14_reg_3684;
ap_reg_pp0_iter7_tmp_8_14_reg_3684 <= ap_reg_pp0_iter6_tmp_8_14_reg_3684;
ap_reg_pp0_iter8_tmp_8_14_reg_3684 <= ap_reg_pp0_iter7_tmp_8_14_reg_3684;
ap_reg_pp0_iter9_tmp_8_14_reg_3684 <= ap_reg_pp0_iter8_tmp_8_14_reg_3684;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0))) then
ap_reg_pp0_iter2_tmp_8_3_reg_3574 <= tmp_8_3_reg_3574;
ap_reg_pp0_iter3_tmp_8_3_reg_3574 <= ap_reg_pp0_iter2_tmp_8_3_reg_3574;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0))) then
ap_reg_pp0_iter2_tmp_8_4_reg_3594 <= tmp_8_4_reg_3594;
ap_reg_pp0_iter3_tmp_8_4_reg_3594 <= ap_reg_pp0_iter2_tmp_8_4_reg_3594;
ap_reg_pp0_iter4_tmp_8_4_reg_3594 <= ap_reg_pp0_iter3_tmp_8_4_reg_3594;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0))) then
ap_reg_pp0_iter2_tmp_8_5_reg_3609 <= tmp_8_5_reg_3609;
ap_reg_pp0_iter3_tmp_8_5_reg_3609 <= ap_reg_pp0_iter2_tmp_8_5_reg_3609;
ap_reg_pp0_iter4_tmp_8_5_reg_3609 <= ap_reg_pp0_iter3_tmp_8_5_reg_3609;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00011001 = ap_const_boolean_0))) then
ap_reg_pp0_iter2_tmp_8_6_reg_3624 <= tmp_8_6_reg_3624;
ap_reg_pp0_iter3_tmp_8_6_reg_3624 <= ap_reg_pp0_iter2_tmp_8_6_reg_3624;
ap_reg_pp0_iter4_tmp_8_6_reg_3624 <= ap_reg_pp0_iter3_tmp_8_6_reg_3624;
ap_reg_pp0_iter5_tmp_8_6_reg_3624 <= ap_reg_pp0_iter4_tmp_8_6_reg_3624;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00011001 = ap_const_boolean_0))) then
ap_reg_pp0_iter2_tmp_8_7_reg_3634 <= tmp_8_7_reg_3634;
ap_reg_pp0_iter3_tmp_8_7_reg_3634 <= ap_reg_pp0_iter2_tmp_8_7_reg_3634;
ap_reg_pp0_iter4_tmp_8_7_reg_3634 <= ap_reg_pp0_iter3_tmp_8_7_reg_3634;
ap_reg_pp0_iter5_tmp_8_7_reg_3634 <= ap_reg_pp0_iter4_tmp_8_7_reg_3634;
ap_reg_pp0_iter6_tmp_8_7_reg_3634 <= ap_reg_pp0_iter5_tmp_8_7_reg_3634;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00011001 = ap_const_boolean_0))) then
ap_reg_pp0_iter2_tmp_8_8_reg_3639 <= tmp_8_8_reg_3639;
ap_reg_pp0_iter3_tmp_8_8_reg_3639 <= ap_reg_pp0_iter2_tmp_8_8_reg_3639;
ap_reg_pp0_iter4_tmp_8_8_reg_3639 <= ap_reg_pp0_iter3_tmp_8_8_reg_3639;
ap_reg_pp0_iter5_tmp_8_8_reg_3639 <= ap_reg_pp0_iter4_tmp_8_8_reg_3639;
ap_reg_pp0_iter6_tmp_8_8_reg_3639 <= ap_reg_pp0_iter5_tmp_8_8_reg_3639;
ap_reg_pp0_iter7_tmp_8_8_reg_3639 <= ap_reg_pp0_iter6_tmp_8_8_reg_3639;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011001 = ap_const_boolean_0))) then
ap_reg_pp0_iter2_tmp_8_9_reg_3649 <= tmp_8_9_reg_3649;
ap_reg_pp0_iter3_tmp_8_9_reg_3649 <= ap_reg_pp0_iter2_tmp_8_9_reg_3649;
ap_reg_pp0_iter4_tmp_8_9_reg_3649 <= ap_reg_pp0_iter3_tmp_8_9_reg_3649;
ap_reg_pp0_iter5_tmp_8_9_reg_3649 <= ap_reg_pp0_iter4_tmp_8_9_reg_3649;
ap_reg_pp0_iter6_tmp_8_9_reg_3649 <= ap_reg_pp0_iter5_tmp_8_9_reg_3649;
ap_reg_pp0_iter7_tmp_8_9_reg_3649 <= ap_reg_pp0_iter6_tmp_8_9_reg_3649;
ap_reg_pp0_iter8_tmp_8_9_reg_3649 <= ap_reg_pp0_iter7_tmp_8_9_reg_3649;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_lv1_0 = ap_reg_pp0_iter1_exitcond_flatten3_reg_2229))) then
bufi_load_10_reg_3504 <= bufi_Dout_A;
bufw_load_9_reg_3499 <= bufw_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_lv1_0 = ap_reg_pp0_iter1_exitcond_flatten3_reg_2229))) then
bufi_load_11_reg_3539 <= bufi_Dout_A;
bufw_load_10_reg_3534 <= bufw_Dout_A;
tmp_8_1_reg_3529 <= grp_fu_571_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_lv1_0 = ap_reg_pp0_iter1_exitcond_flatten3_reg_2229))) then
bufi_load_12_reg_3564 <= bufi_Dout_A;
bufw_load_11_reg_3559 <= bufw_Dout_A;
tmp_8_2_reg_3554 <= grp_fu_571_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_lv1_0 = ap_reg_pp0_iter1_exitcond_flatten3_reg_2229))) then
bufi_load_13_reg_3584 <= bufi_Dout_A;
bufw_load_12_reg_3579 <= bufw_Dout_A;
tmp_8_3_reg_3574 <= grp_fu_571_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_lv1_0 = ap_reg_pp0_iter1_exitcond_flatten3_reg_2229))) then
bufi_load_14_reg_3604 <= bufi_Dout_A;
bufw_load_13_reg_3599 <= bufw_Dout_A;
tmp_8_4_reg_3594 <= grp_fu_571_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_lv1_0 = ap_reg_pp0_iter1_exitcond_flatten3_reg_2229))) then
bufi_load_15_reg_3614 <= bufi_Dout_A;
tmp_8_5_reg_3609 <= grp_fu_571_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (exitcond_flatten3_reg_2229 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00011001 = ap_const_boolean_0))) then
bufi_load_1_reg_2974 <= bufi_Dout_A;
bufw_load_8_reg_2979 <= bufw_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (exitcond_flatten3_reg_2229 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00011001 = ap_const_boolean_0))) then
bufi_load_2_reg_3059 <= bufi_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (exitcond_flatten3_reg_2229 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011001 = ap_const_boolean_0))) then
bufi_load_3_reg_3109 <= bufi_Dout_A;
bufw_load_1_reg_3104 <= bufw_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (exitcond_flatten3_reg_2229 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
bufi_load_4_reg_3159 <= bufi_Dout_A;
bufw_load_2_reg_3154 <= bufw_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_lv1_0 = ap_reg_pp0_iter1_exitcond_flatten3_reg_2229))) then
bufi_load_5_reg_3269 <= bufi_Dout_A;
bufw_load_3_reg_3264 <= bufw_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_lv1_0 = ap_reg_pp0_iter1_exitcond_flatten3_reg_2229))) then
bufi_load_6_reg_3339 <= bufi_Dout_A;
bufw_load_4_reg_3334 <= bufw_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_lv1_0 = ap_reg_pp0_iter1_exitcond_flatten3_reg_2229))) then
bufi_load_7_reg_3404 <= bufi_Dout_A;
bufw_load_5_reg_3399 <= bufw_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_lv1_0 = ap_reg_pp0_iter1_exitcond_flatten3_reg_2229))) then
bufi_load_8_reg_3439 <= bufi_Dout_A;
bufw_load_6_reg_3434 <= bufw_Dout_A;
tmp_8_reg_3429 <= grp_fu_571_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_lv1_0 = ap_reg_pp0_iter1_exitcond_flatten3_reg_2229))) then
bufi_load_9_reg_3469 <= bufi_Dout_A;
bufw_load_7_reg_3464 <= bufw_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (exitcond_flatten3_reg_2229 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00011001 = ap_const_boolean_0))) then
bufi_load_reg_2924 <= bufi_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_flatten3_reg_2229 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0))) then
bufo_addr_reg_2650 <= tmp_174_cast_fu_1241_p1(12 - 1 downto 0);
i_cast6_mid2_reg_2567(2 downto 0) <= i_cast6_mid2_fu_1148_p1(2 downto 0);
j_cast4_mid2_cast_reg_2585(2 downto 0) <= j_cast4_mid2_cast_fu_1151_p1(2 downto 0);
tmp_116_reg_2644 <= tmp_116_fu_1224_p2;
tmp_13_reg_2604(15 downto 2) <= tmp_13_fu_1176_p2(15 downto 2);
tmp_56_reg_2624 <= tmp_56_fu_1185_p2;
tmp_67_reg_2629 <= grp_fu_1043_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (exitcond_flatten3_reg_2229 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0))) then
bufo_load_reg_2809 <= bufo_Dout_A;
bufw_load_reg_2804 <= bufw_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_lv1_0 = ap_reg_pp0_iter1_exitcond_flatten3_reg_2229))) then
bufw_load_14_reg_3629 <= bufw_Dout_A;
tmp_8_6_reg_3624 <= grp_fu_571_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_lv1_0 = ap_reg_pp0_iter1_exitcond_flatten3_reg_2229))) then
bufw_load_15_reg_3644 <= bufw_Dout_A;
tmp_8_8_reg_3639 <= grp_fu_571_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0) and (exitcond_flatten3_reg_2229 = ap_const_lv1_0))) then
col_b_1_reg_2408 <= col_b_1_fu_819_p2;
row_b_1_reg_2402 <= row_b_1_fu_814_p2;
tmp_48_reg_2414(8 downto 4) <= tmp_48_fu_824_p3(8 downto 4);
tmp_53_reg_2437 <= tmp_50_fu_846_p2(11 downto 3);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (exitcond_flatten3_reg_2229 = ap_const_lv1_0))) then
col_b_cast2_mid2_reg_2489 <= col_b_cast2_mid2_fu_996_p3;
row_b_cast3_mid2_reg_2473 <= row_b_cast3_mid2_fu_969_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_flatten3_reg_2229 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0))) then
col_b_mid1_reg_2363 <= col_b_mid1_fu_767_p3;
i_1_reg_2345 <= i_1_fu_749_p2;
j_1_reg_2351 <= j_1_fu_755_p2;
row_b_mid_reg_2357 <= row_b_mid_fu_760_p3;
to_b_mid2_reg_2369 <= to_b_mid2_fu_783_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0) and (exitcond_flatten3_reg_2229 = ap_const_lv1_0))) then
exitcond_flatten1_reg_2269 <= exitcond_flatten1_fu_656_p2;
not_exitcond_flatten_1_reg_2274 <= not_exitcond_flatten_1_fu_667_p2;
not_exitcond_flatten_reg_2262 <= not_exitcond_flatten_fu_651_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_lv1_0 = exitcond_flatten3_fu_621_p2))) then
exitcond_flatten2_reg_2251 <= exitcond_flatten2_fu_639_p2;
exitcond_flatten_reg_2238 <= exitcond_flatten_fu_633_p2;
indvar_flatten81_op_reg_2257 <= indvar_flatten81_op_fu_645_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_flatten3_reg_2229 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0))) then
exitcond_flatten43_m_reg_2290 <= exitcond_flatten43_m_fu_688_p2;
exitcond_flatten_mid_2_reg_2299 <= exitcond_flatten_mid_2_fu_692_p2;
tmp_2_reg_2285 <= tmp_2_fu_678_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (exitcond_flatten3_reg_2229 = ap_const_lv1_0))) then
i_cast7_mid2_reg_2386 <= i_cast7_mid2_fu_803_p3;
j_cast5_mid2_reg_2395 <= j_cast5_mid2_fu_809_p3;
to_b_1_reg_2463 <= to_b_1_fu_926_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_flatten3_reg_2229 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0))) then
indvar_flatten41_op_reg_2340 <= indvar_flatten41_op_fu_743_p2;
indvar_flatten_op_reg_2335 <= indvar_flatten_op_fu_737_p2;
j_mid_reg_2309 <= j_mid_fu_697_p3;
tmp_2_mid2_reg_2328 <= tmp_2_mid2_fu_731_p2;
tmp_3_reg_2315 <= tmp_3_fu_708_p2;
tmp_7_reg_2322 <= tmp_7_fu_721_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (exitcond_flatten3_reg_2229 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0))) then
indvar_flatten_next1_reg_2381 <= indvar_flatten_next1_fu_797_p3;
indvar_flatten_next_reg_2376 <= indvar_flatten_next_fu_791_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0) and (exitcond_flatten3_reg_2229 = ap_const_lv1_0))) then
indvar_flatten_next2_reg_2280 <= indvar_flatten_next2_fu_672_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
indvar_flatten_next3_reg_2233 <= indvar_flatten_next3_fu_627_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0) and (ap_reg_pp0_iter7_exitcond_flatten3_reg_2229 = ap_const_lv1_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter15) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0) and (ap_const_lv1_0 = ap_reg_pp0_iter15_exitcond_flatten3_reg_2229)))) then
reg_575 <= grp_fu_567_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_flatten3_reg_2229 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011001 = ap_const_boolean_0))) then
tmp_101_reg_3094 <= tmp_101_fu_1811_p1;
tmp_102_reg_3099 <= tmp_102_fu_1815_p1;
tmp_20_reg_3064(15 downto 2) <= tmp_20_fu_1778_p2(15 downto 2);
tmp_38_reg_3074 <= tmp_38_fu_1787_p2;
tmp_88_reg_3084 <= tmp_88_fu_1795_p2;
tmp_95_reg_3089 <= tmp_95_fu_1806_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (exitcond_flatten3_reg_2229 = ap_const_lv1_0))) then
tmp_103_reg_3139 <= tmp_103_fu_1875_p2;
tmp_109_reg_3144 <= tmp_109_fu_1880_p1;
tmp_115_reg_3149 <= tmp_115_fu_1884_p1;
tmp_21_reg_3114(15 downto 2) <= tmp_21_fu_1847_p2(15 downto 2);
tmp_39_reg_3124 <= tmp_39_fu_1856_p2;
tmp_96_reg_3134 <= tmp_96_fu_1864_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0) and (ap_const_lv1_0 = ap_reg_pp0_iter1_exitcond_flatten3_reg_2229))) then
tmp_104_reg_3184 <= tmp_104_fu_1905_p2;
tmp_110_reg_3189 <= tmp_110_fu_1916_p2;
tmp_126_reg_3194 <= tmp_126_fu_1921_p1;
tmp_133_reg_3199 <= tmp_133_fu_1925_p1;
tmp_140_reg_3204 <= tmp_140_fu_1929_p1;
tmp_147_reg_3209 <= tmp_147_fu_1933_p1;
tmp_154_reg_3214 <= tmp_154_fu_1937_p1;
tmp_161_reg_3219 <= tmp_161_fu_1941_p1;
tmp_168_reg_3224 <= tmp_168_fu_1945_p1;
tmp_172_reg_3229 <= tmp_172_fu_1949_p1;
tmp_173_reg_3234 <= tmp_173_fu_1953_p1;
tmp_175_reg_3239 <= tmp_175_fu_1957_p1;
tmp_176_reg_3244 <= tmp_176_fu_1961_p1;
tmp_177_reg_3249 <= tmp_177_fu_1965_p1;
tmp_178_reg_3254 <= tmp_178_fu_1969_p1;
tmp_179_reg_3259 <= tmp_179_fu_1973_p1;
tmp_22_reg_3164(15 downto 2) <= tmp_22_fu_1888_p2(15 downto 2);
tmp_40_reg_3174 <= tmp_40_fu_1897_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_flatten3_reg_2229 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00011001 = ap_const_boolean_0))) then
tmp_107_reg_2969 <= grp_fu_1434_p2;
tmp_18_reg_2929(15 downto 2) <= tmp_18_fu_1688_p2(15 downto 2);
tmp_36_reg_2939 <= tmp_36_fu_1697_p2;
tmp_72_reg_2949 <= tmp_72_fu_1705_p2;
tmp_79_reg_2954 <= tmp_79_fu_1716_p2;
tmp_85_reg_2959 <= tmp_85_fu_1721_p1;
tmp_86_reg_2964 <= tmp_86_fu_1725_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter11) and (ap_const_lv1_0 = ap_reg_pp0_iter11_exitcond_flatten3_reg_2229))) then
tmp_10_10_reg_3734 <= grp_fu_567_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter12) and (ap_const_lv1_0 = ap_reg_pp0_iter12_exitcond_flatten3_reg_2229))) then
tmp_10_11_reg_3739 <= grp_fu_567_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter13) and (ap_const_lv1_0 = ap_reg_pp0_iter13_exitcond_flatten3_reg_2229))) then
tmp_10_12_reg_3744 <= grp_fu_567_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter14) and (ap_const_lv1_0 = ap_reg_pp0_iter14_exitcond_flatten3_reg_2229))) then
tmp_10_13_reg_3749 <= grp_fu_567_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_lv1_0 = ap_reg_pp0_iter2_exitcond_flatten3_reg_2229) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
tmp_10_1_reg_3689 <= grp_fu_567_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_const_lv1_0 = ap_reg_pp0_iter3_exitcond_flatten3_reg_2229))) then
tmp_10_2_reg_3694 <= grp_fu_567_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_const_lv1_0 = ap_reg_pp0_iter4_exitcond_flatten3_reg_2229))) then
tmp_10_3_reg_3699 <= grp_fu_567_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_const_lv1_0 = ap_reg_pp0_iter5_exitcond_flatten3_reg_2229))) then
tmp_10_4_reg_3704 <= grp_fu_567_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6) and (ap_const_lv1_0 = ap_reg_pp0_iter6_exitcond_flatten3_reg_2229))) then
tmp_10_5_reg_3709 <= grp_fu_567_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_const_lv1_0 = ap_reg_pp0_iter8_exitcond_flatten3_reg_2229))) then
tmp_10_7_reg_3714 <= grp_fu_567_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9) and (ap_const_lv1_0 = ap_reg_pp0_iter9_exitcond_flatten3_reg_2229))) then
tmp_10_8_reg_3719 <= grp_fu_567_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter10) and (ap_const_lv1_0 = ap_reg_pp0_iter10_exitcond_flatten3_reg_2229))) then
tmp_10_9_reg_3724 <= grp_fu_567_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_const_lv1_0 = ap_reg_pp0_iter2_exitcond_flatten3_reg_2229))) then
tmp_10_reg_3664 <= grp_fu_567_p2;
tmp_8_11_reg_3669 <= grp_fu_571_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter10) and (ap_const_lv1_0 = ap_reg_pp0_iter10_exitcond_flatten3_reg_2229))) then
tmp_10_s_reg_3729 <= grp_fu_567_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0) and (ap_const_lv1_0 = ap_reg_pp0_iter1_exitcond_flatten3_reg_2229))) then
tmp_111_reg_3294 <= tmp_111_fu_1994_p2;
tmp_127_reg_3299 <= tmp_127_fu_2005_p2;
tmp_134_reg_3304 <= tmp_134_fu_2017_p2;
tmp_141_reg_3309 <= tmp_141_fu_2029_p2;
tmp_148_reg_3314 <= tmp_148_fu_2041_p2;
tmp_155_reg_3319 <= tmp_155_fu_2053_p2;
tmp_162_reg_3324 <= tmp_162_fu_2065_p2;
tmp_169_reg_3329 <= tmp_169_fu_2077_p2;
tmp_23_reg_3274(15 downto 2) <= tmp_23_fu_1977_p2(15 downto 2);
tmp_41_reg_3284 <= tmp_41_fu_1986_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_flatten3_reg_2229 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0))) then
tmp_117_reg_2547 <= tmp_117_fu_1118_p1;
tmp_118_reg_2552 <= grp_fu_920_p2(13 downto 3);
tmp_119_reg_2557 <= grp_fu_920_p2(11 downto 3);
tmp_171_reg_2562 <= tmp_171_fu_1142_p2;
tmp_55_reg_2527 <= tmp_55_fu_1083_p2;
tmp_59_reg_2532 <= grp_fu_890_p2;
tmp_6_cast_mid2_reg_2516 <= tmp_6_cast_mid2_fu_1052_p3;
tmp_cast_mid2_reg_2522 <= tmp_cast_mid2_fu_1057_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_flatten3_reg_2229 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0))) then
tmp_120_reg_2704 <= tmp_120_fu_1310_p2;
tmp_14_reg_2655(15 downto 2) <= tmp_14_fu_1246_p2(15 downto 2);
tmp_32_reg_2679 <= tmp_32_fu_1254_p2;
tmp_75_reg_2689 <= grp_fu_1112_p2;
tmp_cast_mid2_cast_reg_2660(5 downto 0) <= tmp_cast_mid2_cast_fu_1251_p1(5 downto 0);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_flatten3_reg_2229 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0))) then
tmp_121_reg_2749 <= tmp_121_fu_1370_p2;
tmp_15_reg_2709(15 downto 2) <= tmp_15_fu_1316_p2(15 downto 2);
tmp_33_reg_2719 <= tmp_33_fu_1325_p2;
tmp_61_reg_2724 <= tmp_61_fu_1329_p1;
tmp_62_reg_2729 <= tmp_62_fu_1333_p1;
tmp_83_reg_2734 <= grp_fu_1218_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_flatten3_reg_2229 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00011001 = ap_const_boolean_0))) then
tmp_124_reg_3024 <= grp_fu_1508_p2;
tmp_131_reg_3029 <= grp_fu_1537_p2;
tmp_138_reg_3034 <= grp_fu_1566_p2;
tmp_145_reg_3039 <= grp_fu_1595_p2;
tmp_152_reg_3044 <= grp_fu_1624_p2;
tmp_159_reg_3049 <= grp_fu_1653_p2;
tmp_166_reg_3054 <= grp_fu_1682_p2;
tmp_19_reg_2984(15 downto 2) <= tmp_19_fu_1733_p2(15 downto 2);
tmp_37_reg_2994 <= tmp_37_fu_1742_p2;
tmp_80_reg_3004 <= tmp_80_fu_1750_p2;
tmp_87_reg_3009 <= tmp_87_fu_1761_p2;
tmp_93_reg_3014 <= tmp_93_fu_1766_p1;
tmp_94_reg_3019 <= tmp_94_fu_1770_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0) and (ap_const_lv1_0 = ap_reg_pp0_iter1_exitcond_flatten3_reg_2229))) then
tmp_128_reg_3364 <= tmp_128_fu_2099_p2;
tmp_135_reg_3369 <= tmp_135_fu_2103_p2;
tmp_142_reg_3374 <= tmp_142_fu_2107_p2;
tmp_149_reg_3379 <= tmp_149_fu_2111_p2;
tmp_156_reg_3384 <= tmp_156_fu_2115_p2;
tmp_163_reg_3389 <= tmp_163_fu_2119_p2;
tmp_170_reg_3394 <= tmp_170_fu_2123_p2;
tmp_24_reg_3344(15 downto 2) <= tmp_24_fu_2082_p2(15 downto 2);
tmp_42_reg_3354 <= tmp_42_fu_2091_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_flatten3_reg_2229 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0))) then
tmp_16_reg_2754(15 downto 2) <= tmp_16_fu_1374_p2(15 downto 2);
tmp_34_reg_2764 <= tmp_34_fu_1383_p2;
tmp_63_reg_2769 <= tmp_63_fu_1394_p2;
tmp_69_reg_2774 <= tmp_69_fu_1399_p1;
tmp_70_reg_2779 <= tmp_70_fu_1403_p1;
tmp_91_reg_2784 <= grp_fu_1290_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_flatten3_reg_2229 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00011001 = ap_const_boolean_0))) then
tmp_17_reg_2814(15 downto 2) <= tmp_17_fu_1444_p2(15 downto 2);
tmp_35_reg_2824 <= tmp_35_fu_1453_p2;
tmp_64_reg_2829 <= tmp_64_fu_1457_p2;
tmp_71_reg_2834 <= tmp_71_fu_1468_p2;
tmp_77_reg_2839 <= tmp_77_fu_1473_p1;
tmp_78_reg_2844 <= tmp_78_fu_1477_p1;
tmp_99_reg_2849 <= grp_fu_1364_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0) and (ap_const_lv1_0 = ap_reg_pp0_iter1_exitcond_flatten3_reg_2229))) then
tmp_25_reg_3409(15 downto 2) <= tmp_25_fu_2127_p2(15 downto 2);
tmp_43_reg_3419 <= tmp_43_fu_2136_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0) and (ap_const_lv1_0 = ap_reg_pp0_iter1_exitcond_flatten3_reg_2229))) then
tmp_26_reg_3444(15 downto 2) <= tmp_26_fu_2144_p2(15 downto 2);
tmp_44_reg_3454 <= tmp_44_fu_2153_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0) and (ap_const_lv1_0 = ap_reg_pp0_iter1_exitcond_flatten3_reg_2229))) then
tmp_27_reg_3474(15 downto 2) <= tmp_27_fu_2161_p2(15 downto 2);
tmp_28_reg_3479(15 downto 2) <= tmp_28_fu_2166_p2(15 downto 2);
tmp_45_reg_3489 <= tmp_45_fu_2175_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0) and (ap_const_lv1_0 = ap_reg_pp0_iter1_exitcond_flatten3_reg_2229))) then
tmp_46_reg_3514 <= tmp_46_fu_2187_p2;
tmp_47_reg_3519 <= tmp_47_fu_2191_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0) and (exitcond_flatten3_reg_2229 = ap_const_lv1_0))) then
tmp_52_reg_2500 <= tmp_52_fu_1016_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0) and (exitcond_flatten3_reg_2229 = ap_const_lv1_0) and (ap_const_lv1_0 = exitcond_flatten_mid_2_reg_2299))) then
tmp_6_cast_mid5_reg_2468 <= tmp_6_cast_mid5_fu_955_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0) and (exitcond_flatten3_reg_2229 = ap_const_lv1_0) and (exitcond_flatten_mid_2_reg_2299 = ap_const_lv1_1))) then
tmp_6_mid1_reg_2479 <= tmp_6_mid1_fu_983_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_const_lv1_0 = ap_reg_pp0_iter2_exitcond_flatten3_reg_2229))) then
tmp_8_10_reg_3659 <= grp_fu_571_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_const_lv1_0 = ap_reg_pp0_iter2_exitcond_flatten3_reg_2229))) then
tmp_8_12_reg_3674 <= grp_fu_571_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_const_lv1_0 = ap_reg_pp0_iter2_exitcond_flatten3_reg_2229))) then
tmp_8_13_reg_3679 <= grp_fu_571_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_const_lv1_0 = ap_reg_pp0_iter2_exitcond_flatten3_reg_2229))) then
tmp_8_14_reg_3684 <= grp_fu_571_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_lv1_0 = ap_reg_pp0_iter1_exitcond_flatten3_reg_2229))) then
tmp_8_7_reg_3634 <= grp_fu_571_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_lv1_0 = ap_reg_pp0_iter1_exitcond_flatten3_reg_2229))) then
tmp_8_9_reg_3649 <= grp_fu_571_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_lv1_0 = ap_reg_pp0_iter1_exitcond_flatten3_reg_2229) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
tmp_8_s_reg_3654 <= grp_fu_571_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0) and (exitcond_flatten3_reg_2229 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_mid2_reg_2328))) then
tmp_cast_mid5_reg_2484 <= tmp_cast_mid5_fu_989_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0) and (exitcond_flatten3_reg_2229 = ap_const_lv1_0) and (tmp_2_mid2_reg_2328 = ap_const_lv1_1))) then
tmp_mid1_reg_2495 <= tmp_mid1_fu_1010_p2;
end if;
end if;
end process;
tmp_48_reg_2414(3 downto 0) <= "0000";
tmp_51_reg_2432(2 downto 0) <= "000";
i_cast6_mid2_reg_2567(63 downto 3) <= "0000000000000000000000000000000000000000000000000000000000000";
j_cast4_mid2_cast_reg_2585(13 downto 3) <= "00000000000";
tmp_13_reg_2604(1 downto 0) <= "00";
tmp_14_reg_2655(1 downto 0) <= "00";
tmp_cast_mid2_cast_reg_2660(15 downto 6) <= "0000000000";
tmp_15_reg_2709(1 downto 0) <= "00";
tmp_16_reg_2754(1 downto 0) <= "00";
tmp_17_reg_2814(1 downto 0) <= "00";
tmp_18_reg_2929(1 downto 0) <= "00";
tmp_19_reg_2984(1 downto 0) <= "00";
tmp_20_reg_3064(1 downto 0) <= "00";
tmp_21_reg_3114(1 downto 0) <= "00";
tmp_22_reg_3164(1 downto 0) <= "00";
tmp_23_reg_3274(1 downto 0) <= "00";
tmp_24_reg_3344(1 downto 0) <= "00";
tmp_25_reg_3409(1 downto 0) <= "00";
tmp_26_reg_3444(1 downto 0) <= "00";
tmp_27_reg_3474(1 downto 0) <= "00";
tmp_28_reg_3479(1 downto 0) <= "00";
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, ap_CS_fsm_pp0_stage6, ap_enable_reg_pp0_iter15, exitcond_flatten3_fu_621_p2, ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter14, ap_block_pp0_stage0_flag00011011, ap_block_pp0_stage15_flag00011011, ap_block_pp0_stage6_flag00011011, ap_block_pp0_stage1_flag00011011, ap_block_pp0_stage2_flag00011011, ap_block_pp0_stage3_flag00011011, ap_block_pp0_stage4_flag00011011, ap_block_pp0_stage5_flag00011011, ap_block_pp0_stage7_flag00011011, ap_block_pp0_stage8_flag00011011, ap_block_pp0_stage9_flag00011011, ap_block_pp0_stage10_flag00011011, ap_block_pp0_stage11_flag00011011, ap_block_pp0_stage12_flag00011011, ap_block_pp0_stage13_flag00011011, ap_block_pp0_stage14_flag00011011)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_pp0_stage0 =>
if (((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and not(((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (exitcond_flatten3_fu_621_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0))))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (exitcond_flatten3_fu_621_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_fsm_state249;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
end if;
when ap_ST_fsm_pp0_stage1 =>
if ((ap_block_pp0_stage1_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage2;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage1;
end if;
when ap_ST_fsm_pp0_stage2 =>
if ((ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage3;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage2;
end if;
when ap_ST_fsm_pp0_stage3 =>
if ((ap_block_pp0_stage3_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage4;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage3;
end if;
when ap_ST_fsm_pp0_stage4 =>
if ((ap_block_pp0_stage4_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage5;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage4;
end if;
when ap_ST_fsm_pp0_stage5 =>
if ((ap_block_pp0_stage5_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage6;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage5;
end if;
when ap_ST_fsm_pp0_stage6 =>
if (((ap_block_pp0_stage6_flag00011011 = ap_const_boolean_0) and not(((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter15) and (ap_block_pp0_stage6_flag00011011 = ap_const_boolean_0) and (ap_enable_reg_pp0_iter14 = ap_const_logic_0))))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage7;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter15) and (ap_block_pp0_stage6_flag00011011 = ap_const_boolean_0) and (ap_enable_reg_pp0_iter14 = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_fsm_state249;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage6;
end if;
when ap_ST_fsm_pp0_stage7 =>
if ((ap_block_pp0_stage7_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage8;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage7;
end if;
when ap_ST_fsm_pp0_stage8 =>
if ((ap_block_pp0_stage8_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage9;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage8;
end if;
when ap_ST_fsm_pp0_stage9 =>
if ((ap_block_pp0_stage9_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage10;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage9;
end if;
when ap_ST_fsm_pp0_stage10 =>
if ((ap_block_pp0_stage10_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage11;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage10;
end if;
when ap_ST_fsm_pp0_stage11 =>
if ((ap_block_pp0_stage11_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage12;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage11;
end if;
when ap_ST_fsm_pp0_stage12 =>
if ((ap_block_pp0_stage12_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage13;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage12;
end if;
when ap_ST_fsm_pp0_stage13 =>
if ((ap_block_pp0_stage13_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage14;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage13;
end if;
when ap_ST_fsm_pp0_stage14 =>
if ((ap_block_pp0_stage14_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage15;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage14;
end if;
when ap_ST_fsm_pp0_stage15 =>
if ((ap_block_pp0_stage15_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage15;
end if;
when ap_ST_fsm_state249 =>
ap_NS_fsm <= ap_ST_fsm_state1;
when others =>
ap_NS_fsm <= "XXXXXXXXXXXXXXXXXX";
end case;
end process;
ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(1);
ap_CS_fsm_pp0_stage1 <= ap_CS_fsm(2);
ap_CS_fsm_pp0_stage10 <= ap_CS_fsm(11);
ap_CS_fsm_pp0_stage11 <= ap_CS_fsm(12);
ap_CS_fsm_pp0_stage12 <= ap_CS_fsm(13);
ap_CS_fsm_pp0_stage13 <= ap_CS_fsm(14);
ap_CS_fsm_pp0_stage14 <= ap_CS_fsm(15);
ap_CS_fsm_pp0_stage15 <= ap_CS_fsm(16);
ap_CS_fsm_pp0_stage2 <= ap_CS_fsm(3);
ap_CS_fsm_pp0_stage3 <= ap_CS_fsm(4);
ap_CS_fsm_pp0_stage4 <= ap_CS_fsm(5);
ap_CS_fsm_pp0_stage5 <= ap_CS_fsm(6);
ap_CS_fsm_pp0_stage6 <= ap_CS_fsm(7);
ap_CS_fsm_pp0_stage7 <= ap_CS_fsm(8);
ap_CS_fsm_pp0_stage8 <= ap_CS_fsm(9);
ap_CS_fsm_pp0_stage9 <= ap_CS_fsm(10);
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state249 <= ap_CS_fsm(17);
ap_block_pp0_stage0_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage0_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage0_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage10_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage10_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage10_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage11_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage11_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage11_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage12_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage12_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage12_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage13_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage13_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage13_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage14_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage14_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage14_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage15_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage15_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage15_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage1_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage1_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage1_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage2_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage2_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage2_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage3_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage3_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage3_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage4_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage4_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage4_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage5_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage5_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage5_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage6_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage6_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage6_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage7_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage7_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage7_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage8_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage8_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage8_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage9_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage9_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage9_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state100_pp0_stage2_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state101_pp0_stage3_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state102_pp0_stage4_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state103_pp0_stage5_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state104_pp0_stage6_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state105_pp0_stage7_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state106_pp0_stage8_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state107_pp0_stage9_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state108_pp0_stage10_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state109_pp0_stage11_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state10_pp0_stage8_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state110_pp0_stage12_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state111_pp0_stage13_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state112_pp0_stage14_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state113_pp0_stage15_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state114_pp0_stage0_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state115_pp0_stage1_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state116_pp0_stage2_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state117_pp0_stage3_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state118_pp0_stage4_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state119_pp0_stage5_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state11_pp0_stage9_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state120_pp0_stage6_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state121_pp0_stage7_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state122_pp0_stage8_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state123_pp0_stage9_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state124_pp0_stage10_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state125_pp0_stage11_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state126_pp0_stage12_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state127_pp0_stage13_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state128_pp0_stage14_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state129_pp0_stage15_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state12_pp0_stage10_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state130_pp0_stage0_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state131_pp0_stage1_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state132_pp0_stage2_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state133_pp0_stage3_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state134_pp0_stage4_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state135_pp0_stage5_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state136_pp0_stage6_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state137_pp0_stage7_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state138_pp0_stage8_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state139_pp0_stage9_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state13_pp0_stage11_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state140_pp0_stage10_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state141_pp0_stage11_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state142_pp0_stage12_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state143_pp0_stage13_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state144_pp0_stage14_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state145_pp0_stage15_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state146_pp0_stage0_iter9 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state147_pp0_stage1_iter9 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state148_pp0_stage2_iter9 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state149_pp0_stage3_iter9 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state14_pp0_stage12_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state150_pp0_stage4_iter9 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state151_pp0_stage5_iter9 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state152_pp0_stage6_iter9 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state153_pp0_stage7_iter9 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state154_pp0_stage8_iter9 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state155_pp0_stage9_iter9 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state156_pp0_stage10_iter9 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state157_pp0_stage11_iter9 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state158_pp0_stage12_iter9 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state159_pp0_stage13_iter9 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state15_pp0_stage13_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state160_pp0_stage14_iter9 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state161_pp0_stage15_iter9 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state162_pp0_stage0_iter10 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state163_pp0_stage1_iter10 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state164_pp0_stage2_iter10 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state165_pp0_stage3_iter10 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state166_pp0_stage4_iter10 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state167_pp0_stage5_iter10 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state168_pp0_stage6_iter10 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state169_pp0_stage7_iter10 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state16_pp0_stage14_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state170_pp0_stage8_iter10 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state171_pp0_stage9_iter10 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state172_pp0_stage10_iter10 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state173_pp0_stage11_iter10 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state174_pp0_stage12_iter10 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state175_pp0_stage13_iter10 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state176_pp0_stage14_iter10 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state177_pp0_stage15_iter10 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state178_pp0_stage0_iter11 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state179_pp0_stage1_iter11 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state17_pp0_stage15_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state180_pp0_stage2_iter11 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state181_pp0_stage3_iter11 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state182_pp0_stage4_iter11 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state183_pp0_stage5_iter11 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state184_pp0_stage6_iter11 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state185_pp0_stage7_iter11 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state186_pp0_stage8_iter11 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state187_pp0_stage9_iter11 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state188_pp0_stage10_iter11 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state189_pp0_stage11_iter11 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state18_pp0_stage0_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state190_pp0_stage12_iter11 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state191_pp0_stage13_iter11 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state192_pp0_stage14_iter11 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state193_pp0_stage15_iter11 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state194_pp0_stage0_iter12 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state195_pp0_stage1_iter12 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state196_pp0_stage2_iter12 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state197_pp0_stage3_iter12 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state198_pp0_stage4_iter12 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state199_pp0_stage5_iter12 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state19_pp0_stage1_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state200_pp0_stage6_iter12 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state201_pp0_stage7_iter12 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state202_pp0_stage8_iter12 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state203_pp0_stage9_iter12 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state204_pp0_stage10_iter12 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state205_pp0_stage11_iter12 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state206_pp0_stage12_iter12 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state207_pp0_stage13_iter12 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state208_pp0_stage14_iter12 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state209_pp0_stage15_iter12 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state20_pp0_stage2_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state210_pp0_stage0_iter13 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state211_pp0_stage1_iter13 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state212_pp0_stage2_iter13 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state213_pp0_stage3_iter13 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state214_pp0_stage4_iter13 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state215_pp0_stage5_iter13 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state216_pp0_stage6_iter13 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state217_pp0_stage7_iter13 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state218_pp0_stage8_iter13 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state219_pp0_stage9_iter13 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state21_pp0_stage3_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state220_pp0_stage10_iter13 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state221_pp0_stage11_iter13 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state222_pp0_stage12_iter13 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state223_pp0_stage13_iter13 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state224_pp0_stage14_iter13 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state225_pp0_stage15_iter13 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state226_pp0_stage0_iter14 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state227_pp0_stage1_iter14 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state228_pp0_stage2_iter14 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state229_pp0_stage3_iter14 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state22_pp0_stage4_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state230_pp0_stage4_iter14 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state231_pp0_stage5_iter14 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state232_pp0_stage6_iter14 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state233_pp0_stage7_iter14 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state234_pp0_stage8_iter14 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state235_pp0_stage9_iter14 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state236_pp0_stage10_iter14 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state237_pp0_stage11_iter14 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state238_pp0_stage12_iter14 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state239_pp0_stage13_iter14 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state23_pp0_stage5_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state240_pp0_stage14_iter14 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state241_pp0_stage15_iter14 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state242_pp0_stage0_iter15 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state243_pp0_stage1_iter15 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state244_pp0_stage2_iter15 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state245_pp0_stage3_iter15 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state246_pp0_stage4_iter15 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state247_pp0_stage5_iter15 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state248_pp0_stage6_iter15 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state24_pp0_stage6_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state25_pp0_stage7_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state26_pp0_stage8_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state27_pp0_stage9_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state28_pp0_stage10_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state29_pp0_stage11_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state2_pp0_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state30_pp0_stage12_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state31_pp0_stage13_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state32_pp0_stage14_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state33_pp0_stage15_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state34_pp0_stage0_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state35_pp0_stage1_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state36_pp0_stage2_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state37_pp0_stage3_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state38_pp0_stage4_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state39_pp0_stage5_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state3_pp0_stage1_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state40_pp0_stage6_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state41_pp0_stage7_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state42_pp0_stage8_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state43_pp0_stage9_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state44_pp0_stage10_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state45_pp0_stage11_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state46_pp0_stage12_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state47_pp0_stage13_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state48_pp0_stage14_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state49_pp0_stage15_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state4_pp0_stage2_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state50_pp0_stage0_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state51_pp0_stage1_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state52_pp0_stage2_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state53_pp0_stage3_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state54_pp0_stage4_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state55_pp0_stage5_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state56_pp0_stage6_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state57_pp0_stage7_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state58_pp0_stage8_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state59_pp0_stage9_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state5_pp0_stage3_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state60_pp0_stage10_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state61_pp0_stage11_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state62_pp0_stage12_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state63_pp0_stage13_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state64_pp0_stage14_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state65_pp0_stage15_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state66_pp0_stage0_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state67_pp0_stage1_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state68_pp0_stage2_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state69_pp0_stage3_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state6_pp0_stage4_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state70_pp0_stage4_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state71_pp0_stage5_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state72_pp0_stage6_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state73_pp0_stage7_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state74_pp0_stage8_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state75_pp0_stage9_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state76_pp0_stage10_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state77_pp0_stage11_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state78_pp0_stage12_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state79_pp0_stage13_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state7_pp0_stage5_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state80_pp0_stage14_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state81_pp0_stage15_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state82_pp0_stage0_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state83_pp0_stage1_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state84_pp0_stage2_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state85_pp0_stage3_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state86_pp0_stage4_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state87_pp0_stage5_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state88_pp0_stage6_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state89_pp0_stage7_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state8_pp0_stage6_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state90_pp0_stage8_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state91_pp0_stage9_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state92_pp0_stage10_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state93_pp0_stage11_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state94_pp0_stage12_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state95_pp0_stage13_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state96_pp0_stage14_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state97_pp0_stage15_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state98_pp0_stage0_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state99_pp0_stage1_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state9_pp0_stage7_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_condition_pp0_exit_iter0_state2_assign_proc : process(exitcond_flatten3_fu_621_p2)
begin
if ((exitcond_flatten3_fu_621_p2 = ap_const_lv1_1)) then
ap_condition_pp0_exit_iter0_state2 <= ap_const_logic_1;
else
ap_condition_pp0_exit_iter0_state2 <= ap_const_logic_0;
end if;
end process;
ap_done_assign_proc : process(ap_CS_fsm_state249)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state249)) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter7, ap_enable_reg_pp0_iter15, ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_enable_reg_pp0_iter8, ap_enable_reg_pp0_iter9, ap_enable_reg_pp0_iter10, ap_enable_reg_pp0_iter11, ap_enable_reg_pp0_iter12, ap_enable_reg_pp0_iter13, ap_enable_reg_pp0_iter14)
begin
if (((ap_const_logic_0 = ap_enable_reg_pp0_iter0) and (ap_const_logic_0 = ap_enable_reg_pp0_iter1) and (ap_const_logic_0 = ap_enable_reg_pp0_iter2) and (ap_const_logic_0 = ap_enable_reg_pp0_iter3) and (ap_const_logic_0 = ap_enable_reg_pp0_iter4) and (ap_const_logic_0 = ap_enable_reg_pp0_iter5) and (ap_const_logic_0 = ap_enable_reg_pp0_iter6) and (ap_const_logic_0 = ap_enable_reg_pp0_iter7) and (ap_const_logic_0 = ap_enable_reg_pp0_iter8) and (ap_const_logic_0 = ap_enable_reg_pp0_iter9) and (ap_const_logic_0 = ap_enable_reg_pp0_iter10) and (ap_const_logic_0 = ap_enable_reg_pp0_iter11) and (ap_const_logic_0 = ap_enable_reg_pp0_iter12) and (ap_const_logic_0 = ap_enable_reg_pp0_iter13) and (ap_const_logic_0 = ap_enable_reg_pp0_iter14) and (ap_const_logic_0 = ap_enable_reg_pp0_iter15))) then
ap_idle_pp0 <= ap_const_logic_1;
else
ap_idle_pp0 <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(ap_CS_fsm_state249)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state249)) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
bufi_Addr_A <= std_logic_vector(shift_left(unsigned(bufi_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufi_Addr_A_orig_assign_proc : process(ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage15, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, tmp_35_cast_fu_1321_p1, ap_block_pp0_stage10_flag00000000, tmp_36_cast_fu_1379_p1, ap_block_pp0_stage11_flag00000000, tmp_37_cast_fu_1449_p1, ap_block_pp0_stage12_flag00000000, tmp_38_cast_fu_1693_p1, ap_block_pp0_stage13_flag00000000, tmp_39_cast_fu_1738_p1, ap_block_pp0_stage14_flag00000000, tmp_40_cast_fu_1783_p1, ap_block_pp0_stage15_flag00000000, tmp_41_cast_fu_1852_p1, tmp_42_cast_fu_1893_p1, tmp_43_cast_fu_1982_p1, tmp_44_cast_fu_2087_p1, ap_block_pp0_stage3_flag00000000, tmp_45_cast_fu_2132_p1, ap_block_pp0_stage4_flag00000000, tmp_46_cast_fu_2149_p1, ap_block_pp0_stage5_flag00000000, tmp_47_cast_fu_2171_p1, ap_block_pp0_stage6_flag00000000, tmp_48_cast_fu_2183_p1, ap_block_pp0_stage7_flag00000000, tmp_49_cast_fu_2199_p1, tmp_50_cast_fu_2207_p1)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
bufi_Addr_A_orig <= tmp_50_cast_fu_2207_p1(32 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
bufi_Addr_A_orig <= tmp_49_cast_fu_2199_p1(32 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
bufi_Addr_A_orig <= tmp_48_cast_fu_2183_p1(32 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
bufi_Addr_A_orig <= tmp_47_cast_fu_2171_p1(32 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
bufi_Addr_A_orig <= tmp_46_cast_fu_2149_p1(32 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
bufi_Addr_A_orig <= tmp_45_cast_fu_2132_p1(32 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
bufi_Addr_A_orig <= tmp_44_cast_fu_2087_p1(32 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
bufi_Addr_A_orig <= tmp_43_cast_fu_1982_p1(32 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
bufi_Addr_A_orig <= tmp_42_cast_fu_1893_p1(32 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
bufi_Addr_A_orig <= tmp_41_cast_fu_1852_p1(32 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
bufi_Addr_A_orig <= tmp_40_cast_fu_1783_p1(32 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
bufi_Addr_A_orig <= tmp_39_cast_fu_1738_p1(32 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
bufi_Addr_A_orig <= tmp_38_cast_fu_1693_p1(32 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
bufi_Addr_A_orig <= tmp_37_cast_fu_1449_p1(32 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
bufi_Addr_A_orig <= tmp_36_cast_fu_1379_p1(32 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
bufi_Addr_A_orig <= tmp_35_cast_fu_1321_p1(32 - 1 downto 0);
else
bufi_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufi_Clk_A <= ap_clk;
bufi_Din_A <= ap_const_lv32_0;
bufi_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_flag00011001, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_flag00011001, ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_flag00011001, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_flag00011001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00011001, ap_CS_fsm_pp0_stage3, ap_block_pp0_stage3_flag00011001, ap_CS_fsm_pp0_stage4, ap_block_pp0_stage4_flag00011001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_flag00011001, ap_CS_fsm_pp0_stage8, ap_block_pp0_stage8_flag00011001, ap_CS_fsm_pp0_stage9, ap_block_pp0_stage9_flag00011001, ap_CS_fsm_pp0_stage10, ap_block_pp0_stage10_flag00011001, ap_CS_fsm_pp0_stage11, ap_block_pp0_stage11_flag00011001, ap_CS_fsm_pp0_stage12, ap_block_pp0_stage12_flag00011001, ap_CS_fsm_pp0_stage13, ap_block_pp0_stage13_flag00011001, ap_CS_fsm_pp0_stage14, ap_block_pp0_stage14_flag00011001, ap_CS_fsm_pp0_stage15, ap_block_pp0_stage15_flag00011001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0)))) then
bufi_EN_A <= ap_const_logic_1;
else
bufi_EN_A <= ap_const_logic_0;
end if;
end process;
bufi_Rst_A <= ap_rst_n_inv;
bufi_WEN_A <= ap_const_lv4_0;
bufo_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_Addr_A_orig_assign_proc : process(ap_CS_fsm_pp0_stage6, ap_enable_reg_pp0_iter15, ap_enable_reg_pp0_iter0, bufo_addr_reg_2650, ap_reg_pp0_iter14_bufo_addr_reg_2650, ap_CS_fsm_pp0_stage9, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage6_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter15) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
bufo_Addr_A_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(ap_reg_pp0_iter14_bufo_addr_reg_2650),32));
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
bufo_Addr_A_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(bufo_addr_reg_2650),32));
else
bufo_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufo_Clk_A <= ap_clk;
bufo_Din_A <= reg_575;
bufo_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_flag00011001, ap_enable_reg_pp0_iter15, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, ap_block_pp0_stage9_flag00011001, ap_CS_fsm_pp0_stage10, ap_block_pp0_stage10_flag00011001, ap_CS_fsm_pp0_stage11, ap_block_pp0_stage11_flag00011001)
begin
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter15)))) then
bufo_EN_A <= ap_const_logic_1;
else
bufo_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_Rst_A <= ap_rst_n_inv;
bufo_WEN_A_assign_proc : process(ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_flag00011001, ap_enable_reg_pp0_iter15, ap_reg_pp0_iter15_exitcond_flatten3_reg_2229)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter15) and (ap_const_lv1_0 = ap_reg_pp0_iter15_exitcond_flatten3_reg_2229))) then
bufo_WEN_A <= ap_const_lv4_F;
else
bufo_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufw_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_Addr_A_orig_assign_proc : process(ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage15, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000, ap_block_pp0_stage8_flag00000000, tmp_62_cast_fu_1259_p1, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, tmp_121_cast_fu_1440_p1, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, tmp_69_cast_fu_1701_p1, ap_block_pp0_stage14_flag00000000, tmp_76_cast_fu_1746_p1, ap_block_pp0_stage15_flag00000000, tmp_83_cast_fu_1791_p1, tmp_90_cast_fu_1860_p1, tmp_97_cast_fu_1901_p1, tmp_104_cast_fu_1990_p1, ap_block_pp0_stage3_flag00000000, tmp_111_cast_fu_2095_p1, ap_block_pp0_stage4_flag00000000, tmp_128_cast_fu_2140_p1, ap_block_pp0_stage5_flag00000000, tmp_135_cast_fu_2157_p1, ap_block_pp0_stage6_flag00000000, tmp_142_cast_fu_2179_p1, ap_block_pp0_stage7_flag00000000, tmp_149_cast_fu_2195_p1, tmp_156_cast_fu_2203_p1, tmp_163_cast_fu_2211_p1, tmp_170_cast_fu_2215_p1)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
bufw_Addr_A_orig <= tmp_170_cast_fu_2215_p1(32 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
bufw_Addr_A_orig <= tmp_163_cast_fu_2211_p1(32 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
bufw_Addr_A_orig <= tmp_156_cast_fu_2203_p1(32 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
bufw_Addr_A_orig <= tmp_149_cast_fu_2195_p1(32 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
bufw_Addr_A_orig <= tmp_142_cast_fu_2179_p1(32 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
bufw_Addr_A_orig <= tmp_135_cast_fu_2157_p1(32 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
bufw_Addr_A_orig <= tmp_128_cast_fu_2140_p1(32 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
bufw_Addr_A_orig <= tmp_111_cast_fu_2095_p1(32 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
bufw_Addr_A_orig <= tmp_104_cast_fu_1990_p1(32 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
bufw_Addr_A_orig <= tmp_97_cast_fu_1901_p1(32 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
bufw_Addr_A_orig <= tmp_90_cast_fu_1860_p1(32 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
bufw_Addr_A_orig <= tmp_83_cast_fu_1791_p1(32 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
bufw_Addr_A_orig <= tmp_76_cast_fu_1746_p1(32 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
bufw_Addr_A_orig <= tmp_69_cast_fu_1701_p1(32 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
bufw_Addr_A_orig <= tmp_121_cast_fu_1440_p1(32 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
bufw_Addr_A_orig <= tmp_62_cast_fu_1259_p1(32 - 1 downto 0);
else
bufw_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufw_Clk_A <= ap_clk;
bufw_Din_A <= ap_const_lv32_0;
bufw_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_flag00011001, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_flag00011001, ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_flag00011001, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_flag00011001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00011001, ap_CS_fsm_pp0_stage3, ap_block_pp0_stage3_flag00011001, ap_CS_fsm_pp0_stage4, ap_block_pp0_stage4_flag00011001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_flag00011001, ap_CS_fsm_pp0_stage8, ap_block_pp0_stage8_flag00011001, ap_CS_fsm_pp0_stage9, ap_block_pp0_stage9_flag00011001, ap_CS_fsm_pp0_stage10, ap_block_pp0_stage10_flag00011001, ap_CS_fsm_pp0_stage11, ap_block_pp0_stage11_flag00011001, ap_CS_fsm_pp0_stage12, ap_block_pp0_stage12_flag00011001, ap_CS_fsm_pp0_stage13, ap_block_pp0_stage13_flag00011001, ap_CS_fsm_pp0_stage14, ap_block_pp0_stage14_flag00011001, ap_CS_fsm_pp0_stage15, ap_block_pp0_stage15_flag00011001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0)))) then
bufw_EN_A <= ap_const_logic_1;
else
bufw_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_Rst_A <= ap_rst_n_inv;
bufw_WEN_A <= ap_const_lv4_0;
col_b_1_fu_819_p2 <= std_logic_vector(unsigned(ap_const_lv5_1) + unsigned(col_b_mid1_reg_2363));
col_b_cast2_mid2_cas_fu_1182_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(col_b_cast2_mid2_reg_2489),14));
col_b_cast2_mid2_fu_996_p3 <=
col_b_1_reg_2408 when (tmp_2_mid2_reg_2328(0) = '1') else
col_b_mid1_reg_2363;
col_b_mid1_fu_767_p3 <=
ap_const_lv5_0 when (tmp_7_reg_2322(0) = '1') else
col_b_reg_543;
col_b_phi_fu_547_p4_assign_proc : process(col_b_reg_543, exitcond_flatten3_reg_2229, ap_CS_fsm_pp0_stage0, col_b_cast2_mid2_reg_2489, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten3_reg_2229 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
col_b_phi_fu_547_p4 <= col_b_cast2_mid2_reg_2489;
else
col_b_phi_fu_547_p4 <= col_b_reg_543;
end if;
end process;
exitcond_flatten1_fu_656_p2 <= "1" when (indvar_flatten_phi_fu_535_p4 = ap_const_lv10_100) else "0";
exitcond_flatten2_fu_639_p2 <= "1" when (indvar_flatten3_phi_fu_511_p4 = ap_const_lv14_1000) else "0";
exitcond_flatten3_fu_621_p2 <= "1" when (indvar_flatten1_phi_fu_465_p4 = ap_const_lv17_19000) else "0";
exitcond_flatten43_m_fu_688_p2 <= (exitcond_flatten2_reg_2251 and not_exitcond_flatten_reg_2262);
exitcond_flatten43_n_fu_662_p2 <= (exitcond_flatten2_reg_2251 xor ap_const_lv1_1);
exitcond_flatten_fu_633_p2 <= "1" when (indvar_flatten2_phi_fu_488_p4 = ap_const_lv16_5000) else "0";
exitcond_flatten_mid_2_fu_692_p2 <= (exitcond_flatten_mid_fu_684_p2 and not_exitcond_flatten_1_reg_2274);
exitcond_flatten_mid_fu_684_p2 <= (exitcond_flatten1_reg_2269 and not_exitcond_flatten_reg_2262);
grp_fu_1043_p0 <= (ap_const_lv55_0 & tmp_65_fu_1020_p2);
grp_fu_1043_p1 <= ((ap_const_lv53_0 & tmp_65_fu_1020_p2) & ap_const_lv2_0);
grp_fu_1112_p0 <= (ap_const_lv55_0 & tmp_73_fu_1089_p2);
grp_fu_1112_p1 <= ((ap_const_lv53_0 & tmp_73_fu_1089_p2) & ap_const_lv2_0);
grp_fu_1190_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_cast7_mid2_reg_2386),64));
grp_fu_1218_p0 <= (ap_const_lv55_0 & tmp_81_fu_1195_p2);
grp_fu_1218_p1 <= ((ap_const_lv53_0 & tmp_81_fu_1195_p2) & ap_const_lv2_0);
grp_fu_1290_p0 <= (ap_const_lv55_0 & tmp_89_fu_1267_p2);
grp_fu_1290_p1 <= ((ap_const_lv53_0 & tmp_89_fu_1267_p2) & ap_const_lv2_0);
grp_fu_1364_p0 <= (ap_const_lv55_0 & tmp_97_fu_1341_p2);
grp_fu_1364_p1 <= ((ap_const_lv53_0 & tmp_97_fu_1341_p2) & ap_const_lv2_0);
grp_fu_1434_p0 <= (ap_const_lv55_0 & tmp_105_fu_1411_p2);
grp_fu_1434_p1 <= ((ap_const_lv53_0 & tmp_105_fu_1411_p2) & ap_const_lv2_0);
grp_fu_1508_p0 <= (ap_const_lv55_0 & tmp_122_fu_1485_p2);
grp_fu_1508_p1 <= ((ap_const_lv53_0 & tmp_122_fu_1485_p2) & ap_const_lv2_0);
grp_fu_1537_p0 <= (ap_const_lv55_0 & tmp_129_fu_1514_p2);
grp_fu_1537_p1 <= ((ap_const_lv53_0 & tmp_129_fu_1514_p2) & ap_const_lv2_0);
grp_fu_1566_p0 <= (ap_const_lv55_0 & tmp_136_fu_1543_p2);
grp_fu_1566_p1 <= ((ap_const_lv53_0 & tmp_136_fu_1543_p2) & ap_const_lv2_0);
grp_fu_1595_p0 <= (ap_const_lv55_0 & tmp_143_fu_1572_p2);
grp_fu_1595_p1 <= ((ap_const_lv53_0 & tmp_143_fu_1572_p2) & ap_const_lv2_0);
grp_fu_1624_p0 <= (ap_const_lv55_0 & tmp_150_fu_1601_p2);
grp_fu_1624_p1 <= ((ap_const_lv53_0 & tmp_150_fu_1601_p2) & ap_const_lv2_0);
grp_fu_1653_p0 <= (ap_const_lv55_0 & tmp_157_fu_1630_p2);
grp_fu_1653_p1 <= ((ap_const_lv53_0 & tmp_157_fu_1630_p2) & ap_const_lv2_0);
grp_fu_1682_p0 <= (ap_const_lv55_0 & tmp_164_fu_1659_p2);
grp_fu_1682_p1 <= ((ap_const_lv53_0 & tmp_164_fu_1659_p2) & ap_const_lv2_0);
grp_fu_567_p0_assign_proc : process(reg_575, ap_CS_fsm_pp0_stage6, ap_enable_reg_pp0_iter7, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage11, bufo_load_reg_2809, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage15, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2, tmp_10_reg_3664, tmp_10_1_reg_3689, ap_enable_reg_pp0_iter3, tmp_10_2_reg_3694, tmp_10_3_reg_3699, ap_enable_reg_pp0_iter4, tmp_10_4_reg_3704, ap_enable_reg_pp0_iter5, tmp_10_5_reg_3709, ap_enable_reg_pp0_iter6, tmp_10_7_reg_3714, ap_enable_reg_pp0_iter8, tmp_10_8_reg_3719, ap_enable_reg_pp0_iter9, tmp_10_9_reg_3724, ap_enable_reg_pp0_iter10, tmp_10_s_reg_3729, tmp_10_10_reg_3734, ap_enable_reg_pp0_iter11, tmp_10_11_reg_3739, ap_enable_reg_pp0_iter12, tmp_10_12_reg_3744, ap_enable_reg_pp0_iter13, tmp_10_13_reg_3749, ap_enable_reg_pp0_iter14, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter14) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_567_p0 <= tmp_10_13_reg_3749;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_const_logic_1 = ap_enable_reg_pp0_iter13) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_567_p0 <= tmp_10_12_reg_3744;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_const_logic_1 = ap_enable_reg_pp0_iter12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_567_p0 <= tmp_10_11_reg_3739;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_const_logic_1 = ap_enable_reg_pp0_iter11) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_567_p0 <= tmp_10_10_reg_3734;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter11) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_567_p0 <= tmp_10_s_reg_3729;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter10) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_567_p0 <= tmp_10_9_reg_3724;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_567_p0 <= tmp_10_8_reg_3719;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_567_p0 <= tmp_10_7_reg_3714;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_567_p0 <= reg_575;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_567_p0 <= tmp_10_5_reg_3709;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_567_p0 <= tmp_10_4_reg_3704;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_567_p0 <= tmp_10_3_reg_3699;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_567_p0 <= tmp_10_2_reg_3694;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_567_p0 <= tmp_10_1_reg_3689;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_567_p0 <= tmp_10_reg_3664;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_567_p0 <= bufo_load_reg_2809;
else
grp_fu_567_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_567_p1_assign_proc : process(ap_CS_fsm_pp0_stage6, ap_enable_reg_pp0_iter7, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage15, ap_enable_reg_pp0_iter1, tmp_8_reg_3429, tmp_8_1_reg_3529, ap_reg_pp0_iter2_tmp_8_2_reg_3554, ap_reg_pp0_iter3_tmp_8_3_reg_3574, ap_reg_pp0_iter4_tmp_8_4_reg_3594, ap_reg_pp0_iter4_tmp_8_5_reg_3609, ap_reg_pp0_iter5_tmp_8_6_reg_3624, ap_reg_pp0_iter6_tmp_8_7_reg_3634, ap_reg_pp0_iter7_tmp_8_8_reg_3639, ap_reg_pp0_iter8_tmp_8_9_reg_3649, ap_enable_reg_pp0_iter2, ap_reg_pp0_iter10_tmp_8_s_reg_3654, ap_reg_pp0_iter10_tmp_8_10_reg_3659, ap_reg_pp0_iter11_tmp_8_11_reg_3669, ap_reg_pp0_iter12_tmp_8_12_reg_3674, ap_reg_pp0_iter13_tmp_8_13_reg_3679, ap_reg_pp0_iter14_tmp_8_14_reg_3684, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_enable_reg_pp0_iter8, ap_enable_reg_pp0_iter9, ap_enable_reg_pp0_iter10, ap_enable_reg_pp0_iter11, ap_enable_reg_pp0_iter12, ap_enable_reg_pp0_iter13, ap_enable_reg_pp0_iter14, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter14) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_567_p1 <= ap_reg_pp0_iter14_tmp_8_14_reg_3684;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_const_logic_1 = ap_enable_reg_pp0_iter13) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_567_p1 <= ap_reg_pp0_iter13_tmp_8_13_reg_3679;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_const_logic_1 = ap_enable_reg_pp0_iter12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_567_p1 <= ap_reg_pp0_iter12_tmp_8_12_reg_3674;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_const_logic_1 = ap_enable_reg_pp0_iter11) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_567_p1 <= ap_reg_pp0_iter11_tmp_8_11_reg_3669;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter11) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_567_p1 <= ap_reg_pp0_iter10_tmp_8_10_reg_3659;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter10) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_567_p1 <= ap_reg_pp0_iter10_tmp_8_s_reg_3654;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_567_p1 <= ap_reg_pp0_iter8_tmp_8_9_reg_3649;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_567_p1 <= ap_reg_pp0_iter7_tmp_8_8_reg_3639;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter7) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_567_p1 <= ap_reg_pp0_iter6_tmp_8_7_reg_3634;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_567_p1 <= ap_reg_pp0_iter5_tmp_8_6_reg_3624;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_567_p1 <= ap_reg_pp0_iter4_tmp_8_5_reg_3609;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_567_p1 <= ap_reg_pp0_iter4_tmp_8_4_reg_3594;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_567_p1 <= ap_reg_pp0_iter3_tmp_8_3_reg_3574;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_567_p1 <= ap_reg_pp0_iter2_tmp_8_2_reg_3554;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_567_p1 <= tmp_8_1_reg_3529;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_567_p1 <= tmp_8_reg_3429;
else
grp_fu_567_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_571_p0_assign_proc : process(ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage11, bufw_load_reg_2804, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage13, bufw_load_8_reg_2979, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage15, bufw_load_1_reg_3104, bufw_load_2_reg_3154, ap_enable_reg_pp0_iter1, bufw_load_3_reg_3264, bufw_load_4_reg_3334, bufw_load_5_reg_3399, bufw_load_6_reg_3434, bufw_load_7_reg_3464, bufw_load_9_reg_3499, bufw_load_10_reg_3534, bufw_load_11_reg_3559, bufw_load_12_reg_3579, bufw_load_13_reg_3599, bufw_load_14_reg_3629, bufw_load_15_reg_3644, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_571_p0 <= bufw_load_15_reg_3644;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_571_p0 <= bufw_load_14_reg_3629;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_571_p0 <= bufw_load_13_reg_3599;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_571_p0 <= bufw_load_12_reg_3579;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_571_p0 <= bufw_load_11_reg_3559;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_571_p0 <= bufw_load_10_reg_3534;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_571_p0 <= bufw_load_9_reg_3499;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_571_p0 <= bufw_load_8_reg_2979;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_571_p0 <= bufw_load_7_reg_3464;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_571_p0 <= bufw_load_6_reg_3434;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_571_p0 <= bufw_load_5_reg_3399;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_571_p0 <= bufw_load_4_reg_3334;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_571_p0 <= bufw_load_3_reg_3264;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_571_p0 <= bufw_load_2_reg_3154;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_571_p0 <= bufw_load_1_reg_3104;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_571_p0 <= bufw_load_reg_2804;
else
grp_fu_571_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_571_p1_assign_proc : process(ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage12, bufi_load_reg_2924, ap_CS_fsm_pp0_stage13, bufi_load_1_reg_2974, ap_CS_fsm_pp0_stage14, bufi_load_2_reg_3059, ap_CS_fsm_pp0_stage15, bufi_load_3_reg_3109, ap_enable_reg_pp0_iter1, bufi_load_4_reg_3159, bufi_load_5_reg_3269, bufi_load_6_reg_3339, bufi_load_7_reg_3404, bufi_load_8_reg_3439, bufi_load_9_reg_3469, bufi_load_10_reg_3504, bufi_load_11_reg_3539, bufi_load_12_reg_3564, bufi_load_13_reg_3584, bufi_load_14_reg_3604, bufi_load_15_reg_3614, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
grp_fu_571_p1 <= bufi_load_15_reg_3614;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
grp_fu_571_p1 <= bufi_load_14_reg_3604;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
grp_fu_571_p1 <= bufi_load_13_reg_3584;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_571_p1 <= bufi_load_12_reg_3564;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
grp_fu_571_p1 <= bufi_load_11_reg_3539;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
grp_fu_571_p1 <= bufi_load_10_reg_3504;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
grp_fu_571_p1 <= bufi_load_9_reg_3469;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
grp_fu_571_p1 <= bufi_load_8_reg_3439;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_571_p1 <= bufi_load_7_reg_3404;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
grp_fu_571_p1 <= bufi_load_6_reg_3339;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
grp_fu_571_p1 <= bufi_load_5_reg_3269;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
grp_fu_571_p1 <= bufi_load_4_reg_3159;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_571_p1 <= bufi_load_3_reg_3109;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_571_p1 <= bufi_load_2_reg_3059;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_571_p1 <= bufi_load_1_reg_2974;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
grp_fu_571_p1 <= bufi_load_reg_2924;
else
grp_fu_571_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_890_p0 <= (ap_const_lv55_0 & tmp_57_fu_866_p2);
grp_fu_890_p1 <= ((ap_const_lv53_0 & tmp_57_fu_866_p2) & ap_const_lv2_0);
grp_fu_920_p0 <= (ap_const_lv55_0 & tmp_112_fu_896_p2);
grp_fu_920_p1 <= ((ap_const_lv53_0 & tmp_112_fu_896_p2) & ap_const_lv2_0);
i_1_fu_749_p2 <= std_logic_vector(unsigned(ap_const_lv3_1) + unsigned(i_reg_472));
i_cast6_mid2_fu_1148_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_cast7_mid2_reg_2386),64));
i_cast7_fu_581_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_phi_fu_476_p4),6));
i_cast7_mid2_cast_fu_931_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_cast7_mid2_reg_2386),6));
i_cast7_mid2_fu_803_p3 <=
i_1_reg_2345 when (exitcond_flatten_reg_2238(0) = '1') else
i_reg_472;
i_phi_fu_476_p4_assign_proc : process(i_reg_472, exitcond_flatten3_reg_2229, ap_CS_fsm_pp0_stage0, i_cast7_mid2_reg_2386, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten3_reg_2229 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
i_phi_fu_476_p4 <= i_cast7_mid2_reg_2386;
else
i_phi_fu_476_p4 <= i_reg_472;
end if;
end process;
indvar_flatten1_phi_fu_465_p4_assign_proc : process(indvar_flatten1_reg_461, exitcond_flatten3_reg_2229, ap_CS_fsm_pp0_stage0, indvar_flatten_next3_reg_2233, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten3_reg_2229 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
indvar_flatten1_phi_fu_465_p4 <= indvar_flatten_next3_reg_2233;
else
indvar_flatten1_phi_fu_465_p4 <= indvar_flatten1_reg_461;
end if;
end process;
indvar_flatten2_phi_fu_488_p4_assign_proc : process(indvar_flatten2_reg_484, exitcond_flatten3_reg_2229, ap_CS_fsm_pp0_stage0, indvar_flatten_next2_reg_2280, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten3_reg_2229 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
indvar_flatten2_phi_fu_488_p4 <= indvar_flatten_next2_reg_2280;
else
indvar_flatten2_phi_fu_488_p4 <= indvar_flatten2_reg_484;
end if;
end process;
indvar_flatten3_phi_fu_511_p4_assign_proc : process(indvar_flatten3_reg_507, exitcond_flatten3_reg_2229, ap_CS_fsm_pp0_stage0, indvar_flatten_next1_reg_2381, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten3_reg_2229 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
indvar_flatten3_phi_fu_511_p4 <= indvar_flatten_next1_reg_2381;
else
indvar_flatten3_phi_fu_511_p4 <= indvar_flatten3_reg_507;
end if;
end process;
indvar_flatten41_op_fu_743_p2 <= std_logic_vector(unsigned(ap_const_lv14_1) + unsigned(indvar_flatten3_reg_507));
indvar_flatten81_op_fu_645_p2 <= std_logic_vector(unsigned(ap_const_lv16_1) + unsigned(indvar_flatten2_phi_fu_488_p4));
indvar_flatten_next1_fu_797_p3 <=
ap_const_lv14_1 when (tmp_3_reg_2315(0) = '1') else
indvar_flatten41_op_reg_2340;
indvar_flatten_next2_fu_672_p3 <=
ap_const_lv16_1 when (exitcond_flatten_reg_2238(0) = '1') else
indvar_flatten81_op_reg_2257;
indvar_flatten_next3_fu_627_p2 <= std_logic_vector(unsigned(ap_const_lv17_1) + unsigned(indvar_flatten1_phi_fu_465_p4));
indvar_flatten_next_fu_791_p3 <=
ap_const_lv10_1 when (tmp_7_reg_2322(0) = '1') else
indvar_flatten_op_reg_2335;
indvar_flatten_op_fu_737_p2 <= std_logic_vector(unsigned(ap_const_lv10_1) + unsigned(indvar_flatten_reg_531));
indvar_flatten_phi_fu_535_p4_assign_proc : process(indvar_flatten_reg_531, ap_reg_pp0_iter1_exitcond_flatten3_reg_2229, ap_CS_fsm_pp0_stage1, indvar_flatten_next_reg_2376, ap_enable_reg_pp0_iter1, ap_block_pp0_stage1_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_lv1_0 = ap_reg_pp0_iter1_exitcond_flatten3_reg_2229) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
indvar_flatten_phi_fu_535_p4 <= indvar_flatten_next_reg_2376;
else
indvar_flatten_phi_fu_535_p4 <= indvar_flatten_reg_531;
end if;
end process;
j_1_fu_755_p2 <= std_logic_vector(unsigned(ap_const_lv3_1) + unsigned(j_mid_reg_2309));
j_cast4_mid1_cast_fu_952_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(j_1_reg_2351),6));
j_cast4_mid2_cast_fu_1151_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(j_cast5_mid2_reg_2395),14));
j_cast5_fu_585_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(j_phi_fu_499_p4),6));
j_cast5_mid2_cast_fu_949_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(j_cast5_mid2_reg_2395),6));
j_cast5_mid2_fu_809_p3 <=
j_1_reg_2351 when (exitcond_flatten43_m_reg_2290(0) = '1') else
j_mid_reg_2309;
j_mid_fu_697_p3 <=
ap_const_lv3_0 when (exitcond_flatten_reg_2238(0) = '1') else
j_reg_495;
j_phi_fu_499_p4_assign_proc : process(j_reg_495, exitcond_flatten3_reg_2229, ap_CS_fsm_pp0_stage0, j_cast5_mid2_reg_2395, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten3_reg_2229 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
j_phi_fu_499_p4 <= j_cast5_mid2_reg_2395;
else
j_phi_fu_499_p4 <= j_reg_495;
end if;
end process;
not_exitcond_flatten_1_fu_667_p2 <= (exitcond_flatten_reg_2238 or exitcond_flatten43_n_fu_662_p2);
not_exitcond_flatten_2_fu_726_p2 <= (exitcond_flatten_mid_2_reg_2299 xor ap_const_lv1_1);
not_exitcond_flatten_fu_651_p2 <= (exitcond_flatten_reg_2238 xor ap_const_lv1_1);
p_shl10_cast_fu_2034_p3 <= (tmp_172_reg_3229 & ap_const_lv2_0);
p_shl12_cast_fu_2022_p3 <= (tmp_161_reg_3219 & ap_const_lv2_0);
p_shl14_cast_fu_2010_p3 <= (tmp_147_reg_3209 & ap_const_lv2_0);
p_shl16_cast_fu_1998_p3 <= (tmp_133_reg_3199 & ap_const_lv2_0);
p_shl18_cast_fu_1302_p4 <= ((tmp_119_reg_2557 & tmp_116_reg_2644) & ap_const_lv2_0);
p_shl1_cast_fu_1161_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_fu_1154_p3),16));
p_shl20_cast_fu_1909_p3 <= (tmp_115_reg_3149 & ap_const_lv2_0);
p_shl22_cast_fu_1868_p3 <= (tmp_102_reg_3099 & ap_const_lv2_0);
p_shl24_cast_fu_1799_p3 <= (tmp_94_reg_3019 & ap_const_lv2_0);
p_shl26_cast_fu_1754_p3 <= (tmp_86_reg_2964 & ap_const_lv2_0);
p_shl28_cast_fu_1709_p3 <= (tmp_78_reg_2844 & ap_const_lv2_0);
p_shl2_cast_fu_1172_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_12_fu_1165_p3),16));
p_shl30_cast_fu_1461_p3 <= (tmp_70_reg_2779 & ap_const_lv2_0);
p_shl32_cast_fu_1387_p3 <= (tmp_62_reg_2729 & ap_const_lv2_0);
p_shl34_cast_fu_1075_p4 <= ((tmp_53_reg_2437 & tmp_52_reg_2500) & ap_const_lv2_0);
p_shl3_cast_fu_842_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_49_fu_835_p3),12));
p_shl6_cast_fu_2058_p3 <= (tmp_177_reg_3249 & ap_const_lv2_0);
p_shl8_cast_fu_2046_p3 <= (tmp_175_reg_3239 & ap_const_lv2_0);
p_shl_cast_fu_2070_p3 <= (tmp_179_reg_3259 & ap_const_lv2_0);
row_b_1_fu_814_p2 <= std_logic_vector(unsigned(ap_const_lv5_1) + unsigned(row_b_mid_reg_2357));
row_b_cast3_mid2_cas_fu_1049_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(row_b_cast3_mid2_reg_2473),10));
row_b_cast3_mid2_fu_969_p3 <=
row_b_1_reg_2402 when (exitcond_flatten_mid_2_reg_2299(0) = '1') else
row_b_mid_reg_2357;
row_b_mid_fu_760_p3 <=
ap_const_lv5_0 when (tmp_3_reg_2315(0) = '1') else
row_b_reg_519;
row_b_phi_fu_523_p4_assign_proc : process(row_b_reg_519, exitcond_flatten3_reg_2229, ap_CS_fsm_pp0_stage0, row_b_cast3_mid2_reg_2473, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten3_reg_2229 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
row_b_phi_fu_523_p4 <= row_b_cast3_mid2_reg_2473;
else
row_b_phi_fu_523_p4 <= row_b_reg_519;
end if;
end process;
tmp_101_fu_1811_p1 <= grp_fu_1729_p2(14 - 1 downto 0);
tmp_102_fu_1815_p1 <= grp_fu_1729_p2(12 - 1 downto 0);
tmp_103_fu_1875_p2 <= std_logic_vector(unsigned(tmp_101_reg_3094) + unsigned(p_shl22_cast_fu_1868_p3));
tmp_104_cast_fu_1990_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_104_reg_3184),64));
tmp_104_fu_1905_p2 <= std_logic_vector(unsigned(tmp_103_reg_3139) + unsigned(j_cast4_mid2_cast_reg_2585));
tmp_105_fu_1411_p2 <= (tmp_48_reg_2414 or ap_const_lv9_7);
tmp_109_fu_1880_p1 <= grp_fu_1774_p2(14 - 1 downto 0);
tmp_110_fu_1916_p2 <= std_logic_vector(unsigned(tmp_109_reg_3144) + unsigned(p_shl20_cast_fu_1909_p3));
tmp_111_cast_fu_2095_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_111_reg_3294),64));
tmp_111_fu_1994_p2 <= std_logic_vector(unsigned(tmp_110_reg_3189) + unsigned(j_cast4_mid2_cast_reg_2585));
tmp_112_fu_896_p2 <= (tmp_48_fu_824_p3 or ap_const_lv9_8);
tmp_115_fu_1884_p1 <= grp_fu_1774_p2(12 - 1 downto 0);
tmp_116_fu_1224_p2 <= (tmp_117_reg_2547 or i_cast7_mid2_reg_2386);
tmp_117_fu_1118_p1 <= grp_fu_920_p2(3 - 1 downto 0);
tmp_118_cast_fu_1296_p3 <= (tmp_118_reg_2552 & tmp_116_reg_2644);
tmp_11_fu_1154_p3 <= (tmp_6_cast_mid2_reg_2516 & ap_const_lv5_0);
tmp_120_fu_1310_p2 <= std_logic_vector(unsigned(tmp_118_cast_fu_1296_p3) + unsigned(p_shl18_cast_fu_1302_p4));
tmp_121_cast_fu_1440_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_121_reg_2749),64));
tmp_121_fu_1370_p2 <= std_logic_vector(unsigned(tmp_120_reg_2704) + unsigned(j_cast4_mid2_cast_reg_2585));
tmp_122_fu_1485_p2 <= (tmp_48_reg_2414 or ap_const_lv9_9);
tmp_126_fu_1921_p1 <= grp_fu_1819_p2(14 - 1 downto 0);
tmp_127_fu_2005_p2 <= std_logic_vector(unsigned(tmp_126_reg_3194) + unsigned(p_shl16_cast_fu_1998_p3));
tmp_128_cast_fu_2140_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_128_reg_3364),64));
tmp_128_fu_2099_p2 <= std_logic_vector(unsigned(tmp_127_reg_3299) + unsigned(j_cast4_mid2_cast_reg_2585));
tmp_129_fu_1514_p2 <= (tmp_48_reg_2414 or ap_const_lv9_A);
tmp_12_fu_1165_p3 <= (tmp_6_cast_mid2_reg_2516 & ap_const_lv2_0);
tmp_133_fu_1925_p1 <= grp_fu_1819_p2(12 - 1 downto 0);
tmp_134_fu_2017_p2 <= std_logic_vector(unsigned(tmp_140_reg_3204) + unsigned(p_shl14_cast_fu_2010_p3));
tmp_135_cast_fu_2157_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_135_reg_3369),64));
tmp_135_fu_2103_p2 <= std_logic_vector(unsigned(tmp_134_reg_3304) + unsigned(j_cast4_mid2_cast_reg_2585));
tmp_136_fu_1543_p2 <= (tmp_48_reg_2414 or ap_const_lv9_B);
tmp_13_fu_1176_p2 <= std_logic_vector(unsigned(p_shl2_cast_fu_1172_p1) + unsigned(p_shl1_cast_fu_1161_p1));
tmp_140_fu_1929_p1 <= grp_fu_1823_p2(14 - 1 downto 0);
tmp_141_fu_2029_p2 <= std_logic_vector(unsigned(tmp_154_reg_3214) + unsigned(p_shl12_cast_fu_2022_p3));
tmp_142_cast_fu_2179_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_142_reg_3374),64));
tmp_142_fu_2107_p2 <= std_logic_vector(unsigned(tmp_141_reg_3309) + unsigned(j_cast4_mid2_cast_reg_2585));
tmp_143_fu_1572_p2 <= (tmp_48_reg_2414 or ap_const_lv9_C);
tmp_147_fu_1933_p1 <= grp_fu_1823_p2(12 - 1 downto 0);
tmp_148_fu_2041_p2 <= std_logic_vector(unsigned(tmp_168_reg_3224) + unsigned(p_shl10_cast_fu_2034_p3));
tmp_149_cast_fu_2195_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_149_reg_3379),64));
tmp_149_fu_2111_p2 <= std_logic_vector(unsigned(tmp_148_reg_3314) + unsigned(j_cast4_mid2_cast_reg_2585));
tmp_14_fu_1246_p2 <= std_logic_vector(unsigned(ap_const_lv16_510) + unsigned(tmp_13_reg_2604));
tmp_150_fu_1601_p2 <= (tmp_48_reg_2414 or ap_const_lv9_D);
tmp_154_fu_1937_p1 <= grp_fu_1827_p2(14 - 1 downto 0);
tmp_155_fu_2053_p2 <= std_logic_vector(unsigned(tmp_173_reg_3234) + unsigned(p_shl8_cast_fu_2046_p3));
tmp_156_cast_fu_2203_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_156_reg_3384),64));
tmp_156_fu_2115_p2 <= std_logic_vector(unsigned(tmp_155_reg_3319) + unsigned(j_cast4_mid2_cast_reg_2585));
tmp_157_fu_1630_p2 <= (tmp_48_reg_2414 or ap_const_lv9_E);
tmp_15_fu_1316_p2 <= std_logic_vector(unsigned(ap_const_lv16_A20) + unsigned(tmp_13_reg_2604));
tmp_161_fu_1941_p1 <= grp_fu_1827_p2(12 - 1 downto 0);
tmp_162_fu_2065_p2 <= std_logic_vector(unsigned(tmp_176_reg_3244) + unsigned(p_shl6_cast_fu_2058_p3));
tmp_163_cast_fu_2211_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_163_reg_3389),64));
tmp_163_fu_2119_p2 <= std_logic_vector(unsigned(tmp_162_reg_3324) + unsigned(j_cast4_mid2_cast_reg_2585));
tmp_164_fu_1659_p2 <= (tmp_48_reg_2414 or ap_const_lv9_F);
tmp_168_fu_1945_p1 <= grp_fu_1831_p2(14 - 1 downto 0);
tmp_169_fu_2077_p2 <= std_logic_vector(unsigned(tmp_178_reg_3254) + unsigned(p_shl_cast_fu_2070_p3));
tmp_16_fu_1374_p2 <= std_logic_vector(unsigned(ap_const_lv16_F30) + unsigned(tmp_13_reg_2604));
tmp_170_cast_fu_2215_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_170_reg_3394),64));
tmp_170_fu_2123_p2 <= std_logic_vector(unsigned(tmp_169_reg_3329) + unsigned(j_cast4_mid2_cast_reg_2585));
tmp_171_fu_1142_p2 <= std_logic_vector(unsigned(tmp_52_cast1_fu_1062_p1) + unsigned(row_b_cast3_mid2_cas_fu_1049_p1));
tmp_172_fu_1949_p1 <= grp_fu_1831_p2(12 - 1 downto 0);
tmp_173_cast_fu_1228_p3 <= (tmp_171_reg_2562 & ap_const_lv4_0);
tmp_173_fu_1953_p1 <= grp_fu_1835_p2(14 - 1 downto 0);
tmp_174_cast_fu_1241_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_174_fu_1235_p2),64));
tmp_174_fu_1235_p2 <= std_logic_vector(unsigned(tmp_173_cast_fu_1228_p3) + unsigned(col_b_cast2_mid2_cas_fu_1182_p1));
tmp_175_fu_1957_p1 <= grp_fu_1835_p2(12 - 1 downto 0);
tmp_176_fu_1961_p1 <= grp_fu_1839_p2(14 - 1 downto 0);
tmp_177_fu_1965_p1 <= grp_fu_1839_p2(12 - 1 downto 0);
tmp_178_fu_1969_p1 <= grp_fu_1843_p2(14 - 1 downto 0);
tmp_179_fu_1973_p1 <= grp_fu_1843_p2(12 - 1 downto 0);
tmp_17_fu_1444_p2 <= std_logic_vector(unsigned(ap_const_lv16_1440) + unsigned(tmp_13_reg_2604));
tmp_18_fu_1688_p2 <= std_logic_vector(unsigned(ap_const_lv16_1950) + unsigned(tmp_13_reg_2604));
tmp_19_fu_1733_p2 <= std_logic_vector(unsigned(ap_const_lv16_1E60) + unsigned(tmp_13_reg_2604));
tmp_1_fu_605_p2 <= std_logic_vector(shift_left(unsigned(col_b_phi_fu_547_p4),to_integer(unsigned('0' & ap_const_lv5_1(5-1 downto 0)))));
tmp_20_fu_1778_p2 <= std_logic_vector(unsigned(ap_const_lv16_2370) + unsigned(tmp_13_reg_2604));
tmp_21_fu_1847_p2 <= std_logic_vector(unsigned(ap_const_lv16_2880) + unsigned(tmp_13_reg_2604));
tmp_22_fu_1888_p2 <= std_logic_vector(unsigned(ap_const_lv16_2D90) + unsigned(tmp_13_reg_2604));
tmp_23_fu_1977_p2 <= std_logic_vector(unsigned(ap_const_lv16_32A0) + unsigned(tmp_13_reg_2604));
tmp_24_fu_2082_p2 <= std_logic_vector(unsigned(ap_const_lv16_37B0) + unsigned(tmp_13_reg_2604));
tmp_25_fu_2127_p2 <= std_logic_vector(unsigned(ap_const_lv16_3CC0) + unsigned(tmp_13_reg_2604));
tmp_26_fu_2144_p2 <= std_logic_vector(unsigned(ap_const_lv16_41D0) + unsigned(tmp_13_reg_2604));
tmp_27_fu_2161_p2 <= std_logic_vector(unsigned(ap_const_lv16_46E0) + unsigned(tmp_13_reg_2604));
tmp_28_fu_2166_p2 <= std_logic_vector(unsigned(ap_const_lv16_4BF0) + unsigned(tmp_13_reg_2604));
tmp_29_fu_774_p2 <= (tmp_2_mid2_reg_2328 or exitcond_flatten_mid_2_reg_2299);
tmp_2_fu_678_p2 <= "1" when (to_b_phi_fu_559_p4 = ap_const_lv5_10) else "0";
tmp_2_mid1_fu_712_p2 <= (tmp_2_mid_fu_704_p2 and not_exitcond_flatten_1_reg_2274);
tmp_2_mid2_fu_731_p2 <= (tmp_2_mid1_fu_712_p2 and not_exitcond_flatten_2_fu_726_p2);
tmp_2_mid_fu_704_p2 <= (tmp_2_reg_2285 and not_exitcond_flatten_reg_2262);
tmp_30_fu_778_p2 <= (tmp_29_fu_774_p2 or tmp_3_reg_2315);
tmp_31_fu_1001_p2 <= std_logic_vector(shift_left(unsigned(col_b_1_reg_2408),to_integer(unsigned('0' & ap_const_lv5_1(5-1 downto 0)))));
tmp_32_fu_1254_p2 <= std_logic_vector(unsigned(tmp_13_reg_2604) + unsigned(tmp_cast_mid2_cast_fu_1251_p1));
tmp_33_fu_1325_p2 <= std_logic_vector(unsigned(tmp_14_reg_2655) + unsigned(tmp_cast_mid2_cast_reg_2660));
tmp_34_fu_1383_p2 <= std_logic_vector(unsigned(tmp_15_reg_2709) + unsigned(tmp_cast_mid2_cast_reg_2660));
tmp_35_cast_fu_1321_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_32_reg_2679),64));
tmp_35_fu_1453_p2 <= std_logic_vector(unsigned(tmp_16_reg_2754) + unsigned(tmp_cast_mid2_cast_reg_2660));
tmp_36_cast_fu_1379_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_33_reg_2719),64));
tmp_36_fu_1697_p2 <= std_logic_vector(unsigned(tmp_17_reg_2814) + unsigned(tmp_cast_mid2_cast_reg_2660));
tmp_37_cast_fu_1449_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_34_reg_2764),64));
tmp_37_fu_1742_p2 <= std_logic_vector(unsigned(tmp_18_reg_2929) + unsigned(tmp_cast_mid2_cast_reg_2660));
tmp_38_cast_fu_1693_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_35_reg_2824),64));
tmp_38_fu_1787_p2 <= std_logic_vector(unsigned(tmp_19_reg_2984) + unsigned(tmp_cast_mid2_cast_reg_2660));
tmp_39_cast_fu_1738_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_36_reg_2939),64));
tmp_39_fu_1856_p2 <= std_logic_vector(unsigned(tmp_20_reg_3064) + unsigned(tmp_cast_mid2_cast_reg_2660));
tmp_3_fu_708_p2 <= (exitcond_flatten43_m_reg_2290 or exitcond_flatten_reg_2238);
tmp_40_cast_fu_1783_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_37_reg_2994),64));
tmp_40_fu_1897_p2 <= std_logic_vector(unsigned(tmp_21_reg_3114) + unsigned(tmp_cast_mid2_cast_reg_2660));
tmp_41_cast_fu_1852_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_38_reg_3074),64));
tmp_41_fu_1986_p2 <= std_logic_vector(unsigned(tmp_22_reg_3164) + unsigned(tmp_cast_mid2_cast_reg_2660));
tmp_42_cast_fu_1893_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_39_reg_3124),64));
tmp_42_fu_2091_p2 <= std_logic_vector(unsigned(tmp_23_reg_3274) + unsigned(tmp_cast_mid2_cast_reg_2660));
tmp_43_cast_fu_1982_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_40_reg_3174),64));
tmp_43_fu_2136_p2 <= std_logic_vector(unsigned(tmp_24_reg_3344) + unsigned(tmp_cast_mid2_cast_reg_2660));
tmp_44_cast_fu_2087_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_41_reg_3284),64));
tmp_44_fu_2153_p2 <= std_logic_vector(unsigned(tmp_25_reg_3409) + unsigned(tmp_cast_mid2_cast_reg_2660));
tmp_45_cast_fu_2132_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_42_reg_3354),64));
tmp_45_fu_2175_p2 <= std_logic_vector(unsigned(tmp_26_reg_3444) + unsigned(tmp_cast_mid2_cast_reg_2660));
tmp_46_cast_fu_2149_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_43_reg_3419),64));
tmp_46_fu_2187_p2 <= std_logic_vector(unsigned(tmp_27_reg_3474) + unsigned(tmp_cast_mid2_cast_reg_2660));
tmp_47_cast_fu_2171_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_44_reg_3454),64));
tmp_47_fu_2191_p2 <= std_logic_vector(unsigned(tmp_28_reg_3479) + unsigned(tmp_cast_mid2_cast_reg_2660));
tmp_48_cast_fu_2183_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_45_reg_3489),64));
tmp_48_fu_824_p3 <= (to_b_mid2_reg_2369 & ap_const_lv4_0);
tmp_49_cast_fu_2199_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_46_reg_3514),64));
tmp_49_fu_835_p3 <= (to_b_mid2_reg_2369 & ap_const_lv6_0);
tmp_50_cast_fu_2207_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_47_reg_3519),64));
tmp_50_fu_846_p2 <= std_logic_vector(unsigned(tmp_52_cast_fu_831_p1) + unsigned(p_shl3_cast_fu_842_p1));
tmp_51_fu_852_p1 <= tmp_50_fu_846_p2(3 - 1 downto 0);
tmp_52_cast1_fu_1062_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_48_reg_2414),10));
tmp_52_cast_fu_831_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_48_fu_824_p3),12));
tmp_52_fu_1016_p2 <= (tmp_51_reg_2432 or i_cast7_mid2_reg_2386);
tmp_54_fu_1065_p3 <= (tmp_53_reg_2437 & tmp_52_reg_2500);
tmp_55_fu_1083_p2 <= std_logic_vector(unsigned(tmp_59_cast_fu_1071_p1) + unsigned(p_shl34_cast_fu_1075_p4));
tmp_56_fu_1185_p2 <= std_logic_vector(unsigned(tmp_55_reg_2527) + unsigned(j_cast4_mid2_cast_fu_1151_p1));
tmp_57_fu_866_p2 <= (tmp_48_fu_824_p3 or ap_const_lv9_1);
tmp_59_cast_fu_1071_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_54_fu_1065_p3),14));
tmp_5_cast_fu_595_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_fu_589_p2),6));
tmp_5_cast_mid1_fu_979_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_9_fu_974_p2),6));
tmp_5_fu_717_p2 <= (exitcond_flatten_mid_2_reg_2299 or exitcond_flatten43_m_reg_2290);
tmp_61_fu_1329_p1 <= grp_fu_1190_p2(14 - 1 downto 0);
tmp_62_cast_fu_1259_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_56_reg_2624),64));
tmp_62_fu_1333_p1 <= grp_fu_1190_p2(12 - 1 downto 0);
tmp_63_fu_1394_p2 <= std_logic_vector(unsigned(tmp_61_reg_2724) + unsigned(p_shl32_cast_fu_1387_p3));
tmp_64_fu_1457_p2 <= std_logic_vector(unsigned(tmp_63_reg_2769) + unsigned(j_cast4_mid2_cast_reg_2585));
tmp_65_fu_1020_p2 <= (tmp_48_reg_2414 or ap_const_lv9_2);
tmp_69_cast_fu_1701_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_64_reg_2829),64));
tmp_69_fu_1399_p1 <= grp_fu_1263_p2(14 - 1 downto 0);
tmp_6_cast_mid2_fu_1052_p3 <=
tmp_6_mid1_reg_2479 when (exitcond_flatten_mid_2_reg_2299(0) = '1') else
tmp_6_cast_mid5_reg_2468;
tmp_6_cast_mid3_fu_937_p3 <=
tmp_6_cast_mid_cast_fu_934_p1 when (exitcond_flatten_reg_2238(0) = '1') else
tmp_6_reg_2219;
tmp_6_cast_mid5_fu_955_p3 <=
i_cast7_mid2_cast_fu_931_p1 when (exitcond_flatten43_m_reg_2290(0) = '1') else
tmp_6_cast_mid3_fu_937_p3;
tmp_6_cast_mid_cast_fu_934_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_1_reg_2345),6));
tmp_6_fu_599_p2 <= std_logic_vector(unsigned(i_cast7_fu_581_p1) + unsigned(tmp_5_cast_fu_595_p1));
tmp_6_mid1_fu_983_p2 <= std_logic_vector(unsigned(i_cast7_mid2_cast_fu_931_p1) + unsigned(tmp_5_cast_mid1_fu_979_p1));
tmp_70_fu_1403_p1 <= grp_fu_1263_p2(12 - 1 downto 0);
tmp_71_fu_1468_p2 <= std_logic_vector(unsigned(tmp_69_reg_2774) + unsigned(p_shl30_cast_fu_1461_p3));
tmp_72_fu_1705_p2 <= std_logic_vector(unsigned(tmp_71_reg_2834) + unsigned(j_cast4_mid2_cast_reg_2585));
tmp_73_fu_1089_p2 <= (tmp_48_reg_2414 or ap_const_lv9_3);
tmp_76_cast_fu_1746_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_72_reg_2949),64));
tmp_77_fu_1473_p1 <= grp_fu_1337_p2(14 - 1 downto 0);
tmp_78_fu_1477_p1 <= grp_fu_1337_p2(12 - 1 downto 0);
tmp_79_fu_1716_p2 <= std_logic_vector(unsigned(tmp_77_reg_2839) + unsigned(p_shl28_cast_fu_1709_p3));
tmp_7_fu_721_p2 <= (tmp_5_fu_717_p2 or exitcond_flatten_reg_2238);
tmp_80_fu_1750_p2 <= std_logic_vector(unsigned(tmp_79_reg_2954) + unsigned(j_cast4_mid2_cast_reg_2585));
tmp_81_fu_1195_p2 <= (tmp_48_reg_2414 or ap_const_lv9_4);
tmp_83_cast_fu_1791_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_80_reg_3004),64));
tmp_85_fu_1721_p1 <= grp_fu_1407_p2(14 - 1 downto 0);
tmp_86_fu_1725_p1 <= grp_fu_1407_p2(12 - 1 downto 0);
tmp_87_fu_1761_p2 <= std_logic_vector(unsigned(tmp_85_reg_2959) + unsigned(p_shl26_cast_fu_1754_p3));
tmp_88_fu_1795_p2 <= std_logic_vector(unsigned(tmp_87_reg_3009) + unsigned(j_cast4_mid2_cast_reg_2585));
tmp_89_fu_1267_p2 <= (tmp_48_reg_2414 or ap_const_lv9_5);
tmp_90_cast_fu_1860_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_88_reg_3084),64));
tmp_93_fu_1766_p1 <= grp_fu_1481_p2(14 - 1 downto 0);
tmp_94_fu_1770_p1 <= grp_fu_1481_p2(12 - 1 downto 0);
tmp_95_fu_1806_p2 <= std_logic_vector(unsigned(tmp_93_reg_3014) + unsigned(p_shl24_cast_fu_1799_p3));
tmp_96_fu_1864_p2 <= std_logic_vector(unsigned(tmp_95_reg_3089) + unsigned(j_cast4_mid2_cast_reg_2585));
tmp_97_cast_fu_1901_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_96_reg_3134),64));
tmp_97_fu_1341_p2 <= (tmp_48_reg_2414 or ap_const_lv9_6);
tmp_9_cast_fu_611_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_1_fu_605_p2),6));
tmp_9_cast_mid1_fu_1006_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_31_fu_1001_p2),6));
tmp_9_fu_974_p2 <= std_logic_vector(shift_left(unsigned(row_b_1_reg_2402),to_integer(unsigned('0' & ap_const_lv5_1(5-1 downto 0)))));
tmp_cast_mid2_cast_fu_1251_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_cast_mid2_reg_2522),16));
tmp_cast_mid2_fu_1057_p3 <=
tmp_mid1_reg_2495 when (tmp_2_mid2_reg_2328(0) = '1') else
tmp_cast_mid5_reg_2484;
tmp_cast_mid3_fu_962_p3 <=
j_cast4_mid1_cast_fu_952_p1 when (exitcond_flatten43_m_reg_2290(0) = '1') else
tmp_cast_mid_fu_943_p3;
tmp_cast_mid5_fu_989_p3 <=
j_cast5_mid2_cast_fu_949_p1 when (exitcond_flatten_mid_2_reg_2299(0) = '1') else
tmp_cast_mid3_fu_962_p3;
tmp_cast_mid_fu_943_p3 <=
ap_const_lv6_0 when (exitcond_flatten_reg_2238(0) = '1') else
tmp_s_reg_2224;
tmp_fu_589_p2 <= std_logic_vector(shift_left(unsigned(row_b_phi_fu_523_p4),to_integer(unsigned('0' & ap_const_lv5_1(5-1 downto 0)))));
tmp_mid1_fu_1010_p2 <= std_logic_vector(unsigned(j_cast5_mid2_cast_fu_949_p1) + unsigned(tmp_9_cast_mid1_fu_1006_p1));
tmp_s_fu_615_p2 <= std_logic_vector(unsigned(j_cast5_fu_585_p1) + unsigned(tmp_9_cast_fu_611_p1));
to_b_1_fu_926_p2 <= std_logic_vector(unsigned(ap_const_lv5_1) + unsigned(to_b_mid2_reg_2369));
to_b_mid2_fu_783_p3 <=
ap_const_lv5_0 when (tmp_30_fu_778_p2(0) = '1') else
to_b_reg_555;
to_b_phi_fu_559_p4_assign_proc : process(to_b_reg_555, ap_reg_pp0_iter1_exitcond_flatten3_reg_2229, ap_CS_fsm_pp0_stage2, to_b_1_reg_2463, ap_enable_reg_pp0_iter1, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_lv1_0 = ap_reg_pp0_iter1_exitcond_flatten3_reg_2229) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
to_b_phi_fu_559_p4 <= to_b_1_reg_2463;
else
to_b_phi_fu_559_p4 <= to_b_reg_555;
end if;
end process;
end behav;
| mit | fa1d44abf096bb90889fc059c42ffd91 | 0.635361 | 2.693085 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/work/debug/cpu_disas.vhd | 1 | 4,217 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: cpu_disas
-- File: cpu_disas.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: Module for disassembly
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
use grlib.sparc.all;
use std.textio.all;
use grlib.sparc_disas.all;
-- pragma translate_on
entity cpu_disas is
port (
clk : in std_ulogic;
rstn : in std_ulogic;
dummy : out std_ulogic;
inst : in std_logic_vector(31 downto 0);
pc : in std_logic_vector(31 downto 2);
result: in std_logic_vector(31 downto 0);
index : in std_logic_vector(3 downto 0);
wreg : in std_ulogic;
annul : in std_ulogic;
holdn : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic);
end;
architecture behav of cpu_disas is
begin
dummy <= '1';
-- pragma translate_off
trc : process(clk)
variable valid : boolean;
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable fpins, fpld : boolean;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
fpins := (op = FMT3) and ((op3 = FPOP1) or (op3 = FPOP2));
fpld := (op = LDST) and ((op3 = LDF) or (op3 = LDDF) or (op3 = LDFSR));
valid := (((not annul) and pv) = '1') and (not ((fpins or fpld) and (trap = '0')));
valid := valid and (holdn = '1');
if rising_edge(clk) and (rstn = '1') then
print_insn (conv_integer(index), pc(31 downto 2) & "00", inst,
result, valid, trap = '1', wreg = '1', false);
end if;
end process;
-- pragma translate_on
end;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
use grlib.sparc.all;
use std.textio.all;
use grlib.sparc_disas.all;
-- pragma translate_on
entity gaisler_cpu_disas is
port (
clk : in std_ulogic;
rstn : in std_ulogic;
dummy : out std_ulogic;
inst : in std_logic_vector(31 downto 0);
pc : in std_logic_vector(31 downto 2);
result: in std_logic_vector(31 downto 0);
index : in std_logic_vector(3 downto 0);
wreg : in std_ulogic;
annul : in std_ulogic;
holdn : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic);
end;
architecture behav of gaisler_cpu_disas is
begin
dummy <= '1';
-- pragma translate_off
trc : process(clk)
variable valid : boolean;
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable fpins, fpld : boolean;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
fpins := (op = FMT3) and ((op3 = FPOP1) or (op3 = FPOP2));
fpld := (op = LDST) and ((op3 = LDF) or (op3 = LDDF) or (op3 = LDFSR));
valid := (((not annul) and pv) = '1') and (not ((fpins or fpld) and (trap = '0')));
valid := valid and (holdn = '1');
if rising_edge(clk) and (rstn = '1') then
print_insn (conv_integer(index), pc(31 downto 2) & "00", inst,
result, valid, trap = '1', wreg = '1', false);
end if;
end process;
-- pragma translate_on
end;
| gpl-2.0 | ba7eb2f9805339e447a36e789d309386 | 0.608964 | 3.456557 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-altera-ep2s60-sdr/testbench.vhd | 1 | 9,465 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 8; -- rom data width (8/32)
romdepth : integer := 23; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 20; -- ram address depth
srambanks : integer := 1 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal clkout, pllref : std_ulogic;
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(23 downto 0);
signal data : std_logic_vector(31 downto 0);
signal ramsn : std_ulogic;
signal ramoen : std_ulogic;
signal rwen : std_ulogic;
signal mben : std_logic_vector(3 downto 0);
--signal rwenx : std_logic_vector(3 downto 0);
signal romsn : std_ulogic;
signal iosn : std_ulogic;
signal oen : std_ulogic;
--signal read : std_ulogic;
signal writen : std_ulogic;
signal brdyn : std_ulogic;
signal bexcn : std_ulogic;
signal wdog : std_ulogic;
signal dsuen, dsutx, dsurx, dsubren, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal test : std_ulogic;
signal error : std_logic;
signal gpio : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal sdcke : std_ulogic; -- clk en
signal sdcsn : std_ulogic; -- chip sel
signal sdwen : std_ulogic; -- write en
signal sdrasn : std_ulogic; -- row addr stb
signal sdcasn : std_ulogic; -- col addr stb
signal sddqm : std_logic_vector (3 downto 0); -- data i/o mask
signal sdclk : std_ulogic;
signal sdba : std_logic_vector(1 downto 0);
signal plllock : std_ulogic;
signal txd1, rxd1 : std_ulogic;
--signal txd2, rxd2 : std_ulogic;
-- for smc lan chip
signal eth_aen : std_ulogic; -- for smsc eth
signal eth_readn : std_ulogic; -- for smsc eth
signal eth_writen : std_ulogic; -- for smsc eth
signal eth_nbe : std_logic_vector(3 downto 0); -- for smsc eth
signal eth_datacsn : std_ulogic;
constant lresp : boolean := false;
signal sa : std_logic_vector(14 downto 0);
signal sd : std_logic_vector(31 downto 0);
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
rst <= dsurst;
dsubren <= '1'; rxd1 <= '1';
d3 : entity work.leon3mp generic map (fabtech, memtech, padtech, clktech,
ncpu, disas, dbguart, pclow )
port map (rst, clk, error, address, data, ramsn, ramoen, rwen, mben, iosn,
romsn, oen, writen, open, open, sa(11 downto 0), sd, sdclk, sdcke,
sdcsn, sdwen, sdrasn, sdcasn, sddqm, sdba, dsutx, dsurx, dsubren,
dsuact, rxd1, txd1, eth_aen, eth_readn,
eth_writen, eth_nbe);
sd1 : if (CFG_MCTRL_SDEN = 1) and (CFG_MCTRL_SEPBUS = 1) generate
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
Ba => sdba, Clk => sdclk, Cke => sdcke,
Cs_n => sdcsn, Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
Ba => sdba, Clk => sdclk, Cke => sdcke,
Cs_n => sdcsn, Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
end generate;
-- 8 bit prom
prom0 : sram generic map (index => 6, abits => romdepth, fname => promfile)
port map (address(romdepth-1 downto 0), data(31 downto 24),
romsn, rwen, oen);
sram0 : for i in 0 to (sramwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
port map (address(sramdepth+1 downto 2), data(31-i*8 downto 24-i*8), ramsn,
rwen, ramoen);
end generate;
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
data <= buskeep(data), (others => 'H') after 250 ns;
sd <= buskeep(sd), (others => 'H') after 250 ns;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data,
iosn, oen, writen, brdyn);
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
| gpl-2.0 | 496a857d73e808e895c42890921f6cd2 | 0.581828 | 3.138263 | false | false | false | false |
VerkhovtsovPavel/BSUIR_Labs | Master/POCP/My_Designs/Stack/src/MRAM.vhd | 1 | 2,042 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library stack;
use stack.OneHotStack.all;
entity MRAM is
port (
CLK: in std_logic;
RW: in std_logic;
ADDR: in mem_addr;
DIN: in operand;
DOUT: out operand
);
end MRAM;
architecture Beh of MRAM is
type tRAM is array (0 to 31) of operand;
signal RAM: tRAM:= (
-- | BIN | ADR BIN
"0000000000000000", -- | 00000 |
"0000000000000000", -- | 00001 |
"0000000000000000", -- | 00010 |
"0000000000000000", -- | 00011 |
"0000000000000000", -- | 00100 |
"0000000000000000", -- | 00101 |
"0000000000000000", -- | 00110 |
"0000000000000000", -- | 00111 |
"0000000000000000", -- | 01000 |
"0000000000000000", -- | 01001 |
"0000000000000000", -- | 01010 |
"0000000000000000", -- | 01011 |
"0000000000000000", -- | 01100 |
"0000000000000000", -- | 01101 |
"0000000000000000", -- | 01110 |
"0000000000000000", -- | 01111 |
"0000000000001000", -- | 10000 |
"0000000000000000", -- | 10001 |
"0000000000000000", -- | 10010 |
"0000000000000001", -- | 10011 |
"0000000000000000", -- | 10100 |
"0000000000000001", -- | 10101 |
others => "0000000000000000"
);
signal data_in: operand;
signal data_out: operand;
Begin
data_in <= Din;
WRITE: process (CLK, RW, ADDR, data_in)
begin
if (RW = '0') then
if (rising_edge(CLK)) then
RAM(conv_integer(ADDR)) <= data_in;
end if;
end if;
end process;
data_out <= RAM (conv_integer(ADDR));
RDP: process (RW, RAM, data_out)
begin
if (RW = '1') then
DOUT <= data_out;
else
DOUT <= (others => 'Z');
end if;
end process;
end Beh; | mit | 5666afd44564c35a4ce893a0040cb5d2 | 0.491185 | 3.781481 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/sim/ddr3ram.vhd | 1 | 30,816 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddr3ram
-- File: ddr3ram.vhd
-- Author: Magnus Hjorth, Aeroflex Gaisler
-- Description: Generic simulation model of DDR3 SDRAM (JESD79-3)
------------------------------------------------------------------------------
--pragma translate_off
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdio.hread;
use grlib.stdlib.all;
entity ddr3ram is
generic (
width: integer := 32;
abits: integer range 13 to 16 := 13;
colbits: integer range 9 to 12 := 10;
rowbits: integer range 1 to 16 := 13;
implbanks: integer range 1 to 8 := 1;
fname: string;
lddelay: time := (0 ns);
ldguard: integer range 0 to 1 := 0; -- 1: wait for doload input before
-- loading RAM
-- Speed bins: 0-1:800E-D, 2-4:1066G-E 5-8:1333J-F 9-12:1600K-G
speedbin: integer range 0 to 12 := 0;
density: integer range 2 to 6 := 3; -- 2:512M 3:1G 4:2G 5:4G 6:8G bits/chip
pagesize: integer range 1 to 2 := 1; -- 1K/2K page size (controls tRRD)
changeendian: integer range 0 to 32 := 0
);
port (
ck: in std_ulogic;
ckn: in std_ulogic;
cke: in std_ulogic;
csn: in std_ulogic;
odt: in std_ulogic;
rasn: in std_ulogic;
casn: in std_ulogic;
wen: in std_ulogic;
dm: in std_logic_vector(width/8-1 downto 0);
ba: in std_logic_vector(2 downto 0);
a: in std_logic_vector(abits-1 downto 0);
resetn: in std_ulogic;
dq: inout std_logic_vector(width-1 downto 0);
dqs: inout std_logic_vector(width/8-1 downto 0);
dqsn: inout std_logic_vector(width/8-1 downto 0);
doload: in std_ulogic := '1'
);
end;
architecture sim of ddr3ram is
type moderegs is record
-- Mode register (0)
ppd: std_ulogic;
wr: std_logic_vector(2 downto 0);
dllres: std_ulogic;
tm: std_ulogic;
rbt: std_ulogic;
caslat: std_logic_vector(3 downto 0);
blen: std_logic_vector(1 downto 0);
-- Extended mode register 1
qoff: std_ulogic;
tdqsen: std_ulogic;
level: std_ulogic;
al: std_logic_vector(1 downto 0);
rtt_nom: std_logic_vector(2 downto 0);
dic: std_logic_vector(1 downto 0);
dlldis: std_ulogic;
-- Extended mode register 2
rtt_wr: std_logic_vector(1 downto 0);
srt: std_ulogic;
asr: std_ulogic;
cwl: std_logic_vector(2 downto 0);
pasr: std_logic_vector(2 downto 0);
-- Extended mode register 3
mpr: std_ulogic;
mprloc: std_logic_vector(1 downto 0);
end record;
-- Mode registers as signal, useful for debugging
signal mr: moderegs;
-- Handshaking between command and DQ/DQS processes
signal read_en, write_en, dqscal_en: boolean := false;
signal read_data, write_data: std_logic_vector(2*width-1 downto 0);
signal write_mask: std_logic_vector(width/4-1 downto 0);
signal initdone: boolean := false;
-- Small delta-t to adjust calculations for jitter tol.
constant deltat: time := 50 ps;
-- Timing parameters
constant tWR: time := 15 ns;
constant tMRD_ck: integer := 4;
constant tRTP_ck: integer := 4;
constant tRTP_t: time := 7.5 ns;
function tRTP(tper: time) return time is
begin
if tRTP_ck*tper > tRTP_t then return tRTP_ck*tper; else return tRTP_t; end if;
end tRTP;
constant tMOD_ck: integer := 12;
constant tMOD_t: time := 15 ns;
type timetab is array (0 to 12) of time;
-- 800E 800D 1066G 1066H 1066E 1333J 1333H 1333G 1333F 1600K 1600J 1600H 1600G
constant tRAS : timetab :=
(37.5 ns, 37.5 ns, 37.5 ns, 37.5 ns, 37.5 ns, 36 ns, 36 ns, 36 ns, 36 ns, 35 ns, 35 ns, 35 ns, 35 ns);
constant tRP : timetab :=
(15 ns, 12.5 ns, 15 ns, 13.125 ns, 11.25 ns, 15 ns, 13.5 ns, 12 ns, 10.5 ns, 13.75 ns, 12.5 ns, 11.25 ns, 10 ns);
constant tRCD: timetab := tRP;
type timetab2 is array(2 to 6) of time;
constant tRFC: timetab2 := (90 ns, 110 ns, 160 ns, 300 ns, 350 ns);
function tRRD(tper: time; speedbin: integer range 0 to 12) return time is
variable t: time;
begin
case speedbin is
when 0 to 1 => t:=10 ns;
when 2 to 4 => if pagesize<2 then t:=7.5 ns; else t:=10 ns; end if;
when 5 to 12 => if pagesize<2 then t:=6 ns; else t:=7.5 ns; end if;
end case;
if t < 4*tper then t:=4*tper; end if;
return t;
end tRRD;
function pick(t,f: integer; b: boolean) return integer is
begin
if b then return t; else return f; end if;
end pick;
begin
-----------------------------------------------------------------------------
-- Init sequence checker
-----------------------------------------------------------------------------
initp: process
procedure checkcmd(crasn,ccasn,cwen: std_ulogic;
cba: std_logic_vector(2 downto 0);
ca: std_logic_vector(15 downto 0)) is
variable amatch: boolean;
begin
wait until rising_edge(ck);
while cke='1' and (csn='1' or (rasn='1' and casn='1' and wen='1')) loop
wait until rising_edge(ck);
end loop;
amatch := true;
for x in a'range loop
if ca(x)/='-' and ca(x)/=a(x) then amatch:=false; end if;
end loop;
assert cke='1' and csn='0' and rasn=crasn and casn=ccasn and wen=cwen and
(cba="---" or cba=ba) and amatch
report "Wrong command during init sequence" severity warning;
end checkcmd;
variable t,t2: time;
variable i: integer;
begin
initdone <= false;
-- Allow resetn to be X or U for a while during sim start
if resetn /= '0' then
wait until resetn='0' for 1 us;
end if;
assert resetn='0' report "RESETn not asserted on power-up" severity warning;
wait until resetn/='0' for 200 us;
assert resetn='0' report "RESETn raised with less than 200 us init delay" severity warning;
l0: loop
initdone <= false;
wait until resetn/='0';
assert cke='0' report "CKE not low when RESETn deasserted" severity warning;
wait until (resetn='0' or cke/='0') for 500 us;
if resetn='0' then next; end if;
assert cke='0' report "CKE raised with less than 500 us delay after RESETn deasserted" severity warning;
wait until (resetn='0' or cke/='0') and rising_edge(ck);
if resetn='0' then next; end if;
assert cke='1' and (csn='1' or (rasn='1' and casn='1' and wen='1'));
t := now;
t2 := t+tRFC(density)+(10 ns);
i := 0;
while i<5 and now<t2 loop
wait until (resetn='0' or rising_edge(ck));
if resetn='0' then next l0; end if;
assert cke='1' and (csn='1' or (rasn='1' and casn='1' and wen='1'));
i := i+1;
end loop;
-- EMRS EMR2
checkcmd('0','0','0',"010","----------------");
if resetn='0' then next; end if;
-- EMRS EMR3
checkcmd('0','0','0',"011","----------------");
if resetn='0' then next; end if;
-- EMRS EMR1 enable DLL
checkcmd('0','0','0',"001","---------------0");
if resetn='0' then next; end if;
-- EMRS EMR0 reset DLL
checkcmd('0','0','0',"000","-------1--------");
if resetn='0' then next; end if;
-- ZQCL
checkcmd('1','1','0',"---","-----1----------");
if resetn='0' then next; end if;
for x in 1 to 512 loop
wait until (resetn='0' or rising_edge(ck));
if resetn='0' then next l0; end if;
assert cke='1' and (csn='1' or (rasn='1' and casn='1' and wen='1'));
end loop;
initdone <= true;
wait until resetn='0';
end loop;
end process;
-----------------------------------------------------------------------------
-- Command state machine
-----------------------------------------------------------------------------
cmdp: process(ck)
-- Data split by bank to avoid exceeding 4G
constant b0size: integer := (2**(colbits+rowbits)) * ((width+15)/16);
constant b1size: integer := pick(b0size, 1, implbanks>1);
constant b2size: integer := pick(b0size, 1, implbanks>2);
constant b3size: integer := pick(b0size, 1, implbanks>3);
constant b4size: integer := pick(b0size, 1, implbanks>4);
constant b5size: integer := pick(b0size, 1, implbanks>5);
constant b6size: integer := pick(b0size, 1, implbanks>6);
constant b7size: integer := pick(b0size, 1, implbanks>7);
subtype coldata is std_logic_vector(width-1 downto 0);
subtype idata is integer range 0 to (2**20)-1; -- 16 data bits + 2x2 X/U state
type idata_arr is array(natural range <>) of idata;
variable memdata0: idata_arr(0 to b0size-1);
variable memdata1: idata_arr(0 to b1size-1);
variable memdata2: idata_arr(0 to b2size-1);
variable memdata3: idata_arr(0 to b3size-1);
variable memdata4: idata_arr(0 to b4size-1);
variable memdata5: idata_arr(0 to b5size-1);
variable memdata6: idata_arr(0 to b6size-1);
variable memdata7: idata_arr(0 to b7size-1);
function reversedata(data : std_logic_vector; step : integer)
return std_logic_vector is
variable rdata: std_logic_vector(data'length-1 downto 0);
begin
for i in 0 to (data'length/step-1) loop
rdata(i*step+step-1 downto i*step) := data(data'length-i*step-1 downto data'length-i*step-step);
end loop;
return rdata;
end function reversedata;
impure function memdata_get(bank,idx: integer) return coldata is
variable r: coldata;
variable x: idata;
variable p: std_logic_vector(19 downto 0);
variable iidx: integer;
begin
iidx := (idx*width)/16;
for q in 0 to (width+15)/16-1 loop
case bank is
when 0 => x := memdata0(iidx+q);
when 1 => x := memdata1(iidx+q);
when 2 => x := memdata2(iidx+q);
when 3 => x := memdata3(iidx+q);
when 4 => x := memdata4(iidx+q);
when 5 => x := memdata5(iidx+q);
when 6 => x := memdata6(iidx+q);
when others => x := memdata7(iidx+q);
end case;
p := std_logic_vector(to_unsigned(x,20));
if p(18)='0' then p(15 downto 8) := "UUUUUUUU";
elsif p(19)='1' then p(15 downto 8) := "XXXXXXXX"; end if;
if p(16)='0' then p(7 downto 0) := "UUUUUUUU";
elsif p(17)='1' then p(7 downto 0) := "XXXXXXXX"; end if;
if width < 16 then
r := p(7 downto 0);
else
r(width-16*q-1 downto width-16*q-16) := p(15 downto 0);
end if;
end loop;
if changeendian /= 0 then
r := reversedata(r, changeendian);
end if;
return r;
end memdata_get;
procedure memdata_set(bank,idx: integer; v: coldata) is
variable n: coldata;
variable x: idata;
variable p: std_logic_vector(19 downto 0);
variable iidx: integer;
begin
-- assert false
-- report ("memdata_set: bank " & tost(bank) & " idx " & tost(idx) & " data " & tost(v))
-- severity note;
n := v;
if changeendian /= 0 then
n := reversedata(n, changeendian);
end if;
iidx := (idx*width)/16;
for q in 0 to (width+15)/16-1 loop
p := "0101" & x"0000";
if width < 16 then
p(7 downto 0) := n;
else
p(15 downto 0) := n(width-16*q-1 downto width-16*q-16);
end if;
if p(15 downto 8)="UUUUUUUU" then p(18):='0'; p(15 downto 8):=x"00";
elsif is_x(p(15 downto 8)) then p(19):='1'; p(15 downto 8):=x"00"; end if;
if p(7 downto 0)="UUUUUUUU" then p(16):='0'; p(7 downto 0):=x"00";
elsif is_x(p(7 downto 0)) then p(17):='1'; p(7 downto 0):=x"00"; end if;
x := to_integer(unsigned(p));
case bank is
when 0 => memdata0(iidx+q) := x;
when 1 => memdata1(iidx+q) := x;
when 2 => memdata2(iidx+q) := x;
when 3 => memdata3(iidx+q) := x;
when 4 => memdata4(iidx+q) := x;
when 5 => memdata5(iidx+q) := x;
when 6 => memdata6(iidx+q) := x;
when others => memdata7(iidx+q) := x;
end case;
end loop;
end memdata_set;
procedure load_srec is
file TCF : text open read_mode is fname;
variable L1: line;
variable CH : character;
variable rectype : std_logic_vector(3 downto 0);
variable recaddr : std_logic_vector(31 downto 0);
variable reclen : std_logic_vector(7 downto 0);
variable recdata : std_logic_vector(0 to 16*8-1);
variable idx, coloffs, len: integer;
begin
L1:= new string'("");
while not endfile(TCF) loop
readline(TCF,L1);
if (L1'length /= 0) then
while (not (L1'length=0)) and (L1(L1'left) = ' ') loop
std.textio.read(L1,CH);
end loop;
if L1'length > 0 then
read(L1, ch);
if (ch = 'S') or (ch = 's') then
hread(L1, rectype);
hread(L1, reclen);
len := to_integer(unsigned(reclen))-1;
recaddr := (others => '0');
case rectype is
when "0001" => hread(L1, recaddr(15 downto 0)); len := len - 2;
when "0010" => hread(L1, recaddr(23 downto 0)); len := len - 3;
when "0011" => hread(L1, recaddr); len := len - 4;
when others => next;
end case;
hread(L1, recdata(0 to len*8-1));
if width < 16 then
idx := to_integer(unsigned(recaddr(rowbits+colbits-1 downto 0)));
while len > 1 loop
memdata0(idx) := 16#10000# + to_integer(unsigned(recdata(0 to 7)));
idx := idx+1;
len := len-1;
recdata(0 to recdata'length-8-1) := recdata(8 to recdata'length-1);
end loop;
else
assert recaddr(0)='0'; -- Assume 16-bit alignment on SREC entry
idx := to_integer(unsigned(recaddr(rowbits+colbits+log2(width/16) downto 1)));
while len > 1 loop
memdata0(idx) := 16#50000# + to_integer(unsigned(recdata(0 to 15)));
idx := idx+1;
len := len-2;
recdata(0 to recdata'length-16-1) := recdata(16 to recdata'length-1);
end loop;
if len > 0 then
memdata0(idx) := 16#40000# + to_integer(unsigned(recdata(0 to 15)));
end if;
end if;
end if;
end if;
end if;
end loop;
end load_srec;
variable vmr: moderegs;
type bankstate is record
openrow: integer;
opentime: time;
closetime: time;
writetime: time;
readtime: time;
autopch: integer;
pchpush: boolean;
end record;
type bankstate_arr is array(natural range <>) of bankstate;
variable banks: bankstate_arr(7 downto 0) := (others => (-1, 0 ns, 0 ns, 0 ns, 0 ns, -1, false));
type int_arr is array(natural range <>) of integer;
type dataacc is record
r,w: boolean;
col: int_arr(0 to 1);
bank: integer;
first,wchop: boolean;
end record;
type dataacc_arr is array(natural range <>) of dataacc;
variable accpipe: dataacc_arr(0 to 25);
variable cmd: std_logic_vector(2 downto 0);
variable bank: integer;
variable colv: unsigned(a'high-2 downto 0);
variable alow: unsigned(2 downto 0);
variable col: integer;
variable prev_re, re: time;
variable blen, wblen: integer;
variable lastref: time := 0 ns;
variable i, al, cl, cwl, wrap: integer;
variable b: boolean;
variable mrscount: integer := 100;
variable mrstime: time;
variable loaded: boolean := false;
variable cold: coldata;
procedure checktime(got, exp: time; gt: boolean; req: string) is
begin
assert (got + deltat > exp and gt) or (got-deltat < exp and not gt)
report (req & " violation, got: " & tost(got/(1 ps)) & " ps, exp: " & tost(exp/(1 ps)) & "ps")
severity warning;
end checktime;
begin
if rising_edge(ck) and resetn='1' then
-- Update pipe regs
prev_re := re;
re := now;
accpipe(1 to accpipe'high) := accpipe(0 to accpipe'high-1);
accpipe(0).r:=false; accpipe(0).w:=false; accpipe(0).first:=false;
-- Parse MR fields
cmd := rasn & casn & wen;
if is_x(vmr.caslat) then cl:=0; else cl:=to_integer(unsigned(vmr.caslat(3 downto 1)))+4; end if;
if cl<5 or cl>11 then cl:=0; end if;
case vmr.al is
when "00" => al:=0;
when "01" => al:=cl-1;
when "10" => al:=cl-2;
when others => al:=-1;
end case;
if is_x(vmr.cwl) then cwl:=0; else cwl:=to_integer(unsigned(vmr.cwl))+5; end if;
if cwl>8 then cwl:=0; end if;
if is_x(vmr.wr) then wrap:=0; else wrap:=to_integer(unsigned(vmr.wr))+4; end if;
if wrap<5 or wrap>12 then wrap:=0; end if;
-- Checks for all-bank commands
mrscount := mrscount+1;
assert (mrscount >= tMRD_ck) or (cke='1' and (csn='1' or cmd="111"))
report "tMRD violation!" severity warning;
assert (mrscount > tMOD_ck and now > mrstime+tMOD_t-deltat) or
(cke='1' and (csn='1' or cmd="111" or cmd="000"))
report "tMOD violation!" severity warning;
if cke='1' and csn='0' and cmd/="111" then
checktime(now-lastref, tRFC(density), true, "tRFC");
end if;
if vmr.mpr='1' then
assert cke='0' or csn='1' or cmd="111" or cmd="101"
report "Command other than read in MPR mode!" severity warning;
for x in 7 downto 0 loop
assert banks(x).openrow<0
report "Row opened in MPR mode!" severity warning;
end loop;
end if;
-- Main command handler
if cke='1' and csn='0' then
case cmd is
when "111" => -- NOP
when "011" => -- RAS
assert initdone report "Opening row before init sequence done!" severity warning;
bank := to_integer(unsigned(ba));
assert banks(bank).openrow < 0
report "Row already open" severity warning;
checktime(now-banks(bank).closetime, tRP(speedbin), true, "tRP");
for x in 0 to 7 loop
checktime(now-banks(x).opentime, tRRD(re-prev_re, speedbin), true, "tRRD");
end loop;
banks(bank).openrow := to_integer(unsigned(a(rowbits-1 downto 0)));
banks(bank).opentime := now;
when "101" | "100" => -- Read/Write
bank := to_integer(unsigned(ba));
assert banks(bank).openrow >= 0 or vmr.mpr='1'
report "Row not open" severity error;
checktime(now-banks(bank).opentime+al*(re-prev_re), tRCD(speedbin), true, "tRCD");
for x in 0 to 3 loop
assert not accpipe(x).r and not accpipe(x).w;
end loop;
if cmd(0)='1' then accpipe(3).r:=true; else accpipe(3).w:=true; end if;
colv := unsigned(std_logic_vector'(a(a'high downto 13) & a(11) & a(9 downto 0)));
wblen := 8;
case vmr.blen is
when "00" => blen := 8;
when "01" => if a(12)='1' then blen:=8; else blen:=4; end if;
when "11" => blen := 4; wblen:=4;
when others => assert false report "Invalid burst length setting in MR!" severity error;
end case;
alow := unsigned(a(2 downto 0));
if cmd(0)='0' then
alow(1 downto 0) := "00";
if blen=8 then alow(2):='0'; end if;
end if;
for x in 0 to blen-1 loop
accpipe(3-x/2).bank := bank;
if cmd(0)='1' then accpipe(3-x/2).r:=true; else accpipe(3-x/2).w:=true; end if;
if vmr.rbt='0' then -- Sequential
colv(log2(blen)-1 downto 0) := alow(log2(blen)-1 downto 0) + x;
else -- Interleaved
colv(log2(blen)-1 downto 0) := alow(log2(blen)-1 downto 0) xor to_unsigned(x,log2(blen));
end if;
col := banks(bank).openrow * (2**colbits) + to_integer(colv(colbits-1 downto 0));
accpipe(3-x/2).col(x mod 2) := col;
accpipe(3-x/2).wchop := (blen<wblen);
end loop;
accpipe(3).first := true;
-- Auto precharge
if a(10)='1' then
if cmd(0)='1' then
banks(bank).autopch := al+tRTP_ck;
else
banks(bank).autopch := al+cwl+wblen/2+wrap;
end if;
banks(bank).pchpush := true;
end if;
when "110" => -- ZQInit
for x in 0 to 7 loop
checktime(now-banks(x).closetime, tRP(speedbin), true, "tRP");
end loop;
for x in 3+cl+al downto 0 loop
assert not accpipe(x).r severity warning;
end loop;
for x in 4+cwl+al downto 0 loop
assert not accpipe(x).w severity warning;
end loop;
-- Currently does not check TZQCoper/TZQCs
when "010" => -- Precharge
if a(10)='0' then bank := to_integer(unsigned(ba)); else bank:=0; end if;
for x in 6+cwl+al downto 0 loop
assert ( (not ((accpipe(x).r and x<=3+al) or accpipe(x).w)) or
(a(10)='0' and accpipe(x).bank/=bank) )
report "Precharging bank with access in progress" severity warning;
end loop;
for x in 0 to 7 loop
if a(10)='1' or ba=std_logic_vector(to_unsigned(x,3)) then
assert banks(x).autopch<0
report "Precharging bank that is auto-precharged!" severity note;
assert a(10)='1' or banks(x).openrow >= 0
report "Precharging single bank that is in idle state!" severity note;
banks(x).autopch := 0; -- Handled below case statement
banks(x).pchpush := false;
end if;
end loop;
when "001" => -- Auto refresh
for x in 0 to 7 loop
assert banks(x).openrow < 0
report "Bank in wrong state for auto refresh!" severity warning;
checktime(now-banks(x).closetime, tRP(speedbin), true, "tRP");
end loop;
lastref := now;
when "000" => -- MRS
for x in 0 to 7 loop
checktime(now-banks(x).closetime, tRP(speedbin), true, "tRP");
end loop;
bank := to_integer(unsigned(ba));
case bank is
when 0 =>
vmr.ppd := a(12);
vmr.wr := a(11 downto 9);
vmr.dllres := a(8);
vmr.tm := a(7);
vmr.caslat := a(6 downto 4) & a(2);
vmr.rbt := a(3);
vmr.blen := a(1 downto 0);
when 1 =>
vmr.qoff := a(12);
vmr.tdqsen := a(11);
vmr.level := a(7);
vmr.al := a(4 downto 3);
vmr.rtt_nom := a(9) & a(6) & a(2);
vmr.dic := a(5) & a(1);
vmr.dlldis := a(0);
when 2 =>
vmr.rtt_wr := a(10 downto 9);
vmr.srt := a(7);
vmr.asr := a(6);
vmr.cwl := a(5 downto 3);
vmr.pasr := a(2 downto 0);
when 3 =>
vmr.mpr := a(2);
vmr.mprloc := a(1 downto 0);
when others =>
assert false report ("MRS to invalid bank addr: " & std_logic'image(ba(1)) & std_logic'image(ba(0))) severity warning;
end case;
mrscount := 0;
mrstime := now;
when others =>
assert false report ("Invalid command: " & std_logic'image(rasn) & std_logic'image(casn) & std_logic'image(wen)) severity warning;
end case;
end if;
-- Manual or auto precharge handling
for x in 0 to 7 loop
if banks(x).autopch=0 then
if banks(x).pchpush and
((now-banks(x).readtime-deltat) < tRTP_t or
(now-banks(x).opentime-deltat) < tRAS(speedbin)) then
-- Auto delay auto-precharge to satisfy tRTP_t
-- NOTE: According to Micron's datasheets, their DDR3 memories
-- automatically hold off the auto precharge so that also tRAS is satisfied,
-- and the MIG controller seems to depend on this. It is not clear in the
-- JEDEC standard (rev F) whether this is guaranteed behavior for all DDR3
-- RAMs, but we emulate that behavior here.
banks(x).autopch := banks(x).autopch+1;
else
checktime(now-banks(x).writetime, tWR, true, "tWR");
checktime(now-banks(x).opentime, tRAS(speedbin), true, "tRAS");
checktime(now-banks(x).readtime, tRTP(re-prev_re), true, "tRTP");
banks(x).openrow := -1;
banks(x).closetime := now;
end if;
end if;
if banks(x).autopch >= 0 then
banks(x).autopch := banks(x).autopch - 1;
end if;
end loop;
-- Read/write management
if not loaded and lddelay < now and (ldguard=0 or doload='1') then
load_srec;
loaded := true;
end if;
if accpipe(2+cl+al).r then
assert cl>1 report "Incorrect CL setting!" severity warning;
read_en <= true;
-- print("Reading from col " & tost(accpipe(2+i).col(0)) & " and " & tost(accpipe(2+i).col(1)));
-- col0 <= accpipe(2+i).col(0); col1 <= accpipe(2+i).col(1);
if vmr.mpr='1' then
assert vmr.mprloc="00" report "Read from undefined MPR!" severity warning;
read_data <= (others => '0');
for x in width/8-1 downto 0 loop
read_data(x*8) <= '1';
end loop;
else
read_data <= memdata_get(accpipe(2+cl+al).bank, accpipe(2+cl+al).col(0)) &
memdata_get(accpipe(2+cl+al).bank, accpipe(2+cl+al).col(1));
end if;
else
read_en <= false;
end if;
if accpipe(3+al).r and accpipe(3+al).first then
banks(accpipe(3+al).bank).readtime := now;
end if;
write_en <= accpipe(2+cwl+al).w or accpipe(3+cwl+al).w;
if accpipe(4+cwl+al).w then
assert not is_x(write_mask) report "Write error!";
for x in 0 to 1 loop
cold := memdata_get(accpipe(4+cwl+al).bank, accpipe(4+cwl+al).col(x));
for b in width/8-1 downto 0 loop
if write_mask((1-x)*width/8+b)='0' then
cold(8*b+7 downto 8*b) :=
write_data( (1-x)*width+b*8+7 downto (1-x)*width+b*8);
end if;
end loop;
memdata_set(accpipe(4+cwl+al).bank, accpipe(4+cwl+al).col(x), cold);
end loop;
banks(accpipe(4+cwl+al).bank).writetime := now;
end if;
if accpipe(6+cwl+al).w and accpipe(6+cwl+al).wchop then
banks(accpipe(6+cwl+al).bank).writetime := now;
end if;
dqscal_en <= (vmr.level='1');
elsif resetn='0' then
for x in banks'range loop
banks(x).openrow := -1;
end loop;
end if;
mr <= vmr;
end process;
-----------------------------------------------------------------------------
-- DQS/DQ handling and data sampling process
-----------------------------------------------------------------------------
dqproc: process
variable rdata: std_logic_vector(2*width-1 downto 0);
variable hdata: std_logic_vector(width-1 downto 0);
variable hmask: std_logic_vector(width/8-1 downto 0);
variable prevdqs: std_logic_vector(width/8-1 downto 0);
begin
dq <= (others => 'Z');
dqs <= (others => 'Z');
dqsn <= (others => 'Z');
wait until read_en or write_en or dqscal_en;
assert not (read_en and write_en);
if dqscal_en then
while dqscal_en loop
prevdqs := dqs;
wait on dqs,dqscal_en;
for x in dqs'range loop
if dqs(x)='1' and prevdqs(x)='0' then
dq(8*x+7 downto 8*x) <= "0000000" & ck;
end if;
end loop;
end loop;
elsif read_en then
dqs <= (others => '0');
dqsn <= (others => '1');
wait until falling_edge(ck);
while read_en loop
rdata := read_data;
wait until rising_edge(ck);
dqs <= (others => '1');
dqsn <= (others => '0');
dq <= rdata(2*width-1 downto width);
wait until falling_edge(ck);
dqs <= (others => '0');
dqsn <= (others => '1');
dq <= rdata(width-1 downto 0);
end loop;
wait until rising_edge(ck);
else
wait until falling_edge(ck);
while write_en loop
prevdqs := to_X01(dqs);
wait until to_X01(dqs) /= prevdqs or not write_en or rising_edge(ck);
if rising_edge(ck) then
write_data <= (others => 'X');
write_mask <= (others => 'X');
end if;
for x in dqs'range loop
if prevdqs(x)='0' and to_X01(dqs(x))='1' then
hdata(8*x+7 downto 8*x) := dq(8*x+7 downto 8*x);
hmask(x) := dm(x);
elsif prevdqs(x)='1' and to_X01(dqs(x))='0' then
write_data(width+8*x+7 downto width+8*x) <= hdata(8*x+7 downto 8*x);
write_data(8*x+7 downto 8*x) <= dq(8*x+7 downto 8*x);
write_mask(width/8+x) <= hmask(x);
write_mask(x) <= dm(x);
end if;
end loop;
end loop;
end if;
end process;
end;
-- pragma translate_on
| gpl-2.0 | edeb4a5f8cd4bf12341711483e93c296 | 0.533716 | 3.594541 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-xilinx-xc3sd-1800/leon3mp.vhd | 1 | 24,900 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2006 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ddrpkg.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.net.all;
use gaisler.jtag.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
reset : in std_ulogic;
reset_o1 : out std_ulogic;
reset_o2 : out std_ulogic;
clk_in : in std_ulogic;
clk_vga : in std_ulogic;
errorn : out std_ulogic;
-- PROM interface
address : out std_logic_vector(23 downto 0);
data : inout std_logic_vector(7 downto 0);
romsn : out std_ulogic;
oen : out std_ulogic;
writen : out std_ulogic;
-- pragma translate_off
iosn : out std_ulogic;
testdata : inout std_logic_vector(23 downto 0);
-- pragma translate_on
-- DDR2 memory
ddr_clk : out std_logic_vector(1 downto 0);
ddr_clkb : out std_logic_vector(1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic;
ddr_csb : out std_logic;
ddr_we : out std_ulogic; -- write enable
ddr_ras : out std_ulogic; -- ras
ddr_cas : out std_ulogic; -- cas
ddr_dm : out std_logic_vector(3 downto 0); -- dm
ddr_dqs : inout std_logic_vector(3 downto 0); -- dqs
ddr_dqsn : inout std_logic_vector(3 downto 0); -- dqsn
ddr_ad : out std_logic_vector(12 downto 0); -- address
ddr_ba : out std_logic_vector(1 downto 0); -- bank address
ddr_dq : inout std_logic_vector(31 downto 0); -- data
ddr_odt : out std_logic;
-- Debug support unit
dsubre : in std_ulogic; -- Debug Unit break (connect to button)
-- AHB Uart
dsurx : in std_ulogic;
dsutx : out std_ulogic;
-- Ethernet signals
etx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
emdc : out std_ulogic;
emdio : inout std_logic;
-- SVGA
vid_hsync : out std_logic;
vid_vsync : out std_logic;
vid_r : out std_logic_vector(3 downto 0);
vid_g : out std_logic_vector(3 downto 0);
vid_b : out std_logic_vector(3 downto 0);
-- SPI flash
spi_sel_n : inout std_ulogic;
spi_clk : out std_ulogic;
spi_mosi : out std_ulogic;
-- Output signals to LEDs
led : out std_logic_vector(2 downto 0)
);
end;
architecture rtl of leon3mp is
signal vcc : std_logic;
signal gnd : std_logic;
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal gpti : gptimer_in_type;
signal vgao : apbvga_out_type;
signal spii : spi_in_type;
signal spio : spi_out_type;
signal slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
signal spmi : spimctrl_in_type;
signal spmo : spimctrl_out_type;
signal lclk : std_ulogic;
signal lclk_vga : std_ulogic;
signal clkm, rstn, clkml : std_ulogic;
signal tck, tms, tdi, tdo : std_ulogic;
signal rstraw : std_logic;
signal lock : std_logic;
-- RS232 APB Uart
signal rxd1 : std_logic;
signal txd1 : std_logic;
-- Used for connecting input/output signals to the DDR2 controller
signal core_ddr_clk : std_logic_vector(2 downto 0);
signal core_ddr_clkb : std_logic_vector(2 downto 0);
signal core_ddr_cke : std_logic_vector(1 downto 0);
signal core_ddr_csb : std_logic_vector(1 downto 0);
signal core_ddr_ad : std_logic_vector(13 downto 0);
signal core_ddr_odt : std_logic_vector(1 downto 0);
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of lock : signal is true;
attribute syn_keep of clkml : signal is true;
attribute syn_keep of clkm : signal is true;
attribute syn_preserve of clkml : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute syn_keep of lclk_vga : signal is true;
attribute syn_preserve of lclk_vga : signal is true;
attribute keep of lock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
constant BOARD_FREQ : integer := 125000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1';
gnd <= '0';
cgi.pllctrl <= "00";
cgi.pllrst <= rstraw;
-- Glitch free reset that can be used for the Eth Phy and flash memory
reset_o1 <= rstn;
reset_o2 <= rstn;
rst0 : rstgen generic map (acthigh => 1)
port map (reset, clkm, lock, rstn, rstraw);
clk_pad : clkpad generic map (tech => padtech) port map (clk_in, lclk);
-- clock generator
clkgen0 : clkgen
generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd, clkm, open, open, open, open, cgi, cgo, open, open, open);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1,
nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_SVGA_ENABLE,
nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
-- LEON3 processor
leon3gen : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR,
CFG_NCPU-1)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
error_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
-- LEON3 Debug Support Unit
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsui.enable <= '1';
led(2) <= dsuo.active;
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
-- Debug UART
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart
generic map (hindex => CFG_NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
led(0) <= not dui.rxd;
led(1) <= not duo.txd;
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd);
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 5, pindex => 0, paddr => 0,
ram8 => CFG_MCTRL_RAM8BIT, ram16 => CFG_MCTRL_RAM16BIT, rammask => 0)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(5), apbi, apbo(0), wpo, open);
end generate;
memi.brdyn <= '1';
memi.bexcn <= '1';
memi.writen <= '1';
memi.wrn <= "1111";
memi.bwidth <= "00";
mg0 : if (CFG_MCTRL_LEON2 = 0) generate
apbo(0) <= apb_none;
ahbso(5) <= ahbs_none;
roms_pad : outpad generic map (tech => padtech)
port map (romsn, vcc);
memo.bdrive(0) <= '1';
end generate;
mgpads : if (CFG_MCTRL_LEON2 /= 0) generate
addr_pad : outpadv generic map (tech => padtech, width => 24)
port map (address, memo.address(23 downto 0));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
-- pragma translate_off
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
tbdr : iopadv generic map (tech => padtech, width => 24)
port map (testdata(23 downto 0), memo.data(23 downto 0),
memo.bdrive(1), memi.data(23 downto 0));
-- pragma translate_on
end generate;
bdr : iopadv generic map (tech => padtech, width => 8)
port map (data(7 downto 0), memo.data(31 downto 24),
memo.bdrive(0), memi.data(31 downto 24));
----------------------------------------------------------------------
--- DDR2 memory controller ------------------------------------------
----------------------------------------------------------------------
ddr2sp0 : if (CFG_DDR2SP /= 0) generate
ddrc0 : ddr2spa generic map ( fabtech => spartan3, memtech => memtech,
hindex => 4, haddr => 16#400#, hmask => 16#F00#, ioaddr => 1,
pwron => CFG_DDR2SP_INIT, MHz => BOARD_FREQ/1000, clkmul => 2, clkdiv => 2,
TRFC => CFG_DDR2SP_TRFC,
-- readdly must be 0 for simulation, but 1 for hardware
--pragma translate_off
readdly => 0,
--pragma translate_on
ahbfreq => CPU_FREQ/1000, col => CFG_DDR2SP_COL, Mbyte => CFG_DDR2SP_SIZE,
ddrbits => CFG_DDR2SP_DATAWIDTH, odten => 0)
port map ( cgo.clklock, rstn, lclk, clkm, vcc, lock, clkml, clkml, ahbsi, ahbso(4),
core_ddr_clk, core_ddr_clkb, ddr_clk_fb_out, ddr_clk_fb, core_ddr_cke,
core_ddr_csb, ddr_we, ddr_ras, ddr_cas, ddr_dm, ddr_dqs, ddr_dqsn,
core_ddr_ad, ddr_ba, ddr_dq, core_ddr_odt);
ddr_clk(1 downto 0) <= core_ddr_clk(1 downto 0);
ddr_clkb(1 downto 0) <= core_ddr_clkb(1 downto 0);
ddr_cke <= core_ddr_cke(0);
ddr_csb <= core_ddr_csb(0);
ddr_ad <= core_ddr_ad(12 downto 0);
ddr_odt <= core_ddr_odt(0);
end generate;
noddr : if (CFG_DDR2SP = 0) generate lock <= '1'; end generate;
----------------------------------------------------------------------
--- SPI Memory Controller--------------------------------------------
----------------------------------------------------------------------
spimc: if CFG_SPICTRL_ENABLE = 0 and CFG_SPIMCTRL = 1 generate
spimctrl0 : spimctrl -- SPI Memory Controller
generic map (hindex => 7, hirq => 11, faddr => 16#e00#, fmask => 16#ff8#,
ioaddr => 16#002#, iomask => 16#fff#,
spliten => CFG_SPLIT, oepol => 0,
sdcard => CFG_SPIMCTRL_SDCARD,
readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => CFG_SPIMCTRL_DUALOUTPUT,
scaler => CFG_SPIMCTRL_SCALER,
altscaler => CFG_SPIMCTRL_ASCALER,
pwrupcnt => CFG_SPIMCTRL_PWRUPCNT)
port map (rstn, clkm, ahbsi, ahbso(7), spmi, spmo);
-- MISO is shared with Flash data 0
spmi.miso <= memi.data(24);
mosi_pad : outpad generic map (tech => padtech)
port map (spi_mosi, spmo.mosi);
sck_pad : outpad generic map (tech => padtech)
port map (spi_clk, spmo.sck);
slvsel0_pad : odpad generic map (tech => padtech)
port map (spi_sel_n, spmo.csn);
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
-- APB Bridge
apb0 : apbctrl
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
-- Interrupt controller
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
-- Time Unit
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW,
ntimers => CFG_GPT_NTIM, nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop;
gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
-- GPIO Unit
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate
grgpio0: grgpio
generic map(pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 12)
port map(rstn, clkm, apbi, apbo(11), gpioi, gpioo);
end generate;
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1;
u1i.ctsn <= '0';
u1i.extclk <= '0';
txd1 <= u1o.txd;
serrx_pad : inpad generic map (tech => padtech) port map (dsurx, rxd1);
sertx_pad : outpad generic map (tech => padtech) port map (dsutx, txd1);
led(0) <= not rxd1;
led(1) <= not txd1;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
-- There is no PS/2 port
apbo(5) <= apb_none;
spic: if CFG_SPICTRL_ENABLE = 1 generate -- SPI controller
spi1 : spictrl
generic map (pindex => 7, paddr => 7, pmask => 16#fff#, pirq => 11,
fdepth => CFG_SPICTRL_FIFO, slvselen => CFG_SPICTRL_SLVREG,
slvselsz => CFG_SPICTRL_SLVS, odmode => 0, netlist => 0,
syncram => CFG_SPICTRL_SYNCRAM, ft => CFG_SPICTRL_FT)
port map (rstn, clkm, apbi, apbo(7), spii, spio, slvsel);
spii.spisel <= '1'; -- Master only
-- MISO is shared with Flash data 0
spii.miso <= memi.data(24);
mosi_pad : outpad generic map (tech => padtech)
port map (spi_mosi, spio.mosi);
sck_pad : outpad generic map (tech => padtech)
port map (spi_clk, spio.sck);
slvsel_pad : odpad generic map (tech => padtech)
port map (spi_sel_n, slvsel(0));
end generate spic;
nospi: if CFG_SPICTRL_ENABLE = 0 and CFG_SPIMCTRL = 0 generate
apbo(7) <= apb_none;
mosi_pad : outpad generic map (tech => padtech)
port map (spi_mosi, gnd);
sck_pad : outpad generic map (tech => padtech)
port map (spi_clk, gnd);
slvsel_pad : odpad generic map (tech => padtech)
port map (spi_sel_n, vcc);
end generate;
-----------------------------------------------------------------------
--- SVGA -------------------------------------------------------------
-----------------------------------------------------------------------
svga : if CFG_SVGA_ENABLE /= 0 generate
clk_vga_pad : clkpad generic map (tech => padtech) port map (clk_vga, lclk_vga);
svga0 : svgactrl
generic map(memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
clk0 => 40000,clk1 => 0, clk2 => 0, burstlen => 5)
port map(rstn, clkm, lclk_vga, apbi, apbo(6), vgao, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), open);
vert_sync_pad : outpad generic map (tech => padtech)
port map (vid_vsync, vgao.vsync);
horiz_sync_pad : outpad generic map (tech => padtech)
port map (vid_hsync, vgao.hsync);
video_out_r_pad : outpadv generic map (tech => padtech, width => 4)
port map (vid_r, vgao.video_out_r(7 downto 4));
video_out_g_pad : outpadv generic map (tech => padtech, width => 4)
port map (vid_g, vgao.video_out_g(7 downto 4));
video_out_b_pad : outpadv generic map (tech => padtech, width => 4)
port map (vid_b, vgao.video_out_b(7 downto 4));
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm
generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
pindex => 15, paddr => 15, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 1,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G)
port map(rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
apbi => apbi, apbo => apbo(15), ethi => ethi, etho => etho);
end generate;
ethpads : if (CFG_GRETH = 1) generate -- eth pads
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (etx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (erxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (etxd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map (etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram
generic map (hindex => 3, haddr => CFG_AHBRADDR, tech => CFG_MEMTECH,
kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_SVGA_ENABLE+1) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Demonstration design for Xilinx Spartan3A DSP 1800A board",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end rtl;
| gpl-2.0 | 1804f4ad82c4fc67a932dafa02451fee | 0.532771 | 3.819018 | false | false | false | false |
khaledhassan/vhdl-examples | adder_numeric_std/adder.vhd | 1 | 2,049 | -- Copyright (c) 2012 Brian Nezvadovitz <http://nezzen.net>
-- This software is distributed under the terms of the MIT License shown below.
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to
-- deal in the Software without restriction, including without limitation the
-- rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
-- sell copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
-- IN THE SOFTWARE.
-- Implements an adder of variable width with carry signals.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adder is
generic (
WIDTH : positive := 8
);
port (
a : in std_logic_vector(WIDTH-1 downto 0);
b : in std_logic_vector(WIDTH-1 downto 0);
c_in : in std_logic;
sum : out std_logic_vector(WIDTH-1 downto 0);
c_out : out std_logic
);
end;
architecture BHV of adder is
signal full_sum : std_logic_vector(WIDTH downto 0);
signal c_in_vec : std_logic_vector(0 downto 0);
begin
c_in_vec(0) <= c_in;
full_sum <= std_logic_vector( resize(unsigned(a), WIDTH+1) + resize(unsigned(b), WIDTH+1) + resize(unsigned(c_in_vec), WIDTH+1) );
sum <= full_sum(WIDTH-1 downto 0);
c_out <= full_sum(WIDTH);
end BHV;
| mit | 16f51a857daac1236e641c4ebe7736e5 | 0.70327 | 3.794444 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.cache/ip/2017.2.1/c0a9116ee5914c6d/zqynq_lab_1_design_processing_system7_0_0_sim_netlist.vhdl | 1 | 197,453 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2.1 (win64) Build 1957588 Wed Aug 9 16:32:24 MDT 2017
-- Date : Fri Sep 22 17:17:54 2017
-- Host : EffulgentTome running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_processing_system7_0_0_sim_netlist.vhdl
-- Design : zqynq_lab_1_design_processing_system7_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 is
port (
CAN0_PHY_TX : out STD_LOGIC;
CAN0_PHY_RX : in STD_LOGIC;
CAN1_PHY_TX : out STD_LOGIC;
CAN1_PHY_RX : in STD_LOGIC;
ENET0_GMII_TX_EN : out STD_LOGIC;
ENET0_GMII_TX_ER : out STD_LOGIC;
ENET0_MDIO_MDC : out STD_LOGIC;
ENET0_MDIO_O : out STD_LOGIC;
ENET0_MDIO_T : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET0_SOF_RX : out STD_LOGIC;
ENET0_SOF_TX : out STD_LOGIC;
ENET0_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ENET0_GMII_COL : in STD_LOGIC;
ENET0_GMII_CRS : in STD_LOGIC;
ENET0_GMII_RX_CLK : in STD_LOGIC;
ENET0_GMII_RX_DV : in STD_LOGIC;
ENET0_GMII_RX_ER : in STD_LOGIC;
ENET0_GMII_TX_CLK : in STD_LOGIC;
ENET0_MDIO_I : in STD_LOGIC;
ENET0_EXT_INTIN : in STD_LOGIC;
ENET0_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
ENET1_GMII_TX_EN : out STD_LOGIC;
ENET1_GMII_TX_ER : out STD_LOGIC;
ENET1_MDIO_MDC : out STD_LOGIC;
ENET1_MDIO_O : out STD_LOGIC;
ENET1_MDIO_T : out STD_LOGIC;
ENET1_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET1_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET1_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET1_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET1_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET1_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET1_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET1_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET1_SOF_RX : out STD_LOGIC;
ENET1_SOF_TX : out STD_LOGIC;
ENET1_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ENET1_GMII_COL : in STD_LOGIC;
ENET1_GMII_CRS : in STD_LOGIC;
ENET1_GMII_RX_CLK : in STD_LOGIC;
ENET1_GMII_RX_DV : in STD_LOGIC;
ENET1_GMII_RX_ER : in STD_LOGIC;
ENET1_GMII_TX_CLK : in STD_LOGIC;
ENET1_MDIO_I : in STD_LOGIC;
ENET1_EXT_INTIN : in STD_LOGIC;
ENET1_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
GPIO_I : in STD_LOGIC_VECTOR ( 63 downto 0 );
GPIO_O : out STD_LOGIC_VECTOR ( 63 downto 0 );
GPIO_T : out STD_LOGIC_VECTOR ( 63 downto 0 );
I2C0_SDA_I : in STD_LOGIC;
I2C0_SDA_O : out STD_LOGIC;
I2C0_SDA_T : out STD_LOGIC;
I2C0_SCL_I : in STD_LOGIC;
I2C0_SCL_O : out STD_LOGIC;
I2C0_SCL_T : out STD_LOGIC;
I2C1_SDA_I : in STD_LOGIC;
I2C1_SDA_O : out STD_LOGIC;
I2C1_SDA_T : out STD_LOGIC;
I2C1_SCL_I : in STD_LOGIC;
I2C1_SCL_O : out STD_LOGIC;
I2C1_SCL_T : out STD_LOGIC;
PJTAG_TCK : in STD_LOGIC;
PJTAG_TMS : in STD_LOGIC;
PJTAG_TDI : in STD_LOGIC;
PJTAG_TDO : out STD_LOGIC;
SDIO0_CLK : out STD_LOGIC;
SDIO0_CLK_FB : in STD_LOGIC;
SDIO0_CMD_O : out STD_LOGIC;
SDIO0_CMD_I : in STD_LOGIC;
SDIO0_CMD_T : out STD_LOGIC;
SDIO0_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_LED : out STD_LOGIC;
SDIO0_CDN : in STD_LOGIC;
SDIO0_WP : in STD_LOGIC;
SDIO0_BUSPOW : out STD_LOGIC;
SDIO0_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 );
SDIO1_CLK : out STD_LOGIC;
SDIO1_CLK_FB : in STD_LOGIC;
SDIO1_CMD_O : out STD_LOGIC;
SDIO1_CMD_I : in STD_LOGIC;
SDIO1_CMD_T : out STD_LOGIC;
SDIO1_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_LED : out STD_LOGIC;
SDIO1_CDN : in STD_LOGIC;
SDIO1_WP : in STD_LOGIC;
SDIO1_BUSPOW : out STD_LOGIC;
SDIO1_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 );
SPI0_SCLK_I : in STD_LOGIC;
SPI0_SCLK_O : out STD_LOGIC;
SPI0_SCLK_T : out STD_LOGIC;
SPI0_MOSI_I : in STD_LOGIC;
SPI0_MOSI_O : out STD_LOGIC;
SPI0_MOSI_T : out STD_LOGIC;
SPI0_MISO_I : in STD_LOGIC;
SPI0_MISO_O : out STD_LOGIC;
SPI0_MISO_T : out STD_LOGIC;
SPI0_SS_I : in STD_LOGIC;
SPI0_SS_O : out STD_LOGIC;
SPI0_SS1_O : out STD_LOGIC;
SPI0_SS2_O : out STD_LOGIC;
SPI0_SS_T : out STD_LOGIC;
SPI1_SCLK_I : in STD_LOGIC;
SPI1_SCLK_O : out STD_LOGIC;
SPI1_SCLK_T : out STD_LOGIC;
SPI1_MOSI_I : in STD_LOGIC;
SPI1_MOSI_O : out STD_LOGIC;
SPI1_MOSI_T : out STD_LOGIC;
SPI1_MISO_I : in STD_LOGIC;
SPI1_MISO_O : out STD_LOGIC;
SPI1_MISO_T : out STD_LOGIC;
SPI1_SS_I : in STD_LOGIC;
SPI1_SS_O : out STD_LOGIC;
SPI1_SS1_O : out STD_LOGIC;
SPI1_SS2_O : out STD_LOGIC;
SPI1_SS_T : out STD_LOGIC;
UART0_DTRN : out STD_LOGIC;
UART0_RTSN : out STD_LOGIC;
UART0_TX : out STD_LOGIC;
UART0_CTSN : in STD_LOGIC;
UART0_DCDN : in STD_LOGIC;
UART0_DSRN : in STD_LOGIC;
UART0_RIN : in STD_LOGIC;
UART0_RX : in STD_LOGIC;
UART1_DTRN : out STD_LOGIC;
UART1_RTSN : out STD_LOGIC;
UART1_TX : out STD_LOGIC;
UART1_CTSN : in STD_LOGIC;
UART1_DCDN : in STD_LOGIC;
UART1_DSRN : in STD_LOGIC;
UART1_RIN : in STD_LOGIC;
UART1_RX : in STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
TTC0_CLK0_IN : in STD_LOGIC;
TTC0_CLK1_IN : in STD_LOGIC;
TTC0_CLK2_IN : in STD_LOGIC;
TTC1_WAVE0_OUT : out STD_LOGIC;
TTC1_WAVE1_OUT : out STD_LOGIC;
TTC1_WAVE2_OUT : out STD_LOGIC;
TTC1_CLK0_IN : in STD_LOGIC;
TTC1_CLK1_IN : in STD_LOGIC;
TTC1_CLK2_IN : in STD_LOGIC;
WDT_CLK_IN : in STD_LOGIC;
WDT_RST_OUT : out STD_LOGIC;
TRACE_CLK : in STD_LOGIC;
TRACE_CTL : out STD_LOGIC;
TRACE_DATA : out STD_LOGIC_VECTOR ( 1 downto 0 );
TRACE_CLK_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
USB1_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB1_VBUS_PWRSELECT : out STD_LOGIC;
USB1_VBUS_PWRFAULT : in STD_LOGIC;
SRAM_INTIN : in STD_LOGIC;
M_AXI_GP0_ARESETN : out STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARESETN : out STD_LOGIC;
M_AXI_GP1_ARVALID : out STD_LOGIC;
M_AXI_GP1_AWVALID : out STD_LOGIC;
M_AXI_GP1_BREADY : out STD_LOGIC;
M_AXI_GP1_RREADY : out STD_LOGIC;
M_AXI_GP1_WLAST : out STD_LOGIC;
M_AXI_GP1_WVALID : out STD_LOGIC;
M_AXI_GP1_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ACLK : in STD_LOGIC;
M_AXI_GP1_ARREADY : in STD_LOGIC;
M_AXI_GP1_AWREADY : in STD_LOGIC;
M_AXI_GP1_BVALID : in STD_LOGIC;
M_AXI_GP1_RLAST : in STD_LOGIC;
M_AXI_GP1_RVALID : in STD_LOGIC;
M_AXI_GP1_WREADY : in STD_LOGIC;
M_AXI_GP1_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_ARESETN : out STD_LOGIC;
S_AXI_GP0_ARREADY : out STD_LOGIC;
S_AXI_GP0_AWREADY : out STD_LOGIC;
S_AXI_GP0_BVALID : out STD_LOGIC;
S_AXI_GP0_RLAST : out STD_LOGIC;
S_AXI_GP0_RVALID : out STD_LOGIC;
S_AXI_GP0_WREADY : out STD_LOGIC;
S_AXI_GP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_ACLK : in STD_LOGIC;
S_AXI_GP0_ARVALID : in STD_LOGIC;
S_AXI_GP0_AWVALID : in STD_LOGIC;
S_AXI_GP0_BREADY : in STD_LOGIC;
S_AXI_GP0_RREADY : in STD_LOGIC;
S_AXI_GP0_WLAST : in STD_LOGIC;
S_AXI_GP0_WVALID : in STD_LOGIC;
S_AXI_GP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_ARESETN : out STD_LOGIC;
S_AXI_GP1_ARREADY : out STD_LOGIC;
S_AXI_GP1_AWREADY : out STD_LOGIC;
S_AXI_GP1_BVALID : out STD_LOGIC;
S_AXI_GP1_RLAST : out STD_LOGIC;
S_AXI_GP1_RVALID : out STD_LOGIC;
S_AXI_GP1_WREADY : out STD_LOGIC;
S_AXI_GP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_ACLK : in STD_LOGIC;
S_AXI_GP1_ARVALID : in STD_LOGIC;
S_AXI_GP1_AWVALID : in STD_LOGIC;
S_AXI_GP1_BREADY : in STD_LOGIC;
S_AXI_GP1_RREADY : in STD_LOGIC;
S_AXI_GP1_WLAST : in STD_LOGIC;
S_AXI_GP1_WVALID : in STD_LOGIC;
S_AXI_GP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_ACP_ARESETN : out STD_LOGIC;
S_AXI_ACP_ARREADY : out STD_LOGIC;
S_AXI_ACP_AWREADY : out STD_LOGIC;
S_AXI_ACP_BVALID : out STD_LOGIC;
S_AXI_ACP_RLAST : out STD_LOGIC;
S_AXI_ACP_RVALID : out STD_LOGIC;
S_AXI_ACP_WREADY : out STD_LOGIC;
S_AXI_ACP_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_BID : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_RID : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_ACP_ACLK : in STD_LOGIC;
S_AXI_ACP_ARVALID : in STD_LOGIC;
S_AXI_ACP_AWVALID : in STD_LOGIC;
S_AXI_ACP_BREADY : in STD_LOGIC;
S_AXI_ACP_RREADY : in STD_LOGIC;
S_AXI_ACP_WLAST : in STD_LOGIC;
S_AXI_ACP_WVALID : in STD_LOGIC;
S_AXI_ACP_ARID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_WID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACP_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACP_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARUSER : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_ACP_AWUSER : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_ACP_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_ACP_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_ARESETN : out STD_LOGIC;
S_AXI_HP0_ARREADY : out STD_LOGIC;
S_AXI_HP0_AWREADY : out STD_LOGIC;
S_AXI_HP0_BVALID : out STD_LOGIC;
S_AXI_HP0_RLAST : out STD_LOGIC;
S_AXI_HP0_RVALID : out STD_LOGIC;
S_AXI_HP0_WREADY : out STD_LOGIC;
S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_ACLK : in STD_LOGIC;
S_AXI_HP0_ARVALID : in STD_LOGIC;
S_AXI_HP0_AWVALID : in STD_LOGIC;
S_AXI_HP0_BREADY : in STD_LOGIC;
S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_RREADY : in STD_LOGIC;
S_AXI_HP0_WLAST : in STD_LOGIC;
S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_WVALID : in STD_LOGIC;
S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_ARESETN : out STD_LOGIC;
S_AXI_HP1_ARREADY : out STD_LOGIC;
S_AXI_HP1_AWREADY : out STD_LOGIC;
S_AXI_HP1_BVALID : out STD_LOGIC;
S_AXI_HP1_RLAST : out STD_LOGIC;
S_AXI_HP1_RVALID : out STD_LOGIC;
S_AXI_HP1_WREADY : out STD_LOGIC;
S_AXI_HP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP1_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_ACLK : in STD_LOGIC;
S_AXI_HP1_ARVALID : in STD_LOGIC;
S_AXI_HP1_AWVALID : in STD_LOGIC;
S_AXI_HP1_BREADY : in STD_LOGIC;
S_AXI_HP1_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP1_RREADY : in STD_LOGIC;
S_AXI_HP1_WLAST : in STD_LOGIC;
S_AXI_HP1_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP1_WVALID : in STD_LOGIC;
S_AXI_HP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP1_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_ARESETN : out STD_LOGIC;
S_AXI_HP2_ARREADY : out STD_LOGIC;
S_AXI_HP2_AWREADY : out STD_LOGIC;
S_AXI_HP2_BVALID : out STD_LOGIC;
S_AXI_HP2_RLAST : out STD_LOGIC;
S_AXI_HP2_RVALID : out STD_LOGIC;
S_AXI_HP2_WREADY : out STD_LOGIC;
S_AXI_HP2_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP2_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_ACLK : in STD_LOGIC;
S_AXI_HP2_ARVALID : in STD_LOGIC;
S_AXI_HP2_AWVALID : in STD_LOGIC;
S_AXI_HP2_BREADY : in STD_LOGIC;
S_AXI_HP2_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP2_RREADY : in STD_LOGIC;
S_AXI_HP2_WLAST : in STD_LOGIC;
S_AXI_HP2_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP2_WVALID : in STD_LOGIC;
S_AXI_HP2_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP2_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP2_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP2_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_ARESETN : out STD_LOGIC;
S_AXI_HP3_ARREADY : out STD_LOGIC;
S_AXI_HP3_AWREADY : out STD_LOGIC;
S_AXI_HP3_BVALID : out STD_LOGIC;
S_AXI_HP3_RLAST : out STD_LOGIC;
S_AXI_HP3_RVALID : out STD_LOGIC;
S_AXI_HP3_WREADY : out STD_LOGIC;
S_AXI_HP3_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP3_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_ACLK : in STD_LOGIC;
S_AXI_HP3_ARVALID : in STD_LOGIC;
S_AXI_HP3_AWVALID : in STD_LOGIC;
S_AXI_HP3_BREADY : in STD_LOGIC;
S_AXI_HP3_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP3_RREADY : in STD_LOGIC;
S_AXI_HP3_WLAST : in STD_LOGIC;
S_AXI_HP3_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP3_WVALID : in STD_LOGIC;
S_AXI_HP3_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP3_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP3_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP3_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
IRQ_P2F_DMAC_ABORT : out STD_LOGIC;
IRQ_P2F_DMAC0 : out STD_LOGIC;
IRQ_P2F_DMAC1 : out STD_LOGIC;
IRQ_P2F_DMAC2 : out STD_LOGIC;
IRQ_P2F_DMAC3 : out STD_LOGIC;
IRQ_P2F_DMAC4 : out STD_LOGIC;
IRQ_P2F_DMAC5 : out STD_LOGIC;
IRQ_P2F_DMAC6 : out STD_LOGIC;
IRQ_P2F_DMAC7 : out STD_LOGIC;
IRQ_P2F_SMC : out STD_LOGIC;
IRQ_P2F_QSPI : out STD_LOGIC;
IRQ_P2F_CTI : out STD_LOGIC;
IRQ_P2F_GPIO : out STD_LOGIC;
IRQ_P2F_USB0 : out STD_LOGIC;
IRQ_P2F_ENET0 : out STD_LOGIC;
IRQ_P2F_ENET_WAKE0 : out STD_LOGIC;
IRQ_P2F_SDIO0 : out STD_LOGIC;
IRQ_P2F_I2C0 : out STD_LOGIC;
IRQ_P2F_SPI0 : out STD_LOGIC;
IRQ_P2F_UART0 : out STD_LOGIC;
IRQ_P2F_CAN0 : out STD_LOGIC;
IRQ_P2F_USB1 : out STD_LOGIC;
IRQ_P2F_ENET1 : out STD_LOGIC;
IRQ_P2F_ENET_WAKE1 : out STD_LOGIC;
IRQ_P2F_SDIO1 : out STD_LOGIC;
IRQ_P2F_I2C1 : out STD_LOGIC;
IRQ_P2F_SPI1 : out STD_LOGIC;
IRQ_P2F_UART1 : out STD_LOGIC;
IRQ_P2F_CAN1 : out STD_LOGIC;
IRQ_F2P : in STD_LOGIC_VECTOR ( 1 downto 0 );
Core0_nFIQ : in STD_LOGIC;
Core0_nIRQ : in STD_LOGIC;
Core1_nFIQ : in STD_LOGIC;
Core1_nIRQ : in STD_LOGIC;
DMA0_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA0_DAVALID : out STD_LOGIC;
DMA0_DRREADY : out STD_LOGIC;
DMA0_RSTN : out STD_LOGIC;
DMA1_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DAVALID : out STD_LOGIC;
DMA1_DRREADY : out STD_LOGIC;
DMA1_RSTN : out STD_LOGIC;
DMA2_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DAVALID : out STD_LOGIC;
DMA2_DRREADY : out STD_LOGIC;
DMA2_RSTN : out STD_LOGIC;
DMA3_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA3_DAVALID : out STD_LOGIC;
DMA3_DRREADY : out STD_LOGIC;
DMA3_RSTN : out STD_LOGIC;
DMA0_ACLK : in STD_LOGIC;
DMA0_DAREADY : in STD_LOGIC;
DMA0_DRLAST : in STD_LOGIC;
DMA0_DRVALID : in STD_LOGIC;
DMA1_ACLK : in STD_LOGIC;
DMA1_DAREADY : in STD_LOGIC;
DMA1_DRLAST : in STD_LOGIC;
DMA1_DRVALID : in STD_LOGIC;
DMA2_ACLK : in STD_LOGIC;
DMA2_DAREADY : in STD_LOGIC;
DMA2_DRLAST : in STD_LOGIC;
DMA2_DRVALID : in STD_LOGIC;
DMA3_ACLK : in STD_LOGIC;
DMA3_DAREADY : in STD_LOGIC;
DMA3_DRLAST : in STD_LOGIC;
DMA3_DRVALID : in STD_LOGIC;
DMA0_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA3_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
FCLK_CLK3 : out STD_LOGIC;
FCLK_CLK2 : out STD_LOGIC;
FCLK_CLK1 : out STD_LOGIC;
FCLK_CLK0 : out STD_LOGIC;
FCLK_CLKTRIG3_N : in STD_LOGIC;
FCLK_CLKTRIG2_N : in STD_LOGIC;
FCLK_CLKTRIG1_N : in STD_LOGIC;
FCLK_CLKTRIG0_N : in STD_LOGIC;
FCLK_RESET3_N : out STD_LOGIC;
FCLK_RESET2_N : out STD_LOGIC;
FCLK_RESET1_N : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
FTMD_TRACEIN_DATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FTMD_TRACEIN_VALID : in STD_LOGIC;
FTMD_TRACEIN_CLK : in STD_LOGIC;
FTMD_TRACEIN_ATID : in STD_LOGIC_VECTOR ( 3 downto 0 );
FTMT_F2P_TRIG_0 : in STD_LOGIC;
FTMT_F2P_TRIGACK_0 : out STD_LOGIC;
FTMT_F2P_TRIG_1 : in STD_LOGIC;
FTMT_F2P_TRIGACK_1 : out STD_LOGIC;
FTMT_F2P_TRIG_2 : in STD_LOGIC;
FTMT_F2P_TRIGACK_2 : out STD_LOGIC;
FTMT_F2P_TRIG_3 : in STD_LOGIC;
FTMT_F2P_TRIGACK_3 : out STD_LOGIC;
FTMT_F2P_DEBUG : in STD_LOGIC_VECTOR ( 31 downto 0 );
FTMT_P2F_TRIGACK_0 : in STD_LOGIC;
FTMT_P2F_TRIG_0 : out STD_LOGIC;
FTMT_P2F_TRIGACK_1 : in STD_LOGIC;
FTMT_P2F_TRIG_1 : out STD_LOGIC;
FTMT_P2F_TRIGACK_2 : in STD_LOGIC;
FTMT_P2F_TRIG_2 : out STD_LOGIC;
FTMT_P2F_TRIGACK_3 : in STD_LOGIC;
FTMT_P2F_TRIG_3 : out STD_LOGIC;
FTMT_P2F_DEBUG : out STD_LOGIC_VECTOR ( 31 downto 0 );
FPGA_IDLE_N : in STD_LOGIC;
EVENT_EVENTO : out STD_LOGIC;
EVENT_STANDBYWFE : out STD_LOGIC_VECTOR ( 1 downto 0 );
EVENT_STANDBYWFI : out STD_LOGIC_VECTOR ( 1 downto 0 );
EVENT_EVENTI : in STD_LOGIC;
DDR_ARB : in STD_LOGIC_VECTOR ( 3 downto 0 );
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
attribute C_DM_WIDTH : integer;
attribute C_DM_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 4;
attribute C_DQS_WIDTH : integer;
attribute C_DQS_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 4;
attribute C_DQ_WIDTH : integer;
attribute C_DQ_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 32;
attribute C_EMIO_GPIO_WIDTH : integer;
attribute C_EMIO_GPIO_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_EN_EMIO_ENET0 : integer;
attribute C_EN_EMIO_ENET0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_ENET1 : integer;
attribute C_EN_EMIO_ENET1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_PJTAG : integer;
attribute C_EN_EMIO_PJTAG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "TRUE";
attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_FCLK_CLK2_BUF : string;
attribute C_FCLK_CLK2_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_FCLK_CLK3_BUF : string;
attribute C_FCLK_CLK3_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_GP0_EN_MODIFIABLE_TXN : integer;
attribute C_GP0_EN_MODIFIABLE_TXN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_GP1_EN_MODIFIABLE_TXN : integer;
attribute C_GP1_EN_MODIFIABLE_TXN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
attribute C_INCLUDE_ACP_TRANS_CHECK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_INCLUDE_TRACE_BUFFER : integer;
attribute C_INCLUDE_TRACE_BUFFER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_IRQ_F2P_MODE : string;
attribute C_IRQ_F2P_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "DIRECT";
attribute C_MIO_PRIMITIVE : integer;
attribute C_MIO_PRIMITIVE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 54;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_M_AXI_GP0_ID_WIDTH : integer;
attribute C_M_AXI_GP0_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_M_AXI_GP1_ID_WIDTH : integer;
attribute C_M_AXI_GP1_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_NUM_F2P_INTR_INPUTS : integer;
attribute C_NUM_F2P_INTR_INPUTS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 2;
attribute C_PACKAGE_NAME : string;
attribute C_PACKAGE_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "clg484";
attribute C_PS7_SI_REV : string;
attribute C_PS7_SI_REV of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "PRODUCTION";
attribute C_S_AXI_ACP_ARUSER_VAL : integer;
attribute C_S_AXI_ACP_ARUSER_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 31;
attribute C_S_AXI_ACP_AWUSER_VAL : integer;
attribute C_S_AXI_ACP_AWUSER_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 31;
attribute C_S_AXI_ACP_ID_WIDTH : integer;
attribute C_S_AXI_ACP_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 3;
attribute C_S_AXI_GP0_ID_WIDTH : integer;
attribute C_S_AXI_GP0_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_GP1_ID_WIDTH : integer;
attribute C_S_AXI_GP1_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP0_DATA_WIDTH : integer;
attribute C_S_AXI_HP0_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP0_ID_WIDTH : integer;
attribute C_S_AXI_HP0_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP1_DATA_WIDTH : integer;
attribute C_S_AXI_HP1_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP1_ID_WIDTH : integer;
attribute C_S_AXI_HP1_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP2_DATA_WIDTH : integer;
attribute C_S_AXI_HP2_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP2_ID_WIDTH : integer;
attribute C_S_AXI_HP2_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP3_DATA_WIDTH : integer;
attribute C_S_AXI_HP3_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP3_ID_WIDTH : integer;
attribute C_S_AXI_HP3_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
attribute C_TRACE_BUFFER_CLOCK_DELAY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
attribute C_TRACE_BUFFER_FIFO_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 128;
attribute C_TRACE_INTERNAL_WIDTH : integer;
attribute C_TRACE_INTERNAL_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 2;
attribute C_TRACE_PIPELINE_WIDTH : integer;
attribute C_TRACE_PIPELINE_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 8;
attribute C_USE_AXI_NONSECURE : integer;
attribute C_USE_AXI_NONSECURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
attribute C_USE_DEFAULT_ACP_USER_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_M_AXI_GP0 : integer;
attribute C_USE_M_AXI_GP0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_USE_M_AXI_GP1 : integer;
attribute C_USE_M_AXI_GP1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_ACP : integer;
attribute C_USE_S_AXI_ACP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_GP0 : integer;
attribute C_USE_S_AXI_GP0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_GP1 : integer;
attribute C_USE_S_AXI_GP1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP0 : integer;
attribute C_USE_S_AXI_HP0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP1 : integer;
attribute C_USE_S_AXI_HP1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP2 : integer;
attribute C_USE_S_AXI_HP2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP3 : integer;
attribute C_USE_S_AXI_HP3 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "zqynq_lab_1_design_processing_system7_0_0.hwdef";
attribute POWER : string;
attribute POWER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal ENET0_MDIO_T_n : STD_LOGIC;
signal ENET1_MDIO_T_n : STD_LOGIC;
signal FCLK_CLK_unbuffered : STD_LOGIC_VECTOR ( 0 to 0 );
signal I2C0_SCL_T_n : STD_LOGIC;
signal I2C0_SDA_T_n : STD_LOGIC;
signal I2C1_SCL_T_n : STD_LOGIC;
signal I2C1_SDA_T_n : STD_LOGIC;
signal \^m_axi_gp0_arcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_gp0_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp0_awcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_gp0_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp1_arcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_gp1_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp1_awcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_gp1_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal SDIO0_CMD_T_n : STD_LOGIC;
signal SDIO0_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal SDIO1_CMD_T_n : STD_LOGIC;
signal SDIO1_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal SPI0_MISO_T_n : STD_LOGIC;
signal SPI0_MOSI_T_n : STD_LOGIC;
signal SPI0_SCLK_T_n : STD_LOGIC;
signal SPI0_SS_T_n : STD_LOGIC;
signal SPI1_MISO_T_n : STD_LOGIC;
signal SPI1_MOSI_T_n : STD_LOGIC;
signal SPI1_SCLK_T_n : STD_LOGIC;
signal SPI1_SS_T_n : STD_LOGIC;
signal \TRACE_CTL_PIPE[0]\ : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of \TRACE_CTL_PIPE[0]\ : signal is "true";
signal \TRACE_CTL_PIPE[1]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[1]\ : signal is "true";
signal \TRACE_CTL_PIPE[2]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[2]\ : signal is "true";
signal \TRACE_CTL_PIPE[3]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[3]\ : signal is "true";
signal \TRACE_CTL_PIPE[4]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[4]\ : signal is "true";
signal \TRACE_CTL_PIPE[5]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[5]\ : signal is "true";
signal \TRACE_CTL_PIPE[6]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[6]\ : signal is "true";
signal \TRACE_CTL_PIPE[7]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[7]\ : signal is "true";
signal \TRACE_DATA_PIPE[0]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[0]\ : signal is "true";
signal \TRACE_DATA_PIPE[1]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[1]\ : signal is "true";
signal \TRACE_DATA_PIPE[2]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[2]\ : signal is "true";
signal \TRACE_DATA_PIPE[3]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[3]\ : signal is "true";
signal \TRACE_DATA_PIPE[4]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[4]\ : signal is "true";
signal \TRACE_DATA_PIPE[5]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[5]\ : signal is "true";
signal \TRACE_DATA_PIPE[6]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[6]\ : signal is "true";
signal \TRACE_DATA_PIPE[7]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[7]\ : signal is "true";
signal buffered_DDR_Addr : STD_LOGIC_VECTOR ( 14 downto 0 );
signal buffered_DDR_BankAddr : STD_LOGIC_VECTOR ( 2 downto 0 );
signal buffered_DDR_CAS_n : STD_LOGIC;
signal buffered_DDR_CKE : STD_LOGIC;
signal buffered_DDR_CS_n : STD_LOGIC;
signal buffered_DDR_Clk : STD_LOGIC;
signal buffered_DDR_Clk_n : STD_LOGIC;
signal buffered_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal buffered_DDR_DQS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DQS_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DRSTB : STD_LOGIC;
signal buffered_DDR_ODT : STD_LOGIC;
signal buffered_DDR_RAS_n : STD_LOGIC;
signal buffered_DDR_VRN : STD_LOGIC;
signal buffered_DDR_VRP : STD_LOGIC;
signal buffered_DDR_WEB : STD_LOGIC;
signal buffered_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal buffered_PS_CLK : STD_LOGIC;
signal buffered_PS_PORB : STD_LOGIC;
signal buffered_PS_SRSTB : STD_LOGIC;
signal gpio_out_t_n : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOTRACECTL_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of DDR_CAS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_CKE_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_CS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_Clk_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_Clk_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_DRSTB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_ODT_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_RAS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_VRN_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_VRP_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_WEB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS7_i : label is "PRIMITIVE";
attribute BOX_TYPE of PS_CLK_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS_PORB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS_SRSTB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of \buffer_fclk_clk_0.FCLK_CLK_0_BUFG\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[0].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[10].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[11].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[12].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[13].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[14].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[15].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[16].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[17].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[18].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[19].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[1].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[20].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[21].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[22].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[23].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[24].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[25].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[26].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[27].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[28].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[29].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[2].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[30].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[31].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[32].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[33].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[34].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[35].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[36].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[37].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[38].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[39].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[3].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[40].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[41].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[42].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[43].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[44].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[45].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[46].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[47].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[48].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[49].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[4].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[50].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[51].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[52].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[53].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[5].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[6].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[7].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[8].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[9].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[0].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[1].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[2].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[0].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[10].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[11].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[12].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[13].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[14].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[1].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[2].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[3].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[4].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[5].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[6].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[7].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[8].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[9].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[0].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[1].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[2].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[3].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[0].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[10].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[11].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[12].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[13].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[14].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[15].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[16].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[17].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[18].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[19].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[1].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[20].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[21].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[22].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[23].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[24].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[25].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[26].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[27].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[28].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[29].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[2].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[30].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[31].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[3].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[4].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[5].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[6].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[7].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[8].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[9].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[0].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[1].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[2].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[3].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[0].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[1].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[2].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[3].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
begin
ENET0_GMII_TXD(7) <= \<const0>\;
ENET0_GMII_TXD(6) <= \<const0>\;
ENET0_GMII_TXD(5) <= \<const0>\;
ENET0_GMII_TXD(4) <= \<const0>\;
ENET0_GMII_TXD(3) <= \<const0>\;
ENET0_GMII_TXD(2) <= \<const0>\;
ENET0_GMII_TXD(1) <= \<const0>\;
ENET0_GMII_TXD(0) <= \<const0>\;
ENET0_GMII_TX_EN <= \<const0>\;
ENET0_GMII_TX_ER <= \<const0>\;
ENET1_GMII_TXD(7) <= \<const0>\;
ENET1_GMII_TXD(6) <= \<const0>\;
ENET1_GMII_TXD(5) <= \<const0>\;
ENET1_GMII_TXD(4) <= \<const0>\;
ENET1_GMII_TXD(3) <= \<const0>\;
ENET1_GMII_TXD(2) <= \<const0>\;
ENET1_GMII_TXD(1) <= \<const0>\;
ENET1_GMII_TXD(0) <= \<const0>\;
ENET1_GMII_TX_EN <= \<const0>\;
ENET1_GMII_TX_ER <= \<const0>\;
M_AXI_GP0_ARCACHE(3 downto 2) <= \^m_axi_gp0_arcache\(3 downto 2);
M_AXI_GP0_ARCACHE(1) <= \<const1>\;
M_AXI_GP0_ARCACHE(0) <= \^m_axi_gp0_arcache\(0);
M_AXI_GP0_ARSIZE(2) <= \<const0>\;
M_AXI_GP0_ARSIZE(1 downto 0) <= \^m_axi_gp0_arsize\(1 downto 0);
M_AXI_GP0_AWCACHE(3 downto 2) <= \^m_axi_gp0_awcache\(3 downto 2);
M_AXI_GP0_AWCACHE(1) <= \<const1>\;
M_AXI_GP0_AWCACHE(0) <= \^m_axi_gp0_awcache\(0);
M_AXI_GP0_AWSIZE(2) <= \<const0>\;
M_AXI_GP0_AWSIZE(1 downto 0) <= \^m_axi_gp0_awsize\(1 downto 0);
M_AXI_GP1_ARCACHE(3 downto 2) <= \^m_axi_gp1_arcache\(3 downto 2);
M_AXI_GP1_ARCACHE(1) <= \<const1>\;
M_AXI_GP1_ARCACHE(0) <= \^m_axi_gp1_arcache\(0);
M_AXI_GP1_ARSIZE(2) <= \<const0>\;
M_AXI_GP1_ARSIZE(1 downto 0) <= \^m_axi_gp1_arsize\(1 downto 0);
M_AXI_GP1_AWCACHE(3 downto 2) <= \^m_axi_gp1_awcache\(3 downto 2);
M_AXI_GP1_AWCACHE(1) <= \<const1>\;
M_AXI_GP1_AWCACHE(0) <= \^m_axi_gp1_awcache\(0);
M_AXI_GP1_AWSIZE(2) <= \<const0>\;
M_AXI_GP1_AWSIZE(1 downto 0) <= \^m_axi_gp1_awsize\(1 downto 0);
PJTAG_TDO <= \<const0>\;
TRACE_CLK_OUT <= \<const0>\;
TRACE_CTL <= \TRACE_CTL_PIPE[0]\;
TRACE_DATA(1 downto 0) <= \TRACE_DATA_PIPE[0]\(1 downto 0);
DDR_CAS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CAS_n,
PAD => DDR_CAS_n
);
DDR_CKE_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CKE,
PAD => DDR_CKE
);
DDR_CS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CS_n,
PAD => DDR_CS_n
);
DDR_Clk_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Clk,
PAD => DDR_Clk
);
DDR_Clk_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Clk_n,
PAD => DDR_Clk_n
);
DDR_DRSTB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DRSTB,
PAD => DDR_DRSTB
);
DDR_ODT_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_ODT,
PAD => DDR_ODT
);
DDR_RAS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_RAS_n,
PAD => DDR_RAS_n
);
DDR_VRN_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_VRN,
PAD => DDR_VRN
);
DDR_VRP_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_VRP,
PAD => DDR_VRP
);
DDR_WEB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_WEB,
PAD => DDR_WEB
);
ENET0_MDIO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ENET0_MDIO_T_n,
O => ENET0_MDIO_T
);
ENET1_MDIO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ENET1_MDIO_T_n,
O => ENET1_MDIO_T
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\GPIO_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(0),
O => GPIO_T(0)
);
\GPIO_T[10]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(10),
O => GPIO_T(10)
);
\GPIO_T[11]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(11),
O => GPIO_T(11)
);
\GPIO_T[12]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(12),
O => GPIO_T(12)
);
\GPIO_T[13]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(13),
O => GPIO_T(13)
);
\GPIO_T[14]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(14),
O => GPIO_T(14)
);
\GPIO_T[15]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(15),
O => GPIO_T(15)
);
\GPIO_T[16]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(16),
O => GPIO_T(16)
);
\GPIO_T[17]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(17),
O => GPIO_T(17)
);
\GPIO_T[18]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(18),
O => GPIO_T(18)
);
\GPIO_T[19]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(19),
O => GPIO_T(19)
);
\GPIO_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(1),
O => GPIO_T(1)
);
\GPIO_T[20]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(20),
O => GPIO_T(20)
);
\GPIO_T[21]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(21),
O => GPIO_T(21)
);
\GPIO_T[22]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(22),
O => GPIO_T(22)
);
\GPIO_T[23]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(23),
O => GPIO_T(23)
);
\GPIO_T[24]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(24),
O => GPIO_T(24)
);
\GPIO_T[25]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(25),
O => GPIO_T(25)
);
\GPIO_T[26]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(26),
O => GPIO_T(26)
);
\GPIO_T[27]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(27),
O => GPIO_T(27)
);
\GPIO_T[28]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(28),
O => GPIO_T(28)
);
\GPIO_T[29]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(29),
O => GPIO_T(29)
);
\GPIO_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(2),
O => GPIO_T(2)
);
\GPIO_T[30]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(30),
O => GPIO_T(30)
);
\GPIO_T[31]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(31),
O => GPIO_T(31)
);
\GPIO_T[32]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(32),
O => GPIO_T(32)
);
\GPIO_T[33]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(33),
O => GPIO_T(33)
);
\GPIO_T[34]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(34),
O => GPIO_T(34)
);
\GPIO_T[35]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(35),
O => GPIO_T(35)
);
\GPIO_T[36]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(36),
O => GPIO_T(36)
);
\GPIO_T[37]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(37),
O => GPIO_T(37)
);
\GPIO_T[38]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(38),
O => GPIO_T(38)
);
\GPIO_T[39]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(39),
O => GPIO_T(39)
);
\GPIO_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(3),
O => GPIO_T(3)
);
\GPIO_T[40]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(40),
O => GPIO_T(40)
);
\GPIO_T[41]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(41),
O => GPIO_T(41)
);
\GPIO_T[42]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(42),
O => GPIO_T(42)
);
\GPIO_T[43]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(43),
O => GPIO_T(43)
);
\GPIO_T[44]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(44),
O => GPIO_T(44)
);
\GPIO_T[45]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(45),
O => GPIO_T(45)
);
\GPIO_T[46]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(46),
O => GPIO_T(46)
);
\GPIO_T[47]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(47),
O => GPIO_T(47)
);
\GPIO_T[48]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(48),
O => GPIO_T(48)
);
\GPIO_T[49]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(49),
O => GPIO_T(49)
);
\GPIO_T[4]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(4),
O => GPIO_T(4)
);
\GPIO_T[50]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(50),
O => GPIO_T(50)
);
\GPIO_T[51]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(51),
O => GPIO_T(51)
);
\GPIO_T[52]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(52),
O => GPIO_T(52)
);
\GPIO_T[53]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(53),
O => GPIO_T(53)
);
\GPIO_T[54]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(54),
O => GPIO_T(54)
);
\GPIO_T[55]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(55),
O => GPIO_T(55)
);
\GPIO_T[56]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(56),
O => GPIO_T(56)
);
\GPIO_T[57]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(57),
O => GPIO_T(57)
);
\GPIO_T[58]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(58),
O => GPIO_T(58)
);
\GPIO_T[59]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(59),
O => GPIO_T(59)
);
\GPIO_T[5]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(5),
O => GPIO_T(5)
);
\GPIO_T[60]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(60),
O => GPIO_T(60)
);
\GPIO_T[61]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(61),
O => GPIO_T(61)
);
\GPIO_T[62]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(62),
O => GPIO_T(62)
);
\GPIO_T[63]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(63),
O => GPIO_T(63)
);
\GPIO_T[6]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(6),
O => GPIO_T(6)
);
\GPIO_T[7]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(7),
O => GPIO_T(7)
);
\GPIO_T[8]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(8),
O => GPIO_T(8)
);
\GPIO_T[9]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(9),
O => GPIO_T(9)
);
I2C0_SCL_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C0_SCL_T_n,
O => I2C0_SCL_T
);
I2C0_SDA_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C0_SDA_T_n,
O => I2C0_SDA_T
);
I2C1_SCL_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C1_SCL_T_n,
O => I2C1_SCL_T
);
I2C1_SDA_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C1_SDA_T_n,
O => I2C1_SDA_T
);
PS7_i: unisim.vcomponents.PS7
port map (
DDRA(14 downto 0) => buffered_DDR_Addr(14 downto 0),
DDRARB(3 downto 0) => DDR_ARB(3 downto 0),
DDRBA(2 downto 0) => buffered_DDR_BankAddr(2 downto 0),
DDRCASB => buffered_DDR_CAS_n,
DDRCKE => buffered_DDR_CKE,
DDRCKN => buffered_DDR_Clk_n,
DDRCKP => buffered_DDR_Clk,
DDRCSB => buffered_DDR_CS_n,
DDRDM(3 downto 0) => buffered_DDR_DM(3 downto 0),
DDRDQ(31 downto 0) => buffered_DDR_DQ(31 downto 0),
DDRDQSN(3 downto 0) => buffered_DDR_DQS_n(3 downto 0),
DDRDQSP(3 downto 0) => buffered_DDR_DQS(3 downto 0),
DDRDRSTB => buffered_DDR_DRSTB,
DDRODT => buffered_DDR_ODT,
DDRRASB => buffered_DDR_RAS_n,
DDRVRN => buffered_DDR_VRN,
DDRVRP => buffered_DDR_VRP,
DDRWEB => buffered_DDR_WEB,
DMA0ACLK => DMA0_ACLK,
DMA0DAREADY => DMA0_DAREADY,
DMA0DATYPE(1 downto 0) => DMA0_DATYPE(1 downto 0),
DMA0DAVALID => DMA0_DAVALID,
DMA0DRLAST => DMA0_DRLAST,
DMA0DRREADY => DMA0_DRREADY,
DMA0DRTYPE(1 downto 0) => DMA0_DRTYPE(1 downto 0),
DMA0DRVALID => DMA0_DRVALID,
DMA0RSTN => DMA0_RSTN,
DMA1ACLK => DMA1_ACLK,
DMA1DAREADY => DMA1_DAREADY,
DMA1DATYPE(1 downto 0) => DMA1_DATYPE(1 downto 0),
DMA1DAVALID => DMA1_DAVALID,
DMA1DRLAST => DMA1_DRLAST,
DMA1DRREADY => DMA1_DRREADY,
DMA1DRTYPE(1 downto 0) => DMA1_DRTYPE(1 downto 0),
DMA1DRVALID => DMA1_DRVALID,
DMA1RSTN => DMA1_RSTN,
DMA2ACLK => DMA2_ACLK,
DMA2DAREADY => DMA2_DAREADY,
DMA2DATYPE(1 downto 0) => DMA2_DATYPE(1 downto 0),
DMA2DAVALID => DMA2_DAVALID,
DMA2DRLAST => DMA2_DRLAST,
DMA2DRREADY => DMA2_DRREADY,
DMA2DRTYPE(1 downto 0) => DMA2_DRTYPE(1 downto 0),
DMA2DRVALID => DMA2_DRVALID,
DMA2RSTN => DMA2_RSTN,
DMA3ACLK => DMA3_ACLK,
DMA3DAREADY => DMA3_DAREADY,
DMA3DATYPE(1 downto 0) => DMA3_DATYPE(1 downto 0),
DMA3DAVALID => DMA3_DAVALID,
DMA3DRLAST => DMA3_DRLAST,
DMA3DRREADY => DMA3_DRREADY,
DMA3DRTYPE(1 downto 0) => DMA3_DRTYPE(1 downto 0),
DMA3DRVALID => DMA3_DRVALID,
DMA3RSTN => DMA3_RSTN,
EMIOCAN0PHYRX => CAN0_PHY_RX,
EMIOCAN0PHYTX => CAN0_PHY_TX,
EMIOCAN1PHYRX => CAN1_PHY_RX,
EMIOCAN1PHYTX => CAN1_PHY_TX,
EMIOENET0EXTINTIN => ENET0_EXT_INTIN,
EMIOENET0GMIICOL => '0',
EMIOENET0GMIICRS => '0',
EMIOENET0GMIIRXCLK => ENET0_GMII_RX_CLK,
EMIOENET0GMIIRXD(7 downto 0) => B"00000000",
EMIOENET0GMIIRXDV => '0',
EMIOENET0GMIIRXER => '0',
EMIOENET0GMIITXCLK => ENET0_GMII_TX_CLK,
EMIOENET0GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED(7 downto 0),
EMIOENET0GMIITXEN => NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED,
EMIOENET0GMIITXER => NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED,
EMIOENET0MDIOI => ENET0_MDIO_I,
EMIOENET0MDIOMDC => ENET0_MDIO_MDC,
EMIOENET0MDIOO => ENET0_MDIO_O,
EMIOENET0MDIOTN => ENET0_MDIO_T_n,
EMIOENET0PTPDELAYREQRX => ENET0_PTP_DELAY_REQ_RX,
EMIOENET0PTPDELAYREQTX => ENET0_PTP_DELAY_REQ_TX,
EMIOENET0PTPPDELAYREQRX => ENET0_PTP_PDELAY_REQ_RX,
EMIOENET0PTPPDELAYREQTX => ENET0_PTP_PDELAY_REQ_TX,
EMIOENET0PTPPDELAYRESPRX => ENET0_PTP_PDELAY_RESP_RX,
EMIOENET0PTPPDELAYRESPTX => ENET0_PTP_PDELAY_RESP_TX,
EMIOENET0PTPSYNCFRAMERX => ENET0_PTP_SYNC_FRAME_RX,
EMIOENET0PTPSYNCFRAMETX => ENET0_PTP_SYNC_FRAME_TX,
EMIOENET0SOFRX => ENET0_SOF_RX,
EMIOENET0SOFTX => ENET0_SOF_TX,
EMIOENET1EXTINTIN => ENET1_EXT_INTIN,
EMIOENET1GMIICOL => '0',
EMIOENET1GMIICRS => '0',
EMIOENET1GMIIRXCLK => ENET1_GMII_RX_CLK,
EMIOENET1GMIIRXD(7 downto 0) => B"00000000",
EMIOENET1GMIIRXDV => '0',
EMIOENET1GMIIRXER => '0',
EMIOENET1GMIITXCLK => ENET1_GMII_TX_CLK,
EMIOENET1GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED(7 downto 0),
EMIOENET1GMIITXEN => NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED,
EMIOENET1GMIITXER => NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED,
EMIOENET1MDIOI => ENET1_MDIO_I,
EMIOENET1MDIOMDC => ENET1_MDIO_MDC,
EMIOENET1MDIOO => ENET1_MDIO_O,
EMIOENET1MDIOTN => ENET1_MDIO_T_n,
EMIOENET1PTPDELAYREQRX => ENET1_PTP_DELAY_REQ_RX,
EMIOENET1PTPDELAYREQTX => ENET1_PTP_DELAY_REQ_TX,
EMIOENET1PTPPDELAYREQRX => ENET1_PTP_PDELAY_REQ_RX,
EMIOENET1PTPPDELAYREQTX => ENET1_PTP_PDELAY_REQ_TX,
EMIOENET1PTPPDELAYRESPRX => ENET1_PTP_PDELAY_RESP_RX,
EMIOENET1PTPPDELAYRESPTX => ENET1_PTP_PDELAY_RESP_TX,
EMIOENET1PTPSYNCFRAMERX => ENET1_PTP_SYNC_FRAME_RX,
EMIOENET1PTPSYNCFRAMETX => ENET1_PTP_SYNC_FRAME_TX,
EMIOENET1SOFRX => ENET1_SOF_RX,
EMIOENET1SOFTX => ENET1_SOF_TX,
EMIOGPIOI(63 downto 0) => GPIO_I(63 downto 0),
EMIOGPIOO(63 downto 0) => GPIO_O(63 downto 0),
EMIOGPIOTN(63 downto 0) => gpio_out_t_n(63 downto 0),
EMIOI2C0SCLI => I2C0_SCL_I,
EMIOI2C0SCLO => I2C0_SCL_O,
EMIOI2C0SCLTN => I2C0_SCL_T_n,
EMIOI2C0SDAI => I2C0_SDA_I,
EMIOI2C0SDAO => I2C0_SDA_O,
EMIOI2C0SDATN => I2C0_SDA_T_n,
EMIOI2C1SCLI => I2C1_SCL_I,
EMIOI2C1SCLO => I2C1_SCL_O,
EMIOI2C1SCLTN => I2C1_SCL_T_n,
EMIOI2C1SDAI => I2C1_SDA_I,
EMIOI2C1SDAO => I2C1_SDA_O,
EMIOI2C1SDATN => I2C1_SDA_T_n,
EMIOPJTAGTCK => PJTAG_TCK,
EMIOPJTAGTDI => PJTAG_TDI,
EMIOPJTAGTDO => NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED,
EMIOPJTAGTDTN => NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED,
EMIOPJTAGTMS => PJTAG_TMS,
EMIOSDIO0BUSPOW => SDIO0_BUSPOW,
EMIOSDIO0BUSVOLT(2 downto 0) => SDIO0_BUSVOLT(2 downto 0),
EMIOSDIO0CDN => SDIO0_CDN,
EMIOSDIO0CLK => SDIO0_CLK,
EMIOSDIO0CLKFB => SDIO0_CLK_FB,
EMIOSDIO0CMDI => SDIO0_CMD_I,
EMIOSDIO0CMDO => SDIO0_CMD_O,
EMIOSDIO0CMDTN => SDIO0_CMD_T_n,
EMIOSDIO0DATAI(3 downto 0) => SDIO0_DATA_I(3 downto 0),
EMIOSDIO0DATAO(3 downto 0) => SDIO0_DATA_O(3 downto 0),
EMIOSDIO0DATATN(3 downto 0) => SDIO0_DATA_T_n(3 downto 0),
EMIOSDIO0LED => SDIO0_LED,
EMIOSDIO0WP => SDIO0_WP,
EMIOSDIO1BUSPOW => SDIO1_BUSPOW,
EMIOSDIO1BUSVOLT(2 downto 0) => SDIO1_BUSVOLT(2 downto 0),
EMIOSDIO1CDN => SDIO1_CDN,
EMIOSDIO1CLK => SDIO1_CLK,
EMIOSDIO1CLKFB => SDIO1_CLK_FB,
EMIOSDIO1CMDI => SDIO1_CMD_I,
EMIOSDIO1CMDO => SDIO1_CMD_O,
EMIOSDIO1CMDTN => SDIO1_CMD_T_n,
EMIOSDIO1DATAI(3 downto 0) => SDIO1_DATA_I(3 downto 0),
EMIOSDIO1DATAO(3 downto 0) => SDIO1_DATA_O(3 downto 0),
EMIOSDIO1DATATN(3 downto 0) => SDIO1_DATA_T_n(3 downto 0),
EMIOSDIO1LED => SDIO1_LED,
EMIOSDIO1WP => SDIO1_WP,
EMIOSPI0MI => SPI0_MISO_I,
EMIOSPI0MO => SPI0_MOSI_O,
EMIOSPI0MOTN => SPI0_MOSI_T_n,
EMIOSPI0SCLKI => SPI0_SCLK_I,
EMIOSPI0SCLKO => SPI0_SCLK_O,
EMIOSPI0SCLKTN => SPI0_SCLK_T_n,
EMIOSPI0SI => SPI0_MOSI_I,
EMIOSPI0SO => SPI0_MISO_O,
EMIOSPI0SSIN => SPI0_SS_I,
EMIOSPI0SSNTN => SPI0_SS_T_n,
EMIOSPI0SSON(2) => SPI0_SS2_O,
EMIOSPI0SSON(1) => SPI0_SS1_O,
EMIOSPI0SSON(0) => SPI0_SS_O,
EMIOSPI0STN => SPI0_MISO_T_n,
EMIOSPI1MI => SPI1_MISO_I,
EMIOSPI1MO => SPI1_MOSI_O,
EMIOSPI1MOTN => SPI1_MOSI_T_n,
EMIOSPI1SCLKI => SPI1_SCLK_I,
EMIOSPI1SCLKO => SPI1_SCLK_O,
EMIOSPI1SCLKTN => SPI1_SCLK_T_n,
EMIOSPI1SI => SPI1_MOSI_I,
EMIOSPI1SO => SPI1_MISO_O,
EMIOSPI1SSIN => SPI1_SS_I,
EMIOSPI1SSNTN => SPI1_SS_T_n,
EMIOSPI1SSON(2) => SPI1_SS2_O,
EMIOSPI1SSON(1) => SPI1_SS1_O,
EMIOSPI1SSON(0) => SPI1_SS_O,
EMIOSPI1STN => SPI1_MISO_T_n,
EMIOSRAMINTIN => SRAM_INTIN,
EMIOTRACECLK => TRACE_CLK,
EMIOTRACECTL => NLW_PS7_i_EMIOTRACECTL_UNCONNECTED,
EMIOTRACEDATA(31 downto 0) => NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED(31 downto 0),
EMIOTTC0CLKI(2) => TTC0_CLK2_IN,
EMIOTTC0CLKI(1) => TTC0_CLK1_IN,
EMIOTTC0CLKI(0) => TTC0_CLK0_IN,
EMIOTTC0WAVEO(2) => TTC0_WAVE2_OUT,
EMIOTTC0WAVEO(1) => TTC0_WAVE1_OUT,
EMIOTTC0WAVEO(0) => TTC0_WAVE0_OUT,
EMIOTTC1CLKI(2) => TTC1_CLK2_IN,
EMIOTTC1CLKI(1) => TTC1_CLK1_IN,
EMIOTTC1CLKI(0) => TTC1_CLK0_IN,
EMIOTTC1WAVEO(2) => TTC1_WAVE2_OUT,
EMIOTTC1WAVEO(1) => TTC1_WAVE1_OUT,
EMIOTTC1WAVEO(0) => TTC1_WAVE0_OUT,
EMIOUART0CTSN => UART0_CTSN,
EMIOUART0DCDN => UART0_DCDN,
EMIOUART0DSRN => UART0_DSRN,
EMIOUART0DTRN => UART0_DTRN,
EMIOUART0RIN => UART0_RIN,
EMIOUART0RTSN => UART0_RTSN,
EMIOUART0RX => UART0_RX,
EMIOUART0TX => UART0_TX,
EMIOUART1CTSN => UART1_CTSN,
EMIOUART1DCDN => UART1_DCDN,
EMIOUART1DSRN => UART1_DSRN,
EMIOUART1DTRN => UART1_DTRN,
EMIOUART1RIN => UART1_RIN,
EMIOUART1RTSN => UART1_RTSN,
EMIOUART1RX => UART1_RX,
EMIOUART1TX => UART1_TX,
EMIOUSB0PORTINDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0),
EMIOUSB0VBUSPWRFAULT => USB0_VBUS_PWRFAULT,
EMIOUSB0VBUSPWRSELECT => USB0_VBUS_PWRSELECT,
EMIOUSB1PORTINDCTL(1 downto 0) => USB1_PORT_INDCTL(1 downto 0),
EMIOUSB1VBUSPWRFAULT => USB1_VBUS_PWRFAULT,
EMIOUSB1VBUSPWRSELECT => USB1_VBUS_PWRSELECT,
EMIOWDTCLKI => WDT_CLK_IN,
EMIOWDTRSTO => WDT_RST_OUT,
EVENTEVENTI => EVENT_EVENTI,
EVENTEVENTO => EVENT_EVENTO,
EVENTSTANDBYWFE(1 downto 0) => EVENT_STANDBYWFE(1 downto 0),
EVENTSTANDBYWFI(1 downto 0) => EVENT_STANDBYWFI(1 downto 0),
FCLKCLK(3) => FCLK_CLK3,
FCLKCLK(2) => FCLK_CLK2,
FCLKCLK(1) => FCLK_CLK1,
FCLKCLK(0) => FCLK_CLK_unbuffered(0),
FCLKCLKTRIGN(3 downto 0) => B"0000",
FCLKRESETN(3) => FCLK_RESET3_N,
FCLKRESETN(2) => FCLK_RESET2_N,
FCLKRESETN(1) => FCLK_RESET1_N,
FCLKRESETN(0) => FCLK_RESET0_N,
FPGAIDLEN => FPGA_IDLE_N,
FTMDTRACEINATID(3 downto 0) => B"0000",
FTMDTRACEINCLOCK => FTMD_TRACEIN_CLK,
FTMDTRACEINDATA(31 downto 0) => B"00000000000000000000000000000000",
FTMDTRACEINVALID => '0',
FTMTF2PDEBUG(31 downto 0) => FTMT_F2P_DEBUG(31 downto 0),
FTMTF2PTRIG(3) => FTMT_F2P_TRIG_3,
FTMTF2PTRIG(2) => FTMT_F2P_TRIG_2,
FTMTF2PTRIG(1) => FTMT_F2P_TRIG_1,
FTMTF2PTRIG(0) => FTMT_F2P_TRIG_0,
FTMTF2PTRIGACK(3) => FTMT_F2P_TRIGACK_3,
FTMTF2PTRIGACK(2) => FTMT_F2P_TRIGACK_2,
FTMTF2PTRIGACK(1) => FTMT_F2P_TRIGACK_1,
FTMTF2PTRIGACK(0) => FTMT_F2P_TRIGACK_0,
FTMTP2FDEBUG(31 downto 0) => FTMT_P2F_DEBUG(31 downto 0),
FTMTP2FTRIG(3) => FTMT_P2F_TRIG_3,
FTMTP2FTRIG(2) => FTMT_P2F_TRIG_2,
FTMTP2FTRIG(1) => FTMT_P2F_TRIG_1,
FTMTP2FTRIG(0) => FTMT_P2F_TRIG_0,
FTMTP2FTRIGACK(3) => FTMT_P2F_TRIGACK_3,
FTMTP2FTRIGACK(2) => FTMT_P2F_TRIGACK_2,
FTMTP2FTRIGACK(1) => FTMT_P2F_TRIGACK_1,
FTMTP2FTRIGACK(0) => FTMT_P2F_TRIGACK_0,
IRQF2P(19) => Core1_nFIQ,
IRQF2P(18) => Core0_nFIQ,
IRQF2P(17) => Core1_nIRQ,
IRQF2P(16) => Core0_nIRQ,
IRQF2P(15 downto 2) => B"00000000000000",
IRQF2P(1 downto 0) => IRQ_F2P(1 downto 0),
IRQP2F(28) => IRQ_P2F_DMAC_ABORT,
IRQP2F(27) => IRQ_P2F_DMAC7,
IRQP2F(26) => IRQ_P2F_DMAC6,
IRQP2F(25) => IRQ_P2F_DMAC5,
IRQP2F(24) => IRQ_P2F_DMAC4,
IRQP2F(23) => IRQ_P2F_DMAC3,
IRQP2F(22) => IRQ_P2F_DMAC2,
IRQP2F(21) => IRQ_P2F_DMAC1,
IRQP2F(20) => IRQ_P2F_DMAC0,
IRQP2F(19) => IRQ_P2F_SMC,
IRQP2F(18) => IRQ_P2F_QSPI,
IRQP2F(17) => IRQ_P2F_CTI,
IRQP2F(16) => IRQ_P2F_GPIO,
IRQP2F(15) => IRQ_P2F_USB0,
IRQP2F(14) => IRQ_P2F_ENET0,
IRQP2F(13) => IRQ_P2F_ENET_WAKE0,
IRQP2F(12) => IRQ_P2F_SDIO0,
IRQP2F(11) => IRQ_P2F_I2C0,
IRQP2F(10) => IRQ_P2F_SPI0,
IRQP2F(9) => IRQ_P2F_UART0,
IRQP2F(8) => IRQ_P2F_CAN0,
IRQP2F(7) => IRQ_P2F_USB1,
IRQP2F(6) => IRQ_P2F_ENET1,
IRQP2F(5) => IRQ_P2F_ENET_WAKE1,
IRQP2F(4) => IRQ_P2F_SDIO1,
IRQP2F(3) => IRQ_P2F_I2C1,
IRQP2F(2) => IRQ_P2F_SPI1,
IRQP2F(1) => IRQ_P2F_UART1,
IRQP2F(0) => IRQ_P2F_CAN1,
MAXIGP0ACLK => M_AXI_GP0_ACLK,
MAXIGP0ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0),
MAXIGP0ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0),
MAXIGP0ARCACHE(3 downto 2) => \^m_axi_gp0_arcache\(3 downto 2),
MAXIGP0ARCACHE(1) => NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED(1),
MAXIGP0ARCACHE(0) => \^m_axi_gp0_arcache\(0),
MAXIGP0ARESETN => M_AXI_GP0_ARESETN,
MAXIGP0ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0),
MAXIGP0ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0),
MAXIGP0ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0),
MAXIGP0ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0),
MAXIGP0ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0),
MAXIGP0ARREADY => M_AXI_GP0_ARREADY,
MAXIGP0ARSIZE(1 downto 0) => \^m_axi_gp0_arsize\(1 downto 0),
MAXIGP0ARVALID => M_AXI_GP0_ARVALID,
MAXIGP0AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0),
MAXIGP0AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0),
MAXIGP0AWCACHE(3 downto 2) => \^m_axi_gp0_awcache\(3 downto 2),
MAXIGP0AWCACHE(1) => NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED(1),
MAXIGP0AWCACHE(0) => \^m_axi_gp0_awcache\(0),
MAXIGP0AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0),
MAXIGP0AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0),
MAXIGP0AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0),
MAXIGP0AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0),
MAXIGP0AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0),
MAXIGP0AWREADY => M_AXI_GP0_AWREADY,
MAXIGP0AWSIZE(1 downto 0) => \^m_axi_gp0_awsize\(1 downto 0),
MAXIGP0AWVALID => M_AXI_GP0_AWVALID,
MAXIGP0BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0),
MAXIGP0BREADY => M_AXI_GP0_BREADY,
MAXIGP0BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0),
MAXIGP0BVALID => M_AXI_GP0_BVALID,
MAXIGP0RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0),
MAXIGP0RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0),
MAXIGP0RLAST => M_AXI_GP0_RLAST,
MAXIGP0RREADY => M_AXI_GP0_RREADY,
MAXIGP0RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0),
MAXIGP0RVALID => M_AXI_GP0_RVALID,
MAXIGP0WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0),
MAXIGP0WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0),
MAXIGP0WLAST => M_AXI_GP0_WLAST,
MAXIGP0WREADY => M_AXI_GP0_WREADY,
MAXIGP0WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0),
MAXIGP0WVALID => M_AXI_GP0_WVALID,
MAXIGP1ACLK => M_AXI_GP1_ACLK,
MAXIGP1ARADDR(31 downto 0) => M_AXI_GP1_ARADDR(31 downto 0),
MAXIGP1ARBURST(1 downto 0) => M_AXI_GP1_ARBURST(1 downto 0),
MAXIGP1ARCACHE(3 downto 2) => \^m_axi_gp1_arcache\(3 downto 2),
MAXIGP1ARCACHE(1) => NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED(1),
MAXIGP1ARCACHE(0) => \^m_axi_gp1_arcache\(0),
MAXIGP1ARESETN => M_AXI_GP1_ARESETN,
MAXIGP1ARID(11 downto 0) => M_AXI_GP1_ARID(11 downto 0),
MAXIGP1ARLEN(3 downto 0) => M_AXI_GP1_ARLEN(3 downto 0),
MAXIGP1ARLOCK(1 downto 0) => M_AXI_GP1_ARLOCK(1 downto 0),
MAXIGP1ARPROT(2 downto 0) => M_AXI_GP1_ARPROT(2 downto 0),
MAXIGP1ARQOS(3 downto 0) => M_AXI_GP1_ARQOS(3 downto 0),
MAXIGP1ARREADY => M_AXI_GP1_ARREADY,
MAXIGP1ARSIZE(1 downto 0) => \^m_axi_gp1_arsize\(1 downto 0),
MAXIGP1ARVALID => M_AXI_GP1_ARVALID,
MAXIGP1AWADDR(31 downto 0) => M_AXI_GP1_AWADDR(31 downto 0),
MAXIGP1AWBURST(1 downto 0) => M_AXI_GP1_AWBURST(1 downto 0),
MAXIGP1AWCACHE(3 downto 2) => \^m_axi_gp1_awcache\(3 downto 2),
MAXIGP1AWCACHE(1) => NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED(1),
MAXIGP1AWCACHE(0) => \^m_axi_gp1_awcache\(0),
MAXIGP1AWID(11 downto 0) => M_AXI_GP1_AWID(11 downto 0),
MAXIGP1AWLEN(3 downto 0) => M_AXI_GP1_AWLEN(3 downto 0),
MAXIGP1AWLOCK(1 downto 0) => M_AXI_GP1_AWLOCK(1 downto 0),
MAXIGP1AWPROT(2 downto 0) => M_AXI_GP1_AWPROT(2 downto 0),
MAXIGP1AWQOS(3 downto 0) => M_AXI_GP1_AWQOS(3 downto 0),
MAXIGP1AWREADY => M_AXI_GP1_AWREADY,
MAXIGP1AWSIZE(1 downto 0) => \^m_axi_gp1_awsize\(1 downto 0),
MAXIGP1AWVALID => M_AXI_GP1_AWVALID,
MAXIGP1BID(11 downto 0) => M_AXI_GP1_BID(11 downto 0),
MAXIGP1BREADY => M_AXI_GP1_BREADY,
MAXIGP1BRESP(1 downto 0) => M_AXI_GP1_BRESP(1 downto 0),
MAXIGP1BVALID => M_AXI_GP1_BVALID,
MAXIGP1RDATA(31 downto 0) => M_AXI_GP1_RDATA(31 downto 0),
MAXIGP1RID(11 downto 0) => M_AXI_GP1_RID(11 downto 0),
MAXIGP1RLAST => M_AXI_GP1_RLAST,
MAXIGP1RREADY => M_AXI_GP1_RREADY,
MAXIGP1RRESP(1 downto 0) => M_AXI_GP1_RRESP(1 downto 0),
MAXIGP1RVALID => M_AXI_GP1_RVALID,
MAXIGP1WDATA(31 downto 0) => M_AXI_GP1_WDATA(31 downto 0),
MAXIGP1WID(11 downto 0) => M_AXI_GP1_WID(11 downto 0),
MAXIGP1WLAST => M_AXI_GP1_WLAST,
MAXIGP1WREADY => M_AXI_GP1_WREADY,
MAXIGP1WSTRB(3 downto 0) => M_AXI_GP1_WSTRB(3 downto 0),
MAXIGP1WVALID => M_AXI_GP1_WVALID,
MIO(53 downto 0) => buffered_MIO(53 downto 0),
PSCLK => buffered_PS_CLK,
PSPORB => buffered_PS_PORB,
PSSRSTB => buffered_PS_SRSTB,
SAXIACPACLK => S_AXI_ACP_ACLK,
SAXIACPARADDR(31 downto 0) => S_AXI_ACP_ARADDR(31 downto 0),
SAXIACPARBURST(1 downto 0) => S_AXI_ACP_ARBURST(1 downto 0),
SAXIACPARCACHE(3 downto 0) => S_AXI_ACP_ARCACHE(3 downto 0),
SAXIACPARESETN => S_AXI_ACP_ARESETN,
SAXIACPARID(2 downto 0) => S_AXI_ACP_ARID(2 downto 0),
SAXIACPARLEN(3 downto 0) => S_AXI_ACP_ARLEN(3 downto 0),
SAXIACPARLOCK(1 downto 0) => S_AXI_ACP_ARLOCK(1 downto 0),
SAXIACPARPROT(2 downto 0) => S_AXI_ACP_ARPROT(2 downto 0),
SAXIACPARQOS(3 downto 0) => S_AXI_ACP_ARQOS(3 downto 0),
SAXIACPARREADY => S_AXI_ACP_ARREADY,
SAXIACPARSIZE(1 downto 0) => S_AXI_ACP_ARSIZE(1 downto 0),
SAXIACPARUSER(4 downto 0) => S_AXI_ACP_ARUSER(4 downto 0),
SAXIACPARVALID => S_AXI_ACP_ARVALID,
SAXIACPAWADDR(31 downto 0) => S_AXI_ACP_AWADDR(31 downto 0),
SAXIACPAWBURST(1 downto 0) => S_AXI_ACP_AWBURST(1 downto 0),
SAXIACPAWCACHE(3 downto 0) => S_AXI_ACP_AWCACHE(3 downto 0),
SAXIACPAWID(2 downto 0) => S_AXI_ACP_AWID(2 downto 0),
SAXIACPAWLEN(3 downto 0) => S_AXI_ACP_AWLEN(3 downto 0),
SAXIACPAWLOCK(1 downto 0) => S_AXI_ACP_AWLOCK(1 downto 0),
SAXIACPAWPROT(2 downto 0) => S_AXI_ACP_AWPROT(2 downto 0),
SAXIACPAWQOS(3 downto 0) => S_AXI_ACP_AWQOS(3 downto 0),
SAXIACPAWREADY => S_AXI_ACP_AWREADY,
SAXIACPAWSIZE(1 downto 0) => S_AXI_ACP_AWSIZE(1 downto 0),
SAXIACPAWUSER(4 downto 0) => S_AXI_ACP_AWUSER(4 downto 0),
SAXIACPAWVALID => S_AXI_ACP_AWVALID,
SAXIACPBID(2 downto 0) => S_AXI_ACP_BID(2 downto 0),
SAXIACPBREADY => S_AXI_ACP_BREADY,
SAXIACPBRESP(1 downto 0) => S_AXI_ACP_BRESP(1 downto 0),
SAXIACPBVALID => S_AXI_ACP_BVALID,
SAXIACPRDATA(63 downto 0) => S_AXI_ACP_RDATA(63 downto 0),
SAXIACPRID(2 downto 0) => S_AXI_ACP_RID(2 downto 0),
SAXIACPRLAST => S_AXI_ACP_RLAST,
SAXIACPRREADY => S_AXI_ACP_RREADY,
SAXIACPRRESP(1 downto 0) => S_AXI_ACP_RRESP(1 downto 0),
SAXIACPRVALID => S_AXI_ACP_RVALID,
SAXIACPWDATA(63 downto 0) => S_AXI_ACP_WDATA(63 downto 0),
SAXIACPWID(2 downto 0) => S_AXI_ACP_WID(2 downto 0),
SAXIACPWLAST => S_AXI_ACP_WLAST,
SAXIACPWREADY => S_AXI_ACP_WREADY,
SAXIACPWSTRB(7 downto 0) => S_AXI_ACP_WSTRB(7 downto 0),
SAXIACPWVALID => S_AXI_ACP_WVALID,
SAXIGP0ACLK => S_AXI_GP0_ACLK,
SAXIGP0ARADDR(31 downto 0) => S_AXI_GP0_ARADDR(31 downto 0),
SAXIGP0ARBURST(1 downto 0) => S_AXI_GP0_ARBURST(1 downto 0),
SAXIGP0ARCACHE(3 downto 0) => S_AXI_GP0_ARCACHE(3 downto 0),
SAXIGP0ARESETN => S_AXI_GP0_ARESETN,
SAXIGP0ARID(5 downto 0) => S_AXI_GP0_ARID(5 downto 0),
SAXIGP0ARLEN(3 downto 0) => S_AXI_GP0_ARLEN(3 downto 0),
SAXIGP0ARLOCK(1 downto 0) => S_AXI_GP0_ARLOCK(1 downto 0),
SAXIGP0ARPROT(2 downto 0) => S_AXI_GP0_ARPROT(2 downto 0),
SAXIGP0ARQOS(3 downto 0) => S_AXI_GP0_ARQOS(3 downto 0),
SAXIGP0ARREADY => S_AXI_GP0_ARREADY,
SAXIGP0ARSIZE(1 downto 0) => S_AXI_GP0_ARSIZE(1 downto 0),
SAXIGP0ARVALID => S_AXI_GP0_ARVALID,
SAXIGP0AWADDR(31 downto 0) => S_AXI_GP0_AWADDR(31 downto 0),
SAXIGP0AWBURST(1 downto 0) => S_AXI_GP0_AWBURST(1 downto 0),
SAXIGP0AWCACHE(3 downto 0) => S_AXI_GP0_AWCACHE(3 downto 0),
SAXIGP0AWID(5 downto 0) => S_AXI_GP0_AWID(5 downto 0),
SAXIGP0AWLEN(3 downto 0) => S_AXI_GP0_AWLEN(3 downto 0),
SAXIGP0AWLOCK(1 downto 0) => S_AXI_GP0_AWLOCK(1 downto 0),
SAXIGP0AWPROT(2 downto 0) => S_AXI_GP0_AWPROT(2 downto 0),
SAXIGP0AWQOS(3 downto 0) => S_AXI_GP0_AWQOS(3 downto 0),
SAXIGP0AWREADY => S_AXI_GP0_AWREADY,
SAXIGP0AWSIZE(1 downto 0) => S_AXI_GP0_AWSIZE(1 downto 0),
SAXIGP0AWVALID => S_AXI_GP0_AWVALID,
SAXIGP0BID(5 downto 0) => S_AXI_GP0_BID(5 downto 0),
SAXIGP0BREADY => S_AXI_GP0_BREADY,
SAXIGP0BRESP(1 downto 0) => S_AXI_GP0_BRESP(1 downto 0),
SAXIGP0BVALID => S_AXI_GP0_BVALID,
SAXIGP0RDATA(31 downto 0) => S_AXI_GP0_RDATA(31 downto 0),
SAXIGP0RID(5 downto 0) => S_AXI_GP0_RID(5 downto 0),
SAXIGP0RLAST => S_AXI_GP0_RLAST,
SAXIGP0RREADY => S_AXI_GP0_RREADY,
SAXIGP0RRESP(1 downto 0) => S_AXI_GP0_RRESP(1 downto 0),
SAXIGP0RVALID => S_AXI_GP0_RVALID,
SAXIGP0WDATA(31 downto 0) => S_AXI_GP0_WDATA(31 downto 0),
SAXIGP0WID(5 downto 0) => S_AXI_GP0_WID(5 downto 0),
SAXIGP0WLAST => S_AXI_GP0_WLAST,
SAXIGP0WREADY => S_AXI_GP0_WREADY,
SAXIGP0WSTRB(3 downto 0) => S_AXI_GP0_WSTRB(3 downto 0),
SAXIGP0WVALID => S_AXI_GP0_WVALID,
SAXIGP1ACLK => S_AXI_GP1_ACLK,
SAXIGP1ARADDR(31 downto 0) => S_AXI_GP1_ARADDR(31 downto 0),
SAXIGP1ARBURST(1 downto 0) => S_AXI_GP1_ARBURST(1 downto 0),
SAXIGP1ARCACHE(3 downto 0) => S_AXI_GP1_ARCACHE(3 downto 0),
SAXIGP1ARESETN => S_AXI_GP1_ARESETN,
SAXIGP1ARID(5 downto 0) => S_AXI_GP1_ARID(5 downto 0),
SAXIGP1ARLEN(3 downto 0) => S_AXI_GP1_ARLEN(3 downto 0),
SAXIGP1ARLOCK(1 downto 0) => S_AXI_GP1_ARLOCK(1 downto 0),
SAXIGP1ARPROT(2 downto 0) => S_AXI_GP1_ARPROT(2 downto 0),
SAXIGP1ARQOS(3 downto 0) => S_AXI_GP1_ARQOS(3 downto 0),
SAXIGP1ARREADY => S_AXI_GP1_ARREADY,
SAXIGP1ARSIZE(1 downto 0) => S_AXI_GP1_ARSIZE(1 downto 0),
SAXIGP1ARVALID => S_AXI_GP1_ARVALID,
SAXIGP1AWADDR(31 downto 0) => S_AXI_GP1_AWADDR(31 downto 0),
SAXIGP1AWBURST(1 downto 0) => S_AXI_GP1_AWBURST(1 downto 0),
SAXIGP1AWCACHE(3 downto 0) => S_AXI_GP1_AWCACHE(3 downto 0),
SAXIGP1AWID(5 downto 0) => S_AXI_GP1_AWID(5 downto 0),
SAXIGP1AWLEN(3 downto 0) => S_AXI_GP1_AWLEN(3 downto 0),
SAXIGP1AWLOCK(1 downto 0) => S_AXI_GP1_AWLOCK(1 downto 0),
SAXIGP1AWPROT(2 downto 0) => S_AXI_GP1_AWPROT(2 downto 0),
SAXIGP1AWQOS(3 downto 0) => S_AXI_GP1_AWQOS(3 downto 0),
SAXIGP1AWREADY => S_AXI_GP1_AWREADY,
SAXIGP1AWSIZE(1 downto 0) => S_AXI_GP1_AWSIZE(1 downto 0),
SAXIGP1AWVALID => S_AXI_GP1_AWVALID,
SAXIGP1BID(5 downto 0) => S_AXI_GP1_BID(5 downto 0),
SAXIGP1BREADY => S_AXI_GP1_BREADY,
SAXIGP1BRESP(1 downto 0) => S_AXI_GP1_BRESP(1 downto 0),
SAXIGP1BVALID => S_AXI_GP1_BVALID,
SAXIGP1RDATA(31 downto 0) => S_AXI_GP1_RDATA(31 downto 0),
SAXIGP1RID(5 downto 0) => S_AXI_GP1_RID(5 downto 0),
SAXIGP1RLAST => S_AXI_GP1_RLAST,
SAXIGP1RREADY => S_AXI_GP1_RREADY,
SAXIGP1RRESP(1 downto 0) => S_AXI_GP1_RRESP(1 downto 0),
SAXIGP1RVALID => S_AXI_GP1_RVALID,
SAXIGP1WDATA(31 downto 0) => S_AXI_GP1_WDATA(31 downto 0),
SAXIGP1WID(5 downto 0) => S_AXI_GP1_WID(5 downto 0),
SAXIGP1WLAST => S_AXI_GP1_WLAST,
SAXIGP1WREADY => S_AXI_GP1_WREADY,
SAXIGP1WSTRB(3 downto 0) => S_AXI_GP1_WSTRB(3 downto 0),
SAXIGP1WVALID => S_AXI_GP1_WVALID,
SAXIHP0ACLK => S_AXI_HP0_ACLK,
SAXIHP0ARADDR(31 downto 0) => S_AXI_HP0_ARADDR(31 downto 0),
SAXIHP0ARBURST(1 downto 0) => S_AXI_HP0_ARBURST(1 downto 0),
SAXIHP0ARCACHE(3 downto 0) => S_AXI_HP0_ARCACHE(3 downto 0),
SAXIHP0ARESETN => S_AXI_HP0_ARESETN,
SAXIHP0ARID(5 downto 0) => S_AXI_HP0_ARID(5 downto 0),
SAXIHP0ARLEN(3 downto 0) => S_AXI_HP0_ARLEN(3 downto 0),
SAXIHP0ARLOCK(1 downto 0) => S_AXI_HP0_ARLOCK(1 downto 0),
SAXIHP0ARPROT(2 downto 0) => S_AXI_HP0_ARPROT(2 downto 0),
SAXIHP0ARQOS(3 downto 0) => S_AXI_HP0_ARQOS(3 downto 0),
SAXIHP0ARREADY => S_AXI_HP0_ARREADY,
SAXIHP0ARSIZE(1 downto 0) => S_AXI_HP0_ARSIZE(1 downto 0),
SAXIHP0ARVALID => S_AXI_HP0_ARVALID,
SAXIHP0AWADDR(31 downto 0) => S_AXI_HP0_AWADDR(31 downto 0),
SAXIHP0AWBURST(1 downto 0) => S_AXI_HP0_AWBURST(1 downto 0),
SAXIHP0AWCACHE(3 downto 0) => S_AXI_HP0_AWCACHE(3 downto 0),
SAXIHP0AWID(5 downto 0) => S_AXI_HP0_AWID(5 downto 0),
SAXIHP0AWLEN(3 downto 0) => S_AXI_HP0_AWLEN(3 downto 0),
SAXIHP0AWLOCK(1 downto 0) => S_AXI_HP0_AWLOCK(1 downto 0),
SAXIHP0AWPROT(2 downto 0) => S_AXI_HP0_AWPROT(2 downto 0),
SAXIHP0AWQOS(3 downto 0) => S_AXI_HP0_AWQOS(3 downto 0),
SAXIHP0AWREADY => S_AXI_HP0_AWREADY,
SAXIHP0AWSIZE(1 downto 0) => S_AXI_HP0_AWSIZE(1 downto 0),
SAXIHP0AWVALID => S_AXI_HP0_AWVALID,
SAXIHP0BID(5 downto 0) => S_AXI_HP0_BID(5 downto 0),
SAXIHP0BREADY => S_AXI_HP0_BREADY,
SAXIHP0BRESP(1 downto 0) => S_AXI_HP0_BRESP(1 downto 0),
SAXIHP0BVALID => S_AXI_HP0_BVALID,
SAXIHP0RACOUNT(2 downto 0) => S_AXI_HP0_RACOUNT(2 downto 0),
SAXIHP0RCOUNT(7 downto 0) => S_AXI_HP0_RCOUNT(7 downto 0),
SAXIHP0RDATA(63 downto 0) => S_AXI_HP0_RDATA(63 downto 0),
SAXIHP0RDISSUECAP1EN => S_AXI_HP0_RDISSUECAP1_EN,
SAXIHP0RID(5 downto 0) => S_AXI_HP0_RID(5 downto 0),
SAXIHP0RLAST => S_AXI_HP0_RLAST,
SAXIHP0RREADY => S_AXI_HP0_RREADY,
SAXIHP0RRESP(1 downto 0) => S_AXI_HP0_RRESP(1 downto 0),
SAXIHP0RVALID => S_AXI_HP0_RVALID,
SAXIHP0WACOUNT(5 downto 0) => S_AXI_HP0_WACOUNT(5 downto 0),
SAXIHP0WCOUNT(7 downto 0) => S_AXI_HP0_WCOUNT(7 downto 0),
SAXIHP0WDATA(63 downto 0) => S_AXI_HP0_WDATA(63 downto 0),
SAXIHP0WID(5 downto 0) => S_AXI_HP0_WID(5 downto 0),
SAXIHP0WLAST => S_AXI_HP0_WLAST,
SAXIHP0WREADY => S_AXI_HP0_WREADY,
SAXIHP0WRISSUECAP1EN => S_AXI_HP0_WRISSUECAP1_EN,
SAXIHP0WSTRB(7 downto 0) => S_AXI_HP0_WSTRB(7 downto 0),
SAXIHP0WVALID => S_AXI_HP0_WVALID,
SAXIHP1ACLK => S_AXI_HP1_ACLK,
SAXIHP1ARADDR(31 downto 0) => S_AXI_HP1_ARADDR(31 downto 0),
SAXIHP1ARBURST(1 downto 0) => S_AXI_HP1_ARBURST(1 downto 0),
SAXIHP1ARCACHE(3 downto 0) => S_AXI_HP1_ARCACHE(3 downto 0),
SAXIHP1ARESETN => S_AXI_HP1_ARESETN,
SAXIHP1ARID(5 downto 0) => S_AXI_HP1_ARID(5 downto 0),
SAXIHP1ARLEN(3 downto 0) => S_AXI_HP1_ARLEN(3 downto 0),
SAXIHP1ARLOCK(1 downto 0) => S_AXI_HP1_ARLOCK(1 downto 0),
SAXIHP1ARPROT(2 downto 0) => S_AXI_HP1_ARPROT(2 downto 0),
SAXIHP1ARQOS(3 downto 0) => S_AXI_HP1_ARQOS(3 downto 0),
SAXIHP1ARREADY => S_AXI_HP1_ARREADY,
SAXIHP1ARSIZE(1 downto 0) => S_AXI_HP1_ARSIZE(1 downto 0),
SAXIHP1ARVALID => S_AXI_HP1_ARVALID,
SAXIHP1AWADDR(31 downto 0) => S_AXI_HP1_AWADDR(31 downto 0),
SAXIHP1AWBURST(1 downto 0) => S_AXI_HP1_AWBURST(1 downto 0),
SAXIHP1AWCACHE(3 downto 0) => S_AXI_HP1_AWCACHE(3 downto 0),
SAXIHP1AWID(5 downto 0) => S_AXI_HP1_AWID(5 downto 0),
SAXIHP1AWLEN(3 downto 0) => S_AXI_HP1_AWLEN(3 downto 0),
SAXIHP1AWLOCK(1 downto 0) => S_AXI_HP1_AWLOCK(1 downto 0),
SAXIHP1AWPROT(2 downto 0) => S_AXI_HP1_AWPROT(2 downto 0),
SAXIHP1AWQOS(3 downto 0) => S_AXI_HP1_AWQOS(3 downto 0),
SAXIHP1AWREADY => S_AXI_HP1_AWREADY,
SAXIHP1AWSIZE(1 downto 0) => S_AXI_HP1_AWSIZE(1 downto 0),
SAXIHP1AWVALID => S_AXI_HP1_AWVALID,
SAXIHP1BID(5 downto 0) => S_AXI_HP1_BID(5 downto 0),
SAXIHP1BREADY => S_AXI_HP1_BREADY,
SAXIHP1BRESP(1 downto 0) => S_AXI_HP1_BRESP(1 downto 0),
SAXIHP1BVALID => S_AXI_HP1_BVALID,
SAXIHP1RACOUNT(2 downto 0) => S_AXI_HP1_RACOUNT(2 downto 0),
SAXIHP1RCOUNT(7 downto 0) => S_AXI_HP1_RCOUNT(7 downto 0),
SAXIHP1RDATA(63 downto 0) => S_AXI_HP1_RDATA(63 downto 0),
SAXIHP1RDISSUECAP1EN => S_AXI_HP1_RDISSUECAP1_EN,
SAXIHP1RID(5 downto 0) => S_AXI_HP1_RID(5 downto 0),
SAXIHP1RLAST => S_AXI_HP1_RLAST,
SAXIHP1RREADY => S_AXI_HP1_RREADY,
SAXIHP1RRESP(1 downto 0) => S_AXI_HP1_RRESP(1 downto 0),
SAXIHP1RVALID => S_AXI_HP1_RVALID,
SAXIHP1WACOUNT(5 downto 0) => S_AXI_HP1_WACOUNT(5 downto 0),
SAXIHP1WCOUNT(7 downto 0) => S_AXI_HP1_WCOUNT(7 downto 0),
SAXIHP1WDATA(63 downto 0) => S_AXI_HP1_WDATA(63 downto 0),
SAXIHP1WID(5 downto 0) => S_AXI_HP1_WID(5 downto 0),
SAXIHP1WLAST => S_AXI_HP1_WLAST,
SAXIHP1WREADY => S_AXI_HP1_WREADY,
SAXIHP1WRISSUECAP1EN => S_AXI_HP1_WRISSUECAP1_EN,
SAXIHP1WSTRB(7 downto 0) => S_AXI_HP1_WSTRB(7 downto 0),
SAXIHP1WVALID => S_AXI_HP1_WVALID,
SAXIHP2ACLK => S_AXI_HP2_ACLK,
SAXIHP2ARADDR(31 downto 0) => S_AXI_HP2_ARADDR(31 downto 0),
SAXIHP2ARBURST(1 downto 0) => S_AXI_HP2_ARBURST(1 downto 0),
SAXIHP2ARCACHE(3 downto 0) => S_AXI_HP2_ARCACHE(3 downto 0),
SAXIHP2ARESETN => S_AXI_HP2_ARESETN,
SAXIHP2ARID(5 downto 0) => S_AXI_HP2_ARID(5 downto 0),
SAXIHP2ARLEN(3 downto 0) => S_AXI_HP2_ARLEN(3 downto 0),
SAXIHP2ARLOCK(1 downto 0) => S_AXI_HP2_ARLOCK(1 downto 0),
SAXIHP2ARPROT(2 downto 0) => S_AXI_HP2_ARPROT(2 downto 0),
SAXIHP2ARQOS(3 downto 0) => S_AXI_HP2_ARQOS(3 downto 0),
SAXIHP2ARREADY => S_AXI_HP2_ARREADY,
SAXIHP2ARSIZE(1 downto 0) => S_AXI_HP2_ARSIZE(1 downto 0),
SAXIHP2ARVALID => S_AXI_HP2_ARVALID,
SAXIHP2AWADDR(31 downto 0) => S_AXI_HP2_AWADDR(31 downto 0),
SAXIHP2AWBURST(1 downto 0) => S_AXI_HP2_AWBURST(1 downto 0),
SAXIHP2AWCACHE(3 downto 0) => S_AXI_HP2_AWCACHE(3 downto 0),
SAXIHP2AWID(5 downto 0) => S_AXI_HP2_AWID(5 downto 0),
SAXIHP2AWLEN(3 downto 0) => S_AXI_HP2_AWLEN(3 downto 0),
SAXIHP2AWLOCK(1 downto 0) => S_AXI_HP2_AWLOCK(1 downto 0),
SAXIHP2AWPROT(2 downto 0) => S_AXI_HP2_AWPROT(2 downto 0),
SAXIHP2AWQOS(3 downto 0) => S_AXI_HP2_AWQOS(3 downto 0),
SAXIHP2AWREADY => S_AXI_HP2_AWREADY,
SAXIHP2AWSIZE(1 downto 0) => S_AXI_HP2_AWSIZE(1 downto 0),
SAXIHP2AWVALID => S_AXI_HP2_AWVALID,
SAXIHP2BID(5 downto 0) => S_AXI_HP2_BID(5 downto 0),
SAXIHP2BREADY => S_AXI_HP2_BREADY,
SAXIHP2BRESP(1 downto 0) => S_AXI_HP2_BRESP(1 downto 0),
SAXIHP2BVALID => S_AXI_HP2_BVALID,
SAXIHP2RACOUNT(2 downto 0) => S_AXI_HP2_RACOUNT(2 downto 0),
SAXIHP2RCOUNT(7 downto 0) => S_AXI_HP2_RCOUNT(7 downto 0),
SAXIHP2RDATA(63 downto 0) => S_AXI_HP2_RDATA(63 downto 0),
SAXIHP2RDISSUECAP1EN => S_AXI_HP2_RDISSUECAP1_EN,
SAXIHP2RID(5 downto 0) => S_AXI_HP2_RID(5 downto 0),
SAXIHP2RLAST => S_AXI_HP2_RLAST,
SAXIHP2RREADY => S_AXI_HP2_RREADY,
SAXIHP2RRESP(1 downto 0) => S_AXI_HP2_RRESP(1 downto 0),
SAXIHP2RVALID => S_AXI_HP2_RVALID,
SAXIHP2WACOUNT(5 downto 0) => S_AXI_HP2_WACOUNT(5 downto 0),
SAXIHP2WCOUNT(7 downto 0) => S_AXI_HP2_WCOUNT(7 downto 0),
SAXIHP2WDATA(63 downto 0) => S_AXI_HP2_WDATA(63 downto 0),
SAXIHP2WID(5 downto 0) => S_AXI_HP2_WID(5 downto 0),
SAXIHP2WLAST => S_AXI_HP2_WLAST,
SAXIHP2WREADY => S_AXI_HP2_WREADY,
SAXIHP2WRISSUECAP1EN => S_AXI_HP2_WRISSUECAP1_EN,
SAXIHP2WSTRB(7 downto 0) => S_AXI_HP2_WSTRB(7 downto 0),
SAXIHP2WVALID => S_AXI_HP2_WVALID,
SAXIHP3ACLK => S_AXI_HP3_ACLK,
SAXIHP3ARADDR(31 downto 0) => S_AXI_HP3_ARADDR(31 downto 0),
SAXIHP3ARBURST(1 downto 0) => S_AXI_HP3_ARBURST(1 downto 0),
SAXIHP3ARCACHE(3 downto 0) => S_AXI_HP3_ARCACHE(3 downto 0),
SAXIHP3ARESETN => S_AXI_HP3_ARESETN,
SAXIHP3ARID(5 downto 0) => S_AXI_HP3_ARID(5 downto 0),
SAXIHP3ARLEN(3 downto 0) => S_AXI_HP3_ARLEN(3 downto 0),
SAXIHP3ARLOCK(1 downto 0) => S_AXI_HP3_ARLOCK(1 downto 0),
SAXIHP3ARPROT(2 downto 0) => S_AXI_HP3_ARPROT(2 downto 0),
SAXIHP3ARQOS(3 downto 0) => S_AXI_HP3_ARQOS(3 downto 0),
SAXIHP3ARREADY => S_AXI_HP3_ARREADY,
SAXIHP3ARSIZE(1 downto 0) => S_AXI_HP3_ARSIZE(1 downto 0),
SAXIHP3ARVALID => S_AXI_HP3_ARVALID,
SAXIHP3AWADDR(31 downto 0) => S_AXI_HP3_AWADDR(31 downto 0),
SAXIHP3AWBURST(1 downto 0) => S_AXI_HP3_AWBURST(1 downto 0),
SAXIHP3AWCACHE(3 downto 0) => S_AXI_HP3_AWCACHE(3 downto 0),
SAXIHP3AWID(5 downto 0) => S_AXI_HP3_AWID(5 downto 0),
SAXIHP3AWLEN(3 downto 0) => S_AXI_HP3_AWLEN(3 downto 0),
SAXIHP3AWLOCK(1 downto 0) => S_AXI_HP3_AWLOCK(1 downto 0),
SAXIHP3AWPROT(2 downto 0) => S_AXI_HP3_AWPROT(2 downto 0),
SAXIHP3AWQOS(3 downto 0) => S_AXI_HP3_AWQOS(3 downto 0),
SAXIHP3AWREADY => S_AXI_HP3_AWREADY,
SAXIHP3AWSIZE(1 downto 0) => S_AXI_HP3_AWSIZE(1 downto 0),
SAXIHP3AWVALID => S_AXI_HP3_AWVALID,
SAXIHP3BID(5 downto 0) => S_AXI_HP3_BID(5 downto 0),
SAXIHP3BREADY => S_AXI_HP3_BREADY,
SAXIHP3BRESP(1 downto 0) => S_AXI_HP3_BRESP(1 downto 0),
SAXIHP3BVALID => S_AXI_HP3_BVALID,
SAXIHP3RACOUNT(2 downto 0) => S_AXI_HP3_RACOUNT(2 downto 0),
SAXIHP3RCOUNT(7 downto 0) => S_AXI_HP3_RCOUNT(7 downto 0),
SAXIHP3RDATA(63 downto 0) => S_AXI_HP3_RDATA(63 downto 0),
SAXIHP3RDISSUECAP1EN => S_AXI_HP3_RDISSUECAP1_EN,
SAXIHP3RID(5 downto 0) => S_AXI_HP3_RID(5 downto 0),
SAXIHP3RLAST => S_AXI_HP3_RLAST,
SAXIHP3RREADY => S_AXI_HP3_RREADY,
SAXIHP3RRESP(1 downto 0) => S_AXI_HP3_RRESP(1 downto 0),
SAXIHP3RVALID => S_AXI_HP3_RVALID,
SAXIHP3WACOUNT(5 downto 0) => S_AXI_HP3_WACOUNT(5 downto 0),
SAXIHP3WCOUNT(7 downto 0) => S_AXI_HP3_WCOUNT(7 downto 0),
SAXIHP3WDATA(63 downto 0) => S_AXI_HP3_WDATA(63 downto 0),
SAXIHP3WID(5 downto 0) => S_AXI_HP3_WID(5 downto 0),
SAXIHP3WLAST => S_AXI_HP3_WLAST,
SAXIHP3WREADY => S_AXI_HP3_WREADY,
SAXIHP3WRISSUECAP1EN => S_AXI_HP3_WRISSUECAP1_EN,
SAXIHP3WSTRB(7 downto 0) => S_AXI_HP3_WSTRB(7 downto 0),
SAXIHP3WVALID => S_AXI_HP3_WVALID
);
PS_CLK_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_CLK,
PAD => PS_CLK
);
PS_PORB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_PORB,
PAD => PS_PORB
);
PS_SRSTB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_SRSTB,
PAD => PS_SRSTB
);
SDIO0_CMD_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_CMD_T_n,
O => SDIO0_CMD_T
);
\SDIO0_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(0),
O => SDIO0_DATA_T(0)
);
\SDIO0_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(1),
O => SDIO0_DATA_T(1)
);
\SDIO0_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(2),
O => SDIO0_DATA_T(2)
);
\SDIO0_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(3),
O => SDIO0_DATA_T(3)
);
SDIO1_CMD_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_CMD_T_n,
O => SDIO1_CMD_T
);
\SDIO1_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(0),
O => SDIO1_DATA_T(0)
);
\SDIO1_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(1),
O => SDIO1_DATA_T(1)
);
\SDIO1_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(2),
O => SDIO1_DATA_T(2)
);
\SDIO1_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(3),
O => SDIO1_DATA_T(3)
);
SPI0_MISO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_MISO_T_n,
O => SPI0_MISO_T
);
SPI0_MOSI_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_MOSI_T_n,
O => SPI0_MOSI_T
);
SPI0_SCLK_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_SCLK_T_n,
O => SPI0_SCLK_T
);
SPI0_SS_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_SS_T_n,
O => SPI0_SS_T
);
SPI1_MISO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_MISO_T_n,
O => SPI1_MISO_T
);
SPI1_MOSI_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_MOSI_T_n,
O => SPI1_MOSI_T
);
SPI1_SCLK_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_SCLK_T_n,
O => SPI1_SCLK_T
);
SPI1_SS_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_SS_T_n,
O => SPI1_SS_T
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
\buffer_fclk_clk_0.FCLK_CLK_0_BUFG\: unisim.vcomponents.BUFG
port map (
I => FCLK_CLK_unbuffered(0),
O => FCLK_CLK0
);
\genblk13[0].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(0),
PAD => MIO(0)
);
\genblk13[10].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(10),
PAD => MIO(10)
);
\genblk13[11].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(11),
PAD => MIO(11)
);
\genblk13[12].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(12),
PAD => MIO(12)
);
\genblk13[13].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(13),
PAD => MIO(13)
);
\genblk13[14].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(14),
PAD => MIO(14)
);
\genblk13[15].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(15),
PAD => MIO(15)
);
\genblk13[16].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(16),
PAD => MIO(16)
);
\genblk13[17].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(17),
PAD => MIO(17)
);
\genblk13[18].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(18),
PAD => MIO(18)
);
\genblk13[19].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(19),
PAD => MIO(19)
);
\genblk13[1].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(1),
PAD => MIO(1)
);
\genblk13[20].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(20),
PAD => MIO(20)
);
\genblk13[21].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(21),
PAD => MIO(21)
);
\genblk13[22].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(22),
PAD => MIO(22)
);
\genblk13[23].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(23),
PAD => MIO(23)
);
\genblk13[24].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(24),
PAD => MIO(24)
);
\genblk13[25].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(25),
PAD => MIO(25)
);
\genblk13[26].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(26),
PAD => MIO(26)
);
\genblk13[27].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(27),
PAD => MIO(27)
);
\genblk13[28].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(28),
PAD => MIO(28)
);
\genblk13[29].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(29),
PAD => MIO(29)
);
\genblk13[2].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(2),
PAD => MIO(2)
);
\genblk13[30].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(30),
PAD => MIO(30)
);
\genblk13[31].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(31),
PAD => MIO(31)
);
\genblk13[32].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(32),
PAD => MIO(32)
);
\genblk13[33].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(33),
PAD => MIO(33)
);
\genblk13[34].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(34),
PAD => MIO(34)
);
\genblk13[35].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(35),
PAD => MIO(35)
);
\genblk13[36].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(36),
PAD => MIO(36)
);
\genblk13[37].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(37),
PAD => MIO(37)
);
\genblk13[38].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(38),
PAD => MIO(38)
);
\genblk13[39].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(39),
PAD => MIO(39)
);
\genblk13[3].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(3),
PAD => MIO(3)
);
\genblk13[40].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(40),
PAD => MIO(40)
);
\genblk13[41].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(41),
PAD => MIO(41)
);
\genblk13[42].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(42),
PAD => MIO(42)
);
\genblk13[43].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(43),
PAD => MIO(43)
);
\genblk13[44].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(44),
PAD => MIO(44)
);
\genblk13[45].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(45),
PAD => MIO(45)
);
\genblk13[46].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(46),
PAD => MIO(46)
);
\genblk13[47].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(47),
PAD => MIO(47)
);
\genblk13[48].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(48),
PAD => MIO(48)
);
\genblk13[49].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(49),
PAD => MIO(49)
);
\genblk13[4].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(4),
PAD => MIO(4)
);
\genblk13[50].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(50),
PAD => MIO(50)
);
\genblk13[51].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(51),
PAD => MIO(51)
);
\genblk13[52].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(52),
PAD => MIO(52)
);
\genblk13[53].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(53),
PAD => MIO(53)
);
\genblk13[5].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(5),
PAD => MIO(5)
);
\genblk13[6].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(6),
PAD => MIO(6)
);
\genblk13[7].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(7),
PAD => MIO(7)
);
\genblk13[8].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(8),
PAD => MIO(8)
);
\genblk13[9].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(9),
PAD => MIO(9)
);
\genblk14[0].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(0),
PAD => DDR_BankAddr(0)
);
\genblk14[1].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(1),
PAD => DDR_BankAddr(1)
);
\genblk14[2].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(2),
PAD => DDR_BankAddr(2)
);
\genblk15[0].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(0),
PAD => DDR_Addr(0)
);
\genblk15[10].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(10),
PAD => DDR_Addr(10)
);
\genblk15[11].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(11),
PAD => DDR_Addr(11)
);
\genblk15[12].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(12),
PAD => DDR_Addr(12)
);
\genblk15[13].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(13),
PAD => DDR_Addr(13)
);
\genblk15[14].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(14),
PAD => DDR_Addr(14)
);
\genblk15[1].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(1),
PAD => DDR_Addr(1)
);
\genblk15[2].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(2),
PAD => DDR_Addr(2)
);
\genblk15[3].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(3),
PAD => DDR_Addr(3)
);
\genblk15[4].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(4),
PAD => DDR_Addr(4)
);
\genblk15[5].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(5),
PAD => DDR_Addr(5)
);
\genblk15[6].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(6),
PAD => DDR_Addr(6)
);
\genblk15[7].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(7),
PAD => DDR_Addr(7)
);
\genblk15[8].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(8),
PAD => DDR_Addr(8)
);
\genblk15[9].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(9),
PAD => DDR_Addr(9)
);
\genblk16[0].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(0),
PAD => DDR_DM(0)
);
\genblk16[1].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(1),
PAD => DDR_DM(1)
);
\genblk16[2].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(2),
PAD => DDR_DM(2)
);
\genblk16[3].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(3),
PAD => DDR_DM(3)
);
\genblk17[0].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(0),
PAD => DDR_DQ(0)
);
\genblk17[10].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(10),
PAD => DDR_DQ(10)
);
\genblk17[11].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(11),
PAD => DDR_DQ(11)
);
\genblk17[12].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(12),
PAD => DDR_DQ(12)
);
\genblk17[13].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(13),
PAD => DDR_DQ(13)
);
\genblk17[14].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(14),
PAD => DDR_DQ(14)
);
\genblk17[15].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(15),
PAD => DDR_DQ(15)
);
\genblk17[16].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(16),
PAD => DDR_DQ(16)
);
\genblk17[17].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(17),
PAD => DDR_DQ(17)
);
\genblk17[18].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(18),
PAD => DDR_DQ(18)
);
\genblk17[19].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(19),
PAD => DDR_DQ(19)
);
\genblk17[1].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(1),
PAD => DDR_DQ(1)
);
\genblk17[20].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(20),
PAD => DDR_DQ(20)
);
\genblk17[21].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(21),
PAD => DDR_DQ(21)
);
\genblk17[22].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(22),
PAD => DDR_DQ(22)
);
\genblk17[23].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(23),
PAD => DDR_DQ(23)
);
\genblk17[24].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(24),
PAD => DDR_DQ(24)
);
\genblk17[25].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(25),
PAD => DDR_DQ(25)
);
\genblk17[26].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(26),
PAD => DDR_DQ(26)
);
\genblk17[27].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(27),
PAD => DDR_DQ(27)
);
\genblk17[28].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(28),
PAD => DDR_DQ(28)
);
\genblk17[29].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(29),
PAD => DDR_DQ(29)
);
\genblk17[2].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(2),
PAD => DDR_DQ(2)
);
\genblk17[30].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(30),
PAD => DDR_DQ(30)
);
\genblk17[31].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(31),
PAD => DDR_DQ(31)
);
\genblk17[3].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(3),
PAD => DDR_DQ(3)
);
\genblk17[4].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(4),
PAD => DDR_DQ(4)
);
\genblk17[5].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(5),
PAD => DDR_DQ(5)
);
\genblk17[6].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(6),
PAD => DDR_DQ(6)
);
\genblk17[7].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(7),
PAD => DDR_DQ(7)
);
\genblk17[8].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(8),
PAD => DDR_DQ(8)
);
\genblk17[9].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(9),
PAD => DDR_DQ(9)
);
\genblk18[0].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(0),
PAD => DDR_DQS_n(0)
);
\genblk18[1].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(1),
PAD => DDR_DQS_n(1)
);
\genblk18[2].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(2),
PAD => DDR_DQS_n(2)
);
\genblk18[3].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(3),
PAD => DDR_DQS_n(3)
);
\genblk19[0].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(0),
PAD => DDR_DQS(0)
);
\genblk19[1].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(1),
PAD => DDR_DQS(1)
);
\genblk19[2].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(2),
PAD => DDR_DQS(2)
);
\genblk19[3].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(3),
PAD => DDR_DQS(3)
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[0]\
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[0]\(1)
);
i_10: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[7]\(1)
);
i_11: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[7]\(0)
);
i_12: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[6]\(1)
);
i_13: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[6]\(0)
);
i_14: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[5]\(1)
);
i_15: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[5]\(0)
);
i_16: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[4]\(1)
);
i_17: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[4]\(0)
);
i_18: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[3]\(1)
);
i_19: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[3]\(0)
);
i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[0]\(0)
);
i_20: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[2]\(1)
);
i_21: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[2]\(0)
);
i_22: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[1]\(1)
);
i_23: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[1]\(0)
);
i_3: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[7]\
);
i_4: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[6]\
);
i_5: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[5]\
);
i_6: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[4]\
);
i_7: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[3]\
);
i_8: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[2]\
);
i_9: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[1]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
IRQ_F2P : in STD_LOGIC_VECTOR ( 1 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "zqynq_lab_1_design_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "processing_system7_v5_5_processing_system7,Vivado 2017.2.1";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_inst_CAN0_PHY_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_CAN1_PHY_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_MDC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_MDC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_EVENT_EVENTO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET1_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET2_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET3_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SCL_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SCL_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SDA_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SDA_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SCL_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SCL_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SDA_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SDA_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CAN0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CAN1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CTI_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_GPIO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_I2C0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_I2C1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_QSPI_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SMC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SPI0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SPI1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_UART0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_UART1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_USB0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_USB1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_PJTAG_TDO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_BUSPOW_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CLK_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CMD_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CMD_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_LED_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_BUSPOW_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CLK_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CMD_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CMD_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_LED_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MISO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MISO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MOSI_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MOSI_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SCLK_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SCLK_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS1_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS2_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MISO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MISO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MOSI_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MOSI_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SCLK_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SCLK_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS1_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS2_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TRACE_CLK_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TRACE_CTL_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_DTRN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_RTSN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_DTRN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_RTSN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_WDT_RST_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA1_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA2_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA3_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_ENET0_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_ENET1_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_EVENT_STANDBYWFE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_EVENT_STANDBYWFI_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_GPIO_O_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_GPIO_T_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO0_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_SDIO0_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO0_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO1_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_SDIO1_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO1_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_S_AXI_ACP_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_ACP_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_GP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_GP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP2_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP2_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP3_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP3_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_TRACE_DATA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_USB1_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_DM_WIDTH : integer;
attribute C_DM_WIDTH of inst : label is 4;
attribute C_DQS_WIDTH : integer;
attribute C_DQS_WIDTH of inst : label is 4;
attribute C_DQ_WIDTH : integer;
attribute C_DQ_WIDTH of inst : label is 32;
attribute C_EMIO_GPIO_WIDTH : integer;
attribute C_EMIO_GPIO_WIDTH of inst : label is 64;
attribute C_EN_EMIO_ENET0 : integer;
attribute C_EN_EMIO_ENET0 of inst : label is 0;
attribute C_EN_EMIO_ENET1 : integer;
attribute C_EN_EMIO_ENET1 of inst : label is 0;
attribute C_EN_EMIO_PJTAG : integer;
attribute C_EN_EMIO_PJTAG of inst : label is 0;
attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of inst : label is 0;
attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of inst : label is "TRUE";
attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of inst : label is "FALSE";
attribute C_FCLK_CLK2_BUF : string;
attribute C_FCLK_CLK2_BUF of inst : label is "FALSE";
attribute C_FCLK_CLK3_BUF : string;
attribute C_FCLK_CLK3_BUF of inst : label is "FALSE";
attribute C_GP0_EN_MODIFIABLE_TXN : integer;
attribute C_GP0_EN_MODIFIABLE_TXN of inst : label is 1;
attribute C_GP1_EN_MODIFIABLE_TXN : integer;
attribute C_GP1_EN_MODIFIABLE_TXN of inst : label is 1;
attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
attribute C_INCLUDE_ACP_TRANS_CHECK of inst : label is 0;
attribute C_INCLUDE_TRACE_BUFFER : integer;
attribute C_INCLUDE_TRACE_BUFFER of inst : label is 0;
attribute C_IRQ_F2P_MODE : string;
attribute C_IRQ_F2P_MODE of inst : label is "DIRECT";
attribute C_MIO_PRIMITIVE : integer;
attribute C_MIO_PRIMITIVE of inst : label is 54;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of inst : label is 0;
attribute C_M_AXI_GP0_ID_WIDTH : integer;
attribute C_M_AXI_GP0_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of inst : label is 0;
attribute C_M_AXI_GP1_ID_WIDTH : integer;
attribute C_M_AXI_GP1_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of inst : label is 12;
attribute C_NUM_F2P_INTR_INPUTS : integer;
attribute C_NUM_F2P_INTR_INPUTS of inst : label is 2;
attribute C_PACKAGE_NAME : string;
attribute C_PACKAGE_NAME of inst : label is "clg484";
attribute C_PS7_SI_REV : string;
attribute C_PS7_SI_REV of inst : label is "PRODUCTION";
attribute C_S_AXI_ACP_ARUSER_VAL : integer;
attribute C_S_AXI_ACP_ARUSER_VAL of inst : label is 31;
attribute C_S_AXI_ACP_AWUSER_VAL : integer;
attribute C_S_AXI_ACP_AWUSER_VAL of inst : label is 31;
attribute C_S_AXI_ACP_ID_WIDTH : integer;
attribute C_S_AXI_ACP_ID_WIDTH of inst : label is 3;
attribute C_S_AXI_GP0_ID_WIDTH : integer;
attribute C_S_AXI_GP0_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_GP1_ID_WIDTH : integer;
attribute C_S_AXI_GP1_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP0_DATA_WIDTH : integer;
attribute C_S_AXI_HP0_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP0_ID_WIDTH : integer;
attribute C_S_AXI_HP0_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP1_DATA_WIDTH : integer;
attribute C_S_AXI_HP1_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP1_ID_WIDTH : integer;
attribute C_S_AXI_HP1_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP2_DATA_WIDTH : integer;
attribute C_S_AXI_HP2_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP2_ID_WIDTH : integer;
attribute C_S_AXI_HP2_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP3_DATA_WIDTH : integer;
attribute C_S_AXI_HP3_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP3_ID_WIDTH : integer;
attribute C_S_AXI_HP3_ID_WIDTH of inst : label is 6;
attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
attribute C_TRACE_BUFFER_CLOCK_DELAY of inst : label is 12;
attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
attribute C_TRACE_BUFFER_FIFO_SIZE of inst : label is 128;
attribute C_TRACE_INTERNAL_WIDTH : integer;
attribute C_TRACE_INTERNAL_WIDTH of inst : label is 2;
attribute C_TRACE_PIPELINE_WIDTH : integer;
attribute C_TRACE_PIPELINE_WIDTH of inst : label is 8;
attribute C_USE_AXI_NONSECURE : integer;
attribute C_USE_AXI_NONSECURE of inst : label is 0;
attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
attribute C_USE_DEFAULT_ACP_USER_VAL of inst : label is 0;
attribute C_USE_M_AXI_GP0 : integer;
attribute C_USE_M_AXI_GP0 of inst : label is 1;
attribute C_USE_M_AXI_GP1 : integer;
attribute C_USE_M_AXI_GP1 of inst : label is 0;
attribute C_USE_S_AXI_ACP : integer;
attribute C_USE_S_AXI_ACP of inst : label is 0;
attribute C_USE_S_AXI_GP0 : integer;
attribute C_USE_S_AXI_GP0 of inst : label is 0;
attribute C_USE_S_AXI_GP1 : integer;
attribute C_USE_S_AXI_GP1 of inst : label is 0;
attribute C_USE_S_AXI_HP0 : integer;
attribute C_USE_S_AXI_HP0 of inst : label is 0;
attribute C_USE_S_AXI_HP1 : integer;
attribute C_USE_S_AXI_HP1 of inst : label is 0;
attribute C_USE_S_AXI_HP2 : integer;
attribute C_USE_S_AXI_HP2 of inst : label is 0;
attribute C_USE_S_AXI_HP3 : integer;
attribute C_USE_S_AXI_HP3 of inst : label is 0;
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of inst : label is "zqynq_lab_1_design_processing_system7_0_0.hwdef";
attribute POWER : string;
attribute POWER of inst : label is "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of inst : label is 0;
begin
inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7
port map (
CAN0_PHY_RX => '0',
CAN0_PHY_TX => NLW_inst_CAN0_PHY_TX_UNCONNECTED,
CAN1_PHY_RX => '0',
CAN1_PHY_TX => NLW_inst_CAN1_PHY_TX_UNCONNECTED,
Core0_nFIQ => '0',
Core0_nIRQ => '0',
Core1_nFIQ => '0',
Core1_nIRQ => '0',
DDR_ARB(3 downto 0) => B"0000",
DDR_Addr(14 downto 0) => DDR_Addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_BankAddr(2 downto 0),
DDR_CAS_n => DDR_CAS_n,
DDR_CKE => DDR_CKE,
DDR_CS_n => DDR_CS_n,
DDR_Clk => DDR_Clk,
DDR_Clk_n => DDR_Clk_n,
DDR_DM(3 downto 0) => DDR_DM(3 downto 0),
DDR_DQ(31 downto 0) => DDR_DQ(31 downto 0),
DDR_DQS(3 downto 0) => DDR_DQS(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_DQS_n(3 downto 0),
DDR_DRSTB => DDR_DRSTB,
DDR_ODT => DDR_ODT,
DDR_RAS_n => DDR_RAS_n,
DDR_VRN => DDR_VRN,
DDR_VRP => DDR_VRP,
DDR_WEB => DDR_WEB,
DMA0_ACLK => '0',
DMA0_DAREADY => '0',
DMA0_DATYPE(1 downto 0) => NLW_inst_DMA0_DATYPE_UNCONNECTED(1 downto 0),
DMA0_DAVALID => NLW_inst_DMA0_DAVALID_UNCONNECTED,
DMA0_DRLAST => '0',
DMA0_DRREADY => NLW_inst_DMA0_DRREADY_UNCONNECTED,
DMA0_DRTYPE(1 downto 0) => B"00",
DMA0_DRVALID => '0',
DMA0_RSTN => NLW_inst_DMA0_RSTN_UNCONNECTED,
DMA1_ACLK => '0',
DMA1_DAREADY => '0',
DMA1_DATYPE(1 downto 0) => NLW_inst_DMA1_DATYPE_UNCONNECTED(1 downto 0),
DMA1_DAVALID => NLW_inst_DMA1_DAVALID_UNCONNECTED,
DMA1_DRLAST => '0',
DMA1_DRREADY => NLW_inst_DMA1_DRREADY_UNCONNECTED,
DMA1_DRTYPE(1 downto 0) => B"00",
DMA1_DRVALID => '0',
DMA1_RSTN => NLW_inst_DMA1_RSTN_UNCONNECTED,
DMA2_ACLK => '0',
DMA2_DAREADY => '0',
DMA2_DATYPE(1 downto 0) => NLW_inst_DMA2_DATYPE_UNCONNECTED(1 downto 0),
DMA2_DAVALID => NLW_inst_DMA2_DAVALID_UNCONNECTED,
DMA2_DRLAST => '0',
DMA2_DRREADY => NLW_inst_DMA2_DRREADY_UNCONNECTED,
DMA2_DRTYPE(1 downto 0) => B"00",
DMA2_DRVALID => '0',
DMA2_RSTN => NLW_inst_DMA2_RSTN_UNCONNECTED,
DMA3_ACLK => '0',
DMA3_DAREADY => '0',
DMA3_DATYPE(1 downto 0) => NLW_inst_DMA3_DATYPE_UNCONNECTED(1 downto 0),
DMA3_DAVALID => NLW_inst_DMA3_DAVALID_UNCONNECTED,
DMA3_DRLAST => '0',
DMA3_DRREADY => NLW_inst_DMA3_DRREADY_UNCONNECTED,
DMA3_DRTYPE(1 downto 0) => B"00",
DMA3_DRVALID => '0',
DMA3_RSTN => NLW_inst_DMA3_RSTN_UNCONNECTED,
ENET0_EXT_INTIN => '0',
ENET0_GMII_COL => '0',
ENET0_GMII_CRS => '0',
ENET0_GMII_RXD(7 downto 0) => B"00000000",
ENET0_GMII_RX_CLK => '0',
ENET0_GMII_RX_DV => '0',
ENET0_GMII_RX_ER => '0',
ENET0_GMII_TXD(7 downto 0) => NLW_inst_ENET0_GMII_TXD_UNCONNECTED(7 downto 0),
ENET0_GMII_TX_CLK => '0',
ENET0_GMII_TX_EN => NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED,
ENET0_GMII_TX_ER => NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED,
ENET0_MDIO_I => '0',
ENET0_MDIO_MDC => NLW_inst_ENET0_MDIO_MDC_UNCONNECTED,
ENET0_MDIO_O => NLW_inst_ENET0_MDIO_O_UNCONNECTED,
ENET0_MDIO_T => NLW_inst_ENET0_MDIO_T_UNCONNECTED,
ENET0_PTP_DELAY_REQ_RX => NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_DELAY_REQ_TX => NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_RX => NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_TX => NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_RX => NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_TX => NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_RX => NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_TX => NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET0_SOF_RX => NLW_inst_ENET0_SOF_RX_UNCONNECTED,
ENET0_SOF_TX => NLW_inst_ENET0_SOF_TX_UNCONNECTED,
ENET1_EXT_INTIN => '0',
ENET1_GMII_COL => '0',
ENET1_GMII_CRS => '0',
ENET1_GMII_RXD(7 downto 0) => B"00000000",
ENET1_GMII_RX_CLK => '0',
ENET1_GMII_RX_DV => '0',
ENET1_GMII_RX_ER => '0',
ENET1_GMII_TXD(7 downto 0) => NLW_inst_ENET1_GMII_TXD_UNCONNECTED(7 downto 0),
ENET1_GMII_TX_CLK => '0',
ENET1_GMII_TX_EN => NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED,
ENET1_GMII_TX_ER => NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED,
ENET1_MDIO_I => '0',
ENET1_MDIO_MDC => NLW_inst_ENET1_MDIO_MDC_UNCONNECTED,
ENET1_MDIO_O => NLW_inst_ENET1_MDIO_O_UNCONNECTED,
ENET1_MDIO_T => NLW_inst_ENET1_MDIO_T_UNCONNECTED,
ENET1_PTP_DELAY_REQ_RX => NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET1_PTP_DELAY_REQ_TX => NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET1_PTP_PDELAY_REQ_RX => NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET1_PTP_PDELAY_REQ_TX => NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET1_PTP_PDELAY_RESP_RX => NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET1_PTP_PDELAY_RESP_TX => NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET1_PTP_SYNC_FRAME_RX => NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET1_PTP_SYNC_FRAME_TX => NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET1_SOF_RX => NLW_inst_ENET1_SOF_RX_UNCONNECTED,
ENET1_SOF_TX => NLW_inst_ENET1_SOF_TX_UNCONNECTED,
EVENT_EVENTI => '0',
EVENT_EVENTO => NLW_inst_EVENT_EVENTO_UNCONNECTED,
EVENT_STANDBYWFE(1 downto 0) => NLW_inst_EVENT_STANDBYWFE_UNCONNECTED(1 downto 0),
EVENT_STANDBYWFI(1 downto 0) => NLW_inst_EVENT_STANDBYWFI_UNCONNECTED(1 downto 0),
FCLK_CLK0 => FCLK_CLK0,
FCLK_CLK1 => NLW_inst_FCLK_CLK1_UNCONNECTED,
FCLK_CLK2 => NLW_inst_FCLK_CLK2_UNCONNECTED,
FCLK_CLK3 => NLW_inst_FCLK_CLK3_UNCONNECTED,
FCLK_CLKTRIG0_N => '0',
FCLK_CLKTRIG1_N => '0',
FCLK_CLKTRIG2_N => '0',
FCLK_CLKTRIG3_N => '0',
FCLK_RESET0_N => FCLK_RESET0_N,
FCLK_RESET1_N => NLW_inst_FCLK_RESET1_N_UNCONNECTED,
FCLK_RESET2_N => NLW_inst_FCLK_RESET2_N_UNCONNECTED,
FCLK_RESET3_N => NLW_inst_FCLK_RESET3_N_UNCONNECTED,
FPGA_IDLE_N => '0',
FTMD_TRACEIN_ATID(3 downto 0) => B"0000",
FTMD_TRACEIN_CLK => '0',
FTMD_TRACEIN_DATA(31 downto 0) => B"00000000000000000000000000000000",
FTMD_TRACEIN_VALID => '0',
FTMT_F2P_DEBUG(31 downto 0) => B"00000000000000000000000000000000",
FTMT_F2P_TRIGACK_0 => NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED,
FTMT_F2P_TRIGACK_1 => NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED,
FTMT_F2P_TRIGACK_2 => NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED,
FTMT_F2P_TRIGACK_3 => NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED,
FTMT_F2P_TRIG_0 => '0',
FTMT_F2P_TRIG_1 => '0',
FTMT_F2P_TRIG_2 => '0',
FTMT_F2P_TRIG_3 => '0',
FTMT_P2F_DEBUG(31 downto 0) => NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED(31 downto 0),
FTMT_P2F_TRIGACK_0 => '0',
FTMT_P2F_TRIGACK_1 => '0',
FTMT_P2F_TRIGACK_2 => '0',
FTMT_P2F_TRIGACK_3 => '0',
FTMT_P2F_TRIG_0 => NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED,
FTMT_P2F_TRIG_1 => NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED,
FTMT_P2F_TRIG_2 => NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED,
FTMT_P2F_TRIG_3 => NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED,
GPIO_I(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
GPIO_O(63 downto 0) => NLW_inst_GPIO_O_UNCONNECTED(63 downto 0),
GPIO_T(63 downto 0) => NLW_inst_GPIO_T_UNCONNECTED(63 downto 0),
I2C0_SCL_I => '0',
I2C0_SCL_O => NLW_inst_I2C0_SCL_O_UNCONNECTED,
I2C0_SCL_T => NLW_inst_I2C0_SCL_T_UNCONNECTED,
I2C0_SDA_I => '0',
I2C0_SDA_O => NLW_inst_I2C0_SDA_O_UNCONNECTED,
I2C0_SDA_T => NLW_inst_I2C0_SDA_T_UNCONNECTED,
I2C1_SCL_I => '0',
I2C1_SCL_O => NLW_inst_I2C1_SCL_O_UNCONNECTED,
I2C1_SCL_T => NLW_inst_I2C1_SCL_T_UNCONNECTED,
I2C1_SDA_I => '0',
I2C1_SDA_O => NLW_inst_I2C1_SDA_O_UNCONNECTED,
I2C1_SDA_T => NLW_inst_I2C1_SDA_T_UNCONNECTED,
IRQ_F2P(1 downto 0) => IRQ_F2P(1 downto 0),
IRQ_P2F_CAN0 => NLW_inst_IRQ_P2F_CAN0_UNCONNECTED,
IRQ_P2F_CAN1 => NLW_inst_IRQ_P2F_CAN1_UNCONNECTED,
IRQ_P2F_CTI => NLW_inst_IRQ_P2F_CTI_UNCONNECTED,
IRQ_P2F_DMAC0 => NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED,
IRQ_P2F_DMAC1 => NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED,
IRQ_P2F_DMAC2 => NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED,
IRQ_P2F_DMAC3 => NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED,
IRQ_P2F_DMAC4 => NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED,
IRQ_P2F_DMAC5 => NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED,
IRQ_P2F_DMAC6 => NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED,
IRQ_P2F_DMAC7 => NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED,
IRQ_P2F_DMAC_ABORT => NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED,
IRQ_P2F_ENET0 => NLW_inst_IRQ_P2F_ENET0_UNCONNECTED,
IRQ_P2F_ENET1 => NLW_inst_IRQ_P2F_ENET1_UNCONNECTED,
IRQ_P2F_ENET_WAKE0 => NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED,
IRQ_P2F_ENET_WAKE1 => NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED,
IRQ_P2F_GPIO => NLW_inst_IRQ_P2F_GPIO_UNCONNECTED,
IRQ_P2F_I2C0 => NLW_inst_IRQ_P2F_I2C0_UNCONNECTED,
IRQ_P2F_I2C1 => NLW_inst_IRQ_P2F_I2C1_UNCONNECTED,
IRQ_P2F_QSPI => NLW_inst_IRQ_P2F_QSPI_UNCONNECTED,
IRQ_P2F_SDIO0 => NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED,
IRQ_P2F_SDIO1 => NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED,
IRQ_P2F_SMC => NLW_inst_IRQ_P2F_SMC_UNCONNECTED,
IRQ_P2F_SPI0 => NLW_inst_IRQ_P2F_SPI0_UNCONNECTED,
IRQ_P2F_SPI1 => NLW_inst_IRQ_P2F_SPI1_UNCONNECTED,
IRQ_P2F_UART0 => NLW_inst_IRQ_P2F_UART0_UNCONNECTED,
IRQ_P2F_UART1 => NLW_inst_IRQ_P2F_UART1_UNCONNECTED,
IRQ_P2F_USB0 => NLW_inst_IRQ_P2F_USB0_UNCONNECTED,
IRQ_P2F_USB1 => NLW_inst_IRQ_P2F_USB1_UNCONNECTED,
MIO(53 downto 0) => MIO(53 downto 0),
M_AXI_GP0_ACLK => M_AXI_GP0_ACLK,
M_AXI_GP0_ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => M_AXI_GP0_ARCACHE(3 downto 0),
M_AXI_GP0_ARESETN => NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED,
M_AXI_GP0_ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0),
M_AXI_GP0_ARREADY => M_AXI_GP0_ARREADY,
M_AXI_GP0_ARSIZE(2 downto 0) => M_AXI_GP0_ARSIZE(2 downto 0),
M_AXI_GP0_ARVALID => M_AXI_GP0_ARVALID,
M_AXI_GP0_AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => M_AXI_GP0_AWCACHE(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0),
M_AXI_GP0_AWREADY => M_AXI_GP0_AWREADY,
M_AXI_GP0_AWSIZE(2 downto 0) => M_AXI_GP0_AWSIZE(2 downto 0),
M_AXI_GP0_AWVALID => M_AXI_GP0_AWVALID,
M_AXI_GP0_BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0),
M_AXI_GP0_BREADY => M_AXI_GP0_BREADY,
M_AXI_GP0_BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0),
M_AXI_GP0_BVALID => M_AXI_GP0_BVALID,
M_AXI_GP0_RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0),
M_AXI_GP0_RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0),
M_AXI_GP0_RLAST => M_AXI_GP0_RLAST,
M_AXI_GP0_RREADY => M_AXI_GP0_RREADY,
M_AXI_GP0_RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0),
M_AXI_GP0_RVALID => M_AXI_GP0_RVALID,
M_AXI_GP0_WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0),
M_AXI_GP0_WLAST => M_AXI_GP0_WLAST,
M_AXI_GP0_WREADY => M_AXI_GP0_WREADY,
M_AXI_GP0_WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0),
M_AXI_GP0_WVALID => M_AXI_GP0_WVALID,
M_AXI_GP1_ACLK => '0',
M_AXI_GP1_ARADDR(31 downto 0) => NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED(31 downto 0),
M_AXI_GP1_ARBURST(1 downto 0) => NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED(1 downto 0),
M_AXI_GP1_ARCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARESETN => NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED,
M_AXI_GP1_ARID(11 downto 0) => NLW_inst_M_AXI_GP1_ARID_UNCONNECTED(11 downto 0),
M_AXI_GP1_ARLEN(3 downto 0) => NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP1_ARPROT(2 downto 0) => NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED(2 downto 0),
M_AXI_GP1_ARQOS(3 downto 0) => NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARREADY => '0',
M_AXI_GP1_ARSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP1_ARVALID => NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED,
M_AXI_GP1_AWADDR(31 downto 0) => NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED(31 downto 0),
M_AXI_GP1_AWBURST(1 downto 0) => NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED(1 downto 0),
M_AXI_GP1_AWCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWID(11 downto 0) => NLW_inst_M_AXI_GP1_AWID_UNCONNECTED(11 downto 0),
M_AXI_GP1_AWLEN(3 downto 0) => NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP1_AWPROT(2 downto 0) => NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED(2 downto 0),
M_AXI_GP1_AWQOS(3 downto 0) => NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWREADY => '0',
M_AXI_GP1_AWSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP1_AWVALID => NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED,
M_AXI_GP1_BID(11 downto 0) => B"000000000000",
M_AXI_GP1_BREADY => NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED,
M_AXI_GP1_BRESP(1 downto 0) => B"00",
M_AXI_GP1_BVALID => '0',
M_AXI_GP1_RDATA(31 downto 0) => B"00000000000000000000000000000000",
M_AXI_GP1_RID(11 downto 0) => B"000000000000",
M_AXI_GP1_RLAST => '0',
M_AXI_GP1_RREADY => NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED,
M_AXI_GP1_RRESP(1 downto 0) => B"00",
M_AXI_GP1_RVALID => '0',
M_AXI_GP1_WDATA(31 downto 0) => NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED(31 downto 0),
M_AXI_GP1_WID(11 downto 0) => NLW_inst_M_AXI_GP1_WID_UNCONNECTED(11 downto 0),
M_AXI_GP1_WLAST => NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED,
M_AXI_GP1_WREADY => '0',
M_AXI_GP1_WSTRB(3 downto 0) => NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED(3 downto 0),
M_AXI_GP1_WVALID => NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED,
PJTAG_TCK => '0',
PJTAG_TDI => '0',
PJTAG_TDO => NLW_inst_PJTAG_TDO_UNCONNECTED,
PJTAG_TMS => '0',
PS_CLK => PS_CLK,
PS_PORB => PS_PORB,
PS_SRSTB => PS_SRSTB,
SDIO0_BUSPOW => NLW_inst_SDIO0_BUSPOW_UNCONNECTED,
SDIO0_BUSVOLT(2 downto 0) => NLW_inst_SDIO0_BUSVOLT_UNCONNECTED(2 downto 0),
SDIO0_CDN => '0',
SDIO0_CLK => NLW_inst_SDIO0_CLK_UNCONNECTED,
SDIO0_CLK_FB => '0',
SDIO0_CMD_I => '0',
SDIO0_CMD_O => NLW_inst_SDIO0_CMD_O_UNCONNECTED,
SDIO0_CMD_T => NLW_inst_SDIO0_CMD_T_UNCONNECTED,
SDIO0_DATA_I(3 downto 0) => B"0000",
SDIO0_DATA_O(3 downto 0) => NLW_inst_SDIO0_DATA_O_UNCONNECTED(3 downto 0),
SDIO0_DATA_T(3 downto 0) => NLW_inst_SDIO0_DATA_T_UNCONNECTED(3 downto 0),
SDIO0_LED => NLW_inst_SDIO0_LED_UNCONNECTED,
SDIO0_WP => '0',
SDIO1_BUSPOW => NLW_inst_SDIO1_BUSPOW_UNCONNECTED,
SDIO1_BUSVOLT(2 downto 0) => NLW_inst_SDIO1_BUSVOLT_UNCONNECTED(2 downto 0),
SDIO1_CDN => '0',
SDIO1_CLK => NLW_inst_SDIO1_CLK_UNCONNECTED,
SDIO1_CLK_FB => '0',
SDIO1_CMD_I => '0',
SDIO1_CMD_O => NLW_inst_SDIO1_CMD_O_UNCONNECTED,
SDIO1_CMD_T => NLW_inst_SDIO1_CMD_T_UNCONNECTED,
SDIO1_DATA_I(3 downto 0) => B"0000",
SDIO1_DATA_O(3 downto 0) => NLW_inst_SDIO1_DATA_O_UNCONNECTED(3 downto 0),
SDIO1_DATA_T(3 downto 0) => NLW_inst_SDIO1_DATA_T_UNCONNECTED(3 downto 0),
SDIO1_LED => NLW_inst_SDIO1_LED_UNCONNECTED,
SDIO1_WP => '0',
SPI0_MISO_I => '0',
SPI0_MISO_O => NLW_inst_SPI0_MISO_O_UNCONNECTED,
SPI0_MISO_T => NLW_inst_SPI0_MISO_T_UNCONNECTED,
SPI0_MOSI_I => '0',
SPI0_MOSI_O => NLW_inst_SPI0_MOSI_O_UNCONNECTED,
SPI0_MOSI_T => NLW_inst_SPI0_MOSI_T_UNCONNECTED,
SPI0_SCLK_I => '0',
SPI0_SCLK_O => NLW_inst_SPI0_SCLK_O_UNCONNECTED,
SPI0_SCLK_T => NLW_inst_SPI0_SCLK_T_UNCONNECTED,
SPI0_SS1_O => NLW_inst_SPI0_SS1_O_UNCONNECTED,
SPI0_SS2_O => NLW_inst_SPI0_SS2_O_UNCONNECTED,
SPI0_SS_I => '0',
SPI0_SS_O => NLW_inst_SPI0_SS_O_UNCONNECTED,
SPI0_SS_T => NLW_inst_SPI0_SS_T_UNCONNECTED,
SPI1_MISO_I => '0',
SPI1_MISO_O => NLW_inst_SPI1_MISO_O_UNCONNECTED,
SPI1_MISO_T => NLW_inst_SPI1_MISO_T_UNCONNECTED,
SPI1_MOSI_I => '0',
SPI1_MOSI_O => NLW_inst_SPI1_MOSI_O_UNCONNECTED,
SPI1_MOSI_T => NLW_inst_SPI1_MOSI_T_UNCONNECTED,
SPI1_SCLK_I => '0',
SPI1_SCLK_O => NLW_inst_SPI1_SCLK_O_UNCONNECTED,
SPI1_SCLK_T => NLW_inst_SPI1_SCLK_T_UNCONNECTED,
SPI1_SS1_O => NLW_inst_SPI1_SS1_O_UNCONNECTED,
SPI1_SS2_O => NLW_inst_SPI1_SS2_O_UNCONNECTED,
SPI1_SS_I => '0',
SPI1_SS_O => NLW_inst_SPI1_SS_O_UNCONNECTED,
SPI1_SS_T => NLW_inst_SPI1_SS_T_UNCONNECTED,
SRAM_INTIN => '0',
S_AXI_ACP_ACLK => '0',
S_AXI_ACP_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_ACP_ARBURST(1 downto 0) => B"00",
S_AXI_ACP_ARCACHE(3 downto 0) => B"0000",
S_AXI_ACP_ARESETN => NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED,
S_AXI_ACP_ARID(2 downto 0) => B"000",
S_AXI_ACP_ARLEN(3 downto 0) => B"0000",
S_AXI_ACP_ARLOCK(1 downto 0) => B"00",
S_AXI_ACP_ARPROT(2 downto 0) => B"000",
S_AXI_ACP_ARQOS(3 downto 0) => B"0000",
S_AXI_ACP_ARREADY => NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED,
S_AXI_ACP_ARSIZE(2 downto 0) => B"000",
S_AXI_ACP_ARUSER(4 downto 0) => B"00000",
S_AXI_ACP_ARVALID => '0',
S_AXI_ACP_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_ACP_AWBURST(1 downto 0) => B"00",
S_AXI_ACP_AWCACHE(3 downto 0) => B"0000",
S_AXI_ACP_AWID(2 downto 0) => B"000",
S_AXI_ACP_AWLEN(3 downto 0) => B"0000",
S_AXI_ACP_AWLOCK(1 downto 0) => B"00",
S_AXI_ACP_AWPROT(2 downto 0) => B"000",
S_AXI_ACP_AWQOS(3 downto 0) => B"0000",
S_AXI_ACP_AWREADY => NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED,
S_AXI_ACP_AWSIZE(2 downto 0) => B"000",
S_AXI_ACP_AWUSER(4 downto 0) => B"00000",
S_AXI_ACP_AWVALID => '0',
S_AXI_ACP_BID(2 downto 0) => NLW_inst_S_AXI_ACP_BID_UNCONNECTED(2 downto 0),
S_AXI_ACP_BREADY => '0',
S_AXI_ACP_BRESP(1 downto 0) => NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED(1 downto 0),
S_AXI_ACP_BVALID => NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED,
S_AXI_ACP_RDATA(63 downto 0) => NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED(63 downto 0),
S_AXI_ACP_RID(2 downto 0) => NLW_inst_S_AXI_ACP_RID_UNCONNECTED(2 downto 0),
S_AXI_ACP_RLAST => NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED,
S_AXI_ACP_RREADY => '0',
S_AXI_ACP_RRESP(1 downto 0) => NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED(1 downto 0),
S_AXI_ACP_RVALID => NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED,
S_AXI_ACP_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_ACP_WID(2 downto 0) => B"000",
S_AXI_ACP_WLAST => '0',
S_AXI_ACP_WREADY => NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED,
S_AXI_ACP_WSTRB(7 downto 0) => B"00000000",
S_AXI_ACP_WVALID => '0',
S_AXI_GP0_ACLK => '0',
S_AXI_GP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_ARBURST(1 downto 0) => B"00",
S_AXI_GP0_ARCACHE(3 downto 0) => B"0000",
S_AXI_GP0_ARESETN => NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED,
S_AXI_GP0_ARID(5 downto 0) => B"000000",
S_AXI_GP0_ARLEN(3 downto 0) => B"0000",
S_AXI_GP0_ARLOCK(1 downto 0) => B"00",
S_AXI_GP0_ARPROT(2 downto 0) => B"000",
S_AXI_GP0_ARQOS(3 downto 0) => B"0000",
S_AXI_GP0_ARREADY => NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED,
S_AXI_GP0_ARSIZE(2 downto 0) => B"000",
S_AXI_GP0_ARVALID => '0',
S_AXI_GP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_AWBURST(1 downto 0) => B"00",
S_AXI_GP0_AWCACHE(3 downto 0) => B"0000",
S_AXI_GP0_AWID(5 downto 0) => B"000000",
S_AXI_GP0_AWLEN(3 downto 0) => B"0000",
S_AXI_GP0_AWLOCK(1 downto 0) => B"00",
S_AXI_GP0_AWPROT(2 downto 0) => B"000",
S_AXI_GP0_AWQOS(3 downto 0) => B"0000",
S_AXI_GP0_AWREADY => NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED,
S_AXI_GP0_AWSIZE(2 downto 0) => B"000",
S_AXI_GP0_AWVALID => '0',
S_AXI_GP0_BID(5 downto 0) => NLW_inst_S_AXI_GP0_BID_UNCONNECTED(5 downto 0),
S_AXI_GP0_BREADY => '0',
S_AXI_GP0_BRESP(1 downto 0) => NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED(1 downto 0),
S_AXI_GP0_BVALID => NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED,
S_AXI_GP0_RDATA(31 downto 0) => NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED(31 downto 0),
S_AXI_GP0_RID(5 downto 0) => NLW_inst_S_AXI_GP0_RID_UNCONNECTED(5 downto 0),
S_AXI_GP0_RLAST => NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED,
S_AXI_GP0_RREADY => '0',
S_AXI_GP0_RRESP(1 downto 0) => NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED(1 downto 0),
S_AXI_GP0_RVALID => NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED,
S_AXI_GP0_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_WID(5 downto 0) => B"000000",
S_AXI_GP0_WLAST => '0',
S_AXI_GP0_WREADY => NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED,
S_AXI_GP0_WSTRB(3 downto 0) => B"0000",
S_AXI_GP0_WVALID => '0',
S_AXI_GP1_ACLK => '0',
S_AXI_GP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_ARBURST(1 downto 0) => B"00",
S_AXI_GP1_ARCACHE(3 downto 0) => B"0000",
S_AXI_GP1_ARESETN => NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED,
S_AXI_GP1_ARID(5 downto 0) => B"000000",
S_AXI_GP1_ARLEN(3 downto 0) => B"0000",
S_AXI_GP1_ARLOCK(1 downto 0) => B"00",
S_AXI_GP1_ARPROT(2 downto 0) => B"000",
S_AXI_GP1_ARQOS(3 downto 0) => B"0000",
S_AXI_GP1_ARREADY => NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED,
S_AXI_GP1_ARSIZE(2 downto 0) => B"000",
S_AXI_GP1_ARVALID => '0',
S_AXI_GP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_AWBURST(1 downto 0) => B"00",
S_AXI_GP1_AWCACHE(3 downto 0) => B"0000",
S_AXI_GP1_AWID(5 downto 0) => B"000000",
S_AXI_GP1_AWLEN(3 downto 0) => B"0000",
S_AXI_GP1_AWLOCK(1 downto 0) => B"00",
S_AXI_GP1_AWPROT(2 downto 0) => B"000",
S_AXI_GP1_AWQOS(3 downto 0) => B"0000",
S_AXI_GP1_AWREADY => NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED,
S_AXI_GP1_AWSIZE(2 downto 0) => B"000",
S_AXI_GP1_AWVALID => '0',
S_AXI_GP1_BID(5 downto 0) => NLW_inst_S_AXI_GP1_BID_UNCONNECTED(5 downto 0),
S_AXI_GP1_BREADY => '0',
S_AXI_GP1_BRESP(1 downto 0) => NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED(1 downto 0),
S_AXI_GP1_BVALID => NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED,
S_AXI_GP1_RDATA(31 downto 0) => NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED(31 downto 0),
S_AXI_GP1_RID(5 downto 0) => NLW_inst_S_AXI_GP1_RID_UNCONNECTED(5 downto 0),
S_AXI_GP1_RLAST => NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED,
S_AXI_GP1_RREADY => '0',
S_AXI_GP1_RRESP(1 downto 0) => NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED(1 downto 0),
S_AXI_GP1_RVALID => NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED,
S_AXI_GP1_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_WID(5 downto 0) => B"000000",
S_AXI_GP1_WLAST => '0',
S_AXI_GP1_WREADY => NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED,
S_AXI_GP1_WSTRB(3 downto 0) => B"0000",
S_AXI_GP1_WVALID => '0',
S_AXI_HP0_ACLK => '0',
S_AXI_HP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP0_ARBURST(1 downto 0) => B"00",
S_AXI_HP0_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP0_ARESETN => NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED,
S_AXI_HP0_ARID(5 downto 0) => B"000000",
S_AXI_HP0_ARLEN(3 downto 0) => B"0000",
S_AXI_HP0_ARLOCK(1 downto 0) => B"00",
S_AXI_HP0_ARPROT(2 downto 0) => B"000",
S_AXI_HP0_ARQOS(3 downto 0) => B"0000",
S_AXI_HP0_ARREADY => NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED,
S_AXI_HP0_ARSIZE(2 downto 0) => B"000",
S_AXI_HP0_ARVALID => '0',
S_AXI_HP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP0_AWBURST(1 downto 0) => B"00",
S_AXI_HP0_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP0_AWID(5 downto 0) => B"000000",
S_AXI_HP0_AWLEN(3 downto 0) => B"0000",
S_AXI_HP0_AWLOCK(1 downto 0) => B"00",
S_AXI_HP0_AWPROT(2 downto 0) => B"000",
S_AXI_HP0_AWQOS(3 downto 0) => B"0000",
S_AXI_HP0_AWREADY => NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED,
S_AXI_HP0_AWSIZE(2 downto 0) => B"000",
S_AXI_HP0_AWVALID => '0',
S_AXI_HP0_BID(5 downto 0) => NLW_inst_S_AXI_HP0_BID_UNCONNECTED(5 downto 0),
S_AXI_HP0_BREADY => '0',
S_AXI_HP0_BRESP(1 downto 0) => NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP0_BVALID => NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED,
S_AXI_HP0_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP0_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_RDATA(63 downto 0) => NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP0_RDISSUECAP1_EN => '0',
S_AXI_HP0_RID(5 downto 0) => NLW_inst_S_AXI_HP0_RID_UNCONNECTED(5 downto 0),
S_AXI_HP0_RLAST => NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED,
S_AXI_HP0_RREADY => '0',
S_AXI_HP0_RRESP(1 downto 0) => NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP0_RVALID => NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED,
S_AXI_HP0_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP0_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP0_WID(5 downto 0) => B"000000",
S_AXI_HP0_WLAST => '0',
S_AXI_HP0_WREADY => NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED,
S_AXI_HP0_WRISSUECAP1_EN => '0',
S_AXI_HP0_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP0_WVALID => '0',
S_AXI_HP1_ACLK => '0',
S_AXI_HP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP1_ARBURST(1 downto 0) => B"00",
S_AXI_HP1_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP1_ARESETN => NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED,
S_AXI_HP1_ARID(5 downto 0) => B"000000",
S_AXI_HP1_ARLEN(3 downto 0) => B"0000",
S_AXI_HP1_ARLOCK(1 downto 0) => B"00",
S_AXI_HP1_ARPROT(2 downto 0) => B"000",
S_AXI_HP1_ARQOS(3 downto 0) => B"0000",
S_AXI_HP1_ARREADY => NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED,
S_AXI_HP1_ARSIZE(2 downto 0) => B"000",
S_AXI_HP1_ARVALID => '0',
S_AXI_HP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP1_AWBURST(1 downto 0) => B"00",
S_AXI_HP1_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP1_AWID(5 downto 0) => B"000000",
S_AXI_HP1_AWLEN(3 downto 0) => B"0000",
S_AXI_HP1_AWLOCK(1 downto 0) => B"00",
S_AXI_HP1_AWPROT(2 downto 0) => B"000",
S_AXI_HP1_AWQOS(3 downto 0) => B"0000",
S_AXI_HP1_AWREADY => NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED,
S_AXI_HP1_AWSIZE(2 downto 0) => B"000",
S_AXI_HP1_AWVALID => '0',
S_AXI_HP1_BID(5 downto 0) => NLW_inst_S_AXI_HP1_BID_UNCONNECTED(5 downto 0),
S_AXI_HP1_BREADY => '0',
S_AXI_HP1_BRESP(1 downto 0) => NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP1_BVALID => NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED,
S_AXI_HP1_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP1_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP1_RDATA(63 downto 0) => NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP1_RDISSUECAP1_EN => '0',
S_AXI_HP1_RID(5 downto 0) => NLW_inst_S_AXI_HP1_RID_UNCONNECTED(5 downto 0),
S_AXI_HP1_RLAST => NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED,
S_AXI_HP1_RREADY => '0',
S_AXI_HP1_RRESP(1 downto 0) => NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP1_RVALID => NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED,
S_AXI_HP1_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP1_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP1_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP1_WID(5 downto 0) => B"000000",
S_AXI_HP1_WLAST => '0',
S_AXI_HP1_WREADY => NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED,
S_AXI_HP1_WRISSUECAP1_EN => '0',
S_AXI_HP1_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP1_WVALID => '0',
S_AXI_HP2_ACLK => '0',
S_AXI_HP2_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP2_ARBURST(1 downto 0) => B"00",
S_AXI_HP2_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP2_ARESETN => NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED,
S_AXI_HP2_ARID(5 downto 0) => B"000000",
S_AXI_HP2_ARLEN(3 downto 0) => B"0000",
S_AXI_HP2_ARLOCK(1 downto 0) => B"00",
S_AXI_HP2_ARPROT(2 downto 0) => B"000",
S_AXI_HP2_ARQOS(3 downto 0) => B"0000",
S_AXI_HP2_ARREADY => NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED,
S_AXI_HP2_ARSIZE(2 downto 0) => B"000",
S_AXI_HP2_ARVALID => '0',
S_AXI_HP2_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP2_AWBURST(1 downto 0) => B"00",
S_AXI_HP2_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP2_AWID(5 downto 0) => B"000000",
S_AXI_HP2_AWLEN(3 downto 0) => B"0000",
S_AXI_HP2_AWLOCK(1 downto 0) => B"00",
S_AXI_HP2_AWPROT(2 downto 0) => B"000",
S_AXI_HP2_AWQOS(3 downto 0) => B"0000",
S_AXI_HP2_AWREADY => NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED,
S_AXI_HP2_AWSIZE(2 downto 0) => B"000",
S_AXI_HP2_AWVALID => '0',
S_AXI_HP2_BID(5 downto 0) => NLW_inst_S_AXI_HP2_BID_UNCONNECTED(5 downto 0),
S_AXI_HP2_BREADY => '0',
S_AXI_HP2_BRESP(1 downto 0) => NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP2_BVALID => NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED,
S_AXI_HP2_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP2_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP2_RDATA(63 downto 0) => NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP2_RDISSUECAP1_EN => '0',
S_AXI_HP2_RID(5 downto 0) => NLW_inst_S_AXI_HP2_RID_UNCONNECTED(5 downto 0),
S_AXI_HP2_RLAST => NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED,
S_AXI_HP2_RREADY => '0',
S_AXI_HP2_RRESP(1 downto 0) => NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP2_RVALID => NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED,
S_AXI_HP2_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP2_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP2_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP2_WID(5 downto 0) => B"000000",
S_AXI_HP2_WLAST => '0',
S_AXI_HP2_WREADY => NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED,
S_AXI_HP2_WRISSUECAP1_EN => '0',
S_AXI_HP2_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP2_WVALID => '0',
S_AXI_HP3_ACLK => '0',
S_AXI_HP3_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP3_ARBURST(1 downto 0) => B"00",
S_AXI_HP3_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP3_ARESETN => NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED,
S_AXI_HP3_ARID(5 downto 0) => B"000000",
S_AXI_HP3_ARLEN(3 downto 0) => B"0000",
S_AXI_HP3_ARLOCK(1 downto 0) => B"00",
S_AXI_HP3_ARPROT(2 downto 0) => B"000",
S_AXI_HP3_ARQOS(3 downto 0) => B"0000",
S_AXI_HP3_ARREADY => NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED,
S_AXI_HP3_ARSIZE(2 downto 0) => B"000",
S_AXI_HP3_ARVALID => '0',
S_AXI_HP3_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP3_AWBURST(1 downto 0) => B"00",
S_AXI_HP3_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP3_AWID(5 downto 0) => B"000000",
S_AXI_HP3_AWLEN(3 downto 0) => B"0000",
S_AXI_HP3_AWLOCK(1 downto 0) => B"00",
S_AXI_HP3_AWPROT(2 downto 0) => B"000",
S_AXI_HP3_AWQOS(3 downto 0) => B"0000",
S_AXI_HP3_AWREADY => NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED,
S_AXI_HP3_AWSIZE(2 downto 0) => B"000",
S_AXI_HP3_AWVALID => '0',
S_AXI_HP3_BID(5 downto 0) => NLW_inst_S_AXI_HP3_BID_UNCONNECTED(5 downto 0),
S_AXI_HP3_BREADY => '0',
S_AXI_HP3_BRESP(1 downto 0) => NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP3_BVALID => NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED,
S_AXI_HP3_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP3_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP3_RDATA(63 downto 0) => NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP3_RDISSUECAP1_EN => '0',
S_AXI_HP3_RID(5 downto 0) => NLW_inst_S_AXI_HP3_RID_UNCONNECTED(5 downto 0),
S_AXI_HP3_RLAST => NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED,
S_AXI_HP3_RREADY => '0',
S_AXI_HP3_RRESP(1 downto 0) => NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP3_RVALID => NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED,
S_AXI_HP3_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP3_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP3_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP3_WID(5 downto 0) => B"000000",
S_AXI_HP3_WLAST => '0',
S_AXI_HP3_WREADY => NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED,
S_AXI_HP3_WRISSUECAP1_EN => '0',
S_AXI_HP3_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP3_WVALID => '0',
TRACE_CLK => '0',
TRACE_CLK_OUT => NLW_inst_TRACE_CLK_OUT_UNCONNECTED,
TRACE_CTL => NLW_inst_TRACE_CTL_UNCONNECTED,
TRACE_DATA(1 downto 0) => NLW_inst_TRACE_DATA_UNCONNECTED(1 downto 0),
TTC0_CLK0_IN => '0',
TTC0_CLK1_IN => '0',
TTC0_CLK2_IN => '0',
TTC0_WAVE0_OUT => TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT => TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT => TTC0_WAVE2_OUT,
TTC1_CLK0_IN => '0',
TTC1_CLK1_IN => '0',
TTC1_CLK2_IN => '0',
TTC1_WAVE0_OUT => NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED,
TTC1_WAVE1_OUT => NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED,
TTC1_WAVE2_OUT => NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED,
UART0_CTSN => '0',
UART0_DCDN => '0',
UART0_DSRN => '0',
UART0_DTRN => NLW_inst_UART0_DTRN_UNCONNECTED,
UART0_RIN => '0',
UART0_RTSN => NLW_inst_UART0_RTSN_UNCONNECTED,
UART0_RX => '1',
UART0_TX => NLW_inst_UART0_TX_UNCONNECTED,
UART1_CTSN => '0',
UART1_DCDN => '0',
UART1_DSRN => '0',
UART1_DTRN => NLW_inst_UART1_DTRN_UNCONNECTED,
UART1_RIN => '0',
UART1_RTSN => NLW_inst_UART1_RTSN_UNCONNECTED,
UART1_RX => '1',
UART1_TX => NLW_inst_UART1_TX_UNCONNECTED,
USB0_PORT_INDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0),
USB0_VBUS_PWRFAULT => USB0_VBUS_PWRFAULT,
USB0_VBUS_PWRSELECT => USB0_VBUS_PWRSELECT,
USB1_PORT_INDCTL(1 downto 0) => NLW_inst_USB1_PORT_INDCTL_UNCONNECTED(1 downto 0),
USB1_VBUS_PWRFAULT => '0',
USB1_VBUS_PWRSELECT => NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED,
WDT_CLK_IN => '0',
WDT_RST_OUT => NLW_inst_WDT_RST_OUT_UNCONNECTED
);
end STRUCTURE;
| mit | ab61f8b0bc667fa542d54d16d18fb3ee | 0.634475 | 2.756222 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.cache/ip/2017.2.1/2ff70a5d74413a8b/zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_sim_netlist.vhdl | 1 | 79,179 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2.1 (win64) Build 1957588 Wed Aug 9 16:32:24 MDT 2017
-- Date : Fri Sep 22 17:41:20 2017
-- Host : EffulgentTome running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_sim_netlist.vhdl
-- Design : zqynq_lab_1_design_axi_bram_ctrl_0_bram_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper is
port (
douta : out STD_LOGIC_VECTOR ( 15 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 15 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 15 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 15 downto 0 );
wea : in STD_LOGIC_VECTOR ( 1 downto 0 );
web : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper is
signal \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_87\ : STD_LOGIC;
signal \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_88\ : STD_LOGIC;
signal \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_91\ : STD_LOGIC;
signal \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_92\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[15:0][0:2047]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 18,
READ_WIDTH_B => 18,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 18,
WRITE_WIDTH_B => 18
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 4) => addra(10 downto 0),
ADDRARDADDR(3 downto 0) => B"1111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 4) => addrb(10 downto 0),
ADDRBWRADDR(3 downto 0) => B"1111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 16) => B"0000000000000000",
DIADI(15 downto 0) => dina(15 downto 0),
DIBDI(31 downto 16) => B"0000000000000000",
DIBDI(15 downto 0) => dinb(15 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 16) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 16),
DOADO(15 downto 0) => douta(15 downto 0),
DOBDO(31 downto 16) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 16),
DOBDO(15 downto 0) => doutb(15 downto 0),
DOPADOP(3 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 2),
DOPADOP(1) => \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_87\,
DOPADOP(0) => \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_88\,
DOPBDOP(3 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 2),
DOPBDOP(1) => \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_91\,
DOPBDOP(0) => \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_92\,
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3 downto 2) => wea(1 downto 0),
WEA(1 downto 0) => wea(1 downto 0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3 downto 2) => web(1 downto 0),
WEBWE(1 downto 0) => web(1 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\ is
port (
douta : out STD_LOGIC_VECTOR ( 15 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 15 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 15 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 15 downto 0 );
wea : in STD_LOGIC_VECTOR ( 1 downto 0 );
web : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\ is
signal \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_87\ : STD_LOGIC;
signal \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_88\ : STD_LOGIC;
signal \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_91\ : STD_LOGIC;
signal \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_92\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[31:16][0:2047]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 18,
READ_WIDTH_B => 18,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 18,
WRITE_WIDTH_B => 18
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 4) => addra(10 downto 0),
ADDRARDADDR(3 downto 0) => B"1111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 4) => addrb(10 downto 0),
ADDRBWRADDR(3 downto 0) => B"1111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 16) => B"0000000000000000",
DIADI(15 downto 0) => dina(15 downto 0),
DIBDI(31 downto 16) => B"0000000000000000",
DIBDI(15 downto 0) => dinb(15 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 16) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 16),
DOADO(15 downto 0) => douta(15 downto 0),
DOBDO(31 downto 16) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 16),
DOBDO(15 downto 0) => doutb(15 downto 0),
DOPADOP(3 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 2),
DOPADOP(1) => \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_87\,
DOPADOP(0) => \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_88\,
DOPBDOP(3 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 2),
DOPBDOP(1) => \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_91\,
DOPBDOP(0) => \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_92\,
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3 downto 2) => wea(1 downto 0),
WEA(1 downto 0) => wea(1 downto 0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3 downto 2) => web(1 downto 0),
WEBWE(1 downto 0) => web(1 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is
port (
douta : out STD_LOGIC_VECTOR ( 15 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 15 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 15 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 15 downto 0 );
wea : in STD_LOGIC_VECTOR ( 1 downto 0 );
web : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper
port map (
addra(10 downto 0) => addra(10 downto 0),
addrb(10 downto 0) => addrb(10 downto 0),
clka => clka,
clkb => clkb,
dina(15 downto 0) => dina(15 downto 0),
dinb(15 downto 0) => dinb(15 downto 0),
douta(15 downto 0) => douta(15 downto 0),
doutb(15 downto 0) => doutb(15 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(1 downto 0) => wea(1 downto 0),
web(1 downto 0) => web(1 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ is
port (
douta : out STD_LOGIC_VECTOR ( 15 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 15 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 15 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 15 downto 0 );
wea : in STD_LOGIC_VECTOR ( 1 downto 0 );
web : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\
port map (
addra(10 downto 0) => addra(10 downto 0),
addrb(10 downto 0) => addrb(10 downto 0),
clka => clka,
clkb => clkb,
dina(15 downto 0) => dina(15 downto 0),
dinb(15 downto 0) => dinb(15 downto 0),
douta(15 downto 0) => douta(15 downto 0),
doutb(15 downto 0) => doutb(15 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(1 downto 0) => wea(1 downto 0),
web(1 downto 0) => web(1 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is
port (
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
wea : in STD_LOGIC_VECTOR ( 3 downto 0 );
web : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width
port map (
addra(10 downto 0) => addra(10 downto 0),
addrb(10 downto 0) => addrb(10 downto 0),
clka => clka,
clkb => clkb,
dina(15 downto 0) => dina(15 downto 0),
dinb(15 downto 0) => dinb(15 downto 0),
douta(15 downto 0) => douta(15 downto 0),
doutb(15 downto 0) => doutb(15 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(1 downto 0) => wea(1 downto 0),
web(1 downto 0) => web(1 downto 0)
);
\ramloop[1].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\
port map (
addra(10 downto 0) => addra(10 downto 0),
addrb(10 downto 0) => addrb(10 downto 0),
clka => clka,
clkb => clkb,
dina(15 downto 0) => dina(31 downto 16),
dinb(15 downto 0) => dinb(31 downto 16),
douta(15 downto 0) => douta(31 downto 16),
doutb(15 downto 0) => doutb(31 downto 16),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(1 downto 0) => wea(3 downto 2),
web(1 downto 0) => web(3 downto 2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is
port (
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
wea : in STD_LOGIC_VECTOR ( 3 downto 0 );
web : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is
begin
\valid.cstr\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr
port map (
addra(10 downto 0) => addra(10 downto 0),
addrb(10 downto 0) => addrb(10 downto 0),
clka => clka,
clkb => clkb,
dina(31 downto 0) => dina(31 downto 0),
dinb(31 downto 0) => dinb(31 downto 0),
douta(31 downto 0) => douta(31 downto 0),
doutb(31 downto 0) => doutb(31 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(3 downto 0) => wea(3 downto 0),
web(3 downto 0) => web(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6_synth is
port (
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
wea : in STD_LOGIC_VECTOR ( 3 downto 0 );
web : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6_synth;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6_synth is
begin
\gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top
port map (
addra(10 downto 0) => addra(10 downto 0),
addrb(10 downto 0) => addrb(10 downto 0),
clka => clka,
clkb => clkb,
dina(31 downto 0) => dina(31 downto 0),
dinb(31 downto 0) => dinb(31 downto 0),
douta(31 downto 0) => douta(31 downto 0),
doutb(31 downto 0) => doutb(31 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(3 downto 0) => wea(3 downto 0),
web(3 downto 0) => web(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 3 downto 0 );
addra : in STD_LOGIC_VECTOR ( 31 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 3 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 31 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 31 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 32;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 32;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 8;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "0";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "2";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "Estimated Power for IP : 10.7492 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "NONE";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "no_coe_file_loaded";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 2;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 2048;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 2048;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 32;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 32;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 4;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 4;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 2048;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 2048;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 32;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 32;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "zynq";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "yes";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
rdaddrecc(31) <= \<const0>\;
rdaddrecc(30) <= \<const0>\;
rdaddrecc(29) <= \<const0>\;
rdaddrecc(28) <= \<const0>\;
rdaddrecc(27) <= \<const0>\;
rdaddrecc(26) <= \<const0>\;
rdaddrecc(25) <= \<const0>\;
rdaddrecc(24) <= \<const0>\;
rdaddrecc(23) <= \<const0>\;
rdaddrecc(22) <= \<const0>\;
rdaddrecc(21) <= \<const0>\;
rdaddrecc(20) <= \<const0>\;
rdaddrecc(19) <= \<const0>\;
rdaddrecc(18) <= \<const0>\;
rdaddrecc(17) <= \<const0>\;
rdaddrecc(16) <= \<const0>\;
rdaddrecc(15) <= \<const0>\;
rdaddrecc(14) <= \<const0>\;
rdaddrecc(13) <= \<const0>\;
rdaddrecc(12) <= \<const0>\;
rdaddrecc(11) <= \<const0>\;
rdaddrecc(10) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
rsta_busy <= \<const0>\;
rstb_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(31) <= \<const0>\;
s_axi_rdaddrecc(30) <= \<const0>\;
s_axi_rdaddrecc(29) <= \<const0>\;
s_axi_rdaddrecc(28) <= \<const0>\;
s_axi_rdaddrecc(27) <= \<const0>\;
s_axi_rdaddrecc(26) <= \<const0>\;
s_axi_rdaddrecc(25) <= \<const0>\;
s_axi_rdaddrecc(24) <= \<const0>\;
s_axi_rdaddrecc(23) <= \<const0>\;
s_axi_rdaddrecc(22) <= \<const0>\;
s_axi_rdaddrecc(21) <= \<const0>\;
s_axi_rdaddrecc(20) <= \<const0>\;
s_axi_rdaddrecc(19) <= \<const0>\;
s_axi_rdaddrecc(18) <= \<const0>\;
s_axi_rdaddrecc(17) <= \<const0>\;
s_axi_rdaddrecc(16) <= \<const0>\;
s_axi_rdaddrecc(15) <= \<const0>\;
s_axi_rdaddrecc(14) <= \<const0>\;
s_axi_rdaddrecc(13) <= \<const0>\;
s_axi_rdaddrecc(12) <= \<const0>\;
s_axi_rdaddrecc(11) <= \<const0>\;
s_axi_rdaddrecc(10) <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6_synth
port map (
addra(10 downto 0) => addra(12 downto 2),
addrb(10 downto 0) => addrb(12 downto 2),
clka => clka,
clkb => clkb,
dina(31 downto 0) => dina(31 downto 0),
dinb(31 downto 0) => dinb(31 downto 0),
douta(31 downto 0) => douta(31 downto 0),
doutb(31 downto 0) => doutb(31 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(3 downto 0) => wea(3 downto 0),
web(3 downto 0) => web(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 3 downto 0 );
addra : in STD_LOGIC_VECTOR ( 31 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 3 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 31 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "zqynq_lab_1_design_axi_bram_ctrl_0_bram_0,blk_mem_gen_v8_3_6,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "blk_mem_gen_v8_3_6,Vivado 2017.2.1";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 32;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 32;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 8;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "0";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "2";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 1;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 10.7492 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 1;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 1;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 1;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "NONE";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "no_coe_file_loaded";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 0;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 2;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 2048;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 2048;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 32;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 32;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 1;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 1;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 1;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 4;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 4;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 2048;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 2048;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 32;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 32;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "zynq";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6
port map (
addra(31 downto 0) => addra(31 downto 0),
addrb(31 downto 0) => addrb(31 downto 0),
clka => clka,
clkb => clkb,
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(31 downto 0) => dina(31 downto 0),
dinb(31 downto 0) => dinb(31 downto 0),
douta(31 downto 0) => douta(31 downto 0),
doutb(31 downto 0) => doutb(31 downto 0),
eccpipece => '0',
ena => ena,
enb => enb,
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(31 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(31 downto 0),
regcea => '0',
regceb => '0',
rsta => rsta,
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => rstb,
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(31 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(31 downto 0),
s_axi_rdata(31 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(31 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(31 downto 0) => B"00000000000000000000000000000000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(3 downto 0) => B"0000",
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(3 downto 0) => wea(3 downto 0),
web(3 downto 0) => web(3 downto 0)
);
end STRUCTURE;
| mit | 54b8f952c655bb2fba255da583c9be72 | 0.713661 | 3.760222 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/lab3_project.xpr/project_1/project_1.ipdefs/ip_0/RecComp_cnn_lab_convolve_kernel_1_0/hdl/vhdl/convolve_kernel_fbkb.vhd | 1 | 3,595 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.3
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity convolve_kernel_fbkb is
generic (
ID : integer := 1;
NUM_STAGE : integer := 14;
din0_WIDTH : integer := 32;
din1_WIDTH : integer := 32;
dout_WIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of convolve_kernel_fbkb is
--------------------- Component ---------------------
component convolve_kernel_ap_fadd_12_no_dsp_32 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(31 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(31 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
signal ce_r : std_logic;
signal dout_i : std_logic_vector(dout_WIDTH-1 downto 0);
signal dout_r : std_logic_vector(dout_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
convolve_kernel_ap_fadd_12_no_dsp_32_u : component convolve_kernel_ap_fadd_12_no_dsp_32
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce_r;
a_tvalid <= '1';
a_tdata <= din0_buf1;
b_tvalid <= '1';
b_tdata <= din1_buf1;
dout_i <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
process (clk) begin
if clk'event and clk = '1' then
ce_r <= ce;
end if;
end process;
process (clk) begin
if clk'event and clk = '1' then
if ce_r = '1' then
dout_r <= dout_i;
end if;
end if;
end process;
dout <= dout_i when ce_r = '1' else dout_r;
end architecture;
| mit | cd3b984c317f850771eb552f43cc5819 | 0.484006 | 3.609438 | false | false | false | false |
eamadio/fpgaMSP430 | fmsp430/misc/fmsp_and_gate.vhd | 1 | 3,442 | ------------------------------------------------------------------------------
--! Copyright (C) 2009 , Olivier Girard
--
--! Redistribution and use in source and binary forms, with or without
--! modification, are permitted provided that the following conditions
--! are met:
--! * Redistributions of source code must retain the above copyright
--! notice, this list of conditions and the following disclaimer.
--! * Redistributions in binary form must reproduce the above copyright
--! notice, this list of conditions and the following disclaimer in the
--! documentation and/or other materials provided with the distribution.
--! * Neither the name of the authors nor the names of its contributors
--! may be used to endorse or promote products derived from this software
--! without specific prior written permission.
--
--! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
--! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
--! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
--! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
--! OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
--! THE POSSIBILITY OF SUCH DAMAGE
--
------------------------------------------------------------------------------
--
--! @file fmsp_and_gate.vhd
--!
--! @brief fpgaMSP430 Generic AND gate cell
--
--! @author Olivier Girard, [email protected]
--! @author Emmanuel Amadio, [email protected] (VHDL Rewrite)
--
------------------------------------------------------------------------------
--! @version 1
--! @date: 2017-04-21
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all; --! standard unresolved logic UX01ZWLH-
entity fmsp_and_gate is
port (
--! INPUTs
a : in std_logic; --! AND gate input A
b : in std_logic; --! AND gate input B
--! OUTPUTs
y : out std_logic --! AND gate outputt
);
end entity fmsp_and_gate;
architecture RTL of fmsp_and_gate is
begin
--=============================================================================
--! 1) SOME COMMENTS ON THIS MODULE
--=============================================================================
--
--! In its ASIC version, some combinatorial pathes of the openMSP430 are
--! sensitive to glitches, in particular the ones generating the wakeup
--! signals.
--! To prevent synthesis from optmizing combinatorial clouds into glitchy
--! logic, this AND gate module has been instanciated in the critical places.
--
--! Make sure that synthesis doesn't ungroup this module. As an alternative,
--! a standard cell from the library could also be directly instanciated here
--! (don't forget the "dont_touch" attribute)
--
--
--=============================================================================
--! 2) AND GATE
--=============================================================================
y <= a and b;
end RTL; --! fmsp_and_gate
| bsd-3-clause | 976771df86a32dedd2fd0c10314f3d4e | 0.58803 | 4.787204 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/adventures_with_ip/adventures_with_ip.cache/ip/2017.3/33befe9f7af11a93/ip_design_led_controller_0_0_sim_netlist.vhdl | 1 | 66,499 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 18:54:09 2017
-- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_led_controller_0_0_sim_netlist.vhdl
-- Design : ip_design_led_controller_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_led_controller_v1_0_S00_AXI is
port (
S_AXI_ARREADY : out STD_LOGIC;
S_AXI_AWREADY : out STD_LOGIC;
S_AXI_WREADY : out STD_LOGIC;
LEDs_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_bvalid : out STD_LOGIC;
s00_axi_arvalid : in STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_araddr : in STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_aresetn : in STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_rready : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_led_controller_v1_0_S00_AXI;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_led_controller_v1_0_S00_AXI is
signal \^leds_out\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^s_axi_arready\ : STD_LOGIC;
signal \^s_axi_awready\ : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
signal aw_en_i_1_n_0 : STD_LOGIC;
signal aw_en_reg_n_0 : STD_LOGIC;
signal axi_araddr : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \axi_araddr[2]_i_1_n_0\ : STD_LOGIC;
signal \axi_araddr[3]_i_1_n_0\ : STD_LOGIC;
signal axi_arready_i_1_n_0 : STD_LOGIC;
signal \axi_awaddr[2]_i_1_n_0\ : STD_LOGIC;
signal \axi_awaddr[3]_i_1_n_0\ : STD_LOGIC;
signal axi_awready0 : STD_LOGIC;
signal axi_bvalid_i_1_n_0 : STD_LOGIC;
signal axi_rvalid_i_1_n_0 : STD_LOGIC;
signal axi_wready0 : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 1 downto 0 );
signal p_1_in : STD_LOGIC_VECTOR ( 31 downto 7 );
signal reg_data_out : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s00_axi_bvalid\ : STD_LOGIC;
signal \^s00_axi_rvalid\ : STD_LOGIC;
signal slv_reg0 : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \slv_reg0[7]_i_1_n_0\ : STD_LOGIC;
signal slv_reg1 : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \slv_reg1[15]_i_1_n_0\ : STD_LOGIC;
signal \slv_reg1[23]_i_1_n_0\ : STD_LOGIC;
signal \slv_reg1[31]_i_1_n_0\ : STD_LOGIC;
signal \slv_reg1[7]_i_1_n_0\ : STD_LOGIC;
signal slv_reg2 : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \slv_reg2[15]_i_1_n_0\ : STD_LOGIC;
signal \slv_reg2[23]_i_1_n_0\ : STD_LOGIC;
signal \slv_reg2[31]_i_1_n_0\ : STD_LOGIC;
signal \slv_reg2[7]_i_1_n_0\ : STD_LOGIC;
signal slv_reg3 : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \slv_reg3[15]_i_1_n_0\ : STD_LOGIC;
signal \slv_reg3[23]_i_1_n_0\ : STD_LOGIC;
signal \slv_reg3[31]_i_1_n_0\ : STD_LOGIC;
signal \slv_reg3[7]_i_1_n_0\ : STD_LOGIC;
signal \slv_reg_rden__0\ : STD_LOGIC;
signal \slv_reg_wren__0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axi_araddr[3]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of axi_arready_i_1 : label is "soft_lutpair1";
attribute SOFT_HLUTNM of axi_wready_i_1 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \slv_reg0[7]_i_3\ : label is "soft_lutpair0";
begin
LEDs_out(7 downto 0) <= \^leds_out\(7 downto 0);
S_AXI_ARREADY <= \^s_axi_arready\;
S_AXI_AWREADY <= \^s_axi_awready\;
S_AXI_WREADY <= \^s_axi_wready\;
s00_axi_bvalid <= \^s00_axi_bvalid\;
s00_axi_rvalid <= \^s00_axi_rvalid\;
aw_en_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"F7FFC4CCC4CCC4CC"
)
port map (
I0 => s00_axi_wvalid,
I1 => aw_en_reg_n_0,
I2 => \^s_axi_awready\,
I3 => s00_axi_awvalid,
I4 => s00_axi_bready,
I5 => \^s00_axi_bvalid\,
O => aw_en_i_1_n_0
);
aw_en_reg: unisim.vcomponents.FDSE
port map (
C => s00_axi_aclk,
CE => '1',
D => aw_en_i_1_n_0,
Q => aw_en_reg_n_0,
S => \slv_reg0[7]_i_1_n_0\
);
\axi_araddr[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s00_axi_araddr(0),
I1 => s00_axi_arvalid,
I2 => \^s_axi_arready\,
I3 => axi_araddr(2),
O => \axi_araddr[2]_i_1_n_0\
);
\axi_araddr[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s00_axi_araddr(1),
I1 => s00_axi_arvalid,
I2 => \^s_axi_arready\,
I3 => axi_araddr(3),
O => \axi_araddr[3]_i_1_n_0\
);
\axi_araddr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => '1',
D => \axi_araddr[2]_i_1_n_0\,
Q => axi_araddr(2),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_araddr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => '1',
D => \axi_araddr[3]_i_1_n_0\,
Q => axi_araddr(3),
R => \slv_reg0[7]_i_1_n_0\
);
axi_arready_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s00_axi_arvalid,
I1 => \^s_axi_arready\,
O => axi_arready_i_1_n_0
);
axi_arready_reg: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => '1',
D => axi_arready_i_1_n_0,
Q => \^s_axi_arready\,
R => \slv_reg0[7]_i_1_n_0\
);
\axi_awaddr[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FBFFFFFF08000000"
)
port map (
I0 => s00_axi_awaddr(0),
I1 => s00_axi_awvalid,
I2 => \^s_axi_awready\,
I3 => aw_en_reg_n_0,
I4 => s00_axi_wvalid,
I5 => p_0_in(0),
O => \axi_awaddr[2]_i_1_n_0\
);
\axi_awaddr[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FBFFFFFF08000000"
)
port map (
I0 => s00_axi_awaddr(1),
I1 => s00_axi_awvalid,
I2 => \^s_axi_awready\,
I3 => aw_en_reg_n_0,
I4 => s00_axi_wvalid,
I5 => p_0_in(1),
O => \axi_awaddr[3]_i_1_n_0\
);
\axi_awaddr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => '1',
D => \axi_awaddr[2]_i_1_n_0\,
Q => p_0_in(0),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_awaddr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => '1',
D => \axi_awaddr[3]_i_1_n_0\,
Q => p_0_in(1),
R => \slv_reg0[7]_i_1_n_0\
);
axi_awready_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => s00_axi_awvalid,
I1 => \^s_axi_awready\,
I2 => aw_en_reg_n_0,
I3 => s00_axi_wvalid,
O => axi_awready0
);
axi_awready_reg: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => '1',
D => axi_awready0,
Q => \^s_axi_awready\,
R => \slv_reg0[7]_i_1_n_0\
);
axi_bvalid_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFF80008000"
)
port map (
I0 => \^s_axi_wready\,
I1 => \^s_axi_awready\,
I2 => s00_axi_awvalid,
I3 => s00_axi_wvalid,
I4 => s00_axi_bready,
I5 => \^s00_axi_bvalid\,
O => axi_bvalid_i_1_n_0
);
axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => '1',
D => axi_bvalid_i_1_n_0,
Q => \^s00_axi_bvalid\,
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(0),
I1 => \^leds_out\(0),
I2 => slv_reg3(0),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(0),
O => reg_data_out(0)
);
\axi_rdata[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(10),
I1 => slv_reg0(10),
I2 => slv_reg3(10),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(10),
O => reg_data_out(10)
);
\axi_rdata[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(11),
I1 => slv_reg0(11),
I2 => slv_reg3(11),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(11),
O => reg_data_out(11)
);
\axi_rdata[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(12),
I1 => slv_reg0(12),
I2 => slv_reg3(12),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(12),
O => reg_data_out(12)
);
\axi_rdata[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(13),
I1 => slv_reg0(13),
I2 => slv_reg3(13),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(13),
O => reg_data_out(13)
);
\axi_rdata[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(14),
I1 => slv_reg0(14),
I2 => slv_reg3(14),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(14),
O => reg_data_out(14)
);
\axi_rdata[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(15),
I1 => slv_reg0(15),
I2 => slv_reg3(15),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(15),
O => reg_data_out(15)
);
\axi_rdata[16]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(16),
I1 => slv_reg0(16),
I2 => slv_reg3(16),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(16),
O => reg_data_out(16)
);
\axi_rdata[17]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(17),
I1 => slv_reg0(17),
I2 => slv_reg3(17),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(17),
O => reg_data_out(17)
);
\axi_rdata[18]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(18),
I1 => slv_reg0(18),
I2 => slv_reg3(18),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(18),
O => reg_data_out(18)
);
\axi_rdata[19]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(19),
I1 => slv_reg0(19),
I2 => slv_reg3(19),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(19),
O => reg_data_out(19)
);
\axi_rdata[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(1),
I1 => \^leds_out\(1),
I2 => slv_reg3(1),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(1),
O => reg_data_out(1)
);
\axi_rdata[20]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(20),
I1 => slv_reg0(20),
I2 => slv_reg3(20),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(20),
O => reg_data_out(20)
);
\axi_rdata[21]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(21),
I1 => slv_reg0(21),
I2 => slv_reg3(21),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(21),
O => reg_data_out(21)
);
\axi_rdata[22]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(22),
I1 => slv_reg0(22),
I2 => slv_reg3(22),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(22),
O => reg_data_out(22)
);
\axi_rdata[23]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(23),
I1 => slv_reg0(23),
I2 => slv_reg3(23),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(23),
O => reg_data_out(23)
);
\axi_rdata[24]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(24),
I1 => slv_reg0(24),
I2 => slv_reg3(24),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(24),
O => reg_data_out(24)
);
\axi_rdata[25]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(25),
I1 => slv_reg0(25),
I2 => slv_reg3(25),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(25),
O => reg_data_out(25)
);
\axi_rdata[26]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(26),
I1 => slv_reg0(26),
I2 => slv_reg3(26),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(26),
O => reg_data_out(26)
);
\axi_rdata[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(27),
I1 => slv_reg0(27),
I2 => slv_reg3(27),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(27),
O => reg_data_out(27)
);
\axi_rdata[28]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(28),
I1 => slv_reg0(28),
I2 => slv_reg3(28),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(28),
O => reg_data_out(28)
);
\axi_rdata[29]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(29),
I1 => slv_reg0(29),
I2 => slv_reg3(29),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(29),
O => reg_data_out(29)
);
\axi_rdata[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(2),
I1 => \^leds_out\(2),
I2 => slv_reg3(2),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(2),
O => reg_data_out(2)
);
\axi_rdata[30]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(30),
I1 => slv_reg0(30),
I2 => slv_reg3(30),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(30),
O => reg_data_out(30)
);
\axi_rdata[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(31),
I1 => slv_reg0(31),
I2 => slv_reg3(31),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(31),
O => reg_data_out(31)
);
\axi_rdata[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(3),
I1 => \^leds_out\(3),
I2 => slv_reg3(3),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(3),
O => reg_data_out(3)
);
\axi_rdata[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(4),
I1 => \^leds_out\(4),
I2 => slv_reg3(4),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(4),
O => reg_data_out(4)
);
\axi_rdata[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(5),
I1 => \^leds_out\(5),
I2 => slv_reg3(5),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(5),
O => reg_data_out(5)
);
\axi_rdata[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(6),
I1 => \^leds_out\(6),
I2 => slv_reg3(6),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(6),
O => reg_data_out(6)
);
\axi_rdata[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(7),
I1 => \^leds_out\(7),
I2 => slv_reg3(7),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(7),
O => reg_data_out(7)
);
\axi_rdata[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(8),
I1 => slv_reg0(8),
I2 => slv_reg3(8),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(8),
O => reg_data_out(8)
);
\axi_rdata[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(9),
I1 => slv_reg0(9),
I2 => slv_reg3(9),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(9),
O => reg_data_out(9)
);
\axi_rdata_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(0),
Q => s00_axi_rdata(0),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(10),
Q => s00_axi_rdata(10),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(11),
Q => s00_axi_rdata(11),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(12),
Q => s00_axi_rdata(12),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(13),
Q => s00_axi_rdata(13),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(14),
Q => s00_axi_rdata(14),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(15),
Q => s00_axi_rdata(15),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(16),
Q => s00_axi_rdata(16),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(17),
Q => s00_axi_rdata(17),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(18),
Q => s00_axi_rdata(18),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(19),
Q => s00_axi_rdata(19),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(1),
Q => s00_axi_rdata(1),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(20),
Q => s00_axi_rdata(20),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(21),
Q => s00_axi_rdata(21),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(22),
Q => s00_axi_rdata(22),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(23),
Q => s00_axi_rdata(23),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(24),
Q => s00_axi_rdata(24),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(25),
Q => s00_axi_rdata(25),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(26),
Q => s00_axi_rdata(26),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(27),
Q => s00_axi_rdata(27),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(28),
Q => s00_axi_rdata(28),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(29),
Q => s00_axi_rdata(29),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(2),
Q => s00_axi_rdata(2),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(30),
Q => s00_axi_rdata(30),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(31),
Q => s00_axi_rdata(31),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(3),
Q => s00_axi_rdata(3),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(4),
Q => s00_axi_rdata(4),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(5),
Q => s00_axi_rdata(5),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(6),
Q => s00_axi_rdata(6),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(7),
Q => s00_axi_rdata(7),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(8),
Q => s00_axi_rdata(8),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(9),
Q => s00_axi_rdata(9),
R => \slv_reg0[7]_i_1_n_0\
);
axi_rvalid_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"08F8"
)
port map (
I0 => \^s_axi_arready\,
I1 => s00_axi_arvalid,
I2 => \^s00_axi_rvalid\,
I3 => s00_axi_rready,
O => axi_rvalid_i_1_n_0
);
axi_rvalid_reg: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => '1',
D => axi_rvalid_i_1_n_0,
Q => \^s00_axi_rvalid\,
R => \slv_reg0[7]_i_1_n_0\
);
axi_wready_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"4000"
)
port map (
I0 => \^s_axi_wready\,
I1 => s00_axi_wvalid,
I2 => s00_axi_awvalid,
I3 => aw_en_reg_n_0,
O => axi_wready0
);
axi_wready_reg: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => '1',
D => axi_wready0,
Q => \^s_axi_wready\,
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0[15]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0200"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => p_0_in(0),
I3 => s00_axi_wstrb(1),
O => p_1_in(15)
);
\slv_reg0[23]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0200"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => p_0_in(0),
I3 => s00_axi_wstrb(2),
O => p_1_in(23)
);
\slv_reg0[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0200"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => p_0_in(0),
I3 => s00_axi_wstrb(3),
O => p_1_in(31)
);
\slv_reg0[7]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s00_axi_aresetn,
O => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0[7]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0200"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => p_0_in(0),
I3 => s00_axi_wstrb(0),
O => p_1_in(7)
);
\slv_reg0[7]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^s_axi_wready\,
I1 => \^s_axi_awready\,
I2 => s00_axi_awvalid,
I3 => s00_axi_wvalid,
O => \slv_reg_wren__0\
);
\slv_reg0_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(7),
D => s00_axi_wdata(0),
Q => \^leds_out\(0),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(15),
D => s00_axi_wdata(10),
Q => slv_reg0(10),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(15),
D => s00_axi_wdata(11),
Q => slv_reg0(11),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(15),
D => s00_axi_wdata(12),
Q => slv_reg0(12),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(15),
D => s00_axi_wdata(13),
Q => slv_reg0(13),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(15),
D => s00_axi_wdata(14),
Q => slv_reg0(14),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(15),
D => s00_axi_wdata(15),
Q => slv_reg0(15),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(23),
D => s00_axi_wdata(16),
Q => slv_reg0(16),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(23),
D => s00_axi_wdata(17),
Q => slv_reg0(17),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(23),
D => s00_axi_wdata(18),
Q => slv_reg0(18),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(23),
D => s00_axi_wdata(19),
Q => slv_reg0(19),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(7),
D => s00_axi_wdata(1),
Q => \^leds_out\(1),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(23),
D => s00_axi_wdata(20),
Q => slv_reg0(20),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(23),
D => s00_axi_wdata(21),
Q => slv_reg0(21),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(23),
D => s00_axi_wdata(22),
Q => slv_reg0(22),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(23),
D => s00_axi_wdata(23),
Q => slv_reg0(23),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(31),
D => s00_axi_wdata(24),
Q => slv_reg0(24),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(31),
D => s00_axi_wdata(25),
Q => slv_reg0(25),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(31),
D => s00_axi_wdata(26),
Q => slv_reg0(26),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(31),
D => s00_axi_wdata(27),
Q => slv_reg0(27),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(31),
D => s00_axi_wdata(28),
Q => slv_reg0(28),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(31),
D => s00_axi_wdata(29),
Q => slv_reg0(29),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(7),
D => s00_axi_wdata(2),
Q => \^leds_out\(2),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(31),
D => s00_axi_wdata(30),
Q => slv_reg0(30),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(31),
D => s00_axi_wdata(31),
Q => slv_reg0(31),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(7),
D => s00_axi_wdata(3),
Q => \^leds_out\(3),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(7),
D => s00_axi_wdata(4),
Q => \^leds_out\(4),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(7),
D => s00_axi_wdata(5),
Q => \^leds_out\(5),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(7),
D => s00_axi_wdata(6),
Q => \^leds_out\(6),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(7),
D => s00_axi_wdata(7),
Q => \^leds_out\(7),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(15),
D => s00_axi_wdata(8),
Q => slv_reg0(8),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(15),
D => s00_axi_wdata(9),
Q => slv_reg0(9),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1[15]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => s00_axi_wstrb(1),
I3 => p_0_in(0),
O => \slv_reg1[15]_i_1_n_0\
);
\slv_reg1[23]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => s00_axi_wstrb(2),
I3 => p_0_in(0),
O => \slv_reg1[23]_i_1_n_0\
);
\slv_reg1[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => s00_axi_wstrb(3),
I3 => p_0_in(0),
O => \slv_reg1[31]_i_1_n_0\
);
\slv_reg1[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => s00_axi_wstrb(0),
I3 => p_0_in(0),
O => \slv_reg1[7]_i_1_n_0\
);
\slv_reg1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[7]_i_1_n_0\,
D => s00_axi_wdata(0),
Q => slv_reg1(0),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[15]_i_1_n_0\,
D => s00_axi_wdata(10),
Q => slv_reg1(10),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[15]_i_1_n_0\,
D => s00_axi_wdata(11),
Q => slv_reg1(11),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[15]_i_1_n_0\,
D => s00_axi_wdata(12),
Q => slv_reg1(12),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[15]_i_1_n_0\,
D => s00_axi_wdata(13),
Q => slv_reg1(13),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[15]_i_1_n_0\,
D => s00_axi_wdata(14),
Q => slv_reg1(14),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[15]_i_1_n_0\,
D => s00_axi_wdata(15),
Q => slv_reg1(15),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[23]_i_1_n_0\,
D => s00_axi_wdata(16),
Q => slv_reg1(16),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[23]_i_1_n_0\,
D => s00_axi_wdata(17),
Q => slv_reg1(17),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[23]_i_1_n_0\,
D => s00_axi_wdata(18),
Q => slv_reg1(18),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[23]_i_1_n_0\,
D => s00_axi_wdata(19),
Q => slv_reg1(19),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[7]_i_1_n_0\,
D => s00_axi_wdata(1),
Q => slv_reg1(1),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[23]_i_1_n_0\,
D => s00_axi_wdata(20),
Q => slv_reg1(20),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[23]_i_1_n_0\,
D => s00_axi_wdata(21),
Q => slv_reg1(21),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[23]_i_1_n_0\,
D => s00_axi_wdata(22),
Q => slv_reg1(22),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[23]_i_1_n_0\,
D => s00_axi_wdata(23),
Q => slv_reg1(23),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[31]_i_1_n_0\,
D => s00_axi_wdata(24),
Q => slv_reg1(24),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[31]_i_1_n_0\,
D => s00_axi_wdata(25),
Q => slv_reg1(25),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[31]_i_1_n_0\,
D => s00_axi_wdata(26),
Q => slv_reg1(26),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[31]_i_1_n_0\,
D => s00_axi_wdata(27),
Q => slv_reg1(27),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[31]_i_1_n_0\,
D => s00_axi_wdata(28),
Q => slv_reg1(28),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[31]_i_1_n_0\,
D => s00_axi_wdata(29),
Q => slv_reg1(29),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[7]_i_1_n_0\,
D => s00_axi_wdata(2),
Q => slv_reg1(2),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[31]_i_1_n_0\,
D => s00_axi_wdata(30),
Q => slv_reg1(30),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[31]_i_1_n_0\,
D => s00_axi_wdata(31),
Q => slv_reg1(31),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[7]_i_1_n_0\,
D => s00_axi_wdata(3),
Q => slv_reg1(3),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[7]_i_1_n_0\,
D => s00_axi_wdata(4),
Q => slv_reg1(4),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[7]_i_1_n_0\,
D => s00_axi_wdata(5),
Q => slv_reg1(5),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[7]_i_1_n_0\,
D => s00_axi_wdata(6),
Q => slv_reg1(6),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[7]_i_1_n_0\,
D => s00_axi_wdata(7),
Q => slv_reg1(7),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[15]_i_1_n_0\,
D => s00_axi_wdata(8),
Q => slv_reg1(8),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[15]_i_1_n_0\,
D => s00_axi_wdata(9),
Q => slv_reg1(9),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2[15]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => s00_axi_wstrb(1),
I3 => p_0_in(0),
O => \slv_reg2[15]_i_1_n_0\
);
\slv_reg2[23]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => s00_axi_wstrb(2),
I3 => p_0_in(0),
O => \slv_reg2[23]_i_1_n_0\
);
\slv_reg2[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => s00_axi_wstrb(3),
I3 => p_0_in(0),
O => \slv_reg2[31]_i_1_n_0\
);
\slv_reg2[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => s00_axi_wstrb(0),
I3 => p_0_in(0),
O => \slv_reg2[7]_i_1_n_0\
);
\slv_reg2_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[7]_i_1_n_0\,
D => s00_axi_wdata(0),
Q => slv_reg2(0),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[15]_i_1_n_0\,
D => s00_axi_wdata(10),
Q => slv_reg2(10),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[15]_i_1_n_0\,
D => s00_axi_wdata(11),
Q => slv_reg2(11),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[15]_i_1_n_0\,
D => s00_axi_wdata(12),
Q => slv_reg2(12),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[15]_i_1_n_0\,
D => s00_axi_wdata(13),
Q => slv_reg2(13),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[15]_i_1_n_0\,
D => s00_axi_wdata(14),
Q => slv_reg2(14),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[15]_i_1_n_0\,
D => s00_axi_wdata(15),
Q => slv_reg2(15),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[23]_i_1_n_0\,
D => s00_axi_wdata(16),
Q => slv_reg2(16),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[23]_i_1_n_0\,
D => s00_axi_wdata(17),
Q => slv_reg2(17),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[23]_i_1_n_0\,
D => s00_axi_wdata(18),
Q => slv_reg2(18),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[23]_i_1_n_0\,
D => s00_axi_wdata(19),
Q => slv_reg2(19),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[7]_i_1_n_0\,
D => s00_axi_wdata(1),
Q => slv_reg2(1),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[23]_i_1_n_0\,
D => s00_axi_wdata(20),
Q => slv_reg2(20),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[23]_i_1_n_0\,
D => s00_axi_wdata(21),
Q => slv_reg2(21),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[23]_i_1_n_0\,
D => s00_axi_wdata(22),
Q => slv_reg2(22),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[23]_i_1_n_0\,
D => s00_axi_wdata(23),
Q => slv_reg2(23),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[31]_i_1_n_0\,
D => s00_axi_wdata(24),
Q => slv_reg2(24),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[31]_i_1_n_0\,
D => s00_axi_wdata(25),
Q => slv_reg2(25),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[31]_i_1_n_0\,
D => s00_axi_wdata(26),
Q => slv_reg2(26),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[31]_i_1_n_0\,
D => s00_axi_wdata(27),
Q => slv_reg2(27),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[31]_i_1_n_0\,
D => s00_axi_wdata(28),
Q => slv_reg2(28),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[31]_i_1_n_0\,
D => s00_axi_wdata(29),
Q => slv_reg2(29),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[7]_i_1_n_0\,
D => s00_axi_wdata(2),
Q => slv_reg2(2),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[31]_i_1_n_0\,
D => s00_axi_wdata(30),
Q => slv_reg2(30),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[31]_i_1_n_0\,
D => s00_axi_wdata(31),
Q => slv_reg2(31),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[7]_i_1_n_0\,
D => s00_axi_wdata(3),
Q => slv_reg2(3),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[7]_i_1_n_0\,
D => s00_axi_wdata(4),
Q => slv_reg2(4),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[7]_i_1_n_0\,
D => s00_axi_wdata(5),
Q => slv_reg2(5),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[7]_i_1_n_0\,
D => s00_axi_wdata(6),
Q => slv_reg2(6),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[7]_i_1_n_0\,
D => s00_axi_wdata(7),
Q => slv_reg2(7),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[15]_i_1_n_0\,
D => s00_axi_wdata(8),
Q => slv_reg2(8),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[15]_i_1_n_0\,
D => s00_axi_wdata(9),
Q => slv_reg2(9),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3[15]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => s00_axi_wstrb(1),
I2 => p_0_in(0),
I3 => p_0_in(1),
O => \slv_reg3[15]_i_1_n_0\
);
\slv_reg3[23]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => s00_axi_wstrb(2),
I2 => p_0_in(0),
I3 => p_0_in(1),
O => \slv_reg3[23]_i_1_n_0\
);
\slv_reg3[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => s00_axi_wstrb(3),
I2 => p_0_in(0),
I3 => p_0_in(1),
O => \slv_reg3[31]_i_1_n_0\
);
\slv_reg3[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => s00_axi_wstrb(0),
I2 => p_0_in(0),
I3 => p_0_in(1),
O => \slv_reg3[7]_i_1_n_0\
);
\slv_reg3_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[7]_i_1_n_0\,
D => s00_axi_wdata(0),
Q => slv_reg3(0),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[15]_i_1_n_0\,
D => s00_axi_wdata(10),
Q => slv_reg3(10),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[15]_i_1_n_0\,
D => s00_axi_wdata(11),
Q => slv_reg3(11),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[15]_i_1_n_0\,
D => s00_axi_wdata(12),
Q => slv_reg3(12),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[15]_i_1_n_0\,
D => s00_axi_wdata(13),
Q => slv_reg3(13),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[15]_i_1_n_0\,
D => s00_axi_wdata(14),
Q => slv_reg3(14),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[15]_i_1_n_0\,
D => s00_axi_wdata(15),
Q => slv_reg3(15),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[23]_i_1_n_0\,
D => s00_axi_wdata(16),
Q => slv_reg3(16),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[23]_i_1_n_0\,
D => s00_axi_wdata(17),
Q => slv_reg3(17),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[23]_i_1_n_0\,
D => s00_axi_wdata(18),
Q => slv_reg3(18),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[23]_i_1_n_0\,
D => s00_axi_wdata(19),
Q => slv_reg3(19),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[7]_i_1_n_0\,
D => s00_axi_wdata(1),
Q => slv_reg3(1),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[23]_i_1_n_0\,
D => s00_axi_wdata(20),
Q => slv_reg3(20),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[23]_i_1_n_0\,
D => s00_axi_wdata(21),
Q => slv_reg3(21),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[23]_i_1_n_0\,
D => s00_axi_wdata(22),
Q => slv_reg3(22),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[23]_i_1_n_0\,
D => s00_axi_wdata(23),
Q => slv_reg3(23),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[31]_i_1_n_0\,
D => s00_axi_wdata(24),
Q => slv_reg3(24),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[31]_i_1_n_0\,
D => s00_axi_wdata(25),
Q => slv_reg3(25),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[31]_i_1_n_0\,
D => s00_axi_wdata(26),
Q => slv_reg3(26),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[31]_i_1_n_0\,
D => s00_axi_wdata(27),
Q => slv_reg3(27),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[31]_i_1_n_0\,
D => s00_axi_wdata(28),
Q => slv_reg3(28),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[31]_i_1_n_0\,
D => s00_axi_wdata(29),
Q => slv_reg3(29),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[7]_i_1_n_0\,
D => s00_axi_wdata(2),
Q => slv_reg3(2),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[31]_i_1_n_0\,
D => s00_axi_wdata(30),
Q => slv_reg3(30),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[31]_i_1_n_0\,
D => s00_axi_wdata(31),
Q => slv_reg3(31),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[7]_i_1_n_0\,
D => s00_axi_wdata(3),
Q => slv_reg3(3),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[7]_i_1_n_0\,
D => s00_axi_wdata(4),
Q => slv_reg3(4),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[7]_i_1_n_0\,
D => s00_axi_wdata(5),
Q => slv_reg3(5),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[7]_i_1_n_0\,
D => s00_axi_wdata(6),
Q => slv_reg3(6),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[7]_i_1_n_0\,
D => s00_axi_wdata(7),
Q => slv_reg3(7),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[15]_i_1_n_0\,
D => s00_axi_wdata(8),
Q => slv_reg3(8),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[15]_i_1_n_0\,
D => s00_axi_wdata(9),
Q => slv_reg3(9),
R => \slv_reg0[7]_i_1_n_0\
);
slv_reg_rden: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \^s00_axi_rvalid\,
I1 => s00_axi_arvalid,
I2 => \^s_axi_arready\,
O => \slv_reg_rden__0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_led_controller_v1_0 is
port (
S_AXI_ARREADY : out STD_LOGIC;
S_AXI_AWREADY : out STD_LOGIC;
S_AXI_WREADY : out STD_LOGIC;
LEDs_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_bvalid : out STD_LOGIC;
s00_axi_arvalid : in STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_araddr : in STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_aresetn : in STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_rready : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_led_controller_v1_0;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_led_controller_v1_0 is
begin
led_controller_v1_0_S00_AXI_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_led_controller_v1_0_S00_AXI
port map (
LEDs_out(7 downto 0) => LEDs_out(7 downto 0),
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WREADY => S_AXI_WREADY,
s00_axi_aclk => s00_axi_aclk,
s00_axi_araddr(1 downto 0) => s00_axi_araddr(1 downto 0),
s00_axi_aresetn => s00_axi_aresetn,
s00_axi_arvalid => s00_axi_arvalid,
s00_axi_awaddr(1 downto 0) => s00_axi_awaddr(1 downto 0),
s00_axi_awvalid => s00_axi_awvalid,
s00_axi_bready => s00_axi_bready,
s00_axi_bvalid => s00_axi_bvalid,
s00_axi_rdata(31 downto 0) => s00_axi_rdata(31 downto 0),
s00_axi_rready => s00_axi_rready,
s00_axi_rvalid => s00_axi_rvalid,
s00_axi_wdata(31 downto 0) => s00_axi_wdata(31 downto 0),
s00_axi_wstrb(3 downto 0) => s00_axi_wstrb(3 downto 0),
s00_axi_wvalid => s00_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
LEDs_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_awready : out STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wready : out STD_LOGIC;
s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_bvalid : out STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_arvalid : in STD_LOGIC;
s00_axi_arready : out STD_LOGIC;
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "ip_design_led_controller_0_0,led_controller_v1_0,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "led_controller_v1_0,Vivado 2017.3";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal \<const0>\ : STD_LOGIC;
attribute X_INTERFACE_INFO : string;
attribute X_INTERFACE_INFO of s00_axi_aclk : signal is "xilinx.com:signal:clock:1.0 S00_AXI_CLK CLK";
attribute X_INTERFACE_PARAMETER : string;
attribute X_INTERFACE_PARAMETER of s00_axi_aclk : signal is "XIL_INTERFACENAME S00_AXI_CLK, ASSOCIATED_BUSIF S00_AXI, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0";
attribute X_INTERFACE_INFO of s00_axi_aresetn : signal is "xilinx.com:signal:reset:1.0 S00_AXI_RST RST";
attribute X_INTERFACE_PARAMETER of s00_axi_aresetn : signal is "XIL_INTERFACENAME S00_AXI_RST, POLARITY ACTIVE_LOW";
attribute X_INTERFACE_INFO of s00_axi_arready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY";
attribute X_INTERFACE_INFO of s00_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID";
attribute X_INTERFACE_INFO of s00_axi_awready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY";
attribute X_INTERFACE_INFO of s00_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID";
attribute X_INTERFACE_INFO of s00_axi_bready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI BREADY";
attribute X_INTERFACE_INFO of s00_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI BVALID";
attribute X_INTERFACE_INFO of s00_axi_rready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RREADY";
attribute X_INTERFACE_PARAMETER of s00_axi_rready : signal is "XIL_INTERFACENAME S00_AXI, WIZ_DATA_WIDTH 32, WIZ_NUM_REG 4, SUPPORTS_NARROW_BURST 0, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 4, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
attribute X_INTERFACE_INFO of s00_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RVALID";
attribute X_INTERFACE_INFO of s00_axi_wready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WREADY";
attribute X_INTERFACE_INFO of s00_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WVALID";
attribute X_INTERFACE_INFO of s00_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR";
attribute X_INTERFACE_INFO of s00_axi_arprot : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT";
attribute X_INTERFACE_INFO of s00_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR";
attribute X_INTERFACE_INFO of s00_axi_awprot : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT";
attribute X_INTERFACE_INFO of s00_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 S00_AXI BRESP";
attribute X_INTERFACE_INFO of s00_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RDATA";
attribute X_INTERFACE_INFO of s00_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RRESP";
attribute X_INTERFACE_INFO of s00_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WDATA";
attribute X_INTERFACE_INFO of s00_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB";
begin
s00_axi_bresp(1) <= \<const0>\;
s00_axi_bresp(0) <= \<const0>\;
s00_axi_rresp(1) <= \<const0>\;
s00_axi_rresp(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_led_controller_v1_0
port map (
LEDs_out(7 downto 0) => LEDs_out(7 downto 0),
S_AXI_ARREADY => s00_axi_arready,
S_AXI_AWREADY => s00_axi_awready,
S_AXI_WREADY => s00_axi_wready,
s00_axi_aclk => s00_axi_aclk,
s00_axi_araddr(1 downto 0) => s00_axi_araddr(3 downto 2),
s00_axi_aresetn => s00_axi_aresetn,
s00_axi_arvalid => s00_axi_arvalid,
s00_axi_awaddr(1 downto 0) => s00_axi_awaddr(3 downto 2),
s00_axi_awvalid => s00_axi_awvalid,
s00_axi_bready => s00_axi_bready,
s00_axi_bvalid => s00_axi_bvalid,
s00_axi_rdata(31 downto 0) => s00_axi_rdata(31 downto 0),
s00_axi_rready => s00_axi_rready,
s00_axi_rvalid => s00_axi_rvalid,
s00_axi_wdata(31 downto 0) => s00_axi_wdata(31 downto 0),
s00_axi_wstrb(3 downto 0) => s00_axi_wstrb(3 downto 0),
s00_axi_wvalid => s00_axi_wvalid
);
end STRUCTURE;
| mit | 91c99cfe550a6db8f85b03723966daf7 | 0.51282 | 2.530115 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/techmap/maps/allmul.vhd | 1 | 3,153 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: allmul
-- File: allmul.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Multiplier components
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package allmul is
component mul_dw is
generic (
a_width : positive := 2; -- multiplier word width
b_width : positive := 2; -- multiplicand word width
num_stages : positive := 2; -- number of pipeline stages
stall_mode : natural range 0 to 1 := 1 -- '0': non-stallable; '1': stallable
);
port(a : in std_logic_vector(a_width-1 downto 0);
b : in std_logic_vector(b_width-1 downto 0);
clk : in std_logic;
en : in std_logic;
sign : in std_logic;
product : out std_logic_vector(a_width+b_width-1 downto 0));
end component;
component gen_mult_pipe
generic (
a_width : positive; -- multiplier word width
b_width : positive; -- multiplicand word width
num_stages : positive := 2; -- number of pipeline stages
stall_mode : natural range 0 to 1 := 1); -- '0': non-stallable; '1': stallable
port (
clk : in std_logic; -- register clock
en : in std_logic; -- register enable
tc : in std_logic; -- '0' : unsigned, '1' : signed
a : in std_logic_vector(a_width-1 downto 0); -- multiplier
b : in std_logic_vector(b_width-1 downto 0); -- multiplicand
product : out std_logic_vector(a_width+b_width-1 downto 0)); -- product
end component;
component axcel_mul_33x33_signed
generic (
pipe: Integer := 0);
port (
a: in Std_Logic_Vector(32 downto 0);
b: in Std_Logic_Vector(32 downto 0);
en: in Std_Logic;
clk: in Std_Logic;
p: out Std_Logic_Vector(65 downto 0));
end component;
end;
| gpl-2.0 | 9979c6980a66b6cef659cc4db4615a29 | 0.541072 | 4.121569 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/memctrl/srctrl.vhd | 1 | 16,113 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: srctrl
-- File: srctrl.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Modified: Marko Isomaki - Gaisler Research
-- Description: 32-bit SRAM memory controller with read-modify-write
-- Supports also 64-bit AHB read/write accesses
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.memctrl.all;
entity srctrl is
generic (
hindex : integer := 0;
romaddr : integer := 0;
rommask : integer := 16#ff0#;
ramaddr : integer := 16#400#;
rammask : integer := 16#ff0#;
ioaddr : integer := 16#200#;
iomask : integer := 16#ff0#;
ramws : integer := 0;
romws : integer := 2;
iows : integer := 2;
rmw : integer := 0; -- read-modify-write enable
prom8en : integer := 0;
oepol : integer := 0;
srbanks : integer range 1 to 5 := 1;
banksz : integer range 0 to 13 := 13;
romasel : integer range 0 to 28 := 19
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sri : in memory_in_type;
sro : out memory_out_type;
sdo : out sdctrl_out_type
);
end;
architecture rtl of srctrl is
constant VERSION : amba_version_type := 0;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg(VENDOR_GAISLER, GAISLER_SRCTRL, 0, VERSION, 0),
4 => ahb_membar(romaddr, '1', '1', rommask),
5 => ahb_membar(ramaddr, '1', '1', rammask),
6 => ahb_membar(ioaddr, '0', '0', iomask),
others => zero32);
type srcycletype is (idle, read1, read2, write1, write2, write3, rmw1, rmw2, rmw3);
type prom8cycletype is (idle, read1, read2);
function byteswap (rdata, wdata : std_logic_vector(31 downto 0); addr, size : std_logic_vector) return std_logic_vector is
variable tmp : std_logic_vector(31 downto 0);
variable a : std_logic_vector(1 downto 0);
begin
tmp := rdata; a := addr(1 downto 0);
if size(0) = '0' then
case a is
when "00" => tmp(31 downto 24) := wdata(31 downto 24);
when "01" => tmp(23 downto 16) := wdata(23 downto 16);
when "10" => tmp(15 downto 8) := wdata(15 downto 8);
when others => tmp(7 downto 0) := wdata(7 downto 0);
end case;
else
if addr(1) = '0' then tmp(31 downto 16) := wdata(31 downto 16);
else tmp(15 downto 0) := wdata(15 downto 0); end if;
end if;
return(tmp);
end;
-- local registers
type reg_type is record
hready : std_ulogic;
hsel : std_ulogic;
hmbsel : std_logic_vector(0 to 2);
bdrive : std_ulogic;
nbdrive : std_ulogic;
srstate : srcycletype;
haddr : std_logic_vector(31 downto 0);
hrdata : std_logic_vector(63 downto 0);
hwdata : std_logic_vector(63 downto 0);
hwrite : std_ulogic;
htrans : std_logic_vector(1 downto 0);
hburst : std_logic_vector(2 downto 0);
hresp : std_logic_vector(1 downto 0);
size : std_logic_vector(1 downto 0);
read : std_ulogic;
oen : std_ulogic;
ramsn : std_ulogic;
romsn : std_ulogic;
vramsn : std_logic_vector(4 downto 0);
ramoen : std_logic_vector(4 downto 0);
vromsn : std_logic_vector(1 downto 0);
writen : std_ulogic;
wen : std_logic_vector(3 downto 0);
mben : std_logic_vector(3 downto 0);
ws : std_logic_vector(3 downto 0);
iosn : std_ulogic;
-- 8-bit prom access
pr8state : prom8cycletype;
data8 : std_logic_vector(23 downto 0);
ready8 : std_ulogic;
bwidth : std_logic_vector(1 downto 0);
end record;
signal r, ri : reg_type;
-- vectored output enable to data pads
signal rbdrive, ribdrive : std_logic_vector(31 downto 0);
attribute syn_preserve : boolean;
attribute syn_preserve of rbdrive : signal is true;
begin
ctrl : process(rst, ahbsi, r, sri, rbdrive)
variable v : reg_type; -- local variables for registers
variable dqm : std_logic_vector(3 downto 0);
variable adec : std_logic_vector(1 downto 0);
variable rams : std_logic_vector(4 downto 0);
variable roms : std_logic_vector(1 downto 0);
variable haddr : std_logic_vector(31 downto 0);
variable hrdata : std_logic_vector(63 downto 0);
variable hsize : std_logic_vector(1 downto 0);
variable hwrite : std_ulogic;
variable htrans : std_logic_vector(1 downto 0);
variable vramws, vromws, viows : std_logic_vector(3 downto 0);
-- 8-bit prom access
variable romsn : std_ulogic;
variable bdrive : std_ulogic;
variable oen : std_ulogic;
variable writen : std_ulogic;
variable hready : std_ulogic;
variable ws : std_logic_vector(3 downto 0);
variable prom8sel : std_ulogic;
variable vbdrive : std_logic_vector(31 downto 0);
variable sbdrive : std_ulogic;
begin
-- Variable default settings to avoid latches
v := r; v.hresp := HRESP_OKAY; v.hrdata(31 downto 0) := sri.data;
hrdata := r.hrdata;
vramws := conv_std_logic_vector(ramws, 4); vbdrive := rbdrive;
vromws := conv_std_logic_vector(romws, 4);
viows := conv_std_logic_vector(iows, 4);
v.bwidth := sri.bwidth;
if (prom8en = 1) and (r.bwidth = "00") then prom8sel := '1';
else prom8sel := '0'; end if;
if (ahbsi.hready = '1') then
if (ahbsi.hsel(hindex) and ahbsi.htrans(1)) = '1' then
v.size := ahbsi.hsize(1 downto 0); v.hwrite := ahbsi.hwrite;
v.htrans := ahbsi.htrans; v.hburst := ahbsi.hburst;
v.hsel := '1'; v.hmbsel := ahbsi.hmbsel(0 to 2);
v.haddr := ahbsi.haddr; v.hready := '0';
else
v.hsel := '0';
end if;
end if;
if (r.hsel = '1') and (ahbsi.hready = '0') then
haddr := r.haddr; hsize := r.size;
htrans := r.htrans; hwrite := r.hwrite;
else
haddr := ahbsi.haddr; hsize := ahbsi.hsize(1 downto 0);
htrans := ahbsi.htrans; hwrite := ahbsi.hwrite;
end if;
-- chip-select decoding
adec := haddr(banksz+14 downto banksz+13);
rams := '0' & decode(adec);
case srbanks is
when 1 => rams := "00001";
when 2 => rams := "000" & (rams(3 downto 2) or rams(1 downto 0));
when others => null;
end case;
roms := haddr(romasel) & not haddr(romasel);
-- generate write strobes
if rmw = 1 then dqm := "0000"; else
case r.size is
when "00" =>
case r.haddr(1 downto 0) is
when "00" => dqm := "1110";
when "01" => dqm := "1101";
when "10" => dqm := "1011";
when others => dqm := "0111";
end case;
when "01" =>
if r.haddr(1) = '0' then dqm := "1100"; else dqm := "0011"; end if;
when others => dqm := "0000";
end case;
end if;
-- main FSM
case r.srstate is
when idle =>
if (v.hsel = '1') and not
(((v.ramsn or r.romsn) = '0') or ((v.romsn or r.ramsn) = '0')) and not
((v.hmbsel(0) and not hwrite and prom8sel) = '1' and prom8en = 1)
then
v.hready := '0';
v.ramsn := not v.hmbsel(1); v.romsn := not v.hmbsel(0);
v.iosn := not v.hmbsel(2);
v.read := not hwrite;
if hwrite = '1' then
if (rmw = 1) and (hsize(1) = '0') and (v.hmbsel(1) = '1') then
v.srstate := rmw1; v.read := '1';
else v.srstate := write1; end if;
elsif ahbsi.htrans = "10" then v.srstate := read1;
else v.srstate := read2; end if;
v.oen := not v.read;
else
v.ramsn := '1'; v.romsn := '1'; v.bdrive := '1'; v.oen := '1';
v.iosn := '1';
end if;
if v.romsn = '0' then v.ws := vromws;
elsif v.iosn = '0' then v.ws := viows;
else v.ws := vramws; end if;
when read1 =>
v.srstate := read2;
v.hrdata(63 downto 32) := r.hrdata(31 downto 0);
when read2 =>
v.ws := r.ws -1; v.oen := '0';
if r.ws = "0000" then
if (r.size /= "11") or (r.haddr(2) = '1') or (AHBDW = 32) then
v.srstate := idle; v.hready := '1'; v.haddr := ahbsi.haddr;
v.ramsn := not (ahbsi.hmbsel(1) and ahbsi.htrans(1));
v.romsn := not (ahbsi.hmbsel(0) and ahbsi.htrans(1));
v.oen := not (ahbsi.hsel(hindex) and ahbsi.htrans(1) and not ahbsi.hwrite);
else
v.srstate := read1; v.haddr(2) := '1';
if v.romsn = '0' then v.ws := vromws;
elsif v.iosn = '0' then v.ws := viows;
else v.ws := vramws; end if;
end if;
end if;
when write1 =>
if r.romsn = '0' then v.ws := vromws;
elsif v.iosn = '0' then v.ws := viows;
else v.ws := vramws; end if;
v.srstate := write2; v.bdrive := '0'; v.wen := dqm; v.writen := '0';
v.hwdata(31 downto 0) := ahbsi.hwdata(31 downto 0);
if not ((r.size = "11") and (r.haddr(2) = '1')) then
v.hwdata(63 downto 32) := ahbsi.hwdata(63 mod AHBDW downto 32 mod AHBDW);
end if;
when write2 =>
if r.ws = "0000" then
if (r.size /= "11") or (r.haddr(2) = '1') or (AHBDW = 32) then
v.srstate := idle; v.bdrive := '1'; v.hready := '1';
else
v.srstate := write3;
end if;
v.wen := "1111"; v.writen := '1';
end if;
v.ws := r.ws -1;
when write3 =>
v.haddr(2) := '1'; v.hwdata(63 downto 32) := r.hwdata(31 downto 0);
v.srstate := write1;
when rmw1 =>
if (rmw = 1) then v.oen := '0';
v.srstate := rmw2;
v.hwdata(31 downto 0) := ahbsi.hwdata(31 downto 0);
v.hwdata(63 downto 32) := ahbsi.hwdata(63 mod AHBDW downto 32 mod AHBDW);
end if;
when rmw2 =>
if (rmw = 1) then
v.ws := r.ws -1;
if r.ws = "0000" then v.oen := '1'; v.srstate := rmw3; end if;
end if;
when rmw3 =>
if (rmw = 1) then
v.hwdata(63 downto 32) := byteswap(r.hrdata(31 downto 0), r.hwdata(63 downto 32), r.haddr, r.size);
v.srstate := write2; v.bdrive := '0'; v.wen := dqm; v.writen := '0';
end if;
if r.romsn = '0' then v.ws := vromws; else v.ws := vramws; end if;
end case;
if (ahbsi.hready and ahbsi.hsel(hindex) ) = '1' then
if ahbsi.htrans(1) = '0' then v.hready := '1'; end if;
end if;
-- 8-bit PROM access FSM
if prom8en = 1 then
hready := '0'; ws := v.ws; v.ready8 := '0';
bdrive := '1'; oen := '1'; writen := '1'; romsn := '1';
if r.ready8 = '1' then
v.data8 := r.data8(15 downto 0) & r.hrdata(31 downto 24);
case r.size is
when "00" => hrdata(31 downto 0) := r.hrdata(31 downto 24) &
r.hrdata(31 downto 24) & r.hrdata(31 downto 24) & r.hrdata(31 downto 24);
when "01" => hrdata(31 downto 0) := r.data8(7 downto 0) & r.hrdata(31 downto 24) &
r.data8(7 downto 0) & r.hrdata(31 downto 24);
when others => hrdata(31 downto 0) := r.data8 & r.hrdata(31 downto 24);
end case;
end if;
case r.pr8state is
when idle =>
if ( (v.hsel and v.hmbsel(0) and not hwrite and prom8sel) = '1')
then
romsn := '0'; v.pr8state := read1; oen := '0';
end if;
when read1 =>
oen := '0'; romsn := '0'; v.pr8state := read2; ws := vromws;
when read2 =>
oen := '0'; ws := r.ws - 1; romsn := '0';
if r.ws = "0000" then
v.haddr(1 downto 0) := r.haddr(1 downto 0) + 1;
if (r.size = "00") or ((r.size = "01") and (r.haddr(0) = '1'))
or r.haddr(1 downto 0) = "11"
then
hready := '1'; v.pr8state := idle; oen := '1';
else
v.pr8state := read1;
end if;
v.ready8 := '1';
end if;
when others =>
v.pr8state := idle;
end case;
v.romsn := v.romsn and romsn; v.bdrive := v.bdrive and bdrive;
v.oen := v.oen and oen; v.writen := v.writen and writen;
v.hready := v.hready or hready; v.ws := ws;
end if;
if (v.oen or v.ramsn) = '0' then v.ramoen := not rams;
else v.ramoen := (others => '1'); end if;
if v.romsn = '0' then v.vromsn := not roms;
else v.vromsn := (others => '1'); end if;
if v.ramsn = '0' then v.vramsn := not rams;
else v.vramsn := (others => '1'); end if;
if v.read = '1' then v.mben := "0000"; else v.mben := v.wen; end if;
v.nbdrive := not v.bdrive;
if oepol = 1 then sbdrive := r.nbdrive; vbdrive := (others => v.nbdrive);
else sbdrive := r.bdrive; vbdrive := (others => v.bdrive); end if;
if (r.size /= "11") or (AHBDW = 32) then hrdata(63 downto 32) := hrdata(31 downto 0); end if;
-- reset
if rst = '0' then
v.srstate := idle; v.hsel := '0'; v.writen := '1';
v.wen := (others => '1'); v.hready := '1'; v.read := '1';
v.ws := (others => '0');
if prom8en = 1 then v.pr8state := idle; end if;
end if;
ribdrive <= vbdrive;
ri <= v;
sro.address <= r.haddr;
sro.bdrive <= (others => sbdrive);
sro.vbdrive <= rbdrive;
sro.ramsn <= "111" & r.vramsn;
sro.ramoen <= "111" & r.ramoen;
sro.romsn <= "111111" & r.vromsn;
sro.iosn <= r.iosn;
sro.wrn <= r.wen;
sro.oen <= r.oen;
sro.read <= r.read;
sro.data <= r.hwdata(63 downto 32);
sro.writen <= r.writen;
sro.ramn <= r.ramsn;
sro.romn <= r.romsn;
ahbso.hready <= r.hready;
ahbso.hresp <= r.hresp;
ahbso.hrdata <= ahbdrivedata(hrdata);
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbso.hsplit <= (others => '0');
end process;
sdo.sdcsn <= "11"; sdo.sdcke <= "11"; sdo.sdwen <= '1'; sdo.rasn <= '1';
sdo.casn <= '1'; sdo.dqm <= (others => '1'); sdo.address <= (others => '0');
sdo.data <= (others => '0'); sdo.conf <= (others => '0'); sdo.odt <= (others => '0');
sdo.cal_pll <= (others => '0'); sdo.cal_inc <= (others => '0');
sdo.cal_en <= (others => '0'); sdo.sdck <= (others => '0');
sdo.ba <= (others => '0'); sdo.cb <= (others => '0');
sdo.vbdrive <= (others => '0'); sdo.qdrive <= '0'; sdo.bdrive <= '0';
sdo.oct <= '0';
sdo.ce <= '0'; sdo.moben <= '0'; sdo.cal_rst <= '0';
sdo.xsdcsn <= (others => '0'); sdo.vcbdrive <= (others => '0');
sdo.cbdqm <= (others => '0'); sdo.cbcal_en <= (others => '0');
sdo.cbcal_inc <= (others => '0'); sdo.read_pend <= (others => '0');
sdo.regwdata <= (others => '0'); sdo.regwrite <= (others => '0');
sro.mben <= r.mben;
sro.sdram_en <= '0';
sro.rs_edac_en <= '0';
sro.ce <= '0';
sro.sddata <= (others => '0');
sro.svbdrive <= (others => '0');
sro.sa <= (others => '0');
sro.cb <= (others => '0');
sro.scb <= (others => '0');
sro.vcdrive <= (others => '0');
sro.svcdrive <= (others => '0');
sro.scb <= (others => '0');
regs : process(clk,rst)
begin
if rising_edge(clk) then r <= ri; rbdrive <= ribdrive; end if;
if rst = '0' then
r.ramsn <= '1';
r.romsn <= '1'; r.oen <= '1';
r.bdrive <= '1'; r.nbdrive <= '0';
r.vramsn <= (others => '1'); r.vromsn <= (others => '1');
if oepol = 0 then rbdrive <= (others => '1');
else rbdrive <= (others => '0'); end if;
end if;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("srctrl" & tost(hindex) &
": 32-bit PROM/SRAM controller rev " & tost(VERSION));
-- pragma translate_on
end;
| gpl-2.0 | 8b19dfb25c54467d31dc937f3b927775 | 0.558431 | 3.069143 | false | false | false | false |
VerkhovtsovPavel/BSUIR_Labs | Labs/POCP/POCP-6/src/TB/FIFO_T.vhd | 1 | 1,439 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity FIFO_T is
end FIFO_T;
architecture Beh of FIFO_T is
component FIFO is
generic(
-- øèíà àäðåñà
m: integer := 2;
-- øèíà äàííûõ
n: integer := 2
);
port (
-- ñèíõðîíèçàöèÿ
CLK: in std_logic;
-- ñèãíàë óïðàâëåíèÿ ÷òåíèåì/çàïèñüþ
WR: in std_logic;
-- äâóíàïðàâëåííàÿ øèíà äàííûõ
DB: inout std_logic_vector (n-1 downto 0);
EMPTY: out std_logic;
FULL: out std_logic
);
end component;
signal CLK: std_logic := '0';
signal WR: std_logic := '0';
signal DB: std_logic_vector(1 downto 0) := "00";
signal empty: std_logic;
signal full: std_logic;
constant CLK_Period: time := 10 ns;
begin
UFIFO: FIFO port map(
CLK => CLK,
WR => WR,
DB => DB,
empty => empty,
full => full
);
CLK_Process: process
begin
CLK <= '0';
wait for CLK_Period/2;
CLK <= '1';
wait for CLK_Period/2;
end process;
main: process
begin
wait for clk_period;
WR <= '0';
DB <= "11";
wait for clk_period;
DB <= "10";
wait for clk_period;
DB <= "01";
wait for clk_period;
WR <= '1';
DB <= "ZZ";
wait for clk_period;
DB <= "ZZ";
wait for clk_period;
DB <= "ZZ";
wait for clk_period;
DB <= "ZZ";
wait;
end process;
end Beh;
configuration config_L of FIFO_T is
for Beh
for UFIFO : FIFO
use entity work.fifo(Beh);
end for;
end for;
end config_L; | mit | 6d4f932cb9bf50e7ac69e1daddfeaa10 | 0.613621 | 2.551418 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | VHDL_UART/VHDL_UART.vhd | 1 | 1,061 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--library UART_LIB;
--use UART_LIB.all;
entity UART is
port(
CLOCK_50: in std_logic;
SW: in std_logic_vector(9 downto 0);
KEY: in std_logic_vector(3 downto 0);
LEDR: out std_logic_vector(9 downto 0);
LEDG: out std_logic_vector(7 downto 0);
UART_TXD: out std_logic;
UART_RXD: in std_logic
);
end UART;
architecture MAIN of UART is
signal TX_DATA: std_logic_vector(7 downto 0);
signal TX_START: std_logic:='0';
signal TX_BUSY: std_logic; -- Why not set 0?
-----------------------------------------
COMPONENT TX
PORT(
CLK: in std_logic;
START: in std_logic;
BUSY: out std_logic;
DATA: in std_logic_vector(7 downto 0);
TX_LINE: out std_logic
);
end component TX;
begin
C1: TX port map (CLOCK_50, TX_START, TX_BUSY, TX_DATA, UART_TXD);
PROCESS(CLOCK_50)
begin
if (CLOCK_50'event and CLOCK_50='1') then
if (KEY(0) = '0' and TX_BUSY='0') then
TX_DATA<=sw(7 downto 0);
TX_START<='1';
LEDR(7 downto 0)<=TX_DATA;
else
TX_START<='0';
end if;
end if;
end process;
end main; | mit | 1483f02dbd17aa5ec01678c2d667ac9b | 0.652215 | 2.619753 | false | false | false | false |
quicky2000/top_optim_sharp_driver | top_optim_sharp_driver.vhd | 1 | 2,797 | --
-- This file is part of top_optim_sharp_driver
-- Copyright (C) 2011 Julien Thevenon ( julien_thevenon at yahoo.fr )
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity top_optim_sharp_driver is
Port ( clk : in STD_LOGIC;
w1a : inout STD_LOGIC_VECTOR (15 downto 0);
w1b : inout STD_LOGIC_VECTOR (15 downto 0));
end top_optim_sharp_driver;
architecture Behavioral of top_optim_sharp_driver is
signal vsync : std_logic;
signal hsync : std_logic;
signal enable : std_logic;
-- Signals to communicate with block giving color
signal x_out : std_logic_vector ( 9 downto 0);
signal y_out : std_logic_vector ( 8 downto 0);
signal reset : std_logic;
begin
--Number of Slices : 71
--Number of Slice Flip Flops: 61
--Number of 4 input LUTs: 128
--Number of bonded IOBs: 23
--Clock : 92.524Mhz
--inst_optim_screen_driver : entity work.driver_sharp(v1_0)
--Number of Slices: 52
--Number of Slice Flip Flops: 48
--Number of 4 input LUTs: 97
--Number of bonded IOBs: 23
-- Clock : 181.455Mhz
--inst_optim_screen_driver : entity work.driver_sharp(v1_1)
--Number of Slices: 16
--Number of Slice Flip Flops: 27
--Number of 4 input LUTs: 29
--Number of bonded IOBs: 23
-- Clock 224.517 Mhz
--inst_optim_screen_driver : entity work.driver_sharp(v1_2)
--Number of Slices: 38
--Number of Slice Flip Flops: 69
--Number of 4 input LUTs: 49
--Number of bonded IOBs: 23
-- Clock : 221.141Mhz
inst_optim_screen_driver : entity work.driver_sharp(v1_3)
port map(
clk => clk,
rst => reset,
vsync => vsync,
hsync => hsync,
enable => enable,
x_out => x_out,
y_out => y_out);
w1a(0) <= vsync;
w1a(1) <= hsync;
w1a(2) <= enable;
w1a(12 downto 3) <= x_out(9 downto 0);
w1b(8 downto 0) <= y_out(8 downto 0);
reset <= '0';
end Behavioral;
| gpl-3.0 | daba001d63bc5d43d687539e82e86ee6 | 0.683947 | 3.386199 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op968_17.vhdl | 1 | 6,411 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal gnd: electrical;
terminal vbias3: electrical;
terminal vbias2: electrical;
terminal vbias4: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
terminal net11: electrical;
terminal net12: electrical;
terminal net13: electrical;
begin
subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias1,
S => vdd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net1,
G => vbias3,
S => net7
);
subnet0_subnet1_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net7,
G => net1,
S => gnd
);
subnet0_subnet1_m3 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net8,
G => net1,
S => gnd
);
subnet0_subnet1_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => vbias3,
S => net8
);
subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net2,
G => vbias3,
S => net9
);
subnet0_subnet2_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net9,
G => net2,
S => gnd
);
subnet0_subnet2_m3 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net10,
G => net2,
S => gnd
);
subnet0_subnet2_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net4,
G => vbias3,
S => net10
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net5,
G => vbias3,
S => net3
);
subnet0_subnet4_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => out1,
G => vbias3,
S => net4
);
subnet0_subnet5_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net5,
G => vbias2,
S => net11
);
subnet0_subnet5_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net11,
G => net5,
S => vdd
);
subnet0_subnet5_m3 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net12,
G => net5,
S => vdd
);
subnet0_subnet5_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => out1,
G => vbias2,
S => net12
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net13
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net13,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 80c673da7567431f84103ccbb6fb9a34 | 0.577445 | 3.110626 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op948_2.vhdl | 1 | 4,202 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal gnd: electrical;
terminal vbias3: electrical;
terminal vbias4: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
begin
subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in1,
S => net4
);
subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in2,
S => net4
);
subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net4,
G => vbias1,
S => vdd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => vbias2,
S => net1
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => out1,
G => vbias2,
S => net2
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net3,
G => net3,
S => gnd
);
subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmcout_1,
scope => private
)
port map(
D => out1,
G => net3,
S => gnd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net5
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net5,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 9fd6f7f969a3b657579814d344a7e40d | 0.587577 | 3.259891 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/copper/vhdl_source/copper_regs.vhd | 5 | 2,952 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.copper_pkg.all;
entity copper_regs is
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
control : out t_copper_control;
status : in t_copper_status );
end copper_regs;
architecture registers of copper_regs is
signal control_i : t_copper_control;
begin
control <= control_i;
p_bus: process(clock)
begin
if rising_edge(clock) then
io_resp <= c_io_resp_init;
control_i.command <= X"0";
control_i.stop <= '0';
if io_req.write='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_copper_command =>
control_i.command <= io_req.data(3 downto 0);
when c_copper_framelen_l =>
control_i.frame_length(7 downto 0) <= unsigned(io_req.data);
when c_copper_framelen_h =>
control_i.frame_length(15 downto 8) <= unsigned(io_req.data);
when c_copper_break =>
control_i.stop <= '1';
when others =>
null;
end case;
elsif io_req.read='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_copper_status =>
io_resp.data(0) <= status.running;
when c_copper_measure_l =>
io_resp.data <= std_logic_vector(status.measured_time(7 downto 0));
when c_copper_measure_h =>
io_resp.data <= std_logic_vector(status.measured_time(15 downto 8));
when c_copper_framelen_l =>
io_resp.data <= std_logic_vector(control_i.frame_length(7 downto 0));
when c_copper_framelen_h =>
io_resp.data <= std_logic_vector(control_i.frame_length(15 downto 8));
when others =>
null;
end case;
end if;
if reset='1' then
control_i <= c_copper_control_init;
end if;
end if;
end process;
end architecture;
| gpl-3.0 | 0d9018c086e3b2f6e91f1ee69bb668d4 | 0.461043 | 4.077348 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/6502/vhdl_sim/tb_proc_core.vhd | 4 | 3,110 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library work;
use work.pkg_6502_defs.all;
use work.flat_memory_model.all;
entity tb_proc_core is
generic (
test_file : string := "testcode";
test_base : integer := 16#FF00# );
end tb_proc_core;
architecture tb of tb_proc_core is
signal clock : std_logic := '0';
signal clock_en : std_logic;
signal reset : std_logic;
signal addr_out : std_logic_vector(16 downto 0);
signal data_in : std_logic_vector(7 downto 0) := X"AA";
signal data_out : std_logic_vector(7 downto 0);
signal read_write_n : std_logic;
signal nmi_n : std_logic := '1';
signal irq_n : std_logic := '1';
signal stop_clock : boolean := false;
shared variable ram : h_mem_object;
begin
clock <= not clock after 50 ns when not stop_clock;
clock_en <= '1';
reset <= '1', '0' after 300 ns;
core: entity work.proc_core
generic map (
support_bcd => true )
port map (
clock => clock,
clock_en => clock_en,
reset => reset,
irq_n => irq_n,
nmi_n => nmi_n,
addr_out => addr_out,
data_in => data_in,
data_out => data_out,
read_write_n => read_write_n );
process(clock)
variable addr : std_logic_vector(31 downto 0) := (others => '0');
begin
if falling_edge(clock) then
addr(15 downto 0) := addr_out(15 downto 0);
data_in <= read_memory_8(ram, addr);
if read_write_n = '0' then
write_memory_8(ram, addr, data_out);
if addr_out(15 downto 0) = X"FFF8" then
stop_clock <= true;
if data_out = X"55" then
report "Test program completed successfully." severity note;
else
report "Test program failed." severity error;
end if;
elsif addr_out(15 downto 0) = X"FFF9" then
case data_out is
when X"01" => report "Break IRQ service routine." severity note;
when X"02" => report "External IRQ service routine." severity note;
when X"03" => report "NMI service routine." severity note;
when others => report "Unknown event message." severity warning;
end case;
end if;
end if;
end if;
end process;
test: process
begin
register_mem_model("6502 ram", ram);
load_memory(test_file, ram, conv_std_logic_vector(test_base, 32));
wait for 30 us;
irq_n <= '0';
wait for 10 us;
irq_n <= '1';
wait for 10 us;
nmi_n <= '0';
wait for 10 us;
nmi_n <= '1';
wait;
end process;
end tb;
| gpl-3.0 | 9d29b40b657cc4749e109fd7c89bf81f | 0.49164 | 3.84901 | false | true | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/sigma_delta_dac/vhdl_source/high_pass.vhd | 5 | 1,274 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.my_math_pkg.all;
entity high_pass is
generic (
g_width : natural := 12 );
port (
clock : in std_logic;
enable : in std_logic := '1';
reset : in std_logic;
x : in signed(g_width-1 downto 0);
q : out signed(g_width downto 0) );
end high_pass;
architecture gideon of high_pass is
signal z : signed(g_width downto 0);
signal count : integer range 0 to 3;
begin
process(clock)
variable z_half : signed(g_width downto 0);
begin
if rising_edge(clock) then
z_half := (z(z'high) & z(z'high downto 1));
if enable='1' then
z <= sum_limit((x(x'high) & x), z_half); -- z=x+(z/2)
q <= sub_limit((x(x'high) & x), z_half); -- q=x-(z/2)
end if;
-- z <= extend(x, g_width+1);
-- q <= extend(x, g_width+1) - z;
if reset='1' then
z <= (others => '0');
q <= (others => '0');
count <= 0;
end if;
end if;
end process;
end gideon;
| gpl-3.0 | d3cf031e3d817f915f379d750aad78db | 0.449765 | 3.335079 | false | false | false | false |
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